Freescale Semiconductor DSP56374 User Manual

DSP56374

24-Bit Digital Signal Processor

User Guide

Document Number: DSP56374UG

Rev. 1.2

07/2007

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Table of Contents

Paragraph Page Number Number

Preface i

Chapter 1

DSP56374 Overview

1.1 Introduction ...............................................................................................................................................................1-1

1.2 DSP56300 Core Description .....................................................................................................................................1-2

1.3 DSP56374 Audio Processor Architecture .................................................................................................................1-3

1.4 DSP56300 Core Functional Blocks ...........................................................................................................................1-3

1.4.1 Data ALU ............................................................................................................................................................1-3

1.4.1.1 Data ALU Registers ......................................................................................................................................1-3

1.4.1.2 Multiplier-Accumulator (MAC) ...................................................................................................................1-3

1.4.2 Address Generation Unit (AGU) ........................................................................................................................1-4

1.4.3 Program Control Unit (PCU) ..............................................................................................................................1-4

1.4.4 Internal Buses ......................................................................................................................................................1-4

1.4.5 Direct Memory Access (DMA) ...........................................................................................................................1-5

1.4.6 PLL-based Clock Oscillator ................................................................................................................................1-5

1.4.7 On-Chip Memory ................................................................................................................................................1-5

1.4.8 Off-Chip Memory Expansion .............................................................................................................................1-5

1.4.9 Power Requirements ...........................................................................................................................................1-5

1.5 Peripheral Overview ..................................................................................................................................................1-6

1.5.1 General Purpose Input/Output (GPIO) ...............................................................................................................1-6

1.5.2 Triple Timer (TEC) .............................................................................................................................................1-6

1.5.3 Enhanced Serial Audio Interface (ESAI) ............................................................................................................1-7

1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1) .....................................................................................................1-7

1.5.5 Serial Host Interface (SHI) .................................................................................................................................1-7

1.5.6 Watchdog timer (WDT) ......................................................................................................................................1-7

Chapter 2

Signal/Connection Descriptions

2.1 Signal Groupings .......................................................................................................................................................2-1

2.2 Power .........................................................................................................................................................................2-1

2.3 Ground .......................................................................................................................................................................2-3

2.4 SCAN ........................................................................................................................................................................2-4

2.5 Clock and PLL ...........................................................................................................................................................2-4

2.6 Interrupt and Mode Control .......................................................................................................................................2-4

2.7 Serial Host Interface ..................................................................................................................................................2-6

2.8 Enhanced Serial Audio Interface ...............................................................................................................................2-8

2.9 Enhanced Serial Audio Interface_1 .........................................................................................................................2-12

2.10 Dedicated GPIO - Port G .........................................................................................................................................2-16

2.11 Timer .......................................................................................................................................................................2-18

2.12 JTAG/OnCE Interface .............................................................................................................................................2-19

Chapter 3

Memory Configuration

3.1 Data and Program Memory Maps .............................................................................................................................3-1

3.1.1 Reserved Memory Spaces ...................................................................................................................................3-5

3.1.2 Bootstrap CODE .................................................................................................................................................3-5

3.1.3 Dynamic Memory Configuration Switching ......................................................................................................3-5

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3.1.4 External Memory Support ...................................................................................................................................3-5

3.1.5 DMA and Memory ..............................................................................................................................................3-5

3.1.6 Memory BLOCKS ..............................................................................................................................................3-6

3.2 Memory Patch Module ..............................................................................................................................................3-6

3.3 Internal I/O Memory Map .........................................................................................................................................3-7

Chapter 4

Core Configuration

4.1 Introduction ...............................................................................................................................................................4-1

4.2 Operating Mode Register (OMR) ..............................................................................................................................4-1

4.2.1 RESERVED - Bits 4, 5, 10 - 15 and 23 ..............................................................................................................4-1

4.3 Operating Modes .......................................................................................................................................................4-1

4.4 Interrupt Priority Registers ........................................................................................................................................4-3

4.5 DMA Request Sources ..............................................................................................................................................4-9

4.6 PLL Initialization ....................................................................................................................................................4-10

4.6.1 PLL Pre-Divider Factor (PD0-PD4) .................................................................................................................4-10

4.6.2 PLL Multiplication Factor (MF0-MF7) ............................................................................................................4-10

4.6.3 PLL Feedback Multiplier (OD1) ......................................................................................................................4-10

4.6.4 PLL Output Divide Factor (OD0-OD1) ............................................................................................................4-10

4.6.5 PLL Divider Factor (DF0-DF2) ........................................................................................................................4-10

4.6.6 PLL LOCK MUX (PLKM) ..............................................................................................................................4-10

4.7 Device Identification (ID) Register .........................................................................................................................4-10

4.8 JTAG Identification (ID) Register ..........................................................................................................................4-11

Chapter 5

PLL and Clock generator

5.1 Introduction ...............................................................................................................................................................5-1

5.2 PLL and Clock Signals ..............................................................................................................................................5-1

5.3 PLL Block .................................................................................................................................................................5-1

5.3.1 Frequency Predivider ..........................................................................................................................................5-2

5.3.2 Phase Detector and Charge Pump Loop Filter ....................................................................................................5-2

5.3.3 Voltage Controlled Oscillator (VCO) .................................................................................................................5-2

5.3.4 PLL DividerS ......................................................................................................................................................5-2

5.3.5 PLL Multiplication Factor (MF) .........................................................................................................................5-3

5.4 PLL Operation ...........................................................................................................................................................5-3

5.4.1 EXTAL Clock Input Division .............................................................................................................................5-3

5.4.2 PLL Frequency Multiplication ............................................................................................................................5-3

5.4.3 PLL Output Frequency (PLL Out) ......................................................................................................................5-4

5.5 Clock Generator ........................................................................................................................................................5-6

5.5.1 Low-Power Divider (LPD) .................................................................................................................................5-6

5.6 Operating Frequency (Fosc) ......................................................................................................................................5-6

5.7 PLL Programming Model .........................................................................................................................................5-7

5.8 PLL Initialization Procedure ...................................................................................................................................5-10

5.9 PLL Programming Examples ..................................................................................................................................5-11

Chapter 6

General Purpose Input/Output

6.1 Introduction ..............................................................................................................................................................6-1

6.2 Programming Model ..................................................................................................................................................6-1

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6.2.1 Port C and E Signals and Registers .....................................................................................................................6-1

6.2.2 Port G Signals and Registers ...............................................................................................................................6-1

6.2.2.1 Port G Control Register (PCRG) ..................................................................................................................6-1

6.2.2.2 Port G Direction Register (PRRG) ...............................................................................................................6-1

6.2.2.3 Port G Data register (PDRG) ........................................................................................................................6-2

6.2.2.4 ESAI/EXTAL clocking control ....................................................................................................................6-2

6.2.3 Port H Signals and Registers ...............................................................................................................................6-3

6.2.3.1 Port H Control Register (PCRH) ..................................................................................................................6-3

6.2.3.2 Port H Direction Register (PRRH) ...............................................................................................................6-3

6.2.3.3 Port H Data register (PDRH) ........................................................................................................................6-4

6.2.4 Timer/Event Counter Signals ..............................................................................................................................6-4

Chapter 7

Serial Host Interface

7.1 Introduction ...............................................................................................................................................................7-1

7.2 Serial Host Interface Internal Architecture ...............................................................................................................7-1

7.3 SHI Clock Generator .................................................................................................................................................7-2

7.4 Serial Host Interface Programming Model ...............................................................................................................7-2

7.4.1 SHI Input/Output Shift Register (IOSR)—Host Side .........................................................................................7-4

7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side ........................................................................................7-4

7.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side ..............................................................................................7-5

7.4.4 SHI Slave Address Register (HSAR)—DSP Side ..............................................................................................7-5

7.4.4.1 HSAR Reserved Bits—Bits 19, 17– 0 ..........................................................................................................7-5

7.4.4.2 HSAR I

7.4.5 SHI Clock Control Register (HCKR)—DSP Side ..............................................................................................7-5

7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0 ............................................................................7-5

7.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 .................................................................................................7-6

7.4.5.3 HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3 ............................................................................7-7

7.4.5.4 HCKR Filter Mode (HFM[1:0]) — Bits 13–12 ............................................................................................7-7

7.4.5.5 HCKR Reserved Bits—Bits 23–14, 11 ........................................................................................................7-7

7.4.6 SHI Control/Status Register (HCSR)—DSP Side ..............................................................................................7-7

7.4.6.1 HCSR Host Enable (HEN)—Bit 0 ...............................................................................................................7-7

7.4.6.1.1 SHI Individual Reset ..............................................................................................................................7-8

7.4.6.2 HCSR I

7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 ............................................................................7-8

7.4.6.4 HCSR I

7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 .............................................................................................7-8

7.4.6.6 HCSR Master Mode (HMST)—Bit 6 ...........................................................................................................7-8

7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7 .................................................................................7-9

7.4.6.8 HCSR Idle (HIDLE)—Bit 9 .........................................................................................................................7-9

7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10 .....................................................................................7-9

7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 ......................................................................................7-9

7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12 .......................................................................7-10

7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14 ............................................................................7-10

7.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15 .................................................................................7-10

7.4.6.14 HCSR Reserved Bits—Bits 23, 18 and 16 .................................................................................................7-10

7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17 ......................................................................................7-10

7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 ..................................................................................................7-10

7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20 ...........................................................................................7-11

C Slave Address (HA[6:3], HA1)—Bits 23–20,18 .......................................................................7-5

C/SPI Selection (HI2C)—Bit 1 ......................................................................................................7-8

C Clock Freeze (HCKFR)—Bit 4 ..................................................................................................7-8

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7.4.6.18 Host Bus Error (HBER)—Bit 21 ................................................................................................................7-11

7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22 .........................................................................................................7-11

7.5 Characteristics Of The SPI Bus ...............................................................................................................................7-11

7.6 Characteristics Of The I

7.6.1 Overview ...........................................................................................................................................................7-11

7.6.2 I2C Data Transfer Formats ................................................................................................................................7-13

7.7 SHI Programming Considerations ...........................................................................................................................7-13

7.7.1 SPI Slave Mode .................................................................................................................................................7-13

7.7.2 SPI Master Mode ..............................................................................................................................................7-14

7.7.3 I

7.7.3.1 Receive Data in I2C Slave Mode ................................................................................................................7-15

7.7.3.2 Transmit Data In I2C Slave Mode ..............................................................................................................7-15

7.7.4 I

7.7.4.1 Receive Data in I2C Master Mode ..............................................................................................................7-16

7.7.4.2 Transmit Data In I2C Master Mode ............................................................................................................7-16

7.7.5 SHI Operation During DSP Stop ......................................................................................................................7-17

7.7.6 GPIO- HREQ Signal and Registers ..................................................................................................................7-17

C Slave Mode .................................................................................................................................................7-14

C Master Mode ...............................................................................................................................................7-15

C Bus ...............................................................................................................................7-11

Chapter 8

Enhanced Serial Audio Interface (ESAI)

8.1 Introduction ...............................................................................................................................................................8-1

8.2 ESAI Data and Control Pins ......................................................................................................................................8-2

8.2.1 Serial Transmit 0 Data Pin (SDO0) ....................................................................................................................8-3

8.2.2 Serial Transmit 1 Data Pin (SDO1) ....................................................................................................................8-3

8.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) ..........................................................................................8-3

8.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) ..........................................................................................8-3

8.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) ..........................................................................................8-3

8.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) ..........................................................................................8-3

8.2.7 Receiver Serial Clock (SCKR) ...........................................................................................................................8-4

8.2.8 Transmitter Serial Clock (SCKT) .......................................................................................................................8-4

8.2.9 Frame Sync for Receiver (FSR) ..........................................................................................................................8-5

8.2.10 Frame Sync for Transmitter (FST) .....................................................................................................................8-6

8.2.11 High Frequency Clock for Transmitter (HCKT) ................................................................................................8-6

8.2.12 High Frequency Clock for Receiver (HCKR) .....................................................................................................8-6

8.3 ESAI Programming Model ........................................................................................................................................8-6

8.3.1 ESAI Transmitter Clock Control Register (TCCR) ............................................................................................8-6

8.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 7–0 .........................................................8-7

8.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8 .........................................................................................8-8

8.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 13–9 ............................................................8-8

8.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 17–14 ........................................................8-8

8.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 .........................................................................................8-9

8.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 ................................................................................8-9

8.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 ...........................................................8-9

8.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 ..........................................................................8-9

8.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22 ..................................................................8-9

8.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 ........................................................8-9

8.3.2 ESAI Transmit Control Register (TCR) .............................................................................................................8-9

8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0 ..............................................................................................8-10

8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1 ..............................................................................................8-10

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8.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2 ..............................................................................................8-10

8.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 ..............................................................................................8-11

8.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 ..............................................................................................8-11

8.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5 ..............................................................................................8-11

8.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6 .........................................................................................8-11

8.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7 ............................................................................8-11

8.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 9-8 ......................................................8-12

8.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 14-10 .....................................................8-13

8.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15 ..................................................................................8-14

8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 ...................................................................8-15

8.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17 ..............................................................................8-16

8.3.2.14 TCR Reserved Bit - Bits 18 ........................................................................................................................8-16

8.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19 ...............................................................................8-16

8.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 .......................................................................8-16

8.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 ............................................................8-16

8.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22 ...........................................................................................8-16

8.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 .........................................................................8-16

8.3.3 ESAI Receive Clock Control Register (RCCR) ...............................................................................................8-16

8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0 .......................................................8-17

8.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8 .......................................................................................8-17

8.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 13–9 .........................................................8-17

8.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 17-14 ......................................................8-17

8.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18 .......................................................................................8-18

8.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19 ..............................................................................8-18

8.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 .........................................................8-18

8.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 ........................................................................8-18

8.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 ................................................................8-19

8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 ......................................................8-19

8.3.4 ESAI Receive Control Register (RCR) .............................................................................................................8-19

8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 ..............................................................................................8-20

8.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 ..............................................................................................8-20

8.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2.............................................................................................. 8-20

8.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 ..............................................................................................8-20

8.3.4.5 RCR Reserved Bits - Bits 5-4, 18-17 .........................................................................................................8-20

8.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6 ........................................................................................8-20

8.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7 ...........................................................................8-21

8.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 9-8 .....................................................8-21

8.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 14-10 .......................................................8-21

8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 ..................................................................................8-22

8.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16 ...................................................................8-22

8.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19 ...............................................................................8-22

8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 ........................................................................8-23

8.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 .............................................................8-23

8.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22 ............................................................................................8-23

8.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 ..........................................................................8-23

8.3.5 ESAI Common Control Register (SAICR) .......................................................................................................8-23

8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 .................................................................................................8-23

8.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 .................................................................................................8-24

8.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 .................................................................................................8-24

8.3.5.4 SAICR Reserved Bits - Bits 5-3, 23-9 ........................................................................................................8-24

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8.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6 .................................................................................8-24

8.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7 ..........................................................................8-24

8.3.5.7 SAICR Alignment Control (ALC) - Bit 8 ..................................................................................................8-24

8.3.6 ESAI Status Register (SAISR) ..........................................................................................................................8-25

8.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 ......................................................................................................8-26

8.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1 ......................................................................................................8-26

8.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2 ......................................................................................................8-26

8.3.6.4 SAISR Reserved Bits - Bits 5-3, 12-11, 23-18 ...........................................................................................8-26

8.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 .........................................................................................8-26

8.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7 ...................................................................................8-26

8.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8 ......................................................................................8-27

8.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9 ..........................................................................8-27

8.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10 .........................................................................8-27

8.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13 .....................................................................................8-27

8.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14 ...............................................................................8-27

8.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15 ..............................................................................8-27

8.3.6.14 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16 ..................................................................8-27

8.3.6.13 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17 ................................................................... 8-28

8.3.7 ESAI Receive Shift Registers ...........................................................................................................................8-29

8.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0) ....................................................................................8-30

8.3.9 ESAI Transmit Shift Registers ..........................................................................................................................8-30

8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) ..................................................................8-30

8.3.11 ESAI Time Slot Register (TSR) .......................................................................................................................8-30

8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) ...............................................................................................8-30

8.3.13 Receive Slot Mask Registers (RSMA, RSMB) ................................................................................................8-31

8.4 Operating Modes .....................................................................................................................................................8-32

8.4.1 ESAI After Reset ..............................................................................................................................................8-32

8.4.2 ESAI Initialization ............................................................................................................................................8-32

8.4.3 ESAI Interrupt Requests ...................................................................................................................................8-33

8.4.4 Operating Modes – Normal, Network and On-Demand ...................................................................................8-33

8.4.4.1 Normal/Network/On-Demand Mode Selection ..........................................................................................8-33

8.4.4.2 Synchronous/Asynchronous Operating Modes ..........................................................................................8-34

8.4.4.3 Frame Sync Selection 3 ...............................................................................................................................8-34

8.4.4.4 Shift Direction Selection ............................................................................................................................8-34

8.4.5 Serial I/O Flags .................................................................................................................................................8-34

8.5 GPIO - Pins and Registers .......................................................................................................................................8-35

8.5.1 Port C (ESAI) GPIO - Pins and Registers ........................................................................................................8-35

8.5.1.1 Port C Control Register (PCRC) ................................................................................................................8-35

8.5.1.2 Port C Direction Register (PRRC) ..............................................................................................................8-35

8.5.1.3 Port C Data register (PDRC) ...................................................................................................................... 8-36

8.5.2 Port E (ESAI_1) GPIO - Pins and Registers .....................................................................................................8-36

8.5.2.1 Port E Control Register (PCRE) .................................................................................................................8-37

8.5.2.2 Port E Direction Register (PRRE) ..............................................................................................................8-37

8.5.2.3 Port E Data register (PDRE) .......................................................................................................................8-37

8.6 ESAI Initialization Examples ..................................................................................................................................8-38

8.6.1 Initializing the ESAI Using Individual Reset ...................................................................................................8-38

8.6.2 Initializing Just the ESAI Transmitter Section .................................................................................................8-38

8.6.3 Initializing Just the ESAI Receiver Section ......................................................................................................8-38

DSP56374 Users Guide, Rev. 1.2

TOC-6 Freescale Semiconductor

Table of Contents

Paragraph Page Number Number

Chapter 9

Triple Timer Module

9.1 Overview ...................................................................................................................................................................9-1

9.1.1 Triple Timer Module Block Diagram .................................................................................................................9-1

9.1.2 Individual Timer Block Diagram ........................................................................................................................9-1

9.2 Operation ...................................................................................................................................................................9-2

9.2.1 Timer After Reset ...............................................................................................................................................9-2

9.2.2 Timer Initialization .............................................................................................................................................9-2

9.2.3 Timer Exceptions ................................................................................................................................................9-3

9.3 Operating Modes .......................................................................................................................................................9-3

9.3.1 Triple Timer Modes ............................................................................................................................................9-3

9.3.1.1 Timer GPIO (Mode 0) ..................................................................................................................................9-4

9.3.1.2 Timer Pulse (Mode 1) ...................................................................................................................................9-5

9.3.1.3 Timer Toggle (Mode 2) ................................................................................................................................9-7

9.3.1.4 Timer Event Counter (Mode 3) ....................................................................................................................9-9

9.3.2 Signal Measurement Modes ..............................................................................................................................9-10

9.3.2.1 Measurement Input Width (Mode 4) ..........................................................................................................9-10

9.3.2.2 Measurement Input Period (Mode 5) ..........................................................................................................9-12

9.3.2.3 Measurement Capture (Mode 6) .................................................................................................................9-13

9.3.3 Pulse Width Modulation (PWM, Mode 7) ........................................................................................................9-14

9.3.4 Watchdog Modes ..............................................................................................................................................9-16

9.3.4.1 Watchdog Pulse (Mode 9) ..........................................................................................................................9-16

9.3.4.2 Watchdog Toggle (Mode 10) .....................................................................................................................9-17

9.3.4.3 Reserved Modes .........................................................................................................................................9-18

9.3.5 Special Cases ....................................................................................................................................................9-18

9.3.6 DMA Trigger ....................................................................................................................................................9-18

9.4 Triple Timer Module Programming Model .............................................................................................................9-18

9.4.1 Prescaler Counter ..............................................................................................................................................9-18

9.4.2 Timer Prescaler Load Register (TPLR) ............................................................................................................9-19

9.4.3 Timer Prescaler Count Register (TPCR) ..........................................................................................................9-20

9.4.4 Timer Control/Status Register (TCSR) .............................................................................................................9-21

9.4.5 Timer Load Register (TLR) ..............................................................................................................................9-25

9.4.6 Timer Compare Register (TCPR) .....................................................................................................................9-25

9.4.7 Timer Count Register (TCR) ............................................................................................................................9-25

Chapter 10

Watchdog Timer Module

10.1 Introduction ............................................................................................................................................................10-1

10.2 WDT Pin ..................................................................................................................................................................10-1

10.3 WDT Operation ......................................................................................................................................................10-1

10.4 Description of Registers ..........................................................................................................................................10-2

10.4.1 Watchdog Control Register (WCR) .................................................................................................................10-2

10.4.2 Watchdog Counter & WCNTR Register ..........................................................................................................10-2

10.4.3 Watchdog Modulus Register (WMR) ..............................................................................................................10-3

10.4.4 Watchdog Service Register (WSR) ..................................................................................................................10-3

10.5 Operation in Different Modes ................................................................................................................................10-3

10.5.1 WAIT Mode .....................................................................................................................................................10-3

10.5.2 DEBUG Mode .................................................................................................................................................10-3

10.5.3 STOP MODE ....................................................................................................................................................10-3

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor TOC-7

Table Of Contents

Paragraph Page Number Number

Appendix A

Bootstrap Source Code

A.1 DSP56374 Bootstrap Program .................................................................................................................................A-1

A.2 Using The Serial EEPROM Boot Mode ...................................................................................................................A-5

Appendix B

Equates

Appendix C

Programmer’s Reference

C.1 Introduction ..............................................................................................................................................................C-1

C.1.1 Peripheral Addresses ..........................................................................................................................................C-1

C.1.2 Interrupt Addresses ............................................................................................................................................C-1

C.1.3 Interrupt Priorities ..............................................................................................................................................C-1

C.1.4 Programming Sheets ..........................................................................................................................................C-1

C.1.5 Internal I/O Memory Map ..................................................................................................................................C-1

C.1.6 Interrupt Vector Addresses ................................................................................................................................C-7

C.2 Interrupt Source Priorities (within an IPL) .............................................................................................................C-10

C.3 Programming Sheets ...............................................................................................................................................C-11

Appendix D

BSDL

D.1 52-pin BSDL ............................................................................................................................................................D-1

D.2 80-pin BSDL ............................................................................................................................................................D-6

DSP56374 Users Guide, Rev. 1.2

TOC-8 Freescale Semiconductor

List of Figures

Figure Page Number Number

1-1 DSP56374 Block Diagram ........................................................................................................................................1-1

2-1 80-pin Vdd Connections ............................................................................................................................................2-2

2-2 52-pin Vdd Connections ............................................................................................................................................2-3

3-1 Default Memory Map (MS 0) ...................................................................................................................................3-2

3-2 Memory Map (MS 1, MSW(1-0) 11) ........................................................................................................................3-2

3-3 Memory Map (MS 1, MSW(1-0) 10) ........................................................................................................................3-3

3-4 Memory Map (MS 1, MSW(1-0) 01) ........................................................................................................................3-4

3-5 Memory Map (MS 1, MSW(1-0) 00) ........................................................................................................................3-4

4-1 Interrupt Priority Register P ......................................................................................................................................4-4

4-2 Interrupt Priority Register C ......................................................................................................................................4-4

4-3 PCTL Register .........................................................................................................................................................4-10

5-1 PLL Clock Generator Block Diagram .......................................................................................................................5-1

5-2 PLL Block Diagram ..................................................................................................................................................5-2

5-3 PLL Loop with One Divider when OD1=0 (FM = 2) ...............................................................................................5-4

5-4 PLL Loop with Two Dividers when OD1=1 (FM = 4) .............................................................................................5-4

5-5 PLL Out = VCO Out/2 [OD1 = 0, OD0 = 1] ............................................................................................................5-5

5-6 PLL Out = VCO Out/2 [OD1 = 1, OD0 = 0] ............................................................................................................5-5

5-7 PLL Out = VCO Out/4 [OD1 = 1, OD0 = 1] ............................................................................................................5-6

5-8 CLKGEN Block Diagram .........................................................................................................................................5-6

5-9 PLL Control (PCTL) Register ...................................................................................................................................5-7

6-1 PCRG Register ..........................................................................................................................................................6-2

6-2 PRRG Register ..........................................................................................................................................................6-2

6-3 PDRG Register ..........................................................................................................................................................6-2

6-4 PCRH Register ..........................................................................................................................................................6-4

6-5 PRRH Register ..........................................................................................................................................................6-4

6-6 PDRH Register ..........................................................................................................................................................6-4

7-1 Serial Host Interface Block Diagram ........................................................................................................................7-2

7-2 SHI Clock Generator .................................................................................................................................................7-2

7-3 SHI Programming Model—Host Side ......................................................................................................................7-3

7-4 SHI Programming Model—DSP Side .......................................................................................................................7-3

7-5 SHI I/O Shift Register (IOSR) ..................................................................................................................................7-4

7-6 SPI Data-To-Clock Timing Diagram ........................................................................................................................7-6

7-7 I

7-8 I

7-9 Acknowledgment on the I2C Bus ............................................................................................................................7-12

7-10 I

7-11 I2C Bus Protocol For Host Read Cycle ...................................................................................................................7-13

8-1 ESAI Block Diagram .................................................................................................................................................8-2

8-2 TCCR Register ..........................................................................................................................................................8-6

8-3 ESAI Clock Generator Functional Block Diagram ...................................................................................................8-7

8-4 ESAI Frame Sync Generator Functional Block Diagram .........................................................................................8-8

8-5 TCR Register ...........................................................................................................................................................8-10

8-6 Normal and Network Operation ..............................................................................................................................8-13

8-7 Frame Length Selection ...........................................................................................................................................8-15

8-8 RCCR Register ........................................................................................................................................................8-17

8-9 RCR Register ...........................................................................................................................................................8-20

8-10 SAICR Register .......................................................................................................................................................8-23

8-11 SAICR SYN Bit Operation .....................................................................................................................................8-25

C Bit Transfer .......................................................................................................................................................7-12

C Start and Stop Events ........................................................................................................................................7-12

C Bus Protocol For Host Write Cycle ..................................................................................................................7-13

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor LOF-1

List of Figures

Figure Page Number Number

8-12 SAISR Register .......................................................................................................................................................8-26

8-13 ESAI Data Path Programming Model ([R/T]SHFD=0) ..........................................................................................8-28

8-14 ESAI Data Path Programming Model ([R/T]SHFD=1) ..........................................................................................8-29

8-15 TSMA Register ........................................................................................................................................................8-30

8-16 RSMA Register .......................................................................................................................................................8-31

8-17 TSMB Register ........................................................................................................................................................8-31

8-18 RSMB Register ........................................................................................................................................................8-32

8-19 PCRC Register ........................................................................................................................................................8-36

8-20 PRRC Register ........................................................................................................................................................8-36

8-21 PDRC Register ........................................................................................................................................................8-36

8-22 PCRE Register .........................................................................................................................................................8-37

8-23 PRRE Register .........................................................................................................................................................8-37

8-24 PDRE Register ........................................................................................................................................................8-38

9-1 Triple Timer Module Block Diagram .......................................................................................................................9-1

9-2 Timer Module Block Diagram ..................................................................................................................................9-2

9-3 Timer Mode (TRM = 1) ............................................................................................................................................9-4

9-4 Timer Mode (TRM = 0) ............................................................................................................................................9-5

9-5 Pulse Mode (TRM = 1) .............................................................................................................................................9-6

9-6 Pulse Mode (TRM = 0) .............................................................................................................................................9-7

9-7 Toggle Mode, TRM = 1 ............................................................................................................................................9-8

9-8 Toggle Mode, TRM = 0 ............................................................................................................................................9-8

9-9 Event Counter Mode, TRM = 1 .................................................................................................................................9-9

9-10 Event Counter Mode, TRM = 0 ...............................................................................................................................9-10

9-11 Pulse Width Measurement Mode, TRM = 1 ...........................................................................................................9-11

9-12 Pulse Width Measurement Mode, TRM = 0 ...........................................................................................................9-11

9-13 Period Measurement Mode, TRM = 1 .....................................................................................................................9-12

9-14 Period Measurement Mode, TRM = 0 .....................................................................................................................9-13

9-15 Capture Measurement Mode, TRM = 0 ..................................................................................................................9-14

9-16 Pulse Width Modulation Toggle Mode, TRM = 1 ..................................................................................................9-15

9-17 Pulse Width Modulation Toggle Mode, TRM = 0 ..................................................................................................9-16

9-18 Watchdog Pulse Mode .............................................................................................................................................9-17

9-19 Watchdog Toggle Mode ..........................................................................................................................................9-18

9-20 Timer Module Programmer’s Model ......................................................................................................................9-19

9-21 Timer Prescaler Count Register (TPCR) .................................................................................................................9-20

10-1 Watchdog Timer Block Diagram .............................................................................................................................10-2

C-1 Status Register (SR) ...............................................................................................................................................C-12

C-2 Operating Mode Register (OMR) ...........................................................................................................................C-13

C-3 Interrupt Priority Register–Core (IPR–C) ..............................................................................................................C-14

C-4 Interrupt Priority Register – Peripherals (IPR–P) ..................................................................................................C-15

C-5 Phase Lock Loop Control Register (PCTL) ...........................................................................................................C-16

C-6 SHI Slave Address and Clock Control Registers ...................................................................................................C-17

C-7 SHI Host Control/Status Register ...........................................................................................................................C-18

C-8 ESAI Transmit Clock Control Register ..................................................................................................................C-19

C-9 ESAI Transmit Control Register ............................................................................................................................C-20

C-10 ESAI Receive Clock Control Register ...................................................................................................................C-21

C-11 ESAI Receive Control Register ..............................................................................................................................C-22

C-12 ESAI Common Control Register ............................................................................................................................C-23

C-13 ESAI Status Register ..............................................................................................................................................C-24

C-14 ESAI_1 Transmit Clock Control Register ..............................................................................................................C-25

C-15 ESAI_1 Transmit Control Register ........................................................................................................................C-26

DSP56374 Users Guide, Rev. 1.2

LOF-2 Freescale Semiconductor

List of Figures

Figure Page Number Number

C-16 ESAI_1 Receive Clock Control Register ...............................................................................................................C-27

C-17 ESAI_1 Receive Control Register ..........................................................................................................................C-28

C-18 ESAI_1 Common Control Register ........................................................................................................................C-29

C-19 ESAI_1 Status Register ..........................................................................................................................................C-30

C-20 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) ...................................................................C-31

C-21 Timer Control/Status Register ................................................................................................................................C-32

C-22 Timer Load, Compare and Count Registers ...........................................................................................................C-33

C-23 GPIO Port C ...........................................................................................................................................................C-35

C-24 GPIO Port E ............................................................................................................................................................C-36

C-25 GPIO Port G ...........................................................................................................................................................C-37

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor LOF-3

List of Figures

Notes

DSP56374 Users Guide, Rev. 1.2

LOF-4 Freescale Semiconductor

List of Tables

Tab le Page Number Number

1-1 DSP56374 Memory Switch Configurations ..............................................................................................................1-2

2-1 DSP56374 Functional Signal Groupings ..................................................................................................................2-1

2-2 Power Inputs ..............................................................................................................................................................2-1

2-3 Grounds .....................................................................................................................................................................2-3

2-4 SCAN signals ............................................................................................................................................................2-4

2-5 Clock and PLL Signals ..............................................................................................................................................2-4

2-6 Interrupt and Mode Control .......................................................................................................................................2-4

2-7 Serial Host Interface Signals .....................................................................................................................................2-6

2-8 Enhanced Serial Audio Interface Signals ..................................................................................................................2-8

2-9 Enhanced Serial Audio Interface_1 Signals ............................................................................................................2-12

2-10 Dedicated GPIO - Port G Signals ............................................................................................................................2-16

2-11 Timer Signal ............................................................................................................................................................2-18

2-12 JTAG/OnCE Interface .............................................................................................................................................2-19

3-1 Internal Memory Configuration ................................................................................................................................3-1

3-2 Internal Memory Locations .......................................................................................................................................3-1

3-3 Internal Memory Locations .......................................................................................................................................3-2

3-4 Internal Memory Locations .......................................................................................................................................3-3

3-5 Internal Memory Locations .......................................................................................................................................3-3

3-6 Internal Memory Locations .......................................................................................................................................3-4

3-7 Internal Memory Configurations ...............................................................................................................................3-5

3-8 Internal I/O Memory Map (X Memory) ....................................................................................................................3-7

3-9 Internal I/O Memory Map (Y Memory) ..................................................................................................................3-10

4-1 Operating Mode Register (OMR) ..............................................................................................................................4-1

4-2 DSP56374 Operating Modes .....................................................................................................................................4-2

4-3 DSP56374 Mode Descriptions ..................................................................................................................................4-2

4-4 Interrupt Priority Level Bits ......................................................................................................................................4-3

4-5 Interrupt Sources Priorities Within an IPL ................................................................................................................4-4

4-6 DSP56374 Interrupt Vectors .....................................................................................................................................4-6

4-7 DMA Request Sources ..............................................................................................................................................4-9

4-8 Identification Register Configuration ......................................................................................................................4-10

4-9 JTAG Identification Register Configuration ...........................................................................................................4-11

5-1 Feedback Multiplier (FM); FM = 2(1 + OD1) ..........................................................................................................5-2

5-2 Output Divide Factor (OD) .......................................................................................................................................5-3

5-3 Output Divide Factor (OD) .......................................................................................................................................5-8

5-4 PLL Control (PCTL) Register Bit Definitions ..........................................................................................................5-8

5-5 PLL Programming Examples ..................................................................................................................................5-11

6-1 PCRG and PRRG Bits Functionality .........................................................................................................................6-1

6-2 PCRH and PRRH Bits Functionality .........................................................................................................................6-3

7-1 SHI Interrupt Vectors ................................................................................................................................................7-4

7-2 SHI Internal Interrupt Priorities ................................................................................................................................7-4

7-3 SHI Noise Reduction Filter Mode .............................................................................................................................7-7

7-4 SHI Data Size ............................................................................................................................................................7-8

7-5 HREQ Function In SPI Slave Mode ..........................................................................................................................7-9

7-6 HCSR Receive Interrupt Enable Bits ......................................................................................................................7-10

8-1 Receiver Clock Sources (asynchronous mode only) .................................................................................................8-4

8-2 Transmitter Clock Sources ........................................................................................................................................8-5

8-3 Transmitter High Frequency Clock Divider ..............................................................................................................8-9

8-4 Transmit Network Mode Selection .........................................................................................................................8-12

8-5 ESAI Transmit Slot and Word Length Selection ....................................................................................................8-14

8-6 Receiver High Frequency Clock Divider ......................................................................................

8-7 SCKR Pin Definition Table .....................................................................................................................................8-18

8-8 FSR Pin Definition Table ........................................................................................................................................8-19

..........................8-18

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor LOT-1

List of Tables

Tab le Page Number Number

8-9 HCKR Pin Definition Table ....................................................................................................................................8-19

8-10 ESAI Receive Network Mode Selection .................................................................................................................8-21

8-11 ESAI Receive Slot and Word Length Selection ......................................................................................................8-21

8-12 PCRC and PRRC Bits Functionality .......................................................................................................................8-35

8-13 PCRE and PRRE Bits Functionality .......................................................................................................................8-37

9-1 Timer Prescaler Load Register (TPLR) Bit Definitions ..........................................................................................9-20

9-2 Timer Prescaler Count Register (TPCR) Bit Definitions ...................................................................................... 9--20

9-3 Timer Control/Status Register (TCSR) Bit Definitions ........................................................................................ 9--21

9-4 Inverter (INV) Bit Operation ...................................................................................................................................9-24

C-1 Internal I/O Memory Map (X Memory) ...................................................................................................................C-1

C-2 Internal I/O Memory Map (Y Memory) ...................................................................................................................C-4

C-3 DSP56374 Interrupt Vectors ....................................................................................................................................C-7

C-4 Interrupt Sources Priorities Within an IPL .............................................................................................................C-10

DSP56374 Users Guide, Rev. 1.2

LOT-2 Freescale Semiconductor

Preface

This manual describes the DSP56374 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules. The DSP56374 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP56374 are also described in this manual.

The SCF5250 is designed to support a multitude of digital signal processing applications that require a lot of horsepower in a small package. While generic in its signal-processing capabilities, the DSP56374 includes various built-in audio processing features designed to meet the needs of both consumer and automotive audio applications. The DSP56374 provides a wealth of audio-processing functions, including a basic operating system, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, and many more. The DSP56374 also supports various matrix decoders and sound-field processing algorithms. The SCF5250 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale (formerly Motorola) Symphony™ DSP family. This design provides a two-fold performance increase over Freescale’s popular DSP56000 family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access (DMA).

This manual is intended to be used with the following publications:

•The DSP56300 Family Manual (DSP56300FM/AD), which describes the CPU, core programming models and instruction set details.

•The DSP56374 Technical Data Sheet (DSP56374/D), which provides electrical specifications, timing, pinout and packaging descriptions of the DSP56374.

These documents, as well as Freescale’s DSP development tools, can be obtained through a local Freescale Semiconductor Sales Office or authorized distributor.

To receive the latest information on this DSP, access the Freescale DSP home page at the address given on the back cover of this document.

This manual contains the following sections and appendices.

Section 1—DSP56374 Overview

- Provides a brief description of the DSP56374, including a features list and block diagram. Lists related documentation needed

to use this chip and describes the organization of this manual.

Section 2—Signal/Connection Descriptions

- Describes the signals on the DSP56374 pins and how these signals are grouped into interfaces.

Section 3—Memory Configuration

- Describes the DSP56374 memory spaces, RAM and ROM configuration, memory configurations and their bit settings and

memory maps.

Section 4—Core Configuration

- Describes the registers used to configure the DSP56300 core when programming the DSP56374, in particular the interrupt

vector locations and the operation of the interrupt priority registers. Explains the operating modes and how they affect the processor’s program and data memories.

Section 5—Phase-Locked Loop (PLL) and Clock Generator

- Describes the DSP56374 PLL and clock generator capability and the programming model for the PLL (operation, registers and

control).

Section 6—General Purpose Input/Output (GPIO)

- Describes the DSP56374 GPIO capability and the programming model for the GPIO signals (operation, registers and control).

Section 7—Serial Host Interface (SHI)

- Describes the serial input/output interface providing a path for communication and program/coefficient data transfers between

the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices.

Section 8—Enhanced Serial Audio Interface (ESAI)

- Describes one of the full-duplex serial port for serial communication with a variety of serial devices.

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor i

Preface

Section 9—Triple Timer Module (TEC)

- Describes the Architecture, Programming model, and operating modes of three identical timer devices available for use as

internals or event counters. Describes the operation of the Triple Timer and its many functions.

Section 10—Watchdog Timer Module (WDT)

- Describes the Architecture, Programming model and, operating modes of the watchdog timer.

Appendix A—Bootstrap Program

- Lists the bootstrap code used for the DSP56374.

Appendix B—Equates

- Lists equates for the DSP56374.

Appendix C—Programming Reference

- Lists peripheral addresses, interrupt addresses and interrupt priorities for the DSP56374. Contains programming sheets listing

the contents of the major DSP56374 registers for programmer reference.

Appendix D—BSDL

- Provides the BSDL data for the DSP56374.

DSP56374 Users Guide, Rev. 1.2

ii Freescale Semiconductor

Revision History

The following table summarizes revisions to this document.

Revision Date Location Comments

1.1 Nov 2004 Previous release.

1.2 July 2007 Chapter 6 • In section 6.2.2 Port G Signals and Registers, corrected register acronyms (PCRG, PRRG, PDRG).

• In Table 6-2, corrected statements for ERI1, ETI0, ERI0.

Appendix B • In Equates statements, corrected addresses for PDRG, PRRG, PCRG

on page B-4.

Appendix C • In Figure C-24, corrected register addresses for PCRG, PRRG, PDRG.

• In Table C-2, corrected register acronyms for PCRG, PRRG, PDRG.

Preface

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor iii

Manual Conventions

The following conventions are used in this manual:

• Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB).

• When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer’s sheets to see the exact location of bits within a register.

• When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its value is 0.

• The word “assert” means that a high true (active high) signal is pulled high to V low to ground. The word “de-assert” means that a high true signal is pulled low to ground or that a low true signal is pulled high to

High True/Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

PIN False De-asserted V

PIN True Asserted V

PIN False De-asserted Ground

Note:

1. PIN is a generic term for any pin on the chip.

2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low).

3. V

is an acceptable high voltage level. See the appropriate data sheet for the range of

acceptable high voltage levels (typically a TTL logic high).

True Asserted Ground

or that a low true (active low) signal is pulled

• Pins or signals that are asserted low (made active when pulled to ground)

- In text, have an overbar (e.g., RESET

is asserted low).

- In code examples, have a tilde in front of their names. In example below, line 3 refers to the SS0 pin (shown as ~SS0).

• Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g., SDO0–SDO5).

• Code examples are displayed in a monospaced font, as shown below:

Example Sample Code Listing

BSET #$000007,X:PCRC; Configure:PC7 line 1

BCLR #$000007,X:PRRC; Configure:PDC7 line 2

; SDO4/SDI1 as PC7 for GPIO Input line 3

• Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFFFF is the X memory address for the core interrupt priority register (IPR-C).

• The word “reset” is used in four different contexts in this manual:

- the reset signal, written as “RESET

- the reset instruction, written as “RESET,”

- the reset operating state, written as “Reset,” and

- the reset function, written as “reset.”

,”

DSP56374 Users Guide, Rev. 1.2

iv Freescale Semiconductor

Introduction

Chapter 1 DSP56374 Overview

1.1 Introduction

The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. This manual describes the DSP56374 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules.

The DSP56374 is a member of the Symphony™ family of programmable CMOS DSPs and is built on the high performance, single-clock-per-cycle DSP56300 core. The DSP56374 is provided in either an 80-pin or 52-pin package. This design provides a two-fold performance increase over Freescale’s (formerly Motorola) popular DSP56000 Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing and direct memory access (DMA). Changes in core functionality specific to the DSP56374 are also described in this manual. See Figure 1-1 for the block diagram of the DSP56374.

GPIO

Address

Generation

Unit

DMA Unit

Data

Bus

ESAI

SHI

Interface Interface

Six Channel

Bootstrap

ROM

Internal

Switch

Clock

Gen.

PLL

12*15*

ESAI_1

Interface

PIO_EB

Program Interrupt

Controller

Watch

Triple

dog

Timer

Peripheral

Expansion Area

Program

Decode

Controller

Program

RAM

ROM

20k

Program Address

Generator

Memory Expansion Area

X Data

RAM

PM_EB

DSP56300

DDB YDB XDB PDB GDB

ROM

YAB XAB PAB

DAB

24-Bit

Core

24 Two 56-bit Accumulators

XM_EB

Data ALU

24+56→56-bit MAC

56-bit Barrel Shifter

Y Data

RAM

ROM

YM_EB

Power Mgmt.

JTAG

OnCE

XTAL

EXTAL

RESET

PINIT/NMI

MODA/IRQA/GPIO MODB/IRQB/GPIO MODC/IRQC/GPIO

MODD/IRQD/GPIO

* ESAI_1 and dedicated GPIO pins are not available in the 52-pin package.

Figure 1-1. DSP56374 Block Diagram

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DSP56300 Core Description

1.2 DSP56300 Core Description

The DSP56374 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides several times the performance of Freescale’s (formerly Motorola’s) popular DSP56000 core family while retaining code compatibility.

The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products. For a description of the DSP56300 core, see Section 1.4, DSP56300 Core Functional Blocks. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA).

The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements such as memories and peripherals. Note that new modules may be added to the library to meet customer specifications in future DSP56300 products. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. Refer to Chapter 3, Memory Configuration.

Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral features are described in this manual.

• DSP56300 modular chassis

- 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25V.

- Object Code Compatible with the 56k core.

- Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16-bit arithmatic support.

- Program Control with position independent code support.

- Six-channel DMA controller.

- Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4),

Output divide factor (1, 2 or 4) and a power-saving clock divider (2

- Internal address tracing support and OnCE for Hardware/Software debugging.

- JTAG port, supporting boundary scan, compliant to IEEE 1149.1.

- Very low-power CMOS design, fully static design with operating frequencies down to DC.

- STOP and WAIT low-power standby modes.

• On-chip Memory Configuration

- 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM.

- 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM.

- 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism.

- 6Kx24 Bit Program RAM.

- Various memory switches are available. See memory table below.

Table 1-1. DSP56374 Memory Switch Configurations

: i = 0 to 7) to reduce clock noise

Bit Settings Memory Sizes (24-bit words)

MSW1 MSW0 MS

Prog RAM

X Data

RAM

Y Data

RAM

Prog ROM

X Data

ROM

Y Data

ROM

X X 0 6k6k6k20k4k4k

0 0 1 2k 10k 6k 20k 4k 4k

0 1 1 4k 8k 6k 20k 4k 4k

1 0 1 8k 4k 6k 20k 4k 4k

1 1 1 10K 4k 4k 20k 4k 4k

• Peripheral modules

- Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I

S, Sony, AC97,

network and other programmable protocols.

- Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I

AC97, network and other programmable protocols. Note: Available in the 80-pin package only

- Serial Host Interface (SHI): SPI and I

C protocols, 10-word receive FIFO, support for 8-, 16- and 24-bit words. Three noise

reduction filter modes.

- Triple Timer module (TEC).

- Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the 80-pin

package and 20 pins on the 52-pin package.

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DSP56374 Audio Processor Architecture

- Hardware Watchdog Timer

• Packages

- 80-pin and 52-pin plastic LQFP packages.

1.3 DSP56374 Audio Processor Architecture

This section defines the DSP56374 audio processor architecture. The audio processor is composed of the following units:

• The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, DMA Controller, Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale (formerly Motorola) publication DSP56300FM/AD.

• Phased Lock Loop and Clock Generator

• Memory modules.

• Peripheral modules. The peripheral modules are defined in the following sections.

Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the memory mode of the chip. See

Table 1-1 and Section 1.4.7, On-Chip Memory for more details about memory size.

1.4 DSP56300 Core Functional Blocks

The DSP56300 core provides the following functional blocks:

• Data arithmetic logic unit (Data ALU)

• Address generation unit (AGU)

• Program control unit (PCU)

• DMA controller (with six channels)

• Instruction patch controller

• PLL-based clock oscillator

•OnCE module

•Memory

In addition, the DSP56374 provides a set of on-chip peripherals, described in Section 1.5, Peripheral Overview.

1.4.1 Data ALU

The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of the Data ALU are as follows:

• Fully pipelined 24-bit × 24-bit parallel multiplier-accumulator (MAC)

• Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

• Conditional ALU instructions

• 24-bit or 16-bit arithmetic support under software control.

• Four 24-bit input general purpose registers: X1, X0, Y1 and Y0

• Six Data ALU registers (A2, A1, A0, B2, B1 and B0) that are concatenated into two general purpose, 56-bit accumulators (A and B), accumulator shifters

• Two data bus shifter/limiter circuits

1.4.1.1 Data ALU Registers

The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator.

All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty (i.e., without a pipeline stall).

1.4.1.2 Multiplier-Accumulator (MAC)

The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands. In the case of arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following formExtension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).

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DSP56300 Core Functional Blocks

The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between two’s-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified.

1.4.2 Address Generation Unit (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead.

The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register and a modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset adder).

A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided.

The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.

Each Address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU.

1.4.3 Program Control Unit (PCU)

The PCU performs instruction prefetch, instruction decoding, hardware DO loop control and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of the following three hardware blocks:

• Program decode controller (PDC)

• Program address generator (PAG)

• Program interrupt controller

The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack and loop control. The Program interrupt controller arbitrates among all interrupt requests (internal interrupts, as well as the five external requests: IRQA, IRQB, IRQC, IRQD and NMI) and generates the appropriate interrupt vector address.

PCU features include the following:

• Position independent code support

• Addressing modes optimized for DSP applications (including immediate offsets)

• On-chip memory-expandable hardware stack

• Nested hardware DO loops

• Fast auto-return interrupts

The PCU implements its functions using the following registers:

• PC—program counter register

•SR—Status register

• LA—loop address register

• LC—loop counter register

• VBA—vector base address register

• SZ—stack size register

• SP—stack pointer

• OMR—operating mode register

• SC—stack counter register

The PCU also includes a hardware system stack (SS).

1.4.4 Internal Buses

To provide data exchange between blocks, the following buses are implemented:

• Peripheral input/output expansion bus (PIO_EB) to peripherals

• Program memory expansion bus (PM_EB) to program memory

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DSP56300 Core Functional Blocks

• X memory expansion bus (XM_EB) to X memory

• Y memory expansion bus (YM_EB) to Y memory

• Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU and PCU, as well as the memory-mapped registers in the peripherals

• DMA data bus (DDB) for carrying DMA data between memories and/or peripherals

• DMA address bus (DAB) for carrying DMA addresses to memories and peripherals

• Program Data Bus (PDB) for carrying program data throughout the core

• X memory Data Bus (XDB) for carrying X data throughout the core

• Y memory Data Bus (YDB) for carrying Y data throughout the core

• Program address bus (PAB) for carrying program memory addresses throughout the core

• X memory address bus (XAB) for carrying X memory addresses throughout the core

• Y memory address bus (YAB) for carrying Y memory addresses throughout the core

All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1.

1.4.5 Direct Memory Access (DMA)

The DMA block has the following features:

• Six DMA channels supporting internal and external accesses

• One-, two- and three-dimensional transfers (including circular buffering)

• End-of-block-transfer interrupts

• Triggering from interrupt lines and all peripherals

1.4.6 PLL-based Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, skew elimination and the clock generator (CLKGEN), which performs low-power division and clock pulse generation. PLL-based clocking:

• Allows change of low-power divide factor (DF) without loss of lock

• Provides output clock with skew elimination

• Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise

The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input. This feature offers two immediate benefits:

• A lower frequency clock input reduces the overall electromagnetic interference generated by a system.

• The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system.

1.4.7 On-Chip Memory

The memory space of the DSP56300 core is partitioned into program memory space, X data memory space and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can not be expanded off-chip.

There is an instruction patch module. The patch module is used to patch program ROM. The memory switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM).

There are on-chip ROMs for program and bootstrap memory (20k x 24-bit), X ROM (4k x 24-bit) and Y ROM(4k x 24-bit).

More information on the internal memory is provided in Chapter 3, Memory Configuration.

1.4.8 Off-Chip Memory Expansion

Memory cannot be expanded off-chip. There is no external memory bus.

1.4.9 Power Requirements

To prevent a high current condition and damage to the DSP upon power up, the 3.3V source must be applied ahead of the 1.25V source as shown below.

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Freescale Semiconductor 1-5

Peripheral Overview

1.25V

3.3V

To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is recommended to be made between the DSP56374 3.3V and 1.25V power pins.

3.3V

External Schottky

1.25V

Diode

1.5 Peripheral Overview

The DSP56374 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56374 provides the following peripherals:

• As many as 47 dedicated or user-configurable general purpose input/output (GPIO) signals on the 80-pin package and 20 dedicated or user-configurable GPIO on the 52-pin package.

• Timer/event counter (TEC) module, containing three independent timers

• Memory switch mode in on-chip memory

• Four external interrupt/mode control lines and one external non-maskable interrupt line

• Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master or slave, using the I AC97, network and other programmable protocols

• A second enhanced serial audio interface (ESAI_1) with up to four receivers and up to six transmitters, master or slave, using the

S, Sony, AC97, network and other programmable protocols. Note: only available on the 80-pin package.

• Serial host interface (SHI) using SPI and I and 24-bit words

• A Hardware Watchdog Timer.

C protocols, with multi-master capability, 10-word receive FIFO and support for 8-, 16-

1.5.1 General Purpose Input/Output (GPIO)

The 80-pin DSP56374 provides 15 dedicated GPIO and 29 programmable pins that can operate either as GPIO pins or peripheral pins (ESAI, ESAI_1 and TEC). The four MOD pins, as well as the SHI HREQ pin, can also be utilized as GPIO. The ESAI and ESAI_1 pins are configured as GPIO after hardware reset. Register-programming techniques for all GPIO functionality among these interfaces are very similar and are described in the following sections.

1.5.2 Triple Timer (TEC)

This section describes a peripheral module composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each one having its own register set.

Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Each of the three timers can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) occurred. Each of the three timers connect to the external world through bidirectional pins (TIO0, TIO1 and TIO2). When a TIO pin is configured as input, the timer functions as an external event counter or can measure external pulse width/signal period. When a

S, Sony,

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Peripheral Overview

TIO pin is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When a TIO pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer to Chapter 9, Triple Timer Module.

1.5.3 Enhanced Serial Audio Interface (ESAI)

The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors and peripherals that implement the Freescale (formerly Motorola) SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to Chapter 8, Enhanced Serial Audio Interface (ESAI).

1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1)

The ESAI_1 is a second ESAI interface. The ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1, refer to

Chapter 9, Triple Timer Module.

1.5.5 Serial Host Interface (SHI)

The SHI is a serial input/output interface providing a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Freescale (formerly Motorola) serial peripheral interface (SPI) bus and the Philips inter-integrated-circuit control (I device. To minimize DSP overhead, the SHI supports single-, double- and triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception. For more information on the SHI, refer to Chapter 7, Serial Host Interface.

C) bus. The SHI supports either the SPI or I2C bus protocol, as required, from a slave or a single-master

1.5.6 Watchdog timer (WDT)

The watchdog timer (WDT) is a 16-bit timer used to help software recover from runaway code. The timer is a free-running down-counter used to generate a reset on underflow. Software must periodically service the watchdog timer in order to restart the count down. For more information on the WDT, refer to Chapter 10, Watchdog

Tim er Mod u le.

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DSP56374 Overview

Notes

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Signal Groupings

Chapter 2 Signal/Connection Descriptions

2.1 Signal Groupings

The input and output signals of the DSP56374 are organized into functional groups, which are listed in Ta ble 2 -1.

The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. Resistor values for pins with pull up or pull down resistors may vary with lot and will be between 40k ohms and 65k ohms.

Table 2-1. DSP56374 Functional Signal Groupings

Power (V

Functional Group

)11Tab le 2 -2

Number of

Signals

Detailed

Description

Ground (GND) 9 Table 2-3

Scan Pins 1 Ta ble 2 -4.

Clock and PLL 3 Table 2 -5.

Interrupt and mode control Port H

SHI Port H

ESAI Port C

ESAI_1 Port E

Dedicated GPIO Port G

5 Ta ble 2 -6.

5 Ta ble 2 -7.

12 Tab le 2- 8.

12 Tab le 2- 9.

15 Table 2-10.

Timer 3 Table 2-11.

JTAG/OnCE Port 4 Table 2-12.

Note:

1. Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.

2. Port G signals are the dedicated GPIO port signals.

3. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

4. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

Note: Pins are not 5 V. tolerant unless noted.

2.2 Power

Table 2-2. Power Inputs

Power Name Description

PLLA_VDD

PLLP_VDD(1) PLL Power— The voltage (3.3 V) should be well-regulated, and the input should be provided with

PLLD_VDD

Freescale Semiconductor 2-1

(1) PLL Power— The voltage (3.3 V) should be well-regulated, and the input should be provided with

an extremely low impedance path to the 3.3 V

power rail. The user must provide adequate

external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter as shown in Figure 2-1. and Figure 2-2. below. See the DSP56374 technical data sheet for additional details.

an extremely low impedance path to the 3.3 V

power rail. The user must provide adequate

external decoupling capacitors between PLLP_VDD and PLLP_GND.

(1) PLL Power— The voltage (1.25 V) should be well-regulated, and the input should be provided

with an extremely low impedance path to the 1.25 V

power rail. The user must provide

adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.

DSP56374 Users Guide, Rev. 1.2

Power

Table 2-2. Power Inputs

Power Name Description

CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated, and the input should be provided

with an extremely low impedance path to the 1.25 V adequate external decoupling capacitors.

power rail. The user must provide

IO_VDD (80-pin 4) (52-pin 3)

SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide adequate external decoupling capacitors.

80 IO_Gnd

79 SDO5_PC 6

78 SDO4_PC 7

77 FSR_1_P E1

76 FSR_PC1

75 FST_PC4

74 FST_1_P E4

73 GPIO_PG1 4

72 Core_Vdd

71 Core_Gnd

70 SCKR_1_P E0

69 SCKR_PC 0

68 SCKT_PC 3

67 SCKT_1_PE3

66 HCKR_1_PE2

65 HCKR_PC2

64 HCKT_PC5

63 HCKT_1_PE5

62 SCAN

IO_Vdd 1

MODA_IRQA_PH0 2

MODB_IRQB_PH1 3

GPIO_PG13 4

GPIO_PG12 5

MODC_IRQC_PH2 6

MODD_IRQD_PH3 7

GPIO_PG11 8

Core_Vdd 9

Core_Gnd 10

GPIO_PG10 11

GPIO_PG9 12

HREQ_PH4 13

SS_HA2 14

SCK_SCL 15

MISO_SDA 16

MOSI_HA0 17

GPIO_PG8 18

GPIO_PG7 19

IO_Gnd 20

61 IO_Vdd

60 SDO5_1_PE 6

59 SDO4_1_PE 7

58 SDO3_PC8

57 SDO2_PC9

56 SDO1_PC1 0

55 SDO0_PC1 1

54 SDO3_1_PE 8

53 SDO2_1_PE 9

52 Core_Vdd

51 Core_Gnd

50 SDO1_1_PE 10

49 SDO0_1_PE 11

48 PINIT_NMI

47 IO_Vdd

46 XTAL

45 EXTAL

44 PLLD_Vdd

43 PLLD_Gnd

42 PLLP_Gnd

41 PLLP_Vd d

IO_Vdd 21

GPIO_PG6 22

GPIO_PG5 23

TDO 24

TDI 25

TMS 26

TCK 27

GPIO_PG4 28

TIO00 29

WDT/TIO1 30

PLOCK/TIO2 31

Core_Vdd 32

Core_Gnd 33

GPIO_PG3 34

RESET_B 35

GPIO_PG2 36

GPIO_PG1 37

GPIO_PG0 38

PLLA_Vdd 39

PLLA_Gnd 40

1.25 V

Filter

3.3 V

Figure 2-1. 80-pin Vdd Connections

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+ 228 hidden pages

Freescale Semiconductor DSP56374 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

DSP56374

24-Bit Digital Signal Processor

User Guide

Preface

Revision History

Manual Conventions

Chapter 1 DSP56374 Overview

1.1 Introduction

1.2 DSP56300 Core Description

1.3 DSP56374 Audio Processor Architecture

1.4 DSP56300 Core Functional Blocks

1.4.1 Data ALU

1.4.1.1 Data ALU Registers

1.4.1.2 Multiplier-Accumulator (MAC)

1.4.2 Address Generation Unit (AGU)

1.4.3 Program Control Unit (PCU)

1.4.4 Internal Buses

1.4.5 Direct Memory Access (DMA)

1.4.6 PLL-based Clock Oscillator

1.4.7 On-Chip Memory

1.4.8 Off-Chip Memory Expansion

1.4.9 Power Requirements

1.5 Peripheral Overview

1.5.1 General Purpose Input/Output (GPIO)

1.5.2 Triple Timer (TEC)

1.5.3 Enhanced Serial Audio Interface (ESAI)

1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1)

1.5.5 Serial Host Interface (SHI)

1.5.6 Watchdog timer (WDT)

Chapter 2 Signal/Connection Descriptions

2.1 Signal Groupings

2.2 Power