Freescale Semiconductor DSP56374 User Manual

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Page 1

DSP56374

24-Bit Digital Signal Processor

User Guide

Document Number: DSP56374UG

Rev. 1.2

07/2007

Page 2

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Table of Contents

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Preface i

Chapter 1

DSP56374 Overview

1.1 Introduction ...............................................................................................................................................................1-1

1.2 DSP56300 Core Description .....................................................................................................................................1-2

1.3 DSP56374 Audio Processor Architecture .................................................................................................................1-3

1.4 DSP56300 Core Functional Blocks ...........................................................................................................................1-3

1.4.1 Data ALU ............................................................................................................................................................1-3

1.4.1.1 Data ALU Registers ......................................................................................................................................1-3

1.4.1.2 Multiplier-Accumulator (MAC) ...................................................................................................................1-3

1.4.2 Address Generation Unit (AGU) ........................................................................................................................1-4

1.4.3 Program Control Unit (PCU) ..............................................................................................................................1-4

1.4.4 Internal Buses ......................................................................................................................................................1-4

1.4.5 Direct Memory Access (DMA) ...........................................................................................................................1-5

1.4.6 PLL-based Clock Oscillator ................................................................................................................................1-5

1.4.7 On-Chip Memory ................................................................................................................................................1-5

1.4.8 Off-Chip Memory Expansion .............................................................................................................................1-5

1.4.9 Power Requirements ...........................................................................................................................................1-5

1.5 Peripheral Overview ..................................................................................................................................................1-6

1.5.1 General Purpose Input/Output (GPIO) ...............................................................................................................1-6

1.5.2 Triple Timer (TEC) .............................................................................................................................................1-6

1.5.3 Enhanced Serial Audio Interface (ESAI) ............................................................................................................1-7

1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1) .....................................................................................................1-7

1.5.5 Serial Host Interface (SHI) .................................................................................................................................1-7

1.5.6 Watchdog timer (WDT) ......................................................................................................................................1-7

Chapter 2

Signal/Connection Descriptions

2.1 Signal Groupings .......................................................................................................................................................2-1

2.2 Power .........................................................................................................................................................................2-1

2.3 Ground .......................................................................................................................................................................2-3

2.4 SCAN ........................................................................................................................................................................2-4

2.5 Clock and PLL ...........................................................................................................................................................2-4

2.6 Interrupt and Mode Control .......................................................................................................................................2-4

2.7 Serial Host Interface ..................................................................................................................................................2-6

2.8 Enhanced Serial Audio Interface ...............................................................................................................................2-8

2.9 Enhanced Serial Audio Interface_1 .........................................................................................................................2-12

2.10 Dedicated GPIO - Port G .........................................................................................................................................2-16

2.11 Timer .......................................................................................................................................................................2-18

2.12 JTAG/OnCE Interface .............................................................................................................................................2-19

Chapter 3

Memory Configuration

3.1 Data and Program Memory Maps .............................................................................................................................3-1

3.1.1 Reserved Memory Spaces ...................................................................................................................................3-5

3.1.2 Bootstrap CODE .................................................................................................................................................3-5

3.1.3 Dynamic Memory Configuration Switching ......................................................................................................3-5

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3.1.4 External Memory Support ...................................................................................................................................3-5

3.1.5 DMA and Memory ..............................................................................................................................................3-5

3.1.6 Memory BLOCKS ..............................................................................................................................................3-6

3.2 Memory Patch Module ..............................................................................................................................................3-6

3.3 Internal I/O Memory Map .........................................................................................................................................3-7

Chapter 4

Core Configuration

4.1 Introduction ...............................................................................................................................................................4-1

4.2 Operating Mode Register (OMR) ..............................................................................................................................4-1

4.2.1 RESERVED - Bits 4, 5, 10 - 15 and 23 ..............................................................................................................4-1

4.3 Operating Modes .......................................................................................................................................................4-1

4.4 Interrupt Priority Registers ........................................................................................................................................4-3

4.5 DMA Request Sources ..............................................................................................................................................4-9

4.6 PLL Initialization ....................................................................................................................................................4-10

4.6.1 PLL Pre-Divider Factor (PD0-PD4) .................................................................................................................4-10

4.6.2 PLL Multiplication Factor (MF0-MF7) ............................................................................................................4-10

4.6.3 PLL Feedback Multiplier (OD1) ......................................................................................................................4-10

4.6.4 PLL Output Divide Factor (OD0-OD1) ............................................................................................................4-10

4.6.5 PLL Divider Factor (DF0-DF2) ........................................................................................................................4-10

4.6.6 PLL LOCK MUX (PLKM) ..............................................................................................................................4-10

4.7 Device Identification (ID) Register .........................................................................................................................4-10

4.8 JTAG Identification (ID) Register ..........................................................................................................................4-11

Chapter 5

PLL and Clock generator

5.1 Introduction ...............................................................................................................................................................5-1

5.2 PLL and Clock Signals ..............................................................................................................................................5-1

5.3 PLL Block .................................................................................................................................................................5-1

5.3.1 Frequency Predivider ..........................................................................................................................................5-2

5.3.2 Phase Detector and Charge Pump Loop Filter ....................................................................................................5-2

5.3.3 Voltage Controlled Oscillator (VCO) .................................................................................................................5-2

5.3.4 PLL DividerS ......................................................................................................................................................5-2

5.3.5 PLL Multiplication Factor (MF) .........................................................................................................................5-3

5.4 PLL Operation ...........................................................................................................................................................5-3

5.4.1 EXTAL Clock Input Division .............................................................................................................................5-3

5.4.2 PLL Frequency Multiplication ............................................................................................................................5-3

5.4.3 PLL Output Frequency (PLL Out) ......................................................................................................................5-4

5.5 Clock Generator ........................................................................................................................................................5-6

5.5.1 Low-Power Divider (LPD) .................................................................................................................................5-6

5.6 Operating Frequency (Fosc) ......................................................................................................................................5-6

5.7 PLL Programming Model .........................................................................................................................................5-7

5.8 PLL Initialization Procedure ...................................................................................................................................5-10

5.9 PLL Programming Examples ..................................................................................................................................5-11

Chapter 6

General Purpose Input/Output

6.1 Introduction ..............................................................................................................................................................6-1

6.2 Programming Model ..................................................................................................................................................6-1

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6.2.1 Port C and E Signals and Registers .....................................................................................................................6-1

6.2.2 Port G Signals and Registers ...............................................................................................................................6-1

6.2.2.1 Port G Control Register (PCRG) ..................................................................................................................6-1

6.2.2.2 Port G Direction Register (PRRG) ...............................................................................................................6-1

6.2.2.3 Port G Data register (PDRG) ........................................................................................................................6-2

6.2.2.4 ESAI/EXTAL clocking control ....................................................................................................................6-2

6.2.3 Port H Signals and Registers ...............................................................................................................................6-3

6.2.3.1 Port H Control Register (PCRH) ..................................................................................................................6-3

6.2.3.2 Port H Direction Register (PRRH) ...............................................................................................................6-3

6.2.3.3 Port H Data register (PDRH) ........................................................................................................................6-4

6.2.4 Timer/Event Counter Signals ..............................................................................................................................6-4

Chapter 7

Serial Host Interface

7.1 Introduction ...............................................................................................................................................................7-1

7.2 Serial Host Interface Internal Architecture ...............................................................................................................7-1

7.3 SHI Clock Generator .................................................................................................................................................7-2

7.4 Serial Host Interface Programming Model ...............................................................................................................7-2

7.4.1 SHI Input/Output Shift Register (IOSR)—Host Side .........................................................................................7-4

7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side ........................................................................................7-4

7.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side ..............................................................................................7-5

7.4.4 SHI Slave Address Register (HSAR)—DSP Side ..............................................................................................7-5

7.4.4.1 HSAR Reserved Bits—Bits 19, 17– 0 ..........................................................................................................7-5

7.4.4.2 HSAR I

7.4.5 SHI Clock Control Register (HCKR)—DSP Side ..............................................................................................7-5

7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0 ............................................................................7-5

7.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 .................................................................................................7-6

7.4.5.3 HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3 ............................................................................7-7

7.4.5.4 HCKR Filter Mode (HFM[1:0]) — Bits 13–12 ............................................................................................7-7

7.4.5.5 HCKR Reserved Bits—Bits 23–14, 11 ........................................................................................................7-7

7.4.6 SHI Control/Status Register (HCSR)—DSP Side ..............................................................................................7-7

7.4.6.1 HCSR Host Enable (HEN)—Bit 0 ...............................................................................................................7-7

7.4.6.1.1 SHI Individual Reset ..............................................................................................................................7-8

7.4.6.2 HCSR I

7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 ............................................................................7-8

7.4.6.4 HCSR I

7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 .............................................................................................7-8

7.4.6.6 HCSR Master Mode (HMST)—Bit 6 ...........................................................................................................7-8

7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7 .................................................................................7-9

7.4.6.8 HCSR Idle (HIDLE)—Bit 9 .........................................................................................................................7-9

7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10 .....................................................................................7-9

7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 ......................................................................................7-9

7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12 .......................................................................7-10

7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14 ............................................................................7-10

7.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15 .................................................................................7-10

7.4.6.14 HCSR Reserved Bits—Bits 23, 18 and 16 .................................................................................................7-10

7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17 ......................................................................................7-10

7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 ..................................................................................................7-10

7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20 ...........................................................................................7-11

C Slave Address (HA[6:3], HA1)—Bits 23–20,18 .......................................................................7-5

C/SPI Selection (HI2C)—Bit 1 ......................................................................................................7-8

C Clock Freeze (HCKFR)—Bit 4 ..................................................................................................7-8

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7.4.6.18 Host Bus Error (HBER)—Bit 21 ................................................................................................................7-11

7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22 .........................................................................................................7-11

7.5 Characteristics Of The SPI Bus ...............................................................................................................................7-11

7.6 Characteristics Of The I

7.6.1 Overview ...........................................................................................................................................................7-11

7.6.2 I2C Data Transfer Formats ................................................................................................................................7-13

7.7 SHI Programming Considerations ...........................................................................................................................7-13

7.7.1 SPI Slave Mode .................................................................................................................................................7-13

7.7.2 SPI Master Mode ..............................................................................................................................................7-14

7.7.3 I

7.7.3.1 Receive Data in I2C Slave Mode ................................................................................................................7-15

7.7.3.2 Transmit Data In I2C Slave Mode ..............................................................................................................7-15

7.7.4 I

7.7.4.1 Receive Data in I2C Master Mode ..............................................................................................................7-16

7.7.4.2 Transmit Data In I2C Master Mode ............................................................................................................7-16

7.7.5 SHI Operation During DSP Stop ......................................................................................................................7-17

7.7.6 GPIO- HREQ Signal and Registers ..................................................................................................................7-17

C Slave Mode .................................................................................................................................................7-14

C Master Mode ...............................................................................................................................................7-15

C Bus ...............................................................................................................................7-11

Chapter 8

Enhanced Serial Audio Interface (ESAI)

8.1 Introduction ...............................................................................................................................................................8-1

8.2 ESAI Data and Control Pins ......................................................................................................................................8-2

8.2.1 Serial Transmit 0 Data Pin (SDO0) ....................................................................................................................8-3

8.2.2 Serial Transmit 1 Data Pin (SDO1) ....................................................................................................................8-3

8.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) ..........................................................................................8-3

8.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) ..........................................................................................8-3

8.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) ..........................................................................................8-3

8.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) ..........................................................................................8-3

8.2.7 Receiver Serial Clock (SCKR) ...........................................................................................................................8-4

8.2.8 Transmitter Serial Clock (SCKT) .......................................................................................................................8-4

8.2.9 Frame Sync for Receiver (FSR) ..........................................................................................................................8-5

8.2.10 Frame Sync for Transmitter (FST) .....................................................................................................................8-6

8.2.11 High Frequency Clock for Transmitter (HCKT) ................................................................................................8-6

8.2.12 High Frequency Clock for Receiver (HCKR) .....................................................................................................8-6

8.3 ESAI Programming Model ........................................................................................................................................8-6

8.3.1 ESAI Transmitter Clock Control Register (TCCR) ............................................................................................8-6

8.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 7–0 .........................................................8-7

8.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8 .........................................................................................8-8

8.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 13–9 ............................................................8-8

8.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 17–14 ........................................................8-8

8.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 .........................................................................................8-9

8.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 ................................................................................8-9

8.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 ...........................................................8-9

8.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 ..........................................................................8-9

8.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22 ..................................................................8-9

8.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 ........................................................8-9

8.3.2 ESAI Transmit Control Register (TCR) .............................................................................................................8-9

8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0 ..............................................................................................8-10

8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1 ..............................................................................................8-10

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8.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2 ..............................................................................................8-10

8.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 ..............................................................................................8-11

8.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 ..............................................................................................8-11

8.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5 ..............................................................................................8-11

8.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6 .........................................................................................8-11

8.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7 ............................................................................8-11

8.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 9-8 ......................................................8-12

8.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 14-10 .....................................................8-13

8.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15 ..................................................................................8-14

8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 ...................................................................8-15

8.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17 ..............................................................................8-16

8.3.2.14 TCR Reserved Bit - Bits 18 ........................................................................................................................8-16

8.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19 ...............................................................................8-16

8.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 .......................................................................8-16

8.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 ............................................................8-16

8.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22 ...........................................................................................8-16

8.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 .........................................................................8-16

8.3.3 ESAI Receive Clock Control Register (RCCR) ...............................................................................................8-16

8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0 .......................................................8-17

8.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8 .......................................................................................8-17

8.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 13–9 .........................................................8-17

8.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 17-14 ......................................................8-17

8.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18 .......................................................................................8-18

8.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19 ..............................................................................8-18

8.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 .........................................................8-18

8.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 ........................................................................8-18

8.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 ................................................................8-19

8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 ......................................................8-19

8.3.4 ESAI Receive Control Register (RCR) .............................................................................................................8-19

8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 ..............................................................................................8-20

8.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 ..............................................................................................8-20

8.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2.............................................................................................. 8-20

8.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 ..............................................................................................8-20

8.3.4.5 RCR Reserved Bits - Bits 5-4, 18-17 .........................................................................................................8-20

8.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6 ........................................................................................8-20

8.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7 ...........................................................................8-21

8.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 9-8 .....................................................8-21

8.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 14-10 .......................................................8-21

8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 ..................................................................................8-22

8.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16 ...................................................................8-22

8.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19 ...............................................................................8-22

8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 ........................................................................8-23

8.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 .............................................................8-23

8.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22 ............................................................................................8-23

8.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 ..........................................................................8-23

8.3.5 ESAI Common Control Register (SAICR) .......................................................................................................8-23

8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 .................................................................................................8-23

8.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 .................................................................................................8-24

8.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 .................................................................................................8-24

8.3.5.4 SAICR Reserved Bits - Bits 5-3, 23-9 ........................................................................................................8-24

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8.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6 .................................................................................8-24

8.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7 ..........................................................................8-24

8.3.5.7 SAICR Alignment Control (ALC) - Bit 8 ..................................................................................................8-24

8.3.6 ESAI Status Register (SAISR) ..........................................................................................................................8-25

8.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 ......................................................................................................8-26

8.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1 ......................................................................................................8-26

8.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2 ......................................................................................................8-26

8.3.6.4 SAISR Reserved Bits - Bits 5-3, 12-11, 23-18 ...........................................................................................8-26

8.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 .........................................................................................8-26

8.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7 ...................................................................................8-26

8.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8 ......................................................................................8-27

8.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9 ..........................................................................8-27

8.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10 .........................................................................8-27

8.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13 .....................................................................................8-27

8.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14 ...............................................................................8-27

8.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15 ..............................................................................8-27

8.3.6.14 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16 ..................................................................8-27

8.3.6.13 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17 ................................................................... 8-28

8.3.7 ESAI Receive Shift Registers ...........................................................................................................................8-29

8.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0) ....................................................................................8-30

8.3.9 ESAI Transmit Shift Registers ..........................................................................................................................8-30

8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) ..................................................................8-30

8.3.11 ESAI Time Slot Register (TSR) .......................................................................................................................8-30

8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) ...............................................................................................8-30

8.3.13 Receive Slot Mask Registers (RSMA, RSMB) ................................................................................................8-31

8.4 Operating Modes .....................................................................................................................................................8-32

8.4.1 ESAI After Reset ..............................................................................................................................................8-32

8.4.2 ESAI Initialization ............................................................................................................................................8-32

8.4.3 ESAI Interrupt Requests ...................................................................................................................................8-33

8.4.4 Operating Modes – Normal, Network and On-Demand ...................................................................................8-33

8.4.4.1 Normal/Network/On-Demand Mode Selection ..........................................................................................8-33

8.4.4.2 Synchronous/Asynchronous Operating Modes ..........................................................................................8-34

8.4.4.3 Frame Sync Selection 3 ...............................................................................................................................8-34

8.4.4.4 Shift Direction Selection ............................................................................................................................8-34

8.4.5 Serial I/O Flags .................................................................................................................................................8-34

8.5 GPIO - Pins and Registers .......................................................................................................................................8-35

8.5.1 Port C (ESAI) GPIO - Pins and Registers ........................................................................................................8-35

8.5.1.1 Port C Control Register (PCRC) ................................................................................................................8-35

8.5.1.2 Port C Direction Register (PRRC) ..............................................................................................................8-35

8.5.1.3 Port C Data register (PDRC) ...................................................................................................................... 8-36

8.5.2 Port E (ESAI_1) GPIO - Pins and Registers .....................................................................................................8-36

8.5.2.1 Port E Control Register (PCRE) .................................................................................................................8-37

8.5.2.2 Port E Direction Register (PRRE) ..............................................................................................................8-37

8.5.2.3 Port E Data register (PDRE) .......................................................................................................................8-37

8.6 ESAI Initialization Examples ..................................................................................................................................8-38

8.6.1 Initializing the ESAI Using Individual Reset ...................................................................................................8-38

8.6.2 Initializing Just the ESAI Transmitter Section .................................................................................................8-38

8.6.3 Initializing Just the ESAI Receiver Section ......................................................................................................8-38

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Table of Contents

Paragraph Page Number Number

Chapter 9

Triple Timer Module

9.1 Overview ...................................................................................................................................................................9-1

9.1.1 Triple Timer Module Block Diagram .................................................................................................................9-1

9.1.2 Individual Timer Block Diagram ........................................................................................................................9-1

9.2 Operation ...................................................................................................................................................................9-2

9.2.1 Timer After Reset ...............................................................................................................................................9-2

9.2.2 Timer Initialization .............................................................................................................................................9-2

9.2.3 Timer Exceptions ................................................................................................................................................9-3

9.3 Operating Modes .......................................................................................................................................................9-3

9.3.1 Triple Timer Modes ............................................................................................................................................9-3

9.3.1.1 Timer GPIO (Mode 0) ..................................................................................................................................9-4

9.3.1.2 Timer Pulse (Mode 1) ...................................................................................................................................9-5

9.3.1.3 Timer Toggle (Mode 2) ................................................................................................................................9-7

9.3.1.4 Timer Event Counter (Mode 3) ....................................................................................................................9-9

9.3.2 Signal Measurement Modes ..............................................................................................................................9-10

9.3.2.1 Measurement Input Width (Mode 4) ..........................................................................................................9-10

9.3.2.2 Measurement Input Period (Mode 5) ..........................................................................................................9-12

9.3.2.3 Measurement Capture (Mode 6) .................................................................................................................9-13

9.3.3 Pulse Width Modulation (PWM, Mode 7) ........................................................................................................9-14

9.3.4 Watchdog Modes ..............................................................................................................................................9-16

9.3.4.1 Watchdog Pulse (Mode 9) ..........................................................................................................................9-16

9.3.4.2 Watchdog Toggle (Mode 10) .....................................................................................................................9-17

9.3.4.3 Reserved Modes .........................................................................................................................................9-18

9.3.5 Special Cases ....................................................................................................................................................9-18

9.3.6 DMA Trigger ....................................................................................................................................................9-18

9.4 Triple Timer Module Programming Model .............................................................................................................9-18

9.4.1 Prescaler Counter ..............................................................................................................................................9-18

9.4.2 Timer Prescaler Load Register (TPLR) ............................................................................................................9-19

9.4.3 Timer Prescaler Count Register (TPCR) ..........................................................................................................9-20

9.4.4 Timer Control/Status Register (TCSR) .............................................................................................................9-21

9.4.5 Timer Load Register (TLR) ..............................................................................................................................9-25

9.4.6 Timer Compare Register (TCPR) .....................................................................................................................9-25

9.4.7 Timer Count Register (TCR) ............................................................................................................................9-25

Chapter 10

Watchdog Timer Module

10.1 Introduction ............................................................................................................................................................10-1

10.2 WDT Pin ..................................................................................................................................................................10-1

10.3 WDT Operation ......................................................................................................................................................10-1

10.4 Description of Registers ..........................................................................................................................................10-2

10.4.1 Watchdog Control Register (WCR) .................................................................................................................10-2

10.4.2 Watchdog Counter & WCNTR Register ..........................................................................................................10-2

10.4.3 Watchdog Modulus Register (WMR) ..............................................................................................................10-3

10.4.4 Watchdog Service Register (WSR) ..................................................................................................................10-3

10.5 Operation in Different Modes ................................................................................................................................10-3

10.5.1 WAIT Mode .....................................................................................................................................................10-3

10.5.2 DEBUG Mode .................................................................................................................................................10-3

10.5.3 STOP MODE ....................................................................................................................................................10-3

DSP56374 Users Guide, Rev. 1.2

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Table Of Contents

Paragraph Page Number Number

Appendix A

Bootstrap Source Code

A.1 DSP56374 Bootstrap Program .................................................................................................................................A-1

A.2 Using The Serial EEPROM Boot Mode ...................................................................................................................A-5

Appendix B

Equates

Appendix C

Programmer’s Reference

C.1 Introduction ..............................................................................................................................................................C-1

C.1.1 Peripheral Addresses ..........................................................................................................................................C-1

C.1.2 Interrupt Addresses ............................................................................................................................................C-1

C.1.3 Interrupt Priorities ..............................................................................................................................................C-1

C.1.4 Programming Sheets ..........................................................................................................................................C-1

C.1.5 Internal I/O Memory Map ..................................................................................................................................C-1

C.1.6 Interrupt Vector Addresses ................................................................................................................................C-7

C.2 Interrupt Source Priorities (within an IPL) .............................................................................................................C-10

C.3 Programming Sheets ...............................................................................................................................................C-11

Appendix D

BSDL

D.1 52-pin BSDL ............................................................................................................................................................D-1

D.2 80-pin BSDL ............................................................................................................................................................D-6

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List of Figures

Figure Page Number Number

1-1 DSP56374 Block Diagram ........................................................................................................................................1-1

2-1 80-pin Vdd Connections ............................................................................................................................................2-2

2-2 52-pin Vdd Connections ............................................................................................................................................2-3

3-1 Default Memory Map (MS 0) ...................................................................................................................................3-2

3-2 Memory Map (MS 1, MSW(1-0) 11) ........................................................................................................................3-2

3-3 Memory Map (MS 1, MSW(1-0) 10) ........................................................................................................................3-3

3-4 Memory Map (MS 1, MSW(1-0) 01) ........................................................................................................................3-4

3-5 Memory Map (MS 1, MSW(1-0) 00) ........................................................................................................................3-4

4-1 Interrupt Priority Register P ......................................................................................................................................4-4

4-2 Interrupt Priority Register C ......................................................................................................................................4-4

4-3 PCTL Register .........................................................................................................................................................4-10

5-1 PLL Clock Generator Block Diagram .......................................................................................................................5-1

5-2 PLL Block Diagram ..................................................................................................................................................5-2

5-3 PLL Loop with One Divider when OD1=0 (FM = 2) ...............................................................................................5-4

5-4 PLL Loop with Two Dividers when OD1=1 (FM = 4) .............................................................................................5-4

5-5 PLL Out = VCO Out/2 [OD1 = 0, OD0 = 1] ............................................................................................................5-5

5-6 PLL Out = VCO Out/2 [OD1 = 1, OD0 = 0] ............................................................................................................5-5

5-7 PLL Out = VCO Out/4 [OD1 = 1, OD0 = 1] ............................................................................................................5-6

5-8 CLKGEN Block Diagram .........................................................................................................................................5-6

5-9 PLL Control (PCTL) Register ...................................................................................................................................5-7

6-1 PCRG Register ..........................................................................................................................................................6-2

6-2 PRRG Register ..........................................................................................................................................................6-2

6-3 PDRG Register ..........................................................................................................................................................6-2

6-4 PCRH Register ..........................................................................................................................................................6-4

6-5 PRRH Register ..........................................................................................................................................................6-4

6-6 PDRH Register ..........................................................................................................................................................6-4

7-1 Serial Host Interface Block Diagram ........................................................................................................................7-2

7-2 SHI Clock Generator .................................................................................................................................................7-2

7-3 SHI Programming Model—Host Side ......................................................................................................................7-3

7-4 SHI Programming Model—DSP Side .......................................................................................................................7-3

7-5 SHI I/O Shift Register (IOSR) ..................................................................................................................................7-4

7-6 SPI Data-To-Clock Timing Diagram ........................................................................................................................7-6

7-7 I

7-8 I

7-9 Acknowledgment on the I2C Bus ............................................................................................................................7-12

7-10 I

7-11 I2C Bus Protocol For Host Read Cycle ...................................................................................................................7-13

8-1 ESAI Block Diagram .................................................................................................................................................8-2

8-2 TCCR Register ..........................................................................................................................................................8-6

8-3 ESAI Clock Generator Functional Block Diagram ...................................................................................................8-7

8-4 ESAI Frame Sync Generator Functional Block Diagram .........................................................................................8-8

8-5 TCR Register ...........................................................................................................................................................8-10

8-6 Normal and Network Operation ..............................................................................................................................8-13

8-7 Frame Length Selection ...........................................................................................................................................8-15

8-8 RCCR Register ........................................................................................................................................................8-17

8-9 RCR Register ...........................................................................................................................................................8-20

8-10 SAICR Register .......................................................................................................................................................8-23

8-11 SAICR SYN Bit Operation .....................................................................................................................................8-25

C Bit Transfer .......................................................................................................................................................7-12

C Start and Stop Events ........................................................................................................................................7-12

C Bus Protocol For Host Write Cycle ..................................................................................................................7-13

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Page 12

List of Figures

Figure Page Number Number

8-12 SAISR Register .......................................................................................................................................................8-26

8-13 ESAI Data Path Programming Model ([R/T]SHFD=0) ..........................................................................................8-28

8-14 ESAI Data Path Programming Model ([R/T]SHFD=1) ..........................................................................................8-29

8-15 TSMA Register ........................................................................................................................................................8-30

8-16 RSMA Register .......................................................................................................................................................8-31

8-17 TSMB Register ........................................................................................................................................................8-31

8-18 RSMB Register ........................................................................................................................................................8-32

8-19 PCRC Register ........................................................................................................................................................8-36

8-20 PRRC Register ........................................................................................................................................................8-36

8-21 PDRC Register ........................................................................................................................................................8-36

8-22 PCRE Register .........................................................................................................................................................8-37

8-23 PRRE Register .........................................................................................................................................................8-37

8-24 PDRE Register ........................................................................................................................................................8-38

9-1 Triple Timer Module Block Diagram .......................................................................................................................9-1

9-2 Timer Module Block Diagram ..................................................................................................................................9-2

9-3 Timer Mode (TRM = 1) ............................................................................................................................................9-4

9-4 Timer Mode (TRM = 0) ............................................................................................................................................9-5

9-5 Pulse Mode (TRM = 1) .............................................................................................................................................9-6

9-6 Pulse Mode (TRM = 0) .............................................................................................................................................9-7

9-7 Toggle Mode, TRM = 1 ............................................................................................................................................9-8

9-8 Toggle Mode, TRM = 0 ............................................................................................................................................9-8

9-9 Event Counter Mode, TRM = 1 .................................................................................................................................9-9

9-10 Event Counter Mode, TRM = 0 ...............................................................................................................................9-10

9-11 Pulse Width Measurement Mode, TRM = 1 ...........................................................................................................9-11

9-12 Pulse Width Measurement Mode, TRM = 0 ...........................................................................................................9-11

9-13 Period Measurement Mode, TRM = 1 .....................................................................................................................9-12

9-14 Period Measurement Mode, TRM = 0 .....................................................................................................................9-13

9-15 Capture Measurement Mode, TRM = 0 ..................................................................................................................9-14

9-16 Pulse Width Modulation Toggle Mode, TRM = 1 ..................................................................................................9-15

9-17 Pulse Width Modulation Toggle Mode, TRM = 0 ..................................................................................................9-16

9-18 Watchdog Pulse Mode .............................................................................................................................................9-17

9-19 Watchdog Toggle Mode ..........................................................................................................................................9-18

9-20 Timer Module Programmer’s Model ......................................................................................................................9-19

9-21 Timer Prescaler Count Register (TPCR) .................................................................................................................9-20

10-1 Watchdog Timer Block Diagram .............................................................................................................................10-2

C-1 Status Register (SR) ...............................................................................................................................................C-12

C-2 Operating Mode Register (OMR) ...........................................................................................................................C-13

C-3 Interrupt Priority Register–Core (IPR–C) ..............................................................................................................C-14

C-4 Interrupt Priority Register – Peripherals (IPR–P) ..................................................................................................C-15

C-5 Phase Lock Loop Control Register (PCTL) ...........................................................................................................C-16

C-6 SHI Slave Address and Clock Control Registers ...................................................................................................C-17

C-7 SHI Host Control/Status Register ...........................................................................................................................C-18

C-8 ESAI Transmit Clock Control Register ..................................................................................................................C-19

C-9 ESAI Transmit Control Register ............................................................................................................................C-20

C-10 ESAI Receive Clock Control Register ...................................................................................................................C-21

C-11 ESAI Receive Control Register ..............................................................................................................................C-22

C-12 ESAI Common Control Register ............................................................................................................................C-23

C-13 ESAI Status Register ..............................................................................................................................................C-24

C-14 ESAI_1 Transmit Clock Control Register ..............................................................................................................C-25

C-15 ESAI_1 Transmit Control Register ........................................................................................................................C-26

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Page 13

List of Figures

Figure Page Number Number

C-16 ESAI_1 Receive Clock Control Register ...............................................................................................................C-27

C-17 ESAI_1 Receive Control Register ..........................................................................................................................C-28

C-18 ESAI_1 Common Control Register ........................................................................................................................C-29

C-19 ESAI_1 Status Register ..........................................................................................................................................C-30

C-20 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) ...................................................................C-31

C-21 Timer Control/Status Register ................................................................................................................................C-32

C-22 Timer Load, Compare and Count Registers ...........................................................................................................C-33

C-23 GPIO Port C ...........................................................................................................................................................C-35

C-24 GPIO Port E ............................................................................................................................................................C-36

C-25 GPIO Port G ...........................................................................................................................................................C-37

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List of Figures

Notes

DSP56374 Users Guide, Rev. 1.2

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List of Tables

Tab le Page Number Number

1-1 DSP56374 Memory Switch Configurations ..............................................................................................................1-2

2-1 DSP56374 Functional Signal Groupings ..................................................................................................................2-1

2-2 Power Inputs ..............................................................................................................................................................2-1

2-3 Grounds .....................................................................................................................................................................2-3

2-4 SCAN signals ............................................................................................................................................................2-4

2-5 Clock and PLL Signals ..............................................................................................................................................2-4

2-6 Interrupt and Mode Control .......................................................................................................................................2-4

2-7 Serial Host Interface Signals .....................................................................................................................................2-6

2-8 Enhanced Serial Audio Interface Signals ..................................................................................................................2-8

2-9 Enhanced Serial Audio Interface_1 Signals ............................................................................................................2-12

2-10 Dedicated GPIO - Port G Signals ............................................................................................................................2-16

2-11 Timer Signal ............................................................................................................................................................2-18

2-12 JTAG/OnCE Interface .............................................................................................................................................2-19

3-1 Internal Memory Configuration ................................................................................................................................3-1

3-2 Internal Memory Locations .......................................................................................................................................3-1

3-3 Internal Memory Locations .......................................................................................................................................3-2

3-4 Internal Memory Locations .......................................................................................................................................3-3

3-5 Internal Memory Locations .......................................................................................................................................3-3

3-6 Internal Memory Locations .......................................................................................................................................3-4

3-7 Internal Memory Configurations ...............................................................................................................................3-5

3-8 Internal I/O Memory Map (X Memory) ....................................................................................................................3-7

3-9 Internal I/O Memory Map (Y Memory) ..................................................................................................................3-10

4-1 Operating Mode Register (OMR) ..............................................................................................................................4-1

4-2 DSP56374 Operating Modes .....................................................................................................................................4-2

4-3 DSP56374 Mode Descriptions ..................................................................................................................................4-2

4-4 Interrupt Priority Level Bits ......................................................................................................................................4-3

4-5 Interrupt Sources Priorities Within an IPL ................................................................................................................4-4

4-6 DSP56374 Interrupt Vectors .....................................................................................................................................4-6

4-7 DMA Request Sources ..............................................................................................................................................4-9

4-8 Identification Register Configuration ......................................................................................................................4-10

4-9 JTAG Identification Register Configuration ...........................................................................................................4-11

5-1 Feedback Multiplier (FM); FM = 2(1 + OD1) ..........................................................................................................5-2

5-2 Output Divide Factor (OD) .......................................................................................................................................5-3

5-3 Output Divide Factor (OD) .......................................................................................................................................5-8

5-4 PLL Control (PCTL) Register Bit Definitions ..........................................................................................................5-8

5-5 PLL Programming Examples ..................................................................................................................................5-11

6-1 PCRG and PRRG Bits Functionality .........................................................................................................................6-1

6-2 PCRH and PRRH Bits Functionality .........................................................................................................................6-3

7-1 SHI Interrupt Vectors ................................................................................................................................................7-4

7-2 SHI Internal Interrupt Priorities ................................................................................................................................7-4

7-3 SHI Noise Reduction Filter Mode .............................................................................................................................7-7

7-4 SHI Data Size ............................................................................................................................................................7-8

7-5 HREQ Function In SPI Slave Mode ..........................................................................................................................7-9

7-6 HCSR Receive Interrupt Enable Bits ......................................................................................................................7-10

8-1 Receiver Clock Sources (asynchronous mode only) .................................................................................................8-4

8-2 Transmitter Clock Sources ........................................................................................................................................8-5

8-3 Transmitter High Frequency Clock Divider ..............................................................................................................8-9

8-4 Transmit Network Mode Selection .........................................................................................................................8-12

8-5 ESAI Transmit Slot and Word Length Selection ....................................................................................................8-14

8-6 Receiver High Frequency Clock Divider ......................................................................................

8-7 SCKR Pin Definition Table .....................................................................................................................................8-18

8-8 FSR Pin Definition Table ........................................................................................................................................8-19

..........................8-18

DSP56374 Users Guide, Rev. 1.2

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Page 16

List of Tables

Tab le Page Number Number

8-9 HCKR Pin Definition Table ....................................................................................................................................8-19

8-10 ESAI Receive Network Mode Selection .................................................................................................................8-21

8-11 ESAI Receive Slot and Word Length Selection ......................................................................................................8-21

8-12 PCRC and PRRC Bits Functionality .......................................................................................................................8-35

8-13 PCRE and PRRE Bits Functionality .......................................................................................................................8-37

9-1 Timer Prescaler Load Register (TPLR) Bit Definitions ..........................................................................................9-20

9-2 Timer Prescaler Count Register (TPCR) Bit Definitions ...................................................................................... 9--20

9-3 Timer Control/Status Register (TCSR) Bit Definitions ........................................................................................ 9--21

9-4 Inverter (INV) Bit Operation ...................................................................................................................................9-24

C-1 Internal I/O Memory Map (X Memory) ...................................................................................................................C-1

C-2 Internal I/O Memory Map (Y Memory) ...................................................................................................................C-4

C-3 DSP56374 Interrupt Vectors ....................................................................................................................................C-7

C-4 Interrupt Sources Priorities Within an IPL .............................................................................................................C-10

DSP56374 Users Guide, Rev. 1.2

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Page 17

Preface

This manual describes the DSP56374 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules. The DSP56374 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP56374 are also described in this manual.

The SCF5250 is designed to support a multitude of digital signal processing applications that require a lot of horsepower in a small package. While generic in its signal-processing capabilities, the DSP56374 includes various built-in audio processing features designed to meet the needs of both consumer and automotive audio applications. The DSP56374 provides a wealth of audio-processing functions, including a basic operating system, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, and many more. The DSP56374 also supports various matrix decoders and sound-field processing algorithms. The SCF5250 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale (formerly Motorola) Symphony™ DSP family. This design provides a two-fold performance increase over Freescale’s popular DSP56000 family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access (DMA).

This manual is intended to be used with the following publications:

•The DSP56300 Family Manual (DSP56300FM/AD), which describes the CPU, core programming models and instruction set details.

•The DSP56374 Technical Data Sheet (DSP56374/D), which provides electrical specifications, timing, pinout and packaging descriptions of the DSP56374.

These documents, as well as Freescale’s DSP development tools, can be obtained through a local Freescale Semiconductor Sales Office or authorized distributor.

To receive the latest information on this DSP, access the Freescale DSP home page at the address given on the back cover of this document.

This manual contains the following sections and appendices.

Section 1—DSP56374 Overview

- Provides a brief description of the DSP56374, including a features list and block diagram. Lists related documentation needed

to use this chip and describes the organization of this manual.

Section 2—Signal/Connection Descriptions

- Describes the signals on the DSP56374 pins and how these signals are grouped into interfaces.

Section 3—Memory Configuration

- Describes the DSP56374 memory spaces, RAM and ROM configuration, memory configurations and their bit settings and

memory maps.

Section 4—Core Configuration

- Describes the registers used to configure the DSP56300 core when programming the DSP56374, in particular the interrupt

vector locations and the operation of the interrupt priority registers. Explains the operating modes and how they affect the processor’s program and data memories.

Section 5—Phase-Locked Loop (PLL) and Clock Generator

- Describes the DSP56374 PLL and clock generator capability and the programming model for the PLL (operation, registers and

control).

Section 6—General Purpose Input/Output (GPIO)

- Describes the DSP56374 GPIO capability and the programming model for the GPIO signals (operation, registers and control).

Section 7—Serial Host Interface (SHI)

- Describes the serial input/output interface providing a path for communication and program/coefficient data transfers between

the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices.

Section 8—Enhanced Serial Audio Interface (ESAI)

- Describes one of the full-duplex serial port for serial communication with a variety of serial devices.

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor i

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Preface

Section 9—Triple Timer Module (TEC)

- Describes the Architecture, Programming model, and operating modes of three identical timer devices available for use as

internals or event counters. Describes the operation of the Triple Timer and its many functions.

Section 10—Watchdog Timer Module (WDT)

- Describes the Architecture, Programming model and, operating modes of the watchdog timer.

Appendix A—Bootstrap Program

- Lists the bootstrap code used for the DSP56374.

Appendix B—Equates

- Lists equates for the DSP56374.

Appendix C—Programming Reference

- Lists peripheral addresses, interrupt addresses and interrupt priorities for the DSP56374. Contains programming sheets listing

the contents of the major DSP56374 registers for programmer reference.

Appendix D—BSDL

- Provides the BSDL data for the DSP56374.

DSP56374 Users Guide, Rev. 1.2

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Page 19

Revision History

The following table summarizes revisions to this document.

Revision Date Location Comments

1.1 Nov 2004 Previous release.

1.2 July 2007 Chapter 6 • In section 6.2.2 Port G Signals and Registers, corrected register acronyms (PCRG, PRRG, PDRG).

• In Table 6-2, corrected statements for ERI1, ETI0, ERI0.

Appendix B • In Equates statements, corrected addresses for PDRG, PRRG, PCRG

on page B-4.

Appendix C • In Figure C-24, corrected register addresses for PCRG, PRRG, PDRG.

• In Table C-2, corrected register acronyms for PCRG, PRRG, PDRG.

Preface

DSP56374 Users Guide, Rev. 1.2

Freescale Semiconductor iii

Page 20

Manual Conventions

The following conventions are used in this manual:

• Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB).

• When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer’s sheets to see the exact location of bits within a register.

• When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its value is 0.

• The word “assert” means that a high true (active high) signal is pulled high to V low to ground. The word “de-assert” means that a high true signal is pulled low to ground or that a low true signal is pulled high to

High True/Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

PIN False De-asserted V

PIN True Asserted V

PIN False De-asserted Ground

Note:

1. PIN is a generic term for any pin on the chip.

2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low).

3. V

is an acceptable high voltage level. See the appropriate data sheet for the range of

acceptable high voltage levels (typically a TTL logic high).

True Asserted Ground

or that a low true (active low) signal is pulled

• Pins or signals that are asserted low (made active when pulled to ground)

- In text, have an overbar (e.g., RESET

is asserted low).

- In code examples, have a tilde in front of their names. In example below, line 3 refers to the SS0 pin (shown as ~SS0).

• Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g., SDO0–SDO5).

• Code examples are displayed in a monospaced font, as shown below:

Example Sample Code Listing

BSET #$000007,X:PCRC; Configure:PC7 line 1

BCLR #$000007,X:PRRC; Configure:PDC7 line 2

; SDO4/SDI1 as PC7 for GPIO Input line 3

• Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFFFF is the X memory address for the core interrupt priority register (IPR-C).

• The word “reset” is used in four different contexts in this manual:

- the reset signal, written as “RESET

- the reset instruction, written as “RESET,”

- the reset operating state, written as “Reset,” and

- the reset function, written as “reset.”

,”

DSP56374 Users Guide, Rev. 1.2

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Page 21

Introduction

Chapter 1 DSP56374 Overview

1.1 Introduction

The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. This manual describes the DSP56374 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules.

The DSP56374 is a member of the Symphony™ family of programmable CMOS DSPs and is built on the high performance, single-clock-per-cycle DSP56300 core. The DSP56374 is provided in either an 80-pin or 52-pin package. This design provides a two-fold performance increase over Freescale’s (formerly Motorola) popular DSP56000 Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing and direct memory access (DMA). Changes in core functionality specific to the DSP56374 are also described in this manual. See Figure 1-1 for the block diagram of the DSP56374.

GPIO

Address

Generation

Unit

DMA Unit

Data

Bus

ESAI

SHI

Interface Interface

Six Channel

Bootstrap

ROM

Internal

Switch

Clock

Gen.

PLL

12*15*

ESAI_1

Interface

PIO_EB

Program Interrupt

Controller

Watch

Triple

dog

Timer

Peripheral

Expansion Area

Program

Decode

Controller

Program

RAM

ROM

20k

Program Address

Generator

Memory Expansion Area

X Data

RAM

PM_EB

DSP56300

DDB YDB XDB PDB GDB

ROM

YAB XAB PAB

DAB

24-Bit

Core

24 Two 56-bit Accumulators

XM_EB

Data ALU

24+56→56-bit MAC

56-bit Barrel Shifter

Y Data

RAM

ROM

YM_EB

Power Mgmt.

JTAG

OnCE

XTAL

EXTAL

RESET

PINIT/NMI

MODA/IRQA/GPIO MODB/IRQB/GPIO MODC/IRQC/GPIO

MODD/IRQD/GPIO

* ESAI_1 and dedicated GPIO pins are not available in the 52-pin package.

Figure 1-1. DSP56374 Block Diagram

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DSP56300 Core Description

1.2 DSP56300 Core Description

The DSP56374 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides several times the performance of Freescale’s (formerly Motorola’s) popular DSP56000 core family while retaining code compatibility.

The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products. For a description of the DSP56300 core, see Section 1.4, DSP56300 Core Functional Blocks. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA).

The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements such as memories and peripherals. Note that new modules may be added to the library to meet customer specifications in future DSP56300 products. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. Refer to Chapter 3, Memory Configuration.

Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral features are described in this manual.

• DSP56300 modular chassis

- 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25V.

- Object Code Compatible with the 56k core.

- Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16-bit arithmatic support.

- Program Control with position independent code support.

- Six-channel DMA controller.

- Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4),

Output divide factor (1, 2 or 4) and a power-saving clock divider (2

- Internal address tracing support and OnCE for Hardware/Software debugging.

- JTAG port, supporting boundary scan, compliant to IEEE 1149.1.

- Very low-power CMOS design, fully static design with operating frequencies down to DC.

- STOP and WAIT low-power standby modes.

• On-chip Memory Configuration

- 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM.

- 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM.

- 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism.

- 6Kx24 Bit Program RAM.

- Various memory switches are available. See memory table below.

Table 1-1. DSP56374 Memory Switch Configurations

: i = 0 to 7) to reduce clock noise

Bit Settings Memory Sizes (24-bit words)

MSW1 MSW0 MS

Prog RAM

X Data

RAM

Y Data

RAM

Prog ROM

X Data

ROM

Y Data

ROM

X X 0 6k6k6k20k4k4k

0 0 1 2k 10k 6k 20k 4k 4k

0 1 1 4k 8k 6k 20k 4k 4k

1 0 1 8k 4k 6k 20k 4k 4k

1 1 1 10K 4k 4k 20k 4k 4k

• Peripheral modules

- Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I

S, Sony, AC97,

network and other programmable protocols.

- Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I

AC97, network and other programmable protocols. Note: Available in the 80-pin package only

- Serial Host Interface (SHI): SPI and I

C protocols, 10-word receive FIFO, support for 8-, 16- and 24-bit words. Three noise

reduction filter modes.

- Triple Timer module (TEC).

- Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the 80-pin

package and 20 pins on the 52-pin package.

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DSP56374 Audio Processor Architecture

- Hardware Watchdog Timer

• Packages

- 80-pin and 52-pin plastic LQFP packages.

1.3 DSP56374 Audio Processor Architecture

This section defines the DSP56374 audio processor architecture. The audio processor is composed of the following units:

• The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, DMA Controller, Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale (formerly Motorola) publication DSP56300FM/AD.

• Phased Lock Loop and Clock Generator

• Memory modules.

• Peripheral modules. The peripheral modules are defined in the following sections.

Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the memory mode of the chip. See

Table 1-1 and Section 1.4.7, On-Chip Memory for more details about memory size.

1.4 DSP56300 Core Functional Blocks

The DSP56300 core provides the following functional blocks:

• Data arithmetic logic unit (Data ALU)

• Address generation unit (AGU)

• Program control unit (PCU)

• DMA controller (with six channels)

• Instruction patch controller

• PLL-based clock oscillator

•OnCE module

•Memory

In addition, the DSP56374 provides a set of on-chip peripherals, described in Section 1.5, Peripheral Overview.

1.4.1 Data ALU

The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of the Data ALU are as follows:

• Fully pipelined 24-bit × 24-bit parallel multiplier-accumulator (MAC)

• Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

• Conditional ALU instructions

• 24-bit or 16-bit arithmetic support under software control.

• Four 24-bit input general purpose registers: X1, X0, Y1 and Y0

• Six Data ALU registers (A2, A1, A0, B2, B1 and B0) that are concatenated into two general purpose, 56-bit accumulators (A and B), accumulator shifters

• Two data bus shifter/limiter circuits

1.4.1.1 Data ALU Registers

The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator.

All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty (i.e., without a pipeline stall).

1.4.1.2 Multiplier-Accumulator (MAC)

The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands. In the case of arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following formExtension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).

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DSP56300 Core Functional Blocks

The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between two’s-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified.

1.4.2 Address Generation Unit (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead.

The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register and a modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset adder).

A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided.

The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.

Each Address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU.

1.4.3 Program Control Unit (PCU)

The PCU performs instruction prefetch, instruction decoding, hardware DO loop control and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of the following three hardware blocks:

• Program decode controller (PDC)

• Program address generator (PAG)

• Program interrupt controller

The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack and loop control. The Program interrupt controller arbitrates among all interrupt requests (internal interrupts, as well as the five external requests: IRQA, IRQB, IRQC, IRQD and NMI) and generates the appropriate interrupt vector address.

PCU features include the following:

• Position independent code support

• Addressing modes optimized for DSP applications (including immediate offsets)

• On-chip memory-expandable hardware stack

• Nested hardware DO loops

• Fast auto-return interrupts

The PCU implements its functions using the following registers:

• PC—program counter register

•SR—Status register

• LA—loop address register

• LC—loop counter register

• VBA—vector base address register

• SZ—stack size register

• SP—stack pointer

• OMR—operating mode register

• SC—stack counter register

The PCU also includes a hardware system stack (SS).

1.4.4 Internal Buses

To provide data exchange between blocks, the following buses are implemented:

• Peripheral input/output expansion bus (PIO_EB) to peripherals

• Program memory expansion bus (PM_EB) to program memory

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DSP56300 Core Functional Blocks

• X memory expansion bus (XM_EB) to X memory

• Y memory expansion bus (YM_EB) to Y memory

• Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU and PCU, as well as the memory-mapped registers in the peripherals

• DMA data bus (DDB) for carrying DMA data between memories and/or peripherals

• DMA address bus (DAB) for carrying DMA addresses to memories and peripherals

• Program Data Bus (PDB) for carrying program data throughout the core

• X memory Data Bus (XDB) for carrying X data throughout the core

• Y memory Data Bus (YDB) for carrying Y data throughout the core

• Program address bus (PAB) for carrying program memory addresses throughout the core

• X memory address bus (XAB) for carrying X memory addresses throughout the core

• Y memory address bus (YAB) for carrying Y memory addresses throughout the core

All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1.

1.4.5 Direct Memory Access (DMA)

The DMA block has the following features:

• Six DMA channels supporting internal and external accesses

• One-, two- and three-dimensional transfers (including circular buffering)

• End-of-block-transfer interrupts

• Triggering from interrupt lines and all peripherals

1.4.6 PLL-based Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, skew elimination and the clock generator (CLKGEN), which performs low-power division and clock pulse generation. PLL-based clocking:

• Allows change of low-power divide factor (DF) without loss of lock

• Provides output clock with skew elimination

• Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise

The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input. This feature offers two immediate benefits:

• A lower frequency clock input reduces the overall electromagnetic interference generated by a system.

• The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system.

1.4.7 On-Chip Memory

The memory space of the DSP56300 core is partitioned into program memory space, X data memory space and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can not be expanded off-chip.

There is an instruction patch module. The patch module is used to patch program ROM. The memory switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM).

There are on-chip ROMs for program and bootstrap memory (20k x 24-bit), X ROM (4k x 24-bit) and Y ROM(4k x 24-bit).

More information on the internal memory is provided in Chapter 3, Memory Configuration.

1.4.8 Off-Chip Memory Expansion

Memory cannot be expanded off-chip. There is no external memory bus.

1.4.9 Power Requirements

To prevent a high current condition and damage to the DSP upon power up, the 3.3V source must be applied ahead of the 1.25V source as shown below.

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Peripheral Overview

1.25V

3.3V

To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is recommended to be made between the DSP56374 3.3V and 1.25V power pins.

3.3V

External Schottky

1.25V

Diode

1.5 Peripheral Overview

The DSP56374 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56374 provides the following peripherals:

• As many as 47 dedicated or user-configurable general purpose input/output (GPIO) signals on the 80-pin package and 20 dedicated or user-configurable GPIO on the 52-pin package.

• Timer/event counter (TEC) module, containing three independent timers

• Memory switch mode in on-chip memory

• Four external interrupt/mode control lines and one external non-maskable interrupt line

• Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master or slave, using the I AC97, network and other programmable protocols

• A second enhanced serial audio interface (ESAI_1) with up to four receivers and up to six transmitters, master or slave, using the

S, Sony, AC97, network and other programmable protocols. Note: only available on the 80-pin package.

• Serial host interface (SHI) using SPI and I and 24-bit words

• A Hardware Watchdog Timer.

C protocols, with multi-master capability, 10-word receive FIFO and support for 8-, 16-

1.5.1 General Purpose Input/Output (GPIO)

The 80-pin DSP56374 provides 15 dedicated GPIO and 29 programmable pins that can operate either as GPIO pins or peripheral pins (ESAI, ESAI_1 and TEC). The four MOD pins, as well as the SHI HREQ pin, can also be utilized as GPIO. The ESAI and ESAI_1 pins are configured as GPIO after hardware reset. Register-programming techniques for all GPIO functionality among these interfaces are very similar and are described in the following sections.

1.5.2 Triple Timer (TEC)

This section describes a peripheral module composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each one having its own register set.

Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Each of the three timers can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) occurred. Each of the three timers connect to the external world through bidirectional pins (TIO0, TIO1 and TIO2). When a TIO pin is configured as input, the timer functions as an external event counter or can measure external pulse width/signal period. When a

S, Sony,

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Peripheral Overview

TIO pin is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When a TIO pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer to Chapter 9, Triple Timer Module.

1.5.3 Enhanced Serial Audio Interface (ESAI)

The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors and peripherals that implement the Freescale (formerly Motorola) SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to Chapter 8, Enhanced Serial Audio Interface (ESAI).

1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1)

The ESAI_1 is a second ESAI interface. The ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1, refer to

Chapter 9, Triple Timer Module.

1.5.5 Serial Host Interface (SHI)

The SHI is a serial input/output interface providing a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Freescale (formerly Motorola) serial peripheral interface (SPI) bus and the Philips inter-integrated-circuit control (I device. To minimize DSP overhead, the SHI supports single-, double- and triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception. For more information on the SHI, refer to Chapter 7, Serial Host Interface.

C) bus. The SHI supports either the SPI or I2C bus protocol, as required, from a slave or a single-master

1.5.6 Watchdog timer (WDT)

The watchdog timer (WDT) is a 16-bit timer used to help software recover from runaway code. The timer is a free-running down-counter used to generate a reset on underflow. Software must periodically service the watchdog timer in order to restart the count down. For more information on the WDT, refer to Chapter 10, Watchdog

Tim er Mod u le.

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DSP56374 Overview

Notes

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Signal Groupings

Chapter 2 Signal/Connection Descriptions

2.1 Signal Groupings

The input and output signals of the DSP56374 are organized into functional groups, which are listed in Ta ble 2 -1.

The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. Resistor values for pins with pull up or pull down resistors may vary with lot and will be between 40k ohms and 65k ohms.

Table 2-1. DSP56374 Functional Signal Groupings

Power (V

Functional Group

)11Tab le 2 -2

Number of

Signals

Detailed

Description

Ground (GND) 9 Table 2-3

Scan Pins 1 Ta ble 2 -4.

Clock and PLL 3 Table 2 -5.

Interrupt and mode control Port H

SHI Port H

ESAI Port C

ESAI_1 Port E

Dedicated GPIO Port G

5 Ta ble 2 -6.

5 Ta ble 2 -7.

12 Tab le 2- 8.

12 Tab le 2- 9.

15 Table 2-10.

Timer 3 Table 2-11.

JTAG/OnCE Port 4 Table 2-12.

Note:

1. Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.

2. Port G signals are the dedicated GPIO port signals.

3. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

4. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

Note: Pins are not 5 V. tolerant unless noted.

2.2 Power

Table 2-2. Power Inputs

Power Name Description

PLLA_VDD

PLLP_VDD(1) PLL Power— The voltage (3.3 V) should be well-regulated, and the input should be provided with

PLLD_VDD

Freescale Semiconductor 2-1

(1) PLL Power— The voltage (3.3 V) should be well-regulated, and the input should be provided with

an extremely low impedance path to the 3.3 V

power rail. The user must provide adequate

external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter as shown in Figure 2-1. and Figure 2-2. below. See the DSP56374 technical data sheet for additional details.

an extremely low impedance path to the 3.3 V

power rail. The user must provide adequate

external decoupling capacitors between PLLP_VDD and PLLP_GND.

(1) PLL Power— The voltage (1.25 V) should be well-regulated, and the input should be provided

with an extremely low impedance path to the 1.25 V

power rail. The user must provide

adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.

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Power

Table 2-2. Power Inputs

Power Name Description

CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated, and the input should be provided

with an extremely low impedance path to the 1.25 V adequate external decoupling capacitors.

power rail. The user must provide

IO_VDD (80-pin 4) (52-pin 3)

SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide adequate external decoupling capacitors.

80 IO_Gnd

79 SDO5_PC 6

78 SDO4_PC 7

77 FSR_1_P E1

76 FSR_PC1

75 FST_PC4

74 FST_1_P E4

73 GPIO_PG1 4

72 Core_Vdd

71 Core_Gnd

70 SCKR_1_P E0

69 SCKR_PC 0

68 SCKT_PC 3

67 SCKT_1_PE3

66 HCKR_1_PE2

65 HCKR_PC2

64 HCKT_PC5

63 HCKT_1_PE5

62 SCAN

IO_Vdd 1

MODA_IRQA_PH0 2

MODB_IRQB_PH1 3

GPIO_PG13 4

GPIO_PG12 5

MODC_IRQC_PH2 6

MODD_IRQD_PH3 7

GPIO_PG11 8

Core_Vdd 9

Core_Gnd 10

GPIO_PG10 11

GPIO_PG9 12

HREQ_PH4 13

SS_HA2 14

SCK_SCL 15

MISO_SDA 16

MOSI_HA0 17

GPIO_PG8 18

GPIO_PG7 19

IO_Gnd 20

61 IO_Vdd

60 SDO5_1_PE 6

59 SDO4_1_PE 7

58 SDO3_PC8

57 SDO2_PC9

56 SDO1_PC1 0

55 SDO0_PC1 1

54 SDO3_1_PE 8

53 SDO2_1_PE 9

52 Core_Vdd

51 Core_Gnd

50 SDO1_1_PE 10

49 SDO0_1_PE 11

48 PINIT_NMI

47 IO_Vdd

46 XTAL

45 EXTAL

44 PLLD_Vdd

43 PLLD_Gnd

42 PLLP_Gnd

41 PLLP_Vd d

IO_Vdd 21

GPIO_PG6 22

GPIO_PG5 23

TDO 24

TDI 25

TMS 26

TCK 27

GPIO_PG4 28

TIO00 29

WDT/TIO1 30

PLOCK/TIO2 31

Core_Vdd 32

Core_Gnd 33

GPIO_PG3 34

RESET_B 35

GPIO_PG2 36

GPIO_PG1 37

GPIO_PG0 38

PLLA_Vdd 39

PLLA_Gnd 40

1.25 V

Filter

3.3 V

Figure 2-1. 80-pin Vdd Connections

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Ground

52 IO_Gnd

51 SDO5_PC6

50 SDO4_PC7

49 FSR_PC1

48 FST_PC4

47 Core_V dd

46 Core_Gnd

45 SCKR_PC0

44 SCKT_PC3

43 HCKR_PC2

42 HCKT_PC5

41 SCAN

40 IO_Vdd

3.3 V

2.3 Ground

IO_Vdd 1

MODA_IRQA_PH0 2

MODB_IRQB_PH1 3

MODC_IRQC_PH2 4

MODD_IRQD_PH3 5

Core_Vdd 6

Core_Gnd 7

HREQ_PH4 8

SS_HA2 9

SCK_SCL 10

MISO_SDA 11

MOSI_HA0 12

IO_Gnd 13

39 SDO3_PC8

38 SDO2_PC9

37 SDO1_PC10

36 SDO0_PC11

35 Core_V dd

34 Core_Gnd

33 PINIT_NMI

32 XTAL

31 EXTAL

30 PLLD_Vdd

29 PLLD_Gnd

28 PLLP_Gnd

27 PLLP_Vdd

IO_Vdd 14

TDO 15

TDI 16

TMS 17

TCK 18

TIO00 19

WDT/TIO1 20

PLOCK/TIO2 21

Core_Vdd 22

Core_Gnd 23

RESET_B 24

PLLA_Vdd 25

PLLA_Gnd 26

Filter

Figure 2-2. 52-pin Vdd Connections

Table 2-3. Grounds

1.25 V

Ground Name Description

PLLA_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.

PLLP_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.

PLLD_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.

CORE_GND(4) Core Ground—The Core ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

IO_GND(2) SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,

ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

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SCAN

2.4 SCAN

Table 2-4. SCAN signals

Signal

Name

SCAN Input Input SCAN—Manufacturing test pin. This pin must be connected to ground.

Type

State during

Reset

Signal Description

This pin has an internal pull-down resistor.

2.5 Clock and PLL

Table 2-5. Clock and PLL Signals

Signal

Name

EXTAL Input Input External Clock / Crystal Input—An external clock source must be

XTAL Output Chip Driven Crystal Output—Connects the internal Crystal Oscillator output to an

PINIT/NMI

Type

Input Input PLL Initial/Non-maskable Interrupt—During assertion of RESET, the value

State during

Reset

Signal Description

connected to EXTAL in order to supply the clock to the internal clock generator and PLL.

external crystal. If an external clock is used, leave XTAL unconnected.

of PINIT/NMI register, determining whether the PLL is enabled or disabled. After RESET de-assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered non-maskable interrupt (NMI) request internally synchronized to the internal system clock.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

is written into the PLL Enable (PEN) bit of the PLL control

2.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is de-asserted, these inputs are hardware interrupt request lines.

Table 2-6. Interrupt and Mode Control

Signal Name Type

MODA/IRQA

PH0 Input, Output,

Input MODA

Disconnected

State during

Reset

Input

Signal Description

Mode Select A/External Interrupt Request A—MODA/IRQA is an

active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET and the MODA/IRQA state.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

Port H0—When the MODA/IRQA is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

selects the initial chip operating mode during hardware reset

signal is de-asserted. If the processor is in the stop standby state

pin is pulled to GND, the processor will exit the stop

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Table 2-6. Interrupt and Mode Control (continued)

Interrupt and Mode Control

Signal Name Type

State during

Reset

MODB/IRQB Input MODB

Input

PH1 Input, Output,

Disconnected

MODC/IRQC

Input MODC

Input

Signal Description

Mode Select B/External Interrupt Request B—MODB/IRQB is an

active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

Port H1—When the MODB/IRQB is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC

selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

PH2 Input, Output,

Port H2—When the MODC/IRQC is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

Disconnected

MODD/IRQD

Input MODD

Input

Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

PH3 Input, output,

Port H3—When the MODD/IRQD is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

disconnected

RESET Input Input Reset—RESET

chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET

This pin has an internal pull-up resistor. This input is 5 V tolerant.

is an active-low, Schmitt-trigger input. When asserted, the

signal is de-asserted,

is being asserted.

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Serial Host Interface

2.7 Serial Host Interface

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.

Table 2-7. Serial Host Interface Signals

Signal

Name

Signal Type

State during

Reset

Signal Description

SCK Input or Output Tri-stated SPI Serial Clock—The SCK signal is an output when the SPI is configured

as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS

) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol.

SCL Input or Output I

C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C

mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected

through an external pull-up resistor according to the I2C

to V

specifications.

This signal is tri-stated during hardware, software, and individual reset. This pin has an internal pull-up resistor. This input is 5 V tolerant.

MISO Input or Output Tri-stated SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO

is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS

is de-asserted. An external pull-up resistor is not

required for SPI operation.

SDA Input or

Open-drain

Output

C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input

when receiving and an open-drain output when transmitting. SDA should be connected to VDD through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

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Table 2-7. Serial Host Interface Signals (continued)

Serial Host Interface

Signal

Name

Signal Type

State during

Reset

Signal Description

MOSI Input or Output Tri-stated SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI

is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode.

HA0 Input I

C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the I signal is used to form the slave device address. HA0 is ignored when configured for the I

C mode. When configured for I2C slave mode, the HA0

C master mode.

This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

Input Ignored Input SPI Slave Select—This signal is an active low Schmitt-trigger input when

configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept de-asserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged.

is de-asserted, the SHI ignores SCK clocks and keeps the MISO

If SS output signal in the high-impedance state.

HA2 Input I

C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the I HA2 signal is used to form the slave device address. HA2 is ignored in the

C master mode.

C mode. When configured for the I2C Slave mode, the

HREQ

PH4

Input or Output

Input, Output,

Disconnected

This pin has an internal pull-up resistor. This input is 5 V tolerant.

Tri-stated Host Request—This signal is an active low Schmitt-trigger input when

configured for the master mode but an active low output when configured for the slave mode.

When configured for the slave mode, HREQ

is asserted to indicate that the SHI is ready for the next data word transfer and de-asserted at the first clock pulse of the new data word transfer. When configured for the master mode,

is an input. When asserted by the external slave device, it will trigger

HREQ the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This pin can also be programmed as GPIO.

Port H4—When HREQ

is configured as GPIO, this signal is individually

programmable as input, output, or internally disconnected.

This pin has an internal pull-up resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface

2.8 Enhanced Serial Audio Interface

Table 2-8. Enhanced Serial Audio Interface Signals

Signal Name Signal Type

HCKR Input or Output GPIO

PC2 Input, Output, or

Disconnected

HCKT Input or Output GPIO

PC5 Input, Output, or

Disconnected

State during

Disconnected

Reset

Signal Description

High Frequency Clock for Receiver—When

programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock.

Port C2—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-up resistor. This input is 5 V tolerant.

High Frequency Clock for Transmitter—When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock.

Port C5—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-up resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface

Table 2-8. Enhanced Serial Audio Interface Signals (continued)

Signal Name Signal Type

FSR Input or Output GPIO

PC1 Input, Output, or

Disconnected

State during

Reset

Disconnected

Signal Description

Frame Sync for Receiver—This is the receiver frame sync

input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

Port C1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

FST Input or Output GPIO

Disconnected

PC4 Input, Output, or

Disconnected

Frame Sync for Transmitter—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

Port C4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface

Table 2-8. Enhanced Serial Audio Interface Signals (continued)

Signal Name Signal Type

State during

SCKR Input or Output GPIO

Disconnected

PC0 Input, Output, or

Disconnected

Reset

Signal Description

Receiver Serial Clock—SCKR provides the receiver serial

bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

Port C0—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SCKT Input or Output GPIO

Disconnected

Transmitter Serial Clock—This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode.

PC3 Input, Output, or

Disconnected

Port C3—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO5 Output GPIO

Disconnected

Serial Data Output 5—When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register.

SDI0 Input Serial Data Input 0—When programmed as a receiver,

SDI0 is used to receive serial data into the RX0 serial receive shift register.

PC6 Input, Output, or

Disconnected

Port C6—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface

Table 2-8. Enhanced Serial Audio Interface Signals (continued)

Signal Name Signal Type

SDO4 Output GPIO

State during

Reset

Disconnected

Signal Description

Serial Data Output 4—When programmed as a

transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register.

SDI1 Input Serial Data Input 1—When programmed as a receiver,

SDI1 is used to receive serial data into the RX1 serial receive shift register.

PC7 Input,

Output, or

Disconnected

Port C7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO3 Output GPIO

Disconnected

Serial Data Output 3—When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register.

SDI2 Input Serial Data Input 2—When programmed as a receiver,

SDI2 is used to receive serial data into the RX2 serial receive shift register.

PC8 Input, Output, or

Disconnected

Port C8—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO2 Output GPIO

Disconnected

Serial Data Output 2—When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register

SDI3 Input Serial Data Input 3—When programmed as a receiver,

SDI3 is used to receive serial data into the RX3 serial receive shift register.

PC9 Input,Ooutput,

or Disconnected

Port C9—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO1 Output GPIO

Disconnected

PC10 Input, Output, or

Disconnected

Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial transmit shift register.

Port C10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface_1

Table 2-8. Enhanced Serial Audio Interface Signals (continued)

Signal Name Signal Type

SDO0 Output GPIO

PC11 Input, Output, or

Disconnected

State during

Reset

Disconnected

Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial transmit shift register.

Port C11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

2.9 Enhanced Serial Audio Interface_1

Table 2-9. Enhanced Serial Audio Interface_1 Signals

Signal Name Signal Type

HCKR_1 Input or Output GPIO

State during

Reset

Disconnected

High Frequency Clock for Receiver—When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock.

Signal Description

PE2 Input, Output, or

Disconnected

HCKT_1 Input or Output GPIO

Disconnected

PE5 Input, Output, or

Disconnected

Port E2—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

High Frequency Clock for Transmitter—When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock.

Port E5—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface_1

Table 2-9. Enhanced Serial Audio Interface_1 Signals (continued)

Signal Name Signal Type

State during

FSR_1 Input or Output GPIO

Disconnected

PE1 Input, Output, or

Disconnected

Reset

Signal Description

Frame Sync for Receiver_1—This is the receiver frame

sync input/output signal. In the asynchronous mode (SYN=0), the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR_1 register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR_1 register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode.

Port E1—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant

FST_1 Input or Output GPIO

Disconnected

PE4 Input, Output, or

Disconnected

Frame Sync for Transmitter_1—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST_1 is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI_1 transmit clock control register (TCCR_1).

Port E4—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

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Enhanced Serial Audio Interface_1

Table 2-9. Enhanced Serial Audio Interface_1 Signals (continued)

Signal Name Signal Type

State during

SCKR_1 Input or Output GPIO

Disconnected

PE0 Input, Output, or

Disconnected

Reset

Signal Description

Receiver Serial Clock_1—SCKR_1 provides the receiver

serial bit clock for the ESAI_1. The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR_1 register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR_1 register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode.

Port E0—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant

SCKT_1 Input or Output GPIO

Disconnected

Transmitter Serial Clock_1—This signal provides the serial bit rate clock for the ESAI_1. SCKT_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode.

PE3 Input, Output, or

Disconnected

Port E3—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant

SDO5_1 Output GPIO

Disconnected

Serial Data Output 5_1—When programmed as a transmitter, SDO5_1 is used to transmit data from the TX5 serial transmit shift register.

SDI0_1 Input Serial Data Input 0_1—When programmed as a receiver,

SDI0_1 is used to receive serial data into the RX0 serial receive shift register.

PE6 Input, Output, or

Disconnected

Port E6—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant

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Enhanced Serial Audio Interface_1

Table 2-9. Enhanced Serial Audio Interface_1 Signals (continued)

Signal Name Signal Type

SDO4_1 Output GPIO

State during

Reset

Disconnected

Signal Description

Serial Data Output 4_1—When programmed as a

transmitter, SDO4_1 is used to transmit data from the TX4 serial transmit shift register.

SDI1_1 Input Serial Data Input 1_1—When programmed as a receiver,

SDI1_1 is used to receive serial data into the RX1 serial receive shift register.

PE7 Input, Output, or

Disconnected

Port E7—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO3_1 Output GPIO

Disconnected

Serial Data Output 3—When programmed as a transmitter, SDO3_1 is used to transmit data from the TX3 serial transmit shift register.

SDI2_1 Input Serial Data Input 2—When programmed as a receiver,

SDI2_1 is used to receive serial data into the RX2 serial receive shift register.

PE8 Input, Output, or

Disconnected

Port E8—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO2_1 Output GPIO

Disconnected

Serial Data Output 2—When programmed as a transmitter, SDO2_1 is used to transmit data from the TX2 serial transmit shift register.

SDI3_1 Input Serial Data Input 3—When programmed as a receiver,

SDI3_1 is used to receive serial data into the RX3 serial receive shift register.

PE9 Input, Output, or

Disconnected

Port E9—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

SDO1_1 Output GPIO

Disconnected

PE10 Input, Output, or

Disconnected

Serial Data Output 1—SDO1_1 is used to transmit data from the TX1 serial transmit shift register.

Port E10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

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Dedicated GPIO - Port G

Table 2-9. Enhanced Serial Audio Interface_1 Signals (continued)

Signal Name Signal Type

SDO0_1 Output GPIO

PE11 Input, Output, or

Disconnected

State during

Disconnected

2.10 Dedicated GPIO - Port G

Table 2-10. Dedicated GPIO - Port G Signals

Signal

Name

PG0 Input, Output, or

PG1 Input, Output, or

Type

Disconnected

State During

Reset

GPIO

Disconnected

GPIO

Disconnected

Reset

Signal Description

Serial Data Output 0—SDO0_1 is used to transmit data

from the TX0 serial transmit shift register.

Port E11—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant.

Signal Description

Port G0—This signal is individually programmable as input,

output, or internally disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G1—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

PG2 Input, Output, or

Disconnected

PG3 Input, Output, or

Disconnected

PG4 Input, Output, or

Disconnected

PG5 Input, Output, or

Disconnected

PG6 Input, Output, or

Disconnected

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

Port G2—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G3—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G4—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G5—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G6—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

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Table 2-10. Dedicated GPIO - Port G Signals (continued)

Dedicated GPIO - Port G

Signal

Name

Type

PG7 Input, Output, or

Disconnected

PG8 Input, Output, or

Disconnected

PG9 Input, Output, or

Disconnected

PG10 Input, Output, or

Disconnected

PG11 Input, Output, or

Disconnected

State During

Reset

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

Signal Description

Port G7—This signal is individually programmable as input,

output, or internally disconnected. This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G8—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G9—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G10—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G11—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

PG12 Input, Output, or

Disconnected

PG13 Input, Output, or

Disconnected

PG14 Input, Output, or

Disconnected

GPIO

Disconnected

GPIO

Disconnected

GPIO

Disconnected

Port G12—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G13—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Port G14—This signal is individually programmable as input, output, or internally disconnected.

This pin has an internal pull-down resistor. This input is 5 V tolerant

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Timer

2.11 Timer

Table 2-11. Timer Signal

Signal

Name

TIO0 Input or

TIO1 Input or

WDT Output WDT—When this pin is configured as a hardware watchdog timer pin,

Type

Output

State during

Reset

GPIO Input Timer 0 Input/Output—When timer 0 functions as an external event

counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Watchdog Timer

Output

Timer 1 Input/Output—When timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output.

The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1control/status register (TCSR1). If TIO1 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input.

this signal is asserted low when the hardware watchdog timer counts down to zero.

This pin has an internal pull-down resistor. This input is 5 V tolerant

Signal Description

TIO2 Input or

Output

PLOCK Output PLOCK—When this pin is configured as a PLL lock pin, this signal is

PLOCK Output Timer 2 Input/Output—When timer 2 functions as an external event

counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output.

The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer control/status register (TCSR2). If TIO2 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input.

asserted high when the on-chip PLL enabled and locked and de-asserted when the PLL enabled and unlocked. This pin is also asserted high when the PLL is disabled.

This pin has an internal pull-down resistor. This input is 5 V tolerant

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2.12 JTAG/OnCE Interface

JTAG/OnCE Interface

Table 2-12. JTAG/OnCE Interface

Signal

Name

TCK Input Input Test Clock—TCK is a test clock input signal used to synchronize the JTAG

TDI Input Input Test Data Input—TDI is a test data serial input signal used for test

TDO Output Tri-stated Test Data Output—TDO is a test data serial output signal used for test

TMS Input Input Test Mode Select—TMS is an input signal used to sequence the test

Signal

Type

State during

Reset

Signal Description

test logic. This pin has an internal pull-up resistor. This input is 5 V tolerant.

instructions and data. TDI is sampled on the rising edge of TCK. This pin has an internal pull-up resistor. This input is 5 V tolerant.

instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK.

controller’s state machine. TMS is sampled on the rising edge of TCK. This pin has an internal pull-up resistor. This input is 5 V tolerant.

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Signal/Connection Descriptions

Notes

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Data and Program Memory Maps

Chapter 3 Memory Configuration

3.1 Data and Program Memory Maps

The DSP56374 provides 18k words of RAM divided between three memory spaces (X, Y, and P). The default memory allocation and memory block sizes are as follows (See Figure 3-1):

• Program RAM - 6k words (3 - 2k blocks) in the lowest memory addresses between $000000 - $0007FF.

• XRAM - 4k words (1 - 4k block) in the lowest memory addresses between $000000 - $000FFF and 2k words (1 - 2k block) in the memory addresses between $001000 - $0017FF.

• YRAM - 2k words (1 - 2k block) in the lowest memory addresses between $000000 - $0007FF and 4k words (4 - 1k blocks) in the memory addresses between $000800 - $0017FF.

The DSP56374 provides 28k words of ROM divided between three memory spaces (X, Y, and P). The memory allocations are as follows:

• Program ROM - 20k words.

• XROM - 4k words.

• YROM - 4k words.

The on-chip memory configuration of the DSP56374 is affected by the state of the MSW0, MSW1 and MS (Memory Switch) control bits in the OMR register in the Status Register. The internal data and program memory configurations are shown in Tabl e 3-7. The address ranges for the internal memory are shown in Table 3-2. The memory maps for each memory configuration are shown in Figure 3-1 to Figure 3-5.

Table 3-1. Internal Memory Configuration

Program RAM Program ROM X Data RAM X Data ROM Y Data RAM Y Data ROM

6k (3-2k blocks) $000000-$017FF

20k (20k blocks) 6k (1-4k block)

$000000-$00FFF (1- 2k block) $001000-$017FF

4k (4k blocks) 6k (1-2k block)

$000000-$007FF (4- 1k block) $000800-$017FF

4k (4k blocks)

Table 3-2. Internal Memory Locations

Program RAM Program ROM X Data RAM X Data ROM Y Data RAM Y Data ROM

6k Words $000000 -

$0017FF

20k Words $FF0000 -

$FF4FFF

6k Words $000000 - $0017FF

4k Words $004000 -

$004FFF

6k Words $000000 $0017FF

4k Words $004000 -

$004FFF

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Data and Program Memory Maps

Program X Data Y Data

$FFFFFF

Internal I/O

$FFFFFF

Internal I/O

$FFFF80

$FF5000

Program

ROM

Internal

Reserved

External

4k ROM

6k RAM

$FF01B0

$FF0000

$001800

$000000

Bootstrap Code

External

6k RAM

$FF0000

$005000

$001800 $000000

Internal

Reserved

External

4k ROM

6k RAM

$FF0000

$005000

$004000$004000 $001800 $000000

Figure 3-1. Default Memory Map (MS 0)

Table 3-3. Internal Memory Locations

Program RAM Program ROM X Data RAM X Data ROM Y Data RAM Y Data ROM

10k Words $000000 -

$0027FF

20k Words $FF0000 -

$FF4FFF

4k Words $000000 - $000FFF

4k Words $004000 -

$004FFF

4k Words $000000 $000FFF

4k Words $004000 -

$004FFF

$FFFFFF

$FF5000

$FF01B0 $FF0000

$002800

$000000

Program X Data Y Data

$FFFFFF

$FFFF80

Internal I/O

$FFFFFF

$FFFF80

Internal I/O

Program

ROM

Internal

Reserved

External

4k ROM

Bootstrap Code

External

$FF0000

$005000

Reserved

$FF0000

External

$005000

4k ROM

$004000$004000

10k RAM

$001000 $000000

4k RAM

$001000 $000000

4k RAM

Figure 3-2. Memory Map (MS 1, MSW(1-0) 11)

Internal

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Data and Program Memory Maps

Table 3-4. Internal Memory Locations

Program RAM Program ROM X Data RAM X Data ROM Y Data RAM Y Data ROM

8k Words $000000 -

$001FFF

20k Words $FF0000 -

$FF4FFF

$FFFFFF

$FF5000

$FF01B0 $FF0000

$002000

$000000

4k Words $000000 - $000FFF

4k Words $004000 -

$004FFF

6k Words $000000 $0017FF

Program X Data Y Data

$FFFFFF

Internal I/O

$FFFF80

$FFFFFF

$FFFF80

Internal I/O

Program

ROM

Internal

Reserved

Bootstrap Code

External

$FF0000

$005000

Reserved

$FF0000

External

$005000

4k ROM

$004000$004000

8k RAM

$001000 $000000

4k RAM

$001800 $000000

4k Words $004000 -

$004FFF

Internal

External

4k ROM

6k RAM

Figure 3-3. Memory Map (MS 1, MSW(1-0) 10)

Table 3-5. Internal Memory Locations

Program RAM Program ROM X Data RAM X Data ROM Y Data RAM Y Data ROM

4k Words $000000 -

$000FFF

20k Words $FF0000 -

$FF4FFF

8k Words $000000 - $001FFF

4k Words $004000 -

$004FFF

6k Words $000000 $0017FF

4k Words $004000 -

$004FFF

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Data and Program Memory Maps

Program X Data Y Data

$FFFFFF

Internal I/O

$FFFFFF

Internal I/O

$FFFF80

$FF5000

Program

ROM

Internal

Reserved

External

4k ROM

6k RAM

$FF01B0

$FF0000

$001000

$000000

Bootstrap Code

External

4k RAM

$FF0000

$005000

$004000 $002000

$000000

Internal

Reserved

External

4k ROM

8k RAM

$FF0000

$005000

$004000 $001800

$000000

Figure 3-4. Memory Map (MS 1, MSW(1-0) 01)

Table 3-6. Internal Memory Locations

Program RAM Program ROM X Data RAM X Data ROM Y Data RAM Y Data ROM

2k Words $000000 -

$0007FF

20k Words $FF0000 -

$FF4FFF

10k Words $000000 - $0027FF

4k Words $004000 -

$004FFF

6k Words $000000 $0017FF

4k Words $004000 -

$004FFF

$FFFFFF

$FF5000

$FF01B0

$FF0000

$000800

$000000

Program X Data Y Data

$FFFFFF

Internal I/O

$FFFF80

$FFFFFF

$FFFF80

Internal I/O

Program

ROM

Internal

Reserved

Bootstrap Code

External

$FF0000

$005000

Reserved

$FF0000

External

$005000

4k ROM

$004000$004000

2k RAM

$002800 $000000

10k RAM

$001800 $000000

Figure 3-5. Memory Map (MS 1, MSW(1-0) 00)

DSP56374 Users Guide, Rev. 1.2

Internal

External

4k ROM

6k RAM

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Data and Program Memory Maps

3.1.1 Reserved Memory Spaces

The reserved memory spaces should not be accessed by the user. They are reserved for future expansion.

3.1.2 Bootstrap CODE

The bootstrap ROM is factory-programmed to perform the bootstrap operation following hardware reset. The Bootstrap source code is available in Appendix A, Bootstrap Source Code.

3.1.3 Dynamic Memory Configuration Switching

The internal memory configuration is altered by re-mapping RAM blocks from Y and X data memory into program memory space. The contents of the switched RAM blocks are preserved.

The memory can be dynamically switched from one configuration to another by changing the MS, MSW0 or MSW1 bits in OMR. The address ranges that are directly affected by the switch operation are specified in Table 3 - 2. The memory switch can be accomplished provided that the affected address ranges are not being accessed during the instruction cycle in which the switch operation takes place. Accordingly, the following condition must be observed for trouble-free dynamic switching:

NOTE

No accesses (including instruction fetches) to or from the affected address ranges in program and data memories are allowed during the switch cycle.

The switch cycle actually occurs 3 instruction cycles after the instruction that modifies the MS, MSW0 or MSW1bits.

Any sequence that complies with the switch condition is valid. For example, if the program flow executes in the address range that is not affected by the switch, the switch condition can be met very easily. In this case a switch can be accomplished by just changing the MS, MSW0 or MSW1 bits in OMR in the regular program flow, assuming no accesses to the affected address ranges of the data memory occur up to 3 instructions after the instruction that changes the OMR bit. Special care should be taken in relation to the interrupt vector routines since an interrupt could cause the DSP to fetch instructions out of sequence and might violate the switch condition.

Special attention should be given when running a memory switch routine using the OnCE™ port. Running the switch routine in Trace mode, for example, can cause the switch to complete after the MS bit change while the DSP is in Debug mode. As a result, subsequent instructions might be fetched according to the new memory configuration (after the switch) and, thus, might execute improperly.

Table 3-7. Internal Memory Configurations

Bit Settings Memory Sizes (24-bit words)

MSW1 MSW0 MS

XX06k6K620k4k4k

0 0 1 2k 10k 6k 20k 4k 4k

0 1 1 4k 8k 6k 20k 4k 4k

1 0 1 8k 4k 6k 20k 4k 4k

1 1 1 10k 4k 4k 20k 4k 4k

Prog RAM

X Data

RAM

Y Data

RAM

Prog

ROM

X Data

ROM

Y Data

ROM

3.1.4 External Memory Support

The DSP56374 is not capable of directly accessing external memory.

3.1.5 DMA and Memory

Memory on the DSP56374 consists of 4 - 1k-word blocks, 5 - 2k-word blocks, and 1 - 4k word block (see Figure 3-1). It is important to understand that the DMA is designed for operation on 1k-word blocks. The implications are as follows:

When DMA accesses any of the 4 - 1k-word blocks (i.e., y:$000800..$0017FF), hardware will prevent potential loss of DMA accesses if the core happens to simultaneously access the same 1k-word block. If software does not prevent core/DMA access to the same 1k word block, hardware will delay the DMA access until the core has completed its operation. The DMA will continue to operate the expected access.

When DMA accesses any of the 5 - 2k-word blocks or 1 - 4k word block software should be written to prevent contention where hardware protection is not available. Protection for Core/DMA contention is only provided in a 2k or 4k word block if both the core and DMA are

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Memory Patch Module

accessing the same 1k section of the block. However, if DMA access is executed to a 2k or 4k word block while the core simultaneously accesses the same block, hardware protection may not be provided and DMA operation may not be performed during the core access. The DMA access may be missed. Software should be written to prevent contention where hardware protection is not available.

3.1.6 Memory BLOCKS

The RAM memory is implemented with a combination of 1k-word, 2k-words and 4k-word RAM memory blocks. The finer granularity of the 1k-word memory blocks permit DMA and core accesses to the same memory spaces with less possibility of contention. See Section 3.1.5,

DMA and Memory.

3.2 Memory Patch Module

The patch module provides a means to replace instructions in program ROM with instructions written into the patch module’s instruction registers. A program ROM instruction is replaced by storing the ROM memory address in a patch module address register. The new instruction is to be loaded into the corresponding patch module instruction register.

After reset (either hard reset or the RESET instruction), none of the patch module address registers are enabled for patching. The patch module address registers are initially cleared. Whenever an address register is written to, that address register (and corresponding instruction register) is enabled for patching.

Once an address register is enabled for patching, whenever there is an internal program read (by the core) of that address, the contents of the corresponding instruction register are substituted onto the Program Read Data bus, instead of the actual contents of memory at that address.

The Patch module has no effect on DMA accesses, or writes to program memory. It also has no effect if the address programmed is considered an external address.

Note that writing to an instruction register does not enable it for patching. Only writing to an address register enables patching. Therefore, if not used for patching, the instruction registers can be used as general purpose registers.

Patching example:

Begin

bset #23,omr ; enable patch

; initialize patch module registers ; addresses first

move #$fff000,r1 movep r1,y:$ffffa0 ;load ROM address $fff000 into patch address 0 move #$fff001,r1 movep r1,y:$ffffa1 ;load ROM address $fff001 into patch address 1 move #$fff003,r1 movep r1,y:$ffffa2 ;load ROM address $fff003 into patch address 2

; instructions

move #patch_pattern,r2 movep p:(r2)+,y:$ffffa8 ;load instruction #1 into patch instruction 0 movep p:(r2)+,y:$ffffa9 ;load instruction #2 into patch instruction 1 movep p:(r2)+,y:$ffffaa ;load instruction #3 into patch instruction 2 jmp program ;start running program

org P:$800

patch_pattern

bset #0,a ;instruction #1 = bset #0,a bset #1,a ;instruction #2 = bset #1,a bset #2,a ;instruction #3 = bset #2,a

Anytime the program control unit fetches an instruction from P:$fff000, instruction 1 (bset #0,a) will be fetched in place of the instruction stored in ROM location P:$fff000. Also, when the program control unit fetches an instruction from P:$fff001, instruction 2 (bset #1,a) will be fetched instead. Also, when the program control unit fetches an instruction from P:$fff003, instruction 3 (bset #2,a) will be fetched instead.

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Internal I/O Memory Map

3.3 Internal I/O Memory Map

The DSP56374 on-chip peripheral modules have their register files programmed to the addresses in the internal X-I/O memory range (the top 128 locations of the X data memory space) and internal Y-I/O memory range (48 locations of the Y data memory space) as shown in Tabl e

C-1 and Table C-2.

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Internal I/O Memory Map

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Introduction

Chapter 4 Core Configuration

4.1 Introduction

This chapter contains DSP56300 core configuration information details specific to the SCF5250. These include the following:

• Operating modes

• Bootstrap program

• Interrupt sources and priorities

• DMA request sources

•OMR

• PLL control register

•JTAG

For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual (DSP56300FM/AD).

4.2 Operating Mode Register (OMR)

The contents of the Operating Mode Register (OMR) are shown in Table 4 -1. Refer to the DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale (formerly Motorola) publication DSP56300FM/AD for a description of the OMR bits.

Table 4-1. Operating Mode Register (OMR)

SCS EOM COM

23222120191817161514131211109 8 7 6543210

MSW 1 : 0 SEN WRP EOV EUN XYS CDP1:0 MS SD MD MC MB MA

MSW1 - Memory Switch Mode 1 MS - Master Memory Switch Mode

MSW0 - Memory Switch Mode 0 SD - Stop Delay

SEN - Stack Extension Enable

WRP - Extended Stack Wrap Flag MD - Operating Mode D

EOV - Extended Stack Overflow Flag MC - Operating Mode C

EUN - Extended Stack Underflow Flag CDP1 - Core-DMA Priority 1 MB - Operating Mode B

XYS - Stack Extension Space Select CDP0 - Core-DMA Priority 0 MA - Operating Mode A

- Reserved bit. Read as zero, should be written with zero for future compatibility

4.2.1 RESERVED - Bits 4, 5, 10 - 15 and 23

These bits are reserved. They are read as zero and should be written with zero for future compatibility.

4.3 Operating Modes

The operating modes are defined as shown in Table 4-2. The operating modes are latched from MODA, MODB, MODC and MODD pins during reset. Each operating mode is briefly described below. The operation of all modes is defined by the Bootstrap ROM source code in

Appendix A, Bootstrap Source Code.

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Operating Modes

Table 4-2. DSP56374 Operating Modes

Mode MODD MODC MODB MODA

Reset

Vector

Description

0 0 0 0 0 $000000 Reserved

1 0 0 0 1 $FF0000 Reserved

2 0 0 1 0 $FF0000 Jump to PROM starting address (slave SPI mode)

3 0 0 1 1 $FF0000 Reserved

4 0 1 0 0 $FF0000 Reserved

5 0 1 0 1 $FF0000 Bootstrap from SHI (slave SPI mode)

6 0 1 1 0 $FF0000 Bootstrap from SHI (slave I

C mode)

(HCKFR=1, 100ns filter enabled)

7 0 1 1 1 $FF0000 Bootstrap from SHI (slave I

C mode)

(HCKFR=0)

8 1 0 0 0 $004000 Reserved

9 1 0 0 1 $FF0000 Bootstrap from SHI (Serial I

C EEPROM mode)

(HCKFR=1, 100ns filter enabled)

A 1 0 1 0 $FF0000 Reserved

B 1 0 1 1 $FF0000 Bootstrap from SHI (Serial SPI EEPROM mode)

C 1 1 0 0 $FF0000 Bootstrap from GPIO (Serial SPI EEPROM mode)

D 1 1 0 1 $FF0000 Jump to PROM at default HLX (slave SPI)

E 1 1 1 0 $FF0000 Jump to PROM starting address (slave I

(HCKFR=0)

F 1 1 1 1 $FF0000 Jump to PROM starting address (slave I

(HCKFR=1, 100ns filter enabled)

Table 4-3. DSP56374 Mode Descriptions

Mode 0 Reserved

Mode 1 Reserved

Mode 2 The DSP starts fetching instructions from the starting address of the on-chip Program ROM. SHI operates in

SPI slave mode.

Mode 3 Reserved

Mode 4 Reserved

Mode 5 In this mode, the internal PRAM is loaded from the Serial Host Interface (SHI). The SHI operates in the SPI

slave mode, with 24-bit word width.The bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying the address to start loading the program words and then a 24-bit word for each program word to be loaded. The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program execution starts from the same address where loading started.

Mode 6 Same as Mode 5 except SHI interface operates in the I

filter enabled.

Mode 7 Same as Mode 5 except SHI interface operates in the I

C slave mode with HCKFR set to 1 and the 100ns

C slave mode with HCKFR set to 0.

Mode 8 Reserved

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Interrupt Priority Registers

Table 4-3. DSP56374 Mode Descriptions

Mode 9 In this mode, the internal memory (PRAM, XRAM, or YRAM) is loaded from an external serial EPROM in I

mode withthe 100ns filter enabled. Supports ST M24256 and Atmel AT24C256.

Mode A Reserved

Mode B In this mode, the internal memory (PRAM, XRAM, or YRAM) is loaded from an external serial EPROM in SPI

mode. Supports ST M95256 and Atmel AT25256.

Mode C In this mode, the internal memory (PRAM, XRAM, or YRAM) is loaded from an external serial EPROM in SPI

mode via GPIO pins (PH0 - Chip Select, PH1 - Data in, PH2 - Data out and PH3 - clock). Supports ST M95256 and Atmel AT25256.

Mode D The DSP starts operation of the default HLX. SHI operates in SPI slave mode.

Mode E The DSP starts fetching instructions from the starting address of the on-chip Program ROM. SHI operates in

in I2C mode. No filter in enabled.

Mode F The DSP starts fetching instructions from the starting address of the on-chip Program ROM. SHI operates in

See Appendix A, Bootstrap Source Code for details on using this boot mode.

C mode with the 100ns filter enabled.

in I

4.4 Interrupt Priority Registers

There are two interrupt priority registers in the DSP56374:

1. IPR-C is dedicated for DSP56300 Core interrupt sources.

2. IPR-P is dedicated for DSP56374 Peripheral interrupt sources.

The interrupt priority registers are shown in Table 4- 1 and Table 4-2. The Interrupt Priority Level bits are defined in Table 4-4. The interrupt vectors are shown in Table C -3 and the interrupt priorities are shown in Tab l e C - 4.

Table 4-4. Interrupt Priority Level Bits

IPL bits

Interrupts

Enabled

00 No —

01 Yes 0

10 Yes 1

11 Yes 2

Interrupt

Priority

LevelxxL1 xxL0

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DMA Request Sources

91011

ESL10

TAL1

ESL11

Reserved bit. Read as zero, should be written with zero for future compatibility.

TAL0

21 20 19 18 17 16 15 14 13 12

Figure 4-1. Interrupt Priority Register P

91011

IDL2 IDL1 IDL0

01234567

ESL0ESL1SHL0SHL1

ESAI IPL SHI IPL RESERVED RESERVED

TRIPLE TIMER IPL

ESAI_1 IPL

RESERVED

01234567

IAL0IAL1IAL2IBL0IBL1IBL2ICL0ICL1ICL2

IRQA IPL

IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL

IRQD mode

21 20 19 18 17 16 15 14 13 12

D2L0D2L1D3L0D3L1D4L0D4L1D5L0D5L1

D0L0D0L1D1L0D1L1

DMA0 IPL DMA1 IPL

DMA2 IPL DMA3 IPL DMA4 IPL

DMA5 IPL

Figure 4-2. Interrupt Priority Register C

4.5 DMA Request Sources

The DMA Request Source bits (DRS4-DRS0 bits in the DMA Control/Status registers) encode the source of DMA requests used to trigger the DMA transfers. The DMA request sources may be the internal peripherals or external devices requesting service through the IRQA IRQC

and IRQD pins. The DMA Request Sources are shown in Table 4-5.

, IRQB,

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Table 4-5. DMA Request Sources

PLL Initialization

DMA Request Source Bits

DRS4...DRS0

00000 External (IRQA

00001 External (IRQB pin)

00010 External (IRQC pin)

00011 External (IRQD pin)

00100 Transfer Done from DMA channel 0

00101 Transfer Done from DMA channel 1

00110 Transfer Done from DMA channel 2

00111 Transfer Done from DMA channel 3

01000 Transfer Done from DMA channel 4

01001 Transfer Done from DMA channel 5

01010 Reserved

01011 ESAI Receive Data (RDF=1)

01100 ESAI Transmit Data (TDE=1)

01101 SHI HTX Empty

01110 SHI FIFO Not Empty

Requesting Device

pin)

01111 SHI FIFO Full

10000 Reserved

10001 Reserved

10010 TIMER0 (TCF=1)

10011 TIMER1 (TCF=1)

10100 TIMER2 (TCF=1)

10101 ESAI_1 Receive Data (RDF=1)

10110 ESAI_1 Transmit Data (TDE=1)

10 111 Reserved

11000 Reserved

1100 1-11111 Re served

4.6 PLL Initialization

The following figure displays the PLL control register (PCTL). This register is used to control the PLL operation including its multiplication/divide factors and enabling bits.

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Device Identification (ID) Register

11109876543210

X:$FFFFFD

DF2 DF1 DF0 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0

23 22 21 20 19 18 17 16 15 14 13 12

PLKM PD4 PD3 PD2 PD1 PD0 OD1 OD0 PEN PSTP

Figure 4-3. PCTL Register

4.6.1 PLL Pre-Divider Factor (PD0-PD4)

The DSP56374 PLL Pre-Divider factor is set to 4 during hardware reset, i.e., the Pre-Divider Factor Bits PD0-PD4 in the PLL Control Register (PCTL) are set to $4.

4.6.2 PLL Multiplication Factor (MF0-MF7)

The DSP56374 PLL multiplication factor is set to 29 during hardware reset, i.e., the Multiplication Factor Bits MF0-MF7 in the PLL Control Register (PCTL) are set to $1D.

4.6.3 PLL Feedback Multiplier (OD1)

The DSP56374 PLL Feedback Multiplier is set to 2 during hardware reset, i.e., OD1 is cleared ($0) in the PLL Control Register (PCTL).

4.6.4 PLL Output Divide Factor (OD0-OD1)

The DSP56374 PLL Output Divider factor is set to 2 during hardware reset, i.e., OD1 is cleared ($0) and OD0 is set ($1) in the PLL Control Register (PCTL).

4.6.5 PLL Divider Factor (DF0-DF2)

The DSP56374 PLL Divider factor is set to 1 during hardware reset, i.e., the Divider Factor Bits DF0-DF2 in the PLL Control Register (PCTL) are set to $0.

4.6.6 PLL LOCK MUX (PLKM)

The PLOCK Mux (PLKM) bit is a read/write bit that controls the operation of the PLOCK/TIO2 pin. When PLKM is set, the PLOCK/TIO2 pin operates as the PLL lock indicator (PLOCK). When the PLKM bit is cleared, the PLOCK/TIO2 pin operates as the TIO2 pin.

Note: The PLKM bit is set during hardware reset.

4.7 Device Identification (ID) Register

The Device Identification Register (IDR) is a 24 bit read only factory programmed register used to identify the different DSP56300 core-based family members located at x:$FFFFF5. This register specifies the derivative number and revision number. This information may be used in testing or by software. Table 4-6 shows the ID register configuration.

Table 4-6. Identification Register Configuration

23 16 15 12 11 0

Reserved Revision Number Derivative Number

$00 $0 $374

4.8 JTAG Identification (ID) Register

The JTAG Identification (ID) Register is a 32 bit, read only thought JTAG, factory programmed register used to distinguish the component on a board according to the IEEE 1149.1 standard. Table 4-7 shows the JTAG ID register configuration.

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JTAG Identification (ID) Register

Table 4-7. JTAG Identification Register Configuration

31 28 27 22 21 12 11 1 0

Version

Information

Customer Part

Number

Sequence

Number

Manufacturer

Identity

0000 000111 0000000011 00000001110 1

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Introduction

Chapter 5 PLL and Clock generator

5.1 Introduction

The DSP56374 core features a Phase Locked Loop (PLL) clock generator in its central processing module. The PLL operation is controlled by a PLL control register (PCTL). The PLL allows the processor to operate at a high internal clock frequency derived from a low-frequency clock input, a feature that offers two immediate benefits. First, the lower frequency clock input can reduce the overall electromagnetic interference generated by a system. Second, the ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. Figure 5-1 shows the two main blocks of the clock generator in the DSP56374 core:

• Phase Locked Loop (PLL) that performs:

- Clock input division

- Frequency multiplication

- Skew elimination

• Clock Generator (

- Low-power division

- Internal clock generation

Note that the core is stopped when the PLL is enabled, but unlocked.

CLKGEN) that performs:

EXTAL

Ext.

Clock

Predivider

extal

-----------------PDF

PDF = 1 to 31

PLL

PLL Loop

Frequency

Multiplication

extal MF()FM()

----------------------------------------------PDF

FM = 2 or 4

MF = 1 to 255

Divide by OD

1, 2 or 4

PLL

Out

PEN = 0

PEN = 1

CLKGEN

Low-Power

Divider

PLLOut

---------------------DF

DF = 20 to 2

Core Clock

)

osc

Figure 5-1. PLL Clock Generator Block Diagram

5.2 PLL and Clock Signals

The PLL and clock pin configuration for the DSP56374 is available in the device-specific technical data sheet. The following pins are dedicated to the PLL and clock operation:

PINIT: During assertion of hardware reset, the value of the PINIT input pin is written into the PCTL PLL Enable (PEN) bit. After

• hardware reset is de-asserted, the PLL ignores the

• EXTAL: An external clock is required to drive the DSP. The external clock is input via the EXTAL pin passing the clock through the PLL and Clock generator for optional frequency multiplication.

• XTAL: An external crystal between the values of 10MHz and 25MHz can be driven from the XTAL pin. The external crystal should be connected to both the XTAL and EXTAL pins to provide the source clock frequency.

• TIO2/PLOCK: PLOCK is muxed with the TIO2 pin and operates as a PLOCK pin upon exiting reset. When the PLKM bit is cleared, the TIO2/PLOCK pin operates as a timer pin. When the PLKM bit is set, the TIO2/PLOCK pin operates as a PLOCK pin. When operating as PLOCK, the following applies: The PLOCK pin is asserted (high) when the PLL is enabled and has locked on the proper phase and frequency of EXTAL (maximum lock time is 0.5ms). The PLOCK output is de-asserted (low) if the PLL is enabled and is not locked on the proper phase and frequency. PLOCK is asserted if the PLL is disabled. PLOCK should be a reliable indicator of the PLL lock state after exiting the hardware reset state.

PINIT pin. The default PCTL setting when PINIT is asserted is: $04601D.

5.3 PLL Block

This section describes the PLL control components and operation. Figure 5-2 shows the PLL block diagram.

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PLL Block

EXTAL

Predivider

1 to 31

PD[4–0]

Fref

MF[7–0]

Phase

Detector

Charge Pump

Loop Filter

Frequency

Divider 1 to 255

and

VCO

NOTE:

VCO Out

OD1

Divide

by 2

Divide

by 2

PLL Out

OD0

5 MHz < Fref < 20 MHz

PEN

Clock

Generator

300 MHz < VCO Out< 600 MHz

Figure 5-2. PLL Block Diagram

5.3.1 Frequency Predivider

Clock input frequency division is accomplished by means of a frequency predivider of the input frequency. The pre-divider ranges from 1 to

31. The pre-divider must never be set to zero. The output frequency of the pre-divider (Fref) must be between 5 MHz and 20 MHz to guarantee proper operation.

5.3.2 Phase Detector and Charge Pump Loop Filter

The Phase Detector detects any phase difference between the external clock (EXTAL) and the phase of the clock generated by the PLL. At the point where there is negligible phase difference and the frequency of the two inputs is identical, the PLL is in the locked state. The charge pump loop filter receives signals from the Phase Detector and either increases or decreases the voltage applied to the VCO based on the Phase Detector signals.

5.3.3 Voltage Controlled Oscillator (VCO)

The Voltage Controlled Oscillator (VCO) can oscillate at frequencies from 300 MHz to 600 MHz. The VCO output frequency is determined by the voltage applied to it by the charge pump that corresponds to the PLL input frequency (Fref). The VCO frequency is a function of the input frequency as well as the multiplication components (Multiplication factor (MF) and Feedback Multiplier (FM)).

5.3.4 PLL DividerS

As part of the PLL output stage, there are two divide modules (each is a divide by 2 module) controlled by the OD0 and OD1 bits in the PCTL register. These two bits control the PLL feedback multiplier (FM) as well as the output divide factor (OD). The feedback multiplier is a frequency divider implemented in the PLL feedback loop thus operating as a PLL multiplier and can be programmed to multiply the VCO output frequency up by a factor of 2 or 4. See Table 5-1. The number of divide modules in the PLL loop is determined by the OD1 bit. When one divide module is in the feedback loop (OD1=0) FM = 2. When two divide modules are in the feedback loop (OD1=1) FM = 4. Note that when OD1 is changed, the PLL will lose lock.

Table 5-1. Feedback Multiplier (FM); FM = 2(1 + OD1)

OD1 FM

The output divide factor (OD) determines the PLL output frequency as a function of the VCO frequency. The PLL output frequency can be programmed to be the VCO frequency divided by 2 or 4. The output divide factor (OD) is determined by both the OD1 and OD0 bits. See

Table 5-2. Note that the PLL will not lose lock when OD0 is changed since OD0 is not in the PLL loop. The PLL will lose lock, however,

when OD1 is changed. Also, note that the output divide factor (OD) should not be programmed such that both OD0 = 0 and OD1 = 0.

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PLL Operation

Table 5-2. Output Divide Factor (OD)

OD0 OD1 OD

00Reserved

01Div by 2

10Div by 2

11Div by 4

5.3.5 PLL Multiplication Factor (MF)

The Frequency Divider portion of the PLL feedback loop divides the VCO output by an additional programmable 8-bit value before entering the Phase Detector. The net result is an additional multiplication of the input clock by the programmed value. This is called the Multiplication Factor (MF) and is programmed using the PCTL[MF] bits. The Multiplication Factor can range from 1 to 255. The MF must never be set to zero and although there are 8 bits for programming the MF ranging from 1 to 255, due to VCO output frequency and Fref frequency limitations, the MF should always be programmed between the values of 4 and 60.

5.4 PLL Operation

The PLL uses two major control elements in its circuitry:

• Clock input division

• Frequency multiplication

The following describes the operation of the PLL and its components.

5.4.1 EXTAL Clock Input Division

The PLL can divide the input frequency (EXTAL) by any integer between 1 and 31. The Division Factor can be modified by changing the value of the PCTL Predivider Factor (PDF) bits (PD[4–0]). The output frequency of the predivider is called the reference frequency (Fref) and is determined using the following formula:

Fref

Fextal

----------------

; 5 MHz < Fref < 20 MHz

PDF

5.4.2 PLL Frequency Multiplication

The PLL can multiply the reference frequency by using the MF and FM multipliers in the PLL feedback loop. This is performed by writing to the Multiplication Factor (MF[7–0]) bits and the OD[1] bit (affecting the Feedback Multiplier) in the PCTL register. The output frequency of the VCO (that is, VCO Out as shown in Figure 5-2) is computed using the following formula:

VCO Out

Fextal x MF

---------------------------------------------

XFM

; 300

MHz

< VCO < 600

MHz

PDF

The following figures display how the OD1 bit affects the PLL loop and the VCO output. Figure 5-3 shows that when OD1 is clear, only one divider module is in the PLL loop, effectively applying a feedback multiplier of 2. Figure 5-4 shows that when OD1 is set, two divider modules are in the PLL loop, effectively applying a feedback multiplier of 4. Note that, since OD1 is in the closed loop of the PLL, changes to OD1 do cause a loss of lock condition.

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PLL Operation

EXTAL

Predivider

1 to 31

PD[4–0]

Fref

MF[7–0]

Phase

Detector

Charge Pump

Loop Filter

Frequency

Divider 1 to 255

and

VCO

NOTE:

VCO Out

5 MHz < Fref < 20 MHz 300 MHz < VCO Out< 600 MHz

Figure 5-3. PLL Loop with One Divider when OD1=0 (FM = 2)

Predivider

1 to 31

PD[4–0]

Fref

MF[7–0]

Phase

Detector

Charge Pump

Loop Filter

Frequency

Divider

1 to 255

and

VCO

VCO Out

OD1

Divide

by 2

Divide

by 2

OD1

Divide

by 2

Divide

by 2

PEN

Clock

Generator

Clock

Generator

PLL Out

OD0

NOTE:

5 MHz < Fref < 20 MHz 300 MHz < VCO Out< 600 MHz

Figure 5-4. PLL Loop with Two Dividers when OD1=1 (FM = 4)

5.4.3 PLL Output Frequency (PLL Out)

The PLL Output frequency is a function of the VCO frequency as follows:

PLL Out

VCO

------------ OD

As described above the Output Divider Factor is 2 or 4 as determined by the OD1 and OD0 bits. Note that since OD0 is not in the closed loop of the PLL, changes to OD0 do not cause a loss of lock condition. The figures below show how the OD [1-0] bits affect the PLL Output frequency by dividing the VCO Output. Figure 5-5 displays how setting OD1 = 0 and OD0 = 1 divides the VCO output to generate a PLL Output that is VCO Out/2

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PLL Operation

EXTAL

Predivider

1 to 31

PD[4–0]

Fref

MF[7–0]

Phase

Detector

Charge Pump

Loop Filter

Frequency

Divider

1 to 255

and

VCO

NOTE:

VCO Out

OD1

Divide

by 2

Divide

by 2

PLL Out

OD0

5 MHz < Fref < 20 MHz

PEN

300 MHz < VCO Out< 600 MHz

Figure 5-5. PLL Out = VCO Out/2 [OD1 = 0, OD0 = 1]

Figure 5-6 displays how setting OD1 = 1 and OD0 = 0 divides the VCO output to generate a PLL Output that is VCO Out/2.

EXTAL

Predivider

1 to 31

PD[4–0]

Fref

MF[7–0]

Phase

Detector

Charge Pump

Loop Filter

Frequency

Divider

1 to 255

and

VCO

VCO Out

OD1

Divide

by 2

Divide

by 2

OD0

PLL Out

PEN

Clock

Generator

Clock

Generator

NOTE:

5 MHz < Fref < 20 MHz 300 MHz < VCO Out< 600 MHz

Figure 5-6. PLL Out = VCO Out/2 [OD1 = 1, OD0 = 0]

Figure 5-7 displays how setting OD1 = 1 and OD0 = 1 divides the VCO output to generate a PLL Output that is VCO Out/4.

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Clock Generator

EXTAL

Predivider

1 to 31

PD[4–0]

Fref

MF[7–0]

Phase

Detector

Charge Pump

Loop Filter

Frequency

Divider 1 to 255

and

VCO

NOTE:

VCO Out

OD1

Divide

by 2

Divide

by 2

PLL Out

OD0

5 MHz < Fref < 20 MHz

PEN

Clock

Generator

300 MHz < VCO Out< 600 MHz

Figure 5-7. PLL Out = VCO Out/4 [OD1 = 1, OD0 = 1]

5.5 Clock Generator

Figure 5-8 shows the Clock Generator block diagram. The components of the Clock Generator are described in the following sections.

EXTAL

PLL OUT

Low-Power

Divider

to 2

DF[2–0]

2-Phase Core

Clock

)

OSC

PEN = 1 PEN = 0

Figure 5-8. CLKGEN Block Diagram

5.5.1 Low-Power Divider (LPD)

The Clock Generator section consists of a divider connected to the output of the PLL. The Low-Power Divider (LPD) divides the output frequency of the PLL by any power of 2 from 2 PLL Control Register (PCTL) Division Factor bits DF[2–0]. Since the LPD is not in the closed loop of the PLL, changes to the DF [2-0] bits do not cause a loss of lock condition. The result is a significant power savings when the LPD operates in low-power consumption modes as the device is not involved in intensive calculations. When the device is required to exit a low-power mode, it can immediately do so with no time needed for clock recovery or PLL lock.

to 27. The Division Factor (DF) of the LPD can be modified by changing the value of the

5.6 Operating Frequency (Fosc)

The output stage of the Clock Generator generates the clock signals to the core and the device peripherals. The input source to the clock generator is selected between:

EXTAL (PEN = 0, PLL disabled), which generates the device frequency from the EXTAL clock directly.

•

Fosc

Fextal

--------------- DF

• PLL Output (PEN = 1, PLL enabled), which generates a device frequency defined by the following formula:

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PLL Programming Model

Fosc

Fextal xMF

-------------------------------------------

XFM

PDF x DF x OD

where:

• MF is the Multiplication Factor defined by MF[7–0]

• PDF is the Predivider Factor defined by PD[4–0]

• DF is the Division Factor defined by DF[2–0]

• OD is the Output Divide Factor defined by OD[1-0].

• FM is the Feedback Multiplication Factor defined by OD[1]

•F

is the device operating frequency

OSC

is the external EXTAL input

EXTAL

5.7 PLL Programming Model

The PLL clock generator uses a single register, the PCTL Register, for PLL control. The PCTL is an X I/O mapped 24-bit read/write register used to direct the operation of the on-chip PLL.

Figure 5-9 shows the PCTL control bits. The PCTL bits are described in Table 5-3 .

23 22 21 20 19 18 17 16 15 14 13 12

PLKM PD4 PD3 PD2 PD1 PD0 OD1 OD0 PEN PSTP

Reset:

0010001a0

11109876543210

DF2 DF1 DF0 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0

Reset:

00000011101

a The reset value of the PEN bit is based on the value of the PLL PINIT input.

Figure 5-9. PLL Control (PCTL) Register

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PLL Programming Model

Table 5-3. PLL Control (PCTL) Register Bit Definitions

Bit Number Bit Name

21 PLKM $0 PLL LOCK MUX

20–16 PD[4–0] $4 Predivider Factor

Reset Value

Description

NOTE: The PLKM bit is set during hardware reset.

Defines the PDF value that is applied to the input frequency. PDF can be any integer from 1 to 31. The VCO is a function of PDF and oscillates at a frequency defined by the following formula:

Fextal MF FM××()

------------------------------------------------PDF

PDF must be chosen to ensure that Fref lies in a range specified in the device-specific technical data sheet (5 MHz - 20 MHz) and the resulting VCO output frequency lies in the range specified in the device-specific technical data sheet (300 MHz - 600 MHz). Any time a new value is written into the PD[4–0] bits, the PLL loses the lock condition. The PDF bits (PD[4–0]) are set to $4 during hardware reset. The PDF value should never be set to $0.

15–14 OD[1–0] 01 Output Divider Factor and Feedback Multiplier

Defines the OD and FM values that are applied to the output VCO frequency. The VCO oscillates at a frequency defined by the following formula:

Fextal MF FM

-----------------------------------------------

××()

PDF

FM = 2(1 + OD1). OD1 must be chosen to ensure that the resulting VCO output frequency lies in the range specified in the device-specific technical data sheet (300 MHz - 600 MHz). Any time OD1 is changed, the PLL loses the lock condition.

OD1 is initially cleared (0) following reset. OD0 is initially set (1) following reset. Changes to OD0 do not cause the PLL to lose the lock condition. OD0 and OD1 bits together define the output divide factor (OD). The output divide factor divides the VCO output frequency by a factor of 2 or 4 according to Table 5-4.

Table 5-4. Output Divide Factor (OD)

OD0 OD1 OD

00Reserved

01Div by 2

10Div by 2

11Div by 4

Note that OD0 and OD1 should not simultaneously be cleared. The resulting Fosc frequency will exceed the maximum operating frequency when in this case. The PLL Output is defined by the following formula when OD = 1:

VCO Out

-------------------------OD

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PLL Programming Model

Table 5-3. PLL Control (PCTL) Register Bit Definitions (continued)

Bit Number Bit Name

Reset Value

13 PEN a PLL Enable

Enables PLL operation. When PEN is set, the PLL is enabled and the internal clocks are derived from the PLL VCO output. When PEN is cleared, the PLL is disabled and the internal clocks are derived directly from the EXTAL signal. When the PLL is disabled, the VCO stops to minimize power consumption. The PEN bit may be set or cleared by software any time during the device operation. During hardware reset, this bit is set or cleared based on the value of the PLL PINIT input. Note that the core is stopped when the PLL is enabled, but unlocked.

12 PSTP 0 PLL Stop State

Controls PLL and on-chip crystal oscillator behavior during the Stop processing state. When PSTP is set, the PLL remains operating when the chip is in the Stop state. When PSTP is cleared and the device enters the Stop state, the PLL is disabled, to further reduce power consumption. This however results in longer recovery time upon exit from the Stop state. To enable rapid recovery when exiting the Stop state (but at the cost of higher power consumption during the Stop state), PSTP should be set.

PSTP PEN

0 x Disabled Disabled Long Minimal

1 0 Disabled Enabled Short Lower

1 1 Enabled Enabled Short Higher

Description

Operation During Stop State

PLL Oscillator

Recovery Time

From Stop State

Power

Consumption

During Stop

State

10–8 DF[2–0] 0 Division Factor

Define the DF of the low-power divider. These bits specify the DF as a power of two in the range from 20 to 27. Changing the value of the DF[2–0] bits does not cause a loss of lock condition. Whenever possible, changes of the operating frequency of the device (for example, to enter a low-power mode) should be made by changing the value of the DF[2–0] bits rather than changing the MF[7–0] bits.

DF[2–0] DF Value

000 2

001 2

010 2

011 2

100 2

101 2

110 2

111 2

= 1

= 2

= 4

= 8

= 16

= 32

= 64

= 128

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PLL Initialization Procedure

Table 5-3. PLL Control (PCTL) Register Bit Definitions (continued)

Bit Number Bit Name

7–0 MF[7–0] $1D Multiplication Factor

Reset Value

Description

Defines the Multiplication Factor (MF) that is applied to the PLL input frequency. The MF can be any integer from 1 to 255. The VCO oscillates at a frequency defined by the following formula where PDF is the Predivider Division Factor and FM is the Feedback Multiplier:

Fextal MF FM××()

----------------------------------------------PDF

The MF must be chosen to ensure that the resulting VCO output frequency is in the range specified in the device-specific technical data sheet (300 MHz - 600 MHz). Any time a new value is written into the MF[7–0] bits, the PLL loses the lock condition. The Multiplication Factor bits MF[7–0] are set to $1D (29) during hardware reset.

a The reset value of the PEN bit is based on the value of the PLL PINIT input

5.8 PLL Initialization Procedure

The DSP56374 PLL is programmed via the PCTL register. Unlike the DSP56371, the DSP56374 does not require a two step initialization process. However, the DSP56374 PLL is backwards compatible with the DSP56371 and will support the two step initialization process. The following programming example illustrates the initialization process.

PLL Programming Example:

Input Frequency (EXTAL) - 24.576 MHz

Target Operating Frequency - 150 MHz

Program the PLL control register (PCTL) - $23E012.

- This enables the TIO2/PLOCK pin as a PLOCK pin

- This multiplies up the input frequency to a VCO frequency of 589.824 MHz

- The PLL output is VCO / 4 via the output divider to 147.456 MHz

- The Fosc frequency is VCO / 4 via the output divider and low power divider to 147.456 MHz

Note that the default PCTL value is $04601D.

Use Table 5-5 to determine the appropriate PCTL value for generating the maximum operating frequency (Fosc). Locate the maximum Fref value in the table that is larger than the target Fref. Use the corresponding final PCTL value to generate the maximum operating frequency given the target Fref.

Table 5-5. PCTL Value Guide

150 MHz

Maximum Fref

(MHz)

15.00 $2xE01E

2 5.15 $2xE01D

3 5.35 $2xE01C

45.55 $2xE01B

55.75 $2xE01A

66.00 $2xE019

76.25 $2xE018

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Table 5-5. PCTL Value Guide

150 MHz

PLL Programming Examples

Maximum Fref

(MHz)

8 6.521 $2xE017

96.82 $2xE016

10 7.142 $2xE015

11 7.5 $2xE014

12 7.89 $2xE013

13 8.33 $2xE012

14 8.82 $2xE011

15 9.4 $2xE010

16 10 $2xE00F

17 10.7 $2xE00E

18 11.54 $2xE00D

19 12.5 $2xE00C

20 13.636 $2xE00B

21 15 $2xE00A

22 16.666 $2xE009

Final PCTL

23 18.75 $2xE008

Example:

Maximum Operating Frequency = 150 MHz

EXTAL Frequency = 11.2896 MHz

Target Fref = EXTAL / PD (where PD = 2) = 5.6448 MHz

The maximum Fref value that is greater than the Target Fref is #5: 5.75 MHz. The corresponding final PCTL value is $2xE01A. x represents the PLL Pre-Divider (PD) used to determine the target Fref value. In the example the Pre-Divider (PD) = 2. Thus, the PCTL value is $22E01A. The following PLL parameters can be determined from the final PCTL setting.

VCO frequency = 5.6448 MHz *4 * 26 = 589.056 MHz

PLL Output = VCO / 4= 147.264 MHz

Fosc = PLL Output = 147.264 MHz

This represents the maximum operating frequency obtainable with a target Fref frequency of 5.6448 MHz.

5.9 PLL Programming Examples

Table 5-6. PLL Programming Examples

EXTAL

(MHz)

PDF

5 MHz - 20 MHz

Fref

(MHz)

OD1 OD0 FM MF

VCO Output

(MHz)

300 - 600 MHz

PLL

Output

(MHz)

LPD

Fosc

(MHz)

PCTL

27.00 3 9.0 1 1 4 16 576.0 4 144.0 0 144 $23E010

27.0 4 6.75 1 1 4 22 594.0 4 148.5 0 148.5 $24E016

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PLL Programming Examples

Table 5-6. PLL Programming Examples (continued)

EXTAL

(MHz)

27.0 5 5.4 1 1 4 27 583.2 4 145.8 0 145.8 $25E01B

24.576 4 6.144 1 1 4 24 589.824 4 147.456 0 147.456 $24E018

24.576 3 8.192 1 1 4 18 589.824. 4 147.456 0 147.456 $23E012

12.288 1 12.288 1 1 4 12 589.824 4 147.456 0 147.456 $21E00C

12.288 2 6.144 1 1 4 24 589.824 4 147.456 0 147.456 $22E018

11.2896 2 5.6448 1 1 4 26 587.0592 4 146.7648 0 146.764 $22E01A

PDF

Fref

(MHz)

5 MHz - 20 MHz

OD1 OD0 FM MF

VCO Output

(MHz)

300 - 600 MHz

PLL

Output

(MHz)

LPD

Fosc

(MHz)

PCTL

NOTE

The default PLL setting ($04601D) established upon reset when the PINIT pin is pulled high should not be used at or below 150 MHz operation.

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Introduction

Chapter 6 General Purpose Input/Output

6.1 Introduction

The DSP56374 provides up to 47 programmable signals that are dedicated GPIO pins or pins that can operate either as GPIO pins or peripheral pins (ESAI, ESAI_1, and TEC). Up to 20 pins can be programmed as signal or GPIO pins in the 52-pin package. The signals (except for MODA - MODD, and HREQ) are configured as GPIO after hardware reset. The techniques for register programming for all GPIO functionality is very similar between these interfaces. This section describes how signals may be used as GPIO.

6.2 Programming Model

The signals description section of this manual describes the special uses of these signals in detail. There are six groups of these signals which can be controlled separately or as groups:

• Port C: twelve GPIO signals (shared with the ESAI signals).

• Port E: twelve GPIO signals (shared with the ESAI_1 signals) NOTE: 80-pin package only.

• Port G: fifteen GPIO signals (dedicated GPIO signals) NOTE: 80-pin package only.

• Port H: five GPIO signals (shared with the MODA - MODD and HREQ signals).

• Timer: three GPIO signals (shared with the timer/event counter signals).

6.2.1 Port C and E Signals and Registers

Each of the 12 port C signals not used as an ESAI signal can be configured individually as a GPIO signal. The GPIO functionality of port C is controlled by three registers: port C control register (PCRC), port C direction register (PRRC) and port C data register (PDRC). These registers are described in Chapter 8, Enhanced Serial Audio Interface (ESAI).

Each of the 12 port E signals not used as an ESAI_1 signal can be configured individually as a GPIO signal. The GPIO functionality of port E is controlled by three registers: port E control register (PCRE), port E direction register (PRRE) and port E data register (PDRE). These registers are described in Chapter 8, Enhanced Serial Audio Interface (ESAI).

6.2.2 Port G Signals and Registers

Each of the 15 Port G signals can be configured individually as a GPIO signal. This establishes the appropriate wait state setting for correct operation of the interface. The GPIO functionality of Port G is controlled by three registers: Port G control register (PCRG), Port G direction register (PRRG), and Port G data register (PDRG). These registers are described below.

6.2.2.1 Port G Control Register (PCRG)

The read/write 24-bit Port G Control Register (PCRG) in conjunction with the Port G Direction Register (PRRG) controls the functionality of the dedicated GPIO pins. Each of the PG(14:0) bits controls the functionality of the corresponding port pin. See Tabl e 6 -1. for the port-pin configurations. Hardware and software reset clear all PCRG bits.

6.2.2.2 Port G Direction Register (PRRG)

The read/write 24-bit Port G Direction Register (PRRG) in conjunction with the Port G Control Register (PCRG) controls the functionality of the dedicated GPIO pins. Ta ble 6-1. describes the port-pin configurations. Hardware and software reset clear all PRRG bits.

Table 6-1. PCRG and PRRG Bits Functionality

PDG[i] PG[i] Port Pin[i] Function

0 0 Disconnected

0 1 GPIO input

1 0 GPIO output

1 1 Open Drain Output

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11109876543210

Y:$FFFFFA PG11 PG10 PG9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0

23 22 21 20 19 18 17 16 15 14 13 12

PG14 PG13 PG12

Reserved bit - read as zero; should be written with zero for future compatibility.

Figure 6-1. PCRG Register

11109876543 2 1 0

Y:$FFFFF9 PDG11 PDG10 PDG9 PDG8 PDG7 PDG6 PDG5 PDG4 PDG3 PDG2 PDG1 PDG0

23 22 21 20 19 18 17 16 15 14 13 12

PDG14 PDG13 PDG12

Reserved bit - read as zero; should be written with zero for future compatibility.

Figure 6-2. PRRG Register

6.2.2.3 Port G Data Register (PDRG)

The read/write 24-bit Port G Data Register (see Figure 6-3) is used to read or write data to/from the dedicated GPIO pins. Bits PG(14:0) are used to read or write data from/to the corresponding port pins. If a port pin [i] is configured as a GPIO input, the corresponding PG[i] bit reflects the value present on this pin. If a port pin [i] is configured as a GPIO output, the value written into the corresponding PG[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PG[i] bit is not reset and contains undefined data.

The PDG and PG bits should not be set simultaneously.

11109876543210

Y:$FFFFF8 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

23 22 21 20 19 18 17 16 15 14 13 12

ETI1 ETO1 ERI1 ERO1 ETI0 ETO0 ERI0 ERO0

Reserved bit - read as zero; should be written with zero for future compatibility.

Figure 6-3. PDRG Register

PD14 PD13 PD12

6.2.2.4 ESAI/EXTAL Clocking Control

ESAI/EXTAL clock bits optionally direct the EXTAL clock to the ESAI clocking chain for generating the corresponding high frequency clock, bit clock and framesync clock. There are 8 ESAI/EXTAL clock control bits as described in Tab le 6- 2. These bits are cleared upon reset.

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Table 6-2. ESAI/EXTAL clock bit descriptions

Programming Model

ESAI/EXTAL

control bit

ETI1 When this bit is set, the EXTAL clock can be used to generate the ESAI_1

transmitter clocks : HCKT_1, SCKT_1 and FST_1. When this bit is cleared, the Fosc clock can be used to generate the ESAI_1

transmitter clocks : HCKT_1, SCKT_1 and FST_1.

ETO1 When this bit is set, the EXTAL clock is directed to the HCKT_1 pin.

When this bit is cleared, EXTAL clock is not directed to the HCKT_1 pin

ERI1 When this bit is set, the EXTAL clock can be used to generate the ESAI_1

receiver clocks : HCKR_1, SCKR_1 and FSR_1. When this bit is cleared, the Fosc clock can be used to generate the ESAI_1

receiver clocks : HCKR_1, SCKR_1 and FSR_1.

ERO1 When this bit is set, the EXTAL clock is directed to the HCKR_1 pin.

When this bit is cleared, the EXTAL clock is not directed to the HCKR_1 pin.

ETI0 When this bit is set, the EXTAL clock can be used to generate the ESAI

transmitter clocks : HCKT, SCKT and FST. When this bit is cleared, the Fosc clock can be used to generate the ESAI

transmitter clocks : HCKT, SCKT and FST.

ETO0 When this bit is set, the EXTAL clock is directed to the HCKT pin.

When this bit is cleared, the EXTAL clock is not directed to the HCKT pin.

ERI0 When this bit is set, the EXTAL clock can be used to generate the ESAI

receiver clocks : HCKR, SCKR and FSR. When this bit is cleared, the Fosc clock can be used to generate the ESAI

receiver clocks : HCKR, SCKR and FSR.

Bit description

ERO0 When this bit is set, the EXTAL clock is directed to the HCKR pin.

When this bit is cleared, the EXTAL clock is not directed to the HCKR pin.

6.2.3 Port H Signals and Registers

Each of the five Port H signals (MODA, MODB, MODC, MODD and HREQ) can be configured individually as a GPIO signal. The GPIO functionality of Port H is controlled by three registers: Port H control register (PCRH), Port H direction register (PRRH) and Port H data register (PDRH).

6.2.3.1 Port H Control Register (PCRH)

The read/write 24-bit Port H Control Register (PCRH) in conjunction with the Port H Direction Register (PRRH) controls the functionality of the dedicated GPIO pins. Each of the PH(4:0) bits controls the functionality of the corresponding port pin. See Tabl e 6-3 . for the port-pin configurations. Hardware and software reset sets all PCRH bits.

6.2.3.2 Port H Direction Register (PRRH)

The read/write 24-bit Port H Direction Register (PRRH) in conjunction with the Port H Control Register (PCRH) controls the functionality of the dedicated GPIO pins. Ta ble 6-3. describes the port-pin configurations. Hardware and software reset sets all PRRH bits.

Table 6-3. PCRH and PRRH Bits Functionality

PDH[i] PH[i] Port Pin[i] Function

0 0 Disconnected

0 1 GPIO input

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Table 6-3. PCRH and PRRH Bits Functionality

PDH[i] PH[i] Port Pin[i] Function

1 0 GPIO output

1 1 Respective Functionality

(MODx or HREQ)

11109876543210

X:$FFFF9A

X:$FFFF99

PH4 PH3 PH2 PH1 PH0

23 22 21 20 19 18 17 16 15 14 13 12

Reserved bit - read as zero; should be written with zero for future compatibility.

Figure 6-4. PCRH Register

11109876543210

PDH4 PDH3 PDH2 PDH1 PDH0

23 22 21 20 19 18 17 16 15 14 13 12

Reserved bit - read as zero; should be written with zero for future compatibility.

Figure 6-5. PRRH Register

6.2.3.3 Port H Data RSegister (PDRH)

The read/write 24-bit Port H Data Register (see <Blue>Figure 6-6.) is used to read or write data to/from the dedicated GPIO pins. Bits PH(4:0) are used to read or write data from/to the corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a GPIO input, the corresponding PH[i] bit reflects the value present on this pin. If a port pin [i] is configured as a GPIO output, the value written into the corresponding PH[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PH[i] bit is not reset and contains undefined data.

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X:$FFFF98

23 22 21 20 19 18 17 16 15 14 13 12

Reserved bit - read as zero; should be written with zero for future compatibility.

PD4 PD3 PD2 PD1 PD0

Figure 6-6. PDRH Register

6.2.4 Timer/Event Counter Signals

The timer/event counter signals (TIO0, TIO1 and TIO2), when not used as timer signals can be configured as GPIO signals. These signals are controlled by the appropriate timer control status register (TCSR). The register is described in Chapter 9, Triple Timer Module

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Introduction

Chapter 7 Serial Host Interface

7.1 Introduction

The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI supports two well-known and widely used synchronous serial buses: the Freescale (previously known as Motorola) Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-Circuit Control (I overhead, the SHI supports 8-bit, 16-bit and 24-bit data transfers. The SHI has a 1 or 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception.

When configured in the SPI mode, the SHI can perform the following functions:

• Identify its slave selection (in slave mode)

• Simultaneously transmit (shift out) and receive (shift in) serial data

• Directly operate with 8-, 16- and 24-bit words

• Generate vectored interrupts separately for receive and transmit events and update status bits

• Generate a separate vectored interrupt for a receive exception

• Generate a separate vectored interrupt for a transmit exception

• Generate a separate vectored interrupt for a bus-error exception

• Generate the serial clock signal (in master mode)

• Trigger DMA to service the transmit and receive events

When configured in the I

• Detect/generate start and stop events

• Identify its slave (ID) address (in slave mode)

• Identify the transfer direction (receive/transmit)

• Transfer data byte-wise according to the SCL clock line

• Generate ACK signal following a byte receive

• Inspect ACK signal following a byte transmit

• Directly operate with 8-, 16- and 24-bit words

• Generate vectored interrupts separately for receive and transmit events and update status bits

• Generate a separate vectored interrupt for a receive exception

• Generate a separate vectored interrupt for a transmit exception

• Generate a separate vectored interrupt for a bus error exception

• Generate the clock signal (in master mode)

• Trigger DMA to service the transmit and receive events

C) bus. The SHI supports either bus protocol as either a slave or a single-master device. To minimize DSP

C mode, the SHI can perform the following functions:

7.2 Serial Host Interface Internal Architecture

The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP uses the SHI as a normal memory-mapped peripheral using standard polling, interrupt programming techniques, or DMA transfers. Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes. In addition, the MOVEP instruction allows interface-to-memory and memory-to-interface data transfers without going through an intermediate register. The DMA controller may be used to service the receive or transmit data path. The single master configuration allows the DSP to directly connect to dumb peripheral devices. For that purpose, a programmable baud-rate generator is included to generate the clock signal for serial transfers. The host side invokes the SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using either the bus protocols. Figure 7-1 shows the SHI block diagram.

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I2C or the SPI

Page 84

SHI Clock Generator

Clock

Generator

DSP AccessibleHost Accessible

DSP

Global

Data

Bus

SCK/SCL

MISO/SDA

MOSI/HA0

SS/HA2

HREQ

Control

Logic

HCKR

HCSR

Controller

Logic

INPUT/OUTPUT Shift Register

(IOSR)

HRX

Slave

(FIFO)

Address

Recognition

Unit

(SAR)

HSAR

24 BIT

Figure 7-1. Serial Host Interface Block Diagram

DSP

DMA

Data

Bus

HTX

7.3 SHI Clock Generator

The SHI clock generator generates the SHI serial clock if the interface operates in the master mode. The clock generator is disabled if the interface operates in the slave mode, except in mode, the clock is external and is input to the SHI (HMST = 0). Figure 7-2 illustrates the internal clock path connections. It is the user’s responsibility to select the proper clock rate within the range as defined in the I

I2C mode when the HCKFR bit is set in the HCKR register. When the SHI operates in the slave

C and SPI bus specifications.

HMST

SHI Clock

SCK/SCL

HMST = 0

HMST = 1

CPHA, CPOL, HI2C

Clock Logic

SHI

FOSC

Divide

By 2 Controller

Divide By 1

Divide By 256

Divide By

1 or 8

HRSHDM0–HDM7

Figure 7-2. SHI Clock Generator

7.4 Serial Host Interface Programming Model

The Serial Host Interface programming model has two parts:

• Host side—see Figure 7-3 below and Section 7.4.1, SHI Input/Output Shift Register (IOSR)—Host Side

•

DSP side—see Figure 7-4 and Section 7.4.2, SHI Host Transmit Data Register (HTX)—DSP Side through Section 7.4.6, SHI

Control/Status Register (HCSR)—DSP Side for detailed information.

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Serial Host Interface Programming Model

IOSR

I/O Shift Register (IOSR)

AA0418

Figure 7-3. SHI Programming Model—Host Side

07654321

815 14 13 12 11 10 9

07654321

815 14 13 12 11 10 9

HDM5

07 654321

815 14 13 12 11 10 9

HEN

HM0HRQE0 H MSTHRNEHBER HRFFHROE

HM1

HCKFR

HFIFO

HRQE1HIDLE

023

HDM6HDM7HFM0 HDM2 HDM0HDM1 HRSHDM3HDM4 CPHACPOL

HBIE

HRX

HRIE0HRIE1HTUEHTDE HTIE

HFM1

1623 22 21 20 19 18 17

HA1

HA3HA4HA5

1623 22 21 20 19 18 17

FIFO (10 Words Deep)

HTX

Reserved bit, read as 0, should be written with 0 for future compatibility.

C Slave Address Register (HSAR)

SHI I

HA6

SHI Clock Control Register (HCKR)

X: $FFFF92

X: $FFFF90

SHI Control/Status Register (HCSR)

HBUSY

SHI Receive Data FIFO (HRX)

X: $FFFF91

(read only, X: $FFFF94)

SHI Transmit Data Register (HTX)

(write only, X: $FFFF93)

Figure 7-4. SHI Programming Model—DSP Side

The SHI interrupt vector table is shown in Table 7-1 and the exception priorities generated by the SHI are shown in Table 7- 2 .

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Program Address Interrupt Source

VBA:$0040 SHI Transmit Data

VBA:$0042 SHI Transmit Underrun Error

VBA:$0044 SHI Receive FIFO Not Empty

VBA:$0048 SHI Receive FIFO Full

VBA:$004A SHI Receive Overrun Error

VBA:$004C SHI Bus Error

Table 7-2. SHI Internal Interrupt Priorities

Priority Interrupt

Table 7-1. SHI Interrupt Vectors

Highest

Lowest

SHI Bus Error

SHI Receive Overrun Error

SHI Transmit Underrun Error

SHI Receive FIFO Full

SHI Transmit Data

SHI Receive FIFO Not Empty

7.4.1 SHI Input/Output Shift Register (IOSR)—Host Side

The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both directions (read and write). In compliance with the and out MSB first. In 8-bit data transfer modes, the most significant byte of the IOSR is used as the shift register. In 16-bit data transfer modes, the two most significant bytes become the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the IOSR (see Tab le

7-5).

NOTE

The IOSR cannot be accessed directly either by the host processor or by the DSP. It is fully controlled by the SHI controller logic.

I2C and SPI bus protocols, data is shifted in

Mode of Operation

8-Bit Data

Mode

16-Bit Data

Mode

24-Bit Data

Mode

Stops Data When Data Mode is Selected

Passes Data When Data Mode is Selected

Figure 7-5. SHI I/O Shift Register (IOSR)

7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side

The host transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX register is 24 bits wide. Writing to the HTX register by DSP core instructions or by DMA transfers clears the HTDE flag. The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set (see Section 7.4.6.10, HCSR Transmit-Interrupt Enable (HTIE)—Bit 11). Data should not be written to the HTX

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until HTDE is set in order to prevent overwriting the previous data. HTX is reset to the empty state when in stop mode and during hardware reset, software reset and individual reset.

In the 8-bit data transfer mode, the most significant byte of the HTX is transmitted; in the 16-bit mode, the two most significant bytes are transmitted, and, in the 24-bit mode, all the contents of HTX are transferred.

7.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side

The 24-bit host receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO) register used for Host-to-DSP data transfers. The serial data is received via the shift register and then loaded into the HRX. In the 8-bit data transfer mode, the most significant byte of the shift register is transferred to the HRX (the other bits are cleared); in the 16-bit mode the two most significant bytes are transferred (the least significant byte is cleared), and, in the 24-bit mode, all 24 bits are transferred to the HRX. The HRX may be read by the DSP while the FIFO is being loaded from the shift register. Reading all data from HRX clears the HRNE flag. The HRX may be read by DSP core instructions or by DMA transfers. The HRX FIFO is reset to the empty state when the chip is in stop mode, as well as during hardware reset, software reset and individual reset.

7.4.4 SHI Slave Address Register (HSAR)—DSP Side

The 24-bit slave address register (HSAR) is used when the SHI operates in the I HSAR holds five bits of the 7-bit slave device address. The SHI also acknowledges the general call address specified by the (eight zeroes comprising a 7-bit address and a R/W differentiate between its dedicated address and the general call address. HSAR cannot be accessed by the host processor.

bit), but treats any following data bytes as regular data. That is, the SHI does not

7.4.4.1 HSAR Reserved Bits—Bits 19, 17– 0

These bits are reserved. They read as zero and should be written with zero for future compatibility.

C slave mode and is ignored in the other operational modes.

I2C protocol

7.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18

Part of the I2C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain the HA[6:0] slave device address. The full 7-bit slave device address is compared to the received address byte whenever an I2C master device initiates an I2C bus transfer. During hardware reset or software reset, HA[6:3] = 1011 and HA1 is cleared; this results in a default slave device address of 1011[HA2]0[HA0].

7.4.5 SHI Clock Control Register (HCKR)—DSP Side

The HCKR is a 24-bit read/write register that controls SHI clock generator operation. The HCKR bits should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR).

For proper SHI clock setup, please consult the data sheet. The programmer should not use the combination HRS = 1 and HDM[7:0] = 00000000, since it may cause synchronization problems and improper operation (it is an illegal combination).

The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which is set. The HCKR is not affected by the stop state.

The HCKR bits are described in the following paragraphs.

7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0

The Clock Phase (CPHA) bit controls the relationship between the data on the master-in-slave-out (MISO) and master-out-slave-in (MOSI) pins and the clock produced or received at the SCK pin. The CPOL bit determines the clock polarity (1 = active-high, 0 = active-low).

The clock phase and polarity should be identical for both the master and slave SPI devices. CPHA and CPOL are functional only when the SHI operates in the SPI mode and are ignored in the software reset.

The programmer may select any of four combinations of serial clock (SCK) phase and polarity when operating in the SPI mode (See Figure

7-6).

I2C mode. The CPHA bit is set and the CPOL bit is cleared during hardware reset and

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SCK

MISO/ MOSI

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

MSB654321LSB

Internal Strobe for Data Capture

Figure 7-6. SPI Data-To-Clock Timing Diagram

If CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device whenever data is not being transferred. If the CPOL bit is set, it produces a high value at the SCK pin of the master device whenever data is not being transferred.

CPHA is used with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit, in general, selects the clock edge that captures data and allows it to change states. It has its greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge.

When the SHI is in slave mode and CPHA = 0, the SS word transfer. SS HTDE = 1, clearing HTDE. However, the data is transferred to the shift register for transmission only when SS when the data is transferred from HTX to the shift register.

When the SHI is in slave mode and CPHA = 1, the SS line may remain asserted between successive word transfers. The SS must remain asserted between successive bytes within a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register.

When the SHI is in master mode and CPHA = 0, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The data is transferred immediately to the shift register for transmission. HTDE is set only at the end of the data word transmission.

must remain asserted between successive bytes within a word. The DSP core should write the next data word to HTX when

line must be de-asserted and asserted by the external master between each successive

is de-asserted. HTDE is set

NOTE

The master is responsible for de-asserting and asserting the slave device SS line between word transmissions.

When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register.

7.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2

The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to extend the range of the divider when slower clock rates are desired. When HRS is set, the prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight prescaler is operational. HRS is ignored when the SHI operates in the slave mode, except for and software reset.

Use the equations in the SHI data sheet to determine the value of HRS for the specific serial clock frequency required.

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NOTE

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7.4.5.3 HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3

The HDM[7:0] bits specify the divide ratio of the clock generator divider. A divide ratio between 1 and 256 (HDM[7:0] = $00 to $FF) may be selected. When the SHI operates in the slave mode, the HDM[7:0] bits are ignored (except for bits are cleared during hardware reset and software reset.

I2C when HCKFR is set). The HDM[7:0]

NOTE

Use the equations in the SHI data sheet to determine the value of HDM[7:0] for the specific serial clock frequency required.

7.4.5.4 HCKR Filter Mode (HFM[1:0]) — Bits 13–12

The read/write control bits HFM[1:0] specify the operational mode of the noise reduction filters, as described in Table 7-3.. The filters are designed to eliminate undesired spikes that might occur on the clock and data-in lines and allow the SHI to operate in noisy environments when required. One filter is located in the input path of the SCK/SCL line and the other is located in the input path of the data line (i.e., the SDA line when in

I2C mode, the MISO line when in SPI master mode, and the MOSI line when in SPI slave mode).

Table 7-3. SHI Noise Reduction Filter Mode

HFM1 HFM0 Description

00Bypassed (Disabled)

01Very Narrow Spike Tolerance.

10Narrow Spike Tolerance

11Wide Spike Tolerance

When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment.

When HFM[1:0] = 01, the very narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes with durations of up to 10ns. This mode is useful when very high bit-rate transfers are required and the SHI operates in a nearly noise-free environment.

When HFM[1:0] = 10, the narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes with durations of up to 50ns. This mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit-rate transfer.

When HFM[1:0] = 11, the wide-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes up to 100 ns. This mode is recommended for use in noisy environments; the bit-rate transfer is strictly limited. The wide-spike- tolerance filter mode is highly recommended for use in

I2C bus systems as it fully conforms to the I2C bus specification and improves noise immunity.

NOTE

HFM[1:0] are cleared during hardware reset and software reset.

After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting the HEN bit in the HCSR). Similarly, after changing the H I the CPOL bit in the HCKR, while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR).

C bit in the HCSR or

7.4.5.5 HCKR Reserved Bits—Bits 23–14, 11

These bits in HCKR are reserved. They are read as zero and should be written with zero for future compatibility.

7.4.6 SHI Control/Status Register (HCSR)—DSP Side

The HCSR is a 24-bit register that controls the SHI operation and reflects its status. The control bits are read/write. The status bits are read-only. The bits are described in the following paragraphs. When in the stop state or during individual reset, the HCSR status bits are reset to their hardware-reset state, while the control bits are not affected.

7.4.6.1 HCSR Host Enable (HEN)—Bit 0

The read/write control bit HEN, when set, enables the SHI. When HEN is cleared, the SHI is disabled (that is, it is in the individual reset state, see below). The HCKR and the HCSR control bits are not affected when HEN is cleared. When operating in master mode, HEN should be cleared only when the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset and software reset.

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7.4.6.1.1 SHI Individual Reset

While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. The individual reset state is entered following a one-instruction-cycle delay after clearing HEN.

7.4.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 1

The read/write control bit H I SPI mode. When H

Signal/Connection Descriptions . It is recommended that an SHI individual reset be generated (HEN cleared) before changing H

is cleared during hardware reset and software reset.

I2C is set, the SHI operates in the I2C mode. H I2C affects the functionality of the SHI pins as described in Section 2,

7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2

The read/write control bits HM[1:0] select the size of the data words to be transferred, as shown in Tab le 7- 4.. HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and software reset.

C selects whether the SHI operates in the I2C or SPI modes. When HI2C is cleared, the SHI operates in the

Table 7-4. SHI Data Size

HM1 HMO Description

0 0 8-bit data

0 1 16-bit data

1 0 24-bit data

I2C. H I2C

11Reserved

7.4.6.4 HCSR I2C Clock Freeze (HCKFR)—Bit 4

The read/write control bit HCKFR determines the behavior of the SHI when the SHI is unable to service the master request, when operating

I2C slave mode. The HCKFR bit is used only in the I2C slave mode; it is ignored otherwise.

in the

If HCKFR is set, the SHI holds the clock line to GND if it is not ready to send data to the master during a read transfer or if the input FIFO is full when the master attempts to execute a write transfer. In this way, the master may detect that the slave is not ready for the requested transfer, without causing an error condition in the slave. When HCKFR is set for transmit sessions, the SHI clock generator must be programmed as if to generate the same serial clock as produced by the external master, otherwise erroneous operation may result. The programmed frequency should be in the range of 1 to 0.75 times the external clock frequency.

If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not ready results in an overrun or underrun error condition.

It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardware reset and software reset.

7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5

The read/write control bit HFIFO selects the receive FIFO size. When HFIFO is cleared, the FIFO has one level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HFIFO. HFIFO is cleared during hardware reset and software reset.

7.4.6.6 HCSR Master Mode (HMST)—Bit 6

The read/write control bit HMST determines the SHI operating mode. If HMST is set, the interface operates in the master mode. If HMST is cleared, the interface operates in the slave mode. The SHI supports a single-master configuration in both

When configured as an SPI master, the SHI drives the SCK line and controls the direction of the data lines MOSI and MISO. The SS be held de-asserted in the SPI master mode; if the SS HBER bit is set—see Section 7.4.6.18, Host Bus Error (HBER)—Bit 21).

When configured as an I reception of serial data.

It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST. HMST is cleared during hardware reset and software reset.

C master, the SHI controls the I2C bus by generating start events, clock pulses and stop events for transmission and

line is asserted when the SHI is in SPI master mode, a bus error is generated (the HCSR

I2C and SPI modes.

line must

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7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7

The read/write control bits HRQE[1:0] are used to control the HREQ pin. When HRQE[1:0] are cleared, the HREQ pin is disabled and held in the high impedance state. If either of HRQE[1:0] are set and the SHI is in a master mode, the HREQ de-asserting HREQ operation is defined in Table 7-5. HRQE[1:0] should be changed only when the SHI is idle (HBUSY = 0). HRQE[1:0] are cleared during hardware reset and software reset. Note the HREQ can also be programmed as a GPIO. See Section 6.2.3, Port H Signals and Registers

suspends SCK. If either of HRQE[1:0] are set and the SHI is in SPI slave mode, HREQ becomes an output and its

pin becomes an input controlling SCK:

Table 7-5. HREQ Function In SPI Slave Mode

HRQE1 HRQE0 HREQ Pin Operation

0 0 High impedance

0 1 Asserted if IOSR is ready to receive a new word

1 0 Asserted if IOSR is ready to transmit a new word

1 1 SPI: Asserted if IOSR is ready to transmit and receive

7.4.6.8 HCSR Idle (HIDLE)—Bit 9

The read/write control/status bit HIDLE is used only in the I2C master mode; it is ignored otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing to HTX. To ensure correct transmission of the slave device address byte, HIDLE should be set only when HTX is empty (HTDE = 1). After HIDLE is set, a write to HTX clears HIDLE and causes the generation of a stop event, a start event, and then the transmission of the eight MSBs of the data as the slave device address byte. While HIDLE is cleared, data written to HTX is transmitted as is. If the SHI completes transmitting a word and there is no new data in HTX, the clock is suspended after sampling ACK. If HIDLE is set when the SHI completes transmitting a word with no new data in HTX, a stop event is generated.

HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If HIDLE is cleared, the reception is acknowledged by sending a 0 bit on the SDA line at the ACK clock tick. If HIDLE is set, the reception is not acknowledged (a 1 bit is sent). It is used to signal an end-of-data to a slave transmitter by not generating an ACK on the last byte. As a result, the slave transmitter must release the SDA line to allow the master to generate the stop event. If the SHI completes receiving a word and the HRX FIFO is full, the clock is suspended before transmitting an ACK. While HIDLE is cleared the bus is busy, that is, the start event was sent but no stop event was generated. Setting HIDLE causes a stop event after receiving the current word.

HIDLE is set while the SHI is not in the individual reset.

Programmers should take care to ensure that all DMA channel service to HTX is disabled before setting HIDLE.

I2C master mode, while the chip is in the stop state, and during hardware reset, software reset and

NOTE

7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10

The read/write control bit HBIE is used to enable the SHI bus-error interrupt. If HBIE is cleared, bus-error interrupts are disabled, and the HBER status bit must be polled to determine if an SHI bus error occurred. If both HBIE and HBER are set, the SHI requests an SHI bus-error interrupt service from the interrupt controller. HBIE is cleared by hardware reset and software reset.

NOTE

Clearing HBIE masks a pending bus-error interrupt only after a one instruction cycle delay. If HBIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HBIE and the RTI instruction at the end of the interrupt service routine.

7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11

The read/write control bit HTIE is used to enable the SHI transmit data interrupts. If HTIE is cleared, transmit interrupts are disabled, and the HTDE status bit must be polled to determine if HTX is empty. If both HTIE and HTDE are set and HTUE is cleared, the SHI requests an SHI transmit-data interrupt service from the interrupt controller. If both HTIE and HTUE are set, the SHI requests an SHI transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by hardware reset and software reset.

NOTE

Clearing HTIE masks a pending transmit interrupt only after a one instruction cycle delay. If HTIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HTIE and the RTI instruction at the end of the interrupt service routine.

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7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12

The read/write control bits HRIE[1:0] are used to enable the SHI receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive interrupts are generated according to Table 7-6. HRIE[1:0] are cleared by hardware and software reset.

Table 7-6. HCSR Receive Interrupt Enable Bits

HRIE[1:0] Interrupt Condition

00 Disabled Not applicable

01 Receive FIFO not empty

Receive Overrun Error

10 Reserved Not applicable

11 Receive FIFO full

Receive Overrun Error

HRNE = 1 and HROE = 0 HROE = 1

HRFF = 1 and HROE = 0 HROE = 1

NOTE

Clearing HRIE[1:0] masks a pending receive interrupt only after a one instruction cycle delay. If HRIE[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HRIE[1:0] and the RTI instruction at the end of the interrupt service routine.

7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14

The read-only status bit HTUE indicates whether a transmit-underrun error occurred. Transmit-underrun errors can occur only when operating in the SPI slave mode or the can occur. HTUE is set when both the shift register and the HTX register are empty and the external master begins reading the next word:

• When operating in the transmitted word.

• When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the assertion of SS

If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector is generated. If a transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector is generated. HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware reset, software reset, SHI individual reset and during the stop state.

I2C slave mode when HCKFR is cleared. In a master mode, transmission takes place on demand and no underrun

I2C mode, HTUE is set in the falling edge of the ACK bit. In this case, the SHI retransmits the previously

if CPHA = 0.

7.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15

The read-only status bit HTDE indicates whether the HTX register is empty and can be written by the DSP. HTDE is set when the data word is transferred from HTX to the shift register, except in SPI master mode when CPHA = 0 (see HCKR). When in the SPI master mode with CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared when the DSP writes the HTX either with write instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI individual reset and during the stop state.

7.4.6.14 HCSR Reserved Bits—Bits 23, 18 and 16

These bits are reserved. They read as zero and should be written with zero for future compatibility.

7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17

The read-only status bit HRNE indicates that the Host Receive FIFO (HRX) contains at least one data word. HRNE is set when the FIFO is not empty. HRNE is cleared when HRX is read by the DSP (read instructions or DMA transfers), reducing the number of words in the FIFO to zero. HRNE is cleared during hardware reset, software reset, SHI individual reset and during the stop state.

7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19

The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full. HRFF is cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset and during the stop state.

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7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20

The read-only status bit HROE indicates, when set, that a data-receive overrun error has occurred. Receive-overrun errors cannot occur when operating in the HCKFR is set.

HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to the HRX FIFO and the FIFO is already full (HRFF is set). When a receive-overrun error occurs, the shift register is not transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun interrupt vector is generated. If a receive interrupt occurs with HROE cleared, the regular receive-data interrupt vector is generated.

HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is cleared by hardware reset, software reset, SHI individual reset and during the stop state.

I2C master mode, because the clock is suspended if the receive FIFO is full; nor can they occur in the I2C slave mode when

7.4.6.18 Host Bus Error (HBER)—Bit 21

The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a master (HMST set). In I HBER is set if the transmitter does not receive an acknowledge after a byte is transferred; then a stop event is generated and transmission is suspended. In SPI mode, HBER is set if SS is cleared only by hardware reset, software reset, SHI individual reset and during the stop state.

is asserted; then transmission is suspended at the end of transmission of the current word. HBER

C mode,

7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22

The read-only status bit HBUSY indicates that the I mode). When operating in the operating in the slave SPI mode, HBUSY is set while SS is not empty or if the IOSR is not empty. HBUSY is cleared otherwise. HBUSY is cleared by hardware reset, software reset, SHI individual reset and during the stop state.

I2C mode, HBUSY is set after the SHI detects a start event and remains set until a stop event is detected. When

C bus is busy (when in the I2C mode) or that the SHI itself is busy (when in the SPI

is asserted. When operating in the master SPI mode, HBUSY is set if the HTX register

7.5 Characteristics Of The SPI Bus

The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK) and a Slave Select line (SS). During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a circular manner, with one shift register on the master side and the other on the slave side. Thus the data bytes in the master device and slave device are exchanged. The MISO and MOSI data pins are used for transmitting and receiving serial data. When the SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line. When the SPI is configured as a slave device, MISO is the slave data output line, and MOSI is the slave data input line.

Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, the control bits in the HCKR select the appropriate clock rate, as well as the desired clock polarity and phase format (see Figure 7-6).

line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activity, i.e.,

The SS they keep their MISO output pin in the high-impedance state. When the SHI is configured as an SPI master device, the SS high. If the SS

line is driven low when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set).

line should be held

7.6 Characteristics Of The I2C Bus

The I

C serial bus consists of two bidirectional lines, one for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL

lines must be connected to a positive supply voltage via a pull-up resistor.

In the I

C bus specifications, the standard mode (100KHz clock rate) and a fast mode (400KHz clock

rate) are defined. The SHI can operate in either mode.

7.6.1 Overview

The I2C bus protocol must conform to the following rules:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line when the clock line is high are interpreted as control signals (see Table 7-7).

NOTE

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SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

AA0422

Figure 7-7. I2C Bit Transfer

Accordingly, the I

•

• Start data transfer—The start event is defined as a change in the state of the data line, from high to low, while the clock is

•

C bus protocol defines the following events:

Bus not busy—Both data and clock lines remain high.

high (see Figure 7-8).

Stop data transfer—The stop event is defined as a change in the state of the data line, from low to high, while the clock is high

(see Figure 7-8).

Data valid—The state of the data line represents valid data when, after a start event, the data line is stable for the duration of the

high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.

SDA

SCL

S P

Start Event Stop Event

AA0423

Figure 7-8. I2C Start and Stop Events

Each 8-bit word is followed by one acknowledge bit. This acknowledge bit is a high level put on the bus by the transmitter when the master device generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an acknowledge after each byte is received. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The acknowledging device must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable low during the high period of the acknowledge-related clock pulse (see Table 7-9).

Start

Event

Clock Pulse For

Acknowledgment

SCL From

Master Device

12 89

Data Output

by Transmitter

Data Output

by Receiver

AA0424

Figure 7-9. Acknowledgment on the I2C Bus

A device generating a signal is called a transmitter, and a device receiving a signal is called a receiver. A device controlling a signal is called a master and devices controlled by the master are called slaves. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte clocked out of the slave device. In this case the transmitter must leave the data line high to enable the master to generate the stop event. Handshaking may also be accomplished by using the clock synchronizing mechanism. Slave devices

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can hold the SCL line low, after receiving and acknowledging a byte, to force the master into a wait state until the slave device is ready for the next byte transfer. The SHI supports this feature when operating as a master device and waits until the slave device releases the SCL line before proceeding with the data transfer.

7.6.2 I2C Data Transfer Formats

The I2C bus data transfers follow the following process: after the start event, a slave device address is sent. The address consists of seven

address bits and an eighth bit as a data direction bit (R/W). In the data direction bit, zero indicates a transmission (write), and one indicates a request for data (read). A data transfer is always terminated by a stop event generated by the master device. However, if the master device still wishes to communicate on the bus, it can generate another start event and address another slave device without first generating a stop event. (The SHI does not support this feature when operating as an Various combinations of read/write formats are illustrated in Table 7-10 and Figure 7-11.

I2C master device.) This method is also used to provide indivisible data transfers.

SAA0Slave Address

ACK from

Slave Device

First Data Byte Data Byte

ACK from

Slave Device

ACK from

Slave Device

S, PA

N = 0 to M

Start

Bit Stop Bit

R/W

AA0425

Data Bytes

Start or

Figure 7-10. I2C Bus Protocol For Host Write Cycle

SAA1Slave Address

ACK from

Slave Device

Data Byte

ACK from

Master Device

Last Data Byte

No ACK

from Master Device

N = 0 to M

Start Stop

R/W

Bit Bit

Figure 7-11. I

Data Bytes

AA0426

C Bus Protocol For Host Read Cycle

P 1

NOTE

The first data byte in a write-bus cycle can be used as a user-predefined control byte (e.g., to determine the location to which the forthcoming data bytes should be transferred).

7.7 SHI Programming Considerations

The SHI implements both SPI and I operating mode is selected, the SHI may communicate with an external device by receiving and/or transmitting data. Before changing the SHI operational mode, an SHI individual reset should be generated by clearing the HEN bit. The following paragraphs describe programming considerations for each operational mode.

7.7.1 SPI Slave Mode

The SPI slave mode is entered by enabling the SHI (HEN=1), selecting the SPI mode (HI (HMST=0). The programmer should verify that the CPHA and CPOL bits (in the HCKR) correspond to the external host clock phase and polarity. Other HCKR bits are ignored. When configured in the SPI slave mode, the SHI external pins operate as follows:

• SCK/SCL is the SCK serial clock input.

• MISO/SDA is the MISO serial data output.

• MOSI/HA0 is the MOSI serial data input.

•SS

/HA2 is the SS slave select input.

•HREQ is the Host Request output.

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C bus protocols and can be programmed to operate as a slave device or a single-master device. Once the

C=0) and selecting the slave mode of operation

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In the SPI slave mode, a receive, transmit, or full-duplex data transfer may be performed. Actually, the interface performs data receive and transmit simultaneously. The status bits of both receive and transmit paths are active; however, the programmer may disable undesired interrupts and ignore irrelevant status bits. It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the HRX FIFO to its initial (empty) state (e.g., when switching from transmit to receive data).

If a write to HTX occurs, its contents are transferred to IOSR between data word transfers. The IOSR data is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP may write HTX with either DSP instructions or DMA transfers if the HTDE status bit is set. If no writes to HTX occur, the contents of HTX are not transferred to IOSR, so the data shifted out when receiving is the data present in the IOSR at the time. The HRX FIFO contains valid receive data, which the DSP can read with either DSP instructions or DMA transfers (if the HRNE status bit is set).

The HREQ this operation guarantees that the next received data word is stored in the FIFO. The HREQ

10), is asserted when the IOSR is loaded from HTX with a new data word to transfer. If HREQ (HRQE[1:0] = 11), it is asserted when the receive and transmit conditions are both true. HREQ next data word transfer. The HREQ SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI slave device, enables full hardware handshaking if operating with CPHA = 1.

The SS is aborted and the received data word is lost.

output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready for receive and the HRX FIFO is not full;

output pin, if enabled for transmit (HRQE[1:0] =

is enabled for both transmit and receive is de-asserted at the first clock pulse of the

line may be used to interrupt the external master device. Connecting the HREQ line between two

line should be kept asserted during a data word transfer. If the SS line is de-asserted before the end of the data word transfer, the transfer

7.7.2 SPI Master Mode

The SPI master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode (HI operation (HMST = 1). Before enabling the SHI as an SPI master device, the programmer should program the proper clock rate, phase and polarity in HCKR. When configured in the SPI master mode, the SHI external pins operate as follows:

• SCK/SCL is the SCK serial clock output.

• MISO/SDA is the MISO serial data input.

• MOSI/HA0 is the MOSI serial data output.

•SS

/HA2 is the SS input. It should be kept de-asserted (high) for proper operation.

•HREQ

The external slave device can be selected either by using external logic or by activating a GPIO pin connected to its SS input pin of the SPI master device should be held de-asserted (high) for proper operation. If the SPI master device SS bus error status bit (HBER) is set. If the HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service the SHI bus error interrupt.

In the SPI master mode the DSP must write to HTX to receive, transmit or perform a full-duplex data transfer. Actually, the interface performs simultaneous data receive and transmit. The status bits of both receive and transmit paths are active; however, the programmer may disable undesired interrupts and ignore irrelevant status bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are generated, the IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The DSP programmer may write HTX (if the HTDE status bit is set) with either DSP instructions or DMA transfers to initiate the transfer of the next word. The HRX FIFO contains valid receive data, which the DSP can read with either DSP instructions or DMA transfers, if the HRNE status bit is set.

It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state (e.g., when switching from transmit to receive data).

The HREQ by the slave device, HREQ pulses for the full data word transfer. HREQ de-asserted, HREQ two SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ should be disabled by clearing HRQE[1:0].

is the Host Request input.

input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared and considered if any of them is set. When asserted

indicates that the external slave device is ready for the next data transfer. As a result, the SPI master sends clock

is de-asserted by the external slave device at the first clock pulse of the new data transfer. When

prevents the clock generation of the next data word transfer until it is asserted again. Connecting the HREQ line between

C = 0) and selecting the master mode of

pin. However, the SS

pin is asserted, the host

7.7.3 I2C Slave Mode

The I2C slave mode is entered by enabling the SHI (HEN=1), selecting the I2C mode (HI2C=1) and selecting the slave mode of operation (HMST=0). In this operational mode the contents of HCKR are ignored. When configured in the I as follows:

• SCK/SCL is the SCL serial clock input.

• MISO/SDA is the SDA open drain serial data line.

• MOSI/HA0 is the HA0 slave device address input.

•SS/HA2 is the HA2 slave device address input.

•HREQ

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is the Host Request output.

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When the SHI is enabled and configured in the I2C slave mode, the SHI controller inspects the SDA and SCL lines to detect a start event. Upon detection of the start event, the SHI receives the slave device address byte and enables the slave device address recognition unit. If the slave device address byte was not identified as its personal address, the SHI controller fails to acknowledge this byte by not driving low the SDA line at the ninth clock pulse (ACK = 1). However, it continues to poll the SDA and SCL lines to detect a new start event. If the personal slave device address was correctly identified, the slave device address byte is acknowledged (ACK = 0 is sent) and a receive/transmit session is initiated according to the eighth bit of the received slave device address byte, i.e., the R/W

bit.

7.7.3.1 Receive Data in I2C Slave Mode

A receive session is initiated when the personal slave device address has been correctly identified and the R/W bit of the received slave device address byte has been cleared. Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line. Data is acknowledged byte wise, as required by the I2C bus protocol, and is transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the responsibility of the programmer to select the correct number of bytes in an I2C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count as part of the data; therefore, it is treated separately.

In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited. The HRX FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers (if the HRNE status bit is set).

If HCKFR is cleared, when the HRX FIFO is full and IOSR is filled, an overrun error occurs and the HROE status bit is set. In this case, the last received byte is not acknowledged (ACK=1 is sent) and the word in the IOSR is not transferred to the HRX FIFO. This may inform the external I session by generating a stop event.

If HCKFR is set, when the HRX FIFO is full the SHI holds the clock line to GND not letting the master device write to IOSR, which eliminates the possibility of reaching the overrun condition.

The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready to receive and the HRX FIFO is not full; this operation guarantees that the next received data word is stored in the FIFO. HREQ received word. The HREQ DSPs, one operating as an I

C master device of the occurrence of an overrun error on the slave side. Consequently the I2C master device may terminate this

is de-asserted at the first clock pulse of the next

line may be used to interrupt the external I2C master device. Connecting the HREQ line between two SHI-equipped

C master device and the other as an I2C slave device, enables full hardware handshaking.

7.7.3.2 Transmit Data In I2C Slave Mode

A transmit session is initiated when the personal slave device address has been correctly identified and the R/W bit of the received slave device address byte has been set. Following a transmit initiation, the IOSR is loaded from HTX (assuming the latter was not empty) and its contents are shifted out, MSB first, on the SDA line. Following each transmitted byte, the SHI controller samples the SDA line at the ninth clock pulse and inspects the ACK status. If the transmitted byte was acknowledged (ACK = 0), the SHI controller continues and transmits the next byte. However, if it was not acknowledged (ACK = 1), the transmit session is stopped and the SDA line is released. Consequently, the external master device may generate a stop event in order to terminate the session.

HTX contents are transferred to IOSR when the complete word (according to HM[1:0]) has been shifted out. It is, therefore, the responsibility of the programmer to select the correct number of bytes in an I

C frame so that they fit in a complete number of words. For this purpose, the

slave device address byte does not count as part of the data; therefore, it is treated separately.

In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited. When the HTX transfers its valid data word to IOSR, the HTDE status bit is set and the DSP may write a new data word to HTX with either DSP instructions or DMA transfers.

If HCKFR is cleared and both IOSR and HTX are empty when the master device attempts a transmit session, an underrun condition occurs, setting the HTUE status bit, and the previous word is retransmitted.

If HCKFR is set and both IOSR and HTX are empty when the master device attempts a transmit session, the SHI holds the clock line to GND to avoid an underrun condition.

The HREQ output pin, if enabled for transmit (HRQE[1:0] = 10), is asserted when HTX is transferred to IOSR for transmission. When asserted, HREQ transmitted data word. The HREQ SHI-equipped DSPs, one operating as an I

indicates that the slave device is ready to transmit the next data word. HREQ is de-asserted at the first clock pulse of the next

line may be used to interrupt the external I2C master device. Connecting the HREQ line between two

C master device and the other as an I2C slave device, enables full hardware handshaking.

7.7.4 I2C Master Mode

The I2C master mode is entered by enabling the SHI (HEN=1), selecting the I2C mode (HI2C=1) and selecting the master mode of operation (HMST=1). Before enabling the SHI as an I

When configured in the I

C master mode, the SHI external pins operate as follows:

• SCK/SCL is the SCL open drain serial clock output.

• MISO/SDA is the SDA open drain serial data line.

• MOSI/HA0 is the HA0 slave device address input.

C master, the programmer should program the appropriate clock rate in HCKR.

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•SS/HA2 is the HA2 slave device address input.

•HREQ is the Host Request input.

C master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set. This condition

In the I ensures that the data byte written to HTX is interpreted as being a slave address byte. This data byte must specify the slave device address to be selected and the requested data transfer direction.

NOTE

The slave address byte should be located in the high portion of the data word, whereas the middle and low portions are ignored. Only one byte (the slave address byte) is shifted out, independent of the word length defined by the HM[1:0] bits.

In order for the DSP to initiate a data transfer the following actions are to be performed:

• The DSP tests the HIDLE status bit.

• If the HIDLE status bit is set, the DSP writes the slave device address and the R/W

• The SHI generates a start event.

• The SHI transmits one byte only, internally samples the R/W

direction bit (last bit) and accordingly initiates a receive or transmit

session.

• The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value. If acknowledged (ACK = 0), it starts its receive or transmit session according to the sampled R/W

value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is set, which

causes an SHI Bus Error interrupt request if HBIE is set, and a stop event is generated.

The HREQ input pin is ignored by the I2C master device if HRQE[1:0] are cleared, and it is considered if either of them is set. When asserted, HREQ

indicates that the external slave device is ready for the next data transfer. As a result, the I2C master device sends clock pulses for the

full data word transfer. HREQ

prevents the clock generation of the next data word transfer until it is asserted again. Connecting the HREQ line between two

HREQ SHI-equipped DSPs, one operating as an I

is de-asserted by the external slave device at the first clock pulse of the next data transfer. When de-asserted,

C master device and the other as an I2C slave device, enables full hardware handshaking.

bit to the most significant byte of HTX.

7.7.4.1 Receive Data in I2C Master Mode

A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set. Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line if the HIDLE control bit is cleared. Data is acknowledged byte-wise, as required by the I2C bus protocol, and is transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the responsibility of the programmer to select the correct number of bytes in an I2C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count as part of the data; therefore, it is treated separately.

If the I2C slave transmitter is acknowledged, it should transmit the next data byte. In order to terminate the receive session, the programmer should set the HIDLE bit at the last required data word. As a result, the last byte of the next received data word is not acknowledged, the slave transmitter releases the SDA line, and the SHI generates the stop event and terminates the session.

In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the HRNE status bit is set, the HRX FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers. When the HRX FIFO is full, the SHI suspends the serial clock just before acknowledge. In this case, the clock is reactivated when the FIFO is read (the SHI gives an ACK = 0 and proceeds receiving).

7.7.4.2 Transmit Data In I2C Master Mode

A transmit session is initiated if the R/W direction bit of the transmitted slave device address byte is cleared. Following a transmit initiation, the IOSR is loaded from HTX (assuming HTX is not empty) and its contents are shifted out, MSB-first, on the SDA line. Following each transmitted byte, the SHI controller samples the SDA line at the ninth clock pulse and inspects the ACK status. If the transmitted byte was acknowledged (ACK=0), the SHI controller continues transmitting the next byte. However, if it was not acknowledged (ACK=1), the HBER status bit is set to inform the DSP side that a bus error (or overrun, or any other exception in the slave device) has occurred. Consequently, the

C master device generates a stop event and terminates the session.

HTX contents are transferred to the IOSR when the complete word (according to HM[1:0]) has been shifted out. It is, therefore, the responsibility of the programmer to select the right number of bytes in an I2C frame so that they fit in a complete number of words. Remember that for this purpose, the slave device address byte does not count as part of the data.

In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited. When the HTX transfers its valid data word to the IOSR, the HTDE status bit is set and the DSP may write a new data word to HTX with either DSP instructions or DMA transfers. If both IOSR and HTX are empty, the SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate the transmit session).

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7.7.5 SHI Operation During DSP Stop

The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active. While the DSP is in the stop state, the SHI remains in the individual reset state.

While in the individual reset state the following is true:

• If the SHI was operating in the I2C mode, the SHI signals are disabled (high impedance state).

• If the SHI was operating in the SPI mode, the SHI signals are not affected.

• The HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset.

• The HCSR and HCKR control bits are not affected.

NOTE

It is recommended that the SHI be disabled before entering the stop state.

7.7.6 GPIO- HREQ Signal and Registers

Note that the HREQ pin can also be programmed as a GPIO. See Section 6.2.3, Port H Signals and Registers.

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Notes

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Freescale Semiconductor DSP56374 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

DSP56374

24-Bit Digital Signal Processor

User Guide

Preface

Revision History

Manual Conventions

Chapter 1 DSP56374 Overview

1.1 Introduction

1.2 DSP56300 Core Description

1.3 DSP56374 Audio Processor Architecture

1.4 DSP56300 Core Functional Blocks

1.4.1 Data ALU

1.4.1.1 Data ALU Registers

1.4.1.2 Multiplier-Accumulator (MAC)

1.4.2 Address Generation Unit (AGU)

1.4.3 Program Control Unit (PCU)

1.4.4 Internal Buses

1.4.5 Direct Memory Access (DMA)

1.4.6 PLL-based Clock Oscillator

1.4.7 On-Chip Memory

1.4.8 Off-Chip Memory Expansion

1.4.9 Power Requirements

1.5 Peripheral Overview

1.5.1 General Purpose Input/Output (GPIO)

1.5.2 Triple Timer (TEC)

1.5.3 Enhanced Serial Audio Interface (ESAI)

1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1)

1.5.5 Serial Host Interface (SHI)

1.5.6 Watchdog timer (WDT)

Chapter 2 Signal/Connection Descriptions

2.1 Signal Groupings

2.2 Power

2.3 Ground

2.4 SCAN

2.5 Clock and PLL

2.6 Interrupt and Mode Control

2.7 Serial Host Interface

2.8 Enhanced Serial Audio Interface

2.9 Enhanced Serial Audio Interface_1

2.10 Dedicated GPIO - Port G

2.11 Timer

2.12 JTAG/OnCE Interface

Chapter 3 Memory Configuration

3.1 Data and Program Memory Maps

3.1.1 Reserved Memory Spaces

3.1.2 Bootstrap CODE

3.1.3 Dynamic Memory Configuration Switching

3.1.4 External Memory Support

3.1.5 DMA and Memory

3.1.6 Memory BLOCKS

3.2 Memory Patch Module

3.3 Internal I/O Memory Map

Chapter 4 Core Configuration

4.1 Introduction

4.2 Operating Mode Register (OMR)

4.2.1 RESERVED - Bits 4, 5, 10 - 15 and 23

4.3 Operating Modes

4.4 Interrupt Priority Registers

4.5 DMA Request Sources

4.6 PLL Initialization

4.6.1 PLL Pre-Divider Factor (PD0-PD4)

4.6.2 PLL Multiplication Factor (MF0-MF7)

4.6.3 PLL Feedback Multiplier (OD1)

4.6.4 PLL Output Divide Factor (OD0-OD1)

4.6.5 PLL Divider Factor (DF0-DF2)

4.6.6 PLL LOCK MUX (PLKM)

4.7 Device Identification (ID) Register

4.8 JTAG Identification (ID) Register

Chapter 5 PLL and Clock generator

5.1 Introduction

5.2 PLL and Clock Signals

5.3 PLL Block

5.3.1 Frequency Predivider

5.3.2 Phase Detector and Charge Pump Loop Filter

5.3.3 Voltage Controlled Oscillator (VCO)

5.3.4 PLL DividerS