Freescale Semiconductor DSP56311 Technical Data Manual
Freescale Semiconductor
Technical Data
DSP56311
Rev. 8, 2/2005
© Freescale Semiconductor, Inc., 1999, 2005. All rights reserved.
DSP56311
24-Bit Digital Signal Processor
The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)
controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining
up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
Figure 1. DSP56311 Block Diagram
YA B
XAB
PA B
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
13
MODD/IRQD
DSP56300
616
24-Bit
24
18
DDB
DAB
Peripheral
Core
YM_EB
XM_EB
PM_EB
PIO_EB
Expansion Area
6
5
3
RESET
MODA/IRQA
PINIT/NMI
EXTAL
XTAL
Address
Control
Data
Address
Generation
Unit
Six Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56-b it MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and
I - Cache
Control
Memory Expansion Area
DE
Program
RAM
32 K × 24 bits
X Data
RAM
48 K × 24 bits
Y Data
RAM
48 K × 24 bits
External
Address
Bus
Switch
SCI EFCOPESSIHI08
Tri pl e
Timer
or
31 K × 24 bits
Instruction
Cache
1024 × 24 bits
Bootstrap
ROM
PCAP
and
OnCE™
JTAG
PLL
Clock
Genera tor
Internal
Data
Bus
Switch
External
Data
Bus
Switch
The DSP56311 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolutionbased algorithms.
What’s New?
Rev. 8 includes the following
changes:
• Adds lead-free packaging and
part numbers.
DSP56311 Technical Data, Rev. 8
ii Freescale Semiconductor
Table of Contents
Data Sheet Conventions .......................................................................................................................................ii
Features...............................................................................................................................................................iii
Target Applications ............................................................................................................................................. iv
Product Documentation ......................................................................................................................................iv
Chapter 1 Signals/Connections
1.1 Power ................................................................................................................................................................1-3
1.2 Ground ..............................................................................................................................................................1-3
1.3 Clock .................................................................................................................................................................1-3
1.5 External Memory Expansion Port (Port A) ......................................................................................................1-4
1.6 Interrupt and Mode Control ..............................................................................................................................1-7
1.7 Host Interface (HI08) ........................................................................................................................................1-8
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12
1.10 Serial Communication Interface (SCI) ...........................................................................................................1-13
1.11 Timers .............................................................................................................................................................1-14
1.12 JTAG and OnCE Interface ..............................................................................................................................1-15
Chapter 2 Specifications
2.1 Maximum Ratings.............................................................................................................................................2-1
2.2 Thermal Characteristics ....................................................................................................................................2-2
2.3 DC Electrical Characteristics............................................................................................................................2-3
2.4 AC Electrical Characteristics ............................................................................................................................2-4
Chapter 3 Packaging
3.1 Package Description .........................................................................................................................................3-2
3.2 MAP-BGA Package Mechanical Drawing .....................................................................................................3-10
Chapter 4 Design Considerations
4.1 Thermal Design Considerations........................................................................................................................4-1
4.2 Electrical Design Considerations ......................................................................................................................4-2
4.3 Power Consumption Considerations.................................................................................................................4-3
4.4 PLL Performance Issues ...................................................................................................................................4-4
4.5 Input (EXTAL) Jitter Requirements .................................................................................................................4-6
Appendix A Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
Indicates a signal that is active when pulled low (For example, the RESET pin is active when
low.)
“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples: Signal/Symbol Logic State Signal State Voltage
PIN
True Asserted
VIL/V
OL
PIN
False Deasserted
VIH/V
OH
PIN
True Asserted
VIH/V
OH
PIN
False Deasserted
VIL/V
OL
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
iii
Features
Tab l e 1 lists the features of the DSP56311 device.
Table 1. DSP56311 Features
Feature Description
High-Performance
DSP56300 Core
• Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering
applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTA G)
test access port (TAP)
Enhanced Filter
Coprocessor (EFCOP)
• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 150 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
Internal Peripherals
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
Internal Memories
•192 × 24-bit bootstrap ROM
•128 K × 24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
:
Program
RAM Size
Instruction
Cache Size
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
Switch
Mode
MSW1 MSW0
32 K × 24-bit 0 48 K × 24-bit 48 K × 24-bit disabled disabled 0/1 0/1
31 K × 24-bit 1024 × 24-bit 48 K × 24-bit 48 K × 24-bit enabled disabled 0/1 0/1
96 K × 24-bit 0 16 K × 24-bit 16 K × 24-bit disabled enabled 0 0
95 K × 24-bit 1024 × 24-bit 16 K × 24-bit 16 K × 24-bit enabled enabled 0 0
80 K × 24-bit 0 24 K × 24-bit 24 K × 24-bit disabled enabled 0 1
79 K × 24-bit 1024 × 24-bit 24 K × 24-bit 24 K × 24-bit enabled enabled 0 1
64 K × 24-bit 0 32 K × 24-bit 32 K × 24-bit disabled enabled 1 0
63 K × 24-bit 1024 × 24-bit 32 K × 24-bit 32 K × 24-bit enabled enabled 1 0
48 K × 24-bit 0 40 K × 24-bit 40 K × 24-bit disabled enabled 1 1
47 K × 24-bit 1024 × 24-bit 40 K × 24-bit 40 K × 24-bit enabled enabled 1 1
*Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP)
DSP56311 Technical Data, Rev. 8
iv Freescale Semiconductor
Target Applications
DSP56311 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
• Wireless and wireline infrastructure applications
• Multi-channel wireless local loop systems
• DSP resource boards
• High-speed modem banks
• IP telephony
Product Documentation
The documents listed in Table 2 are required for a complete description of the DSP56311 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
External Memory
Expansion
• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address
lines
• Program memory expansion to one 256 K × 24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
• Internal DRAM controller for glueless interface to dynamic random access memory (DRAMs) up to 100
MHz operating frequency
Power Dissipation
• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and modedependent)
Packaging
• Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Table 2. DSP56311 Documentation
Name Description Order Number
DSP56311
User’s Manual
Detailed functional description of the DSP56311 memory configuration,
operation, and register programming
DSP56311UM
DSP56300 Family
Manual
Detailed description of the DSP56300 family processor core and instruction set DSP56300FM
Application Notes Documents describing specific applications or optimized device operation
including code examples
See the DSP56311 product website
Table 1. DSP56311 Features (Continued)
Feature Description
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-1
Signals/Connections 1
The DSP56311 input and output signals are organized into functional groups as shown in Tab l e 1- 1 . Figure 1-1
diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Note:
The Clock Output (CLKOUT), BCLK, BCLK, CAS, and RAS[0–3] signals used by other DSP56300 family members
are supported by the DSP56311 at operating frequencies up to 100 MHz. Therefore, above 100 MHz, you must
enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register.
When set, the ABE bit eliminates the required set-up and hold times for
BB and BG with respect to CLKOUT. In
addition, DRAM access is not supported above 100 MHz.
Table 1-1. DSP56311 Functional Signal Groupings
Functional Group
Number of
Signals
Power (VCC) 20
Ground (GND) 66
Clock 2
PLL 3
Address bus
Port A
1
18
Data bus 24
Bus control 13
Interrupt and mode control 5
Host interface (HI08) Port B
2
16
Enhanced synchronous serial interface (ESSI) Ports C and D
3
12
Serial communication interface (SCI) Port E
4
3
Timer 3
OnCE/JTAG Port 6
Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4. Port E signals are the SCI port signals multiplexed with the GPIO signals.
5. There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see
Chapter 3).
DSP56311 Technical Data, Rev. 8
1-2 Freescale Semiconductor
Signals/Connections
Figure 1-1. Signals Identified by Functional Group
Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS
/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3. TIO[0–2] can be configured as GPIO signals.
4. CLKOUT, BCLK, BCLK
, CAS, and RAS[0–3] are valid only for operating frequencies ≤ 100 MHz.
DSP56311
24
18
External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)
2
Timers
3
PLL
OnCE/
JTAG Port
Power Inputs:
PLL
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
A[0–17]
D[0–23]
AA0/RAS0
–
AA3/RAS3
4
RD
WR
TA
BR
BG
BB
CAS
4
BCLK
4
BCLK
4
TCK
TDI
TDO
TMS
TRST
DE
CLKOUT
4
PCAP
After
Reset
NMI
V
CCP
V
CCQL
V
CCQH
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
4
Serial
Communications
Interface (SCI) Port
2
4
2
2
Grounds:
PLL
PLL
Ground plane
GND
P
GND
P1
GND
64
Interrupt/
Mode Control
MODA
MODB
MODC
MODD
RESET
Host
Interface
(HI08) Port
1
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/
HCS
Single DS
HRW
HDS
/HDS
Single HR
HREQ
/HREQ
HACK
/HACK
RXD
TXD
SCLK
SC0[0–2]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
8
3
3
EXTAL
XTAL
Clock
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)
2
SC1[0–2]
SCK1
SRD1
STD1
3
Multiplexed
Bus
HAD[0–7]
HAS
/HAS
HA8
HA9
HA10
Double DS
HRD
/HRD
HWR
/HWR
Double HR
HTRQ
/HTRQ
HRRQ
/HRRQ
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
IRQA
IRQB
IRQC
IRQD
PINIT
3
RESET
During Reset
After Reset
Reset
During
Power
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-3
1.1 Power
1.2 Ground
1.3 Clock
Table 1-2. Power Inputs
Power Name Description
V
CCP
PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the V
CC
power rail.
V
CCQL
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from
all other chip power inputs.
V
CCQH
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip
power inputs
, except
V
CCQL
.
V
CCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
to all other chip power inputs,
except
V
CCQL
.
V
CCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
other chip power inputs,
except
V
CCQL
.
V
CCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
chip power inputs,
except
V
CCQL
.
V
CCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs,
except
V
CCQL
.
V
CCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs,
except
V
CCQL
.
Note: The user must provide adequate external decoupling capacitors for all power connections.
Table 1-3. Grounds
Name Description
GND
P
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. V
CCP
should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip
package.
GND
P1
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
GND Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
Table 1-4. Clock Signals
Signal Name Type
State During
Reset
Signal Description
EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
DSP56311 Technical Data, Rev. 8
1-4 Freescale Semiconductor
Signals/Connections
1.4 PLL
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals:
A[0–17], D[0–23], AA[0–3], RD, WR, BB.
1.5.1 External Address Bus
Table 1-5. Phase-Locked Loop Signals
Signal Name Type
State During
Reset
Signal Description
CLKOUT Output Chip-driven Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
Note: At oper ating frequencies above 100 MHz, this signal produces a lowamplitude waveform that is not usable externally by other devices. Above 100
MHz, you can use the asynchronous bus arbitration option that is enabled by
the Asynchronous Bus Arbitration Enable (ABE) bit in the Operating Mode
Register. When set, the DSP enters the Asynchronous Arbitration mode,
which eliminates the BB
and BG set-up and hold time requirements with
respect to CLKOUT.
PCAP Input Input PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
CCP
.
If the PLL is not used, PCAP can be tied to V
CC
, GND, or left floating.
PINIT
NMI
Input
Input
Input PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET
deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
Table 1-6. External Address Bus Signals
Signal Name Type
State During
Reset, Stop,
or Wait
Signal Description
A[0–17] Output Tri-stated Address Bus—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
External Memory Expansion Port (Port A)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-5
1.5.2 External Data Bus
1.5.3 External Bus Control
Table 1-7. External Data Bus Signals
Signal
Name
Type
State During
Reset
State During
Stop or Wait
Signal Description
D[0–23] Input/ Output Ignored Input Last state:
Input
: Ignored
Output
:
Last value
Data Bus—When the DSP is the bus master, D[0–23] are active-high,
bidirectional input/outputs that provide the bidirectional data bus for
external program and data memory accesses. Otherwise, D[0–23]
drivers are tri-stated. If the last state is output, these lines have weak
keepers to maintain the last output state if all drivers are tri-stated.
Table 1-8. External Bus Control Signals
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
AA[0–3]
RAS[0–3]
Output
Output
Tri-stated Address Attribute—When defined as AA, these signals can be used as chip selects
or additional address lines. The default use defines a priority scheme under which
only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit
(Bit 14) of the Operating Mode Register, the priority mechanism is disabled and the
lines can be used together as four external lines that can be decoded externally into
16 chip select signals.
Row Address Strobe—When defined as RAS
, these signals can be used as RAS for
DRAM interface. These signals are tri-statable outputs with programmable polarity.
Note: DRAM access is not supported above 100 MHz.
RD
Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that is
asserted to read external memory on the data bus (D[0–23]). Otherwise, RD
is tri-
stated.
WR
Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output that is
asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals
are tri-stated.
TA
Input Ignored Input Transfer Acknowledge—If the DSP56311 is the bus master and there is no external
bus activity, or the DSP56311 is not the bus master, the TA
input is ignored. The TA
input is a data transfer acknowledge (DTACK) function that can extend an external
bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the
wait states inserted by the bus control register (BCR) by keeping TA
deasserted. In
typical operation, TA
is deasserted at the start of a bus cycle, asserted to enable
completion of the bus cycle, and deasserted before the next bus cycle. The current
bus cycle completes one clock period after TA
is deasserted. The number of wait
states is determined by the TA
input or by the BCR, whichever is longer. The BCR
sets the minimum number of wait states in external bus cycles. In order to use the TA
functionality, the BCR must be programmed to at least one wait state. A zero wait
state access cannot be extended by TA
deassertion.
At operating frequencies ≤ 100 MHz, TA
can operate synchronously (with respect to
CLKOUT) or asynchronously depending on the setting of the TAS bit in the Operating
Mode Register (OMR). If synchronous mode is selected, the user is responsible for
ensuring that TA
transitions occur synchronous to CLKOUT to ensure correct
operation. Synchronous operation is not supported above 100 MHz and the
OMR[TAS] bit must be set to synchronize the TA
signal with the internal clock.
DSP56311 Technical Data, Rev. 8
1-6 Freescale Semiconductor
Signals/Connections
BR Output Reset: Output
(deasserted)
State during Stop/Wait
depends on BRH bit
setting:
• BRH = 0: Output,
deasserted
• BRH = 1: Maintains
last state (that is, if
asserted, remains
asserted)
Bus Request—Asserted when the DSP requests bus mastership. BR
is deasserted
when the DSP no longer needs the bus. BR
may be asserted or deasserted
independently of whether the DSP56311 is a bus master or a bus slave. Bus
“parking” allows BR
to be deasserted even though the DSP56311 is the bus master.
(See the description of bus “parking” in the BB
signal description.) The bus request
hold (BRH) bit in the BCR allows BR
to be asserted under software control even
though the DSP does not need the bus. BR
is typically sent to an external bus
arbitrator that controls the priority, parking, and tenure of each master on the same
external bus. BR
is affected only by DSP requests for the external bus, never for the
internal bus. During hardware reset, BR
is deasserted and the arbitration is reset to
the bus slave state.
BG
Input Ignored Input Bus Grant—Asserted by an external bus arbitration circuit when the DSP56311
becomes the next bus master. When BG
is asserted, the DSP56311 must wait until
BB
is deasserted before taking bus mastership. When BG is deasserted, bus
mastership is typically given up at the end of the current bus cycle. This may occur in
the middle of an instruction that requires more than one external bus cycle for
execution.
The default operation of this bit requires a set-up and hold time as specified in
Chapter 2. An alternate mode can be invoked: set the asynchronous bus arbitration
enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG
and
BB
are synchronized internally. This eliminates the respective set-up and hold time
requirements but adds a required delay between the deassertion of an initial BG
input
and the assertion of a subsequent BG
input.
BB
Input/ Output Ignored Input Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
pending bus master become the bus master (and then assert the signal again). The
bus master may keep BB
asserted after ceasing bus activity regardless of whether
BR
is asserted or deasserted. Called “bus parking,” this allows the current bus master
to reuse the bus without rearbitration until another device requires the bus. BB
is
deasserted by an “active pull-up” method (that is, BB
is driven high and then released
and held high by an external pull-up resistor).
The default operation of this signal requires a set-up and hold time as specified in
Chapter 2. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the
Operating Mode Register. When this bit is set, BG
and BB are synchronized
internally. See BG
for additional information.
Note: BB
requires an external pull-up resistor.
CAS
Output Tri-stated Column Address Strobe—When the DSP is the bus master, CAS is an active-low
output used by DRAM to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM control register is cleared, the signal is tristated.
Note: DRAM access is not supported above 100 MHz.
BCLK Output Tri-stated Bus Clock
When the DSP is the bus master, BCLK is active when the ATE bit in the Operating
Mode Register is set. When BCLK is active and synchronized to CLKOUT by the
internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.
Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude
waveform that is not usable externally by other devices.
BCLK
Output Tri-stated Bus Clock Not
When the DSP is the bus master, BCLK
is the inverse of the BCLK signal. Otherwise,
the signal is tri-stated.
Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude
waveform that is not usable externally by other devices.
Table 1-8. External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
Interrupt and Mode Control
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-7
1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After
RESET
is deasserted, these inputs are hardware interrupt request lines.
Table 1-9. Interrupt and Mode Control
Signal Name Type
State During
Reset
Signal Description
MODA
IRQA
Input
Input
Schmitt-trigger
Input
Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
signal is deasserted.
External Interrupt Request A—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the STOP or WAIT
standby state and IRQA
is asserted, the processor exits the STOP or WAIT
state.
MODB
IRQB
Input
Input
Schmitt-trigger
Input
Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
signal is deasserted.
External Interrupt Request B—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQB
is asserted, the processor exits the WAIT state.
MODC
IRQC
Input
Input
Schmitt-trigger
Input
Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
signal is deasserted.
External Interrupt Request C—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQC
is asserted, the processor exits the WAIT state.
MODD
IRQD
Input
Input
Schmitt-trigger
Input
Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
signal is deasserted.
External Interrupt Request D—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQD
is asserted, the processor exits the WAIT state.
RESET
Input Schmitt-trigger
Input
Reset—Places the chip in the Reset state and resets the internal phase
generator. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET
signal is
deasserted, the initial chip operating mode is latched from the MODA, MODB,
MODC, and MODD inputs. The RESET
signal must be asserted after
powerup.
DSP56311 Technical Data, Rev. 8
1-8 Freescale Semiconductor
Signals/Connections
1.7 Host Interface (HI08)
The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety
of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs,
and DMA hardware.
1.7.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written by another
asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the
Host port). The considerations for proper operation are discussed in Table 1-10.
1.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits
in the HI08 Port Control Register.
Table 1-10. Host Port Usage Considerations
Action Description
Asynchronous read of receive byte
registers
When reading the receive byte registers, Receive register High (RXH), Receive register Middle
(RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll
the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data
in the receive byte registers is valid.
Asynchronous write to transmit byte
registers
The host interface programmer should not write to the transmit byte registers, Transmit register High
(TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register
Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees
that the transmit byte registers transfer valid data to the Host Receive (HRX) register.
Asynchronous write to host vector The host interface programmer must change the Host Vector (HV) register only when the Host
Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a
stable vector.
Table 1-11. Host Interface
Signal Name Type
State During
Reset
1,2
Signal Description
H[0–7]
HAD[0–7]
PB[0–7]
Input/Output
Input/Output
Input or Output
Ignored Input Host Data—When the HI08 is programmed to interface with a non-multiplexed
host bus and the HI function is selected, these signals are lines 0–7 of the
bidirectional Data bus.
Host Address—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, these signals are lines 0–7 of the
bidirectional multiplexed Address/Data bus.
Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port
Control Register, these signals are individually programmed as inputs or outputs
through the HI08 Data Direction Register.
Host Interface (HI08)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-9
HA0
HAS
/HAS
PB8
Input
Input
Input or Output
Ignored Input Host Address Input 0—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is line 0 of
the host address input bus.
Host Address Strobe—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is the host
address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is
programmable but is configured active-low (HAS
) following reset.
Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HA1
HA8
PB9
Input
Input
Input or Output
Ignored Input Host Address Input 1—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is line 1 of
the host address (HA1) input bus.
Host Address 8—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, this signal is line 8 of the host address
(HA8) input bus.
Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HA2
HA9
PB10
Input
Input
Input or Output
Ignored Input Host Address Input 2—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is line 2 of
the host address (HA2) input bus.
Host Address 9—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, this signal is line 9 of the host address
(HA9) input bus.
Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HCS
/HCS
HA10
PB13
Input
Input
Input or Output
Ignored Input Host Chip Select—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is the host
chip select (HCS) input. The polarity of the chip select is programmable but is
configured active-low (HCS
) after reset.
Host Address 10—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line 10 of the
host address (HA10) input bus.
Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HRW
HRD
/HRD
PB11
Input
Input
Input or Output
Ignored Input Host Read/Write—When the HI08 is programmed to interface with a single-
data-strobe host bus and the HI function is selected, this signal is the Host
Read/Write
(HRW) input.
Host Read Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the HRD
strobe Schmitt-trigger input. The polarity of the data strobe is programmable but
is configured as active-low (HRD
) after reset.
Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
Table 1-11. Host Interface (Continued)
Signal Name Type
State During
Reset
1,2
Signal Description
DSP56311 Technical Data, Rev. 8
1-10 Freescale Semiconductor
Signals/Connections
HDS/HDS
HWR
/HWR
PB12
Input
Input
Input or Output
Ignored Input Host Data Strobe—When the HI08 is programmed to interface with a single-
data-strobe host bus and the HI function is selected, this signal is the host data
strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HDS
) following reset.
Host Write Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the host write
data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HWR
) following reset.
Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HREQ
/HREQ
HTRQ
/HTRQ
PB14
Output
Output
Input or Output
Ignored Input Host Request—When the HI08 is programmed to interface with a single host
request host bus and the HI function is selected, this signal is the host request
(HREQ) output. The polarity of the host request is programmable but is
configured as active-low (HREQ
) following reset. The host request may be
programmed as a driven or open-drain output.
Transmit Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
transmit host request (HTRQ) output. The polarity of the host request is
programmable but is configured as active-low (HTRQ
) following reset. The host
request may be programmed as a driven or open-drain output.
Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HACK
/HACK
HRRQ
/HRRQ
PB15
Input
Output
Input or Output
Ignored Input Host Acknowledge—When the HI08 is programmed to interface with a single
host request host bus and the HI function is selected, this signal is the host
acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is programmable but is configured as active-low (HACK
) after
reset.
Receive Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
receive host request (HRRQ) output. The polarity of the host request is
programmable but is configured as active-low (HRRQ
) after reset. The host
request may be programmed as a driven or open-drain output.
Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Table 1-11. Host Interface (Continued)
Signal Name Type
State During
Reset
1,2
Signal Description
Enhanced Synchronous Serial Interface 0 (ESSI0)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-11
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication
with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals that implement the Freescale serial peripheral interface (SPI).
Table 1-12. Enhanced Synchronous Serial Interface 0
Signal Name Type
State During
Reset
1,2
Signal Description
SC00
PC0
Input or Output
Input or Output
Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port C 0—The default configuration following reset is GPIO input PC0. When
configured as PC0, signal direction is controlled through the Port C Direction
Register. The signal can be configured as ESSI signal SC00 through the Port C
Control Register.
SC01
PC1
Input/Output
Input or Output
Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame
sync I/O. For synchronous mode, this signal is used either for transmitter 2
output or for serial I/O flag 1.
Port C 1—The default configuration following reset is GPIO input PC1. When
configured as PC1, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SC01 through the Port
C Control Register.
SC02
PC2
Input/Output
Input or Output
Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode, and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port C 2—The default configuration following reset is GPIO input PC2. When
configured as PC2, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SC02 through the Port
C Control Register.
SCK0
PC3
Input/Output
Input or Output
Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK0 is a
clock input or output, used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port C 3—The default configuration following reset is GPIO input PC3. When
configured as PC3, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SCK0 through the Port
C Control Register.
SRD0
PC4
Input
Input or Output
Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI
Receive Shift Register. SRD0 is an input when data is received.
Port C 4—The default configuration following reset is GPIO input PC4. When
configured as PC4, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SRD0 through the
Port C Control Register.
DSP56311 Technical Data, Rev. 8
1-12 Freescale Semiconductor
Signals/Connections
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
STD0
PC5
Output
Input or Output
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD0 is an output when data is transmitted.
Port C 5—The default configuration following reset is GPIO input PC5. When
configured as PC5, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal STD0 through the Port
C Control Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Table 1-13. Enhanced Serial Synchronous Interface 1
Signal Name Type
State During
Reset
1,2
Signal Description
SC10
PD0
Input or Output
Input or Output
Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port D 0—The default configuration following reset is GPIO input PD0. When
configured as PD0, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC10 through the Port
D Control Register.
SC11
PD1
Input/Output
Input or Output
Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame
sync I/O. For synchronous mode, this signal is used either for Transmitter 2
output or for Serial I/O Flag 1.
Port D 1—The default configuration following reset is GPIO input PD1. When
configured as PD1, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC11 through the Port
D Control Register.
SC12
PD2
Input/Output
Input or Output
Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port D 2—The default configuration following reset is GPIO input PD2. When
configured as PD2, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC12 through the Port
D Control Register.
Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued)
Signal Name Type
State During
Reset
1,2
Signal Description
Serial Communication Interface (SCI)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-13
1.10 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals
such as modems.
SCK1
PD3
Input/Output
Input or Output
Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a
clock input or output used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port D 3—The default configuration following reset is GPIO input PD3. When
configured as PD3, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SCK1 through the Port
D Control Register.
SRD1
PD4
Input
Input or Output
Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI
Receive Shift Register. SRD1 is an input when data is being received.
Port D 4—The default configuration following reset is GPIO input PD4. When
configured as PD4, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SRD1 through the
Port D Control Register.
STD1
PD5
Output
Input or Output
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD1 is an output when data is being transmitted.
Port D 5—The default configuration following reset is GPIO input PD5. When
configured as PD5, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal STD1 through the Port
D Control Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Table 1-14. Serial Communication Interface
Signal Name Type
State During
Reset
1,2
Signal Description
RXD
PE0
Input
Input or Output
Ignored Input Serial Receive Data—Receives byte-oriented serial data and transfers it to the
SCI Receive Shift Register.
Port E 0—The default configuration following reset is GPIO input PE0. When
configured as PE0, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal RXD through the Port E
Control Register.
TXD
PE1
Output
Input or Output
Ignored Input Serial Transmit Data—Transmits data from the SCI Transmit Data Register.
Port E 1—The default configuration following reset is GPIO input PE1. When
configured as PE1, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal TXD through the Port E
Control Register.
Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued)
Signal Name Type
State During
Reset
1,2
Signal Description
DSP56311 Technical Data, Rev. 8
1-14 Freescale Semiconductor
Signals/Connections
1.11 Timers
The DSP56311 has three identical and independent timers. Each timer can use internal or external clocking and can
either interrupt the DSP56311 after a specified number of events (clocks) or signal an external device after
counting a specific number of internal events.
SCLK
PE2
Input/Output
Input or Output
Ignored Input Serial Clock—Provides the input or output clock used by the transmitter and/or
the receiver.
Port E 2—The default configuration following reset is GPIO input PE2. When
configured as PE2, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal SCLK through the Port
E Control Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Table 1-15. Triple Timer Signals
Signal Name Type
State During
Reset
1,2
Signal Description
TIO0 Input or Output Ignored Input Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input. When
Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
The default mode after reset is GPIO input. TIO0 can be changed to output or
configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0).
TIO1 Input or Output Ignored Input Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an
external event counter or in measurement mode, TIO1 is used as input. When
Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used
as output.
The default mode after reset is GPIO input. TIO1 can be changed to output or
configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1).
TIO2 Input or Output Ignored Input Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an
external event counter or in measurement mode, TIO2 is used as input. When
Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used
as output.
The default mode after reset is GPIO input. TIO2 can be changed to output or
configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2).
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Table 1-14. Serial Communication Interface (Continued)
Signal Name Type
State During
Reset
1,2
Signal Description
JTAG and OnCE Interface
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 1-15
1.12 JTAG and OnCE Interface
The DSP56300 family and in particular the DSP56311 support circuit-board test strategies based on the IEEE®
Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to
interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or
on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming
models, see the chapter on debugging support in the DSP56300 Family Manual.
Table 1-16. JTAG/OnCE Interface
Signal
Name
Type
State During
Reset
Signal Description
TCK Input Input Test C loc k—A test clock input signal to synchronize the JTAG test logic.
TDI Input Input Test Data Input—A test data serial input signal for test instructions and data.
TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.
TDO Output Tri-stated Test Data Output—A test data serial output signal for test instructions and
data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
TMS Input Input Test Mode Select—Sequences the test controller’s state machine. TMS is
sampled on the rising edge of TCK and has an internal pull-up resistor.
TRST
Input Input Test R eset—Initializes the test controller asynchronously. TRST has an
internal pull-up resistor. TRST
must be asserted during and after power-up
(see EB610/D for details).
DE
Input/ Output Input Debug Event—As an input, initiates Debug mode from an external command
controller, and, as an open-drain output, acknowledges that the chip has
entered Debug mode. As an input, DE
causes the DSP56300 core to finish
executing the current instruction, save the instruction pipeline information,
enter Debug mode, and wait for commands to be entered from the debug
serial input line. This signal is asserted as an output for three clock cycles
when the chip enters Debug mode as a result of a debug request or as a result
of meeting a breakpoint condition. The DE
has an internal pull-up resistor.
This signal is not a standard part of the JTAG TAP controller. The signal
connects directly to the OnCE module to initiate debug mode directly or to
provide a direct external indication that the chip has entered Debug mode. All
other interface with the OnCE module must occur through the JTAG port.
DSP56311 Technical Data, Rev. 8
1-16 Freescale Semiconductor
Signals/Connections
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 2-1
Specifications 2
The DSP56311 is fabricated in high-density CMOS with transistor-transistor logic (TTL) compatible inputs and
outputs.
2.1 Maximum Ratings
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of
another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum specification is calculated using the worst
case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never
occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum
represents a condition that can never exist.
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (for example, either GND or V
CC
).
Table 2-1. Absolute Maximum Ratings
Rating
1
Symbol Value
1, 2
Unit
Supply Voltage V
CC
–0.1 to 2.0 V
Input/Output Supply Voltage V
CCQH
–0.3 to 4.0 V
All input voltages V
IN
GND – 0.3 to V
CCQH
+ 0.3 V
Current drain per pin excluding V
CC
and GND I 10 mA
Operating temperature range T
J
–40 to +100 °C
Storage temperature T
STG
–55 to +150 °C
Notes: 1. GND = 0 V, V
CC
= 1.8 V ± 0.1 V, V
CCQH
= 3.3 V ± 0.3 V, TJ = –40°C to +100°C, CL = 50 pF
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the maximum rating may affect device reliability or cause permanent damage to the device.
3. Power-up sequence: During power-up, and throughout the DSP56311 operation, V
CCQH
voltage must always be higher or
equal to V
CC
voltage.
DSP56311 Technical Data, Rev. 8
2-2 Freescale Semiconductor
Specifications
2.2 Thermal Characteristics
Table 2-2. Thermal Characteristics
Thermal Resistance Characteristic Symbol
MAP-BGA
Value
Unit
Junction-to-ambient, natural convection, single-layer board (1s)
1,2
R
θJA
49 °C/W
Junction-to-ambient, natural convection, four-layer board (2s2p)
1,3
R
θJMA
26 °C/W
Junction-to-ambient, @200 ft/min air flow, single layer board (1s)
1,3
R
θJMA
39 °C/W
Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p)
1,3
R
θJMA
22 °C/W
Junction-to-board
4
R
θJB
14 °C/W
Junction-to-case thermal resistance
5
R
θJC
5 °C/W
Junction-to-package-top, natural convection
6
Ψ
JT
2 °C/W
Junction-to-package-top, @200 ft/min air flow
6
Ψ
JT
2 °C/W
Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
DC Electrical Characteristics
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 2-3
2.3 DC Electrical Characteristics
Table 2-3. DC Electrical Characteristics
7
Characteristics Symbol Min Typ Max Unit
Supply voltage:
•Core (V
CCQL
) and PLL (V
CCP
)
•I/O (V
CCQH
, V
CCA
, V
CCD
, V
CCC
, V
CCH
, and V
CCS
)
1.7
3.0
1.8
3.3
1.9
3.6
V
V
Input high voltage
• D[0–23], BG
, BB, TA
• MOD/IRQ1, RESET, PINIT/NMI and all
JTAG/ESSI/SCI/Timer/HI08 pins
•EXTAL
8
V
IH
V
IHP
V
IHX
2.0
2.0
0.8 × V
CCQH
—
—
—
V
CCQH
+ 0.3
V
CCQH
+ 0.3
V
CCQH
V
V
V
Input low voltage
• D[0–23], BG
, BB, TA, MOD/IRQ1, RESET, PINIT
• All JTAG/ESSI/SCI/Timer/HI08 pins
•EXTAL
8
V
IL
V
ILP
V
ILX
–0.3
–0.3
–0.3
—
—
—
0.8
0.8
0.2 × V
CCQH
V
V
V
Input leakage current I
IN
–10 — 10 µA
High impedance (off-state) input current
(@ 2.4 V / 0.4 V)
I
TSI
–10 — 10 µA
Output high voltage
•TTL (I
OH
= –0.4 mA)
5,7
•CMOS (IOH = –10 µA)
5
V
OH
2.4
V
CC
– 0.01
—
—
—
—
V
V
Output low voltage
•TTL (I
OL
= 3.0 mA, open-drain pins IOL = 6.7 mA)
5,7
•CMOS (IOL = 10 µA)
5
V
OL
—
—
—
—
0.4
0.01
V
V
Internal supply current
2
:
• In Normal mode
• In Wait mode
3
• In Stop mode
4
I
CCI
I
CCW
I
CCS
—
—
—
150
7. 5
100
—
—
—
mA
mA
µA
PLL supply current —1 2.5mA
Input capacitance
5
C
IN
— — 10 pF
Notes: 1. Refers to MODA/IRQA
, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
2. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all
inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see
Appendix A
). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark.
This reflects typical DSP applications. Typical internal supply current is measured with V
CCQP
= 3.3 V,
V
CC
= 1.8 V at TJ = 100°C.
3. To obtain these results, all inputs must be terminated (that is, not allowed to float). PLL and XTAL signals are disabled during
Stop state.
4. DC current in Stop mode is evaluated based on measurements. To obtain these results, all inputs not disconnected at Stop
mode must be terminated (that is, not allowed to float).
5. Periodically sampled and not 100 percent tested.
6. V
CCQH
= 3.3 V ± 0.3 V, V
CC
= 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
7. This characteristic does not apply to XTAL and PCAP.
8. Driving EXTAL to the low V
IHX
or the high V
ILX
value may cause additional power consumption (DC current). To minimize
power consumption, the minimum V
IHX
should be no lower than
0.9 × V
CCQH
and the maximum V
ILX
should be no higher than 0.1 × V
CCQH
.
DSP56311 Technical Data, Rev. 8
2-4 Freescale Semiconductor
Specifications
2.4 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V
and a V
IH
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of
Tab l e 2- 2. AC timing specifications, which are referenced to a device input signal, are measured in production with
respect to the 50 percent point of the respective input signal’s transition. DSP56311 output levels are measured
with the production test machine V
OL
and VOH reference levels set at 0.4 V and 2.4 V, respectively.
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15
MHz and rated speed.
2.4.1 Internal Clocks
Table 2-4. Internal Clocks
Characteristics Symbol
Expression
Min Typ Max
Internal operation frequency with PLL
enabled
f— (Ef × MF)/
(PDF × DF)
—
Internal operation frequency with PLL
disabled
f— Ef/2 —
Internal clock high period
• With PLL disabled
• With PLL enabled and MF ≤ 4
• With PLL enabled and MF > 4
T
H
—
0.49 × ET
C
×
PDF × DF/MF
0.47 × ET
C
×
PDF × DF/MF
ET
C
—
—
—
0.51 × ETC ×
PDF × DF/MF
0.53 × ET
C
×
PDF × DF/MF
Internal clock low period
• With PLL disabled
• With PLL enabled and
MF ≤ 4
• With PLL enabled and
MF > 4
T
L
—
0.49 × ET
C
×
PDF × DF/MF
0.47 × ET
C
×
PDF × DF/MF
ET
C
—
—
—
0.51 × ETC ×
PDF × DF/MF
0.53 × ET
C
×
PDF × DF/MF
Internal clock cycle time with PLL enabled T
C
—ET
C
× PDF ×
DF/MF
—
Internal clock cycle time with PLL disabled T
C
—2 × ET
C
—
Instruction cycle time I
CYC
—TC—
Notes: 1. DF = Division Factor; Ef = External frequency; ET
C
= External clock cycle; MF = Multiplication Factor;
PDF = Predivision Factor; T
C
= internal clock cycle.
2. See the PLL and Clock Generation section in the
DSP56300 Family Manual
for a details on the PLL.
AC Electrical Characteristics
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 2-5
2.4.2 External Clock Operation
The DSP56311 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are
shown in Figure 2-1.
If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by
setting XTLD (PCTL Register bit 16 = 1—see the DSP56311 User’s Manual). The external square wave source
connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship
between the
EXTAL input and the internal clock and CLKOUT.
Figure 2-1. Crystal Oscillator Circuits
Figure 2-2. External Clock Timing
Suggested Component Values:
f
OSC
= 4 MHz
R = 680 kΩ ± 10%
C = 56 pF ± 20%
Calculations were done for a 4/20 MHz crystal
with the following parameters:
•C
L
of 30/20 pF,
•C
0
of 7/6 pF,
• series resistance of 100/20 Ω, and
• drive level of 2 mW.
XTAL1
C
C
R
Fundamental Frequency
Crystal Oscillator
XTALEXTAL
f
OSC
= 20 MHz
R = 680 kΩ ± 10%
C = 22 pF ± 20%
Note: Mak e sur e tha t in
the PCTL Register:
• XTLD (bit 16) = 0
• If f
OSC
> 200 kHz,
XTLR (bit 15) = 0
EXTAL
V
ILX
V
IHX
Midpoint
Note: The midpoint is
0.5 (V
IHX
+ V
ILX
).
ET
H
ET
L
ET
C
CLKOUT with
PLL disabled
CLKOUT with
PLL enabled
7
5
7
6b
5
3
4
2
6a
DSP56311 Technical Data, Rev. 8
2-6 Freescale Semiconductor
Specifications
2.4.3 Phase Lock Loop (PLL) Characteristics
Table 2-5. Clock Operation
No. Characteristics Symbol
150 MHz
Min Max
1 Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns maximum.
Ef 0 150.0
2 EXTAL input high
1, 2
• With PLL disabled (46.7%–53.3% duty cycle6)
• With PLL enabled (42.5%–57.5% duty cycle
6
)
ET
H
3.11 ns
2.83 ns
∞
157.0 µs
3 EXTAL input low
1, 2
• With PLL disabled (46.7%–53.3% duty cycle6)
• With PLL enabled (42.5%–57.5% duty cycle
6
)
ET
L
3.11 ns
2.83 ns
∞
157.0 µs
4 EXTAL cycle time
2
• With PLL disabled
• With PLL enabled
ET
C
6.67 ns
6.67 ns
∞
273.1 µs
5 Internal clock change from EXTAL fall with PLL disabled 4.3 ns 11.0 ns
6 a.Internal clock rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or
4, PDF = 1, Ef > 15 MHz)
3,5
b. Internal clock falling edge from EXTAL falling edge with PLL enabled (MF ≤ 4, PDF
≠ 1, Ef / PDF > 15 MHz)
3,5
0.0 ns
0.0 ns
1.8 ns
1.8 ns
7 Instruction cycle time = I
CYC
= T
C
4
(see Figure 2-4) (46.7%–53.3% duty cycle)
• With PLL disabled
• With PLL enabled
I
CYC
13.33 ns
6.7 ns
∞
8.53 µs
Notes: 1. Measured at 50 percent of the input transition.
2. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and maximum MF.
3. Periodically sampled and not 100 percent tested.
4. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.
5. The skew is not guaranteed for any other MF value.
6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
Table 2-6. PLL Characteristics
Characteristics
150 MHz
Unit
Min Max
Voltage Controlled Oscillator (VCO) frequency when PLL enabled
(MF × E
f
× 2/PDF)
30 300 MHz
PLL external capacitor (PCAP pin to V
CCP
) (C
PCAP
1
)
•@ MF ≤ 4
•@ MF > 4
(580 × MF) − 100
830 × MF
(780 × MF) − 140
1470 × MF
pF
pF
Note: C
PCAP
is the value of the PLL capacitor (connected between the PCAP pin and V
CCP
) computed using the appropriate expression
listed above.
AC Electrical Characteristics
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 2-7
2.4.4 Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6
No. Characteristics Expression
150 MHz
Unit
Min Max
8 Delay from RESET assertion to all pins at reset value
3
——26.0ns
9 Required RESET
duration
4
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled (PCTL Bit 16 = 0)
• During STOP, XTAL enabled (PCTL Bit 16 = 1)
• During normal operation
Minimum:
50 × ET
C
1000 × ET
C
75000 × ET
C
75000 × ET
C
2.5 × T
C
2.5 × T
C
333.3
6.67
0.50
0.50
16.7
16.7
—
—
—
—
—
—
ns
µs
ms
ms
ns
ns
10 Delay from asynchronous RESET
deassertion to first external address
output (internal reset deassertion)
5
• Minimum
•Maximum
3.25 × TC + 2.0
20.25 × T
C
+ 10
23.7
—
—
145.0
ns
ns
13 Mode select set-up time 30.0 — ns
14 Mode select hold time 0.0 — ns
15 Minimum edge-triggered interrupt request assertion width 6.6 — ns
16 Minimum edge-triggered interrupt request deassertion width 6.6 — ns
17 Delay from IRQA
, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
Minimum:
4.25 × T
C
+ 2.0
7.25 × T
C
+ 2.0
30.4
51.0
—
—
ns
ns
18 Delay from IRQA
, IRQB, IRQC, IRQD, NMI assertion to generalpurpose transfer output valid caused by first interrupt instruction
execution
Minimum:
10 × T
C
+ 5.0 72.0 — ns
19 Delay from address output valid caused by first interrupt instruction
execute to interrupt request deassertion for level sensitive fast
interrupts
1, 7, 8
Maximum:
(WS + 3.75) × T
C
– 10.94 — Note 8 ns
20 Delay from RD
assertion to interrupt request deassertion for level
sensitive fast interrupts
1, 7, 8
Maximum:
(WS + 3.25) × T
C
– 10.94 — Note 8 ns
21 Delay from WR
assertion to interrupt request deassertion for level
sensitive fast interrupts
1, 7, 8
• DRAM for all WS
•SRAM WS = 1
•SRAM WS = 2, 3
•SRAM WS ≥ 4
Maximum:
(WS + 3.5) × T
C
– 10.94
(WS + 3.5) × T
C
– 10.94
(WS + 3) × T
C
– 10.94
(WS + 2.5) × T
C
– 10.94
—
—
—
—
Note 8
Note 8
Note 8
Note 8
ns
ns
ns
ns
24 Duration for IRQA
assertion to recover from Stop state 5.9 — ns
25 Delay from IRQA
assertion to fetch of first instruction (when exiting
Stop)
2, 3
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled
(Operating Mode Register Bit 6 = 0)
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
not enabled (Operating Mode Register Bit 6 = 1)
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
Delay)
PLC × ET
C
× PDF + (128 K −
PLC/2) × T
C
PLC × ETC × PDF + (23.75 ±
0.5) × T
C
(8.25 ± 0.5) × T
C
1.3
232.5 ns
51.7
9.1
12.3 ms
58.3
ms
ns
DSP56311 Technical Data, Rev. 8
2-8 Freescale Semiconductor
Specifications
26 Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)
2, 3
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled
(Operating Mode Register Bit 6 = 0)
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
not enabled
(Operating Mode Register Bit 6 = 1)
• PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)
Minimum:
PLC × ET
C
× PDF + (128K −
PLC/2) × T
C
PLC × ETC × PDF +
(20.5 ± 0.5) × T
C
5.5 × T
C
13.6
12.3
36.7
—
—
—
ms
ms
ns
27 Interrupt Request Rate
• HI08, ESSI, SCI, Timer
•DMA
•IRQ
, NMI (edge trigger)
•IRQ
, NMI (level trigger)
Maximum:
12 × T
C
8 × T
C
8 × T
C
12 × T
C
—
—
—
—
80.0
53.3
53.3
80.0
ns
ns
ns
ns
28 DMA Request Rate
• Data read from HI08, ESSI, SCI
• Data write to HI08, ESSI, SCI
•Timer
•IRQ
, NMI (edge trigger)
Maximum:
6 × T
C
7 × T
C
2 × T
C
3 × T
C
—
—
—
—
40.0
46.7
13.3
20.0
ns
ns
ns
ns
29 Delay from IRQA
, IRQB, IRQC, IRQD, NMI assertion to external
memory (DMA source) access address out valid
Minimum:
4.25 × T
C
+ 2.0 30.3 — ns
Notes: 1. When fast interrupts are used and IRQA
, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended
when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.
2. This timing depends on several settings:
• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL
Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the
Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,
it is not recommended, and these specifications do not guarantee timings for that case.
• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no
stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).
• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the
PCTL Bit 17 and Operating Mode Register Bit 6 settings.
• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter
completes count or PLL lock procedure completion.
• PLC value for PLL disable is 0.
• The maximum value for ET
C
is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66
MHz = 62 µs). During the stabilization period, T
C
, TH, and TL is not constant, and their width may vary, so timing may vary as
well.
3. Periodically sampled and not 100 percent tested.
4. Value depends on clock source:
• For an external clock generator, RESET
duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is
active and valid.
• For an internal oscillator, RESET
duration is measured while RESET is asserted and V
CC
is valid. The specified timing
reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal
and other components connected to the oscillator and reflects worst case conditions.
• When the V
CC
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
5. If PLL does not lose lock.
6. V
CCQH
= 3.3 V ± 0.3 V, V
CC
= 1.8 V ± 0.1 V; TJ = –40°C to +100°C, CL = 50 pF.
7. WS = number of wait states (measured in clock cycles, number of T
C
).
8. Use expression to compute maximum value.
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
No. Characteristics Expression
150 MHz
Unit
Min Max
AC Electrical Characteristics
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor 2-9
Figure 2-3. Reset Timing
Figure 2-4. External Fast Interrupt Timing
V
IH
RESET
Reset Value
First Fetch
All Pins
A[0–17]
8
9 10
A[0–17]
RD
a) First Interrupt Instruction Execution
General
Purpose
I/O
IRQA
, IRQB,
IRQC
, IRQD,
NMI
b) General-Purpose I/O
IRQA, IRQB,
IRQC
, IRQD,
NMI
WR
20
21
1917
18
First Interrupt Instruction
Execution/Fetch
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