Freescale Semiconductor CPU32 Reference Manual
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CPU32
REFERENCE MANUAL
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PREFACE
This reference manual describes programming and operation of the CPU32 instruction processing module, found in the M68300 Family of embedded controllers.
It is part of a multivolume set of manuals — each volume corresponds to a major
module in the M68300 Family.
A user's manual for each device incorporating the CPU32 describes processor
function and operation with reference to other modules within the device.
This manual consists of the following sections and appendix:
Section 1 Overview
Section 2 Architecture Summary
Section 3 Data Organization and Addressing Capabilities
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Section 4 Instruction Set
Section 5 Processing States
Section 6 Exception Processing
Section 7 Development Support
Section 8 Instruction Execution Timing
Appendix A M68000 Family Summary
Index
NOTE
In this manual, the terms assertion and negation specifya particular
logic state.
Negate and negation refer to an inactive or false signal. These
terms are used independently of the voltage level that they represent.
This manual is written for systems designers, systems programmers, and applications programmers. Systems designers need general knowledge of the entire volume, with particular emphasis on Section 1, Section 7, and Appendix A — they will
also need to be familiar with electrical specifications and mechanical data contained in the user’s manual. Systems programmers should become familiar with
Sections 1 through 6, Section 8, and Appendix A. Applications programmers can
find most of the information they need in Sections 1 through 5, Section 8, and Appendix A.
Assert and assertion refer to an active or true signal.
This manual is also written for users of the M68000 Family that are not familiar with
the CPU32. Although there are comparative references to other Motorola microprocessors throughout the manual, Section 1, Section 2, and Appendix A specifically identify the CPU32 within the M68000 Family, and discuss the differences
betweeen it and related devices.
CPU32 REFERENCE MANUAL MOTOROLA
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MOTOROLA CPU32 REFERENCE MANUAL
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TABLE OF CONTENTS
Paragraph Title Page
SECTION 1 OVERVIEW
1.1 Features ....................................................................................................1-1
1.1.1 Virtual Memory ..................................................................................1-2
1.1.2 Loop Mode Instruction Execution ......................................................1-2
1.1.3 Vector Base Register ........................................................................1-3
1.1.4 Exception Handling ...........................................................................1-3
1.1.5 Enhanced Addressing Modes ...........................................................1-4
1.1.6 Instruction Set ...................................................................................1-4
1.1.6.1 Table Lookup and Interpolation Instructions .............................1-4
1.1.6.2 Low-Power Stop Instruction ......................................................1-6
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1.1.7 Processing States .............................................................................1-6
1.1.8 Privilege States .................................................................................1-6
1.2 Block Diagram ...........................................................................................1-6
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SECTION 2ARCHITECTURE SUMMARY
2.1 Programming Model ..................................................................................2-1
2.2 Registers ...................................................................................................2-2
2.3 Data Types ................................................................................................2-3
2.3.1 Organization in Registers ..................................................................2-4
2.3.1.1 Data Registers ..........................................................................2-4
2.3.1.2 Address Registers .....................................................................2-5
2.3.1.3 Control Registers ......................................................................2-5
2.3.2 Organization in Memory ....................................................................2-6
SECTION 3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES
3.1 Program and Data References ..................................................................3-1
3.2 Notation Conventions ................................................................................3-2
3.3 Implicit Reference ......................................................................................3-2
3.4 Effective Address ......................................................................................3-3
3.4.1 Register Direct Mode .........................................................................3-3
3.4.1.1 Data Register Direct ..................................................................3-3
3.4.1.2 Address Register Direct ............................................................3-3
3.4.2 Memory Addressing Modes ...............................................................3-4
3.4.2.1 Address Register Indirect ..........................................................3-4
3.4.2.2 Address Register Indirect With Postincrement ..........................3-4
3.4.2.3 Address Register Indirect With Predecrement ..........................3-4
3.4.2.4 Address Register Indirect With Displacement ...........................3-5
3.4.2.5 Address Register Indirect With Index (8-Bit Displacement) ......3-5
3.4.2.6 Address Register Indirect With Index (Base Displacement) .....3-6
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Paragraph Title Page
3.4.3 Special Addressing Modes ................................................................3-7
3.4.3.1 Program Counter Indirect With Displacement ...........................3-7
3.4.3.2 Program Counter Indirect with Index (8-Bit Displacement) .......3-7
3.4.3.3 Program Counter Indirect with Index (Base Displacement) ......3-8
3.4.3.4 Absolute Short Address ............................................................3-8
3.4.3.5 Absolute Long Address .............................................................3-9
3.4.3.6 Immediate Data .........................................................................3-9
3.4.4 Effective Address Encoding Summary ..............................................3-9
3.5 Programming View of Addressing Modes ...............................................3-11
3.5.1 Addressing Capabilities ...................................................................3-11
3.5.2 General Addressing Mode Summary ..............................................3-14
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3.6 M68000 Family Addressing Capability ....................................................3-14
3.7 Other Data Structures .............................................................................3-15
3.7.1 System Stack ..................................................................................3-15
3.7.2 User Stacks .....................................................................................3-16
3.7.3 Queues ............................................................................................ 3-17
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SECTION 4 INSTRUCTION SET
4.1 M68000 Family Compatibility ....................................................................4-1
4.1.1 New Instructions ................................................................................4-1
4.1.1.1 Low-Power Stop (LPSTOP) ......................................................4-1
4.1.1.2 Table Lookup and Interpolation (TBL) .......................................4-2
4.1.2 Unimplemented Instructions ..............................................................4-2
4.2 Instruction Format .....................................................................................4-2
4.2.1 Notation ............................................................................................. 4-3
4.3 Instruction Summary .................................................................................4-5
4.3.1 Condition Code Register ...................................................................4-5
4.3.2 Data Movement Instructions ..............................................................4-6
4.3.3 Integer Arithmetic Operations ............................................................4-7
4.3.4 Logic Instructions ..............................................................................4-8
4.3.5 Shift and Rotate Instructions .............................................................4-9
4.3.6 Bit Manipulation Instructions .............................................................4-9
4.3.7 Binary-Coded Decimal (BCD) Instructions ......................................4-10
4.3.8 Program Control Instructions ...........................................................4-10
4.3.9 System Control Instructions ............................................................4-11
4.3.10 Condition Tests ...............................................................................4-12
4.4 Instruction Details ....................................................................................4-13
4.5 Instruction Format Summary .................................................................4-170
4.6 Table Lookup and Interpolation Instructions .........................................4-188
4.6.1 Table Example 1: Standard Usage ...............................................4-188
4.6.2 Table Example 2: Compressed Table ...........................................4-189
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Paragraph Title Page
4.6.3 Table Example 3: 8-Bit Independent Variable ...............................4-191
4.6.4 Table Example 4: Maintaining Precision .......................................4-192
4.6.5 Table Example 5: Surface Interpolations ......................................4-194
4.7 Nested Subroutine Calls ........................................................................4-194
4.8 Pipeline Synchronization with the NOP Instruction ...............................4-194
SECTION 5PROCESSING STATES
5.1 State Transitions .......................................................................................5-1
5.2 Privilege Levels .........................................................................................5-1
5.2.1 Supervisor Privilege Level .................................................................5-2
5.2.2 User Privilege Level ..........................................................................5-2
5.2.3 Changing Privilege Level ...................................................................5-2
5.3 Types of Address Space ...........................................................................5-3
5.3.1 CPU Space Access ..........................................................................5-3
5.3.1.1 Type 0000 — Breakpoint ..........................................................5-4
5.3.1.2 Type 0001 — MMU Access ......................................................5-4
5.3.1.3 Type 0010 — Coprocessor Access ...........................................5-4
5.3.1.4 Type 0011 — Internal Register Access .....................................5-4
5.3.1.5 Type 1111 — Interrupt Acknowledge ........................................5-5
SECTION 6 EXCEPTION PROCESSING
6.1 Definition of Exception Processing ............................................................6-1
6.1.1 Exception Vectors .............................................................................6-1
6.1.2 Types of Exceptions ..........................................................................6-2
6.1.3 Exception Processing Sequence .......................................................6-3
6.1.4 Exception Stack Frame .....................................................................6-3
6.1.5 Multiple Exceptions ...........................................................................6-4
6.2 Processing of Specific Exceptions ............................................................6-5
6.2.1 Reset ................................................................................................. 6-5
6.2.2 Bus Error ...........................................................................................6-6
6.2.3 Address Error ....................................................................................6-7
6.2.4 Instruction Traps ................................................................................6-8
6.2.5 Software Breakpoints ........................................................................6-8
6.2.6 Hardware Breakpoints .......................................................................6-8
6.2.7 Format Error ......................................................................................6-9
6.2.8 Illegal or Unimplemented Instructions ...............................................6-9
6.2.9 Privilege Violations ..........................................................................6-10
6.2.10 Tracing ............................................................................................6-11
6.2.11 Interrupts .........................................................................................6-12
6.2.12 Return from Exception .....................................................................6-13
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TABLE OF CONTENTS
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Paragraph Title Page
6.3 Fault Recovery ........................................................................................6-14
6.3.1 Types of Faults ................................................................................6-16
6.3.1.1 Type I: Released Write Faults .................................................6-16
6.3.1.2 Type II: Prefetch, Operand, RMW, and MOVEP Faults ..........6-17
6.3.1.3 Type III: Faults During MOVEM Operand Transfer .................6-17
6.3.1.4 Type IV: Faults During Exception Processing .........................6-18
6.3.2 Correcting a Fault ............................................................................6-18
6.3.2.1 (Type I) Completing Released Writes via Software ................6-19
6.3.2.2 (Type I) Completing Released Writes via RTE .......................6-19
6.3.2.3 (Type II) Correcting Faults via RTE .........................................6-19
6.3.2.4 (Type III) Correcting Faults via Software .................................6-20
6.3.2.5 (Type III) Correcting Faults By Conversion and Restart .........6-20
6.3.2.6 (Type III) Correcting Faults via RTE ........................................6-21
6.3.2.7 (Type IV) Correcting Faults via Software ................................6-21
6.4 CPU32 Stack Frames ..............................................................................6-21
6.4.1 Normal Four-Word Stack Frame .....................................................6-22
6.4.2 Normal Six-Word Stack Frame ........................................................6-22
6.4.3 BERR Stack Frame .........................................................................6-22
SECTION 7 DEVELOPMENT SUPPORT
7.1 CPU32 Integrated Development Support ..................................................7-1
7.1.1 Background Debug Mode (BDM) Overview ......................................7-1
7.1.2 Deterministic Opcode Tracking Overview .........................................7-2
7.1.3 On-Chip Hardware Breakpoint Overview ..........................................7-3
7.2 Background Debug Mode (BDM) ..............................................................7-3
7.2.1 Enabling BDM ...................................................................................7-4
7.2.2 BDM Sources ....................................................................................7-4
7.2.2.1 External BKPT Signal ................................................................7-4
7.2.2.2 BGND Instruction ......................................................................7-4
7.2.2.3 Double Bus Fault .......................................................................7-5
7.2.2.4 Peripheral Breakpoints ..............................................................7-5
7.2.3 Entering BDM ....................................................................................7-5
7.2.4 Command Execution .........................................................................7-5
7.2.5 Background Mode Registers .............................................................7-6
7.2.5.1 Fault Address Register (FAR) ...................................................7-6
7.2.5.2 Return Program Counter (RPC) ................................................7-6
7.2.5.3 Current Instruction Program Counter (PCC) .............................7-7
7.2.6 Returning from BDM ..........................................................................7-7
7.2.7 Serial Interface ..................................................................................7-7
7.2.7.1 CPU Serial Logic .......................................................................7-8
7.2.7.2 Development System Serial Logic ..........................................7-10
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TABLE OF CONTENTS
(Continued)
Paragraph Title Page
7.2.8 Command Set .................................................................................7-11
7.2.8.1 Command Format ...................................................................7-11
7.2.8.2 Command Sequence Diagram ................................................7-12
7.2.8.3 Command Set Summary .........................................................7-14
7.2.8.4 Read A/D Register (RAREG/RDREG) ....................................7-15
7.2.8.5 Write A/D Register (WAREG/WDREG) ...................................7-15
7.2.8.6 Read System Register (RSREG) ............................................7-16
7.2.8.7 Write System Register (WSREG) ...........................................7-16
7.2.8.8 Read Memory Location (READ) ..............................................7-17
7.2.8.9 Write Memory Location (WRITE) ............................................7-18
7.2.8.10 Dump Memory Block (DUMP) .................................................7-19
7.2.8.11 Fill Memory Block (FILL) .........................................................7-21
7.2.8.12 Resume Execution (GO) .........................................................7-22
7.2.8.13 Call User Code (CALL) ...........................................................7-22
7.2.8.14 Reset Peripherals (RST) .........................................................7-24
7.2.8.15 No Operation (NOP) ................................................................7-24
7.2.8.16 Future Commands ..................................................................7-25
7.3 Deterministic Opcode Tracking ...............................................................7-25
7.3.1 Instruction Fetch (IFETCH) .............................................................7-25
7.3.2 Instruction Pipe (IPIPE) ...................................................................7-25
7.3.3 Opcode Tracking during Loop Mode ...............................................7-27
SECTION 8 INSTRUCTION EXECUTION TIMING
8.1 Resource Scheduling ................................................................................8-1
8.1.1 Microsequencer ................................................................................. 8-1
8.1.2 Instruction Pipeline ............................................................................8-2
8.1.3 Bus Controller Resources .................................................................8-2
8.1.3.1 Prefetch Controller ....................................................................8-3
8.1.3.2 Write-Pending Buffer .................................................................8-3
8.1.3.3 Microbus Controller ...................................................................8-3
8.1.4 Instruction Execution Overlap ...........................................................8-4
8.1.5 Effects of Wait States ........................................................................8-5
8.1.6 Instruction Execution Time Calculation .............................................8-5
8.1.7 Effects of Negative Tails ....................................................................8-6
8.2 Instruction Stream Timing Examples .........................................................8-7
8.2.1 Timing Example 1: Execution Overlap ..............................................8-7
8.2.2 Timing Example 2: Branch Instructions .............................................8-8
8.2.3 Timing Example 3: Negative Tails .....................................................8-9
8.3 Instruction Timing Tables ........................................................................8-10
8.3.1 Fetch Effective Address ..................................................................8-12
8.3.2 Calculate Effective Address ............................................................8-13
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8.3.3 MOVE Instruction ............................................................................8-14
8.3.4 Special-Purpose MOVE Instruction .................................................8-14
8.3.5 Arithmetic/Logic Instructions ...........................................................8-15
8.3.6 Immediate Arithmetic/Logic Instructions ..........................................8-17
8.3.7 Binary-Coded Decimal and Extended Instructions ..........................8-18
8.3.8 Single Operand Instructions ............................................................8-18
8.3.9 Shift/Rotate Instructions ..................................................................8-19
8.3.10 Bit Manipulation Instructions ...........................................................8-20
8.3.11 Conditional Branch Instructions .......................................................8-20
8.3.12 Control Instructions .........................................................................8-21
8.3.13 Exception-Related Instructions and Operations ..............................8-21
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8.3.14 Save and Restore Operations .........................................................8-22
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APPENDIX AM68000 FAMILY SUMMARY
INDEX
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LIST OF ILLUSTRATIONS
Figure Title Page
1-1 Loop Mode Instruction Sequence ...................................................................1-3
1-2 CPU32 Block Diagram ................................................................................... 1-7
2-1 User Programming Model .............................................................................. 2-2
2-2 Supervisor Programming Model Supplement .................................................2-2
2-3 Status Register ............................................................................................... 2-3
2-4 Data Organization in Data Registers .............................................................. 2-4
2-5 Address Organization in Address Registers ...................................................2-5
2-6 Memory Operand Addressing ........................................................................ 2-7
3-1 Single-Effective-Address Instruction Operation Word ....................................3-1
3-2 Effective Address Specification Formats ...................................................... 3-10
3-3 Using SIZE in the Index Selection ................................................................ 3-12
3-4 Using Absolute Address with Indexes ..........................................................3-12
3-5 Addressing Array Items ................................................................................3-13
3-6 M68000 Family Address Extension Words .................................................. 3-15
4-1 Instruction Word General Format ...................................................................4-2
4-2 Instruction Description Format ..................................................................... 4-14
4-3 Table Example 1 ........................................................................................ 4-188
4-4 Table Example 2 ........................................................................................ 4-189
4-5 Table Example 3 ........................................................................................ 4-191
6-1 Exception Stack Frame .................................................................................. 6-4
6-2 Reset Operation Flowchart .............................................................................6-6
6-3 Format $0 — Four-Word Stack Frame ......................................................... 6-22
6-4 Format $2 — Six-Word Stack Frame ........................................................... 6-22
6-5 Internal Transfer Count Register ..................................................................6-23
6-6 Format $C — BERR Stack for Prefetches and Operands ............................6-24
6-7 Format $C — BERR Stack on MOVEM Operand ........................................ 6-24
6-8 Format $C — Four- and Six-Word BERR Stack .......................................... 6-24
7-1 In-Circuit Emulator Configuration ................................................................... 7-2
7-2 Bus State Analyzer Configuration .................................................................. 7-2
7-3 BDM Block Diagram .......................................................................................7-3
7-4 BDM Command Execution Flowchart ............................................................ 7-6
7-5 Debug Serial I/O Block Diagram .................................................................... 7-8
7-6 Serial Interface Timing Diagram ..................................................................... 7-9
7-7 BKPT Timing for Single Bus Cycle ............................................................... 7-10
7-8 BKPT Timing for Forcing BDM .....................................................................7-10
7-9 BKPT/DSCLK Logic Diagram ....................................................................... 7-11
7-10 Command-Sequence-Diagram Example ...................................................... 7-13
7-11 Functional Model of Instruction Pipeline ....................................................... 7-26
7-12 Instruction Pipeline Timing Diagram ............................................................. 7-26
8–1 Block Diagram of Independent Resources .....................................................8-2
8-2 Simultaneous Instruction Execution ............................................................... 8-4
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LIST OF ILLUSTRATIONS
(Continued)
Figure Title Page
8–3 Attributed Instruction Times ............................................................................ 8-4
8-4 Example 1 — Instruction Stream ....................................................................8-7
8-5 Example 2 — Branch Taken .......................................................................... 8-8
8-6 Example 2 — Branch Not Taken .................................................................... 8-8
8-7 Example 3 — Branch Negative Tail ............................................................... 8-9
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LIST OF TABLES
Table Title Page
1-1 Instruction Set Summary ....................................................................................... 1-5
3-1 Effective Addressing Mode Categories................................................................ 3-11
4-1 Condition Code Computations...............................................................................4-5
4-2 Data Movement Operations...................................................................................4-6
4-3 Integer Arithmetic Operations................................................................................ 4-7
4-4 Logic Operations.................................................................................................... 4-8
4-5 Shift and Rotate Operations .................................................................................. 4-9
4-6 Bit Manipulation Operations................................................................................ 4-10
4-7 Binary-Coded Decimal Operations...................................................................... 4-10
4-8 Program Control Operations................................................................................4-10
4-9 System Control Operations.................................................................................. 4-11
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4-10 Condition Tests..................................................................................................4-12
4-11 Operation Code Map ....................................................................................... 4-170
5-1 Address Spaces..................................................................................................... 5-3
6-1 Exception Vector Assignments.............................................................................. 6-2
6-2 Exception Priority Groups...................................................................................... 6-4
6-3 Tracing Control....................................................................................................6-11
7-1 BDM Source Summary.......................................................................................... 7-4
7-2 Polling the BDM Entry Source............................................................................... 7-5
7-3 CPU Generated Message Encoding...................................................................... 7-8
7-4 BDM Command Summary...................................................................................7-14
A-1 M68000 instruction Set Extensions.......................................................................A-3
A-2 M68000 Addressing Modes...................................................................................A-4
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LIST OF TABLES
(Continued)
Table Title Page
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SECTION 1 OVERVIEW
The CPU32, the first-generation instruction processing module of the M68300 Family,
is based on the industry-standard MC68000 processor. It has many features of the
MC68010 and MC68020, as well as unique features suited for high-performance controller applications. The CPU32 is source code and binary code compatible with the
M68000 Family.
CPU32 power consumption during normal operation is low because it is a high-speed
complementary metal-oxide semiconductor (HCMOS) device. Power consumption
can be reduced to a minimum during periods of inactivity by executing the low-power
stop (LPSTOP) instruction, which shuts down the CPU32 and other intermodule bus
(IMB) submodules.
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Ease of programming is an important consideration in using a microcontroller. The
CPU32 instruction format reflects a predominately register-memory interaction philosophy. All data resources are available to all operations requiring those resources.
There are eight multifunction data registers and seven general-purpose addressing
registers. The data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long
word) operand lengths for all operations. Address manipulation is supported by word
and long-word operations. Although the program counter (PC) and stack pointers (SP)
are special purpose registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level.
As controller applications become more complex and control programs become larger,
high-level language (HLL) will become the system designer's choice in programming
languages. HLL aids rapid development of complex algorithms, with less error, and is
readily portable. The CPU32 instruction set will efficiently support HLL.
1.1 Features
Features of the CPU32 are as follows:
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• Fully Upward Object Code Compatible with M68000 Family
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Fast Multiply, Divide, and Shift Instructions
• Fast Bus Interface with Dynamic Bus Port Sizing
• Improved Exception Handling for Controller Applications
• Enhanced Addressing Modes
— Scaled Index
— Address Register Indirect with Base Displacement and
— Expanded PC Relative Modes
— 32-Bit Branch Displacements
• Instruction Set Enhancements
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OVERVIEW
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— High-Precision Multiply and Divide
— Trap On Condition Codes
— Upper and Lower Bounds Checking
• Enhanced Breakpoint Instruction
• Trace on Change of Flow
• Table Lookup and Interpolate Instruction
• Low-Power Stop Instruction
• Hardware Breakpoint Signal, Background Mode
• 16.77-MHz Operating Frequency (–40 to 125
• Fully Static Implementation
1.1.1 Virtual Memory
A system that supports virtual memory has a limited amount of high-speed physical
memory that can be accessed directly by the processor and maintains an image of a
much larger “virtual” memory on a secondary storage device. When the processor attempts to access a location in the virtual memory map that is not resident in physical
memory, a page fault occurs. The access to that location is temporarily suspended
while the necessary data is fetched from secondary storage and placed in physical
memory. The suspended access is then restarted or continued. The CPU32 uses instruction restart, which requires that only a small portion of the internal machine state
be saved. After correcting the fault, the machine state is restored, and the instruction
is refetched and restarted. This process is completely transparent to the application
program.
1.1.2 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive. To increase the performance of
the CPU32, a loop mode has been added to the processor. The loop mode is used by
any single-word instruction that does not change the program flow. Loop mode is implemented in conjunction with the DBcc instruction.
form of an instruction loop for the processor to enter loop mode.
Loop mode is entered when DBcc is executed and loop displacement is –4. Once in
loop mode, the processor performs only data cycles associated with the instruction
and suppresses instruction fetches. Termination condition and count are checked after
each execution of looped instruction data operations. The CPU automatically exits
loop mode for interrupts or other exceptions.
C)
Figure 1-1 shows the required
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ONE-WORD INSTRUCTION
DBcc
DBcc DISPLACEMENT
$FFFC = –4
Figure 1-1 Loop Mode Instruction Sequence
1.1.3 Vector Base Register
The vector base register (VBR) contains the base address of the 1024-byte exception
vector table. The table contains 256 exception vectors. Exception vectors are the
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memory addresses of routines that begin execution at the completion of exception processing. Each routine performs operations appropriate to the corresponding exception. Because exception vectors are memory addresses, each table entry is a single
long word.
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Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device; others are supplied automatically by the processor.
The processor multiplies the vector number by four to calculate vector offset, then
adds the offset to the VBR base address. The sum is the memory address of the vector.
Because the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task executed by an
operating system. Details of exception processing are provided in
SECTION 6 EX-
CEPTION PROCESSING
1.1.4 Exception Handling
The processing of an exception occurs in four steps, with variations for different exception causes. During the first step, a temporary internal copy of the status register
is made, and the status register is set for exception processing. During the second
step, the exception vector is determined. During the third step, the current processor
context is saved. During the fourth step, a new context is obtained, and the processor
then proceeds with normal instruction execution.
Exception processing saves the most volatile portion of the current context by pushing
it on the supervisor stack. This context is organized in a format called an exception
stack frame. The stack frame always includes the status register and program counter
at the time an exception occurs. To support generic handlers, the processor also places the vector offset in the exception stack frame and marks the frame with a format
code. The return-from-exception (RTE) instruction uses the format code to determine
what information is on the stack, so that context can be properly restored.
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1.1.5 Enhanced Addressing Modes
Addressing in the CPU32 is register oriented. Most instructions allow the results of the
specified operation to be placed either in a register or in memory. There is no need for
extra instructions to store register contents in memory.
There are seven basic addressing modes:
1. Register Direct
2. Register Indirect
3. Register Indirect with Index
4. Program Counter Indirect with Displacement
5. Program Counter Indirect with Index
6. Absolute
7. Immediate
The register indirect addressing modes include postincrement, predecrement, and offset capability. The PC relative mode also has index and offset capabilities. In addition
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to the addressing modes, many instructions implicitly specify the use of a status register, SP, and/or PC. Addressing is explained fully in
TION AND ADDRESSING CAPABILITIES
modes is found in
APPENDIX A M68000 FAMILY SUMMARY .
. A summary of M68000 Family addressing
SECTION 3 DATA ORGANIZA-
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1.1.6 Instruction Set
The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 1-
1). Two new instructions have been added to facilitate controller applications — lowpower stop (LPSTOP) and table lookup and interpolate (TBL). The following M68020
instructions
The CPU32 traps on unimplemented instructions and illegal effective addressing
modes, allowing the user to emulate instructions or to define special-purpose functions. However, Motorola reserves the right to use all currently uniplemented instructions operation codes for future M68000 core enhancements.
SECTION 4 INSTRUCTION SET for comprehensive information.
See
1.1.6.1 Table Lookup and Interpolation Instructions
are not implemented on the CPU32:
BFxxx — Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO
BFINS, BFSET, BFTST)
CALLM, RTM — Call Module, Return Module
CAS, CAS2 — Compare and Set (Read-Modify-Write Instructions)
cpxxx Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cp RESTORE,
cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK Pack, Unpack BCD Instructions
To speed up real-time applications, a range of discrete data points is often precalculated from a continuous control function, then stored in memory. A full range of data
can require an inordinate amount of memory. The table instructions make it possible
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to store a sample of the full range and recover intermediate values quickly via linear
interpolation. A round-to-nearest algorithm can be applied to the results.
Table 1-1 Instruction Set Summary
Mnemonic Description Mnemonic Description
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
Bcc
BCHG
BCLR
BGND
BKPT
BRA
BSET
BSR
BTST
CHK, CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EXG
EXT, EXTB
LEA
LINK
LPSTOP
LSL, LSR
ILLEGAL Take Illegal Instruction Trap
JMP
JSR
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Background
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Check Register Against Upper
and Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against
Upper and Lower Bounds
Test Condition, Decrement and
Branch
Signed Divide
Unsigned Divide
Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend
Load Effective Address
Link and Allocate
Low Power Stop
Logical Shift Left and Right
Jump
Jump to Subroutine
MOVE
MOVE CCR
MOVE SR
MOVE USP
MOVEA
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS, MULS.L
MULU, MULU.L
NBCD
NEG
NEGX
NOP
OR
ORI
PEA Push Effective Address
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TBLS, TBLSN
TBLU, TBLUN
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK Unlink
Move
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Address
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Inclusive OR
Logical Inclusive OR Immediate
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and
Right
Return and Deallocate
Return from Exception
Return and Restore Codes
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Table Lookup and Interpolate
(Signed)
Table Lookup and Interpolate
(Unsigned)
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
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1.1.6.2 Low-Power Stop Instruction
The CPU32 is a fully static design. Power consumption can be reduced to a minimum
during periods of inactivity by stopping the system clock. The CPU32 instruction set
includes a low-power stop command (LPSTOP) that efficiently implements this capability. The processor will remain in stop mode until a user-specified interrupt, or reset,
occurs.
1.1.7 Processing States
There are four processing states — normal, exception, background and halted.
Normal processing is associated with instruction execution. The bus is used to fetch
instructions and operands, and to store results.
Exception processing is associated with interrupts, trap instructions, tracing, and other
exception conditions.
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Background processing allows interactive debugging of the system.
Halted processing is an indication of catastrophic hardware failure.
SECTION 5 PROCESSING STATES for complete information.
See
1.1.8 Privilege States
The processor can operate at either of two privilege levels. Supervisor level is more
privileged than user level — all instructions are available at supervisor level, but access is restricted at user level.
Effective use of privilege level can protect system resources from uncontrolled access.
The state of the S bit in the status register determines access level and whether the
stack pointer (USP) or the supervisor stack pointer (SSP) is used for stack operations.
SECTION 5 PROCESSING STATES for a complete explanation of privilege lev-
See
els.
1.2 Block Diagram
A block diagram of the CPU32 is shown in Figure 1-2 . The functional elements operate concurrently. Essential synchronization of instruction execution and buss operation is maintained by the sequencer/control unit. The bus controller prefetches
instructions and operands. A three-stage pipeline is used to hold and decode instructions prior to execution. The execution unit maintains the program counter under sequencer control. The bus control contains a write-pending buffer that allows the
sequencer to continue execution of instructions after a request for a write cycle is
queued. See
nation of instruction execution.
SECTION 8 INSTRUCTION EXECUTION TIMING for a detailed expla-
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SEQUENCER
CONTROL
UNIT
DATA BUS
ADDRESS BUS
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16
EXECUTION
UNIT
32
INSTRUCTION
PIPELINE
AND
DECODE
BUS
CONTROL
BUS CONTROL
Figure 1-2 CPU32 Block Diagram
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SECTION 2ARCHITECTURE SUMMARY
The CPU32 is upward source and object code compatible with the MC68000 and
MC68010. It is downward source and object code compatible with the MC68020. Within the M68000 Family, architectural differences are limited to the supervisory operating
state. User state programs can be executed unchanged on upward compatible devices.
The major CPU32 features are as follows:
• 32-Bit Internal Data Path and Arithmetic Hardware
• 32-Bit Address Bus Supported by 32-Bit Calculations
• Rich Instruction Set
• Eight 32-Bit General-Purpose Data Registers
• Seven 32-Bit General-Purpose Address Registers
• Separate User and Supervisor Stack Pointers
• Separate User and Supervisor State Address Spaces
• Separate Program and Data Address Spaces
• Many Data Types
• Flexible Addressing Modes
• Full Interrupt Processing
• Expansion Capability
2.1 Programming Model
The CPU32 programming model consists of two groups of registers that correspond
to the user and supervisor privilege levels. User programs can only use the registers
of the user model. The supervisor programming model, which supplements the user
programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of
MC68010 and later processors.
The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit
program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status
register, two alternate function code registers, and a 32-bit vector base register (see
Figure 2-1 and Figure 2-2 ).
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31 16 15 8 7 0
31 16 15 0
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31 16 15 0
31 0
D0
D1
D2
D3 DATA REGISTERS
D4
D5
D6
D7
A0
A1
A2
A3 ADDRESS REGISTERS
A4
A5
A6
A7 (USP) USER STACK POINTER
PC PROGRAM COUNTER
15 8 7 0
0 CCR CONDITION CODE REGISTER
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Figure 2-1 User Programming Model
31 16 15 0
A7' (SSP) SUPERVISOR STACK
15 8 7 0
(CCR) SR STATUS REGISTER
31 0
PC VECTOR BASE REGISTER
31 3 2 0
SFC ALTERNATE FUNCTION
DFC CODE REGISTERS
POINTER
Figure 2-2 Supervisor Programming Model Supplement
2.2 Registers
Registers D7 to D0 are used as data registers for bit, byte (8-bit), word (16-bit), longword (32-bit), and quad-word (64-bit) operations. Registers A6 to A0 and the user and
supervisor stack pointers are address registers that may be used as software stack
pointers or base address registers. Register A7 (shown as A7 and A7' in
Figure 2-1 )
is a register designation that applies to the user stack pointer in the user privilege level
and to the supervisor stack pointer in the supervisor privilege level. In addition, address registers may be used for word and long-word operations. All of the 16 generalpurpose registers (D7 to D0, A7 to A0) may be used as index registers.
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The program counter (PC) contains the address of the next instruction to be executed
by the CPU32. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate.
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The status register (SR) (see
Figure 2-3 ) contains condition codes, an interrupt prior-
ity mask (three bits), and three control bits. Condition codes reflect the results of a previous operation. The codes are contained in the low byte, or condition code register of
the SR. The interrupt priority mask determines the level of priority an interrupt must
have in order to be acknowledged. The control bits determine trace mode and privilege
level. At user privilege level, only the condition code register is available. At supervisor
privilege level, software can access the full status register.
SYSTEM BYTE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C
TRACE
ENABLE
SUPERVISOR/USER
S TATE
INTERRUPT
PRIORITY MASK
USER BYTE
(CONDITION CODE REGISTER)
EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
Figure 2-3 Status Register
The vector base register (VBR) contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this
register to access the vector table.
Alternate function code registers SFC and DFC contain 3-bit function codes. The
CPU32 generates a function code each time it accesses an address. Specific codes
are assigned to each type of access. The codes can be used to select eight dedicated
4G-byte address spaces. The MOVE instructions can use registers SFC and DFC to
specify the function code of a memory address.
2.3 Data Types
Six basic data types are supported:
1. Bits
2. Binary-Coded Decimal (BCD) Digits
3. Byte Integers (8 bits)
4. Word Integers (16 bits)
5. Long-Word Integers (32 bits)
6. Quad-Word Integers (64 bits)
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2.3.1 Organization in Registers
The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits and addresses of 16 or 32 bits. The seven address registers and the two stack pointers are
used for address operands of 16 or 32 bits. The PC is 32 bits wide.
2.3.1.1 Data Registers
Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word
operands, the low-order 16 bits, and long-word operands, the entire 32 bits. When a
data register is used as either a source or destination operand, only the appropriate
low-order byte or word (in byte or word operations, respectively) is used or changed
— the remaining high-order portion is neither used nor changed. The least significant
bit (LSB) of a long-word integer is addressed as bit zero, and the most significant bit
(MSB) is addressed as bit 31. Figure 2-4 shows the organization of various types of
data in the data registers.
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31 30 10
MSB LSB
BYTE
31 24 23 16 15 8 7 0
HIGH-ORDER BYTE MIDDLE HIGH BYTE MIDDLE LOW BYTE LOW-ORDER BYTE
WORD
31 16 15 0
HIGH-ORDER WORD LOW-ORDER WORD
LONG WORD
31 0
LONG WORD
QUAD WORD
63 62 32
MSB HIGH-ORDER LONG WORD
31 10
LOW-ORDER LONG WORD LSB
Figure 2-4 Data Organization in Data Registers
Quad-word data consists of two long words: for example, the product of 32-bit multiply
or the quotient of 32-bit divide operations (signed and unsigned). Quad words may be
organized in any two data registers without restrictions on order or pairing. There are
no explicit instructions for the management of this data type; however, the MOVEM
instruction can be used to move a quad word into or out of the registers.
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BCD data represents decimal numbers in binary form. CPU32 BCD instructions use a
format in which a byte contains two digits — the four LSB contain the low digit, and the
four MSB contain the high digit. The ABCD, SBCD, and NBCD instructions operate on
two BCD digits packed into a single byte.
2.3.1.2 Address Registers
Each address register and stack pointer holds a 32-bit address. Address registers cannot be used for byte-sized operands. When an address register is used as a source
operand, either the low-order word or the entire long-word operand is used, depending
upon the operation size. When an address register is used as a destination operand,
the entire register is affected, regardless of operation size. If the source operand is a
word, it is first sign extended to 32 bits, and then used in the operation. Address registers can be used to support address computation. The instruction set includes instructions that add to, subtract from, compare, and move the contents of address
registers. Figure 2-5 shows the organization of addresses in address registers.
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31 16 15 0
SIGN EXTENDED 16-BIT ADDRESS OPERAND
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31 0
FULL 32-BIT ADDRESS OPERAND
Figure 2-5 Address Organization in Address Registers
2.3.1.3 Control Registers
The control registers contain control information for supervisor functions. The registers
vary in size. With the exception of the user portion of the SR (CCR), they are accessed
only by instructions at the supervisor privilege level.
The SR shown in Figure 2-3 is 16 bits wide. Only 11 bits of the SR are defined, and
all undefined values are reserved by Motorola for future definition. The undefined bits
are read as zeros and should be written as zeros for future compatibility. The lower
byte of the SR is the CCR. Operations to the CCR can be performed at the supervisor
or user privilege level. All operations to the SR and CCR are word-size operations. For
all CCR operations, the upper byte is read as all zeros and is ignored when written,
regardless of privilege level.
The alternate function code registers (SFC and DFC) are 32-bit registers with only bits
[2:0] implemented. These bits contain address space values (FC2 to FC0) for the read
or write operand of the MOVES instruction. The MOVEC instruction is used to transfer
values to and from the alternate function code registers. These are long-word transfers
— the upper 29 bits are read as zeros and are ignored when written.
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2.3.2 Organization in Memory
Memory is organized on a byte-addressable basis. An address corresponds to a highorder byte. For example, the address (N) of a long-word data item is the address of
the most significant byte of the high-order word. The address of the most significant
byte of the low-order word is (N + 2), and the address of the least significant byte of
the long word is (N + 3). The CPU32 requires data words and long words, as well as
instruction words to be aligned on word boundaries. Data misalignment is not supported. Figure 2-6 shows how operands and instructions are organized in memory. Note
that (N + X) is below (N) — that is, address value increases as one moves down the
page.
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15 8 7 0
MSB BYTE 0 LSB BYTE 1
BYTE 2 BYTE 3
15 0
MSB
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15 0
MSB
LONG WORD 0
BIT DATA
1 BYTE = 8 BITS
76543210
BYTE DATA
(8 BITS)
WORD DATA / INSTRUCTION
(16 BITS)
WORD 0 LSB
WORD 1
WORD 2
LONG WORD DATA / INSTRUCTION
(32 BITS)
HIGH ORDER
LOW ORDER
LSB
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LONG WORD 1
LONG WORD 2
ADDRESS
15
MSB
MSB = Most Significant Bit
LSB = Least Significant Bit
15 12 11 8 7 4 3 0
MSD = Most Significant Digit
LSD = Least Significant Digit
BCD 4
ADDRESS 0
ADDRESS 1
ADDRESS 2
MSDBCD 0
BCD 1
BCD 5
(32 BITS)
HIGH ORDER
LOW ORDER
DECIMAL DATA
2 BCD DIGITS = 1 BYTE
LSD
BCD 2
BCD 6
LSB
BCD 3
BCD 7
0
Figure 2-6 Memory Operand Addressing
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