Freescale Semiconductor 56F8122, 56F8322 User Manual
56F8322/56F8122
Data Sheet
Preliminary Technical Data
56F8300
16-bit Hybrid Controllers
MC56F8322
Rev. 10.0
10/2004
freescale.com
Document Revision History
Version History Description of Change
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional
grammar issues
Added Package Pins to GPIO table in Section 8. Clarification of TRST
usage in this device.
Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling,
consistency of language throughout family. Updated values in Regulator Parameters,
Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing,
Table 10-18, ADC Parameters, Table 10-24, and IO Loading Coefficients at 10MHz,
Table 10-25
Updated values in Power-On Reset Low Voltage Table 10-6.
Added Section 4.8 , added addition text to Section 6.9 on POR reset, added the word
“access” to FM Error Interrupt in Table 4-3, removed min and max numbers; only
documenting Typ. numbers for LVI in Table 10-6.
Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in
Table 10-3 in Pd characteristics
Replace any reference to Flash Interface Unit with Flash Memory Module; corrected typo on
page 1 for ADC channel; changed example in Section 2.2 ; added note on V
V
in Table 2-2 and Table 11-1; corrected typo FIVAL1 and FIVAH1 in Table 4-12;
REFLO
REFH
and
removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14;
added ADC calibration information to Table 10-24 and new graphs in Figure 10-20.
Rev 9.0
Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.
Rev. 10.0
Added 56F8122 information; edited to indicate differences in 56F8322 and 56F8122.
Reformatted to reflect Freescale look and feel. Updated Temperature Sensor and ADC
tables, then updated balance of electrical tables for consistency throughout family. Clarified
I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8322 Techncial Data, Rev. 10.0
2 Freescale Semiconductor
Preliminary
56F8322/56F8122 General Description
Note: Features in italics are NOT available in the 56F8122 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
•8KB Boot Flash
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
3
3
3
4
2
2
6
PWM Outputs
Fault Inputs
AD0
AD1
VREF
TEMP_SENSE
Quadrature
De c od er 0 o r
Quad
Timer A o r
GPIO B
Quad Timer C
or SCI0
or GPIOC
FlexCAN or
GPIOC
PWMA or
SPI1 or
GPIOA
Memory
Program Memory
16K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
Decoding
Peripherals
SPI0 or
SCI1 or
GPIOB
4
RESET
Program Controller
and Ha rdware
Looping Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Peripheral
Device Selects
• FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 21 GPIO lines
• 48-pin LQFP Package
V
4
JTAG/
EOnCE
Port
CAPVDDVSSVDDAVSSA
244
16-Bit
56800E Core
Address
Generation Unit
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
System Bus
Control
IPBus Bridge (IPBB)
RW
Control
COP/
Watchdog
IPWDB IPRDB
Interrupt
Controller
IRQA
Digital Reg
Data ALU
Integration
Analog Reg
Low Voltage
Supervisor
R/W Control
Clock
resets
System
Module
Bit
Manipulation
Unit
PLL
P
O
Clock
R
Generator*
*Includes On-Chip
Relaxation Oscillator
O
S
C
XTAL or GPIOC
EXTAL or GPIOC
56F8322/56F8122 Block Diagram
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 3
Preliminary
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8322/56F8122 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 8
1.4. Architecture Block Diagram . . . . . . . . . . . . . 9
1.5. Product Documentation . . . . . . . . . . . . . . . 13
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 13
Part 2: Signal/Connection Descriptions . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part 3: On-Chip Clock Synthesis (OCCS) . 26
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2. External Clock Operation . . . . . . . . . . . . . . 26
3.3. Use of On-Chip Relaxation Oscillator . . . . . 28
3.4. Internal Clock Operation . . . . . . . . . . . . . . . 28
3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Part 4: Memory Map . . . . . . . . . . . . . . . . . . 30
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 30
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 31
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 34
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 36
4.7. Peripheral Memory Mapped Registers . . . . 36
4.8. Factory-Programmed Memory . . . . . . . . . . 52
Part 5: Interrupt Controller (ITCN) . . . . . . . 52
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3. Functional Description . . . . . . . . . . . . . . . . 52
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 54
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 54
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 55
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Part 6: System Integration Module (SIM) . . 77
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 78
6.4. Operating Mode Register . . . . . . . . . . . . . . 79
6.5. Register Descriptions . . . . . . . . . . . . . . . . . 79
6.6. Clock Generation Overview . . . . . . . . . . . . 91
6.7. Power-Down Modes . . . . . . . . . . . . . . . . . . 91
6.8. Stop and Wait Mode Disable Function . . . . 92
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . .96
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . .98
Part 9: Joint Test Action Group (JTAG) . . . 98
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . .98
Part 10: Specifications . . . . . . . . . . . . . . . . 99
10.1. General Characteristics . . . . . . . . . . . . . . .99
10.2. DC Electrical Characteristics . . . . . . . . . .103
10.3. AC Electrical Characteristics . . . . . . . . . .107
10.4. Flash Memory Characteristics . . . . . . . . .108
10.5. External Clock Operation Timing . . . . . . .109
10.6. Phase Locked Loop Timing . . . . . . . . . . .110
10.7. Oscillator Parameters . . . . . . . . . . . . . . . .110
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . .113
10.9. Serial Peripheral Interface (SPI) Timing . .115
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . .118
10.11. Quadrature Decoder Timing . . . . . . . . . .118
10.12. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . .119
10.13. Controller Area Network (CAN) Timing .120
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . .120
10.15. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . .122
10.16. Equivalent Circuit for ADC Inputs . . . . . .125
10.17. Power Consumption . . . . . . . . . . . . . . . .125
Part 11: Packaging . . . . . . . . . . . . . . . . . . 127
11.1. 56F8322 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .127
11.2. 56F8122 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .129
Part 12: Design Considerations . . . . . . . . 132
12.1. Thermal Design Considerations . . . . . . . .132
12.2. Electrical Design Considerations . . . . . . .133
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .134
Part 13: Ordering Information . . . . . . . . . 135
Part 7: Security Features . . . . . . . . . . . . . . 93
7.1. Operation with Security Enabled . . . . . . . . . 93
7.2. Flash Access Blocking Mechanisms . . . . . . 93
56F8322 Techncial Data, Rev. 10.0
4 Freescale Semiconductor
Preliminary
Part 1 Overview
1.1 56F8322/56F8122 Features
1.1.1 Hybrid Controller Core
• Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
56F8322/56F8122 Features
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8322 and 56F8122 devices.
Table 1-1 Device Differences
Feature 56F8322 56F8122
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
60MHz/60 MIPS 40MHz/40 MIPS
4KB Not Available
8KB Not Available
1 x 6 Not Available
1 Not Available
1 x 4 Not Available
1 Not Available
—5
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 5
Preliminary
1.1.3 Memory
Note: Features in italics are NOT available in the 56F8122 device.
• Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security protection
• On-chip memory, including a low-cost, high-volume Flash solution
— 32KB of Program Flash
— 4KB of Program RAM
—
8KB of Data Flash
8KB of Data RAM
—
8KB of Boot Flash
—
• EEPROM emulation capability
1.1.4 Peripheral Circuits
Note: Features in italics are NOT available in the 56F8122 device.
• One Pulse Width Modulator module with six PWM outputs and one Fault input; fault-tolerant design with
dead time insertion; supports both center-aligned and edge-aligned modes
• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual,
3-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, Channel 2
• Temperature Sensor is tied internally to analog input (ANA7) to monitor the on-chip temperature
• Two 16-bit Quad Timer modules (TMR) totaling six pins:
— In the 56F8322, Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction
with the PWMA and ADCA
— In the 56F8122, Timer C works in conjunction with ADCA
• One Quadature Decoder which works in conjunction with Quad Timer A
• FlexCAN (Can Version 2.0 B-compliant) module with 2-pin port for transmit and receive
•
Up to two Serial Communication Interfaces (SCIs)
•
Up to two Serial Peripheral Interfaces (SPIs)
• Computer Operating Properly (COP)/Watchdog timer
• One dedicated external interrupt pin
• 21 General Purpose I/O (GPIO) pins
• Integrated Power-On Reset and Low-Voltage Interrupt Module
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
• Software-programmable, Phase Lock Loop (PLL)
• On-chip relaxation oscillator
56F8322 Techncial Data, Rev. 10.0
6 Freescale Semiconductor
Preliminary
Device Description
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8322 and 56F8122 are members of the 56800E core-based family of hybrid controllers. Each
combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the
functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective
solution. Because of their low cost, configuration flexibility, and compact program code, the 56F8322
and 56F8122 are well-suited for many applications. These devices include many peripherals that are
especially useful for automotive control (56F8322 only); industrial control and networking; motion
control; home appliances; general purpose inverters; smart sensors; fire and security systems; power
management; and medical monitoring applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C Compilers to enable rapid development of optimized
control applications.
The 56F8322 and 56F8122 support program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. These devices also provide one external
dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
1.2.1 56F8322 Features
The 56F8322 hybrid controller includes 32KB of Program Flash and 8KB of Data Flash, each
programmable through the JTAG port, and 4KB of Program RAM and 8KB of Data RAM. A total of 8KB
of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can
be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot
and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F8322 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and is also capable of supporting six independent PWM functions to enhance motor control
functionality. Complementary operation permits programmable dead time insertion, distortion correction
via current sensing by software, and separate top and bottom output polarity control. The up-counter value
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 7
Preliminary
is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from
1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the
Analog-to-Digital Converters (ADCs) through Quad Timer C, channel 2.
The 56F8322 incorporates one Quadrature Decoder capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This hybrid controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers and
FlexCAN. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function
is not required. A Flex Controller Area Network interface (CAN Version 2.0 B-compliant) and an internal
interrupt controller are also a part of the 56F8322.
1.2.2 56F8122 Features
The 56F8122 hybrid controller includes 32KB of Program Flash, programmable through the JTAG port,
and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of
field-programmable software routines that can be used to program the main Program Flash memory area.
The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page
erase size is 1KB. The Boot Flash memory can also be either bulk or page erased.
This hybrid controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8122.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.
56F8322 Techncial Data, Rev. 10.0
8 Freescale Semiconductor
Preliminary
Architecture Block Diagram
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures.
The 56F8322/56F8122 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the
internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2
shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the
on-board regulator and power and ground signals. They also do not show the multiplexing between
peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions, to see which
signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C, Channel 2, output can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 9
Preliminary
4
JTAG / EOnCE
Boot
Flash
CHIP
TAP
Controller
TAP
Linking
Module
External
JTAG Port
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
56800E
xab1[23:0]
xab2[23:0]
Program
Flash
Program
RAM
Data RAM
Data
Flash
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
IPBus
Bridge
Not available on the 56F8122 device.
IPBus
Control Logic
Flash
Memory
Module
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Memory Module (FM). Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are
56F8322 Techncial Data, Rev. 10.0
10 Freescale Semiconductor
16 bits.
Preliminary
To/From IPBus Bridge
Architecture Block Diagram
CLKGEN
(OSC/PLL)
Interrupt
Controller
(ROSC)
Low-Voltage Interrupt
Timer A
POR & LVI
4
Quadrature Decoder 0
System POR
SIM
RESET
COP Reset
2
FlexCAN
4
2
SCI 1
COP
SPI 1
4
SPI 0
PWMA
3
SYNC Output
GPIO A
2
SCI 0
GPIO B
GPIO C
ch2i
2
Timer C
ch2o
ADCA
6
TEMP_SENSE
Not available on the 56F8122 device.
IPBus
The dotted line on Temperature Sense signifies the
pad-to-pad bond between TEMP_SENSE and
ANA7 on the 56F8322
Figure 1-2 Peripheral Subsystem
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 11
Preliminary
Table 1-2 Bus Signal Names
Name Function
Program Memory Interface
pdb_m[15:0] Program data bus for instruction word fetches or read operations.
cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0] Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0]
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0] Secondary data address bus used for the second of two simultaneous accesses. Capable of
IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
to 0.
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
56F8322 Techncial Data, Rev. 10.0
12 Freescale Semiconductor
Preliminary
1.5 Product Documentation
Product Documentation
The documents listed in
Table 1-3
are required for a complete description and proper design with the 56F8322
and 56F8122 devices. Documentation is available from local Freescale distributors, Freescale semiconductor
sales offices, Freescale Literature Distribution Centers, or online at
http://www.freescale.com/semiconductors/
.
Table 1-3 Chip Documentation
Topic Description Order Number
DSP56800E
Reference Manual
56F8300 Peripheral User
Manual
56F8300 SCI/CAN
Bootloader User Manual
56F8322/56F8122
Technical Data Sheet
Product Brief Summary description and block diagram of the device
Errata Details any chip issues that might be present MC56F8322E
Detailed description of the 56800E family architecture,
16-bit hybrid controller core processor, and the
instruction set
Detailed description of peripherals of the 56800E
family of devices
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
core, memory, peripherals and interfaces
DSP56800ERM
MC56F8300UM
MC56F83xxBLUM
MC56F8322
MC56F8322PB
MC56F8122PB
MC56F8122E
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
Signal/Symbol Logic State Signal State
PIN True Asserted VIL/V
PIN False Deasserted VIH/V
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
Voltage
OL
OH
OH
OL
1
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 13
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups,
as detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row
describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of Pins in Package
Functional Group
56F8322 56F8122
Power (V
Ground (V
Supply Capacitors & V
PLL and Clock
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports
Serial Peripheral Interface (SPI) Port 0
Quadrature Decoder Port 0
CAN Ports
Analog to Digital Converter (ADC) Ports
Timer Module Port C
Timer Module Port A
JTAG/Enhanced On-Chip Emulation (EOnCE)
DD
SS
or V
or V
DDA
SSA
)
)
1
PP
2
3
4
5
55
55
22
22
22
7—
48
4—
2—
99
22
—4
44
Temperature Sense
Dedicated GPIO
1. The VPP input shares the IRQA input
2. Pins in this section can function as SPI #1 and GPIO.
3. Pins in this section can function as SCI #1 and GPIO.
4. Alternately, can function as Quad Timer A pins or GPIO.
5. Pins can function as SCI #0 and GPIO.
6. Tied internally to ANA7
Note: See Table 1-1 for 56F8122 functional differences.
14 Freescale Semiconductor
6
56F8322 Techncial Data, Rev. 10.0
0—
—5
Preliminary
Introduction
Power
Ground
Power
Ground
Other
Supply
Ports
PLL and
Clock or
GPIO
V
DD_IO
V
SS
V
DDA_ADC
V
SSA_ADC
1 - V
V
CAP
CAP
EXTAL (GPIOC0)
XTAL (GPIOC1)
PHASEA0 (TA0, GPIOB7)
4
4
1
1
56F8322
2
2
1
1
1
PHASEB0 (TA1, GPIOB6)
1
INDEX0 (TA2, GPIOB5)
1
HOME0 (TA3, GPIOB4)
1
SCLK0 (GPIOB3)
1
MOSI0 (GPIOB2)
1
MISO0 (RXD1, GPIOB1)
1
(TXD1, GPIOB0)
SS0
1
PWMA0 -1 (GPIOA0 - 1)
2
PWMA2 (SS1, GPIOA2)
1
PWMA3 (MISO1, GPIOA3)
1
PWMA4 (MOSI1, GPIOA4)
1
PWMA5 (SCLK1, GPIOA5)
1
FAULTA0 (GPIOA6)
1
ANA0 - 2
3
ANA4 - 6
3
V
REF
3
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
SPI0 or
SCI1 or
GPIO
PWMA or
SPI1 or
GPIO
ADCA
Note: V
CAN_RX (GPIOC2)
1
CAN_TX (GPIOC3)
1
TC0 (TXD0, GPIOC6)
1
TC1 (RXD0, GPIOC5)
1
IRQA (VPP)
1
RESET
1
JTAG/
EOnCE
Port
TCK
TMS
TDI
TDO
1
1
1
1
1
Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP)
REFH
is tied to V
DDA
and V
REFLO
is tied to V
inside this package
SSA
FlexCAN
or GPIO
Quad Timer C
or SCI0 or
GPIO
Interrupt/
Program
Control
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 15
Preliminary
Power
Ground
Power
Ground
Other
Supply
Ports
PLL and
Clock or
GPIO
V
DD_IO
V
SS
V
DDA_ADC
V
SSA_ADC
1 - V
V
CAP
CAP
EXTAL (GPIOC0)
XTAL (GPIOC1)
TA0 (GPIOB7)
4
4
1
1
56F8122
2
2
1
1
1
TA1 (GPIOB6)
1
TA2 (GPIOB5)
1
TA3 (G PIO B4)
1
SCLK0 (GPIOB3)
1
MOSI0 (GPIOB2)
1
MISO0 (RXD1, GPIOB1)
1
(TXD1, GPIOB0)
SS0
1
GPIOA0 - 1
2
SS1 (GPIOA2)
1
MISO1 (GPIOA3)
1
MOSI1 (GPIOA4)
1
SCLK1 (GPIOA5)
1
GPIOA6
1
ANA0 - 2
3
ANA4 - 6
3
V
REF
3
Quad
Timer A or
GPIO
SPI0 or
SCI1 or
GPIO
SPI1 or
GPIO
ADCA
GPIOC2
JTAG/
EOnCE
Port
TCK
TMS
TDI
TDO
1
GPIOC3
1
TC0 (TXD0, GPIOC6)
1
1
1
1
1
1
TC1 (RXD0, GPIOC5)
1
IRQA (VPP)
1
RESET
1
GPIO
Quad Timer C
or SCI0 or
GPIO
Interrupt/
Program
Control
Figure 2-2 56F8122 Signals Identified by Functional Group (48-Pin LQFP)
56F8322 Techncial Data, Rev. 10.0
16 Freescale Semiconductor
Preliminary
Signal Pins
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). In the 56F8122, after reset, each
pin must be configured for the desired function. The initialization software will configure each pin for the
function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed.
Note: Signals in italics are not available in the 56F8122 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3
pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of
the pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type
V
DD_IO
V
DD_IO
V
DD_IO
V
DD_IO
V
DDA_ADC
V
SS
V
SS
V
SS
V
SS
V
SSA_ADC
V
1 43 Supply Supply V
CAP
V
2 17
CAP
5 Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface
14
34
44
30 Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It
10 Supply Ground — These pins provide ground for chip logic and I/O drivers.
13
31
45
29 Supply ADC Analog Ground — This pin supplies an analog ground to the
State During
Reset
Signal Description
and also the Processor core throught the on-chip voltage regulator, if
it is enabled.
must be connected to a clean analog power supply.
ADC modules.
1 - 2 — Connect each pin to a 2.2µF or greater bypass capacitor
CAP
in order to bypass the core logic voltage regulator, required for proper
chip operation.
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 17
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type
EXTAL
(GPIOC0)
32 Input/
Schmitt
Input/
Output
XTAL
(GPIOC1)
33 Output
Schmitt
Input/
Output
State During
Reset
Input
Input
Output
Input
Signal Description
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to V
SS
.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
Crystal Oscillator Output — This output connects the internal crystal
oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to V
SS
.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
TCK 39 Schmitt
Input
Input, pulled
low internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor. A Schmitt
trigger input is used for noise immunity.
TMS 40 Schmitt
Input
TDI 41 Schmitt
Input
Input, pulled
high
internally
Input, pulled
high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
TDO 42 Output Tri-stated Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling edge
of TCK.
56F8322 Techncial Data, Rev. 10.0
18 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Pins
Signal Name Pin No. Type
PHASEA0
(TA0)
(GPIOB7)
(oscillator_
clock)
PHASEB0
(TA1)
38 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
37 Schmitt
Input
Schmitt
Input/
Output
State During
Reset
Input
Input
Input
Output
Input
Input
Signal Description
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal oscillator clock
signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A ,Channel 1
(GPIOB6)
(SYS_CLK2)
Schmitt
Input/
Output
Output
Input
Output
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK2 signal
(see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEB0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 19
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type
INDEX0
(TA2)
(GPIOB5)
(SYS_CLK)
HOME0
(TA3)
36 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
35 Schmitt
Input
Schmitt
Input/
Output
State During
Reset
Input
Input
Input
Output
Input
Input
Signal Description
Index — Quadrature Decoder 0, INDEX input
TA2 — Timer A, Channel 2
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK signal
(see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is INDEX0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Home — Quadrature Decoder 0, HOME input
TA3 — Timer A, Channel 3
(GPIOB4)
(prescaler_
clock)
SCLK0
(GPIOB3)
Schmitt
Input/
Output
Output
19 Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Output
Tri-stated
Input
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal prescaler_clock
signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is HOME0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the
data clock input. A Schmitt trigger input is used for noise immunity.
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is SCLK0.
56F8322 Techncial Data, Rev. 10.0
20 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Pins
Signal Name Pin No. Type
MOSI0
(GPIOB2)
MISO0
(RXD1)
(GPIOB1)
18 Schmitt
Input/
Output
Schmitt
Input/
Output
16 Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
State During
Reset
Tri-stated
Input
Input
Input
Input
Signal Description
SPI 0 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is MOSI0.
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
Receive Data — SCI1 receive data input
Port B GPIO - This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is MISO0.
SS0
(TXD1)
(GPIOB0)
PWMA0
(GPIOA0)
15 Schmitt
Input
Schmitt
Output
Schmitt
Input/
Output
3Schmitt
Output
Schmitt
Input/
Output
Input
Tri-stated
Input
Tri-stated
Input
SPI 0 Slave Select — SS0
SPI module that the current transfer is to be received.
Transmit Data — SCI1 transmit data output
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is SS0
PWMA0 — This is one of six PWMA output pins.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
is used in slave mode to indicate to the
.
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 21
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type
PWMA1
(GPIOA1)
PWMA2
)
(SS1
(GPIOA2)
4Schmitt
Output
Schmitt
Input/
Output
6Output
Schmitt
Input
Schmitt
Input/
Output
State During
Reset
Tri-stated
Input
Tri-stated
Input
Input
Signal Description
PWMA1 — This is one of six PWMA output pins.
Port A GPIO - This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA1.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PWMA2 — This is one of six PWMA output pins.
SPI 1 Slave Select — SS1 is used in slave mode to indicate to the
SPI module that the current transfer is to be received.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA2.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PWMA3
(MISO1)
(GPIOA3)
7Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Tri-stated
Input
Input
PWMA3 — This is one of six PWMA output pins.
SPI 1 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA3.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
56F8322 Techncial Data, Rev. 10.0
22 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Pins
Signal Name Pin No. Type
PWMA4
(MOSI1)
(GPIOA4)
PWMA5
(SCLK1)
(GPIOA5)
8Output
Schmitt
Input/
Output
Schmitt
Input/
Output
9Output
Schmitt
Input/
Output
Schmitt
Input/
Output
State During
Reset
Tri-stated
Tri-stated
Input
Tri-stated
Input
Input
Signal Description
PWMA4 — This is one of six PWMA output pins.
SPI 1 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA4.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PWMA5 — This is one of six PWMA output pins.
SPI 1 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the
data clock input. A Schmitt trigger input is used for noise immunity.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA5.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
FAULTA0
(GPIOA6)
ANA0 20 Input Input ANA0 - 2 — Analog inputs to ADCA, Channel 0
ANA1 21
ANA2 22
ANA4 23 Input Input ANA4 - 6 — Analog inputs to ADCA, Channel 1
ANA5 24
ANA6 25
12 Schmitt
Input
Schmitt
Input/
Output
Input
Input
FAULTA0 — This fault input pin is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is FAULTA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 23
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type
V
REFP
28 Input/
Output
V
REFMID
V
REFN
CAN_RX
27
26
46 Schmitt
Input
(GPIOC2)
Schmitt
Input/
Output
CAN_TX
(GPIOC3)
47 Output
Schmitt
Input/
Output
State During
Reset
Input/
Output
Input
Input
Tri-stated
Input
Signal Description
V
REFP
, V
REFMID
& V
— Internal pins for voltage reference which
REFN
are brought off-chip so that they can be bypassed. Connect to a 0.1µF
ceramic low ESR capacitor.
FlexCAN Receive Data — This is the CAN input. This pin has an
internal pull-up resistor.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is CAN_RX.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
FlexCAN Transmit Data — CAN output
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is CAN_TX.
TC0
(TXD0)
(GPIOC6)
TC1
(RXD0)
(GPIOC5)
1Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
48 Schmitt
Input/
Output
Output
Schmitt
Input/
Output
Input
Tri-stated
Input
Input
Input
Input
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
TC0 — Timer C, Channel 0
Transmit Data — SCI0 transmit data output
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is TC0.
TC1 — Timer C, Channel 1
Receive Data — SCI0 receive data input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is TC1.
56F8322 Techncial Data, Rev. 10.0
24 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Pins
Signal Name Pin No. Type
IRQA
(VPP)
RESET 2Schmitt
11 Schmitt
Input
Input
State During
Reset
Input
N/A
Input Reset — This input is a direct hardware reset on the processor. When
External Interrupt R equest A — The IRQA
external interrupt request during Stop and Wait mode operation.
During other operating modes, it is a synchronized external interrupt
request which indicates an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered.
— This pin is used for Flash debugging purposes.
V
PP
is asserted low, the hybrid controller is initialized and placed
RESET
in the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET
asserted together. The only exception occurs in a debugging
environment when a hardware DSP reset is required and it is
necessary not to reset the JTAG/EOnCE module. In this case, assert
, but do not assert TRST.
RESET
Signal Description
input is an asynchronous
and TRST should be
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 25
Preliminary
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design.
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator must be connected between the EXTAL and XTAL pins.
3.2.1 Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown
in Figure 3-1. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL
CL2
R
z
Sample External Crystal Parameters:
= 750 KΩ
R
z
Note: If the operating temperature range is limited to
below 85
o
C (105oC junction), then R
= 10 Meg Ω
z
CLKMODE = 0
EXTAL XTAL
CL1
R
z
Figure 3-1 Connecting to a Crystal Oscillator
Note: The OCCS_COHL bit should be set to 1 when a crystal oscillator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
56F8322 Techncial Data, Rev. 10.0
26 Freescale Semiconductor
Preliminary
External Clock Operation
3.2.2 Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-2.
Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components.
The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz)
2 Terminal
EXTAL XTAL
CL1
R
z
CL2
3 Terminal
EXTAL XTAL
R
z
C1
Sample External Ceramic Resonator Parameters:
= 750 KΩ
R
z
CLKMODE = 0
C2
Figure 3-2 Connecting a Ceramic Resonator
Note: The OCCS_COHL bit must be set to 0 when a crystal resonator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.3 External Clock Source
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock
source is connected to XTAL and the EXTAL pin is grounded.
XTAL
External
Clock
EXTAL
V
SS
or GPIO
Note: when using an external clocking
source with this configuration, the
CLKMODE and COHL bits
of the OSCTL register should be set to 1.
Figure 3-3 Connecting an External Clock Register
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 27
Preliminary
3.3 Use of On-Chip Relaxation Oscillator
An internal relaxtion oscillator can supply the reference frequency when an external frequency source of
crystal is not used. During a boot or reset sequence, the relaxation oscillator is enabled by default, and the
PRECS bit in the PLLCR word is set to 0. If an external oscillator is connected, the relaxation oscillator
can be deselected instead by setting the PRECS bit in the PLLCR to 1. If a changeover between internal
and external oscillators is required at start up, internal device circuits compensate for any asynchronous
transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip.
When changing clocks, the user must ensure that the clock source is not switched until the desired clock
is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within + 0.1% of 8MHz by trimming an internal capacitor. Bits 0-9 of the
OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value
to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit
added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the
desired frequency accuracy is achieved.
The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash
information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the
boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information,
see the 56F8300 Peripheral User Manual.
3.4 Internal Clock Operation
At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock
reference for the PLL. Software should power down the block not being used and program the PLL for the
correct frequency.
56F8322 Techncial Data, Rev. 10.0
28 Freescale Semiconductor
Preliminary
XTAL
EXTAL
Crystal
OSC
CLK_MODE
MUX
PLLCID
Relaxation
OSC
MUX
PLLDB
PRECS
PLLCOD
Registers
ZSRC
SYS_CLK2
source to the
SIM
MUX
MSTR_OSC
Prescaler
÷ (1, 2, 4, 8)
FREF
x (1 to 128)
PLL
FEEDBACK
Lock
Detector
F
OUT
÷ 2
F
OUT
/2
Postscaler
÷ (1, 2, 4, 8)
Bus Interface
& Control
Postscaler CLK
Bus
Interface
LCK
Loss of
Reference
loss of reference
clock interrupt
Clock
Detector
Figure 3-4 Internal Clock Operation
3.5 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions with the internal Relaxation Oscillator, since the 56F8322 and 56F8122 contain this
oscillator.
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 29
Preliminary
Part 4 Memory Map
4.1 Introduction
The 56F8322 and 56F8122 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
• Program Address Space, including the Interrupt Vector Table
• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Note: Data Flash and Program RAM are NOT available on the 56F8122 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory 56F8322 56F8122 Use Restrictions
Program Flash
Data Flash
Program RAM
Data RAM
Program Boot Flash
32KB 32KB
8KB —
4KB —
8KB 8KB
8KB 8KB
Erase / Program via Flash interface unit and word writes
to CDBW
Erase / Program via Flash interface unit and word writes
to CDBW. Data Flash can be read via either CDBR or
XDB2, but not by both simultaneously.
None
None
Erase / Program via Flash Interface unit and word
writes to CDBW
4.2 Program Map
The Program Memory map is located in Table 4-2. The operating mode control bits (MA and MB) in the
Operating Mode Register (OMR) usually control the Program Memory map. Because the 56F8322 and
56F8122 do not include EMI, the OMR MA bit, which is used to decide internal or external BOOT, will
have no effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash.
After reset, changing the OMR MB bit will have no effect on the Program Flash.
56F8322 Techncial Data, Rev. 10.0
30 Freescale Semiconductor
Preliminary
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