Freescale Semiconductor 56F8122, 56F8322 User Manual

Download

56F8322/56F8122

Data Sheet

Preliminary Technical Data

56F8300 16-bit Hybrid Controllers

MC56F8322 Rev. 10.0 10/2004

freescale.com

Document Revision History

Version History Description of Change

Rev 1.0

Rev 2.0

Rev 3.0

Rev 4.0

Rev 5.0

Rev 6.0

Rev 7.0

Rev 8.0

Pre-Release version, Alpha customers only

Initial Public Release

Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues

Added Package Pins to GPIO table in Section 8. Clarification of TRST

usage in this device. Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters,

Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing, Table 10-18, ADC Parameters, Table 10-24, and IO Loading Coefficients at 10MHz, Table 10-25

Updated values in Power-On Reset Low Voltage Table 10-6.

Added Section 4.8 , added addition text to Section 6.9 on POR reset, added the word “access” to FM Error Interrupt in Table 4-3, removed min and max numbers; only documenting Typ. numbers for LVI in Table 10-6.

Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in

Table 10-3 in Pd characteristics

Replace any reference to Flash Interface Unit with Flash Memory Module; corrected typo on page 1 for ADC channel; changed example in Section 2.2 ; added note on V

in Table 2-2 and Table 11-1; corrected typo FIVAL1 and FIVAH1 in Table 4-12;

REFLO

REFH

and

removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-20.

Rev 9.0

Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in

Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.

Rev. 10.0

Added 56F8122 information; edited to indicate differences in 56F8322 and 56F8122. Reformatted to reflect Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of electrical tables for consistency throughout family. Clarified I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.

Please see http://www.freescale.com for the most current Data Sheet revision.

56F8322 Techncial Data, Rev. 10.0

2 Freescale Semiconductor

Preliminary

56F8322/56F8122 General Description

Note: Features in italics are NOT available in the 56F8122 device.

• Up to 60 MIPS at 60MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• 32KB Program Flash

• 4KB Program RAM

• 8KB Data Flash

• 8KB Data RAM

•8KB Boot Flash

• One 6-channel PWM module

• Two 3-channel 12-bit ADCs

• Temperature Sensor

• One Quadrature Decoder

PWM Outputs

Fault Inputs

AD0

AD1

VREF

TEMP_SENSE

Quadrature

De c od er 0 o r

Quad

Timer A o r

GPIO B

Quad Timer C

or SCI0

or GPIOC

FlexCAN or

GPIOC

PWMA or

SPI1 or GPIOA

Memory

Program Memory

16K x 16 Flash

2K x 16 RAM

4K x 16 Boot

Flash

Data Memory

4K x 16 Flash

4K x 16 RAM

Decoding Peripherals

SPI0 or SCI1 or GPIOB

RESET

Program Controller

and Ha rdware

Looping Unit

PAB PDB CDBR CDBW

XDB2 XAB1 XAB2

PAB

PDB CDBR CDBW

Peripheral

Device Selects

• FlexCAN module

• Up to two Serial Communication Interfaces (SCIs)

• Up to two Serial Peripheral Interfaces (SPIs)

• Two general-purpose Quad Timers

• Computer Operating Properly (COP)/Watchdog

• On-Chip Relaxation Oscillator

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 21 GPIO lines

• 48-pin LQFP Package

JTAG/

EOnCE

Port

CAPVDDVSSVDDAVSSA

244

16-Bit

56800E Core

Address

Generation Unit

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

System Bus

Control

IPBus Bridge (IPBB)

Control

COP/

Watchdog

IPWDB IPRDB

Interrupt

Controller

IRQA

Digital Reg

Data ALU

Integration

Analog Reg

Low Voltage

Supervisor

R/W Control

Clock resets

System

Module

Bit

Manipulation

Unit

PLL

P O

Clock

Generator*

*Includes On-Chip

Relaxation Oscillator

O S C

XTAL or GPIOC EXTAL or GPIOC

56F8322/56F8122 Block Diagram

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 3 Preliminary

Table of Contents

Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5

1.1. 56F8322/56F8122 Features . . . . . . . . . . . . . 5

1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7

1.3. Award-Winning Development Environment . 8

1.4. Architecture Block Diagram . . . . . . . . . . . . . 9

1.5. Product Documentation . . . . . . . . . . . . . . . 13

1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 13

Part 2: Signal/Connection Descriptions . . 14

2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 17

Part 3: On-Chip Clock Synthesis (OCCS) . 26

3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2. External Clock Operation . . . . . . . . . . . . . . 26

3.3. Use of On-Chip Relaxation Oscillator . . . . . 28

3.4. Internal Clock Operation . . . . . . . . . . . . . . . 28

3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Part 4: Memory Map . . . . . . . . . . . . . . . . . . 30

4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 30

4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 31

4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 34

4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 36

4.7. Peripheral Memory Mapped Registers . . . . 36

4.8. Factory-Programmed Memory . . . . . . . . . . 52

Part 5: Interrupt Controller (ITCN) . . . . . . . 52

5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3. Functional Description . . . . . . . . . . . . . . . . 52

5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 54

5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 54

5.6. Register Descriptions . . . . . . . . . . . . . . . . . 55

5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Part 6: System Integration Module (SIM) . . 77

6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 78

6.4. Operating Mode Register . . . . . . . . . . . . . . 79

6.5. Register Descriptions . . . . . . . . . . . . . . . . . 79

6.6. Clock Generation Overview . . . . . . . . . . . . 91

6.7. Power-Down Modes . . . . . . . . . . . . . . . . . . 91

6.8. Stop and Wait Mode Disable Function . . . . 92

6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Part 8: General Purpose Input/Output

(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96

8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .96

8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . .96

8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . .98

Part 9: Joint Test Action Group (JTAG) . . . 98

9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . .98

Part 10: Specifications . . . . . . . . . . . . . . . . 99

10.1. General Characteristics . . . . . . . . . . . . . . .99

10.2. DC Electrical Characteristics . . . . . . . . . .103

10.3. AC Electrical Characteristics . . . . . . . . . .107

10.4. Flash Memory Characteristics . . . . . . . . .108

10.5. External Clock Operation Timing . . . . . . .109

10.6. Phase Locked Loop Timing . . . . . . . . . . .110

10.7. Oscillator Parameters . . . . . . . . . . . . . . . .110

10.8. Reset, Stop, Wait, Mode Select, and

Interrupt Timing . . . . . . . . . . . . . .113

10.9. Serial Peripheral Interface (SPI) Timing . .115

10.10. Quad Timer Timing . . . . . . . . . . . . . . . . .118

10.11. Quadrature Decoder Timing . . . . . . . . . .118

10.12. Serial Communication Interface (SCI)

Timing . . . . . . . . . . . . . . . . . . . . .119

10.13. Controller Area Network (CAN) Timing .120

10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . .120

10.15. Analog-to-Digital Converter (ADC)

Parameters . . . . . . . . . . . . . . . . .122

10.16. Equivalent Circuit for ADC Inputs . . . . . .125

10.17. Power Consumption . . . . . . . . . . . . . . . .125

Part 11: Packaging . . . . . . . . . . . . . . . . . . 127

11.1. 56F8322 Package and Pin-Out

Information . . . . . . . . . . . . . . . . . .127

11.2. 56F8122 Package and Pin-Out

Information . . . . . . . . . . . . . . . . . .129

Part 12: Design Considerations . . . . . . . . 132

12.1. Thermal Design Considerations . . . . . . . .132

12.2. Electrical Design Considerations . . . . . . .133

12.3. Power Distribution and I/O Ring

Implementation . . . . . . . . . . . . . .134

Part 13: Ordering Information . . . . . . . . . 135

Part 7: Security Features . . . . . . . . . . . . . . 93

7.1. Operation with Security Enabled . . . . . . . . . 93

7.2. Flash Access Blocking Mechanisms . . . . . . 93

56F8322 Techncial Data, Rev. 10.0

4 Freescale Semiconductor

Preliminary

Part 1 Overview

1.1 56F8322/56F8122 Features

1.1.1 Hybrid Controller Core

• Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture

• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface

56F8322/56F8122 Features

1.1.2 Differences Between Devices

Table 1-1 outlines the key differences between the 56F8322 and 56F8122 devices.

Table 1-1 Device Differences

Feature 56F8322 56F8122

Guaranteed Speed

Program RAM

Data Flash

PWM

CAN

Quadrature Decoder

Temperature Sensor

Dedicated GPIO

60MHz/60 MIPS 40MHz/40 MIPS

4KB Not Available

8KB Not Available

1 x 6 Not Available

1 Not Available

1 x 4 Not Available

1 Not Available

—5

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 5 Preliminary

1.1.3 Memory

Note: Features in italics are NOT available in the 56F8122 device.

• Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security protection

• On-chip memory, including a low-cost, high-volume Flash solution

— 32KB of Program Flash

— 4KB of Program RAM

—

8KB of Data Flash

8KB of Data RAM

—

8KB of Boot Flash

—

• EEPROM emulation capability

1.1.4 Peripheral Circuits

Note: Features in italics are NOT available in the 56F8122 device.

• One Pulse Width Modulator module with six PWM outputs and one Fault input; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes

• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual, 3-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, Channel 2

• Temperature Sensor is tied internally to analog input (ANA7) to monitor the on-chip temperature

• Two 16-bit Quad Timer modules (TMR) totaling six pins:

— In the 56F8322, Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction

with the PWMA and ADCA

— In the 56F8122, Timer C works in conjunction with ADCA

• One Quadature Decoder which works in conjunction with Quad Timer A

• FlexCAN (Can Version 2.0 B-compliant) module with 2-pin port for transmit and receive

•

Up to two Serial Communication Interfaces (SCIs)

•

Up to two Serial Peripheral Interfaces (SPIs)

• Computer Operating Properly (COP)/Watchdog timer

• One dedicated external interrupt pin

• 21 General Purpose I/O (GPIO) pins

• Integrated Power-On Reset and Low-Voltage Interrupt Module

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging

• Software-programmable, Phase Lock Loop (PLL)

• On-chip relaxation oscillator

56F8322 Techncial Data, Rev. 10.0

6 Freescale Semiconductor

Preliminary

Device Description

1.1.5 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

• ADC smart power management

• Each peripheral can be individually disabled to save power

1.2 Device Description

The 56F8322 and 56F8122 are members of the 56800E core-based family of hybrid controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of their low cost, configuration flexibility, and compact program code, the 56F8322 and 56F8122 are well-suited for many applications. These devices include many peripherals that are especially useful for automotive control (56F8322 only); industrial control and networking; motion control; home appliances; general purpose inverters; smart sensors; fire and security systems; power management; and medical monitoring applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers to enable rapid development of optimized control applications.

The 56F8322 and 56F8122 support program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide one external dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

1.2.1 56F8322 Features

The 56F8322 hybrid controller includes 32KB of Program Flash and 8KB of Data Flash, each programmable through the JTAG port, and 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F8322 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and is also capable of supporting six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 7 Preliminary

is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters (ADCs) through Quad Timer C, channel 2.

The 56F8322 incorporates one Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded.

This hybrid controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers and FlexCAN. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A Flex Controller Area Network interface (CAN Version 2.0 B-compliant) and an internal interrupt controller are also a part of the 56F8322.

1.2.2 56F8122 Features

The 56F8122 hybrid controller includes 32KB of Program Flash, programmable through the JTAG port, and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory area. The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page erase size is 1KB. The Boot Flash memory can also be either bulk or page erased.

This hybrid controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and two Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An internal interrupt controller is also a part of the 56F8122.

1.3 Award-Winning Development Environment

Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system.

The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.

56F8322 Techncial Data, Rev. 10.0

8 Freescale Semiconductor

Preliminary

Architecture Block Diagram

1.4 Architecture Block Diagram

Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures.

The 56F8322/56F8122 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals.

Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C, Channel 2, output can generate periodic start (SYNC) signals to the ADC to start its conversions.

In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,

please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 9 Preliminary

JTAG / EOnCE

Boot

Flash

CHIP

TAP

Controller

TAP Linking Module

External

JTAG Port

pdb_m[15:0]

pab[20:0]

cdbw[31:0]

56800E

xab1[23:0]

xab2[23:0]

Program

Flash

Program

RAM

Data RAM

Data

Flash

cdbr_m[31:0]

xdb2_m[15:0]

To Flash

IPBus

Bridge

Not available on the 56F8122 device.

IPBus

Control Logic

Flash

Memory

Module

Figure 1-1 System Bus Interfaces

Note: Flash memories are encapsulated within the Flash Memory Module (FM). Flash control is

accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories.

Note: The primary data RAM port is 32 bits wide. Other data ports are

56F8322 Techncial Data, Rev. 10.0

10 Freescale Semiconductor

16 bits.

Preliminary

To/From IPBus Bridge

Architecture Block Diagram

CLKGEN

(OSC/PLL)

Interrupt

Controller

(ROSC)

Low-Voltage Interrupt

Timer A

POR & LVI

Quadrature Decoder 0

System POR

SIM

RESET

COP Reset

FlexCAN

SCI 1

COP

SPI 1

SPI 0

PWMA

SYNC Output

GPIO A

SCI 0

GPIO B

GPIO C

ch2i

Timer C

ch2o

ADCA

TEMP_SENSE

Not available on the 56F8122 device.

IPBus

The dotted line on Temperature Sense signifies the pad-to-pad bond between TEMP_SENSE and ANA7 on the 56F8322

Figure 1-2 Peripheral Subsystem

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 11 Preliminary

Table 1-2 Bus Signal Names

Name Function

Program Memory Interface

pdb_m[15:0] Program data bus for instruction word fetches or read operations.

cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus

are used for writes to program memory.)

pab[20:0] Program memory address bus. Data is returned on pdb_m bus.

Primary Data Memory Interface Bus

cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.

cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus.

xab1[23:0]

xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.

xab2[23:0] Secondary data address bus used for the second of two simultaneous accesses. Capable of

IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate

1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.

Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.

Secondary Data Memory Interface

addressing only words. Data is returned on xdb2_m.

Peripheral Interface Bus

as the Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m.

56F8322 Techncial Data, Rev. 10.0

12 Freescale Semiconductor

Preliminary

1.5 Product Documentation

Product Documentation

The documents listed in

Table 1-3

are required for a complete description and proper design with the 56F8322 and 56F8122 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at

http://www.freescale.com/semiconductors/

Table 1-3 Chip Documentation

Topic Description Order Number

DSP56800E Reference Manual

56F8300 Peripheral User Manual

56F8300 SCI/CAN Bootloader User Manual

56F8322/56F8122 Technical Data Sheet

Product Brief Summary description and block diagram of the device

Errata Details any chip issues that might be present MC56F8322E

Detailed description of the 56800E family architecture, 16-bit hybrid controller core processor, and the instruction set

Detailed description of peripherals of the 56800E family of devices

Detailed description of the SCI/CAN Bootloaders 56F8300 family of devices

Electrical and timing specifications, pin descriptions, and package descriptions (this document)

core, memory, peripherals and interfaces

DSP56800ERM

MC56F8300UM

MC56F83xxBLUM

MC56F8322

MC56F8322PB MC56F8122PB

MC56F8122E

1.6 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low.

Signal/Symbol Logic State Signal State

PIN True Asserted VIL/V

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

Voltage

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 13 Preliminary

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row describes the signal or signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Number of Pins in Package

Functional Group

56F8322 56F8122

Power (V

Ground (V

Supply Capacitors & V

PLL and Clock

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports

Serial Peripheral Interface (SPI) Port 0

Quadrature Decoder Port 0

CAN Ports

Analog to Digital Converter (ADC) Ports

Timer Module Port C

Timer Module Port A

JTAG/Enhanced On-Chip Emulation (EOnCE)

or V

DDA

SSA

)

7—

4—

2—

—4

Temperature Sense

Dedicated GPIO

1. The VPP input shares the IRQA input

2. Pins in this section can function as SPI #1 and GPIO.

3. Pins in this section can function as SCI #1 and GPIO.

4. Alternately, can function as Quad Timer A pins or GPIO.

5. Pins can function as SCI #0 and GPIO.

6. Tied internally to ANA7

Note: See Table 1-1 for 56F8122 functional differences.

14 Freescale Semiconductor

56F8322 Techncial Data, Rev. 10.0

0—

—5

Preliminary

Introduction

Power

Ground

Power

Ground

Other

Supply

Ports

PLL and Clock or

GPIO

DD_IO

DDA_ADC

SSA_ADC

1 - V

CAP

EXTAL (GPIOC0)

XTAL (GPIOC1)

PHASEA0 (TA0, GPIOB7)

56F8322

PHASEB0 (TA1, GPIOB6)

INDEX0 (TA2, GPIOB5)

HOME0 (TA3, GPIOB4)

SCLK0 (GPIOB3)

MOSI0 (GPIOB2)

MISO0 (RXD1, GPIOB1)

(TXD1, GPIOB0)

SS0

PWMA0 -1 (GPIOA0 - 1)

PWMA2 (SS1, GPIOA2)

PWMA3 (MISO1, GPIOA3)

PWMA4 (MOSI1, GPIOA4)

PWMA5 (SCLK1, GPIOA5)

FAULTA0 (GPIOA6)

ANA0 - 2

ANA4 - 6

REF

Quadrature Decoder 0 or Quad Timer A or GPIO

SPI0 or SCI1 or GPIO

PWMA or SPI1 or GPIO

ADCA

Note: V

CAN_RX (GPIOC2)

CAN_TX (GPIOC3)

TC0 (TXD0, GPIOC6)

TC1 (RXD0, GPIOC5)

IRQA (VPP)

RESET

JTAG/

EOnCE

Port

TCK

TMS

TDI

TDO

Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP)

REFH

is tied to V

DDA

and V

REFLO

is tied to V

inside this package

SSA

FlexCAN or GPIO

Quad Timer C or SCI0 or GPIO

Interrupt/ Program Control

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 15 Preliminary

Power

Ground

Power

Ground

Other

Supply

Ports

PLL and Clock or

GPIO

DD_IO

DDA_ADC

SSA_ADC

1 - V

CAP

EXTAL (GPIOC0)

XTAL (GPIOC1)

TA0 (GPIOB7)

56F8122

TA1 (GPIOB6)

TA2 (GPIOB5)

TA3 (G PIO B4)

SCLK0 (GPIOB3)

MOSI0 (GPIOB2)

MISO0 (RXD1, GPIOB1)

(TXD1, GPIOB0)

SS0

GPIOA0 - 1

SS1 (GPIOA2)

MISO1 (GPIOA3)

MOSI1 (GPIOA4)

SCLK1 (GPIOA5)

GPIOA6

ANA0 - 2

ANA4 - 6

REF

Quad Timer A or GPIO

SPI0 or SCI1 or GPIO

SPI1 or GPIO

ADCA

GPIOC2

JTAG/

EOnCE

Port

TCK

TMS

TDI

TDO

GPIOC3

TC0 (TXD0, GPIOC6)

TC1 (RXD0, GPIOC5)

IRQA (VPP)

RESET

GPIO

Quad Timer C or SCI0 or GPIO

Interrupt/ Program Control

Figure 2-2 56F8122 Signals Identified by Functional Group (48-Pin LQFP)

56F8322 Techncial Data, Rev. 10.0

16 Freescale Semiconductor

Preliminary

Signal Pins

2.2 Signal Pins

After reset, each pin is configured for its primary function (listed first). In the 56F8122, after reset, each pin must be configured for the desired function. The initialization software will configure each pin for the function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed.

Note: Signals in italics are not available in the 56F8122 device.

If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3 pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of the pin, it will become an input if no other registers are changed.

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Name Pin No. Type

DD_IO

DDA_ADC

SSA_ADC

1 43 Supply Supply V

CAP

2 17

CAP

5 Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface

30 Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It

10 Supply Ground — These pins provide ground for chip logic and I/O drivers.

29 Supply ADC Analog Ground — This pin supplies an analog ground to the

State During

Reset

Signal Description

and also the Processor core throught the on-chip voltage regulator, if it is enabled.

must be connected to a clean analog power supply.

ADC modules.

1 - 2 — Connect each pin to a 2.2µF or greater bypass capacitor

CAP

in order to bypass the core logic voltage regulator, required for proper chip operation.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 17 Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Name Pin No. Type

EXTAL

(GPIOC0)

32 Input/

Schmitt

Input/

Output

XTAL

(GPIOC1)

33 Output

Schmitt

Input/

Output

State During

Reset

Input

Output

Input

Signal Description

External Crystal Oscillator Input — This input can be connected to

an 8MHz external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to V

The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL.

Port C GPIO — This GPIO pin can be individually programmed as an input or output pin.

After reset, the default state is an EXTAL input with pull-ups disabled.

Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to V

The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL.

Port C GPIO — This GPIO pin can be individually programmed as an input or output pin.

After reset, the default state is an XTAL input with pull-ups disabled.

TCK 39 Schmitt

Input

Input, pulled

low internally

Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-down resistor. A Schmitt trigger input is used for noise immunity.

TMS 40 Schmitt

Input

TDI 41 Schmitt

Input

Input, pulled

high

internally

Input, pulled

high

internally

Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

TDO 42 Output Tri-stated Test Data Output — This tri-stateable output pin provides a serial

output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK.

56F8322 Techncial Data, Rev. 10.0

18 Freescale Semiconductor

Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Pins

Signal Name Pin No. Type

PHASEA0

(TA0)

(GPIOB7)

(oscillator_

clock)

PHASEB0

(TA1)

38 Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

37 Schmitt

Input

Schmitt

Input/

Output

State During

Reset

Input

Output

Input

Signal Description

Phase A — Quadrature Decoder 0, PHASEA input

TA0 — Timer A, Channel 0

Port B GPIO — This GPIO pin can be individually programmed as an

input or output pin.

Clock Output - can be used to monitor the internal oscillator clock signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).

In the 56F8322, the default state after reset is PHASEA0.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

Phase B — Quadrature Decoder 0, PHASEB input

TA1 — Timer A ,Channel 1

(GPIOB6)

(SYS_CLK2)

Schmitt

Input/

Output

Input

Output

Port B GPIO — This GPIO pin can be individually programmed as an input or output pin.

Clock Output - can be used to monitor the internal SYS_CLK2 signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).

In the 56F8322, the default state after reset is PHASEB0.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 19 Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Name Pin No. Type

INDEX0

(TA2)

(GPIOB5)

(SYS_CLK)

HOME0

(TA3)

36 Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

35 Schmitt

Input

Schmitt

Input/

Output

State During

Reset

Input

Output

Input

Signal Description

Index — Quadrature Decoder 0, INDEX input

TA2 — Timer A, Channel 2

Port B GPIO — This GPIO pin can be individually programmed as an

input or output pin.

Clock Output - can be used to monitor the internal SYS_CLK signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).

In the 56F8322, the default state after reset is INDEX0.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

Home — Quadrature Decoder 0, HOME input

TA3 — Timer A, Channel 3

(GPIOB4)

(prescaler_

clock)

SCLK0

(GPIOB3)

Schmitt

Input/

Output

19 Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Output

Tri-stated

Input

Port B GPIO — This GPIO pin can be individually programmed as an input or output pin.

Clock Output - can be used to monitor the internal prescaler_clock signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).

In the 56F8322, the default state after reset is HOME0.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

SPI 0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity.

Port B GPIO — This GPIO pin can be individually programmed as an input or output pin.

After reset, the default state is SCLK0.

56F8322 Techncial Data, Rev. 10.0

20 Freescale Semiconductor

Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Pins

Signal Name Pin No. Type

MOSI0

(GPIOB2)

MISO0

(RXD1)

(GPIOB1)

18 Schmitt

Input/

Output

Schmitt

Input/

Output

16 Schmitt

Input/

Output

Schmitt

Input

Schmitt

Input/

Output

State During

Reset

Tri-stated

Input

Signal Description

SPI 0 Master Out/Slave In — This serial data pin is an output from a

master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data.

Port B GPIO — This GPIO pin can be individually programmed as an input or output pin.

After reset, the default state is MOSI0.

SPI 0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data.

Receive Data — SCI1 receive data input

Port B GPIO - This GPIO pin can be individually programmed as an

input or output pin.

After reset, the default state is MISO0.

SS0

(TXD1)

(GPIOB0)

PWMA0

(GPIOA0)

15 Schmitt

Input

Schmitt

Output

Schmitt

Input/

Output

3Schmitt

Output

Schmitt

Input/

Output

Input

Tri-stated

Input

Tri-stated

Input

SPI 0 Slave Select — SS0 SPI module that the current transfer is to be received.

Transmit Data — SCI1 transmit data output

Port B GPIO — This GPIO pin can be individually programmed as an

input or output pin.

After reset, the default state is SS0

PWMA0 — This is one of six PWMA output pins.

Port A GPIO — This GPIO pin can be individually programmed as an

input or output pin.

In the 56F8322, the default state after reset is PWMA0.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

is used in slave mode to indicate to the

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 21 Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Name Pin No. Type

PWMA1

(GPIOA1)

PWMA2

)

(SS1

(GPIOA2)

4Schmitt

Output

Schmitt

Input/

Output

6Output

Schmitt

Input

Schmitt

Input/

Output

State During

Reset

Tri-stated

Input

Tri-stated

Input

Signal Description

PWMA1 — This is one of six PWMA output pins.

Port A GPIO - This GPIO pin can be individually programmed as an

input or output pin.

In the 56F8322, the default state after reset is PWMA1.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

PWMA2 — This is one of six PWMA output pins.

SPI 1 Slave Select — SS1 is used in slave mode to indicate to the

SPI module that the current transfer is to be received.

Port A GPIO — This GPIO pin can be individually programmed as an input or output pin.

In the 56F8322, the default state after reset is PWMA2.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

PWMA3

(MISO1)

(GPIOA3)

7Output

Schmitt

Input/

Output

Schmitt

Input/

Output

Tri-stated

Input

PWMA3 — This is one of six PWMA output pins.

SPI 1 Master In/Slave Out — This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data.

Port A GPIO — This GPIO pin can be individually programmed as an input or output pin.

In the 56F8322, the default state after reset is PWMA3.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

56F8322 Techncial Data, Rev. 10.0

22 Freescale Semiconductor

Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Pins

Signal Name Pin No. Type

PWMA4

(MOSI1)

(GPIOA4)

PWMA5

(SCLK1)

(GPIOA5)

8Output

Schmitt

Input/

Output

Schmitt

Input/

Output

9Output

Schmitt

Input/

Output

Schmitt

Input/

Output

State During

Reset

Tri-stated

Input

Tri-stated

Input

Signal Description

PWMA4 — This is one of six PWMA output pins.

SPI 1 Master Out/Slave In — This serial data pin is an output from a

master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data.

Port A GPIO — This GPIO pin can be individually programmed as an input or output pin.

In the 56F8322, the default state after reset is PWMA4.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

PWMA5 — This is one of six PWMA output pins.

SPI 1 Serial Clock — In the master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity.

Port A GPIO — This GPIO pin can be individually programmed as an input or output pin.

In the 56F8322, the default state after reset is PWMA5.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

FAULTA0

(GPIOA6)

ANA0 20 Input Input ANA0 - 2 — Analog inputs to ADCA, Channel 0

ANA1 21

ANA2 22

ANA4 23 Input Input ANA4 - 6 — Analog inputs to ADCA, Channel 1

ANA5 24

ANA6 25

12 Schmitt

Input

Schmitt

Input/

Output

Input

FAULTA0 — This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip.

Port A GPIO — This GPIO pin can be individually programmed as an input or output pin.

In the 56F8322, the default state after reset is FAULTA0.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 23 Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Name Pin No. Type

REFP

28 Input/

Output

REFMID

REFN

CAN_RX

46 Schmitt

Input

(GPIOC2)

Schmitt

Input/

Output

CAN_TX

(GPIOC3)

47 Output

Schmitt

Input/

Output

State During

Reset

Input/

Output

Input

Tri-stated

Input

Signal Description

REFP

, V

REFMID

& V

— Internal pins for voltage reference which

REFN

are brought off-chip so that they can be bypassed. Connect to a 0.1µF

ceramic low ESR capacitor.

FlexCAN Receive Data — This is the CAN input. This pin has an internal pull-up resistor.

Port C GPIO — This GPIO pin can be individually programmed as an input or output pin.

In the 56F8322, the default state after reset is CAN_RX.

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

FlexCAN Transmit Data — CAN output

Port C GPIO — This GPIO pin can be individually programmed as an

input or output pin.

In the 56F8322, the default state after reset is CAN_TX.

TC0

(TXD0)

(GPIOC6)

TC1

(RXD0)

(GPIOC5)

1Schmitt

Input/

Output

Schmitt

Input

Schmitt

Input/

Output

48 Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Tri-stated

Input

In the 56F8122, the default state is not one of the functions offered and must be reconfigured.

TC0 — Timer C, Channel 0

Transmit Data — SCI0 transmit data output

Port C GPIO — This GPIO pin can be individually programmed as an

input or output pin.

After reset, the default state is TC0.

TC1 — Timer C, Channel 1

Receive Data — SCI0 receive data input

Port C GPIO — This GPIO pin can be individually programmed as an

input or output pin.

After reset, the default state is TC1.

56F8322 Techncial Data, Rev. 10.0

24 Freescale Semiconductor

Preliminary

Table 2-2 Signal and Package Information for the 48-Pin LQFP

Signal Pins

Signal Name Pin No. Type

IRQA

(VPP)

RESET 2Schmitt

11 Schmitt

Input

State During

Reset

Input

N/A

Input Reset — This input is a direct hardware reset on the processor. When

External Interrupt R equest A — The IRQA external interrupt request during Stop and Wait mode operation. During other operating modes, it is a synchronized external interrupt request which indicates an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered.

— This pin is used for Flash debugging purposes.

is asserted low, the hybrid controller is initialized and placed

RESET in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks.

To ensure complete hardware reset, RESET asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the JTAG/EOnCE module. In this case, assert

, but do not assert TRST.

RESET

Signal Description

input is an asynchronous

and TRST should be

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 25 Preliminary

Part 3 On-Chip Clock Synthesis (OCCS)

3.1 Introduction

Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design.

3.2 External Clock Operation

The system clock can be derived from an external crystal, ceramic resonator or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins.

3.2.1 Crystal Oscillator

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown in Figure 3-1. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.

Crystal Frequency = 4 - 8MHz (optimized for 8MHz)

EXTAL XTAL

CL2

Sample External Crystal Parameters:

= 750 KΩ

Note: If the operating temperature range is limited to below 85

C (105oC junction), then R

= 10 Meg Ω

CLKMODE = 0

EXTAL XTAL

CL1

Figure 3-1 Connecting to a Crystal Oscillator

Note: The OCCS_COHL bit should be set to 1 when a crystal oscillator is used. The reset condition on the

OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual.

56F8322 Techncial Data, Rev. 10.0

26 Freescale Semiconductor

Preliminary

External Clock Operation

3.2.2 Ceramic Resonator (Default)

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-2. Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins.

Resonator Frequency = 4 - 8MHz (optimized for 8MHz)

2 Terminal

EXTAL XTAL

CL1

CL2

3 Terminal

EXTAL XTAL

Sample External Ceramic Resonator Parameters:

= 750 KΩ

CLKMODE = 0

Figure 3-2 Connecting a Ceramic Resonator

Note: The OCCS_COHL bit must be set to 0 when a crystal resonator is used. The reset condition on the

OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual.

3.2.3 External Clock Source

The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to XTAL and the EXTAL pin is grounded.

XTAL

External

Clock

EXTAL

or GPIO

Note: when using an external clocking source with this configuration, the CLKMODE and COHL bits of the OSCTL register should be set to 1.

Figure 3-3 Connecting an External Clock Register

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 27 Preliminary

3.3 Use of On-Chip Relaxation Oscillator

An internal relaxtion oscillator can supply the reference frequency when an external frequency source of crystal is not used. During a boot or reset sequence, the relaxation oscillator is enabled by default, and the PRECS bit in the PLLCR word is set to 0. If an external oscillator is connected, the relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. If a changeover between internal and external oscillators is required at start up, internal device circuits compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable.

To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.1% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the desired frequency accuracy is achieved.

The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the 56F8300 Peripheral User Manual.

3.4 Internal Clock Operation

At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock reference for the PLL. Software should power down the block not being used and program the PLL for the correct frequency.

56F8322 Techncial Data, Rev. 10.0

28 Freescale Semiconductor

Preliminary

XTAL

EXTAL

Crystal

OSC

CLK_MODE

MUX

PLLCID

Relaxation

OSC

MUX

PLLDB

PRECS

PLLCOD

Registers

ZSRC

SYS_CLK2

source to the

SIM

MUX

MSTR_OSC

Prescaler

÷ (1, 2, 4, 8)

FREF

x (1 to 128)

PLL

FEEDBACK

Lock

Detector

OUT

÷ 2

OUT

Postscaler

÷ (1, 2, 4, 8)

Bus Interface

& Control

Postscaler CLK

Bus

Interface

LCK

Loss of

Reference

loss of reference

clock interrupt

Clock

Detector

Figure 3-4 Internal Clock Operation

3.5 Registers

When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions with the internal Relaxation Oscillator, since the 56F8322 and 56F8122 contain this oscillator.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 29 Preliminary

Part 4 Memory Map

4.1 Introduction

The 56F8322 and 56F8122 devices are 16-bit motor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM and Flash memories are used in both spaces.

This section provides memory maps for:

• Program Address Space, including the Interrupt Vector Table

• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps

On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1.

Note: Data Flash and Program RAM are NOT available on the 56F8122 device.

Table 4-1 Chip Memory Configurations

On-Chip Memory 56F8322 56F8122 Use Restrictions

Program Flash

Data Flash

Program RAM

Data RAM

Program Boot Flash

32KB 32KB

8KB —

4KB —

8KB 8KB

Erase / Program via Flash interface unit and word writes to CDBW

Erase / Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously.

None

Erase / Program via Flash Interface unit and word writes to CDBW

4.2 Program Map

The Program Memory map is located in Table 4-2. The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) usually control the Program Memory map. Because the 56F8322 and 56F8122 do not include EMI, the OMR MA bit, which is used to decide internal or external BOOT, will have no effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash. After reset, changing the OMR MB bit will have no effect on the Program Flash.

56F8322 Techncial Data, Rev. 10.0

30 Freescale Semiconductor

Preliminary

Note: Program RAM is NOT available on the 56F8122 device.

Table 4-2 Program Memory Map at Reset

Begin/End Address Memory Allocation

P: $1F FFFF P: $03 0000

P: $02 FFFF P: $02 F800

P: $02 F7FF P: $02 1000

P: $02 0FFF P: $02 0000

P: $01 FFFF P: $00 4000

P: $00 3FFF P: $00 0000

RESERVED

On-Chip Program RAM

4KB

RESERVED

Boot Flash 8KB Cop Reset Address = $02 0002 Boot Location = $02 0000

RESERVED

Internal Program Flash 32KB

Interrupt Vector Table

4.3 Interrupt Vector Table

Table 4-3 provides the device’s reset and interrupt priority structure, including on-chip peripherals. The

table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority.

The location of the vector table is determined by the Vector Base Address (VBA). Please see

Section 5.6.11 for the reset value of the VBA.

In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions.

Note: PWM, CAN and Quadrature Decoder are NOT available on the 56F8122 device.

Table 4-3 Interrupt Vector Table Contents

Peripheral

core 2 3 P:$04 Illegal Instruction

core 3 3 P:$06 SW Interrupt 3

core 4 3 P:$08 HW Stack Overflow

core 5 3 P:$0A Misaligned Long Word Access

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

Reserved for Reset Overlay2

Reserved for COP Reset Overlay2

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 31 Preliminary

Table 4-3 Interrupt Vector Table Contents1 (Continued)

Peripheral

core 6 1-3 P:$0C OnCE Step Counter

core 7 1-3 P:$0E OnCE Breakpoint Unit 0

core 9 1-3 P:$12 OnCE Trace Buffer

core 10 1-3 P:$14 OnCE Transmit Register Empty

core 11 1-3 P:$16 OnCE Receive Register Full

core 14 2 P:$1C SW Interrupt 2

core 15 1 P:$1E SW Interrupt 1

core 16 0 P:$20 SW Interrupt 0

core 17 0-2 P:$22 IRQA

LVI 20 0-2 P:$28 Low-Voltage Detector (power sense)

PLL 21 0-2 P:$2A PLL

FM 22 0-2 P:$2C FM Access Error Interrupt

FM 23 0-2 P:$2E FM Command Complete

FM 24 0-2 P:$30 FM Command, data and address Buffers Empty

FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off

FLEXCAN 27 0-2 P:$36 FLEXCAN Error

FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up

FLEXCAN 29 0-2 P:$3A FLEXCAN Message Buffer Interrupt

GPIOC 33 0-2 P:$42 GPIO C

GPIOB 34 0-2 P:$44 GPIO B

GPIOA 35 0-2 P:$46 GPIO A

SPI1 38 0-2 P:$4C SPI 1 Receiver Full

SPI1 39 0-2 P:$4E SPI 1 Transmitter Empty

SPI0 40 0-2 P:$50 SPI 0 Receiver Full

SPI0 41 0-2 P:$52 SPI 0 Transmitter Empty

SCI1 42 0-2 P:$54 SCI 1 Transmitter Empty

SCI1 43 0-2 P:$56 SCI 1Transmitter Idle

SCI1 45 0-2 P:$5A SCI 1 Receiver Error

SCI1 46 0-2 P:$5C SCI 1 Receiver Full

DEC0 49 0-2 P:$62 Quadrature Decoder #0 Home Switch or Watchdog

DEC0 50 0-2 P:$64 Quadrature Decoder #0 INDEX Pulse

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

Reserved

56F8322 Techncial Data, Rev. 10.0

32 Freescale Semiconductor

Preliminary

Table 4-3 Interrupt Vector Table Contents1 (Continued)

Interrupt Vector Table

Peripheral

TMRC 56 0-2 P:$70 Timer C Channel 0

TMRC 57 0-2 P:$72 Timer C Channel 1

TMRC 58 0-2 P:$74 Timer C Channel 2

TMRC 59 0-2 P:$76 Timer C Channel 3

TMRA 64 0-2 P:$80 Timer A Channel 0

TMRA 65 0-2 P:$82 Timer A Channel 1

TMRA 66 0-2 P:$84 Timer A Channel 2

TMRA 67 0-2 P:$86 Timer A Channel 3

SCI0 68 0-2 P:$88 SCI 0 Transmitter Empty

SCI0 69 0-2 P:$8A SCI 0 Transmitter Idle

SCI0 71 0-2 P:$8E SCI 0 Receiver Error

SCI0 72 0-2 P:$90 SCI 0 Receiver Full

ADCA 74 0-2 P:$94 ADC A Conversion Complete / End of Scan

ADCA 76 0-2 P:$98 ADC A Zero Crossing or Limit Error

PWMA 78 0-2 P:$9C Reload PWM A

PWMA 80 0-2 P:$A0 PWM A Fault

core 81 - 1 P:$A2 SW Interrupt LP

1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address.

2. If the VBA is set to $0200, the first two locations of the vector table will overlay the chip reset addresses.

Vector

Number

82 0 - 2 P:$A4

Priority

Level

Vector Base

Address +

Interrupt Function

Reserved

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 33 Preliminary

4.4 Data Map

Note: Data Flash is NOT available on the 56F8122 device.

Table 4-4 Data Memory Map

Begin/End Address Memory Allocation

X:$FF FFFF X:$FF FF00

X:$FF FEFF X:$01 0000

X:$00 FFFF X:$00 F000

X:$00 EFFF X:$00 2000

X:$00 1FFF X:$00 1000

X:$00 0FFF X:$00 0000

1. All addresses are 16-bit Word addresses.

2. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle, long-word operations

EOnCE 256 locations allocated

RESERVED

On-Chip Peripherals 4096 locations allocated

RESERVED

On-Chip Data Flash

8KB

On-Chip Data RAM

8KB

4.5 Flash Memory Map

Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.

Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers.

The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configure parameters are located between $00_3FF7 and $00_3FFF.

56F8322 Techncial Data, Rev. 10.0

34 Freescale Semiconductor

Preliminary

Flash Memory Map

Data Memory

Banked Registers

Unbanked Registers

BOOT_FLASH_START + $0FFF

BOOT_FLASH_START = $02_0000

Program Memory

8KB

Boot

Reserved

FM_BASE + $14

FM_BASE + $00

DATA_FLASH_START + $0FFF

8KB

DATA_FLASH_START + $0000

PROG_FLASH_START + $00_3FFF PROG_FLASH_START + $00_3FF7 PROG_FLASH_START + $00_3FF6

Configure Field

Block 0 Odd

FM_PROG_MEM_TOP = $00_3FFF

Note: Data Flash is NOT available in the 56F8122 device.

Block 0 Even

32KB

PROG_FLASH_START = $00_0000

. . .

BLOCK 0 Odd (2 Bytes) $00_0003 BLOCK 0 Even (2 Bytes) $00_0002 BLOCK 0 Odd (2 Bytes) $00_0001 BLOCK 0 Even (2 Bytes) $00_0000

Figure 4-1 Flash Array Memory Maps

Table 4-5 shows the page and sector sizes used within each Flash memory block on the chip.

Note: Data Flash is NOT available on the 56F8122 device.

Table 4-5 Flash Memory Partitions

Flash Size Sectors Sector Size Page Size

Program Flash 32KB 16 1K x 16 bits 512 x 16 bits

Data Flash 8KB 16 256 x 16 bits 256 x 16 bits

Boot Flash 8KB 4 1K x 16 bits 256 x 16 bits

Please see the 56F8300 Peripheral User Manual for additional Flash information.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 35 Preliminary

4.6 EOnCE Memory Map

Table 4-6 EOnCE Memory Map

Address Register Acronym Register Name

Reserved

X:$FF FF8A OESCR External Signal Control Register

Reserved

X:$FF FF8E OBCNTR Breakpoint Unit [0] Counter

Reserved

X:$FF FF90 OBMSK (32 bits) Breakpoint 1 Unit [0] Mask Register

X:$FF FF91 — Breakpoint 1 Unit [0] Mask Register

X:$FF FF92 OBAR2 (32 bits) Breakpoint 2 Unit [0] Address Register

X:$FF FF93 — Breakpoint 2 Unit [0] Address Register

X:$FF FF94 OBAR1 (24 bits) Breakpoint 1 Unit [0] Address Register

X:$FF FF95 — Breakpoint 1 Unit [0] Address Register

X:$FF FF96 OBCR (24 bits) Breakpoint Unit [0] Control Register

X:$FF FF97 — Breakpoint Unit [0] Control Register

X:$FF FF98 OTB (21-24 bits/stage) Trace Buffer Register Stages

X:$FF FF99 — Trace Buffer Register Stages

X:$FF FF9A OTBPR (8 bits) Trace Buffer Pointer Register

X:$FF FF9B OTBCR Trace Buffer Control Register

X:$FF FF9C OBASE (8 bits) Peripheral Base Address Register

X:$FF FF9D OSR Status Register

X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter

X:$FF FF9F — Instruction Step Counter

X:$FF FFA0 OCR (bits) Control Register

Reserved

X:$FF FFFC OCLSR (8 bits) Core Lock / Unlock Status Register

X:$FF FFFD OTXRXSR (8 bits) Transmit and Receive Status and Control Register

X:$FF FFFE OTX / ORX (32 bits) Transmit Register / Receive Register

X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word

Receive Register Upper Word

4.7 Peripheral Memory Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only.

Table 4-7 summarizes base addresses for the set of peripherals on the 56F8322 and 56F8122 devices.

Peripherals are listed in order of the base address.

56F8322 Techncial Data, Rev. 10.0

36 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

The following tables list all of the peripheral registers required to control or access the peripherals.

Note: Features in italics are NOT available on the 56F8122 device.

Table 4-7 Data Memory Peripheral Base Address Map Summary

Peripheral Prefix Base Address Table Number

Timer A TMRA X:$00 F040 4-8

Timer C TMRC X:$00 F0C0 4-9

PWM A PWMA X:$00 F140 4-10

Quadrature Decoder 0 DEC0 X:$00 F180 4-11

ITCN ITCN X:$00 F1A0 4-12

ADC A ADCA X:$00 F200 4-13

Temperature Sensor TSENSOR X:$00 F270 4-14

SCI #0 SCI0 X:$00 F280 4-15

SCI #1 SCI1 X:$00 F290 4-16

SPI #0 SPI0 X:$00 F2A0 4-17

SPI #1 SPI1 X:$00 F2B0 4-18

COP COP X:$00 F2C0 4-19

PLL, OSC CLKGEN X:$00 F2D0 4-20

GPIO Port A GPIOA X:$00 F2E0 4-21

GPIO Port B GPIOB X:$00 F300 4-22

GPIO Port C GPIOC X:$00 F310 4-23

SIM SIM X:$00 F350 4-24

Power Supervisor LVI X:$00 F360 4-25

FM FM X:$00 F400 4-26

FlexCAN FC X:$00 F800 4-27

Table 4-8 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040)

TMRA0_CMP1 $0 Compare Register 1

TMRA0_CMP2 $1 Compare Register 2

TMRA0_CAP $2 Capture Register

TMRA0_LOAD $3 Load Register

TMRA0_HOLD $4 Hold Register

TMRA0_CNTR $5 Counter Register

TMRA0_CTRL $6 Control Register

TMRA0_SCR $7 Status and Control Register

TMRA0_CMPLD1 $8 Comparator Load Register 1

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 37 Preliminary

Table 4-8 Quad Timer A Registers Address Map (Continued)

(TMRA_BASE = $00 F040)

TMRA0_CMPLD2 $9 Comparator Load Register 2

TMRA0_COMSCR $A Comparator Status and Control Register

Reserved

TMRA1_CMP1 $10 Compare Register 1

TMRA1_CMP2 $11 Compare Register 2

TMRA1_CAP $12 Capture Register

TMRA1_LOAD $13 Load Register

TMRA1_HOLD $14 Hold Register

TMRA1_CNTR $15 Counter Register

TMRA1_CTRL $16 Control Register

TMRA1_SCR $17 Status and Control Register

TMRA1_CMPLD1 $18 Comparator Load Register 1

TMRA1_CMPLD2 $19 Comparator Load Register 2

TMRA1_COMSCR $1A Comparator Status and Control Register

Reserved

TMRA2_CMP1 $20 Compare Register 1

TMRA2_CMP2 $21 Compare Register 2

TMRA2_CAP $22 Capture Register

TMRA2_LOAD $23 Load Register

TMRA2_HOLD $24 Hold Register

TMRA2_CNTR $25 Counter Register

TMRA2_CTRL $26 Control Register

TMRA2_SCR $27 Status and Control Register

TMRA2_CMPLD1 $28 Comparator Load Register 1

TMRA2_CMPLD2 $29 Comparator Load Register 2

TMRA2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRA3_CMP1 $30 Compare Register 1

TMRA3_CMP2 $31 Compare Register 2

TMRA3_CAP $32 Capture Register

TMRA3_LOAD $33 Load Register

TMRA3_HOLD $34 Hold Register

TMRA3_CNTR $35 Counter Register

TMRA3_CTRL $36 Control Register

TMRA3_SCR $37 Status and Control Register

TMRA3_CMPLD1 $38 Comparator Load Register 1

TMRA3_CMPLD2 $39 Comparator Load Register 2

TMRA3_COMSCR $3A Comparator Status and Control Register

56F8322 Techncial Data, Rev. 10.0

38 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

Table 4-9 Quad Timer C Registers Address Map

(TMRC_BASE = $00 F0C0)

TMRC0_CMP1 $0 Compare Register 1

TMRC0_CMP2 $1 Compare Register 2

TMRC0_CAP $2 Capture Register

TMRC0_LOAD $3 Load Register

TMRC0_HOLD $4 Hold Register

TMRC0_CNTR $5 Counter Register

TMRC0_CTRL $6 Control Register

TMRC0_SCR $7 Status and Control Register

TMRC0_CMPLD1 $8 Comparator Load Register 1

TMRC0_CMPLD2 $9 Comparator Load Register 2

TMRC0_COMSCR $A Comparator Status and Control Register

Reserved

TMRC1_CMP1 $10 Compare Register 1

TMRC1_CMP2 $11 Compare Register 2

TMRC1_CAP $12 Capture Register

TMRC1_LOAD $13 Load Register

TMRC1_HOLD $14 Hold Register

TMRC1_CNTR $15 Counter Register

TMRC1_CTRL $16 Control Register

TMRC1_SCR $17 Status and Control Register

TMRC1_CMPLD1 $18 Comparator Load Register 1

TMRC1_CMPLD2 $19 Comparator Load Register 2

TMRC1_COMSCR $1A Comparator Status and Control Register

Reserved

TMRC2_CMP1 $20 Compare Register 1

TMRC2_CMP2 $21 Compare Register 2

TMRC2_CAP $22 Capture Register

TMRC2_LOAD $23 Load Register

TMRC2_HOLD $24 Hold Register

TMRC2_CNTR $25 Counter Register

TMRC2_CTRL $26 Control Register

TMRC2_SCR $27 Status and Control Register

TMRC2_CMPLD1 $28 Comparator Load Register 1

TMRC2_CMPLD2 $29 Comparator Load Register 2

TMRC2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRC3_CMP1 $30 Compare Register 1

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 39 Preliminary

Table 4-9 Quad Timer C Registers Address Map (Continued)

(TMRC_BASE = $00 F0C0)

TMRC3_CMP2 $31 Compare Register 2

TMRC3_CAP $32 Capture Register

TMRC3_LOAD $33 Load Register

TMRC3_HOLD $34 Hold Register

TMRC3_CNTR $35 Counter Register

TMRC3_CTRL $36 Control Register

TMRC3_SCR $37 Status and Control Register

TMRC3_CMPLD1 $38 Comparator Load Register 1

TMRC3_CMPLD2 $39 Comparator Load Register 2

TMRC3_COMSCR $3A Comparator Status and Control Register

Table 4-10 Pulse Width Modulator A Registers Address Map

(PWMA_BASE = $00 F140)

PWM is NOT available in the 56F8122 device

PWMA_PMCTRL $0 Control Register

PWMA_PMFCTRL $1 Fault Control Register

PWMA_PMFSA $2 Fault Status Acknowledge Register

PWMA_PMOUT $3 Output Control Register

PWMA_PMCNT $4 Counter Register

PWMA_PWMCM $5 Counter Modulo Register

PWMA_PWMVAL0 $6 Value Register 0

PWMA_PWMVAL1 $7 Value Register 1

PWMA_PWMVAL2 $8 Value Register 2

PWMA_PWMVAL3 $9 Value Register 3

PWMA_PWMVAL4 $A Value Register 4

PWMA_PWMVAL5 $B Value Register 5

PWMA_PMDEADTM $C Dead Time Register

PWMA_PMDISMAP1 $D Disable Mapping Register 1

PWMA_PMDISMAP2 $E Disable Mapping Register 2

PWMA_PMCFG $F Configure Register

PWMA_PMCCR $10 Channel Control Register

PWMA_PMPORT $11 Port Register

PWMA_PMICCR $12 Internal Correction Control

56F8322 Techncial Data, Rev. 10.0

40 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

Table 4-11 Quadrature Decoder 0 Registers Address Map

(DEC0_BASE = $00 F180)

Quadrature Decoder is NOT available in the 56F8122 device

DEC0_DECCR $0 Decoder Control Register

DEC0_FIR $1 Filter Interval Register

DEC0_WTR $2 Watchdog Time-out Register

DEC0_POSD $3 Position Difference Counter Register

DEC0_POSDH $4 Position Difference Counter Hold Register

DEC0_REV $5 Revolution Counter Register

DEC0_REVH $6 Revolution Hold Register

DEC0_UPOS $7 Upper Position Counter Register

DEC0_LPOS $8 Lower Position Counter Register

DEC0_UPOSH $9 Upper Position Hold Register

DEC0_LPOSH $A Lower Position Hold Register

DEC0_UIR $B Upper Initialization Register

DEC0_LIR $C Lower Initialization Register

DEC0_IMR $D Input Monitor Register

Table 4-12 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

IPR0 $0 Interrupt Priority Register 0

IPR1 $1 Interrupt Priority Register 1

IPR2 $2 Interrupt Priority Register 2

IPR3 $3 Interrupt Priority Register 3

IPR4 $4 Interrupt Priority Register 4

IPR5 $5 Interrupt Priority Register 5

IPR6 $6 Interrupt Priority Register 6

IPR7 $7 Interrupt Priority Register 7

IPR8 $8 Interrupt Priority Register 8

IPR9 $9 Interrupt Priority Register 9

VBA $A Vector Base Address Register

FIM0 $B Fast Interrupt Match Register 0

FIVAL0 $C Fast Interrupt Vector Address Low 0 Register

FIVAH0 $D Fast Interrupt Vector Address High 0 Register

FIM1 $E Fast Interrupt Match Register 1

FIVAL1 $F Fast Interrupt Vector Address Low 1 Register

FIVAH1 $10 Fast Interrupt Vector Address High 1 Register

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 41 Preliminary

Table 4-12 Interrupt Control Registers Address Map (Continued)

(ITCN_BASE = $00 F1A0)

IRQP 0 $11 IRQ Pending Register 0

IRQP 1 $12 IRQ Pending Register 1

IRQP 2 $13 IRQ Pending Register 2

IRQP 3 $14 IRQ Pending Register 3

IRQP 4 $15 IRQ Pending Register 4

IRQP 5 $16 IRQ Pending Register 5

Reserved

ICTL $1D Interrupt Control Register

Table 4-13 Analog to Digital Converter Registers Address Map

(ADCA_BASE = $00 F200)

ADCA_CR1 $0 Control Register 1

ADCA_CR2 $1 Control Register 2

ADCA_ZCC $2 Zero Crossing Control Register

ADCA_LST 1 $3 Channel List Register 1

ADCA_LST 2 $4 Channel List Register 2

ADCA_SDIS $5 Sample Disable Register

ADCA_STAT $6 Status Register

ADCA_LSTAT $7 Limit Status Register

ADCA_ZCSTAT $8 Zero Crossing Status Register

ADCA_RSLT 0 $9 Result Register 0

ADCA_RSLT 1 $A Result Register 1

ADCA_RSLT 2 $B Result Register 2

ADCA_RSLT 3 $C Result Register 3

ADCA_RSLT 4 $D Result Register 4

ADCA_RSLT 5 $E Result Register 5

ADCA_RSLT 6 $F Result Register 6

ADCA_RSLT 7 $10 Result Register 7

ADCA_LLMT 0 $11 Low Limit Register 0

ADCA_LLMT 1 $12 Low Limit Register 1

ADCA_LLMT 2 $13 Low Limit Register 2

ADCA_LLMT 3 $14 Low Limit Register 3

ADCA_LLMT 4 $15 Low Limit Register 4

ADCA_LLMT 5 $16 Low Limit Register 5

ADCA_LLMT 6 $17 Low Limit Register 6

ADCA_LLMT 7 $18 Low Limit Register 7

ADCA_HLMT 0 $19 High Limit Register 0

56F8322 Techncial Data, Rev. 10.0

42 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

Table 4-13 Analog to Digital Converter Registers Address Map (Continued)

(ADCA_BASE = $00 F200)

ADCA_HLMT 1 $1A High Limit Register 1

ADCA_HLMT 2 $1B High Limit Register 2

ADCA_HLMT 3 $1C High Limit Register 3

ADCA_HLMT 4 $1D High Limit Register 4

ADCA_HLMT 5 $1E High Limit Register 5

ADCA_HLMT 6 $1F High Limit Register 6

ADCA_HLMT 7 $20 High Limit Register 7

ADCA_OFS 0 $21 Offset Register 0

ADCA_OFS 1 $22 Offset Register 1

ADCA_OFS 2 $23 Offset Register 2

ADCA_OFS 3 $24 Offset Register 3

ADCA_OFS 4 $25 Offset Register 4

ADCA_OFS 5 $26 Offset Register 5

ADCA_OFS 6 $27 Offset Register 6

ADCA_OFS 7 $28 Offset Register 7

ADCA_POWER $29 Power Control Register

ADCA_CAL $2A ADC Calibration Register

Table 4-14 Temperature Sensor Register Address Map

(TSENSOR_BASE = $00 F270)

Temperature Sensor is NOT available in the 56F8122 device

TSENSOR_CNTL $0 Control Register

Table 4-15 Serial Communication Interface 0 Registers Address Map

(SCI0_BASE = $00 F280)

SCI0_SCIBR $0 Baud Rate Register

SCI0_SCICR $1 Control Register

Reserved

SCI0_SCISR $3 Status Register

SCI0_SCIDR $4 Data Register

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 43 Preliminary

Table 4-16 Serial Communication Interface 1 Registers Address Map

(SCI1_BASE = $00 F290)

SCI1_SCIBR $0 Baud Rate Register

SCI1_SCICR $1 Control Register

Reserved

SCI1_SCISR $3 Status Register

SCI1_SCIDR $4 Data Register

Table 4-17 Serial Peripheral Interface 0 Registers Address Map

(SPI0_BASE = $00 F2A0)

SPI0_SPSCR $0 Status and Control Register

SPI0_SPDSR $1 Data Size Register

SPI0_SPDRR $2 Data Receive Register

SPI0_SPDTR $3 Data Transmitter Register

Table 4-18 Serial Peripheral Interface 1 Registers Address Map

(SPI1_BASE = $00 F2B0)

SPI1_SPSCR $0 Status and Control Register

SPI1_SPDSR $1 Data Size Register

SPI1_SPDRR $2 Data Receive Register

SPI1_SPDTR $3 Data Transmitter Register

Table 4-19 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F2C0)

COPCTL $0 Control Register

COPTO $1 Time-Out Register

COPCTR $2 Counter Register

56F8322 Techncial Data, Rev. 10.0

44 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

Table 4-20 Clock Generation Module Registers Address Map

(CLKGEN_BASE = $00 F2D0)

PLLCR $0 Control Register

PLLDB $1 Divide-By Register

PLLSR $2 Status Register

Reserved

SHUTDOWN $4 Shutdown Register

OSCTL $5 Oscillator Control Register

Table 4-21 GPIOA Registers Address Map

(GPIOA_BASE = $00 F2E0)

GPIOA_PUR $0 Pull-up Enable Register 0 x 0FFF

GPIOA_DR $1 Data Register 0 x 0000

GPIOA_DDR $2 Data Direction Register 0 x 0000

GPIOA_PER $3 Peripheral Enable Register 0 x 0FFF

GPIOA_IAR $4 Interrupt Assert Register 0 x 0000

GPIOA_IENR $5 Interrupt Enable Register 0 x 0000

GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOA_IPR $7 Interrupt Pending Register 0 x 0000

GPIOA_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 0FFF

GPIOA_RAWDATA $A Raw Data Input Register —

Address Offset Register Description Reset Value

Table 4-22 GPIOB Registers Address Map

(GPIOB_BASE = $00 F300)

GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF

GPIOB_DR $1 Data Register 0 x 0000

GPIOB_DDR $2 Data Direction Register 0 x 0000

GPIOB_PER $3 Peripheral Enable Register 0 x 00FF

GPIOB_IAR $4 Interrupt Assert Register 0 x 0000

GPIOB_IENR $5 Interrupt Enable Register 0 x 0000

GPIOB_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOB_IPR $7 Interrupt Pending Register 0 x 0000

GPIOB_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOB_PPMODE $9 Push-Pull Mode Register 0 x 00FF

GPIOB_RAWDATA $A Raw Data Input Register —

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 45 Preliminary

Table 4-23 GPIOC Registers Address Map

(GPIOC_BASE = $00F310)

GPIOC_PUR $0 Pull-up Enable Register 0 x 007C

GPIOC_DR $1 Data Register 0 x 0000

GPIOC_DDR $2 Data Direction Register 0 x 0000

GPIOC_PER $3 Peripheral Enable Register 0 x 007F

GPIOC_IAR $4 Interrupt Assert Register 0 x 0000

GPIOC_IENR $5 Interrupt Enable Register 0 x 0000

GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOC_IPR $7 Interrupt Pending Register 0 x 0000

GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 007F

GPIOC_RAWDATA $A Raw Data Input Register —

Table 4-24 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

SIM_CONTROL $0 Control Register

SIM_RSTSTS $1 Reset Status Register

SIM_SCR0 $2 Software Control Register 0

SIM_SCR1 $3 Software Control Register 1

SIM_SCR2 $4 Software Control Register 2

SIM_SCR3 $5 Software Control Register 3

SIM_MSH_ID $6 Most Significant Half JTAG ID

SIM_LSH_ID $7 Least Significant Half JTAG ID

SIM_PUDR $8 Pull-up Disable Register

Reserved

SIM_CLKOSR $A Clock Out Select Register

SIM_GPS $B GPIO Peripheral Select Register

SIM_PCE $C Peripheral Clock Enable Register

SIM_ISALH $D I/O Short Address Location High Register

SIM_ISALL $E I/O Short Address Location Low Register

Table 4-25 Power Supervisor Registers Address Map

(LVI_BASE = $00 F360)

LVI_CONTROL $0 Control Register

LVI_STATUS $1 Status Register

56F8322 Techncial Data, Rev. 10.0

46 Freescale Semiconductor

Preliminary

Table 4-26 Flash Module Registers Address Map

(FM_BASE = $00 F400)

FMCLKD $0 Clock Divider Register

FMMCR $1 Module Control Register

Reserved

FMSECH $3 Security High Half Register

FMSECL $4 Security Low Half Register

Reserved

FMPROT $10 Protection Register (Banked)

FMPROTB $11 Protection Boot Register (Banked)

Reserved

FMUSTAT $13 User Status Register (Banked)

FMCMD $14 Command Register (Banked)

Reserved

FMOPT 0 $1A 16-Bit Information Option Register 0

Hot temperature ADC reading of Temperature Sensor; value set during factory test

FMOPT 1 $1B 16-Bit Information Option Register 1

Trim cap setting of the relaxation oscillator

FMOPT 2 $1C 16-Bit Information Option Register 2

Room temperature ADC reading of Temperature Sensor; value set during factory test

Peripheral Memory Mapped Registers

Table 4-27 FlexCAN Registers Address Map

(FC_BASE = $00 F800)

FlexCAN is NOT available in the 56F8122 device

FCMCR $0 Module Configuration Register

Reserved

FCCTL0 $3 Control Register 0 Register

FCCTL1 $4 Control Register 1 Register

FCTMR $5 Free-Running Timer Register

FCMAXMB $6 Maximum Message Buffer Configuration Register

Reserved

FCRXGMASK_H $8 Receive Global Mask High Register

FCRXGMASK_L $9 Receive Global Mask Low Register

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 47 Preliminary

Table 4-27 FlexCAN Registers Address Map (Continued)

(FC_BASE = $00 F800)

FlexCAN is NOT available in the 56F8122 device

FCRX14MASK_H $A Receive Buffer 14 Mask High Register

FCRX14MASK_L $B Receive Buffer 14 Mask Low Register

FCRX15MASK_H $C Receive Buffer 15 Mask High Register

FCRX15MASK_L $D Receive Buffer 15 Mask Low Register

Reserved

FCSTATUS $10 Error and Status Register

FCIMASK1 $11 Interrupt Masks 1 Register

FCIFLAG1 $12 Interrupt Flags 1 Register

FCR/T_ERROR_CNTRS $13 Receive and Transmit Error Counters Register

Reserved

FCMB0_CONTROL $40 Message Buffer 0 Control / Status Register

FCMB0_ID_HIGH $41 Message Buffer 0 ID High Register

FCMB0_ID_LOW $42 Message Buffer 0 ID Low Register

FCMB0_DATA $43 Message Buffer 0 Data Register

FCMB0_DATA $44 Message Buffer 0 Data Register

FCMB0_DATA $45 Message Buffer 0 Data Register

FCMB0_DATA $46 Message Buffer 0 Data Register

Reserved

FCMSB1_CONTROL $48 Message Buffer 1 Control / Status Register

FCMSB1_ID_HIGH $49 Message Buffer 1 ID High Register

FCMSB1_ID_LOW $4A Message Buffer 1 ID Low Register

FCMB1_DATA $4B Message Buffer 1 Data Register

FCMB1_DATA $4C Message Buffer 1 Data Register

FCMB1_DATA $4D Message Buffer 1 Data Register

FCMB1_DATA $4E Message Buffer 1 Data Register

Reserved

FCMB2_CONTROL $50 Message Buffer 2 Control / Status Register

FCMB2_ID_HIGH $51 Message Buffer 2 ID High Register

FCMB2_ID_LOW $52 Message Buffer 2 ID Low Register

FCMB2_DATA $53 Message Buffer 2 Data Register

FCMB2_DATA $54 Message Buffer 2 Data Register

FCMB2_DATA $55 Message Buffer 2 Data Register

FCMB2_DATA $56 Message Buffer 2 Data Register

Reserved

56F8322 Techncial Data, Rev. 10.0

48 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

Table 4-27 FlexCAN Registers Address Map (Continued)

(FC_BASE = $00 F800)

FlexCAN is NOT available in the 56F8122 device

FCMB3_CONTROL $58 Message Buffer 3 Control / Status Register

FCMB3_ID_HIGH $59 Message Buffer 3 ID High Register

FCMB3_ID_LOW $5A Message Buffer 3 ID Low Register

FCMB3_DATA $5B Message Buffer 3 Data Register

FCMB3_DATA $5C Message Buffer 3 Data Register

FCMB3_DATA $5D Message Buffer 3 Data Register

FCMB3_DATA $5E Message Buffer 3 Data Register

Reserved

FCMB4_CONTROL $60 Message Buffer 4 Control / Status Register

FCMB4_ID_HIGH $61 Message Buffer 4 ID High Register

FCMB4_ID_LOW $62 Message Buffer 4 ID Low Register

FCMB4_DATA $63 Message Buffer 4 Data Register

FCMB4_DATA $64 Message Buffer 4 Data Register

FCMB4_DATA $65 Message Buffer 4 Data Register

FCMB4_DATA $66 Message Buffer 4 Data Register

Reserved

FCMB5_CONTROL $68 Message Buffer 5 Control / Status Register

FCMB5_ID_HIGH $69 Message Buffer 5 ID High Register

FCMB5_ID_LOW $6A Message Buffer 5 ID Low Register

FCMB5_DATA $6B Message Buffer 5 Data Register

FCMB5_DATA $6C Message Buffer 5 Data Register

FCMB5_DATA $6D Message Buffer 5 Data Register

FCMB5_DATA $6E Message Buffer 5 Data Register

Reserved

FCMB6_CONTROL $70 Message Buffer 6 Control / Status Register

FCMB6_ID_HIGH $71 Message Buffer 6 ID High Register

FCMB6_ID_LOW $72 Message Buffer 6 ID Low Register

FCMB6_DATA $73 Message Buffer 6 Data Register

FCMB6_DATA $74 Message Buffer 6 Data Register

FCMB6_DATA $75 Message Buffer 6 Data Register

FCMB6_DATA $76 Message Buffer 6 Data Register

Reserved

FCMB7_CONTROL $78 Message Buffer 7 Control / Status Register

FCMB7_ID_HIGH $79 Message Buffer 7 ID High Register

FCMB7_ID_LOW $7A Message Buffer 7 ID Low Register

FCMB7_DATA $7B Message Buffer 7 Data Register

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 49 Preliminary

Table 4-27 FlexCAN Registers Address Map (Continued)

(FC_BASE = $00 F800)

FlexCAN is NOT available in the 56F8122 device

FCMB7_DATA $7C Message Buffer 7 Data Register

FCMB7_DATA $7D Message Buffer 7 Data Register

FCMB7_DATA $7E Message Buffer 7 Data Register

Reserved

FCMB8_CONTROL $80 Message Buffer 8 Control / Status Register

FCMB8_ID_HIGH $81 Message Buffer 8 ID High Register

FCMB8_ID_LOW $82 Message Buffer 8 ID Low Register

FCMB8_DATA $83 Message Buffer 8 Data Register

FCMB8_DATA $84 Message Buffer 8 Data Register

FCMB8_DATA $85 Message Buffer 8 Data Register

FCMB8_DATA $86 Message Buffer 8 Data Register

Reserved

FCMB9_CONTROL $88 Message Buffer 9 Control / Status Register

FCMB9_ID_HIGH $89 Message Buffer 9 ID High Register

FCMB9_ID_LOW $8A Message Buffer 9 ID Low Register

FCMB9_DATA $8B Message Buffer 9 Data Register

FCMB9_DATA $8C Message Buffer 9 Data Register

FCMB9_DATA $8D Message Buffer 9 Data Register

FCMB9_DATA $8E Message Buffer 9 Data Register

Reserved

FCMB10_CONTROL $90 Message Buffer 10 Control / Status Register

FCMB10_ID_HIGH $91 Message Buffer 10 ID High Register

FCMB10_ID_LOW $92 Message Buffer 10 ID Low Register

FCMB10_DATA $93 Message Buffer 10 Data Register

FCMB10_DATA $94 Message Buffer 10 Data Register

FCMB10_DATA $95 Message Buffer 10 Data Register

FCMB10_DATA $96 Message Buffer 10 Data Register

Reserved

FCMB11_CONTROL $98 Message Buffer 11 Control / Status Register

FCMB11_ID_HIGH $99 Message Buffer 11 ID High Register

FCMB11_ID_LOW $9A Message Buffer 11 ID Low Register

FCMB11_DATA $9B Message Buffer 11 Data Register

FCMB11_DATA $9C Message Buffer 11 Data Register

FCMB11_DATA $9D Message Buffer 11 Data Register

FCMB11_DATA $9E Message Buffer 11 Data Register

Reserved

FCMB12_CONTROL $A0 Message Buffer 12 Control / Status Register

56F8322 Techncial Data, Rev. 10.0

50 Freescale Semiconductor

Preliminary

Peripheral Memory Mapped Registers

Table 4-27 FlexCAN Registers Address Map (Continued)

(FC_BASE = $00 F800)

FlexCAN is NOT available in the 56F8122 device

FCMB12_ID_HIGH $A1 Message Buffer 12 ID High Register

FCMB12_ID_LOW $A2 Message Buffer 12 ID Low Register

FCMB12_DATA $A3 Message Buffer 12 Data Register

FCMB12_DATA $A4 Message Buffer 12 Data Register

FCMB12_DATA $A5 Message Buffer 12 Data Register

FCMB12_DATA $A6 Message Buffer 12 Data Register

Reserved

FCMB13_CONTROL $A8 Message Buffer 13 Control / Status Register

FCMB13_ID_HIGH $A9 Message Buffer 13 ID High Register

FCMB13_ID_LOW $AA Message Buffer 13 ID Low Register

FCMB13_DATA $AB Message Buffer 13 Data Register

FCMB13_DATA $AC Message Buffer 13 Data Register

FCMB13_DATA $AD Message Buffer 13 Data Register

FCMB13_DATA $AE Message Buffer 13 Data Register

Reserved

FCMB14_CONTROL $B0 Message Buffer 14 Control / Status Register

FCMB14_ID_HIGH $B1 Message Buffer 14 ID High Register

FCMB14_ID_LOW $B2 Message Buffer 14 ID Low Register

FCMB14_DATA $B3 Message Buffer 14 Data Register

FCMB14_DATA $B4 Message Buffer 14 Data Register

FCMB14_DATA $B5 Message Buffer 14 Data Register

FCMB14_DATA $B6 Message Buffer 14 Data Register

Reserved

FCMB15_CONTROL $B8 Message Buffer 15 Control / Status Register

FCMB15_ID_HIGH $B9 Message Buffer 15 ID High Register

FCMB15_ID_LOW $BA Message Buffer 15 ID Low Register

FCMB15_DATA $BB Message Buffer 15 Data Register

FCMB15_DATA $BC Message Buffer 15 Data Register

FCMB15_DATA $BD Message Buffer 15 Data Register

FCMB15_DATA $BE Message Buffer 15 Data Register

Reserved

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 51 Preliminary

4.8 Factory-Programmed Memory

The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and

Data Flash (not available on the 56F8122) memories of the device. The 56F83xx SCI/CAN Bootloader User Manual provides detailed information on this firmware. An application note, Production Flash Programming, details how the Serial Bootloader program can be used to perform production Flash

programming of the on-board Flash memories as well as other optional methods.

Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the Boot Flash memory.

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

• Programmable priority levels for each IRQ

• Two programmable Fast Interrupts

• Notification to SIM module to restart clocks out of Wait and Stop modes

• Drives initial address on the address bus after reset

For further information, see Table 4-3, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number 81 is the lowest.

5.3.1 Normal Interrupt Handling

Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt.

56F8322 Techncial Data, Rev. 10.0

52 Freescale Semiconductor

Preliminary

Functional Description

5.3.2 Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level.

Table 5-1 Interrupt Mask Bit Definition

SR[9]

0 0 Priorities 0, 1, 2, 3 None

0 1 Priorities 1, 2, 3 Priority 0

1 0 Priorities 2, 3 Priorities 0, 1

1 1 Priority 3 Priorities 0, 1, 2

1. Core status register bits indicating current interrupt mask within the core.

Table 5-2. Interrupt Priority Encoding

IPIC_LEVEL[1:0]

SR[8]

Permitted Exceptions Masked Exceptions

Current Interrupt

Priority Level

Required Nested

Exception Priority

00 No Interrupt or SWILP Priorities 0, 1, 2, 3

01 Priority 0 Priorities 1, 2, 3

10 Priority 1 Priorities 2, 3

11 Priorities 2 or 3 Priority 3

1. See IPIC field definition in Section 5.6.30.2

5.3.3 Fast Interrupt Handling

Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does.

A fast interrupt is defined (to the ITCN) by:

1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers

2. Setting the FIMn register to the appropriate vector number

3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt

When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA.

The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts its fast interrupt handling.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 53 Preliminary

5.4 Block Diagram

INT1

Priority

Level

2 -> 4

Decode

Priority

Level

Level 0

82 -> 7

Priority

Encoder

Level 3

82 -> 7

Priority

Encoder

any0

any3

CONTROL

IACK

SR[9:8]

INT

VAB

IPIC

PIC_EN

INT82

2 -> 4

Decode

Figure 5-1 Interrupt Controller Block Diagram

5.5 Operating Modes

The ITCN module design contains two major modes of operation:

• Functional Mode The ITCN is in this mode by default.

• Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA signal automatically becomes low-level sensitive in these modes, even if the control register bits are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling edge.

A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB

can wake it up.

56F8322 Techncial Data, Rev. 10.0

54 Freescale Semiconductor

Preliminary

5.6 Register Descriptions

A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.

Table 5-3 ITCN Register Summary

(ITCN_BASE = $00 F1A0)

Acronym

IPR0 $0 Interrupt Priority Register 0

IPR1 $1 Interrupt Priority Register 1

IPR2 $2 Interrupt Priority Register 2

IPR3 $3 Interrupt Priority Register 3

IPR4 $4 Interrupt Priority Register 4

IPR5 $5 Interrupt Priority Register 5

IPR6 $6 Interrupt Priority Register 6

IPR7 $7 Interrupt Priority Register 7

IPR8 $8 Interrupt Priority Register 8

IPR9 $9 Interrupt Priority Register 9

VBA $A Vector Base Address Register

FIM0 $B Fast Interrupt 0 Match Register

FIVAL0 $C Fast Interrupt 0 Vector Address Low Register

FIVAH0 $D Fast Interrupt 0 Vector Address High Register

FIM1 $E Fast Interrupt 1 Match Register

FIVAL1 $F Fast Interrupt 1 Vector Address Low Register

FIVAH1 $10 Fast Interrupt 1 Vector Address High Register

IRQP0 $11 IRQ Pending Register 0

IRQP1 $12 IRQ Pending Register 1

IRQP2 $13 IRQ Pending Register 2

IRQP3 $14 IRQ Pending Register 3

IRQP4 $15 IRQ Pending Register 4

IRQP5 $16 IRQ Pending Register 5

ICTL $1D Interrupt Control Register

Base Address + Register Name Section Location

Reserved

5.6.1

5.6.2

5.6.3

5.6.4

5.6.5

5.6.6

5.6.7

5.6.8

5.6.9

5.6.10

5.6.11

5.6.12

5.6.13

5.6.14

5.6.15

5.6.16

5.6.17

5.6.18

5.6.19

5.6.20

5.6.21

5.6.22

5.6.23

5.6.30

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 55 Preliminary

Add.

Offset

Name

$0 IPR0

$1 IPR1

$2 IPR2

$3 IPR3

$4 IPR4

$5 IPR5

$6 IPR6

$7 IPR7

$8 IPR8

$9 IPR9

$A VBA

$B FIM0

$C FIVAL0

$D FIVAH0

$E FIM1

$F FIVAL1

$10 FIVAH1

$11 IRQP0

$12 IRQP1

$13 IRQP2

$14 IRQP3

$15 IRQP4

$16 IRQP5

Reserved

$1D ICTL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0

0 0 0 0 0 0 0 0 0 0

BKPT_ U0

IPL

STPCNT IPL

FMCBE IPL FMCC IPL FMERR IPL LOCK IPL LVI IPL

0 0 0 0 0 0

SPI0_RCV

IPL

0 0 0 0

TMRC0 IPL

W 0 0

TMRA0 IPL

SCI0_RCV

PWMA F IPL

IPL

0 0 0

SPI1_XMIT

IPL

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

SCI0_RERR

IPL

0 0

SPI1_RCV

IPL

SCI1_RCV

IPL

0 0

PWMA_RL

IPL

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

RX_REG IPL TX_REG IPL TRBUF IPL

0 0 0 0

FCMSGBUF

IPL

0 0 0 0

SCI1_RERR

IPL

SCI0_TIDL

IPL

0 0

FAST INTERRUPT 0

VECTOR ADDRESS LOW

FAST INTERRUPT 1

VECTOR ADDRESS LOW

PENDING [16:2] 1

FCWKUP

IPL

0 0

SCI0_XMIT

IPL

ADCA_ZC

IPL

VECTOR BASE ADDRESS

FCERR IPL FCBOFF IPL

GPIOA IPL GPIOB IPL GPIOC IPL

SCI1_TIDL

IPL

TMRC3 IPL TMRC2 IPL TMRC1 IPL

TMRA3 IPL TMRA2 IPL TMRA1 IPL

0 0

SCI1_XMIT

IPL

DEC0_XIRQ

IPL

ADCA_CC IPL

FAST INTERRUPT 0

VECTOR ADDRESS HIGH

FAST INTERRUPT 1

VECTOR ADDRESS HIGH

PENDING [32:17]

PENDING [48:33]

PENDING [64:49]

PENDING [80:65]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

INT IPIC VAB

INT_

DIS

1 0

IRQA

STATE

0 0

SPI0_XMIT

DEC0_HIRQ

0 0

IRQA IPL

IPL

PEND-

ING [81]

IRQA

EDG

= Reserved

Figure 5-2 ITCN Register Map Summary

56F8322 Techncial Data, Rev. 10.0

56 Freescale Semiconductor

Preliminary

5.6.1 Interrupt Priority Register 0 (IPR0)

Base + $0

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0

0 0 0 0 0 0 00 00000000

BKPT_U0IPL STPCNT IPL

0 0 0 0 0 0 0 0 0 0

Figure 5-3 Interrupt Priority Register 0 (IPR0)

5.6.1.1 Reserved—Bits 15–14

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)— Bits13–12

This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 1

• 10 = IRQ is priority level 2

• 11 = IRQ is priority level 3

5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 1

• 10 = IRQ is priority level 2

• 11 = IRQ is priority level 3

5.6.1.4 Reserved—Bits 9–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2 Interrupt Priority Register 1 (IPR1)

Base + $1

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0

0000000000000000

RX_REG IPL TX_REG IPL TRBUF IPL

Figure 5-4 Interrupt Priority Register 1 (IPR1)

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 57 Preliminary

5.6.2.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 1

• 10 = IRQ is priority level 2

• 11 = IRQ is priority level 3

5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 1

• 10 = IRQ is priority level 2

• 11 = IRQ is priority level 3

5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 1

• 10 = IRQ is priority level 2

• 11 = IRQ is priority level 3

5.6.3 Interrupt Priority Register 2 (IPR2)

Base + $2

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FMCBE IPL FMCC IPL FMERR IPL LOCK IPL LVI IPL

0000000000000000

0 0 0 0

IRQA IPL

Figure 5-5 Interrupt Priority Register 2 (IPR2)

56F8322 Techncial Data, Rev. 10.0

58 Freescale Semiconductor

Preliminary

5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)—Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 59 Preliminary

5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.3.6 Reserved—Bits 5–2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.3.7 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.4 Interrupt Priority Register 3 (IPR3)

Base + $3

Read

Write

RESET

5.6.4.1 Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.4.2 FlexCAN Message Buffer Interrupt Priority Level

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0

000000 0 0 0 0 0 0 0 0 0 0

FCMSGBUF IPL FCWKUP IPL FCERR IPL FCBOFF IPL

Figure 5-6 Interrupt Priority Register 3 (IPR3)

(FCMSGBUF IPL)—Bits 9–8

0 0

56F8322 Techncial Data, Rev. 10.0

60 Freescale Semiconductor

Preliminary

5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.4.5 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.4.6 Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.5 Interrupt Priority Register 4 (IPR4)

Base + $4

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI0_RCV

IPL

0000000000000000

SPI1_XMIT

IPL

SPI1_RCV

IPL

0 0 0 0

GPIOA IPL GPIOB IPL GPIOC IPL

Figure 5-7 Interrupt Priority Register 4 (IPR4)

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 61 Preliminary

5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.5.4 Reserved—Bits 9–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.5.5 GPIO_A Interrupt Priority Level (GPIOA IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Techncial Data, Rev. 10.0

62 Freescale Semiconductor

Preliminary

5.6.5.6 GPIO_B Interrupt Priority Level (GPIOB IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.5.7 GPIO_C Interrupt Priority Level (GPIOC IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6 Interrupt Priority Register 5 (IPR5)

Base + $5

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0

0000000 0 00000000

SCI1_RCV

IPL

SCI1_RERR

IPL

0 0

SCI1_TIDL

IPL

SCI1_XMIT

IPL

SPI0_XMIT

IPL

Figure 5-8 Interrupt Priority Register 5 (IPR5)

5.6.6.1 Reserved—Bits 15–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.6.2 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 63 Preliminary

5.6.6.3 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6.4 Reserved—Bits 7–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.6.5 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6.6 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6.7 SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)— Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Techncial Data, Rev. 10.0

64 Freescale Semiconductor

Preliminary

5.6.7 Interrupt Priority Register 6 (IPR6)

Base + $6

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TMRC0 IPL

0000000000000000

0 0 0 0 0 0 0 0 0 0

DEC0_XIRQ

IPL

DEC0_HIRQ

IPL

Figure 5-9 Interrupt Priority Register 6 (IPR6)

5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC_0 IPL)— Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.7.2 Reserved—Bits 13–4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.7.3 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.7.4 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 65 Preliminary

5.6.8 Interrupt Priority Register 7 (IPR7)

Base + $7

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TMRA0 IPL

0000000000000000

0 0 0 0 0 0 0 0

TMRC3 IPL TMRC2 IPL TMRC1 IPL

Figure 5-10 Interrupt Priority Register (IPR7)

5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.8.2 Reserved—Bits 13–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.8.3 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.8.4 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Techncial Data, Rev. 10.0

66 Freescale Semiconductor

Preliminary

5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.9 Interrupt Priority Register 8 (IPR8)

Base + $8

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCI0_RCV

IPL

0000000000000000

SCI0_RERR

IPL

0 0

SCI0_TIDL

IPL

SCI0_XMIT

IPL

TMRA3 IPL TMRA2 IPL TMRA1 IPL

Figure 5-11 Interrupt Priority Register 8 (IPR8)

5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.9.3 Reserved—Bits 11–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 67 Preliminary

5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

56F8322 Techncial Data, Rev. 10.0

68 Freescale Semiconductor

Preliminary

5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.10 Interrupt Priority Register 9 (IPR9)

Base + $9

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWMAF IPL

0000000000000000

0 0

PWMA_RL

IPL

0 0

ADCA_ZC IPL

0 0

ADCA_CC

IPL

0 0

Figure 5-12 Interrupt Priority Register 9 (IPR9)

5.6.10.1 PWM A Fault Interrupt Priority Level (PWMAF IPL)—Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.10.2 Reserved—Bits 13–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)— Bits 11–10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.10.4 Reserved—Bits 9–8

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 69 Preliminary

5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.10.6 Reserved—Bits 5–4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.10.8 Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.11 Vector Base Address Register (VBA)

Base + $A

Read

Write

RESET

5.6.11.1 Reserved—Bits 15–13

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—

The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are determined based upon the highest-priority interrupt; see Section 5.3.1 for details.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0

0000000000000000

VECTOR BASE ADDRESS

Figure 5-13 Vector Base Address Register (VBA)

Bits 12–0

56F8322 Techncial Data, Rev. 10.0

70 Freescale Semiconductor

Preliminary

5.6.12 Fast Interrupt 0 Match Register (FIM0)

Base + $B

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0

0000000000000000

FAST INTERRUPT 0

Figure 5-14 Fast Interrupt 0 Match Register (FIM0)

5.6.12.1 Reserved—Bits 15–7

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0

This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3.

5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Base + $C

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FAST INTERRUPT 0 VECTOR ADDRESS LOW

0000000000000000

Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)

Base + $D

Read

Write

RESET

5.6.14.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0

0000000000000000

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 71 Preliminary

5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.15 Fast Interrupt 1 Match Register (FIM1)

Base + $E

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0

0000000000000000

FAST INTERRUPT 1

Figure 5-17 Fast Interrupt 1 Match Register (FIM1)

5.6.15.1 Reserved—Bits 15–7

This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.

5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0

This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3.

5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Base + $F

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FAST INTERRUPT 1 VECTOR

ADDRESS LOW

0000000000000000

Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)

Base + $10

Read

Write

RESET

72 Freescale Semiconductor

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0

0000000000000000

FAST INTERRUPT 1

VECTOR ADDRESS HIGH

Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)

56F8322 Techncial Data, Rev. 10.0

Preliminary

5.6.17.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.18 IRQ Pending 0 Register (IRQP0)

Base + $11

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PENDING [16:2] 1

1111111111111111

Figure 5-20 IRQ Pending 0 Register (IRQP0)

5.6.18.1 IRQ Pending (PENDING)—Bits 16–2

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.

• 0 = IRQ pending for this vector number

• 1 = No IRQ pending for this vector number

5.6.18.2 Reserved—Bit 0

This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.19 IRQ Pending 1 Register (IRQP1)

$Base + $12

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PENDING [32:17]

1111111111111111

Figure 5-21 IRQ Pending 1 Register (IRQP1)

5.6.19.1 IRQ Pending (PENDING)—Bits 32–17

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.

• 0 = IRQ pending for this vector number

• 1 = No IRQ pending for this vector number

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 73 Preliminary

5.6.20 IRQ Pending 2 Register (IRQP2)

Base + $13

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PENDING [48:33]

1111111111111111

Figure 5-22 IRQ Pending 2 Register (IRQP2)

5.6.20.1 IRQ Pending (PENDING)—Bits 48–33

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.

• 0 = IRQ pending for this vector number

• 1 = No IRQ pending for this vector number

5.6.21 IRQ Pending 3 Register (IRQP3)

Base + $14

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PENDING [64:49]

1111111111111111

Figure 5-23 IRQ Pending 3 Register (IRQP3)

5.6.21.1 IRQ Pending (PENDING)—Bits 64–49

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.

• 0 = IRQ pending for this vector number

• 1 = No IRQ pending for this vector number

5.6.22 IRQ Pending 4 Register (IRQP4)

Base + $15

Read

Write

RESET

5.6.22.1 IRQ Pending (PENDING)—Bits 80–65

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.

• 0 = IRQ pending for this vector number

• 1 = No IRQ pending for this vector number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PENDING [80:65]

1111111111111111

Figure 5-24 IRQ Pending 4 Register (IRQP4)

56F8322 Techncial Data, Rev. 10.0

74 Freescale Semiconductor

Preliminary

5.6.23 IRQ Pending 5 Register (IRQP5)

Base + $16

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

111111111111111 1

PEND-

ING [81]

Figure 5-25 IRQ Pending Register 5 (IRQP5)

5.6.23.1 Reserved—Bits 96–82

This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.

5.6.23.2 IRQ Pending (PENDING)—Bit 81

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81.

• 0 = IRQ pending for this vector number

• 1 = No IRQ pending for this vector number

5.6.24 Reserved—Base + 17

5.6.25 Reserved—Base + 18

5.6.26 Reserved—Base + 19

5.6.27 Reserved—Base + 1A

5.6.28 Reserved—Base + 1B

5.6.29 Reserved—Base + 1C

5.6.30 ITCN Control Register (ICTL)

Base + $1D

Read

Write

RESET

5.6.30.1 Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

• 0 = No interrupt is being sent to the 56800E core

• 1 = An interrupt is being sent to the 56800E core

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT IPIC VAB

0 0 0 1000000 0 1 1 1 0 0

INT_DIS

1 0 IRQA STATE 0

Figure 5-26 ITCN Control Register (ICTL)

IRQA

EDG

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 75 Preliminary

5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine.

Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

• 00 = Required nested exception priority levels are 0, 1, 2, or 3

• 01 = Required nested exception priority levels are 1, 2, or 3

• 10 = Required nested exception priority levels are 2 or 3

• 11 = Required nested exception priority level is 3

5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6

This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine.

Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

• 0 = Normal operation (default)

• 1 = All interrupts disabled

5.6.30.5 Reserved—Bit 4

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.30.6 Reserved—Bit 3

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2

This read-only bit reflects the state of the external IRQA pin.

5.6.30.8 Reserved—Bit 1

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0

This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive.

•0 = IRQA interrupt is a low-level sensitive (default)

•1 = IRQA

interrupt is falling-edge sensitive

56F8322 Techncial Data, Rev. 10.0

76 Freescale Semiconductor

Preliminary

Resets

5.7 Resets

5.7.1 Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released.

5.7.2 ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities:

• Illegal Instruction

• SW Interrupt 3

• HW Stack Overflow

• Misaligned Long Word Access

• SW Interrupt 2

• SW Interrupt 1

• SW Interrupt 0

• SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

Part 6 System Integration Module (SIM)

6.1 Introduction

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system integration module is responsible for the following functions:

• Reset sequencing

• Clock control & distribution

• Stop/Wait control

• Pull-up enables for selected peripherals

• System status registers

• Registers for software access to the JTAG ID of the chip

• Enforcing Flash security

These are discussed in more detail in the sections that follow.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 77 Preliminary

6.2 Features

The SIM has the following features:

• Flash security feature prevents unauthorized access to code/data contained in on-chip flash memory

• Power-saving clock gating for peripherals

• Three power modes (Run, Wait, Stop) to control power utilization

— Stop mode shuts down the 56800E core, system clock, and peripheral clock

— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart)

— Wait mode shuts down the 56800E core and unnecessary system clock operation

— Run mode supports full part operation

• Controls to enable/disable the 56800E core WAIT and STOP instructions

• Controls reset sequencing after reset

• Software-initiated reset

• Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control

• System Control Register

• Registers for software access to the JTAG ID of the chip

6.3 Operating Modes

Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are:

• Reset Mode, which has two submodes:

— Total Reset Mode

– 56800E Core and all peripherals are reset

— Core-Only Reset Mode

– 56800E Core in reset, peripherals are active – This mode is required to provide the on-chip Flash interface module time to load data from Flash

into FM registers

• Run Mode This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation.

• Debug Mode The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.

• Wait Mode In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped. Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other peripherals continue to run.

• Stop Mode 56800E, memory and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.

56F8322 Techncial Data, Rev. 10.0

78 Freescale Semiconductor

Preliminary

6.4 Operating Mode Register

Operating Mode Register

Bit

Typ e

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NL CM XP SD R SA EX 0 MB MA

R/W R/W R/W R/W R/W R/W R/W R/W R/W

0000 0 00000000 0X0

Figure 6-1 OMR

The reset state for the MB bit will depend on the Flash secured state. See Section 4.2 and Part 7 for detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX bit is not functional in this device since there is no external memory interface. For all other bits, see the 56F8300 Peripheral User Manual.

Note: The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.

6.5 Register Descriptions

Table 6-1 SIM Registers

(SIM_BASE = $00 F350)

Address Offset Address Acronym Register Name Section Location

Base + $0 SIM_CONTROL Control Register

Base + $1 SIM_RSTSTS Reset Status Register

Base + $2 SIM_SCR0 Software Control Register 0

Base + $3 SIM_SCR1 Software Control Register 1

Base + $4 SIM_SCR2 Software Control Register 2

Base + $5 SIM_SCR3 Software Control Register 3

Base + $6 SIM_MSH_ID Most Significant Half of JTAG ID

Base + $7 SIM_LSH_ID Least Significant Half of JTAG ID

Base + $8 SIM_PUDR Pull-up Disable Register

Reserved

Base + $A SIM_CLKOSR CLKO Select Register

Base + $B SIM_GPS GPIO Peripheral Select Register

Base + $C SIM_PCE Peripheral Clock Enable Register

Base + $D SIM_ISALH I/O Short Address Location High Register

Base + $E SIM_ISALL I/O Short Address Location Low Register

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

6.5.8

6.5.9

6.5.10

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 79 Preliminary

Add.

Offset

Name

$2 SIM_SCR0

$3 SIM_SCR1

$4 SIM_SCR2

$5 SIM_SCR3

$6 SIM_MSH_ID

$8 SIM_PUDR

$B SIM_GPS

$C SIM_PCE

$D SIM_ISALH

$E SIM_ISALL

SIM_

CONTROL

SIM_

RSTSTS

SIM_LSH_ID

Reserved

SIM_

CLKOSR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1

0 0 0 0

0 0 0 0 0 0

0 0 0 0 0 0 0 0

1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

ADCA CAN

RESET

IRQ

PHSA

DEC0

FIELD

0 0 0 0 0 0

PHSB INDEX HOME

C6 C5 B1 B0 A5 A4 A3 A2

TMRC

ISAL[21:6]

ONCE

EBL0

RST

SWR COPR EXTR POR

CLK DIS

TMRA SCI1 SCI0 SPI1 SPI0

STOP_

DISABLE

JTAG

0 0 0

CLKOSEL

WAIT_

DISABLE

0 0

PWMA

ISAL[23:22]

= Reserved

Figure 6-2 SIM Register Map Summary

6.5.1 SIM Control Register (SIM_CONTROL)

Base + $0

Read

Write

RESET

6.5.1.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0

0000000000000000

ONCE

EBL0

RST

STOP_

DISABLE

Figure 6-3 SIM Control Register (SIM_CONTROL)

WAIT_

56F8322 Techncial Data, Rev. 10.0

80 Freescale Semiconductor

Preliminary

6.5.1.2 OnCE Enable (ONCE EBL)—Bit 5

• 0 = OnCE clock to 56800E core enabled when core TAP is enabled

• 1 = OnCE clock to 56800E core is always enabled

6.5.1.3 Software Reset (SW RST)—Bit 4

Writing 1 to this field will cause the part to reset.

6.5.1.4 Stop Disable (STOP_DISABLE)—Bits 3–2

• 00 = Stop mode will be entered when the 56800E core executes a STOP instruction

• 01 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be reprogrammed in the future

• 10 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be changed by resetting the device

• 11 = Same operation as 10

6.5.1.5 Wait Disable (WAIT_DISABLE)—Bits 1–0

• 00 = Wait mode will be entered when the 56800E core executes a WAIT instruction

• 01 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be reprogrammed in the future

• 10 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only be changed by resetting the device

• 11 = Same operation as 10

6.5.2 SIM Reset Status Register (SIM_RSTSTS)

Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register.

Base + $1

Read

Write

RESET

6.5.2.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.

6.5.2.2 Software Reset (SWR)—Bit 5

When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0

0000000000 00

SWR COPR EXTR POR

0 0

Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 81 Preliminary

6.5.2.3 COP Reset (COPR)—Bit 4

When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.

6.5.2.4 External Reset (EXTR)—Bit 3

If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low.

6.5.2.5 Power-On Reset (POR)—Bit 2

When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On Reset.

6.5.2.6 Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)

Only SIM_SCR0 is shown in this section. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.

Base + $2

Read

Write

POR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD

0000000000000000

Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)

6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0

This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset).

56F8322 Techncial Data, Rev. 10.0

82 Freescale Semiconductor

Preliminary

6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)

This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4.

Base + $6

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0

0000000111110100

Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)

6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $001D.

Base + $7

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1

0000000000011101

Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)

6.5.6 SIM Pull-up Disable Register (SIM_PUDR)

Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See

Table 2-2 to identify which pins can deactivate the internal pull-up resistor.

Base + $8

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0

00000000 0 0000000

RESET

0 0 0 0 0 0

IRQ

JTAG

0 0 0

Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)

6.5.6.1 Reserved—Bits 15–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.6.2 RESET—Bit 11

This bit controls the pull-up resistors on the RESET pin.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 83 Preliminary

6.5.6.3 IRQ—Bit 10

This bit controls the pull-up resistors on the IRQA pin.

6.5.6.4 Reserved—Bits 9–4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.6.5 JTAG—Bit 3

This bit controls the pull-up resistors on the TRST (This pin is always tied inactive on the 56F8322), TMS and TDI pins.

6.5.6.6 Reserved—Bits 2–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.7 CLKO Select Register (SIM_CLKOSR)

The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies.

The upper four bits of the GPIOB register can function as GPIO, Quad Decoder #0 signals, or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice between Quad Decoder #0 and additional clock outputs is made here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as Quad Decoder #0. This can be changed by altering PHASE0 through INDEX as shown in Figure 6-9.

The CLKOUT pin is not bonded out in this device. Instead, it is offered only as a pad for die-level testing.

Base + $A

Read

Write

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0

000000000 0100000

PHSA

PHSB INDEX HOME

CLK

DIS

CLKOSEL

Figure 6-9 CLKO Select Register (SIM_CLKOSR)

6.5.7.1 Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.7.2 PHASEA0 (PHSA)—Bit 9

• 0 = Peripheral output function of GPIOB[7] is defined to be PHASEA0

• 1 = Peripheral output function of GPI B[7] is defined to be the oscillator clock (MSTR_OSC, see

Figure 3-4)

6.5.7.3 PHASEB0 (PHSB)—Bit 8

• 0 = Peripheral output function of GPIOB[6] is defined to be PHASEB0

• 1 = Peripheral output function of GPIOB[6] is defined to be SYS_CLK2

56F8322 Techncial Data, Rev. 10.0

84 Freescale Semiconductor

Preliminary

6.5.7.4 INDEX0 (INDEX)—Bit 7

• 0 = Peripheral output function of GPIOB[5] is defined to be INDEX0

• 1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK

6.5.7.5 HOME0 (HOME)—Bit 6

• 0 = Peripheral output function of GPIOB[4] is defined to be HOME0

• 1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see Figure 3-4)

6.5.7.6 Clockout Disable (CLKDIS)—Bit 5

• 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL

• 1 = CLKOUT is tri-stated

6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0

Selects clock to be muxed out on the CLKO pin.

• 00000 = SYS_CLK (from ROCS - DEFAULT)

• 00001 = Reserved for factory test—56800E clock

• 00010 = Reserved for factory test—XRAM clock

• 00011 = Reserved for factory test—PFLASH odd clock

• 00100 = Reserved for factory test—PFLASH even clock

• 00101 = Reserved for factory test—BFLASH clock

• 00110 = Reserved for factory test—DFLASH clock

• 00111 = MSTR_OSC Oscillator output

• 01000 = F

• 01001 = Reserved for factory test—IPB clock

• 01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)

• 01011 = Reserved for factory test—Prescaler clock (from OCCS)

• 01100 = Reserved for factory test—Postscaler clock (from OCCS)

• 01101 = Reserved for factory test—SYS_CLK2 (from OCCS)

• 01110 = Reserved for factory test—SYS_CLK_DIV2

• 01111 = Reserved for factory test—SYS_CLK_D

• 10000 = ADCA clock

(from OCCS)

out

6.5.8 SIM GPIO Peripheral Select Register (SIM_GPS)

All of the peripheral pins on the 56F8322 and 56F8122 share their I/O with GPIO ports. To select peripheral or GPIO control, program the GPIOx_PER register. When SPI 0 and SCI 1, Quad Timer C and SCI 0, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral has control. The default peripherals are SPI 0, Quad Timer C, and PWMA.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 85 Preliminary

Note: PWM is NOT available in the 56F8122 device.

As shown in Figure 6-10, the GPIO has the final control over which pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O.

GPIOX_PER Register

SIM_GPS Register

Quad Timer Controlled

SCI Controlled

GPIO Controlled

I/O

Pad Control

Figure 6-10 Overall Control of Pads Using SIM_GPS Control

Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

Write

RESET

0 0 0 0 0 0 0 0

0000000000 0 0 0 0 0 0

C6 C5 B1 B0 A5 A4 A3 A2

Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)

6.5.8.1 Reserved—Bits 15–8

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.8.2 GPIO C6 (C6)—Bit 7

This bit selects the alternate function for GPIOC6.

• 0 = TC0 (default)

• 1 = TXD0

6.5.8.3 GPIOC5 (C5)—Bit 6

This bit selects the alternate function for GPIOC5.

• 0 = TC1 (default)

• 1 = RXD0

56F8322 Techncial Data, Rev. 10.0

86 Freescale Semiconductor

Preliminary

6.5.8.4 GPIOB1 (B1)—Bit 5

This bit selects the alternate function for GPIOB1.

• 0 = MISO0 (default)

• 1 = RXD1

6.5.8.5 GPIOB0 (B0)—Bit 4

This bit selects the alternate function for GPIOB0.

• 0 = SS0 (default)

• 1 = TXD1

6.5.8.6 GPIOA5 (A5)—Bit 3

This bit selects the alternate function for GPIOA5.

•0 = PWMA5

• 1 = SCLK1

6.5.8.7 GPIOA4 (A4)—Bit 2

This bit selects the alternate function for GPIOA4.

•0 = PWMA4

•1 = MOS1

6.5.8.8 GPIOA3 (A3)—Bit 1

This bit selects the alternate function for GPIOA3.

•0 = PWMA3

•1 = MISO1

6.5.8.9 GPIOA2 (A2)—Bit 0

This bit selects the alternate function for GPIOA2.

•0 = PWMA2

• 1 = SS1

6.5.9 Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip.

Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

Write

RESET

1 1

1111111 1 11111 11 1

ADCA CAN

DEC0

TMRC

TMRA SCI 1 SCI 0 SPI1 SPI0

PWMA

Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 87 Preliminary

6.5.9.1 Reserved—Bits 15–14

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.2 Analog-to-Digital Converter A Enable (ADCA)—Bit 13

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.3 FlexCAN Enable (CAN)—Bit 12

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.4 Reserved—Bit 11

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.5 Decoder 0 Enable (DEC0)—Bit 10

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.6 Reserved—Bit 9

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.7 Quad Timer C Enable (TMRC)—Bit 8

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.8 Reserved—Bit 7

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.9 Quad Timer A Enable (TMRA)—Bit 6

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

56F8322 Techncial Data, Rev. 10.0

88 Freescale Semiconductor

Preliminary

6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—Bit 5

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.11 Serial Communications Interface 0 Enable (SCI0)—Bit 4

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.12 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.13 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.14 Reserved—Bit 1

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

6.5.9.15 Pulse Width Modulator A Enable (PWMA)—Bit 0

Each bit controls clocks to the indicated peripheral.

• 1 = Clocks are enabled

• 0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)

The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-13.

Note: If this register is set to something other than the top of memory (EOnCE register space) and the EX bit

in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 89 Preliminary

“Hard Coded” Address Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_ISALL Register

2 bits from SIM_ISALH Register

Full 24-Bit for Short I/O Address

Instruction Portion

Figure 6-13 I/O Short Address Determination

With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt.

Note: The default value of this register set points to the EOnCE registers.

Note: The pipeline delay between setting this register set and using short I/O addressing with the new value

is five cycles.

Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

Write

RESET

1 1 1 1 1 1 1 1 1 1 1 1 1 1

111111 1 11111 1 1 11

Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)

6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

Write

RESET

111111 1 11111 1 1 11

Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)

ISAL[21:6]

ISAL[23:22]

56F8322 Techncial Data, Rev. 10.0

90 Freescale Semiconductor

Preliminary

Clock Generation Overview

6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.6 Clock Generation Overview

The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible means to manage power consumption.

Power utilization can be minimized in several ways. In the OCCS, the relaxation oscillator, crystal oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused subfunctions. Refer to Part 3 On-Chip Clock

Synthesis (OCCS), and the 56F8300 Peripheral User Manual for further details.

The memory, peripheral and core clocks all operate at the same frequency (60MHz max).

6.7 Power-Down Modes

The 56F8322/56F8122 operate in one of three power-down modes, as shown in Table 6-2.

Table 6-2 Clock Operation in Power-Down Modes

Mode Core Clocks Peripheral Clocks Description

Run Active Active Device is fully functional

Wait Core and memory

clocks disabled

Stop System clocks continue to be generated in

the SIM, but most are gated prior to reaching memory, core and peripherals.

All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz.

Active Peripherals are active and can produce

interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications.

The only possible recoveries from Stop mode are:

1. CAN traffic (1st message will be lost)

2. Non-clocked interrupts (IRQA

3. COP reset

4. External reset

5. Power-on reset

)

Refer to the PCE register in Section 6.5.9 and ADC power modes. Power is a function of the system frequency, which can be controlled through the OCCS.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 91 Preliminary

6.8 Stop and Wait Mode Disable Function

Permanent Disable

D-FLOP

Reprogrammable Disable

Clock Select

Reset

D-FLOP

Note: Wait disable circuit is similar

56800E

STOP_DIS

Figure 6-16 Internal Stop Disable Circuit

The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E system clock must be set equal to the prescaler output.

Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL) described in Section 6.5.1 . This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset.

6.9 Resets

The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within the SIM itself, by writing to the SIM_CONTROL register, and the COP reset.

Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced to permit proper operation of the device. A POR reset is declared when reset is removed and any of the three voltage detectors (1.8V POR, 2.2V core voltage, or 2.7V I/O voltage) indicate a low supply voltage condition. POR will continue to be asserted until all voltage detectors indicate a stable supply is available (note that as power is removed POR is not declared until the 1.8V core voltage threshold is reached.) A POR reset is then extended for 64 clock cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to implement Flash security, and, finally, followed by a 32 clock window in which the core is initialized. After completion of the described reset sequence, application code will begin execution.

Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock.

56F8322 Techncial Data, Rev. 10.0

92 Freescale Semiconductor

Preliminary

Operation with Security Enabled

Part 7 Security Features

The 56F8322/56F8122 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array.

However, part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of the internal program, as this code would defeat the purpose of security. At the same time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a security key through the SCI, allowing access to a programming routine that updates parameters stored in another section of the Flash.

7.1 Operation with Security Enabled

Once the user has programmed the Flash with his application code, the device can be secured by programming the security bytes located in the FM configuration field, which occupies a portion of the FM array. These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory chapter in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the device will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected.

7.2 Flash Access Blocking Mechanisms

The 56F8322/56F8122 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods to block these are outlined in the next subsections.

7.2.1 Forced Operating Mode Selection

At boot time, the SIM determines in which functional modes the device will operate. These are:

• Unsecured Mode

• Secure Mode (EOnCE disabled)

When Flash security is enabled as described in the Flash Memory module specification, the device will disable the EOnCE debug interface.

7.2.2 Disabling EOnCE Access

On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 93 Preliminary

Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security bytes.

7.2.3 Flash Lockout Recovery

If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration (.cfg) files. Add, or uncomment the following configuration command:

unlock_flash_on_connect 1

For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual.

The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the 56F8300 Peripheral User Manual for more details on setting this register value.

The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values.

JTAG

SYS_CLK

FMCLKDIV

FMERASE

input

clock

FMCLKD

Figure 7-1 JTAG to FM Connection for Lockout Recovery

Two examples of FM_CLKDIV calculations follow.

56F8322 Techncial Data, Rev. 10.0

Flash Memory

DIVIDER

94 Freescale Semiconductor

Preliminary

Flash Access Blocking Mechanisms

EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.

SYS_CLK

150[kHz]

EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8=FM_CLKDIV[6]=1.Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.

150[kHz]

(2)

(DIV + 1)

SYS_CLK

(2)(8)

(DIV + 1)

)(

200[kHz]

)(

200[kHz]

Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual.

Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller

(by asserting TRST operation.

) and the device (by asserting external chip reset) to return to normal unsecured

7.2.4 Product Analysis

The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set.

An alternative method for performing analysis on a secured microcontroller would be to mass-erase and reprogram the Flash with the original code, but modify the security bytes.

To insure that a customer does not inadvertently lock himself out of the device during programming, it is recommended that he program the backdoor access key first, his application code second and the security bytes within the FM configuration field last.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 95 Preliminary

Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction

This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User Manual.

8.2 Configuration

There are three GPIO ports defined on the 56F8322/56F8122. The width of each port and the associated peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is shown in Table 8-3.

Table 8-1 56F8322 GPIO Ports Configuration

GPIO Port

A12 7

B8 8

C7 6

Port

Width

Available

Pins in

56F8322

Table 8-2 56F8122 GPIO Ports Configuration

GPIO Port

A12 7

B8 8

C7 6

Port

Width

Available

Pins in

56F8122

Peripheral Function Reset Function

PWM, SPI 1 PWM

SPI 0, DEC 0, TMRA, SCI 1 SPI 0, DEC 0

XTAL, EXTAL, CAN, TMRC, SCI 0 XTAL, EXTAL, CAN, TMRC

Peripheral Function Reset Function

SPI 1 Must be reconfigured

SPI 0, SCI1, TMRA SPI 0, other pins must be reconfigured

XTAL, EXTAL, TMRC, SCI 0 XTAL, EXTAL, TMRC; other pins must be

reconfigured

56F8322 Techncial Data, Rev. 10.0

96 Freescale Semiconductor

Preliminary

Table 8-3 GPIO External Signals Map

Pins in shaded rows are not available in 56F8322 / 56F8122

Pins in italics are NOT available in the 56F8122 device

Configuration

GPIO Function Peripheral Function

GPIOA0 PWMA0 3 PWM is NOT available in 56F8122

GPIOA1 PWMA1 4 PWM is NOT available in 56F8122

GPIOA2 PWMA2 / SSI

GPIOA3 PWMA3 / MISO1 7 SIM register SIM_GPS is used to select between SPI1 and

GPIOA4 PWMA4 / MOSI1 8 SIM register SIM_GPS is used to select between SPI1 and

GPIOA5 PWMA5 / SCLK1 9 SIM register SIM_GPS is used to select between SPI1 and

GPIOA6 FAULTA0 12

GPIOA7 FAULTA1

GPIOA8 FAULTA2

GPIOA9 ISA0

Package Pin Notes

6 SIM register SIM_GPS is used to select between SPI1 and

PWMA on a pin-by-pin basis

PWM is NOT available in 56F8122

PWMA on a pin-by-pin basis

PWM is NOT available in 56F8122

PWMA on a pin-by-pin basis

PWM is NOT available in 56F8122

PWMA on a pin-by-pin basis

PWM is NOT available in 56F8122

GPIOA10 ISA1

GPIOA11 ISA2

GPIOB0 SS0 / TXD1 15 SIM register SIM_GPS is used to select between SPI1 and

PWMA on a pin-by-pin basis

GPIOB1 MISO0 / RXD1 16 SIM register SIM_GPS is used to select between SPI1 and

PWMA on a pin-by-pin basis

GPIOB2 MOSI0 18

GPIOB3 SCLK0 19

GPIOB4 HOME0 / TA3 35 Quad Decoder 0 register DECCR is used to select

between Decoder 0 and Timer A

Quad Dec is NOT available in 56F8122

GPIOB5 INDEX0 / TA2 36 Quad Decoder 0 register DECCR is used to select

between Decoder 0 and Timer A

Quad Dec is NOT available in 56F8122

GPIOB6 PHASEB0 / TA1 37 Quad Decoder 0 register DECCR is used to select

between Decoder 0 and Timer A

Quad Dec is NOT available in 56F8122

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 97 Preliminary

Table 8-3 GPIO External Signals Map (Continued)

Pins in shaded rows are not available in 56F8322 / 56F8122

Pins in italics are NOT available in the 56F8122 device

GPIO Function Peripheral Function

GPIOB7 PHASEA0 / TA0 38 Quad Decoder 0 register DECCR is used to select

GPIOC0 EXTAL 32 Pull-ups should default to disabled

GPIOC1 XTAL 33 Pull-ups should default to disabled

GPIOC2 CAN_RX 46 CAN is NOT available in 56F8122

GPIOC3 CAN_TX 47 CAN is NOT available in 56F8122

GPIOC4 TC3

GPIOC5 TC1 / RXD0 48 SIM register SIM_GPS is used to select between Timer C

GPIOC6 TC0 / TXD0 1 SIM register SIM_GPS is used to select between Timer C

Package Pin Notes

between Decoder 0 and Timer A

Quad Dec is NOT available in 56F8122

and SCI0 on a pin-by-pin basis

8.3 Memory Maps

The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values of these registers.

Part 9 Joint Test Action Group (JTAG)

9.1 JTAG Information

Please contact your Freescale marketing representative or authorized distributor for device/package-specific BSDL information.

The TRST pin is not available in this package. The pin is tied to VDD in the package.

The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F8300 Peripheral User Manual.

56F8322 Techncial Data, Rev. 10.0

98 Freescale Semiconductor

Preliminary

General Characteristics

Part 10 Specifications

10.1 General Characteristics

The 56F8322/56F8122 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the

power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage.

Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device.

Note: All specifications meet both Automotive and Industrial requirements unless individual

specifications are listed.

Note: The 56F8122 device is guaranteed to 40MHz and specified to meet Industrial requirements only.

CAUTION

This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor 99 Preliminary

Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN

and Quad Decoder are NOT available on the 56F8122 device.

Table 10-1 Absolute Maximum Ratings

(VSS = V

SSA_ADC

Characteristic Symbol Notes Min Max Unit

= 0)

Supply voltage

ADC Supply Voltage

Oscillator / PLL Supply Voltage

Internal Logic Core Supply Voltage

Input Voltage (digital)

Input Voltage (analog)

Output Voltage

Output Voltage (open drain)

Ambient Temperature (Automotive)

Ambient Temperature (Industrial)

Junction Temperature (Automotive)

Junction Temperature (Industrial)

Storage Temperature (Automotive)

Storage Temperature (Industrial)

DD_IO

DDA_ADC,

REFH

DDA_OSC_PLL

DD_CORE

INA

OUT

STG

must be less than

REFH

or equal to

OCR_DIS is High

Pin Groups 1, 3, 4, 5

Pin Groups 1, 2, 3

GPIO pins used in open

DDA_ADC

Pin Group 7

drain mode

- 0.3 4.0 V

- 0.3 3.0 V

-0.3 6.0 V

-0.3 4.0 V

-0.3 6.0 V

-40 125 °C

-40 105 °C

-40 150 °C

-40 125 °C

-55 150 °C

Note: The overall life of this device may be reduced if subjected to extended use over 110°C junction. For additional information,

please contact your sales representative.

Note: Pins in italics are NOT available in the 56F8122 device.

Pin Group 1: TC0-1, FAULTA0, SS0, MISO0, MOSI0, SCLK0, HOME0, INDEX0, PHASEA0, PHASEB0, CAN_RX, CAN_TX

Pin Group 2: TDO

Pin Group 3: PWMA0-5

Pin Group 4: RESET, TMS, TDI, IRQA

Pin Group 5: TCK

Pin Group 6: XTAL, EXTAL

Pin Group 7: ANA0-6

56F8322 Techncial Data, Rev. 10.0

100 Freescale Semiconductor

Preliminary

Freescale Semiconductor 56F8122, 56F8322 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Part 1 Overview

1.1 56F8322/56F8122 Features

1.1.1 Hybrid Controller Core

1.1.2 Differences Between Devices

1.1.3 Memory

1.1.4 Peripheral Circuits

1.1.5 Energy Information

1.2 Device Description

1.2.1 56F8322 Features

1.2.2 56F8122 Features

1.3 Award-Winning Development Environment

1.4 Architecture Block Diagram

1.5 Product Documentation

1.6 Data Sheet Conventions

Part 2 Signal/Connection Descriptions

2.1 Introduction

2.2 Signal Pins

Part 3 On-Chip Clock Synthesis (OCCS)

3.1 Introduction

3.2 External Clock Operation

3.2.1 Crystal Oscillator

3.2.2 Ceramic Resonator (Default)

3.2.3 External Clock Source

3.3 Use of On-Chip Relaxation Oscillator

3.4 Internal Clock Operation

3.5 Registers

Part 4 Memory Map

4.1 Introduction

4.2 Program Map

4.3 Interrupt Vector Table

4.4 Data Map

4.5 Flash Memory Map

4.6 EOnCE Memory Map

4.7 Peripheral Memory Mapped Registers

4.8 Factory-Programmed Memory

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

5.2 Features

5.3 Functional Description

5.3.1 Normal Interrupt Handling

5.3.2 Interrupt Nesting

5.3.3 Fast Interrupt Handling

5.4 Block Diagram

5.5 Operating Modes

5.6 Register Descriptions

5.6.1 Interrupt Priority Register 0 (IPR0)

5.6.1.1 Reserved—Bits 15–14

5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)— Bits13–12

5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10

5.6.1.4 Reserved—Bits 9–0

5.6.2 Interrupt Priority Register 1 (IPR1)

5.6.2.1 Reserved—Bits 15–6

5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4

5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2

5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0

5.6.3 Interrupt Priority Register 2 (IPR2)

5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)—Bits 13–12

5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10

5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8

5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6

5.6.3.6 Reserved—Bits 5–2

5.6.3.7 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0

5.6.4 Interrupt Priority Register 3 (IPR3)

5.6.4.1 Reserved—Bits 15–10

5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6

5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4

5.6.4.5 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2

5.6.4.6 Reserved—Bits 1–0

5.6.5 Interrupt Priority Register 4 (IPR4)

5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14

5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12

5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10

5.6.5.4 Reserved—Bits 9–6

5.6.5.5 GPIO_A Interrupt Priority Level (GPIOA IPL)—Bits 5–4

5.6.5.6 GPIO_B Interrupt Priority Level (GPIOB IPL)—Bits 3–2

5.6.5.7 GPIO_C Interrupt Priority Level (GPIOC IPL)—Bits 1–0