Freescale Semiconductor 56F8300 Series, 56F8357 User Manual

56F8357

Evaluation Module User Manual

56F8300
16-bit Hybrid Controllers

MC56F357EVMUM
Rev. 1
08/2004

freescale.com

TABLE OF CONTENTS

Preface vii

Chapter 1

Introduction

1.1 56F8357EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 56F8357EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 56F8357EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2

Technical Summary

2.1 56F8357. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 Program and Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4 Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5.1 EXTBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.2 EMI_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.3 CLKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.6 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.11 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.11.1 Peripheral Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.11.2 Memory Daughter Card Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.12 Motor Control PWM Signals and LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.13 CAN Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.14 Software Feature Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Freescale Semiconductor i
Preliminary

TOC

2.15 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.15.1 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.15.2 Data Bus Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.15.3 External Memory Control Signal Expansion Connector. . . . . . . . . . . . . . . . . . . . . 2-26

2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . . 2-26

2.15.5 Encoder #1 / SPI #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.15.6 Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.15.7 Timer Channel D Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.15.8 A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.15.9 A/D Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.15.10 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-30

2.15.11 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-30

2.15.12 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.15.13 FlexCAN Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.15.14 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.15.15 PWM Port B Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

Appendix A

56F8357EVM Schematics

Appendix B

56F8357EVM Bill of Material

ii Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

LIST OF FIGURES

1-1 Block Diagram of the 56F8357EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 56F8357EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1-3 Connecting the 56F8357EVM Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2-1 Schematic Diagram of the External CS0 Memory Interface. . . . . . . . . . . . . . . . . . . 2-4

2-2 Schematic Diagram of the External CS1/CS4 Memory Interface. . . . . . . . . . . . . . . 2-5

2-3 Schematic Diagram of the RS-232 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-8 Schematic Diagram of the RESET Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2-10 PWM Group A Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2-11 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2-12 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2-13 Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Freescale Semiconductor iii
Preliminary

LOF

iv Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

LIST OF TABLES

1-1 56F8357EVM Default Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2-1 SCI0 Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-3 EXTBOOT Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-4 EMI Operating Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-5 EMI Operating Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-6 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-7 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-8 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-11

2-9 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2-10 Parallel JTAG Interface Voltage Jumper Selection. . . . . . . . . . . . . . . . . . . . . . 2-13

2-11 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-16

2-12 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2-13 CAN Header Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2-14 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-24

2-15 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-25

2-16 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-26

2-17 Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2-18 SPI #1 Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2-19 Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2-20 Timer Channel D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2-21 A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2-22 A/D Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2-23 SCI #0 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2-24 SCI #1 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2-25 SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Freescale Semiconductor v
Preliminary

2-26 CAN Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2-27 PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2-28 PWM Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

vi Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

Preface

This reference manual describes in detail the hardware on the 56F8357 Evaluation
Module.

Audience

This document is intended for application developers who are creating software for
devices using the Freescale 56F8357 part or a member of the 56F8300 family that is
compatible with this part. Examples would include the 56F8347 and the 56F8356.

Organization

This manual is organized into two chapters and two appendixes.

• Chapter 1,Introduction

• Chapter 2,Technical Summary describes in detail the 56F8357 hardware.

• Appendix A,"56F8357EVM Schematics"contains the schematics of the
56F8357EVM.

Appendix B,"56F8357EVM Bill of Material" provides a list of the materials used on the

•

56F8357EVM board.

provides an overview of the EVM and its features.

Suggested Reading

More documentation on the 56F8357 and the 56F8357EVM kit may be found at URL:

freescale.com

Freescale Semiconductor vii
Preliminary

Preface

Notation Conventions

This manual uses the following notational conventions:

Term or Value Symbol Examples Exceptions

Active High
Signals
(Logic One)

Active Low
Signals
(Logic Zero)

Hexadecimal
Values

Decimal Values No special symbol

Binary Values Begin with the letter

Numbers Considered positive

Blue Text Linkable on-line ...refer to Chapter 7, License

Bold Reference sources,

No special symbol
attached to the
signal name

Noted with an
overbar in text and
in most figures

Begin with a “$”
symbol

attached to the
number

“b” attached to the
number

unless specifically
noted as a negative
value

paths, emphasis

A0

CLKO

WE

OE

$0FF0

$80

10
34

b1010

b0011

5

-10

...see:

http://www.freescale.com/

In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE

Voltage is often shown as
positive: +3.3V

Definitions, Acronyms, and Abbreviations

Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference.

A/D
ADC Analog-to-Digital Converter; a peripheral on the 56F8357 part

CAN Controller Area Network; serial communications peripheral and method
CiA

D/A
DSP Digital Signal Processor or Digital Signal Processing

viii Freescale Semiconductor

Analog-to-Digital; a method of converting Analog signals to Digital
values

CAN in Automation; an international CAN user’s group that coordinates
standards for CAN communications protocols

Digital-to-Analog; a method of converting Digital values to an Analog
form

56F8357EVM User Manual, Rev. 1

Preliminary

56F8357

Hybrid controller with motor control peripherals

EOnCE

Enhanced On-Chip Emulation; a debug bus and port was created to
enable a designer to create a low-cost hardware interface for a
professional-quality debug environment

EVM

Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application

FlexCAN
GPIO

Flexable CAN Interface Module; a peripheral on the 56F8357 part
General Purpose Input and Output port on Freescale’s family of hybrid

controllers; does not share pin functionality with any other peripheral on
the chip and can only be set as an input, output or level-sensitive
interrupt input

IC
JTAG
LED

Integrated Circuit
Joint Test Action Group; a bus protocol/interface used for test and debug
Light Emitting Diode

LQFP Low-profile Quad Flat Package
MPIO

Multi-Purpose Input and Output port on Freescale’s family of hybrid
controllers; shares package pins with other peripherals on the chip and
can function as a GPIO

OnCE

TM

On-Chip Emulation, a debug bus and port created to allow a means for
low-cost hardware to provide a professional-quality debug environment

PCB
PLL
PWM
QuadDec
RAM
R/C
ROM
SCI

Printed Circuit Board
Phase Locked Loop
Pulse Width Modulation
Quadrature Decoder; a peripheral on the 56F8357 part
Random Access Memory
Resistor/Capacitor Network
Read-Only Memory
Serial Communications Interface; a peripherial on Freescale’s family of

hybrid controllers

SPI

Serial Peripheral Interface; a peripheral on Freescale’s family of hybrid
controllers

SRAM

Static Random Access Memory

UART Universal Asynchronous Receiver/Transmitter
WS

Wait State

Freescale Semiconductor ix
Preliminary

Preface

References

The following sources were referenced to produce this manual:

[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor
[2] 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor
[3] 56F8357 Technical Data, MC56F8357, Freescale Semiconductor
[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,

Version 1.0, CAN in Automation

[5] CAN Specification 2.0B, BOSCH or CAN in Automation

x Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

Chapter 1
Introduction

The 56F8357EVM is used to demonstrate the abilities of the 56F8357 hybrid controller and to
provide a hardware tool allowing the development of applications.

The 56F8357EVM is an evaluation module board that includes a 56F8357 part, peripheral
expansion connectors, a CAN interface, 512KB of external memory and a pair of daughter card
connectors. The daughter card connectors are for signal monitoring and user feature
expandability.

The 56F8357EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56F8357EVM facilitate evaluation of the feature set
and the benefits of the family.

• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.

• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the Processor's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the
Processor is available to the user.

Freescale Semiconductor 1-1
Preliminary

Introduction, Rev. 1

1.1 56F8357EVM Architecture

The 56F8357EVM facilitates the evaluation of various features present in the 56F8357 part. The
56F8357EVM can be used to develop real-time software and hardware products. The
56F8357EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The 56F8357EVM is flexible enough to allow a user to fully exploit the 56F8357's
features to optimize the performance of his product, as shown in Figure 1-1.

56F8357

DSub

25-Pin

Program Memory

128Kx16-bit

SRAM

Data Memory

128Kx16-bit

SRAM

Memory
Expansion
Connector

Memory

Daughter Card

Connector

Reset Logic

Mode/IRQ Logic

JTAG

Connector

Parallel

JTAG

Interface

8.00MHz
Crystal

Address,
Data &
Control

RESET

MODE/IRQ

JTAG/EOnCE

XTAL/
EXTAL

SPI #0

SCI #0

SCI #1
Timer C
Timer D

PWMA

ADCA

QuadDec #0

PWMB

ADCB

QuadDec #1

FlexCAN

+3.3V & GND

+3.3VA & AGND

+3.0V

REF

RS-232

Interface

Peripheral
Expansion

Connectors

CAN Interface

Debug LEDs

PWM LEDs

Power Supply

+3.3V, +3.3VA, +5V &

+3.0VA

DSub
9-Pin

Peripheral

Daughter Card

Connector

CAN Bus

Header

CAN Bus

DaisyChain

Figure 1-1. Block Diagram of the 56F8357EVM

1.2 56F8357EVM Configuration Jumpers

Ninteen jumper groups, (JG1-JG19), shown in Figure 1-2, are used to configure various features
on the 56F8357EVM board. Table 1-1 describes the default jumper group settings.

1-2 Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

JG9

JG12

1

JG15
1

JG16

56F8357EVM Configuration Jumpers

3

JG6

JG4

JG5

JG7

4

JG14

2

1

JG13

3

J18

J16

J13

J11

J15

J8

J7

PC0
PC1
PC2
PC3

PD6

3

3

1

2

4

PD7

PWMA0

PWMA1

PWMA2

PWMA3
PWMA4
PWMA5

JG15

JG16

JG10

J14

J12

J6

JG4

JG6

J1

U1

JG2

JG1

Y1

JG9

JG12

U4

J9

MC56F8357EVM

S3

JG11

LED3

S2

P2

RESET

IRQA

J19

J17

J4

JG7

JG5

J24

U2

JG18

J3

J10

JG19

S1

P1

IRQB

J20

J14

J5

J21

JG13

J22

JG8

JG17

J23

J2

U3

JTAG

U8

S/N

U9

JG3

P3

4

2

JG8

3

1

JG17

JG10

JG11

JG2

JG1

1

JG18

3

JG19

3

JG3

1

Figure 1-2. 56F8357EVM Jumper Reference

Table 1-1. 56F8357EVM Default Jumper Options

Jumper

Group

Comment

JG1 Use on-board EXTAL crystal input for oscillator 1–2
JG2 Use on-board XTAL crystal input for oscillator 1–2
JG3 Enable on-board Parallel JTAG Host/Target Interface NC
JG4 Enable Internal Boot Mode 1–2
JG5 Enable A0 - A23 for external memory accesses NC
JG6 Enable Crystal Mode 1–2
JG7 Enable SRAM Memory Bank 0 (use CS0) 1–2
JG8 Enable SRAM Memory Bank 1 (use CS1 & CS4) 1–2 & 3–4
JG9 Pass RXD0 & TXD0 to RS-232 level converter 1–2 & 3–4

Jumpers

Connections

JG10 Enable RS-232 output NC
JG11 Pass RS-232 RST to CTS 1–2
JG12 Pass Temperature Diode to ANA7 1–2
JG13 CAN termination selected 1–2
JG14 Isolate CAN2 (Unpopulated option) NC
JG15 High selected on User Jumper #0 1–2
JG16 High selected on User Jumper #1 1–2

Freescale Semiconductor 1-3
Preliminary

Introduction, Rev. 1

Table 1-1. 56F8357EVM Default Jumper Options (Continued)

Jumper

Group

JG17 CAN2 not terminated (Unpopulated option) NC
JG18 Analog Ground to Digital Ground not reconnected NC
JG19 Use +3.3V for Printer Interface to on-board Parallel JTAG Host/Target 1-2

Comment

Jumpers

Connections

1.3 56F8357EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply to the 56F8357EVM board.

Parallel Extension

Cable

56F8357EVM
PC-compatible
Computer

P1

Connect cable

to Parallel/Printer port

P3

External

+12V

Power

with 2.1mm,
receptacle
connector

Figure 1-3. Connecting the 56F8357EVM Cables

Perform the following steps to connect the 56F8357EVM cables:

1. Connect the parallel extension cable to the Parallel port of the host computer.

2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the

56F8357EVM board. This provides the connection which allows the host computer to
control the board.

3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC
power source.

4. Connect the 2.1mm output power plug from the external power supply into P3, shown in

Figure 1-3, on the 56F8357EVM board.

5. Apply power to the external power supply. The green Power-ON LED, LED13, will
illuminate when power is correctly applied.

1-4 Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

Chapter 2
Technical Summary

The 56F8357EVM is designed as a versatile development card using the 56F8357 processor,
allowing the creation of real-time software and hardware products to support a new generation of
applications in servo and motor control, digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F8357
processor, combined with the on-board 128K × 16-bit external Program/Data Static RAM
(SRAM), 128K × 16-bit external Data/Program SRAM, RS-232 interface, CAN interface,
Daughter Card interface, Peripheral Expansion connectors and parallel JTAG interface, makes
the 56F8357EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F8357 processor.

The main features of the 56F8357EVM, with board and schematic reference designators include:

• 56F8357PY60, a 16-bit +3.3V/+2.5V hybrid controller operating at 60MHz [U1]

• External Fast Static RAM (FSRAM) memory, configured as:
— 128K × 16-bit of memory [U2] with 0 Wait State at 60MHz via CS0
— 128K × 16-bit of memory [U3] with 0 Wait State at 60MHz via CS1/CS2

• 8.00MHz crystal oscillator, for base processor frequency generation [Y1]

• Optional external oscillator frequency input connectors [JG1 and JG2]

• Joint Test Action Group (JTAG) port interface connector, for an external debug Host
Target Interface [J3]

• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
cable [P1], including a disable jumper [JG3] and a printer port voltage selection jumper
[JG19]

• RS-232 interface, for easy connection to a host processor [U4 and P2], including a disable
jumper [JG10]

• RTS and CTS RS-232 control signal access [JG11]

• CAN interface, for high speed, 1.0Mbps, FlexCAN communications [U10 and J20]

• CAN bypass and bus termination [J21 and JG13]

Technical Summary, Rev. 1

Freescale Semiconductor 2-1
Preliminary

• Peripheral Daughter Card connector, to allow the user to connect his own SCI, SPI or
GPIO-compatible peripheral to the hybrid controller[J1]

• Memory Daughter Card connector, to allow the user to connect his own memory or
memory device to the device [J2]

• SCI #0 expansion connector, to allow the user to connect his own SCI #0 /
MPIO-compatible peripheral [J13]

• SCI #1 expansion connector, to allow the user to connect his own SCI #1 /
MPIO-compatible peripheral [J14]

• SPI #0 expansion connector, to allow the user to connect his own SPI #0 /
MPIO-compatible peripheral [J11]

• SPI #1 expansion connector, to allow the user to connect his own SPI #1 /
MPIO-compatible peripheral [J12]

• PWMA expansion connector, to allow the user to connect his own PWMA-compatible
peripheral [J7]

• PWMB expansion connector, to allow the user to connect his own PWMB-compatible
peripheral [J8]

• CAN expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J18]

• Timer A expansion connector, to allow the user to connect his own Timer A / Encoder
#0-compatible peripheral [J15]

• Timer C expansion connector, to allow the user to connect his own Timer C-compatible
peripheral [J16]

• Timer D expansion connector, to allow the user to connect his own Timer D-compatible
peripheral [J17]

• ADC A expansion connector, to allow the user to attach his own A/D port A-compatible
peripheral [J9]

• ADC B expansion connector, to allow the user to attach his own A/D port B-compatible
peripheral [J10]

• Address Bus expansion connector, to allow the user to monitor the external address bus
[J4]

• Data Bus expansion connector, to allow the user to monitor the external data bus [J5]

• External memory bus control signal connector, to allow the user to monitor the external
memory bus [J6]

• On-board power regulation provided from an external +12V DC-supplied power input
[P3]

2-2 Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

• Light Emitting Diode (LED) power indicator [LED13]

• Six on-board real-time user debugging LEDs [LED1-6]

• Six on-board Port A PWM monitoring LEDs [LED7-12]

• Internal/External (EXTBOOT) Boot MODE selector [JG4]

• Address Range (EMI_MODE) Boot MODE selector [JG5]

• Clock MODE (CLKMODE) Boot selector [JG6]

• Temperature Sense Diode to ANA7 selector [JG12]

• Manual RESET push-button [S1]

56F8357

• Manual interrupt push-button for IRQA

• Manual interrupt push-button for IRQB

[S2]

[S3]

• General-purpose jumper on GPIO PE4 [JG15]

• General-purpose jumper on GPIO PE7 [JG16]

2.1 56F8357

The 56F8357EVM uses a Freescale MC56F8357PY60 part, designated as U1 on the board and in
the schematics. This part will operate at a maximum external bus speed of 60MHz. A full
description of the 56F8357, including functionality and user information, is provided in these
documents:

• 56F8357 Technical Data Sheet, (56F8357): Electrical and timing specifications, pin
descriptions, device specific peripheral information and package descriptions (this
document)

• 56F8300 Peripheral User Manual, (MC56F8300UM): Detailed description of peripherals
of the 56F8300 family of devices

• DSP56800E Reference Manual, (DSP56800ERM): Detailed description of the 56800E
family architecture, 16-bit core processor, and the instruction set

Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:

Freescale Semiconductor 2-3
Preliminary

www.freescale.com

Technical Summary, Rev. 1

2.2 Program and Data Memory

The 56F8357EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.

2.2.1 SRAM Bank 0

SRAM bank 0, which is controlled by CS0, uses a 128K×16-bit Fast Static RAM (GSI GS72116,
labeled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1.
CS0 can be configured to use this memory bank as 16 bits of Program memory, Data memory, or
both. Additionally, CS0 can be configured to assign this memory’s size and starting address to
any modulo address space.

This memory bank will operate with zero Wait State access while the MC56F8357 is running at
60MHz and can be disabled by removing the jumper at JG7.

56F8357

A0-A16

D0-D15

RD

WR

PS/CS0

Jumper Pin 1-2:
Enable SRAM

Jumper Removed:
Disable SRAM

JG7

+3.3V

1

2

GS72116

A0-A16
DQ0-DQ15

OE

WE

CE

Figure 2-1. Schematic Diagram of the External CS0 Memory Interface

2.2.2 SRAM Bank 1

SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K × 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in

Figure 2-2. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word

(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.

2-4 Freescale Semiconductor

56F8357EVM User Manual, Rev. 1

Preliminary

Program and Data Memory

This memory bank will operate with zero Wait State access while the 56F8357 is running at
60MHz and can be disabled by removing the jumpers at JG8.

56F8357

A0-A16

D0-D15

DS/CS1

PD2/CS4

RD

WR

JG8

1
3

2
4

GS72116

A0-A16
DQ0-DQ15

OE

WE
LB

HB
CE

Jumper Pin 1-2:
Enable SRAM Low Byte

Jumper Pin 3-4:
Enable SRAM High Byte

Figure 2-2. Schematic Diagram of the External CS1/CS4 Memory Interface

Freescale Semiconductor 2-5
Preliminary

Technical Summary, Rev. 1

2.3 RS-232 Serial Communications

The 56F8357EVM provides an RS-232 interface by the use of an RS-232 level converter, Maxim
MAX3245EEAI, designated as U4. Refer to the RS-232 schematic diagram in Figure 2-3. The
RS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232-compatible
signal levels and connects to the host’s serial port via connector P2. RTS/CTS flow control is
provided on JG11 as a jumper, but could be implemented using uncommitted GPIO signals. The
SCI0 port signals can be isolated from the RS-232 level converter by removing the jumpers in
JG9; see Table 2-1. The pin-out of connector P2 is listed in Table 2-2. The RS-232 level
converter/transceiver can be disabled by placing a jumper at JG10.

56F8357

RS-232

Level Converter

Interface

P2

1
6
2
7
3
8
4

9

x

5

TXD0

RXD0

JG9

1
3

JG11

1
2

TXD

2
4

RXD

RTS

CTS

+3.3V

T1in
R1out

T2in
R2out

T1out

R1in
R2in

T2out

FORCEOFF

Jumper Removed:
Enable RS-232

Jumper Pin 1-2:
Disable RS-232

JG10

1
2

Figure 2-3. Schematic Diagram of the RS-232 Interface

.

Table 2-1. SC I0 Jumper Options

Pin # Signal Pin # Signal

1TXD02RS-232 TXD
3 RXD0 4 RS-232 RXD

2-6 Freescale Semiconductor

JG9

56F8357EVM User Manual, Rev. 1

Preliminary

Operating Mode

.

Table 2-2. RS-232 Serial Connector Description

P2

Pin # Signal Pin # Signal

1 Jumper to 6 & 4 6 Jumper to 1 & 4
2TXD7CTS
3RXD8RTS
4 Jumper to 1 & 6 9 NC
5GND

2.4 Clock Source

The 56F8357EVM uses an 8.00MHz crystal, Y1, connected to its External Crystal Inputs,
EXTAL and XTAL. To achieve its maximum internal operating frequency, the 56F8357 uses its
internal PLL to multiply the input frequency. An external oscillator source can be connected to
the processor by using the oscillator bypass connectors, JG1 and JG2; see Figure 2-4. If the input
frequency is above 8MHz, then the EXTAL input should be jumpered to ground by adding a
jumper between JG1 pins 2 and 3. The input frequency would then be injected on JG2’s pin 2. If
the input frequency is below 4MHz, then the input frequency can be injected on JG1’s pin 2.

EXTERNAL

8.00MHz

OSCILLATOR

HEADERS

JG1

1
2
3

JG2

1
2

56F8357

EXTAL

XTAL

Figure 2-4. Schematic Diagram of the Clock Interface

2.5 Operating Mode

The 56F8357EVM provides three BOOT MODE selection jumpers, EXTBOOT, EMI_MODE
and CLKMODE, to provide boot-up MODE options.

Freescale Semiconductor 2-7
Preliminary

Technical Summary, Rev. 1