DSP56F826/827
User Manual
56F800
16-bit Digital Signal Controllers
DSP56F826-827UM
Rev. 3.0
09/2005
freescale.com
This manual is one of a set of three documents. You need the following manuals to have complete
product information: Family Manual, User’s Manual, and Technical Data Sheet.
Order this document by DSP56F826-827UM - Rev. 5.0
March, 2005
Summary of Changes and Updates:
Clarified SPI Chapter Section 12.9.1.7
Clarified statement in GPIO Chapter immediately aboveTable 8-2
Converted to Freescale look and feel
TABLE OF CONTENTS
Chapter 1
56F826/827 Overview
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 56800 Family Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3 56800 Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.1 56800 Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5 56F826 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5.1 56F826 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.5.2 56F826 Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6 56F827 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.1 56F827 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.6.2 56F827 Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.7 56F826/827 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.7.1 Data Arithmetic Logic Unit (Data ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.7.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.7.3 Program Controller and Hardware Looping Unit. . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.7.4 Bit Manipulation Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.7.5 Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.7.6 On-Chip Emulation (OnCE) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.7.7 On-Chip Clock Synthesis (OCCS) Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.7.8 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.7.9 Phase Locked Loop (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.7.10 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.7.11 Energy Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.7.12 IPBus Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.8 Memory Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.8.1 Program Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.8.2 Program RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.8.3 Data Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.8.4 Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.9 56F826/827 Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.10 Peripheral Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.10.1 External Memory Interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.10.2 Programmable Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.10.3 General-Purpose Input/Output Port (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
1.10.4 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
1.10.5 COP/Watchdog Timer and Modes of Operation Module. . . . . . . . . . . . . . . . . . . . 1-23
TOC
Freescale Semiconductor Table of Contents - i
1.10.6 JTAG/OnCE Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
1.10.7 Quad Timer Module (TMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
1.10.8 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.10.9 Serial Communications Interface (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.10.10 Synchronous Serial Interface (SSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.10.11 Time-of-Day (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
1.10.12 Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Chapter 2
Pin Descriptions
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 Power and Ground Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3 Clock and Phase Lock Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4 Address, Data, and Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5 Quad Timer Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6 JTAG/OnCE Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.8 Serial Peripheral Interface (SPI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.9 Serial Communications Interface (SCI)
or Serial Peripheral Interface (SPI0) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.10 Serial Communications Interface (SCI) or
General Purpose Input/Output (GPIO) Signals
(56F827 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.11 Analog-to-Digital Converter (ADC) Signals
(56F827 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.12 Programmable Chip Select Signals (56F827 only). . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.13 Interrupt and Program Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Chapter 3
Memory and Operating Modes
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 The 56F826/827 Memory Map Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.1 Bus Control Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.2 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 Core Configuration Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.5 On-Chip Peripheral Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.6 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.7 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.7.1 Single Chip Mode: Start-Up (Mode 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.7.2 Modes One and Two (Modes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.7.3 External Mode (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
56F826/827 User Manual, Rev. 3
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3.8 Boot Flash Operation – 56F826 Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.9 Executing Programs from XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.10 56800 Reset and Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.11 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Chapter 4
On-Chip Clock Synthesis (OCCS)
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5.1 Oscillator Inputs (XTAL, EXTAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5.2 External Crystal Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5.3 Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6.1 PLL Control Register (PLLCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6.2 PLL Divide-By Register (PLLDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.6.3 PLL Status Register (PLLSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.6.4 CLKO Select Register (CLKOSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.6.5 Clock Operation in the Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.6.6 PLL Recommended Range of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.7 PLL Lock Time Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.7.1 Lock Time Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.8 PLL Frequency Lock Detector Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Chapter 5
Interrupt Controller (ITCN)
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.4 Priority Level Register (PLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.5 Interrupt Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.6 Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.7 Interrupt Priority Register (IPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.8 Interrupt Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.8.1 Synchronous Serial Interface (SSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.8.2 Serial Peripheral Interface (SPI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.8.3 Serial Peripheral Interface (SPI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.8.4 Serial Communications Interface (SCI0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
TOC
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5.8.5 Serial Communications Interface (SCI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.8.6 Serial Communications Interface (SCI2) (56F827 Only). . . . . . . . . . . . . . . . . . . . . 5-7
5.8.7 Analog-to-Digital Converter (ADC) (56F827 Only) . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.8.8 Timer Module (TMR A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.8.9 Time-of-Day Module (TOD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.8.10 Combined Interrupt Requests for Port A (GPIOA) . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.11 Combined Interrupt Requests for Port B (GPIOB) . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.12 Combined Interrupt Requests for Port C (GPIOC) . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.13 Combined Interrupt Requests for Port D (GPIOD) . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.14 Combined Interrupt Requests for Port E (GPIOE) (56F826 Only) . . . . . . . . . . . . . 5-8
5.8.15 Combined Interrupt Requests for Port F (GPIOF). . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.16 Combined Interrupt Requests for Port G (GPIOG) (56F827 Only) . . . . . . . . . . . . . 5-8
5.8.17 Data Flash Interface Unit (DFIU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.18 Program Flash Interface Unit (PFIU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.19 Upper Program Flash Interface Unit (PFIU2) (56F827 Only) . . . . . . . . . . . . . . . . . 5-8
5.8.20 Phase Lock Loop Module (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.21 Low Voltage Detect (LVD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.9 Priority Level and Vector Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.10 ITCN Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.11 Priority Level and Vector Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.12 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.12.1 Register Definitions (GPR2–GPR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Chapter 6
Flash Memory Interface (FLASH)
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 Flash Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4 Program Flash (PFLASH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.5 Data Flash (DFLASH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.6 Boot Flash (BFLASH) 56F826 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.7 Program/Data/Boot Flash Interface Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.8 Program/Data/Boot Flash Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.9 Functional Description of the PFIU, PFIU2, DFIU and BFIU . . . . . . . . . . . . . . . . . . . 6-10
6.10 Flash Programming and Erase Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.10.1 Intelligent Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.10.2 Dumb Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.10.3 Intelligent Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.11 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.11.1 Flash Control Register (FIU_CNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.11.2 Flash Program Enable Register (FIU_PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.11.3 Flash Erase Enable Register (FIU_EE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
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6.11.4 Flash Address Register (FIU_ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.11.5 Flash Data Register (FIU_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.11.6 Flash Interrupt Enable Register (FIU_IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.11.7 Flash Interrupt Source Register (FIU_IS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.11.8 Flash Interrupt Pending Register (FIU_IP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.11.9 Flash Clock Divisor Register (FIU_CKDIVISOR) . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.11.10 Flash T
ERASE
Limit Register (FIU_TERASEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.11.11 Flash TME Limit Register (FIU_TMEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.11.12 Flash T
6.11.13 Flash T
6.11.14 Flash T
6.11.15 Flash T
6.11.16 Flash T
6.11.17 Flash T
Limit Register (FIU_TNVSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
NVS
Limit Register (FIU_TPGSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
PGS
Limit Register (FIU_TPROGL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
PROG
Limit Register (FIU_TNVHL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
NVH
Limit Register (FIU_TNVH1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
NVH1
Limit Register (FIU_TRCVL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
RCV
6.11.18 Flash Interface Unit Timeout Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
6.12 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
6.13 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Chapter 7
External Memory Interface (EMI)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2 External Memory Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.4.1 Bus Control Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.4.2 State of Pins in Different Processing States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.5 Programmable Chip-Select (56F827 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.6 Chip Select Features (56F827 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.7 Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.7.1 Default Function of PCS0 and PCS1 (56F827 Only) . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.8 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.8.1 PCS Base Address Registers (PCSBAR0, ... ,PCSBAR7) . . . . . . . . . . . . . . . . . . 7-12
7.8.2 PCS Option Registers (PCSOR0, PCSOR1,..., PCSOR7) . . . . . . . . . . . . . . . . . . 7-15
Chapter 8
General Purpose Input/Output (GPIO)
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.4 Chip Specific Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.5 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.6 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
TOC
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8.7 GPIO Programming Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.8 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.8.1 GPIO Pull-Up Enable Register (PUR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.8.2 Data Register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.8.3 Data Direction Register (DDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.8.4 Peripheral Enable Register (PER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.8.5 Interrupt Assert Register (IAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.8.6 Interrupt Enable Register (IENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.8.7 Interrupt Polarity Register (IPOLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.8.8 GPIO Interrupt Pending Register (GPIO_IPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.8.9 Interrupt Edge Sensitive Register (IESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Chapter 9
Analog-to-Digital Converter (ADC)
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.5.1 Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.5.2 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.3 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.6 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.7.1 Analog Input Pins (AN[0-9]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.7.2 Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.7.3 Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.8 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.8.1 ADC Control Register 1 (ADCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.8.2 ADC Control Register 2 (ADCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.8.3 Zero Crossing Control Register (ADZCC1 and ADZCC2) . . . . . . . . . . . . . . . . . . 9-17
9.8.4 ADC Channel List Registers (ADLST1–ADLST5). . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9.8.5 ADC Sample Disable Register (ADSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.8.6 ADC Status Registers (ADSTAT1 and ADSTAT2) . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.8.7 ADC High and Low Limit Status Registers (ADHLSTAT and ADLLSTAT) . . . . . . 9-25
9.8.8 ADC Zero Crossing Status Register (ADZCSTAT) . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.8.9 ADC Result Registers (ADRSLT0,...,ADRSLT9) . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9.8.10 Low and High Limit Registers (ADLLMT0–9,..,ADHLMT0–9). . . . . . . . . . . . . . . . 9-29
9.8.11 ADC Offset Registers (ADOFS0–9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
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Chapter 10
Serial Communications
Interface (SCI)
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4.1 Data Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.4.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.5 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.1 Single-Wire Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.2 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.3 Low-Power Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.6.1 SCI Baud Rate Register (SCIBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.6.2 SCI Control Register (SCICR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.6.3 SCI Status Register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.6.4 SCI Data Register (SCIDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.7 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.9.1 Transmitter Empty Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.9.2 Transmitter Idle Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.9.3 Receiver Full Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.9.4 Receive Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
Chapter 11
Serial Peripheral Interface (SPI)
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.1 Master In/Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.2 Master Out/Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.3 Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.4.4 Slave Select (SS
11.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
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) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
TOC
11.5.1 Data Transmission Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.2 Data Shift Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.3 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.4 Transmission Format When CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.5.5 Transmission Format When CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.5.6 Transmission Initiation Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6 Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.7.1 Overflow Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.8 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.8.1 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.8.2 SPI Data Size Register (SPDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11.8.3 SPI Data Receive Register (SPDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
11.8.4 SPI Data Transmit Register (SPDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
11.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
Chapter 12
Synchronous Serial Interface (SSI)
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.2 SSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.2.1 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.2.2 SSI Clock and Frame Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.4 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.4.1 SSI Transmit Register (STX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.4.2 SSI Transmit FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.4.3 SSI Transmit Shift Register (TXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.4.4 SSI Receive Data Register (SRX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.4.5 SSI Receive FIFO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.4.6 SSI Receive Shift Register (RXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.4.7 SSI Control/Status Register 1 (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.4.8 SSI Receive Control Register 2 (SCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.4.9 SSI Transmit and Receive Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.4.10 SSI Time Slot Register (STSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
12.4.11 SSI FIFO Control/Status Register (SFCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12.4.12 SSI Option Register (SOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.5 SSI Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12.6 Configuration of the SSI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.7 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12.7.1 Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
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12.7.2 Network Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.7.3 Gated Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
12.8 Reset and Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
Chapter 12
Quad Timer Module (TMR)
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
12.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
12.4 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
12.5.1 Counting Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
12.5.2 External Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
12.5.3 OFLAG Output Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
12.5.4 Master Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
12.6 Counting Mode Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
12.6.1 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
12.6.2 Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
12.6.3 Edge Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
12.6.4 Gated Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
12.6.5 Quad Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
12.6.6 Signed Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
12.6.7 Triggered Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
12.6.8 One-Shot Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
12.6.9 Cascade Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
12.6.10 Pulse Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
12.6.11 Fixed-Frequency PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
12.6.12 Variable Frequency PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
12.6.13 Compare Registers Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
12.6.14 Capture Register Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
12.7 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
12.7.1 TMR Control Registers (CTRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
12.7.2 TMR Status and Control Registers (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
12.7.3 TMR Compare Register 1 (CMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
12.7.4 TMR Compare Register 2 (CMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
12.7.5 TMR Capture Register (CAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
12.7.6 TMR Load Register (LOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
12.7.7 TMR Hold Register (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
12.7.8 TMR Counter Register (CNTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
12.7.9 TMR Comparator Load Register 1 (CMPLD1)–56F827 Only . . . . . . . . . . . . . . . 13-20
12.7.10 TMR Comparator Load Register 2 (CMPLD2)–56F827 Only . . . . . . . . . . . . . . . 13-21
12.7.11 TMR Comparator Status and Control Register (COMSCR)– 56F827 Only . . . . 13-21
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12.8 Timer Group A Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
12.8.1 Timer Group A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
Chapter 13
Time-of-Day (TOD)
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
13.3 Counter Operation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
13.4.1 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
13.4.2 Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
13.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
13.5.1 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
13.5.2 TOD Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
13.5.3 Alarm Interrupt Flag and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
13.5.4 One-Second Interrupt Flag and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
13.6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
13.7 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
13.7.1 TOD Control Status (TODCS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
13.7.2 TOD Clock Scaler (TODCSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
13.7.3 TOD Seconds Counter (TODSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
13.7.4 TOD Seconds Alarm Register (TODSAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
13.7.5 TOD Minutes Counter (TODMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
13.7.6 TOD Minutes Alarm Register (TODMAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
13.7.7 TOD Hours Counter (TODHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
13.7.8 TOD Hours Alarm Register (TODHAL)—Bits 4–0. . . . . . . . . . . . . . . . . . . . . . . . 14-13
13.7.9 TOD Days Counter (TODDAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
13.7.10 TOD Days Alarm Register (TODDAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Chapter 15
Reset, Low Voltage, Stop and Wait Operations
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2 Sources of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3 Power-On Reset and Low Voltage Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.4 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.5 Computer Operating Properly (COP) Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.6 COP Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.6.1 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.6.2 COP After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.6.3 COP in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.6.4 COP in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.7 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
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15.7.1 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.7.2 COP Timeout Register (COPTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.7.3 COP Service Register (COPSRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.8 Stop and Wait Mode Disable Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.8.1 System Control Register (SYS_CNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.8.2 System Status Register (SYS_STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.8.3 Most Significant Half of JTAG ID (MSH_ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.8.4 Least Significant Half of JTAG ID (LSH_ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Chapter 16
OnCE Module
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3 Combined JTAG/OnCE Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.4 JTAG/OnCE Port Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.5 OnCE Module Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.6 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.7 Command, Status, and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.7.1 OnCE Shift Register (OSHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.7.2 OnCE Command Register (OCMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.7.3 OnCE Decoder (ODEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.7.4 OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.7.5 COP Timer Disable (COPDIS)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.7.6 OnCE Status Register (OSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16.8 Breakpoint and Trace Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.8.1 OnCE Breakpoint/Trace Counter Register (OCNTR) . . . . . . . . . . . . . . . . . . . . . 16-25
16.8.2 OnCE Memory Address Latch Register (OMAL) . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.8.3 OnCE Breakpoint Address Register (OBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.8.4 OnCE Memory Address Comparator (OMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.8.5 OnCE Breakpoint and Trace Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.9 Pipeline Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27
16.9.1 OnCE PAB Fetch Register (OPABFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.9.2 OnCE PAB Decode Register (OPABDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.9.3 OnCE PAB Execute Register (OPABER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.9.4 OnCE PAB Change-of-Flow FIFO (OPFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.9.5 OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.9.6 OnCE PGDB Register (OPGDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31
16.9.7 OnCE FIFO History Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
16.10 Breakpoint 2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-34
16.11 Breakpoint Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35
16.11.1 Programming the Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39
16.11.2 OnCE Trace Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40
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16.12 The Debug Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41
16.12.1 OnCE Normal, Debug, and Stop Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42
16.12.2 Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43
16.13 Accessing the OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45
16.13.1 Primitive JTAG Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45
16.13.2 Entering the JTAG Test-Logic-Reset State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45
16.13.3 Loading the JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47
16.13.4 Accessing a JTAG Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-49
16.13.5 OnCE Module Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-56
16.13.6 Resetting the Chip Without Resetting the OnCE Unit. . . . . . . . . . . . . . . . . . . . . 16-56
Chapter 17
JTAG Port
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4 JTAG Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.5 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.5.1 JTAG Instruction Register (JTAGIR) and Decoder . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.5.2 JTAG Chip Identification (CID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.5.3 JTAG Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.5.4 JTAG Bypass Register (JTAGBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
17.6 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
17.7 56F826/827 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26
Appendix A
Glossary
A.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
Appendix B
Programmer’s Sheets
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3
2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
3 Interrupt, Vector, and Address Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12
4 Programmer’s Sheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13
56F826/827 User Manual, Rev. 3
Table of Contents - xii Freescale Semiconductor
LIST OF FIGURES
1-1 56800 Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1-2 56800 Bus Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1-3 56F826 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1-4 56F827 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2-1 56F826 Functional Group Pin Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2 56F827 Functional Group Pin Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
3-3 56F80x On-Board Address and Data Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
4-1 OCCS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4-2 Reference Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4-3 Changing Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4-4 External Crystal Oscillator CircuitExternal Clock Source . . . . . . . . . . . . . . . . . . . . 4-7
4-5 Connecting an External Clock Signal using XTAL . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4-6 OCCS Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4-11 Relationship of IPBus Clock and ZCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4-12 Recommended Design Regions of OCCS PLL Operation . . . . . . . . . . . . . . . . . . 4-17
4-13 PLL Output Frequency vs. Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
5-2 Extension to the Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5-3 ITCN Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5-4 Group Priority Register 0 (GPR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
6-1 Program Flash Block Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6-2 Data Flash Block Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6-3 Boot Flash Block Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6-4 Flash Program Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6-5 FLASH Page Erase Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6-6 Flash Mass Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6-7 FLASH Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
7-1 56F826/827 Input/Output Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7-3 Bus Operation (Read/Write–Zero Wait States). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7-4 Bus Operation (Read/Write–Four Wait States). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7-5 PCS Registers Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
8-1 Block Diagram Showing GPIO Port Connections for 56F826. . . . . . . . . . . . . . . . . 8-5
8-2 Block Diagram Showing GPIO Port Connections for 56F827. . . . . . . . . . . . . . . . . 8-6
8-3 Bit-Slice View of the GPIO Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8-4 Edge Detector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8-5 GPIO Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
LOF
Freescale Semiconductor List of Figures - xiii
9-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9-2 ADC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9-3 Recommended Circuit for VREFHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9-6 ADC Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9-8 ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9-9 ADC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9-10 Result Register Data Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
10-1 SCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10-2 SCI Data Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10-3 SCI Transmitter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10-4 SCI Receiver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10-5 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10-6 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10-7 Fast Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10-8 Single-Wire Operation (LOOP = 1, RSRC = 1). . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10-9 Loop Operation (LOOP = 1, RSRC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10-10 SCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
11-1 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11-2 Full Duplex Master/Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11-3 Transmission Format (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11-4 CPHA/SS Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11-5 Transmission Format (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11-6 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11-7 SPRF/SPTE Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11-8 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11-9 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . . . . . . . . . . . . . . . 11-16
11-10 SPI Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11-15 SPI Interrupt Request Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
12-1 SSI Input/Output Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12-2 SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12-3 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12-4 SSI Transmit Clock Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12-5 SSI Transmit Frame Sync Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . 12-7
12-3 SSI Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12-4 SSI Transmit Register (STX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12-5 Transmit Data Path (TSHFD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12-6 Transmit Data Path (TSHFD=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12-7 SSI Receive Data Register (SRX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
56F826/827 User Manual, Rev. 3
List of Figures - xiv Freescale Semiconductor
12-8 Receive Data Path (RSHFD = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12-9 Receive Data Path (RSHFD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12-10 SSI Control/Status Register 1 (SCSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12-11 SSI Receive Control Register 2 (SCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12-15 SSI Transmit Register (STXCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12-16 SSI Receive Control Register (SRXCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12-17 SSI Bit Clock Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
12-18 SSI Time Slot Register (STSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12-19 SSI FIFO Control/Status Register (SFCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12-20 SSI Option Register (SOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12-21 Asynchronous (SYN=0) SSI Configurations-Continuous Clock . . . . . . . . . . . . . 12-32
12-22 Synchronous SSI Configuration-Continuous and Gated Clock. . . . . . . . . . . . . . 12-33
12-23 Serial Clock and Frame Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12-24 Normal Mode Timing—Continuous Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
12-25 Normal Mode Timing—Gated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12-26 Network Mode Timing—Continuous Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
12-1 56F826 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
12-2 56F827 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
12-3 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
12-1 TMR Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13-1 Time-of-Day Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
13-2 TOD Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
15-1 Sources of RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15-2 POR and Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15-3 POR Vs. Low-Voltage Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15-6 Stop/Wait Disable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
16-1 JTAG/OnCE Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16-2 56F80x OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16-3 OnCE Module Registers Accessed From the Core. . . . . . . . . . . . . . . . . . . . . . . 16-12
16-4 OnCE Shift Register (OSHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16-9 OCR Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16-15 OnCE Breakpoint Control Register 2 (OBCTL2). . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16-16 OnCE Status Register (OSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16-18 OnCE Breakpoint Address Register (OBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16-19 OnCE Breakpoint Address Register 2 (OBAR2). . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16-20 OnCE PAB Fetch Register (OPABFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16-21 OnCE PAB Decode Register (OPABDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16-22 OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30
LOF
Freescale Semiconductor List of Figures - xv
16-23 OnCE PDGB Register (OPGDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31
16-24 OnCE FIFO History Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33
16-25 Breakpoint and Trace Counter Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35
16-26 OnCE Breakpoint Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36
16-27 Breakpoint 1 Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37
16-28 Breakpoint 2 Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-38
16-29 Entering the JTAG Test-Logic-Reset State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46
16-30 Holding TMS High to Enter Test-Logic-Reset State . . . . . . . . . . . . . . . . . . . . . . 16-46
16-31 Bit Order for JTAG/OnCE Shifting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47
16-32 Loading DEBUG_REQUEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48
16-33 Shifting Data Through the BYPASS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-49
16-34 OnCE Shifter Selection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-51
16-35 Executing a OnCE Command by Reading the OCR. . . . . . . . . . . . . . . . . . . . . . 16-52
16-36 Executing a OnCE Command by Writing the OCNTR . . . . . . . . . . . . . . . . . . . . 16-53
16-37 OSR Status Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-54
16-38 JTAGIR Status Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-55
17-2 JTAG Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17-3 JTAGIR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17-5 JTAGIR Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17-6 JTAG Chip Identification Register (CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17-7 Chip Identification Register Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17-10 Boundary Scan Register for 56F826 (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17-12 JTAG Bypass Register (JTAGBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
17-13 TAP Controller State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25
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List of Figures - xvi Freescale Semiconductor
LIST OF TABLES
0-1 Pin Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvi
1-1 Feature Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1-2 56800 Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
2-1 56F826/827 Functional Group Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3 Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4 Other Supply Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-5 PLL and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6 Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-7 Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-8 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-9 Quad Timer Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-10 JTAG/OnCE Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-11 Dedicated General Purpose Input/Output (GPIO) Signals . . . . . . . . . . . . . . . . . . 2-11
2-12 Synchronous Serial Interface (SSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-13 Serial Peripheral Interface (SPI1) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-14 Serial Communications Interface (SCI0 & SCI1) Signals . . . . . . . . . . . . . . . . . . . 2-15
2-15 Serial Communications Interface (SCI2) Signals . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-16 Analog-to-Digital Converter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-17 Programmable Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-18 Interrupt and Program Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
3-1 Chip Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-2 Program Memory Map for 56F826/827. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-3 Data Memory Map for 56F826/827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-4 Port A Operation with DRV Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-5 Port A Operation with DRV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-6 Programming WSX[3:0] Bits for Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-7 Programming WSP [3:0] Bits for Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-8 Looping Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-9 MAC Unit Outputs With Saturation Mode Enabled (SA=1). . . . . . . . . . . . . . . . . . 3-11
3-10 56800 On-Chip Core Configuration Register Memory Map . . . . . . . . . . . . . . . . . 3-12
3-11 56F826 Data Memory Peripheral Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3-12 F56827 Data Memory Peripheral Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3-13 System Control Registers Address Map (SYS_BASE = $1000). . . . . . . . . . . . . . 3-15
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Freescale Semiconductor List of Tables - xvii
3-14 Program FLASH Interface Registers Address Map (PFIU_BASE = $1020) . . . . . 3-16
3-15 56F827 Program Flash Interface Unit #2 Registers
Address Map (PFIU2_BASE = $1040) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3-16 Data Flash Interface Unit Registers Address Map (DFIU_BASE = $1060) . . . . . 3-17
3-17 56F826 Boot Flash Interface Unit Registers Address Map
(BFIU_BASE = $1080). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3-18 Interrupt Controller Registers Address Map (ITCN_BASE = $1100) . . . . . . . . . . 3-18
3-19 56F826 Quad Timer A Registers Address Map
(TMRA_BASE = $10A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3-20 56F827 Quad Timer A Registers Address Map
(TMRA_BASE = $1200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3-21 Time-of-Day Registers Address Map (TOD_BASE = $10C0). . . . . . . . . . . . . . . . 3-21
3-22 SSI Registers Address Map (SSI_BASE = $10E0) . . . . . . . . . . . . . . . . . . . . . . . 3-22
3-23 SCI0 Registers Address Map (SCI0_BASE = $1160). . . . . . . . . . . . . . . . . . . . . . 3-22
3-24 SCI1 Registers Address Map (SCI1_BASE = $1170). . . . . . . . . . . . . . . . . . . . . . 3-22
3-25 56F827 SCI2 Registers Address Map (SCI2_BASE = $1180) . . . . . . . . . . . . . . . 3-22
3-26 SPI0 Registers Address Map (SPI0_BASE = $1140) . . . . . . . . . . . . . . . . . . . . . . 3-23
3-27 SPI1 Registers Address Map (SPI1_BASE = $1150) . . . . . . . . . . . . . . . . . . . . . . 3-23
3-28 COP Registers Address Map (COP_BASE = $1120) . . . . . . . . . . . . . . . . . . . . . . 3-23
3-29 Clock Generation Registers Address Map (CLKGEN_BASE = $10F0) . . . . . . . . 3-23
3-30 GPIO Port A Registers Address Map (GPIOA_BASE = $11A0). . . . . . . . . . . . . . 3-24
3-31 GPIO Port B Registers Address Map (GPIOB_BASE = $11B0). . . . . . . . . . . . . . 3-24
3-32 GPIO Port C Registers Address Map (GPIOC_BASE = $11C0) . . . . . . . . . . . . . 3-24
3-33 GPIO Port D Registers Address Map (GPIOD_BASE = $11D0) . . . . . . . . . . . . . 3-25
3-34 56F826 GPIO Port E Registers Address Map (GPIOE_BASE = $11E0) . . . . . . . 3-25
3-35 56F826 GPIO Port F Registers Address Map (GPIOF_BASE = $11F0) . . . . . . . 3-25
3-36 56F827 GPIO Port G Registers Address Map (GPIOG_BASE = $1240) . . . . . . . 3-26
3-37 56F827 ADC Registers Address Map (ADC_BASE = $12C0) . . . . . . . . . . . . . . 3-26
3-38 56F827 PCS Registers Address Map (PCS_BASE = $1190). . . . . . . . . . . . . . . . 3-27
3-39 Program Memory Chip Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3-40 Loading Program Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3-41 Reset and Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3-42 Reset and Interrupt Starting Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
4-1 OCCS Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4-2 OCCS Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4-3 On-Chip Clock States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
5-1 Interrupt Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5-2 Interrupt Vector Source and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5-3 ITCN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
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5-4 ITCN Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
6-1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6-2 IFREN Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6-3 Internal FLASH Timing Variables FLASH Timing Relationships. . . . . . . . . . . . . . . 6-5
6-4 Program Flash Main Block Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6-5 Program Flash Information Block Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6-6 Data Flash Main Block Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6-7 Data Flash Information Block Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6-8 Boot Flash Main Block Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6-9 Boot Flash Main Information Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6-10 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6-11 FLASH Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6-12 IFREN Bit Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
7-1 EMI Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7-2 Programming WSP[3:0] and WSX[3:0] Bits for Wait States . . . . . . . . . . . . . . . . . 7-5
7-3 Port A and PCS Operation with DRV Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7-4 Port A and PCS Operation with DRV Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7-5 EMI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7-6 PCS Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7-7 PCSBAR Encoding of the BLKSZ Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7-8 PCSOR Encoding of PCS PS / DS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
8-1 GPIO Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8-2 GPIO Interrupt Assert Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8-3 GPIO Registers With Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8-4 GPIO Pull-Up Enable Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8-5 GPIO Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8-6 GPIO Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8-7 GPIO Data Transfers Between I/O Pad and IPBus. . . . . . . . . . . . . . . . . . . . . . . . 8-20
9-4 ADC Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9-5 ADC Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9-7 ADC Input Conversion for Sample Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
10-1 Example 8-Bit Data Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10-2 Example 9-Bit Data Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10-3 Example Baud Rates (Module Clock = 40MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10-4 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10-5 Data Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10-6 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10-7 Loop Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
LOT
Freescale Semiconductor List of Tables - xix
10-1 SCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10-2 SCI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10-3 SCI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
11-1 External I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11-2 SPI I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11-1 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11-2 SPI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11-3 SPI Master Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11-4 Data Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
11-5 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
12-1 SSI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12-2 SSI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12-12 SSI Receive Data Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12-13 SSI Transmit Data Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12-14 Frame Sync and Clock Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12-1 SSI Data Word Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12-2 Chip Clock Rates as a Function of SSI
Bit Clock Frequency and Prescale Modulus . . . . . . . . . . . . . . . . . . . . . . 12-26
12-3 Number of Data Words Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12-4 Data FIFO Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12-5 Receive FIFO WaterMark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12-6 Transmit FIFO Empty Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12-7 TFWM Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12-8 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
12-9 SSI Control Bits Requiring Reset Before Change . . . . . . . . . . . . . . . . . . . . . . . 12-44
12-1 TMR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
12-2 TMR Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
12-3 Capture Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13-1 TOD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
13-2 TOD Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
13-3 TOD Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
15-4 COP/SIM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15-5 COP/SIM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15-7 Memory Map Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
16-1 JTAG/OnCE Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16-5 Register Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16-6 EX Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16-7 GO Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
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16-8 R/W Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16-10 Breakpoint Configuration Bits Encoding—Two Breakpoints . . . . . . . . . . . . . . . 16-17
16-11 Event Modifier Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16-12 BS[1:0] Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16-13 Breakpoint Programming with the BS[1:0] and BE[1:0] Bits . . . . . . . . . . . . . . . . 16-22
16-14 BE[1:0] Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16-17 Core Status Bit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
17-1 JTAG Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17-4 JTAGIR Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17-8 JTAG D Codes
JTAG ID code is expressed in hex form, and is calculated as (Version,
Design_Center, Part_Number, Manufacturer_ID,%1) . . . . . . . . . . . . . . . 17-12
17-9 Device ID Register Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17-11 BSR Contents for 56F80x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
D-1 List of Programmer’s Sheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13
LOT
Freescale Semiconductor List of Tables - xxi
56F826/827 User Manual, Rev. 3
List of Tables - xxii Freescale Semiconductor
Preface
About This Manual
Features of the 56F826 and 56F82716-bit devices are described in this manual. Details of
Memory, Operating modes, and Peripheral modules are documented here. This manual is
intended to be used with the DSP56800 Family Manual (DSP56800FM), describing the Central
Processing Unit (CPU), programming models, and instruction set details. The Technical Data
Sheet for each part provides electrical specifications as well as timing, pinout, and packaging
descriptions.
Audience
Information in this manual is intended to assist design and software engineers to integrate the
56F826 and/or 56F827 digital signal processors into a design and/or while developing application
software.
Manual Organization
Manual information is organized into chapters by topic.
Chapter 56F826/827 Overview provides a brief overview of the 56F826/827 devices.
Chapter Pin Descriptions describes pins on the 56F826/827 chips and how those pins are
grouped into various interfaces.
Chapter Memory and Operating Modes recounts the On-Chip Memory, structures, registers,
and interfaces.
Chapter On-Chip Clock Synthesis (OCCS) establishes the internal oscillator Phase Lock Loop
(PLL) and timers distribution chain for the 56F826/827.
Chapter Interrupt Controller (ITCN) details the 56F826/827 External Memory Interface also
referenced as Port A.
Chapter Flash Memory Interface (FLASH) describes the Program Flash, Data Flash, and Boot
Flash features and registers.
Chapter External Memory Interface (EMI) provides the External Memory Interface available
on the 56F826/827.
Preface, Rev. 3
Freescale Semiconductor xxiii
Chapter General Purpose Input/Output (GPIO) describes how GPIO pins share package pins
with other peripherals on the chip.
Chapter Analog-to-Digital Converter (ADC) provides data regarding the package feature in
the 56F827 only.
Chapter Serial Communications Interface (SCI) delineates the peripheral’s ability to
communicate with other devices such as codecs, microprocessors, and peripherals to provide the
primary data input path.
Chapter Serial Peripheral Interface (SPI) outlines the ability of the peripheral to communicate
with external devices such as Liquid Crystal Displays (LCDs) and Micro Controller Units
(MCUs).
Chapter Synchronous Serial Interface (SSI) elaborates on the capabilities of SSI as a part of
Port C and how it communicates with devices such as codecs, microprocessors, other devices,
and peripherals providing the primary data input path.
Chapter Quad Timer Module (TMR) expands on the available internal Quad Timer devices,
including features and registers.
Chapter Time-of-Day (TOD) develops instruction about the sequence of counters to track
elapsed time and its ability to track time up to 179.5 years, or 65,535 days, including keeping
track of leap year adjustments.
Chapter Reset, Low Voltage, Stop and Wait Operations is devoted to the on-chip Watchdog
Timer and the real-time interrupt generator and the modes of operation.
Chapter OnCE Module contains the specifics of the 56F826/827 On-Chip Emulation (OnCE™)
module, accessed through the Joint Test Action Group (JTAG) port.
Chapter JTAG Port provides specifics of the 56F826/827 JTAG port.
Chapter Glossary lists an index of abbreviations and acronyms along with their definitions used
in this manual.
Appendix B Programmer’s Sheets offers programming references and master programming
sheets used to program the 56F826/827 registers.
Additional information
• See http//:www.freescale.com/ for the most current BSDL listings.
• See device Techical Data Sheet for package and pin-out information.
56F826/827 User Manual, Rev. 3
xxiv Freescale Semiconductor
Suggested Reading
A list of books is provided here as an aid:
Advanced Topics in Signal Processing, Jae S. Lim and Alan V. Oppenheim (Prentice-Hall:
1988).
Applications of Digital Signal Processing, A. V. Oppenheim (Prentice-Hall: 1978).
Digital Processing of Signals: Theory and Practice, Maurice Bellanger (John Wiley and Sons:
1984).
Digital Signal Processing, Alan V. Oppenheim and Ronald W. Schafer (Prentice-Hall: 1975).
Digital Signal Processing: A System Design Approach, David J. DeFatta, Joseph G. Lucas, and
William S. Hodgkiss (John Wiley and Sons: 1988).
Discrete-Time Signal Processing, A. V. Oppenheim and R.W. Schafer (Prentice-Hall: 1989).
Foundations of Digital Signal Processing and Data Analysis, J. A. Cadzow (Macmillan: 1987).
Handbook of Digital Signal Processing, D. F. Elliott (Academic Press: 1987).
Introduction to Digital Signal Processing, John G. Proakis and Dimitris G. Manolakis
(Macmillan: 1988).
Multirate Digital Signal Processing, R. E. Crochiere and L. R. Rabiner (Prentice-Hall: 1983).
Signal Processing Algorithms, S. Stearns and R. Davis (Prentice-Hall: 1988).
Signal Processing Handbook, C. H. Chen (Marcel Dekker: 1988).
Signal Processing: The Modern Approach, James V. Candy (McGraw-Hill: 1988).
Theory and Application of Digital Signal Processing, Lawrence R. Rabiner and Bernard Gold
(Prentice-Hall: 1975).
Manual Conventions
Conventions used in this manual:
• Bits within registers are always listed from Most Significant Bit (MSB) to Least Significant
Bit (LSB).
• Bits within a register are formatted AA[n:0] when more than one bit is involved in a
description. For purposes of description, the bits are presented as if they are contiguous
within a register. However, this is not always the case. Refer to the programming model
diagrams or to the programmer’s sheets to see the exact location of bits within a register.
• When a bit is described as set, its value is set to one. When a bit is described as cleared, its
value is set to zero.
• Pins, or signals asserted low, made active when pulled to ground, have an overbar above
their name. For example, the SS0
pin is asserted low.
Preface, Rev. 3
Freescale Semiconductor xxv
• Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFB
is the X memory address for the Interrupt Priority Register (IPR).
• Code examples are displayed in a monospaced font, illustrated below:
BFSET #$0007,X:PCC ; Configure: line 1
; MISO0, MOSI0, SCK0 for SPI master line 2
; ~SS0 as PC3 for GPIO line 3
• Pins, or signals listed in code examples asserted as low have a tilde in front of their names.
In the previous example, line three refers to the SS0
pin, shown as ~SS0.
• The word reset is used in three different contexts in this manual. The word pin is a generic
term for any pin on the chip. They are described as:
— 1) There is a reset pin always written as RESET
— 2) The processor state occurs when the RESET
, in uppercase, using the over bar.
pin is asserted is always written as
Reset.
— 3) The word reset refers to the reset function is written in lowercase with a leading
capital letter as grammar dictates.
• The word pin is a generic term for any pin on the chip.
• The word assert means a high true (active high) signal is pulled high to V
, or a low true
DD
(active low) signal is pulled low to ground.
• The word deassert means a high true signal is pulled low to ground, or a low true signal is
pulled high to V
, illustrated in Table 0-1.
DD
• Shaded areas in registers represents reserved bits. They are written as zero, ensuring future
compatibility.
• Throughout this manual, Data Memory locations are noted as X:$0000 while Program
Memory locations are noted as P:$0000 where $ represents a memory location in hex.
• The PWM value registers are buffered. The value written does not take effect until the
LDOK bit is set and the next PWM load cycle begins. Reading PWMVALx reads value in
a buffer and not necessarily the value the PWM generator is currently using.
Table 0-1. Pin Conventions
V
IL/VOL
IH/VOH
1
OH
OL
Signal/Symbol Logic State Signal State
PIN
PIN False Deasserted
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
1.Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
xxvi Freescale Semiconductor
True Asserted
56F826/827 User Manual, Rev. 3
Voltage
V
Chapter 1
56F826/827 Overview
56F826/827 Overview, Rev. 3
Freescale Semiconductor 1
56F826/827 User Manual, Rev. 3
2 Freescale Semiconductor
Introduction
1.1 Introduction
Differing in size of memories and choice of peripherals, 56F826/827 multi-functional chips offer
solutions for a wide variety of applications. The core provides more processing power than any
other available control chip while saving design space and money. The 56F826 and 56F827 are
members of the Freescale 56800 core-based family of digital signal controllers.
The processing power of these controllers and the functionality of a microcontroller with a
flexible set of peripherals are combined on a single chip. This chip design provides an extremely
cost-effective and compact solution for a number of uses. The family of chips is designed to
provide control for such applications as:
• AC induction motors—for industrial and appliances such as washing machines, HVAC,
fans, vacuums, and motor drives
• Brush DC motors—for car window lifters, electric antennas, toys, cordless tools
• Brushless DC motors—used in automotive and appliances including PC fans, ceiling fans,
blowers, washing machines, electric power steering systems
• Switched and variable reluctance motors—such as washing machines, electric power
steering, dynamic body control, refrigerator compressors, HVAC, fans, vacuums and for
the power control for:
— General converter/inverter applications
— Uninterruptable power systems (in-line, line interactive, and standby)
— Inverter output stages (push-pull, half-bridge, and full bridge)
Either the 56F826/827 may be designed into the following applications:
• Automotive control
• Power line modem
• Uninterruptable power supplies
• Telephony system implementation
• Noise cancellation applications
• Home security
• Steppers and encoders
• Temperature regulation
• HVAC applications
• Remote monitoring and control
• Digital telephone answering machine
56F826/827 Overview, Rev. 3
Freescale Semiconductor 3
56800 Family Description
• Fuel management systems
• Voice enabled appliances
• Cable test equipment
• Electric energy meter with embedded power line modem
• Underwater acoustics
• Glass breakage detection and security systems
• Traffic light control
• Identification tag readers
• Servo drives
1.2 56800 Family Description
The 56800 core is based on a Harvard-style architecture consisting of three execution units
operating in parallel. The Microcontroller Unit (MCU) style programming model and optimized
instruction set provide straightforward generation of efficient, compact, and control code. The
instruction set is highly efficient for C-compilers, facilitating rapid development of optimized
control applications.
The 56800 chips support program execution from either internal or external memories, providing
two external dedicated interrupt lines and up to 32-General-Purpose Input/Output (GPIO) lines.
The controller includes Program Flash and Data Flash, each programmable through the Joint Test
Action Group (JTAG) port, with Program RAM and Data RAM. The controller also supports
program execution for external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
The controller also provides a full set of standard programmable peripherals: Serial
Communications Interface (SCI), Serial Peripheral Interface (SPI), and an additional Quad Timer
(TMR). Any of these interfaces can be used as a General-Purpose In/Out (GPIO) if those
functions are not required. An internal Interrupt Controller and dedicated GPIO, are also included
on some of the parts.
56F826/827 User Manual, Rev. 3
4 Freescale Semiconductor
56800 Core Description
1.3 56800 Core Description
The 56800 core consists of functional units operating in parallel, increasing the throughput of the
machine. The Harvard-style architecture consists of three execution units operating in parallel.
These three execution units allow as many as six operations during each instruction cycle. The
instruction set is also highly efficient for C-compilers. Major features of the 56800 core are:
• Efficient 16-bit 56800 family engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique addressing modes
• Hardware DO and REP loops
• Three internal address buses and one External Address Bus (EAB) available
• Four internal data buses and one EAB available
• Instruction set supports both and controller functions
• Controller style addressing modes and instructions for compact code
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE™ debug programming interface
1.3.1 56800 Core Block Diagram
An overall block diagram of the 56800 core architecture is illustrated in Figure 1-1. The 56800
core is fed by an internal program and Data Memory, an External Memory Interface (EMI), and
various peripherals suitable for embedded applications. The blocks include:
• Data Arithmetic Logic Unit (Data ALU)
• Address Generation Unit (AGU)
• Program controller and hardware looping unit
• Bit Manipulation Unit
• On-Chip Emulation (OnCE) port
• Interrupt Controller
• External Bus Bridge
• Address buses
• Data buses
56F826/827 Overview, Rev. 3
Freescale Semiconductor 5
56800 Core Description
Program
Controller
OMR
SR
LA LC
PC
HWS
Bus and Bit
Manipulation
Unit
OnCE
Instr. Decoder
and
Interrupt Unit
Data
ALU
Y1 Y0
AGU
M01 N
MOD.
+/-
ALU
Limiter
X0 A2 A1 A0 B2 B1 B0
SP
R0
R1
R2
R3
XAB1
XAB2
PAB
PDB
CGDB
XDB2
PGDB
MAC
and
ALU
Program
Memory
Data
Memory
External
Bus
Interface
IPBus
Interface
Figure 1-1. 56800 Core Block Diagram
The Program Controller, AGU and Data ALU each contain a discrete register set and control
logic so each can operate independently and in parallel with the others. Likewise, each functional
unit interfaces with other units, with memory, and with memory-mapped peripherals over the
core’s internal address and data buses, illustrated in Figure 1-2.
56F826/827 User Manual, Rev. 3
6 Freescale Semiconductor
56800 Core Description
Generator
Internal
Data Bus
Switch
PLL
Clock
Address
Generation
Unit
PDB
CGDB
Controller
Program
Program
RAM/FLASH
Expansion
XAB1
XAB2
PAB
RAM/FLASH
Expansion
16-Bit
Core
Data ALU
→
16 x 16 + 36
Three 16-Bit Input Regs
Two 36-Bit Accumulators
36-Bit Mac
Data
On-Chip
Expansion
Area
XDB2
Peripheral
Modules
IPBus
Bridge
TM
OnCE
IRQB
16 Bit Data Bus
IRQA
RESET
Figure 1-2. 56800 Bus Block Diagram
It is possible in a single instruction cycle for the program controller to be fetching a first
instruction, the AGU to generate two addresses for a second instruction, and the Data ALU to
perform a multiply in a third instruction. In a similar manner, the Bit Manipulation Unit (BMU)
can perform an operation of the third instruction previously described instead of the
multiplication in the Data ALU. The architecture is pipelined to take advantage of the parallel
units and significantly decrease the execution time of each instruction.
56F826/827 Overview, Rev. 3
Freescale Semiconductor 7
Architectural Overview
1.4 Architectural Overview
The 56F826/827 consists of the 56800 core, Program and Data Memory, and peripherals useful
for embedded control applications. Block diagrams for each chip describing the differences in
available peripheral sets and memory are illustrated in Figure 1-3 and Figure 1-4.
1.5 56F826 Description
The 56F826 is a member of the 56800 core-based family of devices. On a single chip, it
combines the processing power of a controller and the functionality of a microcontroller with a
flexible set of peripherals creating an extremely cost-effective solution for general-purpose
applications. Because of its low cost, configuration flexibility and compact program code, the
56F826 is well-suited for many applications such as:
• Noise suppression
• Identification tag readers
• Sonic/subsonic detectors
• Security access devices
• Remote metering
• Sonic alarms
• Point of Sale (POS) terminals
• Feature phones
The 56F826 supports program execution from either internal or external memories. Two data
operands can be accessed from the on-chip Data RAM per instruction cycle. Both chips also
provide two external dedicated interrupt lines and up to 46-GPIO lines, depending on peripheral
configuration.
The 56F826 controller includes 31.5K words of Program Flash and 2K words of Data Flash, each
programmable through the JTAG port, with 512 words of Program RAM, and 4K words of Data
RAM. The controller also supports program execution from external memory.
The 56F826 incorporates a total of 2K words of Boot Flash for easy inclusion of
field-programmable software routines, used to program the main Program and Data Flash
memory areas. Both Program and Data Flash memories can be independently bulk-erased or
erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or
page-erased.
56F826/827 User Manual, Rev. 3
8 Freescale Semiconductor
1.5.1 56F826 Features
• Up to 40MIPS at 80MHz core frequency
• MCU functionality in a unified, C-efficient architecture
• Hardware DO and REP loops
• 31.5K × 16-bit words Program Flash
• 512 × 16-bit words Program RAM
•2K × 16-bit words Data Flash Memory
•4K × 16-bit words Data RAM
•2K × 16-bit words Boot Flash Memory
• Up to 64K × 16-bit words each of external memory
expansion for Program and Data memory
• One Serial Port Interface (SPI)
• One additional SPI, or two optional Serial Communication Interfaces (SCIs)
56F826 Description
• One Synchronous Serial Interface (SSI)
• One General-Purpose Quad Timer
• JTAG/OnCE for debugging
• 16 dedicated and 30 shared GPIO
• Time-of-Day (TOD) timer
• 100-pin LQFP package
1.5.2 56F826 Benefits
• Flash Memory provides reliable, non-volatile memory storage, thereby eliminating
required external storage devices.
• Easy to program with flexible application development tools
• Optimized for C-Compiler efficiency
• Simple updating of Flash Memory through SPI, SCI, or OnCE using on-chip boot-loader
• Supports 9-bit communication protocol
• Simple port interface with other asynchronous serial communication devices
• Simple port interface with other asynchronous serial peripheral communication devices
and off-chip EE memory
• Sophisticated debugging using OnCE to view core, peripheral, and memory contents
56F826/827 Overview, Rev. 3
Freescale Semiconductor 9
56F827 Description
Quad Timer
4
6
SCI0 & SCI1
4
4
Dedicated
16
GPIO
SSI
or
GPIO
or
SPI0
SPI1
or
GPIO
GPIO
EXTBOOT
RESET
TOD
Time r
Interrupt
Controller
Program Memory
or
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
Applica-
tion-Specific
Memory &
Program Controller
Hardware Looping Unit
MODULE CONTROLS
ADDRESS BUS [8:0]
Peripherals
IRQB
IRQA
and
COP
RESET
DATA BUS [15:0]
PAB
PDB
XDB2
CGDB
XAB1
XAB2
6
JTAG/
OnCE
Port
Address
Generation
Unit
INTERRUPT
CONTROLS
IPBus Bridge
VDDV
SS
3
Low Voltage Supervisor
CONTROLS
16 16
44
3
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
IPBB
(IPBB)
V
DDIOVSSIO
Data ALU
16-Bit
56800
Core
External
Bus
Interface
Unit
V
DDAVSSA
Analog Reg
Manipulation
Clock Gen
Address Bus
Bit
Unit
PLL
.
External
Switch
External
Data Bus
Switch
Bus
Control
16
16
CLKO
XTAL
EXTAL
A[00:15]
or
GPIO
D[00:15]
PS Select
DS Select
WR Enable
RD Enable
Figure 1-3. 56F826 Block Diagram
1.6 56F827 Description
The 56F827 is a member of the Harvard-style architecture 56800 core-based family of devices. It
combines the processing power of a controller and the functionality of a microcontroller with a
flexible set of peripherals, creating an extremely cost-effective solution for general-purpose
applications. Because of its low cost, configuration flexibility, and compact program code, the
56F827 is well-suited for many applications. Two data operands per instruction cycle can be
accessed from the on-chip Data RAM per instruction cycle. The 56F827 incorporates easy
customer field-programmable software routines used to develop the main program. The 56F827
is well-suited for many applications such as:
• Noise suppression
• Identification tag readers
• Sonic/subsonic detectors
• Security access devices
• Remote metering
56F826/827 User Manual, Rev. 3
10 Freescale Semiconductor
56F827 Description
• Sonic alarms
• Point of Sale (POS) terminals
• Feature phones
The 56800 core consists of three execution units operating in parallel, allowing as many as six
operations per instruction cycle. The microprocessor-style programming model and optimized
instruction set allow forthright generation of efficient, compact code for MCU applications. The
instruction set is also highly efficient for C-Compilers to enable rapid development of optimized
control applications.
The 56F827 supports program execution from either internal or external memories. Two data
operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also
provides two external dedicated interrupt lines, and up to 64-GPIO lines, depending on peripheral
configuration.
The 56F827 controller includes 63K words of Program Flash and 4K words of Data Flash, each
programmable through the JTAG port, with 1K words of Program RAM, and 4K words of Data
RAM. It also supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals including one each
SSI, SCI, SPI, the option to select a second SPI or two SCIs, and one Quad Timer (TMR). The
SSI, SPI, and TMR can be used as GPIOs if those function are not required.
1.6.1 56F827 Features
• Up to 40MIPS at 80MHz core frequency
• MCU functionality in a unified, C-efficient architecture
• Hardware DO and REP loops
• 63K × 16-bit words Program Flash Memory
•1K × 16-bit words Program RAM
•4K × 16-bit words Data Flash Memory
•4K × 16-bit words Data RAM
• Up to 64K × 16-bit words external memory expansion for program and Data Memory
• JTAG/OnCE for debugging
• MCU-friendly instruction set supports controller functions: MAC, Bit Manipulation Unit
(BMU), 14 addressing modes
• 8-channel programmable chip select
• 10-channel, 12-bit Analog-to-Digital Converter (ADC)
56F826/827 Overview, Rev. 3
Freescale Semiconductor 11
56F827 Description
• Synchronous Serial Interface (SSI)
• Serial Port Interface (SPI)
• Serial Communication Interface (SCI)
• General-Purpose Quad Timer (TMR)
• Time-of-Day (TOD) timer
• 128-pin LQFP package
1.6.2 56F827 Benefits
• Flash Memory provides reliable, non-volatile memory storage, thus eliminating required
external storage devices.
• Easy to program with flexible application development tools
• Optimized for C-Compiler efficiency
• Simple updating of Flash Memory through SPI, SCI, or OnCE using on-chip boot loader
• Supports 9-bit communication protocol
• Simple interface with other asynchronous serial communication devices and off-chip EE
memory
• Capable of Analog-to-Digital Converter (ADC) functionality utilizing Quad Timer to
provide independence to each channel timer
• Sophisticated debugging using OnCE to view the core, peripheral, and memory contents
• Power-saving analog shut-down mode
56F826/827 User Manual, Rev. 3
12 Freescale Semiconductor
56F827 Description
V
REFP
V
REFIN
PCS [2:7}
inputs
, V
V
V
VPP
10
REFMID
REFLO
REFHI
16
,
3
Quad Timer A/
4
2
6
SCI 0 &1 or
4
4
Programmable
Chip Select
6
ADC
or GPIO
SCI 2 or
GPIO
SSI 0 or
GPI0
SPI 0
SPI 1 or
GPIO
Dedicated
GPIO
Interrupt
Controller
Program and Boot
Memory
64512 x 16 Flash
1024 x 16 SRAM
Data Memory
4096 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
Applica-
tion-Specific
Memory &
Peripherals
TOD
Timer
EXTBOOT
RESET
IRQA
Program Controller
and Hardware
Looping Unit
COP
RESET
MODULE
CONTROLS
ADDRESS
BUS [8:0]
DATA
BUS [15:0]
DEBUG
IRQB
PAB
PDB
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
V
6
5
JTAG/
OnCE
Port
Address
Generation
Unit
IPBB
CONTROLS
16 16
IPBus Bridge
(IPBB)
V
V
5
Data ALU
DD
SS
3
3
DDIOVSSIO
Low Voltage Supervisor
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
16-Bit
56800
Core
External
Bus
Interface
Unit
V
V
DDA
SSA
22
Analog Reg
Bit
Manipulation
Unit
PLL
Clock
Gen
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
16
16
CLKO
XTAL
EXTAL
A[00:15]
or
GPIOA16[00:16]
D[00:15]
or
GPIOG16[00:16]
PS or PCS
DS or PCS
WR
RD
Figure 1-4. 56F827 Block Diagram
56F826/827 Overview, Rev. 3
Freescale Semiconductor 13
56F826/827 Features
1.7 56F826/827 Features
Table 1-1. Feature Matrix
Feature 56F826 56F827
Speed (MIPS) 40 40
Program Flash 31.5K X 16 63K X 16
Data Flash 2K X 16 4K X 16
Program RAM 512 X 16 1K X 16
Data RAM 4K X 16 4K X 16
Boot Flash 2K X 16 —
ADC — 1
Oscillator External Crystal External Crystal
PLL 1 1
SCI
SPI
TOD 1 1
SSI 1 1
Watchdog 1 1
General-Purpose Timer 1 4-pin Quad Timer 1 4-pin Quad Timer
Dedicated GPIO 16 16
Shared GPIO 32 48
Muxed GPIO 48 64
JTAG/OnCE 1 1
Interrupt Controller 1 1
Programmable Chip Selects — 8
External Bus 32 32
Package 100 LQFP 128 LQFP
1
2
1
1
1 or 2
1
or 1
3
or 2
2
1
1. Two SCIs can be configured as an additional SPI.
2. Can be used as GPIO
1.7.1 Data Arithmetic Logic Unit (Data ALU)
The Data ALU performs all of the arithmetic and logical operations on data operands. It contains:
• Three 16-bit input registers
• Two 32-bit accumulator registers
• Two 4-bit accumulator extension registers
• One parallel, single cycle, non-pipelined MAC unit
• An accumulator shifter
• One data limiter
• One MAC output limiter
• One 16-bit barrel shifter
56F826/827 User Manual, Rev. 3
14 Freescale Semiconductor
56F826/827 Features
The Data ALU is capable of performing the following in one instruction cycle:
• Multiplication
• Multiply-accumulate with positive or negative accumulation
• Addition
• Subtraction
• Shifting
• Logical operations
Arithmetic operations are completed using two’s-complement fractional or integer arithmetic.
Support is also provided for unsigned and multi-precision arithmetic.
Data ALU source operands can be 16, 32, or 36 bits and can originate from input registers and/or
accumulators. ALU results are stored in one of the accumulators. Additionally, some arithmetic
instructions store their 16-bit results in any of the three Data ALU input registers, or write
directly to memory. Arithmetic operations and shifts have a 16-bit or 36-bit result, and logical
operations are performed on 16-bit operands yielding 16-bit results. Data ALU registers can be
read or written by the Core Global Data Bus (CGDB) as 16-bit operands, and the X0 register can
also be written by the X Data Bus two (XDB2) with a 16-bit operand.
1.7.2 Address Generation Unit (AGU)
The Address Generation Unit (AGU) performs all of the effective address calculations and
address storage necessary to address data operands in memory. This unit operates in parallel with
other chip resources to minimize address generation overhead. It contains two ALUs, allowing
the generation of up to two 16-bit addresses every instruction cycle—one for either the XAB1 or
Program Address Bus (PAB) and one for the XAB2 bus. The ALU can directly address 65,536
locations on the XAB1 or XAB2 bus. The ALU can also directly address 65,536 locations on the
PAB, for a total capability of 131,072 16-bit data words. Hooks are provided on the 56800 core
allowing expansion of address space. Its arithmetic unit can perform linear and modulo
arithmetic.
1.7.3 Program Controller and Hardware Looping Unit
The Program Controller performs:
• Instruction prefetch
• Instruction decoding
• Hardware loop control
• Interrupt (exception) processing
56F826/827 Overview, Rev. 3
Freescale Semiconductor 15
56F826/827 Features
Instruction execution is carried out in other core units, such as the Data ALU or AGU. The
program controller consists of a Program Counter (PC) unit, Hardware Looping Control Logic,
Interrupt Control Logic, and Status and Control registers.
Two interrupt control pins provide input to the program interrupt controller. The External
Interrupt Request A (IRQA
) pin and the External Interrupt Request B (IRQB) pin receive
interrupt requests from external sources.
The RESET
Reset state. When the RESET
pin resets the 56F826/827. When asserted, it initializes the chip and places it in the
pin is deasserted, the initial chip operating mode is latched into the
Operating Mode Register (OMR) based upon the value present on the EXTBOOT pin. The
56F826/827 is internally pulled low. Please refer to Section 3.3.2 for additional details.
1.7.4 Bit Manipulation Unit (BMU)
The Bit Manipulation Unit (BMU) performs bit field manipulations on X memory words,
peripheral registers, and registers on the DSP56800 core. It is capable of testing, setting, clearing,
or inverting any bits specified in a 16-bit mask. This unit tests bits on the upper or lower byte of a
16-bit word for branch on-bit field instructions, meaning the mask tests a maximum of eight bits
at a time.
Transfers between buses are accomplished in the bus unit. The bus unit is similar to a switch
matrix, and can connect any two of the three data buses together without adding any pipeline
delays. This procedure is required for transferring a core register to a peripheral register because
the core register is connected to the CGDB bus.
As a general rule, when reading any register less than 16 bits wide, unused bits are read as zero.
Reserved and unused bits should always be written with a zero, ensuring future compatibility.
1.7.5 Address and Data Buses
Addresses are provided to the internal X Data Memory on two unidirectional, 16-bit
buses—(XAB1, and XAB2). Program memory addresses are provided on the unidirectional
16-bit PAB.
Note: The XAB1 can provide addresses for accessing both internal and external memory,
whereas the XAB2 can only provide addresses for accessing internal read-only
memory. The External Address Bus (EAB) provides addresses for external memory.
Data movement on both the 56F80x occurs over three bidirectional, 16-bit buses and at least one
unidirectional 16-bit bus:
• CGDB bidirectional
• PDB bidirectional
56F826/827 User Manual, Rev. 3
16 Freescale Semiconductor
56F826/827 Features
• PGDB bidirectional
• XDB2 unidirectional
When one memory access is performed, data transfer between the Data ALU and the X Data
Memory occurs over the CGDB. When two simultaneous memory reads are performed, transfers
occur over the CGDB and the XDB2. All other data transfers to core blocks occur over the
CGDB, transferring all memory to and from peripherals over the PGDB. Instruction word fetches
occur simultaneously over the PDB. The External Data Bus (EDB) provides bidirectional access
to external Data Memory.
The bus structure supports:
• General register-to-register
• Register-to-memory
• Memory-to-register transfers
Each can transfer up to three 16-bit words in the same instruction cycle. Transfers between buses
are accomplished in the Bit Manipulation Unit (BMU). Table 1-2 lists the address and data buses
for the 56800 core.
Table 1-2. 56800 Address and Data Buses
Bus Bus Name Bus Width Direction Use
XAB1 X Address Bus 1 16-bit Unidirectional Internal and External Memory Address
XAB2 X Address Bus 2 16-bit Unidirectional Internal Memory Address
PAB Program Address Bus 16-bit Unidirectional Internal Memory Address
EAB External Address Bus 16-bit Unidirectional External Memory Address
CGDB Core Global Data Bus 16-bit Unidirectional Internal Data Movement
PDB Program Data Bus 16-bit Unidirectional Instruction Word Fetches
PGDB Peripheral Global Data Bus 16-bit Unidirectional Internal Data Movement
XDB2 X Data Bus 2 16-bit Unidirectional Internal Data Movement
EDB External Data Bus 16-bit Bidirectional External Data Movement
56F826/827 Overview, Rev. 3
Freescale Semiconductor 17
56F826/827 Features
1.7.6 On-Chip Emulation (OnCE) Module
The OnCE module allows interaction in a debug environment with the 56800 core and its
peripherals. Its capabilities include:
• Examining registers
• Setting breakpoints in memory
• Stepping or tracing instructions
It provides simple, inexpensive, and speed independent access to the 56800 core for sophisticated
debugging and economical system development. The JTAG port allows access to the OnCE
module, through the 56F826/827, to its target system where it retains debug control without
sacrificing other user accessible on-chip resources. This technique eliminates costly cabling and
the access to processor pins required by traditional emulator systems. The OnCE interface is
described in Chapter 16.
1.7.7 On-Chip Clock Synthesis (OCCS) Block
The Clock Synthesis module generates the clocking for the 56F826/827. It generates clocks used
by the 56800 core and 56F826/827 peripherals. The module contains a PLL capable of
multiplying up the frequency or being bypassed. A prescaler/divider distributes clocks to
peripherals and to lower power consumption on the 56F826/827. Further, the prescaler divider
selects which clock, if any, is routed to the CLKO pin of both chips.
1.7.8 Oscillators
The 56F826/827 are clocked either from an external crystal or external clock generator input. The
crystal oscillator uses a 4MHz crystal:
• Optionally, can use ceramic resonator in place of crystal
• Optionally, can be divided down by a programmable prescaler
1.7.9 Phase Locked Loop (PLL)
• The PLL will generate an interrupt to instruct the device to gracefully shutdown the
system in the event reference clock is stopped.
• The PLL is designed to run for at least 100 instruction cycles if the oscillator source is
removed.
• The PLL generates output frequencies up to 80MHz.
• The PLL can be bypassed to use an oscillator or prescalar outputs directly.
56F826/827 User Manual, Rev. 3
18 Freescale Semiconductor
56F826/827 Features
A clock gear shifter guarantees smooth transition from one clock source to the next during
normal operation. Clock sources available for Normal operation include:
• Prescaler output
• Postscaler output
• Programmable prescalar output, a divided down version of the oscillator clock— legal
divisors are one, two, four, or eight
1.7.10 Resets
• Integrated POR release occurs when VDD exceeds 1.8V.
• Integrated low voltage detector generates an interrupt when V
drops below 2.2V in the
DD
core or 2.7V in the I/O.
Note: Voltage level is designed to allow the host processor to continue running at speed.
There is nominally about 50mV of hysteresis present on each of the low voltage
interrupt inputs.
1.7.11 Energy Supply Voltages
Dual power supply:
• Chip I/O supply voltage = 3.3V
• Core voltage = 2.5V plus or minus 10 percent
1.7.12 IPBus Bridge
The IPBus Bridge converts Data Memory and interrupt interfaces to IPBus-compliant interfaces
for peripherals.
This IPBus Bridge permits communication between the core and peripherals, utilizing the CGDB
for data and XAB for addresses. All peripherals, except the COP/Watchdog Timer, and TOD
Timer run off the IPBus Clock. (The COP/Watchdog Timer runs at half of the system, or
processor frequency.) The IPBus is 40MHz while the oscillator frequency is 80MHz.
The IPBus Bridge translates the four-phase clock bus protocol of the 56800 core to the single
clock environment of the IPBus protocol used to communicate with the peripherals. All IPBus
transfers are completed in one core clock cycle.
Unaligned word,16-bit and byte, or long word 32-bit accesses are not supported on this IPBus.
The 56800 supports only 16-bit word transfers on word boundaries.
The IPBus Bridge also provides upper level address decoding and peripheral module enable
generation.
56F826/827 Overview, Rev. 3
Freescale Semiconductor 19
Memory Modules
1.8 Memory Modules
Harvard architecture permits as many as three simultaneous accesses to program and Data
Memory.
• On-chip memory, depending on specific chip selected
— 56F826
— 31.5K words of Program Flash
— 512 words of Program RAM
— 2K words of Data Flash
— 4K words of Data RAM
— 2K words of Boot Flash
— 56F827
— 63K words of Program Flash
—1K words of Program RAM
— 4K words of Data Flash
— 4K words of Data RAM
1.8.1 Program Flash
• Single port memory is compatible with the pipelined program bus structure
• Split-gate cell, NOR type structure
• Single-cycle reads at 40MHz
• Intelligent word programming feature
• Memory is organized into a two row information block (equals 64 bytes) and main
memory block
• Pages are 256 words long
• Intelligent page erase and mass erase modes
• Can be programmed and erased under software control
• Optional interrupt on completion of intelligent program and erase functions
1.8.2 Program RAM
• Single port RAM is compatible with the pipelined program bus structure
• Single cycle reads at 40MHz
56F826/827 User Manual, Rev. 3
20 Freescale Semiconductor
56F826/827 Peripheral Blocks
1.8.3 Data Flash
• Single port memory is compatible with the pipelined Data Bus structure
• Muxing allows this memory to be read from PAB, XAB1 or XAB2 databases
• Split-gate cell, NOR type structure
• Single-cycle reads at 40MHz across the automotive temperature range
• Intelligent word programming feature
• Intelligent page erase and mass erase modes
• Can be programmed under software control in the user’s system
1.8.4 Data RAM
• Single read, dual read, or single-write memory compatible with the pipelined data bus
structure
• Single cycle reads/writes at 40MHz
1.9 56F826/827 Peripheral Blocks
The 56F826/827 provides the following peripheral blocks:
• One 10-channel, 12-bit, ADC (56F827 only)
• Up to eight programmable chip select signals available (56F827 only)
• One general-purpose Quad Timer totaling four pins
• One dedicated SPI, plus a second multiplexed with two Serial Communications Interfaces
(SCI0 and SCI1) totaling four GPIO pins
• Up to three SCIs with two pins, or six additional GPIO pins (56F827 only)
• Two SPIs, SPI0 and SPI1, with configurable four-pin port
• The 56F827 also has a third SPI (SPI2) available as four additional GPIO pins
• One SSI with configurable six-pin port, or six additional GPIO lines
• Sixteen dedicated and 48 (56F826), or 64 (56F827) multiplexed GPIO pins
• A COP/Watchdog Timer
• Two external interrupt pins
• Eight-channel programmable chip selects (56F827 only)
• External RESET
pin for hardware reset
• JTAG/OnCE for unobtrusive, processor speed-independent debugging
• Software-programmable, PLL-based frequency synthesizer for the core clock
56F826/827 Overview, Rev. 3
Freescale Semiconductor 21
Peripheral Descriptions
• Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
• One TOD timer
1.10 Peripheral Descriptions
The IPBus Bridge converts Data Memory and interrupt interfaces to the IPBus-compliant
interface for peripherals. The IPBus Bridge permits communication between the core and
peripherals utilizing the CGDB for data and XAB for addresses.
Peripherals run off the IPBus clock at 40MHz. The IPBus clock frequency is half of the oscillator
frequency. Interrupt Priority Register (IPR) and BCR run at 80MHz while the COP/Watchdog
Timer runs at 40MHz.
1.10.1 External Memory Interface (EMI)
The 56F826/827 provide an External Memory Interface (EMI). This port provides a total of 36
pins—16 pins for an External Address Bus (EAB), 16 pins for an External Data Bus (EDB), and
four pins for bus control.
1.10.2 Programmable Chip Select
The primary function of the chip select is to provide the chip enable for external memory and
peripheral devices. All chip select pins are software programmable.
• 56F826
— No chip select
• 56F827
— Up to eight programmable chip select signal available
The programmable chip select provide the following features:
• Reduced system complexity
• Eight programmable active-low chip select
• Control for external boot device
• Programmable base addresses with programmable block sizes
• Maximum block size = 64K (16-bit) words
• Minimum block size = 0.5K (16-bit) words
• Wait states programmable through BCR register of DSP56800 core. Changing number of
wait states affects all chip select together.
• Each chip select can be assigned either program memory or Data Memory or both.
56F826/827 User Manual, Rev. 3
22 Freescale Semiconductor
Peripheral Descriptions
• All chip selects are assigned for both read/write.
• Each chip select can be individually enabled or disabled.
1.10.3 General-Purpose Input/Output Port (GPIO)
This port is configured to make it possible to generate interrupts when a transition is detected on
any of its lower eight pins.
• 56F826
— 32 shared GPIO pins, 48 when multiplexed with other peripherals
— 16 dedicated GPIO pins
• 56F827
— 48 shared GPIO pins, 64 when multiplexed with other peripherals
— 16 dedicated GPIO pins
— Each bit can be individually configured as an input or output
— Each bit can be configured as an interrupt input
1.10.4 Serial Peripheral Interface (SPI)
The SPI is an independent serial communications subsystem allowing 56F826/827
microcontrollers to communicate synchronously with peripheral devices such as LCD display
drivers, A/D subsystems, and MCU microprocessors. The SPI is also capable of interprocessor
communication in a multiple master system. The SPI system can be configured as either a master
or a slave device with high data rates. The SPI works in a demand-driven mode. In Master mode,
a transfer is initiated when data is written to the SPI Data register. In Slave mode, a transfer is
initiated by the reception of a clock signal.
• The 56F826 chip can be configured to have one or two SPIs; the 56F827 chip can be
configured to have up to three SPIs
• Full-duplex synchronous operation via four-wire interface
• Configurable for either master or slave operation
• Multiple slaves may be enabled using GPIO pins
• Double-buffered operation with separate Transmit and Receive registers
1.10.5 COP/Watchdog Timer and Modes of Operation Module
The COP module provides two separate functions:
56F826/827 Overview, Rev. 3
Freescale Semiconductor 23
Peripheral Descriptions
1. A Watchdog Timer
2. An interrupt generator
These two functions monitor processor activity and provide an automatic reset signal if a failure
occurs. Both functions are contained in the same block because the input clock for both comes
from a common clock divider:
• 12-bit counter to provide 4096 different timeout periods
• COP timebase is the CPU clock divided by 16384
• At 80MHz, minimum timeout period is 204.8
204.8
µs
µs, maximum is 839ms, with a resolution of
1.10.6 JTAG/OnCE Port
The JTAG/OnCE port introduces the 56F826/827 into a target system while retaining debug
control. The JTAG port provides board-level testing capability for scan-based emulation
compatible with the IEEE 1149.1a-1993 IEEE Standard Test Access Port and Boundary Scan
Architecture
Port (TAP) containing a 16-state controller.
The OnCE module interacts in a debug environment with the 56800 core and its peripherals
nonintrusively. Its capabilities include:
• Examining registers, memory, or on-chip peripherals
• Setting breakpoints in memory
• Stepping or tracing instructions
The OnCE module provides simple, inexpensive, and speed-independent access to the DSP56800
core for sophisticated debugging and economical system development. The JTAG/OnCE port
provides access to the OnCE module. Through the 56F80x to its target system, it retains debug
control without sacrificing other accessible on-chip resources.
specification defined by the JTAG. Five dedicated pins interface to a Test Access
1.10.7 Quad Timer Module (TMR)
• 56F826
— Timer A with four pins
• 56F827
— Timer A with four pins
Quad timer features:
• Four channels, independently programmable as input capture or output compare
56F826/827 User Manual, Rev. 3
24 Freescale Semiconductor
• Each channel has its own timebase
• Each of four channels can use any of four timer inputs
• Rising-edge, falling-edge, or any edge input capture trigger
• Set, clear, or toggle output capture action
• Programmable clock sources and frequencies, including external clock
• External synchronization input
1.10.8 Analog-to-Digital Converter (ADC)
• 56F826
— No ADC
• 56F827
— One 10 channel, 12-bit, ADC
1.10.9 Serial Communications Interface (SCI)
Peripheral Descriptions
• 56F826 (Two SCI maximum)
— Two optional SCIs, each with two pins, or one SPI
• 56F827 (Three SCI maximum)
— Two optional SCIs, each with two pins, or one SPI and
— One SCI with two pins (or two additional GPIO pins)
SCI features:
— Asynchronous operation
— Baud rate generation
— IR interface support
1.10.10 Synchronous Serial Interface (SSI)
The SSI is a full-duplex, serial port designed to allow the device to communicate with a variety of
serial devices, including industry-standard codecs, other hybrid controllers, microprocessors, and
peripherals to implement the Serial Peripheral Interface (SPI).
SSI features:
• SSI with configurable six-pin port (or six additional GPIO lines)
• Normal mode operation using frame sync
• Gated Clock mode operation requiring no frame sync
56F826/827 Overview, Rev. 3
Freescale Semiconductor 25
Peripheral Descriptions
• Program options for frame sync and clock generation
• Programmable word length from eight to 16 bits
1.10.11 Time-of-Day (TOD)
• 56F826/56F827
— Sequence counters to track seconds, minutes, hours, and days
— Works with crystal frequency of two to 4MHz
— Generates interrupt capability of pulling the part out of Sleep
— Capability to track time up to 179.5 years
— Configurable to generate an alarm at a designated time
1.10.12 Peripheral Interrupts
The peripherals on the 56F826/827 use the interrupt channels found on the 56800 core. Each
peripheral has its own interrupt vector, often more than one interrupt vector for each peripheral,
and can be selectively enabled or disabled via the IPR found on the 56800 core and the Priority
Level Registers (PLRs) found in the Interrupt Controller (ITCN). Chapter 5
details on interrupt vectors.
provides more
56F826/827 User Manual, Rev. 3
26 Freescale Semiconductor
Chapter 2
Pin Descriptions
Pin Descriptions, Rev. 3
Freescale Semiconductor 1
56F826/827 User Manual, Rev. 3
2 Freescale Semiconductor
Introduction
2.1 Introduction
The input and output signals of the 56F826/827 are organized into functional groups illustrated in
Table 2-1. Each row of Table 2-2 through Table 2-17 describes the signals present on an
individual pin. The 56F826/827 have SCI0 and SCI1 pins labeled TXD0, TXD1, RXD0 and
RXD1.
Note: Some pins can carry more than one signal, depending on chip configuration.
Table 2-1. 56F826/827 Functional Group Pin Allocations
826
Functional Group
Number
of Pins
Power (V
Ground (V
V
PP
, V
DD
DDIO, VDDA or VDDA_ADC
, V
SS
SSIO, VSSA, orVSSA_ADC
) (3,4,1,0) (3,5,1,1) Table 2-2
) (3,4,1,0) (3,5,1,1) Table 2-3
-1 Table 2-4
PLL and Clock 3 3 Table 2-5
Address Bus
Data Bus1
1
16 16 Table 2-6
16 16 Table 2-7
Bus Control 4 4 Table 2-8
Quad Timer Module Ports
1
44 Table 2-9
JTAG/On-Chip Emulation (OnCE) 6 6 Table 2-10
Dedicated General Purpose Input/Output 16 16 Table 2-11
Synchronous Serial Interface (SSI) Port
1
66 Table 2-12
827
Number
of Pins
Detailed Description
Serial Peripheral Interface (SPI) Port
1
Serial Communications Interface (SCI) Ports
Serial Communications Interface (SCI) Ports
1
2
44 Table 2-13
-2 Table 2-14
44 Table 2-15
ADC Port - 15 Table 2-16
Programmable Chip Select (PCS
3
)
-6 Table 2-17
Interrupt and Program Control 5 5 Table 2-18
1. Alternately, GPIO pins (56F826 SCIs cannot be used as GPIO)
2. Alternately, two SCIs can be used as an SPI
3. In addition, two Bus Control pins can be programmed as PCS [0-1]
Pin Descriptions, Rev. 3
Freescale Semiconductor 3
Introduction
2.5V Power
3.3V Analog Power
3.3V Power
Ground
Analog Ground
Ground
PLL
and
Clock
External
Address Bus or
GPIO
External Data
Bus
External
Bus Control
V
DD
V
DDA
V
DDIO
V
SS
V
SSA
V
SSIO
EXTAL
XTAL (CLOCKIN)
CLKO
A0-A7 (GPIOE)
A8-A15 (GPIOA)
D0–D15
PS
DS
WR
RD
3
1
4
4*
1
4
1
1
1
8
8
16
1
1
1
1
56F826
GPIOB0–7
8
GPIOD0–7
8
SRD (GPIOC0)
1
SRFS (GPIOC1)
1
SRCK (GPIOC2)
1
STD (GPIOC3)
1
STFS (GPIOC4)
1
STCK (GPIOC5)
1
SCLK (GPIOF4)
1
MOSI (GPIOF5)
1
MISO (GPIOF6)
1
SS
1
TXD0 (SCLK0)
1
RXD0 (MOSI0)
1
TXD1 (MISO0)
1
RXD1 (SS0
1
Dedicated
GPIO
SSI Port
or GPIO
SPI1 Port
or GPIO
(GPIOF7)
SCI0, SCI1
Port or
SPI0 Port
)
Quad Timer A
or GPIO
JTAG/OnCE™
Port
TA0 (GPIOF0)
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
TCK
TMS
TDI
TDO
TRST
DE
1
1
1
1
1
1
1
1
1
1
*Includes TCS pin, which is reserved for factory use and is tied to V
Figure 2-1. 56F826 Functional Group Pin Allocations
1.Alternate pin functionality is shown in parentheses
56F826/827 User Manual, Rev. 3
IRQA
1
IRQB
1
RESET
1
EXTBOOT
1
SS
Interrupt/
Program
Control
1
4 Freescale Semiconductor
Introduction
2.5V Power
3.3V Analog Power
3.3V Analog Power
3.3V Power
Ground
Analog Ground
Analog Ground
Other
Supply Port
PLL
and
Clock
External
Address Bus or
GPIO
External Data
Bus or GPIO
External
Bus Control
Quad Timer A
or GPIO
JTAG/OnCE™
Port
V
DD
V
DDA
V
DDA_ADC
V
DDIO
V
V
SSA
V
SSA_ADC
V
SSIO
V
EXTAL
XTAL (CLOCKIN)
CLKO
A0-A15(GPIOA0–15)
D0–D15(GPIOG0-15)
PS
(PCS0)
DS
(PCS1)
WR
RD
TA0 (GPIOF0)
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
TCK
TMS
TDI
TDO
TRST
DE
SS
PP
3
1
1
5
4*
1
1
5
1
1
1
1
16
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
56F827
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
10
1
1
1
1
1
1
1
1
1
GPIOB0–7
GPIOD0–7
SRD (GPIOC0)
SRFS (GPIOC1)
SRCK (GPIOC2)
STD (GPIOC3)
STFS (GPIOC4)
STCK (GPIOC5)
SCLK (GPIOF4)
MOSI (GPIOF5)
MISO (GPIOF6)
SS (GPIOF7)
TXD0 (SCLK0)
RXD0 (MOSI0)
TXD1 (MISO0)
RXD1 (SS0
)
TXD2 (GPIOC6)
RXD2 (GPIOC7)
2-7
PCS
ANA0–9
VREFN
VREFP
VREFMID
VREFLO
VREFHI
IRQA
IRQB
RESET
EXTBOOT
Dedicated
GPIO
SSI Port
or GPIO
SPI1 Port
or GPIO
SCI0,SCI1
Port or
SPI0 Port
SCI2 Port
or GPIO
Programmable
Chip Select
ADC
Port
Interrupt/
Program
Control
*Includes TCS pin, which is reserved for factory use and is tied to VSS
Figure 2-2. 56F827 Functional Group Pin Allocations
1
1.Alternate pin functionality is shown in parentheses
Pin Descriptions, Rev. 3
Freescale Semiconductor 5
Power and Ground Signals
2.2 Power and Ground Signals
Table 2-2. Power Inputs
No. of
Pins
826 827
Signal Name Signal Description
33 V
DD
Power—These pins provide power to the core of the chip, are generally
connected to a 2.5V supply.
11 V
DDA
Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low-noise 3.3V supply.
01 V
DDA_ADC
Analog Power—This pin is a dedicated power pin for the analog portion of the
ADC module and should be connected to a low-noise 3.3V supply.
45 V
DDIO
Power In/Out—These pins provide power to the I/O structures of the chip, and
are generally connected to a 3.3V supply.
Note: Analog pins must be connected to a power source.
Table 2-3. Grounds
No. of
Pins
826 827
33 VSS GND—These pins provide grounding for the internal structures of the chip and
11 V
Signal Name Signal Description
SSA
should all be attached to V
Analog Ground—This pin supplies an analog ground.
SS.
—1 V
SSA_ADC
Analog Ground—This pin is a dedicated ground pin for the analog portion of the
ADC module.
45 V
SSIO
11 TCS TCS—This pin is reserved for factory use. It must be tied to V
GND In/Out—These pins provide grounding for the I/O ring on the chip. All
should be attached to V
In block diagrams, this pin is considered an additional V
SS.
SS
for normal use.
SS
.
Signal Type is Input/Output (Schmitt).
56F826/827 User Manual, Rev. 3
6 Freescale Semiconductor
No. of
Pins
826 827
Clock and Phase Lock Loop Signals
Table 2-4. Other Supply Port
Signal Name Signal Description
—1 V
PP
VPP—This pin should be left unconnected as an open circuit for normal
functionality.
2.3 Clock and Phase Lock Loop Signals
Table 2-5. PLL and Clock
No. of
Pins
826 827
11 EXTAL Input Input External Crystal Oscillator Input—This input should be
11 XTAL
Signal
Name
(CLOCKIN)
Signal
Type
Input
Input
State
During
Reset
Chip-
driven
Input
Signal Description
connected to a 4MHz external crystal or ceramic resonator. For
additional information, please refer to section 4.5.2.
Crystal Oscillator Output—This output connects the internal
crystal oscillator output to an external crystal. If an external
clock source other than a crystal oscillator is used, XTAL must
be used as the input and EXTAL connected to V
additional information, please refer to section 4.5.1.
External Clock Input—This input should be asserted when
using an external clock or ceramic resonator.
DDA
/2. For
11 CLKO Output Chip-
driven
Freescale Semiconductor 7
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKO Select Register (CLKOSR), the user
can select between outputting a version of the signal applied to
XTAL and a version of the device master clock at the output of
the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
Pin Descriptions, Rev. 3
Address, Data, and Bus Control Signals
2.4 Address, Data, and Bus Control Signals
Table 2-6. Address Bus Signals
No. of
Pins
826 827
8— A0–A7
8— A8-15
—16 A0-15
Signal
Name
(GPIOE0-7)
(GPIOA8-15)
(GPIOA0-15)
Signal
Type
Output
Input/
Output
Output
Input/
Output
Output
Input/
Output
State
During
Reset
Tri-stated Address Bus—A0–A7 specify the address for external program
or data memory accesses.
Port E GPIO—These eight General Purpose I/O (GPIO) pins
can be individulally programmed as input or output pins.
After reset, the default state is Address Bus.
Tri-stated Addressd Bus—A8-A15 specify the address for external
program or data memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins
can be individulally programmed as input or output pins.
After reset, the default state is Address Bus.
Tri-stated Address Bus—A0-A15 specify the address for external
program or data memory accesses.
Port A GPIO—These 16 General Purpose I/O (GPIO) pins can
be individulally programmed as input or output pins.
Signal Description
No. of
Pins
826 827
16 — D0–D15 Input/
—16 D0–D15
Signal
Name
(GPIOG0-15)
Signal
Type
Output
Input/
Output
Input/
Output
After reset, the default state is Address Bus.
Table 2-7. Data Bus Signals
State
During
Reset
Tri-stated Data Bus—D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the external
bus is inactive.
Tri-stated Data Bus—D0-D15 specify the address for external Program
or Data memory accesses.
Port G GPIO—These 16 General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Signal Description
56F826/827 User Manual, Rev. 3
8 Freescale Semiconductor
Table 2-8. Bus Control Signals
Address, Data, and Bus Control Signals
No. of
Pins
826 827
1— PS
—1 PS
1— DS Output Tri-stated
—1 DS
11 WR Output Tri-stated
Signal
Name
Signal
Type
Output Tri-stated
Output Tri-stated
Output Tri-stated
State
During
Reset
Signal Description
Program Memory Select—PS
program memory access.
Program Memory Select—PS
program memory access. This pin can also be programmed as
a programmable chip select.
Data Memory Select—DS
memory access.
Data Memory Select—DS
memory access. This pin can also be programmed as a
programmable chip select.
Write Enable—WR
cycles. When WR
outputs and the device puts data on the bus. When WR
deasserted high, the external data is latched inside the external
device. When WR
DS
pins. WR can be connected directly to the WE pin of a
Static RAM.
is asserted during external memory write
is asserted low, pins D0–D15 become
is asserted, it qualifies the A0–A15, PS, and
is asserted low for external
is asserted low for external
is asserted low for external data
is asserted low for external Data
is
11 RD
Output Tri-stated
Read Enable—RD
cycles. When RD
and an external device is enabled onto the device data bus.
When RD is deasserted high, the external data is latched inside
the device. When RD
and DS
Static RAM or ROM.
pins. RD can be connected directly to the OE pin of a
is asserted during external memory read
is asserted low, pins D0–D15 become inputs
is asserted, it qualifies the A0–A15, PS,
Pin Descriptions, Rev. 3
Freescale Semiconductor 9
Quad Timer Module Signals
2.5 Quad Timer Module Signals
Table 2-9. Quad Timer Module Signals
No. of
Pins
826 827
44 TA0-3
Signal
Name
(GPIOF0-
GPIOF3)
Signal
Type
Input/
Output
Input/
Output
State
During
Reset
Input
Input
2.6 JTAG/OnCE Port Signals
Table 2-10. JTAG/OnCE Port Signals
No. of Pins
826 827
11 TCK Input
Signal
Name
Signal
Type
(Schmitt)
(Input/
Output)
State During
Reset
Input, pulled
low internally
Signal Description
–3—Timer A Channels 0, 1, 2, and 3
TA0
Port F GPIO—These four General Purpose I/O (GPIO) pins
can be individually programmed as input or output.
After reset, the default state is Quad Timer.
Signal Description
Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
11 TMS Input
(Schmitt)
(Input/
Output)
11 TDI Input
(Schmitt)
(Input/
Output)
11 TDO Output
(Schmitt)
(Input/
Output)
Input, pulled
high
internally
Input, pulled
high
internally
Tri-stated Test Data Output—This tri-statable output pin provides a serial
Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
output data stream from the JTAG/OnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
56F826/827 User Manual, Rev. 3
10 Freescale Semiconductor
Table 2-10. JTAG/OnCE Port Signals (Continued)
Synchronous Serial Interface
No. of Pins
826 827
11TRST Input
11 DE
Signal
Name
Signal
Type
(Schmitt)
(Input/
Ouput)
Output Output Debug Event—DE provides a low pulse on recognized debug
State During
Reset
Input, pulled
high
internally
Test Reset—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted.
The only exception occurs in a debugging environment, since the
OnCE/JTAG module is under the control of the debugger. In this
case it is not necessary to assert TRST
Outside of a debugging environment TRST
permanently asserted by grounding the signal, thus disabling the
OnCE/JTAG module on the device.
events.
2.7 Synchronous Serial Interface
Table 2-11. Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins
826 827
Signal
Name
Signal
Type
State
During
Reset
Signal Description
when asserting RESET.
should be
Signal Description
88GPIOB0–
GPIOB7
88GPIOD0–
GPIOD7
Input/
Output
Input/
Output
Input Port B GPIO—These eight dedicated General Purpose I/O
(GPIO) pins can be individually programmed as input or output
pins.
After reset, the default state is GPIO input.
Input Port D GPIO—These eight dedicated General Purpose I/O
(GPIO) pins can be individually programmed as input or output
pins.
After reset, the default state is GPIO input.
Pin Descriptions, Rev. 3
Freescale Semiconductor 11
Synchronous Serial Interface
Table 2-12. Synchronous Serial Interface (SSI) Signals
No. of
Pins
826 827
11 SRD
11 SRFS
11 SRCK
Signal
Name
(GPIOC0)
(GPIOC1)
Signal
Type
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
State
During
Reset
Input
Input
Input
Input
Input
Signal Description
SSI Receive Data (SRD)—This input pin receives serial data
and transfers the data to the SSI Receive Shift Receiver.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with
the capability of being individually programmed as input or
output.
After reset, the default state is GPIO input.
SSI Serial Receive Frame Sync (SRFS)—This bidirectional
pin is used by the receive section of the SSI as frame sync I/O
or flag I/O. The STFS can be used only by the receiver. It is
used to synchronize data transfer and can be an input or an
output.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with
the capability of being individually programmed as input or
output.
After reset, the default state is GPIO input.
SSI Serial Receive Clock (SRCK)—This bidirectional pin
provides the serial bit rate clock for the Receive section of the
SSI. The clock signal can be continuous or gated and can be
used by both the transmitter and receiver in synchronous
mode.
(GPIOC2)
11 STD
(GPIOC3)
Input/
Output
Output
Input/
Output
Input
Input
Input
56F826/827 User Manual, Rev. 3
Port C GPIO—This is a General Purpose I/O (GPIO) pin with
the capability of being individually programmed as input or
output.
After reset, the default state is GPIO input.
SSI Transmit Data (STD)—This output pin transmits serial
data from the SSI Transmitter Shift Register.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with
the capability of being individually programmed as input or
output.
After reset, the default state is GPIO input.
12 Freescale Semiconductor
Synchronous Serial Interface
Table 2-12. Synchronous Serial Interface (SSI) Signals (Continued)
No. of
Pins
826 827
11 STFS
11 STCK
Signal
Name
(GPIOC4)
(GPIOC5)
Signal
Type
Input
Input/
Output
Input/
Output
Input/
Output
State
During
Reset
Input
Input
Input
Input
Signal Description
SSI Serial Transmit Frame Sync (STFS)—This bidirectional
pin is used by the Transmit section of the SSI as frame sync I/O
or flag I/O. The STFS can be used by both the transmitter and
receiver in synchronous mode. It is used to synchronize data
transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with
the capability of being individually programmed as input or
output.
After reset, the default state is GPIO input.
SSI Serial Transmit Clock (STCK)—This bidirectional pin
provides the serial bit rate clock for the transmit section of the
SSI. The clock signal can be continuous or gated. It can be
used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with
the capability of being individually programmed as input or
output.
After reset, the default state is GPIO input.
Pin Descriptions, Rev. 3
Freescale Semiconductor 13
Serial Peripheral Interface (SPI) Signals
2.8 Serial Peripheral Interface (SPI) Signals
Table 2-13. Serial Peripheral Interface (SPI1) Signals
No. of
Pins
826 827
11 SCLK
11 MOSI
11 MISO
Signal
Name
(GPIOF4)
(GPIOF5)
Signal
Type
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
State
During
Reset
Input
Input
Input
Input
Input
Signal Description
SPI Serial Clock—In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as input or output.
After reset, the default state is SCLK.
SPI Master Out/Slave In (MOSI)—This serial data pin is an
output from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle before
the clock edge that the slave device uses to latch the data.
Port F GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as input or output.
SPI Master In/Slave Out (MISO)—This serial data pin is an
input to a master device and an output from a slave device. The
MISO line of a slave device is placed in the high-impedance
state if the slave device is not selected.
(GPIOF6)
11 SS
GPIOF7
Input/
Output
Inputt/
Output
Input/
Output
Input
Input
Input
Port F GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as input or output.
After reset, the default state is MISO.
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the
slave.
Port F GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as input or output.
After reset, the default state is SS
.
56F826/827 User Manual, Rev. 3
14 Freescale Semiconductor
Serial Communications Interface (SCI) or General Purpose Input/Output (GPIO) Signals (56F827 only)
2.9 Serial Communications Interface (SCI) or Serial Peripheral Interface (SPI0) Signals
Table 2-14. Serial Communications Interface (SCI0 & SCI1) Signals
No. of
Pins
826 827
11 TXD0
11RXD0
11 TXD1
Signal
Name
(SCLK0)
(MOSI0)
(MISO0)
Signal
Type
Output
Input/
Output
Input
Input/
Output
Output
Input/
Output
State
During
Reset
Input
Input
Input
Input
Input
Input
Signal Description
Transmit Data (TXD0)—transmit data output
SPI Serial Clock—In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.
After reset, the default state is SCI output.
Receive Data (RXD0)— receive data input.
SPI Master Out/Slave In—This serial data pin is an output
from a master device, and an input to a slave device. The
master device places data on the MOSI line one half-cycle
before the clock edge the slave device uses to latch the data.
After reset, the default state is SCI input.
Transmit Data (TXD1)—transmit data output.
SPI Master In/Slave Out—This serial data pin is an input to a
master device and an output from a slave device. The MISO
line of a slave device is placed in the high-impedance state if
the slave device is not selected.
After reset, the default state is SCI output.
11RXD1
(SS0
)
Input
(Schmitt)
Input
Input
Input
Receive Data (RXD1)— receive data input
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the
slave.
After reset, the default state is SCI input.
2.10 Serial Communications Interface (SCI) or
General Purpose Input/Output (GPIO) Signals
Pin Descriptions, Rev. 3
Freescale Semiconductor 15
Analog-to-Digital Converter (ADC) Signals (56F827 only)
(56F827 only)
Table 2-15. Serial Communications Interface (SCI2) Signals
No. of
Pins
826 827
—1 TXD2
—1 RXD2
Signal
Name
(GPIOC6)
(GPIOC7)
Signal
Type
Output
Input/
Output
Input/
Output
Input/
Output
State
During
Reset
Input
Input
Input
Input
Signal Description
Transmit Data (TXD2)—transmit data output
Port C GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as input or output.
After reset, the default state is GPIO output.
Receive Data (RXD2)— receive data input
Port C GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as input or output.
After reset, the default state is GPIO input.
2.11 Analog-to-Digital Converter (ADC) Signals (56F827 only)
Table 2-16. Analog-to-Digital Converter Signals
No. of
Pins
826 827
—10 ANA0-9 Input Input
—1 VREFP Input Output
—1VREFMID Input Output
—1 VREFN Input Output
—1 VREFHI Input Input
Signal
Name
Signal
Type
State
During
Retset
Signal Description
ANA0-9—Analog inputs to ADC
ADC Reference—The VREFP pin is connected to the positive
side of the ADC range. This pin requires a 0.1µF ceramic
capacitor to V
beginning conversions.
ADC Reference—The VREFMID pin is connected to the
center of the ADC input range. This pin requires a 0.1µF
ceramic capacitor to V
beginning conversions.
ADC Reference—The VREFN pin is connected to the negative
side of the ADC input range. This pin requires a 0.1µF ceramic
capacitor to V
beginning conversions.
ADC Reference—These pins are Positive Reference for ADC
and are generally connected to a 3.3V Analog (V
supply.
and a start-up time of 25ms, prior to
SSA
and a start-up time of 25ms, prior to
SSA
and a start-up time of 25ms, prior to
SSA
DDA_ADC
)
56F826/827 User Manual, Rev. 3
16 Freescale Semiconductor
Programmable Chip Select Signals (56F827 only)
Table 2-16. Analog-to-Digital Converter Signals
No. of
Pins
826 827
—1 VREFLO Input Input
Signal
Name
Signal
Type
State
During
Retset
Signal Description
ADC Reference—These pins are Negative Reference for ADC
and are generally connected to a V
SSA
.
2.12 Programmable Chip Select Signals (56F827 only)
Table 2-17. Programmable Chip Selects
No. of
Pins
826 827
—6 PCS
Signal
Name
Signal
Type
2-7 Input/
Output
State
During
Reset
Tri-stated Programmable Chip Select - PCS2-7 are asserted low for
external peripheral chip select
Signal Description
Pin Descriptions, Rev. 3
Freescale Semiconductor 17
Interrupt and Program Control Signals
2.13 Interrupt and Program Control Signals
Table 2-18. Interrupt and Program Control Signals
No. of Pins
826 827
11 IRQA
11 IRQB Input
11RESET
Signal
Name
Signal
(Schmitt)
(Schmitt)
(Schmitt)
Type
Input
Input
State
During
Reset
Input External Interrupt Request A—The IRQA input is a
synchronized external interrupt request indicating an external
device is requesting service. It can be programmed to be
level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA
processor will exit the Stop state.
Input External Interrupt Request B—The IRQB input is an external
interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered. If level-sensitive triggering is selected,
an external pull-up resistor is required for wired-OR operation.
Input Reset—This input is a direct hardware reset on the processor.
When RESET
in the Reset state. A Schmitt trigger input is used for noise
immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the external boot pin. The internal
reset signal will be deasserted synchronous with the internal
clocks, after a fixed number of internal clocks.
is asserted low, the device is initialized and placed
Signal Description
is asserted, the
11EXTBOOT Input
(Schmitt)
To ensure complete hardware reset, RESET and TRST should
be asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
Input External Boot—This input is tied to V
from off-chip memory. Otherwise, it is tied to ground.
to force device to boot
DD
56F826/827 User Manual, Rev. 3
18 Freescale Semiconductor
Chapter 3
Memory and Operating Modes
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 1
56F826/827 User Manual, Rev. 3
2 Freescale Semiconductor
The 56F826/827 Memory Map Description
3.1 Introduction
Devices 56F826 and 56F827 are members of the 56F800 Family core-based hybrid controllers.
Both combine the processing power and the functionality of a microcontroller with a flexible set
of peripherals on a single chip. Because of their low cost, configuration flexibility and compact
program code, both chips are well suited for many applications.
3.2 The 56F826/827 Memory Map Description
The 56F826/827 uses two independent memory spaces:
1. Data
2. Program
Both memory spaces use Harvard-style architecture. RAM and Flash memory are used for the
on-chip data and on-chip program memories.
Table 3-1. Chip Memory Configurations
On-Chip Memory 56F826 56F827
Program Flash (PFLASH) 31.5K x 16 63K x 16
Data Flash (XFLASH) 2K x 16 4K x 16
Program RAM (PRAM) 512 x 16 1K x 16
Data RAM (XRAM) 4K x 16
Program Boot Flash 2K x 16
—
On-chip memory sizes for each of the parts are summarized in Table 3-1. Both Program and Data
Memories can be expanded off-chip. The Program Memory map is located in Table 3-2. The
Operating Mode control bits (MA and MB) in the Operating Mode Register (OMR), coupled
with the BOOTMAP
bit in the SYS_CNTL register, control the Program Memory Map and select
the vector address. For additional information about the SYS_CNTL register, please see
Figure 15-8 and Section 15.8 in its entirety.
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 3
The 56F826/827 Memory Map Description
Table 3-2. Program Memory Map for 56F826/827
Begin/
End Address
0000
0003
0004
7BFF
7C00
7DFF
7E00
7FFF
8000
87FF
8800
FFFF
In all modes except Mode 3, the first four logical addresses of the 56F826 mirror the first four physical addresses of boot
flash, which provides interrupt vectors for hardware reset and COP (Watchdog Timer) reset. This is largely an academic
point in Mode 0B, as any reset or COP reset changes the memory map back to Mode 0A.
Mode 0A Mode 0B
826 827 826 827
BFlash 4 PFlash
31K
PFlash
31.5K-4
PRAM
1K
PRAM
0.5K
BFlash 2K PFlash
32K
Reserved
PFlash
31.5K
P. RAM
0.5K
External
Program
Memory
32K
PFlash
31K
PRAM
1K
External
Program
Memory
32K
Mode 3
External
Program
Memory
64K
Note: Modes 0A and 0B are supported in this group of devices. For more information about
other modes, please see Section 3.7.2 and Section 3.7.3.
56F826/827 User Manual, Rev. 3
4 Freescale Semiconductor
Table 3-3. Data Memory Map for 56F826/827
Data Memory
Begin/End
Address
0000
0FFF
1000
13FF
1400
17FF
1800
1FFF
2000
2FFF
3000
3FFF
4000
FF7F
FF80
FFFF
EX = 0
826 827
XRAM
4K
On-Chip
Peripheral
Registers
Reserved
XFlash
2K
External Data
Memory
56K -128
On-Chip Core Configuration Registers
XRAM
4K
On-Chip
Peripheral
Registers
Reserved
XFlash
4K
Reserved
External Data
Memory
48K -128
EX = 1
826 and 827
External Data
Memory
64K
When EX = 1, all 64K address space is external, unless I/O short addressing is used. If I/O short addressing is used, then
the on-chip core configuration registers become available.
Note: Table 3-3 summarizes the Data Memory map. The External X memory control bit
(EX) in the Operating Mode Register (OMR) controls the Data Memory map.
3.3 Data Memory
The 56F826 part has 4K words of on-chip Data RAM and 2K words of Data Flash. The 56F827
also has 4K words of on-chip Data RAM; and 4K words of Data Flash.
The 128-Data Memory addresses at the top of the memory map ($FF80 to $FFFF) are reserved
for 56800 on-chip core configuration registers. When EX=0, the internal Data Memory map is
enabled. When EX=1, the segment (hole) does not exist and may be accessed like all other
external data memory.
Note: For 56800 core instructions performing two reads from the data memory in a single
instruction, the second access using the R3 pointer always occurs to on-chip memory,
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 5
Data Memory
regardless how the OMR’s EX bit is programmed. For example, the second read of the
following code sequence accesses on-chip X data memory X:$0:
MOVE #$0000,R3
NOP
MOVE X:(R1)+,Y0 X:(R3)+,X0
Data Memory may be expanded off-chip for both the 56F826 and 56F827. When the OMR EX
bit is programmed with 1, there are 65,536 addressable off-chip data memory locations.
When the EX bit is set, the on-chip core configuration registers may only be accessed using the
I/O Short Addressing mode.
The External Data Memory bus access time is controlled by four bits of the Bus Control Register
(BCR) located at X:$FFF9. This register is illustrated in Figure .
The External X bit (EX, bit three) of the OMR in the 56800 core, determines the mapping of the
Data Memory, illustrated in Table 3-3. Setting the EX bit to 1 completely disables the on-chip
data memory and enables a full 64K External Data Memory map.
Note: There are two exceptions to this rule.
1. The first exception is if a MOVE, TSTW, or BIT FIELD instruction is used with the I/O
Short Addressing mode, the EX bit is ignored. This allows the on-chip core control
registers to be accessed when the EX bit is set. Access time to external memory is always
controlled by the BCR register or it wouldn’t be possible to read/write to non-zero wait
state external memory when EX = 0.
2. The second exception is for instructions performing two reads from the Data Memory in a
single cycle. The EX bit is ignored during the second access using the R3 pointer.
A complete description of the Operating Mode Register (OMR) is provided in DSP56800 Family
Manual.
3.3.1 Bus Control Register (BCR)
BCR–X:$FFF9
Read 0 0 0 0 0 0
Write
Reset 0 000000011001100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
DRV
WAIT STATE FIELD for
EXTERNAL X-MEMORY
WAIT STATE Field for
EXTERNAL P-MEMORY
Figure 3-1. Bus Control Register (BCR)
See Programmer’s Sheet on Appendix page C-19
56F826/827 User Manual, Rev. 3
6 Freescale Semiconductor
Data Memory
3.3.1.1 Reserved—Bits 15–10
This bit field is reserved or not implemented. It is read/written as 0.
3.3.1.2 Drive (DRV)—Bit 9
The Drive Control bit is used to specify what occurs on the external memory port pins when no
external access is performed—whether the pins remain driven or are tri-stated. The Drive (DRV)
bit is cleared on hardware reset. Please see Table 3-4 and 3-5.
Table 3-4. Port A Operation with DRV Bit = 0
Mode Pins
A0
–A15
Normal Mode, External Access Driven Driven Driven
Normal Mode, Internal Access Tri-Stated Tri-Stated Tri-Stated
Stop Mode Tri-Stated Tri-Stated Tri-Stated
Wait Mode Tri-Stated Tri-Stated Tri-Stated
Reset Mode Tri-Stated Pulled High Internally Tri-Stated
, DS, RD, WR
PS
D0–D15
Table 3-5. Port A Operation with DRV = 1
Mode Pins
–A15
A0
Normal Mode, External Access Driven Driven Driven
Normal Mode, Internal Access Driven Driven Tri-Stated
Stop Mode Driven Driven Tri-Stated
Wait Mode Driven Driven Tri-Stated
Reset Mode Tri-stated Pulled high internally Tri-stated
, DS, RD, WR
PS
3.3.1.3 Reserved—Bit 8
This bit field is reserved or not implemented. It is read/written as 0.
D0–D15
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 7
Data Memory
3.3.1.4 Wait State Data Memory (WSX[3:0])—Bits 7–4
These bits provide programming of the wait states for External Data Memory. The bottom two
bits, five and four, are hardcoded to zero. The WSX[3:0] bits are programmed as illustrated in
Table 3-6.
Table 3-6. Programming WSX[3:0] Bits for Wait States
Bit String Hex Value
0000 $0 0
0100 $4 4
1000 $8 8
1100 $C 12
All Others Illegal
Number of Wait
States
These bits allow programming of the wait states for external program memory. The bottom two
bits, one and zero, are hardcoded to zero. The WSP[3:0] bits are programmed as illustrated in
Table 3-7.
Table 3-7. Programming WSP [3:0] Bits for Wait States
Bit String Hex Value
0000 $0 0
0100 $4 4
1000 $8 8
1100 $C 12
All Others Illegal
Number of Wait
States
3.3.2 Operating Mode Register (OMR)
Bits
Read
Write
Reset 0 0000000000000
* MA and MB are latched from the EXTBOOT pin on reset.
8 Freescale Semiconductor
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0
NL
CC
0
SD R SA EX
0
MB MA
**
Figure 3-2. Operating Mode Register (OMR)
See Programmer’s Sheet on Appendix page C-20
56F826/827 User Manual, Rev. 3
Data Memory
3.3.2.1 Nested Looping (NL)—Bit 15
The Nested Looping (NL) bit displays the status of program DO looping and the Hardware Stack
(HWS). When the NL bit is set, it indicates the program is currently in a nested DO loop. That is,
two DO loops are active. When the NL bit is cleared, it indicates the program is currently not in a
nested DO loop. There may be a single active DO loop or no DO loop active. This bit is
necessary for saving and restoring the contents of the hardware stack. REP looping does not
affect this bit.
It is important to never put the processor in the reserved combination as specified in Table 3-8.
This can be avoided by ensuring the Loop Flag (LF) bit is never cleared when the NL bit is set.
The NL bit is cleared on processor reset.
Table 3-8. Looping Status
NL (In OMR) LF (in SR) DO Loop Status
0 0 No DO loops active
0 1 Single DO loop active
10
1 1 Two DO loops active
Reserved
If both the NL and LF bits are set, that is: two DO loops are active and a DO instruction is
executed, a Hardware Stack Overflow Interrupt occurs. The overflow occurs because space in the
Hardware Stack was used, therefore not supporting a third DO loop.
The NL bit is also affected by any accesses to the HWS. Any move instruction writing to the
HWS register should include copying the old contents of the LF bit into the NL bit. Before
clearing the NL bit, its value should be moved into the LF bit (NL
→LF, 0 → NL). For more detail
on the interaction between NL, LF and HWS, please see Section 5.1.7, Hardware Stack, in the
DSP56800 Family Manual and the DO and ENDDO instructions described in Appendix A,
Instruction Set Details, in the DSP56800 Family Manual.
3.3.2.2 Reserved—Bits 14–9
This bit field is reserved or not implemented. It is a read/write field using 0.
3.3.2.3 Condition Codes (CC)—Bit 8
The Condition Code (CC) bit is set if the code is generated using a 36-bit result from the
Multiplier/Accumulator (MAC) array, or a 32-bit result. When the CC bit is set, the C, N, V, and
Z condition codes are generated based on bit 31of the Data Arithmetic Logic Unit (Data ALU)
result. When cleared, the C, N, V, and Z condition codes are generated based on bit 35 of the data
ALU result. The generation of the L, E, and U condition codes is not affected by the CC bit. The
CC bit is cleared by the processor reset.
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 9
Data Memory
Note: The unsigned condition tests for branching or jumping (HI, HS, LO, or LS) can be
used only when the condition codes are generated with the CC bit set. Otherwise, the
chip does not generate the unsigned conditions correctly.
For more detail on the effects of the CC bit on condition codes generated by the data ALU
operators, see Section 3.6, Condition Code Generation, in the DSP56800 Family Manual.
3.3.2.4 Reserved—Bit 7
This bit field is reserved or not implemented. It is a read/write field using 0.
3.3.2.5 Stop Delay (SD)—Bit 6
The Stop Delay (SD) bit selects the delay required by the device to exit the Stop mode. When set,
the processor quickly exits from Stop mode. When the SD bit is cleared, the processor exits
slowly from Stop mode. The SD bit is cleared by processor reset.
3.3.2.6 Rounding (R)—Bit 5
The Rounding (R) bit selects between two’s-complement rounding and convergent rounding.
When the R bit is set, two’s-complement rounding is used. Rounding is always up. Cleared, the R
bit uses convergent rounding. The R bit is cleared by processor reset.
3.3.2.7 Saturation (SA)—Bit 4
The Saturation (SA) bit enables automatic saturation on 32-bit arithmetic results, providing a
user-enabled Saturation mode for those algorithms not able to exploit the four extra bits of A and
B accumulators. When the SA bit is set the accumulators behave as output as if they were only 32
bits wide. The SA bit is cleared by processor reset.
When the SA bit is set automatic saturation occurs at the output of the MAC unit for basic
arithmetic operations. Those basic arithmetic operations are of course, multiplication, addition,
and so on. The saturation is performed by a special saturation circuit inside the MAC unit.
The saturation logic operates by checking three bits of the 36-bit result out of the MAC
unit—exp[3], exp[0], and msp[15]. (The MSB and LSB of the extension register, EXP[3],
EXP[0], and the MSB of the AI register AI[15],
When the SA bit is set, three bits determine if saturation is performed on the MAC unit’s output
and whether to saturate to the maximum positive or negative value, as illustrated in Table 3-9.
56F826/827 User Manual, Rev. 3
10 Freescale Semiconductor
Table 3-9. MAC Unit Outputs With Saturation Mode Enabled (SA=1)
EXP[3] EXP[0] AI[15] Result Stored in Accumulator
0 0 0 (Unchanged)
0 0 1 $0 7FFF FFFF
0 1 0 $0 7FFF FFFF
0 1 1 $0 7FFF FFFF
1 0 0 $F 8000 0000
1 0 1 $F 8000 0000
1 1 0 $F 8000 0000
1 1 1 (Unchanged)
Note: The Saturation mode is always disabled during the execution of the following
instructions: ASLL, ASRR, LSLL, LSRR, ASRAC, LSRAC, IMPY16, MPYSU,
MACSU, OR, EOR, NOT, LSL, LSR, ROL, AND, ROR. For these instructions, no
saturation is performed at the output of the MAC unit.
3.3.2.8 External X Memory (EX)—Bit 3
Data Memory
Setting the External X (EX) memory bit forces all primary data memory accesses to be external.
When the EX bit is set, all accesses to X memory on the X Address Bus One (XAB1) and Core
Global Data Bus (CGDB) or Peripheral Global Data Bus (PGDB) are forced to be external except
using the I/O Short Addressing mode. In this case, the EX bit is ignored and the access is
performed to the on-chip location. When the EX bit is cleared, internal X memory can be
accessed with all addressing modes.
The EX bit is cleared by processor reset. The EX bit is ignored by the second read of a dual-read
instruction (using the X Address Bus Two (XAB2) and X Data Bus Two (XDB2)). For
instructions with two parallel reads, the second read is always performed to internal on-chip
memory.
Note: When the EX bit is set, only the upper 64-peripheral memory-mapped locations are
accessible (X:$FFCO-x:$FFFF) with the I/O Short Addressing mode. The lower
64-memory-mapped locations (X:$FF80
–$FFBF) are not accessible when the EX bit is
set. Access to these addresses results in an entree to external memory. Operating Mode
B (MB)—Bit 1.
This bit is latched from the EXTBOOT pin on reset. Please see Section 3.7 in the DSP56800
Family Manual.
3.3.2.9 Reserved—Bit 2
This bit field is reserved or not implemented. It is a read/write field using 0.
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 11
Core Configuration Memory Map
3.3.2.10 Operating Mode B (MB)—Bit 1
This bit is latched from the EXTBOOT pin on reset. Please refer to Section 3.7 in the DSP56800
Family Manual.
3.3.2.11 Operating Mode A (MA)—Bit 0
This bit is latched from the EXTBOOT pin on reset. Please refer to Section 3.7 in the DSP56800
Family Manual.
3.4 Core Configuration Memory Map
Core configuration registers are part of the Data Memory map on the 56F826/827 part. These
locations may be accessed with the same addressing modes used for ordinary data memory when
the EX bit is cleared. However, when the EX bit is set, the addresses can only be accessed using
the I/O Short Addressing mode. These registers are implemented as part of the 56800 core itself;
therefore, they will be present on all family members based on the core. This is not necessarily
true for the on-chip configuration registers discussed in the next section.
Table 3-10 illustrates the on-chip memory mapped core configuration registers.
Table 3-10. 56800 On-Chip Core Configuration Register Memory Map
Core Config Accessibility Register
X:$FFFF
Accessible Using I/O Short
X:$FFFB Interrupt Priority Register (IPR)
X:$FFF9 Bus Control Register (BCR)
Not Accessible At All When EX=1 Reserved
Addressing
OnCE PGDB Bus Transfer Register (OPGDBR)
Reserved
Reserved
Reserved
Reserved
Reserved
56F826/827 User Manual, Rev. 3
12 Freescale Semiconductor
On-Chip Peripheral Memory Map
3.5 On-Chip Peripheral Memory Map
On-chip peripheral registers are part of the Data Memory map of the 56F826/827. These
locations may be accessed with the same addressing modes used for ordinary data memory.
However, they may not be entered by write and single read operations when the EX bit is set.
(Since the EX bit is ignored on all second reads of a dual parallel move, these addresses are
readable when EX = 1 as the second move.)
Table 3-11 and Table 3-12 illustrate the on-chip memory mapped peripheral registers. The base
address represents the starting address used for each peripheral’s registers. Register memory
locations are assigned in each peripheral chapter established on this base address, plus a given
offset.
Not all peripherals are used on each device. For example, only the 56F827 uses the ADC
peripheral. Also, the Data Memory map for the 56F826 starts from a different location of the
mapped peripheral registers. So, 56F826 base addresses are different from those for the 56F827.
It is important to read the address range and base address corresponding to the chip being used in
Table 3-13. The following list of peripheral abbreviations appears in the same table.
Unless noted, each listed peripheral is available on both chips.
• System Integration Module (SIM)
• Program Flash Interface Unit number Two (PFIU2) (56F826 only)
• Data Flash Interface Unit (DFIU)
• Boot Flash Interface Unit (BFIU)
• Quad Timer A (TMRA)
• Time-of-Day (TOD)
• Synchronous Serial Interface (SSI)
• Clock Generation (CLKGEN)
• Interrupt Controller (ITCN)
• Computer Operating Properly (COP)
• Serial Peripheral Interface 0 (SPI0)
• Serial Peripheral Interface 1 (SPI1)
• Serial Communications Interface 0 (SCI0)
• Serial Communications Interface 1 (SCI1)
• General-Purpose I/O port A (GPIOA)
• General-Purpose I/O port B (GPIOB)
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 13
On-Chip Peripheral Memory Map
• General-Purpose I/O port C (GPIOC)
• General-Purpose I/O port D (GPIOD)
• General-Purpose I/O port E (GPIOE)
• General-Purpose I/O port F (GPIOF)
• Program Flash Interface Unit A Lower (PFIUAL) (56F827 only)
• Program Flash Interface Unit A Upper (PFIUAH) (56F827 only)
• Analog-to-Digital Converter (ADC) (56F827 only)
• Programmable Chip Select (PCS) (56F827only)
Table 3-11. 56F826 Data Memory Peripheral Address Map
Peripheral
Name
SIM
PFIU $1020 - $103F PFIU_BASE = $1020 Table 3-14
DFIU $1060 - $107F DFIU_BASE = $1060 Table 3-16
BFIU $1080 - $109F BFIU_BASE = $1080 Table 3-17
TMRA $10A0 - $10BF TMRA_BASE = $1200 Table 3-19
TOD $10C0 - $10CF TOD_BASE = $10C0 Table 3-21
SSI $10E0 - $10EF SSI_BASE = $10E0 Table 3-22
CLKGEN $10F0 - $10FF CLKGEN_BASE = $10F0 Table 3-29
ITCN $1100 - $111F ITCN_BASE = $1100 Table 3-18
COP $1120 - $112F COP_BASE = $1120 Table 3-28
SPI0 $1140 -$114F SPI0_BASE = $1140 Table 3-26
SPI1 $1150 -$115F SPI1 _BASE = $1150 Table 3-27
SCI $1160 - $116F SCI0_BASE = $1160 Table 3-23
SCI1 $1170 - $117F SCI1_BASE = $1170 Table 3-24
GPIOA $11A0 - $11AF GPIOA_BASE = $11A0 Table 3-30
GPIOB $11B0 - $11BF GPIOB_BASE = $11B0 Table 3-31
GPIOC $11C0 - $11CF GPIOC_BASE = $11C0 Table 3-32
GPIOD $11D0 - $11DF GPIOD_BASE = $11D0 Table 3-33
GPIOE $11E0 - $11EF GPIOE_BASE = $11E0 Table 3-34
GPIOF $11F0 - $11FF GPIOF_BASE = $11F0 Table 3-35
Address Range Base Address
$1000 - $100F
SYS_BASE = $1000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Peripheral Register
Address Tables
Table 3-13
56F826/827 User Manual, Rev. 3
14 Freescale Semiconductor
On-Chip Peripheral Memory Map
Table 3-12. F56827 Data Memory Peripheral Address Map
Peripheral
Name
SIM
PFIU $1020 - $103F PFIU_BASE = $1020 Table 3-14
PFIU2 $1040 - $105F PFIU2_BASE = $1040 Table 3-14
DFIU $1060 - $107F DFIU_BASE = $1060 Table 3-16
TOD $10C0 - $10CF TOD_BASE = $10C0 Table 3-21
SSI $10E0 - $10EF SSI_BASE = $10E0 Table 3-22
CLKGEN $10F0 - $10FF CLKGEN_BASE = $10F0 Table 3-29
ITCN $1100 - $111F ITCN_BASE = $1100 Table 3-19
COP $1120 - $112F COP_BASE = $1120 Table 3-28
SPI0 $1140 -$114F SPI0_BASE = $1140 Table 3-26
SPI1 $1150 -$115F SPI1 _BASE = $1150 Table 3-27
SCI0 $1160 - $116F SCI0_BASE = $1160 Table 3-23
SCI1 $1170 - $117F SCI1_BASE = $1170 Table 3-24
SCI2 $1180 - $118F SCI2_BASE = $1180 Table 3-25
PCS $1190 - $119F PCS_BASE = $1190 Table 3-38
GPIOA $11A0 - $11AF GPIOA_BASE = $11A0 Table 3-30
GPIOB $11B0 - $11BF GPIOB_BASE = $11B0 Table 3-31
GPIOC $11C0 - $11CF GPIOC_BASE = $11C0 Table 3-32
GPIOD $11D0 - $11DF GPIOD_BASE = $11D0 Table 3-33
GPIOF $11F0 - $11FF GPIOF_BASE = $11F0 Table 3-35
TMRA
GPIOG
ADC $12C0 - $13FF ADC_BASE = $12C0 Table 3-37
Address Range Base Address
$1000 - $101F
$1200 - $123F
$1240 - $124F
SYS_BASE = $1000
Reserved
Reserved
Reserved
Reserved
Reserved
TMRA_BASE = $1200
GPIOG_BASE = $1240
Reserved
Reserved
Peripheral Register
Address Tables
Table 3-13
Table 3-20
Table 3-36
Table 3-13. System Control Registers Address Map (SYS_BASE = $1000)
Register
Abbreviation
SYS_CTRL System Control Register $0 SYS_BASE
SYS_STS System Status Register $1 SYS_BASE
MSH_ID Most Significant Half of JTAG_ID $6 SYS_BASE
LSH_ID Least Significant Half of JTAG_ID $7 SYS_BASE
Freescale Semiconductor 15
Register Description Address Offset Base Address
Memory and Operating Modes, Rev. 3
On-Chip Peripheral Memory Map
Table 3-14. Program FLASH Interface Registers Address Map (PFIU_BASE = $1020)
Register
Abbreviation
PFIU_CNTL Program Flash Control Register $0 PFIU_BASE
PFIU_PE Program Flash Program Enable Register $1 PFIU_BASE
PFIU_EE Program Flash Erase Enable Register $2 PFIU_BASE
PFIU_ADDR Program Flash Address Register $3 PFIU_BASE
PFIU_DATA Program Flash Data Register $4 PFIU_BASE
PFIU_IE Program Flash Interrupt Enable Register $5 PFIU_BASE
PFIU_IS Program Flash Interrupt Source Register $6 PFIU_BASE
PFIU_IP Program Flash Interrupt Pending Register $7 PFIU_BASE
PFIU_CKDIVISOR Program Flash Clock Divisor Register $8 PFIU_BASE
PFIU_TERASEL Program Flash Terase Limit Register $9 PFIU_BASE
PFIU_TMEL Program Flash Time Limit Register $A PFIU_BASE
PFIU_TNVSL Program Flash Tnvs Limit Register $B PFIU_BASE
PFIU_TPGSL Program Flash Tpgs Limit Register $C PFIU_BASE
PFIU_TPROGL Program Flash Tprog Limit Register $D PFIU_BASE
PFIU_TNVHL Program Flash TNVH Limit Register $E PFIU_BASE
PFIU_TNVH1L Program Flash TNVH1 Limit Register $F PFIU_BASE
PFIU_TRCVL Program Flash TRCV Limit Register $10 PFIU_BASE
Register Description Address Offset Base Address
Table 3-15. 56F827 Program Flash Interface Unit #2 Registers
Address Map (PFIU2_BASE = $1040)
Register
Abbreviation
PFIU_CNTL Program Flash Control Register $0 PFIU2_BASE
PFIU_PE Program Flash Program Enable Register $1 PFIU2_BASE
PFIU_EE Program Flash Erase Enable Register $2 PFIU2_BASE
PFIU_ADDR Program Flash Address Register $3 PFIU2_BASE
PFIU_DATA Program Flash Data Register $4 PFIU2_BASE
PFIU_IE Program Flash Interrupt Enable Register $5 PFIU2_BASE
PFIU_IS Program Flash Interrupt Source Register $6 PFIU2_BASE
PFIU_IP Program Flash Interrupt Pending Register $7 PFIU2_BASE
PFIU_CKDIVISOR Program Flash Clock Divisor Register $8 PFIU2_BASE
PFIU_TERASEL Program Flash Terase Limit Register $9 PFIU2_BASE
PFIU_TMEL Program Flash Time Limit Register $A PFIU2_BASE
PFIU_TNVSL Program Flash Tnvs Limit Register $B PFIU2_BASE
PFIU_TPGSL Program Flash Tpgs Limit Register $C PFIU2_BASE
PFIU_TPROGL Program Flash Tprog Limit Register $D PFIU2_BASE
Register Description Address Offset Base Address
56F826/827 User Manual, Rev. 3
16 Freescale Semiconductor
On-Chip Peripheral Memory Map
Table 3-15. 56F827 Program Flash Interface Unit #2 Registers
Address Map (PFIU2_BASE = $1040) (Continued)
Register
Abbreviation
PFIU_TNVHL Program Flash TNVH Limit Register $E PFIU2_BASE
PFIU_TNVH1L Program Flash TNVH1 Limit Register $F PFIU2_BASE
PFIU_TRCVL Program Flash TRCV Limit Register $10 PFIU2_BASE
Register Description Address Offset Base Address
Table 3-16. Data Flash Interface Unit Registers Address Map (DFIU_BASE = $1060)
Register
Abbreviation
DFIU_CNTL Data Flash Control Register $0 DFIU_BASE
DFIU_PE Data Flash Program Enable Register $1 DFIU_BASE
DFIU_EE Data Flash Erase Enable Register $2 DFIU_BASE
DFIU_ADDR Data Flash Address Register $3 DFIU_BASE
DFIU_DATA Data Flash Data Register $4 DFIU_BASE
DFIU_IE Data Flash Interrupt Enable Register $5 DFIU_BASE
DFIU_IS Data Flash Interrupt Source Register $6 DFIU_BASE
DFIU_IP Data Flash Interrupt Pending Register $7 DFIU_BASE
DFIU_CKDIVISOR Data Flash Clock Divisor Register $8 DFIU_BASE
DFIU_TERASEL Data Flash Terase Limit Register $9 DFIU_BASE
DFIU_TMEL Data Flash TME Limit Register $A DFIU_BASE
DFIU_TNVSL Data Flash TNVS Limit Register $B DFIU_BASE
DFIU_TPGSL Data Flash TPGS Limit Register $C DFIU_BASE
DFIU_TPROGL Data Flash TPROG Limit Register $D DFIU_BASE
DFIU_TNVHL Data Flash TNVH Limit Register $E DFIU_BASE
DFIU_TNVHL1 Data Flash TNVH1 Limit Register $F DFIU_BASE
DFIU_TRCVL Data Flash TRCV Limit Register $10 DFIU_BASE
Register Description Address Offset Base Address
Table 3-17. 56F826 Boot Flash Interface Unit Registers Address Map
(
BFIU_BASE = $1080)
Register
Abbreviation
BFIU_CNTL Boot Flash Control Register $0 BFIU_BASE
BFIU_PE Boot Flash Program Enable Register $1 BFIU_BASE
BFIU_EE Boot Flash Erase Enable Register $2 BFIU_BASE
BFIU_ADDR Boot Flash Address Register $3 BFIU_BASE
BFIU_DATA Boot Flash Data Register $4 BFIU_BASE
BFIU_IE Boot Flash Interrupt Enable Register $5 BFIU_BASE
BFIU_IS Boot Flash Interrupt Source Register $6 BFIU_BASE
Freescale Semiconductor 17
Register Description Address Offset Base Address
Memory and Operating Modes, Rev. 3
On-Chip Peripheral Memory Map
Table 3-17. 56F826 Boot Flash Interface Unit Registers Address Map
(BFIU_BASE = $1080)
Register
Abbreviation
BFIU_IP Boot Flash Interrupt Pending Register $7 BFIU_BASE
BFIU_CKDIVISOR Boot Flash Clock Divisor Register $8 BFIU_BASE
BFIU_TERASEL Boot Flash Terase Limit Register $9 BFIU_BASE
BFIU_TMEL Boot Flash TME Limit Register $A BFIU_BASE
BFIU_TNVSL Boot Flash TNVS Limit Register $B BFIU_BASE
BFIU_TPGSL Boot Flash TPGS Limit Register $C BFIU_BASE
BFIU_TPROGL Boot Flash TPROG Limit Register $D BFIU_BASE
BFIU_TNVHL Boot Flash TNVH Limit Register $E BFIU_BASE
BFIU_TNVHL1 Boot Flash TNVH1 Limit Register $F BFIU_BASE
BFIU_TRCVL Boot Flash TRCV Limit Register $10 BFIU_BASE
Register Description Address Offset Base Address
Table 3-18. Interrupt Controller Registers Address Map (ITCN_BASE = $1100)
Register
Abbreviation
ITCN_GPR0 Group Priority Register 0 $0 ITCN_BASE
ITCN_GPR1 Group Priority Register 1 $1 ITCN_BASE
ITCN_GPR2 Group Priority Register 2 $2 ITCN_BASE
ITCN_GPR3 Group Priority Register 3 $3 ITCN_BASE
ITCN_GPR4 Group Priority Register 4 $4 ITCN_BASE
ITCN_GPR5 Group Priority Register 5 $5 ITCN_BASE
ITCN_GPR6 Group Priority Register 6 $6 ITCN_BASE
ITCN_GPR7 Group Priority Register 7 $7 ITCN_BASE
ITCN_GPR8 Group Priority Register 8 $8 ITCN_BASE
ITCN_GPR9 Group Priority Register 9 $9 ITCN_BASE
ITCN_GPR10 Group Priority Register 10 $A ITCN_BASE
ITCN_GPR11 Group Priority Register 11 $B ITCN_BASE
ITCN_GPR12 Group Priority Register 12 $C ITCN_BASE
ITCN_GPR13 Group Priority Register 13 $D ITCN_BASE
ITCN_GPR14 Group Priority Register 14 $E ITCN_BASE
ITCN_GPR15 Group Priority Register 15 $F ITCN_BASE
Register Description Address Offset Base Address
56F826/827 User Manual, Rev. 3
18 Freescale Semiconductor
On-Chip Peripheral Memory Map
Table 3-19. 56F826 Quad Timer A Registers Address Map
(TMRA_BASE = $10A0)
Register
Abbreviation
TMRA0_CMP1 Compare Register 1 $0 TMRA_BASE
TMRA0_CMP2 Compare Register 2 $1 TMRA_BASE
TMRA0_CAP Capture Register $2 TMRA_BASE
TMRA0_LOAD Load Register $3 TMRA_BASE
TMRA0_HOLD Hold Register $4 TMRA_BASE
TMRA0_CNTR Counter Register $5 TMRA_BASE
TMRA0_CTRL Control Register $6 TMRA_BASE
TMRA0_SCR Status and Control Register $7 TMRA_BASE
TMRA1_CMP1 Compare Register 1 $8 TMRA_BASE
TMRA1_CMP2 Compare Register 2 $9 TMRA_BASE
TMRA1_CAP Capture Register $A TMRA_BASE
TMRA1_LOAD Load Register $B TMRA_BASE
TMRA1_HOLD Hold Register $C TMRA_BASE
TMRA1_CNTR Counter Register $D TMRA_BASE
TMRA1_CTRL Control Register $E TMRA_BASE
TMRA1_SCR Status and Control Register $F TMRA_BASE
TMRA2_CMP1 Compare Register 1 $10 TMRA_BASE
TMRA2_CMP2 Compare Register 2 $11 TMRA_BASE
TMRA2_CAP Capture Register $12 TMRA_BASE
TMRA2_LOAD Load Register $13 TMRA_BASE
TMRA2_HOLD Hold Register $14 TMRA_BASE
TMRA2_CNTR Counter Register $15 TMRA_BASE
TMRA2_CTRL Control Register $16 TMRA_BASE
TMRA2_SCR Status and Control Register $17 TMRA_BASE
TMRA0_CMP1 Compare Register 1 $18 TMRA_BASE
TMRA0_CMP2 Compare Register 2 $19 TMRA_BASE
TMRA0_CAP Capture Register $1A TMRA_BASE
TMRA0_LOAD Load Register $1B TMRA_BASE
TMRA0_HOLD Hold Register $1C TMRA_BASE
TMRA0_CNTR Counter Register $1D TMRA_BASE
TMRA0_CTRL Control Register $1E TMRA_BASE
TMRA0_SCR Status and Control Register $1F TMRA_BASE
Register Description Address Offset Base Address
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 19
On-Chip Peripheral Memory Map
Table 3-20. 56F827 Quad Timer A Registers Address Map
(TMRA_BASE = $1200)
Register
Abbreviation
TMRA0_CMP1 Compare Register 1 $0 TMRA_BASE
TMRA0_CMP2 Compare Register 2 $1 TMRA_BASE
TMRA0_CAP Capture Register $2 TMRA_BASE
TMRA0_LOAD Load Register $3 TMRA_BASE
TMRA0_HOLD Hold Register $4 TMRA_BASE
TMRA0_CNTR Counter Register $5 TMRA_BASE
TMRA0_CTRL Control Register $6 TMRA_BASE
TMRA0_SCR Status and Control Register $7 TMRA_BASE
TMRA0_CMPLD1 Comparator Load Register 1 $8 TMRA_BASE
TMRA0_CMPLD2 Comparator Load Register 2 $9 TMRA_BASE
TMRA0_COMSCR Comparator Status and Control Register 0 $A TMRA_BASE
TMRA1_CMP1 Compare Register 1 $10 TMRA_BASE
TMRA1_CMP2 Compare Register 2 $11 TMRA_BASE
TMRA1_CAP Capture Register $12 TMRA_BASE
TMRA1_LOAD Load Register $13 TMRA_BASE
TMRA1_HOLD Hold Register $14 TMRA_BASE
TMRA1_CNTR Counter Register $15 TMRA_BASE
TMRA1_CTRL Control Register $16 TMRA_BASE
TMRA1_SCR Status and Control Register $17 TMRA_BASE
TMRA1_CMPLD1 Comparator Load Register 1 $18 TMRA_BASE
TMRA1_CMPLD2 Comparator Load Register 2 $19 TMRA_BASE
TMRA1_COMSCR Comparator Status and Control Register 1 $1A TMRA_BASE
TMRA2_CMP1 Compare Register 1 $20 TMRA_BASE
TMRA2_CMP2 Compare Register 2 $21 TMRA_BASE
TMRA2_CAP Capture Register $22 TMRA_BASE
TMRA2_LOAD Load Register $23 TMRA_BASE
TMRA2_HOLD Hold Register $24 TMRA_BASE
TRMA2_CNTR Counter Register $25 TMRA_BASE
TRMA2_CTRL Control Register $26 TMRA_BASE
TRMA2_SCR Status and Control Register $27 TMRA_BASE
TMRA2_CMPLD1 Comparator Load Register 1 $28 TMRA_BASE
TMRA2_CMPLD2 Comparator Load Register 2 $29 TMRA_BASE
TMRA2_COMSCR Comparator Status and Control Register 2 $2A TMRA_BASE
Register Description Address Offset Base Address
Reserved
Reserved
Reserved
56F826/827 User Manual, Rev. 3
20 Freescale Semiconductor
On-Chip Peripheral Memory Map
Table 3-20. 56F827 Quad Timer A Registers Address Map
(TMRA_BASE = $1200) (Continued)
Register
Abbreviation
TRMA3_CMP1 Compare Register 1 $30 TMRA_BASE
TRMA3_CMP2 Compare Register 2 $31 TMRA_BASE
TRMA3_CAP Capture Register $32 TMRA_BASE
TRMA3_LOAD Load Register $33 TMRA_BASE
TMRA3_HOLD Hold Register $34 TMRA_BASE
TMRA3_CNTR Counter Register $35 TMRA_BASE
TMRA3_CTRL Control Register $36 TMRA_BASE
TRMA3_SCR Status and Control Register $37 TMRA_BASE
TMRA3_CMPLD1 Comparator Load Register 1 $38 TMRA_BASE
TMRA3_CMPLD2 Comparator Load Register 2 $39 TMRA_BASE
TMRA3_COMSCR Comparator Status and Control Register 3 $3A TMRA_BASE
Register Description Address Offset Base Address
Table 3-21. Time-of-Day Registers Address Map (TOD_BASE = $10C0)
Register
Abbreviation
TODCS Control/Status $0 TOD_BASE
TODCSL Clock Scaler Load $1 TOD_BASE
TODSEC Seconds $2 TOD_BASE
TODSAL Seconds Alarm $3 TOD_BASE
TODMIN Minutes $4 TOD_BASE
TODMAL Minutes Alarm $5 TOD_BASE
TODHR Hours $6 TOD_BASE
TODHAL Hours Alarm $7 TOD_BASE
TODDAY Days $8 TOD_BASE
TODDAL Days Alarm $9 TOD_BASE
Register Description Address Offset Base Address
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 21
On-Chip Peripheral Memory Map
Table 3-22. SSI Registers Address Map (SSI_BASE = $10E0)
Register
Abbreviation
STX Transmit Register $0 SSI_BASE
SRX Receive Register $1 SSI_BASE
SCSR Control/Status Register 1 $2 SSI_BASE
SCR2 Control Register 2 $3 SSI_BASE
STXCR Transmit Control Register $4 SSI_BASE
SRXCR Receive Control Register $5 SSI_BASE
STSR Time Slot Register $6 SSI_BASE
SFCSR FIFO Control/Status Register $7 SSI_BASE
SOR Option Register $9 SSI_BASE
Register Description Address Offset Base Address
Reserved
Table 3-23. SCI0 Registers Address Map (SCI0_BASE = $1160)
Register
Abbreviation
SCI0_SCIBR Baud Rate Register $0 SCI0_BASE
SCI0_SCICR Control Register $1 SC0_BASE
SCI0_SCISR Status Register $2 SCI0_BASE
SCI0_SCIDR Data Register $3 SCI0_BASE
Register Description Address Offset Base Address
Table 3-24. SCI1 Registers Address Map (SCI1_BASE = $1170)
Register
Abbreviation
SCI1_SCIBR Baud Rate Register $0 SCI1_BASE
SCI1_SCICR Control Register $1 SCI1_BASE
SCI1_SCISR Status Register $2 SCI1_BASE
SCI1_SCIDR Data Register $3 SCI1_BASE
Register Description Address Offset Base Address
Table 3-25. 56F827 SCI2 Registers Address Map (SCI2_BASE = $1180)
Register
Abbreviation
SCI2_SCIBR Baud Rate Register $0 SCI2_BASE
SCI2_SCICR Control Register $1 SCI2_BASE
SCI2_SCISR Status Register $2 SCI2_BASE
SCI2_SCIDR Data Register $3 SCI2_BASE
Register Description Address Offset Base Address
56F826/827 User Manual, Rev. 3
22 Freescale Semiconductor
On-Chip Peripheral Memory Map
Table 3-26. SPI0 Registers Address Map (SPI0_BASE = $1140)
Register
Abbreviation
SPI0_SPSCR Status and Control Register $0 SPI0_BASE
SPI0_SPDSR Data Size Register $1 SPI0_BASE
SPI0_SPDRR Data Receive Register $2 SPI0_BASE
SPI0_SPDTR Data Transmit Register $3 SPI0_BASE
Register Description Address Offset Base Address
Table 3-27. SPI1 Registers Address Map (SPI1_BASE = $1150)
Register
Abbreviation
SPI1_SPSCR Status and Control Register $0 SPI1__BASE
SPI1_SPDSR Data Size Register $1 SPI1__BASE
SPI1_SPDRR Data Receive Register $2 SPI1__BASE
SPI1_SPDTR Data Transmit Register $3 SPI1__BASE
Register Description Address Offset Base Address
Table 3-28. COP Registers Address Map (COP_BASE = $1120)
Register
Abbreviation
COPCTL Control Register $0 COP_BASE
COPTO Timeout Register $1 COP_BASE
COPSRV Service Register $2 COP_BASE
Register Description Address Offset Base Address
Table 3-29. Clock Generation Registers Address Map (CLKGEN_BASE = $10F0)
Register
Abbreviation
PLLCR Control Register $0 CLKGEN_BASE
PLLDB Divide-By Register $1 CLKGEN_BASE
PLLSR Status Register $2 CLKGEN_BASE
CLKOSR CLKO Select Register $4 CLKGEN_BASE
Register Description Address Offset Base Address
Reserved
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 23
On-Chip Peripheral Memory Map
Table 3-30. GPIO Port A Registers Address Map (GPIOA_BASE = $11A0)
Register
Abbreviation
GPIO_A_PUR Pull-up Enable Register $0 GPIOA_BASE
GPIO_A_DR Data Register $1 GPIOA_BASE
GPIO_A_DDR Data Direction Register $2 GPIOA_BASE
GPIO_A_PER Peripheral Enable Register $3 GPIOA_BASE
GPIO_A_IAR Interrupt Assert Register $4 GPIOA_BASE
GPIO_A_IENR Interrupt Enable Register $5 GPIOA_BASE
GPIO_A_IPOLR Interrupt Polarity Register $6 GPIOA_BASE
GPIO_A_IPR Interrupt Pending Register $7 GPIOA_BASE
GPIO_A_IESR Interrupt Edge-Sensitive Register $8 GPIOA_BASE
Register Description Address Offset Base Address
Table 3-31. GPIO Port B Registers Address Map (GPIOB_BASE = $11B0)
Register
Abbreviation
GPIO_B_PUR Pull-up Enable Register $0 GPIOB_BASE
GPIO_B_DR Data Register $1 GPIOB_BASE
GPIO_B_DDR Data Direction Register $2 GPIOB_BASE
GPIO_B_PER Peripheral Enable Register $3 GPIOB_BASE
GPIO_B_IAR Interrupt Assert Register $4 GPIOB_BASE
GPIO_B_IENR Interrupt Enable Register $5 GPIOB_BASE
GPIO_B_IPOLR Interrupt Polarity Register $6 GPIOB_BASE
GPIO_B_IPR Interrupt Pending Register $7 GPIOB_BASE
GPIO_B_IESR Interrupt Edge-Sensitive Register $8 GPIOB_BASE
Register Description Address Offset Base Address
Table 3-32. GPIO Port C Registers Address Map (GPIOC_BASE = $11C0)
Register
Abbreviation
GPIO_C_PUR Pull-up Enable Register $0 GPIOC_BASE
GPIO_C_DR Data Register $1 GPIOC_BASE
GPIO_C_DDR Data Direction Register $2 GPIOC_BASE
GPIO_C_PER Peripheral Enable Register $3 GPIOC_BASE
GPIO_C_IAR Interrupt Assert Register $4 GPIOC_BASE
GPIO_C_IENR Interrupt Enable Register $5 GPIOC_BASE
GPIO_C_IPOLR Interrupt Polarity Register $6 GPIOC_BASE
GPIO_C_IPR Interrupt Pending Register $7 GPIOC_BASE
GPIO_C_IESR Interrupt Edge-Sensitive Register $8 GPIOC_BASE
24 Freescale Semiconductor
Register Description Address Offset Base Address
56F826/827 User Manual, Rev. 3
On-Chip Peripheral Memory Map
Table 3-33. GPIO Port D Registers Address Map (GPIOD_BASE = $11D0)
Register
Abbreviation
GPIO_D_PUR Pull-up Enable Register $0 GPIOD_BASE
GPIO_D_DR Data Register $1 GPIOD_BASE
GPIO_D_DDR Data Direction Register $2 GPIOD_BASE
GPIO_D_PER Peripheral Enable Register $3 GPIOD_BASE
GPIO_D_IAR Interrupt Assert Register $4 GPIOD_BASE
GPIO_D_IENR Interrupt Enable Register $5 GPIOD_BASE
GPIO_D_IPOLR Interrupt Polarity Register $6 GPIOD_BASE
GPIO_D_IPR Interrupt Pending Register $7 GPIOD_BASE
GPIO_D_IESR Interrupt Edge-Sensitive Register $8 GPIOD_BASE
Register Description Address Offset Base Address
Table 3-34. 56F826 GPIO Port E Registers Address Map (GPIOE_BASE = $11E0)
Register
Abbreviation
GPIO_E_PUR Pull-up Enable Register $0 GPIOE_BASE
GPIO_E_DR Data Register $1 GPIOE_BASE
GPIO_E_DDR Data Direction Register $2 GPIOE_BASE
GPIO_E_PER Peripheral Enable Register $3 GPIOE_BASE
GPIO_E_IAR Interrupt Assert Register $4 GPIOE_BASE
GPIO_E_IENR Interrupt Enable Register $5 GPIOE_BASE
GPIO_E_IPOLR Interrupt Polarity Register $6 GPIOE_BASE
GPIO_E_IPR Interrupt Pending Register $7 GPIOE_BASE
GPIO_E_IESR Interrupt Edge-Sensitive Register $8 GPIOE_BASE
Register Description Address Offset Base Address
Table 3-35. 56F826 GPIO Port F Registers Address Map (GPIOF_BASE = $11F0)
Register
Abbreviation
GPIO_F_PUR Pull-up Enable Register $0 GPIOF_BASE
GPIO_F_DR Data Register $1 GPIOF_BASE
GPIO_F_DDR Data Direction Register $2 GPIOF_BASE
GPIO_F_PER Peripheral Enable Register $3 GPIOF_BASE
GPIO_F_IAR Interrupt Assert Register $4 GPIOF_BASE
GPIO_F_IENR Interrupt Enable Register $5 GPIOF_BASE
GPIO_F_IPOLR Interrupt Polarity Register $6 GPIOF_BASE
GPIO_F_IPR Interrupt Pending Register $7 GPIOF_BASE
GPIO_F_IESR Interrupt Edge-Sensitive Register $8 GPIOF_BASE
Freescale Semiconductor 25
Register Description Address Offset Base Address
Memory and Operating Modes, Rev. 3
On-Chip Peripheral Memory Map
Table 3-36. 56F827 GPIO Port G Registers Address Map (GPIOG_BASE = $1240)
Register
Abbreviation
GPIO_G_PUR Pull-up Enable Register $0 GPIOG_BASE
GPIO_G_DR Data Register $1 GPIOG_BASE
GPIO_G_DDR Data Direction Register $2 GPIOG_BASE
GPIO_G_PER Peripheral Enable Register $3 GPIOG_BASE
GPIO_G_IAR Interrupt Assert Register $4 GPIOG_BASE
GPIO_G_IENR Interrupt Enable Register $5 GPIOG_BASE
GPIO_G_IPOLR Interrupt Polarity Register $6 GPIOG_BASE
GPIO_G_IPR Interrupt Pending Register $7 GPIOG_BASE
GPIO_G_IESR Interrupt Edge-Sensitive Register $8 GPIOG_BASE
Register Description Address Offset Base Address
Table 3-37. 56F827 ADC Registers Address Map (ADC_BASE = $12C0)
Register
Abbreviation
ADCR1 Control Register 1 $0 ADC_BASE
ADCR2 Control Register 2 $1 ADC_BASE
ADZCC1 Zero Crossing Control Register 1 $2 ADC_BASE
ADZCC2 Zero Crossing Control Register 2 $3 ADC_BASE
ADLST1 Channel List Registers 1 $4 ADC_BASE
ADLST2 Channel List Register 2 $5 ADC_BASE
ADLST3 Channel List Register 3 $6 ADC_BASE
ADLST4 Channel List Register 4 $7 ADC_BASE
ADLST5 Channel List Register 5 $8 ADC_BASE
ADSDIS Sample Disable Register $9 ADC_BASE
ADSTAT1 Status Register 1 $A ADC_BASE
ADSTAT2 Status Register 2 $B ADC_BASE
ADLLSTAT Low Limit Status Register $C ADC_BASE
ADHLSTAT High Limit Status Register $D ADC_BASE
ADZCSTAT Zero Crossing Status Register $E ADC_BASE
ADRSLT0–9 ADC Result Registers 0–9
ADLLMT0–9 ADC Low Limit Registers 0–9
ADHLMT0–9 ADC High Limit Registers 0–9
ADOFS0–9 ADC Offset Registers 0–9
Register Description Address Offset Base Address
$F, $10, $11, $12, $13,
$14, $15, $16, $17, $18
$19, $1A, $1B, $1C, $1D,
$1E, $1F, $20, $21, $22
$23, $24, $25, $26, $27,
$28, $29, $2A, $2B, $2C
$2D, $2E, $2F, $30, $31,
$32, $33, $34, $35, $36
Reserved
ADC_BASE
ADC_BASE
ADC_BASE
ADC_BASE
56F826/827 User Manual, Rev. 3
26 Freescale Semiconductor
Table 3-38. 56F827 PCS Registers Address Map (PCS_BASE = $1190)
Program Memory
Register
Abbreviation
PCSBAR 0 Base Address Register 0 $0 PCS_BASE
PCSBAR 1 Base Address Register 1 $1 PCS_BASE
PCSBAR 2 Base Address Register 2 $2 PCS_BASE
PCSBAR 3 Base Address Register 3 $3 PCS_BASE
PCSBAR 4 Base Address Register 4 $4 PCS_BASE
PCSBAR 5 Base Address Register 5 $5 PCS_BASE
PCSBAR 6 Base Address Register 6 $6 PCS_BASE
PCSBAR 7 Base Address Register 7 $7 PCS_BASE
PCSOR 0 Option Control Register 0 $8 PCS_BASE
PCSOR 1 Option Control Register 1 $9 PCS_BASE
PCSOR 2 Option Control Register 2 $A PCS_BASE
PCSOR 3 Option Control Register 3 $B PCS_BASE
PCSOR 4 Option Control Register 4 $C PCS_BASE
PCSOR 5 Option Control Register 5 $D PCS_BASE
PCSOR 6 Option Control Register 6 $E PCS_BASE
PCSOR 7 Option Control Register 7 $F PCS_BASE
Register Description Address Offset Base Address
3.6 Program Memory
As illustrated in Table 3-1, the 56F826 has 31.5K words of on-chip Program Flash and 512
words of on-chip Program RAM and 2K words of Boot Flash. The 56F827 however, has 63K
words of on-chip Program Flash Memory and 1K words on on-chip Program RAM.
Both 56F826 and 56F827 chip program memories may be expanded off-chip up to 64K. The
external program bus access time is controlled by two of four bits on the Bus Control Register
1
(BCR), located at X:$FFF9
The on-chip Program Flash and RAM may hold a combination of interrupt vectors and program
codes. Both may be modified by the application itself.
When mode three is selected, all 64K words of program memory are external.
. This register is provided in Section .
1.All 56800 chips have two low order wait state bits in BCR hardcoded to zero.
Memory and Operating Modes, Rev. 3
Freescale Semiconductor 27
Operating Modes
3.7 Operating Modes
Both chips have two valid operating modes determining the memory maps for Program Memory.
Operating modes can be selected either by applying the appropriate signal to the EXTBOOT pin
during Reset, or by writing to the OMR and changing the MA and MB bits. The EXTBOOT pin
is sampled as the chip leaves the reset state, and the initial operating mode of the chip is set
accordingly.
Table 3-39. Program Memory Chip Operating Modes
State of EXTBOOT Upon Reset MB MA Chip Operating Mode
000
N/A 0 1
N/A 1 0
111
Mode 0
Normal Operation
Not Supported
Mode 3
External ROM
Chip operating modes can also be changed by writing to the operating mode bits MB and MA in
the OMR. Changing operating modes does not reset the chip. Interrupts should be disabled
immediately after an interrupt and before changing the OMR. This will prevent an interrupt from
going to the wrong memory location. Also, one No-Operation (NOP) instruction should be
included after changing the OMR to allow re-mapping to occur.
Note: When COP is reset, the MA and MB bits will revert to the values originally latched
from the EXTBOOT pin in contradiction of RESET
, hardware reset. These original
mode values determine the COP reset vector. EXTBOOT is read-only at the time of
reset.
3.7.1 Single Chip Mode: Start-Up (Mode 0)
Mode zero is the single-chip mode internal Program RAM (PRAM) and PFLASH are enabled for
reads and fetches. The 56F826 has two submodes:
1. Mode 0A Boot mode where all memory is internal
2. Mode 0B non-Boot mode where the first 32K of memory is internal and the second 32K is
external
Note: Please refer to Section 15.8 and Figure 15-8 for additional information about
SYS_CNTL.
If EXTBOOT is asserted low during reset, then Mode 0A boot is automatically entered when
exiting the Reset mode.
56F826/827 User Manual, Rev. 3
28 Freescale Semiconductor
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