This hardware specification contains detailed informatio n on
power considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC885/MPC880 (refer to Table 1
for the list of devices). The MPC885 is the superset device of the
MPC885/MPC880 family. The CPU on the MPC885/MPC880 is
a 32-bit PowerPC™ core that incorporates memory management
units (MMUs) and instruction and data caches and that
implements the PowerPC instruction set.
1Overview
The MPC885/880 is a versatile single-chip integrated
microprocessor and peripheral combination that can be used in a
variety of controller applications and communications and
networking systems. The MPC885/MPC880 provides enhanced
ATM functionality, an additional fast Ethernet controller, a USB,
and an encryption block.
Table 1 shows the functionality supported by the members of the MPC885 family.
Table 1. MPC885 Family
CacheEthernet
Part
I Cache D Cache 10BaseT10/100
MPC8858 Kbyte8 KbyteUp to 3 2 3 21Serial ATM and
MPC8808 Kbyte8 KbyteUp to 22221Serial AT M and
SCC SMC USBATM Support
UTOPIA interface
UTOPIA interface
Security
Engine
Yes
No
2Features
The MPC885/880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC885/880 features:
•Embedded MPC8xx core up to 133 MHz
•Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
•Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
– Caches are physi cally addresse d, implement a leas t recentl y used (LRU) repl acement algori thm, and
are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
and 16 protection groups
— Advanced on-chip emulation debug mode
•Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes the
following:
— Improve d operation, administ ration and ma intenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability
— Optional statistical cell counters per PHY
MPC885/MPC880 Hardware Specifications, Rev. 3
2Freescale Semiconduct or
Page 3
Features
— UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell
transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also
supported.)
— Parameter RAM for both SPI and I
2
C can be relocated without RAM-based microcode
— Supports full-d uplex UTOPIA ma ster (ATM side) and slave ( PHY side) operati ons using a spl it
bus
— AAL2/VBR functionality is ROM-resident.
•Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
•32 address lines
•Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS
to support a DRAM bank.
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS
lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
•General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
•Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that
interface through MII and/or RMII interfaces
•System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
•Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
802.11i, and iSCSI processing. Available on the MPC885, the security engine contains a
crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
MPC885/MPC880 Hardware Specifications, Rev. 3
Freescale Semiconduc tor3
Page 4
Features
— Advanced encryption standard unit (AESU)
– Implements the Rinjdael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256- bit key lengths
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Crypto-channel supporting multi-command descriptor chains
— Integrated controller managing internal resources and bus mastering
— Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes
•Interrupts
— Six external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
•Communications processor module (CPM)
— RISC controller
— Communication-specifi c commands (for example,
RESTARTTRANSMIT)
GRACEFULSTOPTRANSMIT, ENTERHUNTMODE, and
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability
•On-chip 16
× 16 multiply accumulate controller (MAC)
— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies
•Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
•Up to three serial communication controllers (S CCs) supporting the following protocols:
— Serial ATM capability on SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on the SCC(s) supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
MPC885/MPC880 Hardware Specifications, Rev. 3
4Freescale Semiconduct or
Page 5
Features
—AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
•Up to two serial management channels (SMCs) supporting the following protocols:
— UART (l ow-s peed operation)
— Transparent
— General circuit interface (GCI) controller
— Provide management for BRI devices as GCI controller in time-division multiplexed (TDM)
channels
•Universal serial bus ( USB)—Supports operation as a USB function endpoint, a USB host controller ,
or both for testing purposes (loop-back diagnostics)
— USB 2.0 full-/low-speed compatible
— The USB function mode has the following features:
– Four independent e ndpoint s suppo rt contr ol, bul k, int erru pt, and is ochrono us dat a tra nsfer s.
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffe rs per frame
– Automatic retransmission upon transmit error
— The USB host controller has the following features:
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1. 5-Mbps data rates (automatic g eneration of preamble tok en and data
rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffe rs per frame
– Supports local loop back mode for diagnostics (12 Mbps only)
•Serial peripheral inte rface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
•Inter-integrated circuit (I
2
C) port
— Supports master and slave modes
— Supports a multiple-master environment
•Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
MPC885/MPC880 Hardware Specifications, Rev. 3
Freescale Semiconduc tor5
Page 6
Features
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
•Parallel i nterface port (PIP)
— Centronics interfa ce supp ort
— Supports fast connection between compatible ports on MPC885/880 and other MPC8xx devices
•PCMCIA interface
— Master (so cket) interface, release 2.1-compliant
— Supports two independent PCMCIA sockets
— 8 memory or I/O windows supported
•Debug interface
— Eight comparators: four operate on instruc tion address, two oper ate on data address, and two operate on
data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally.
•Normal high and normal low power modes to conserve power
•1.8-V core and 3.3-V I/O operation
•The MPC885/880 comes in a 357-pin ball grid array (PBGA) package.
MPC885/MPC880 Hardware Specifications, Rev. 3
6Freescale Semiconduct or
Page 7
The MPC885 block diagram is shown in Figure 1.
Features
Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
10/100
BaseT
Media Access
Control
MIII/RMII
Instruction
Bus
Load/Store
Bus
8-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
8-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Parallel I/O
4 Baud Rate
Generators
Parallel Interface Port
Slave/Master IF
4
Interrupt
Timers
Timers
Controllers
32-Bit RISC Controller
Unified
Bus
and Program
ROM
System Interface Unit (SIU)
Bus Interface
Security Engine
Controller
Channel
8-Kbyte
Dual-Port RAM
Memory Controller
Internal
Unit
System Functions
PCMCIA-ATA Interface
External
Bus Interface
Unit
AESUDEUMDEU
Virtual IDMA
Serial DMAs
and
SCC2
SCC3 USB
SCC4/
UTOPIA
Time Slot Assigner
Serial Interface
Serial Interface
Figure 1. MPC885 Block Diagram
SPISMC2SMC1
I2C
MPC885/MPC880 Hardware Specifications, Rev. 3
Freescale Semiconduc tor7
Page 8
Features
The MPC880 block diagram is shown in Figure 2.
Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
10/100
BaseT
Media Access
Control
MIII/RMII
Instruction
Bus
Load/Store
Bus
8-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
8-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Parallel I/O
4 Baud Rate
Generators
Parallel Interface Port
Slave/Master IF
4
Interrupt
Timers
Timers
Controllers
32-Bit RISC Controller
Unified
Bus
and Program
ROM
System Interface Unit (SIU)
Bus Interface
8-Kbyte
Dual-Port RAM
Memory Controller
Internal
Unit
System Functions
PCMCIA-ATA Interface
External
Bus Interface
Unit
Virtual IDMA
Serial DMAs
and
USB
SCC3
Time Slot Assigner
SCC4/
UTOPIA
Serial Interface
Serial Interface
Figure 2. MPC880 Block Diagram
SPISMC2SMC1
I2C
MPC885/MPC880 Hardware Specifications, Rev. 3
8Freescale Semiconduct or
Page 9
Maximum Tolerated Ratings
3Maximum Tolerated Ratings
This section pro vides th e maximum tole rated vo ltage an d temperat ure range s for t he MPC885/8 80. Table 2
displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.
Table 2. Maximum Tolerated Ratings
SymbolValueUnit
V
V
DDH
DDL
–0.3 to 4.0V
–0.3 to 2.0V
Supply voltage
Rating
1
VDDSYN–0.3 to 2.0V
Difference
<100mV
between
and
V
DDL
V
DDSYN
Input voltage
Storage temperature rangeT
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional ope rati ng co nditions are provid ed w ith t he D C electrical specific ati ons i n Table 6. Absolute maximum
2
V
in
stg
GND – 0.3 to
V
DDH
–55 to +150°C
ratings are stress ratings only ; functional op eration at t he maxima is not guaran teed. S tress bey ond those li sted may
affect device reliability or cause permanent damage to the device. See Sect ion8, “Power Supply and Power
Sequencing.”
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power
up and normal operation (tha t is, if the MPC88 5/880 is unp owered, a volt age grea ter than 2.5 V mus t not be appli ed
to its inputs).
Table 3. Operating Temperatures
V
RatingSymbolValueUnit
1
Te mperature
Te mperature (extended)T
1
Minimum temperature s are guar anteed a s ambient te mperatu re, TA. Maximum temperatu res are guaran teed as
junction temperature, T
(standard)
T
A(min)
T
j(max)
A(min)
T
j(max)
.
j
0°C
95°C
–40°C
100°C
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V
MPC885/MPC880 Hardware Specifications, Rev. 3
DD
).
Freescale Semiconduc tor9
Page 10
Thermal Characterist ics
4Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC885/880.
Table 4. MPC885/880 Thermal Resistance Data
RatingEnvironmentSymbolValueUnit
Junction-to-ambient
1
Natural convectionSingle-layer board (1s)R
Four-layer board (2s2p)R
Airflow (200 ft/min)Single-layer board (1s)R
Four-layer board (2s2p)R
Junction-to-board
Junction-to-case
Junction-to-package top
4
5
6
Natural convectionΨ
Airflow (200 ft/min)Ψ
1
Junction temperature is a function of on-chip power dissi pa tion, packa ge ther mal resis tan ce, mounting sit e (boa rd)
temperature, ambi ent tem peratu re, airfl ow, power di ssip at ion of ot her co mpone nts on th e boa rd, and boa rd therm al
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal
4
Thermal resista nce b etw ee n t he di e a nd the printed cir cuit b oard per JEDEC JESD51 -8. Boar d te mp era t ure is
measured on the top surface of the board near the package.
5
Indicates the average thermal resist an ce be tw een the di e a nd the case top surface as me as ured by th e c ol d pl ate
method (MIL SPEC-883 Method 1012.1) with the cold pl ate temperature us ed for the c ase temperature. F or exposed
pad packages whe re the pad would be expected to be s old ere d, junction-to-case therma l res is t an ce is a si mu lated
value from the junction to the exposed pad without contact resistance.
6
Thermal characteri zatio n para meter in dicat ing the tem peratu re dif fer ence be tween p acka ge top and the junc tion
temperature per JEDEC JESD51-2.
θJA
θJMA
θJMA
θJMA
R
θJB
R
θJC
2
3
3
3
37°C/W
25
30
22
17
10
JT
JT
2
2
5Power Dissipation
Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are equal, and
2:1, where CPU frequency is twice bus speed.
Table 5. Power Dissipation (PD)
Die Revision
Bus
Mode
1:1
0
2:1133 MHz430495mW
1
Typical power dissipation at V
DDL
= V
= 1.8 V, and V
DDSYN
DDH
MPC885/MPC880 Hardware Specifications, Rev. 3
10Freescale Semiconduct or
CPU
Frequency
Typical
1
Maximum
2
66 MHz310390mW
80 MHz350430mW
is at 3.3 V.
Unit
Page 11
2
Maximum power dissipation at V
The values in Table 5 represent V
include I/O power dissipation over V
widely by application due to buffer current, depending on external
circuitry.
DDL
= V
DDSYN
= 1.9 V, and V
NOTE
-based power diss ipati on an d d o not
DDL
DDH
is at 3.5 V.
DDH
. I/O power d issipation varies
DC Characteristics
The V
power dissipation is negligible.
DDSYN
6DC Characteristics
Table 6 provides the DC electrical characteristics for the MPC885/880.
T able 6. DC Electrical Specifications
CharacteristicSymbolMinMaxUnit
Operating voltag eV
Input high voltage (all inputs except EXTAL and EXTCLK)
Input low voltage
3
2
EXTAL, EXTCLK input high voltageV
Input leakage current, Vin = 5.5 V (except TMS, TRST
DSDI pins) for 5-V tolerant pins
) + PI/O, where PI/O is the power dissipation of the I/O drivers.
DDL
NOTE
The V
power dissipation is negligible.
DDSYN
7.1Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:
T
= TA + (R
J
θJA
× PD)
where:
T
= ambient temperature ºC
A
R
= package j unction-to-a mbient ther mal resistance (ºC/W)
θJA
P
= power dissipation in package
D
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation
of thermal perform ance. However , the answer is o nly an estimate; t est cases have demo nstrated that err ors of a factor
of two (in the quantity T
) are possible.
J–TA
7.2Estimation with Junction-to-Case Thermal Resistance
Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance:
R
= R
θJA
where:
= junction-to-ambient thermal resistance (ºC/W)
R
θJA
R
= junction-to-case thermal resistance (ºC/W)
θJC
R
= case-to-ambient thermal resistance (ºC/W)
θCA
is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the
R
θJC
case-to-am bient therm al resistance, R
heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the
printed circuit boar d surrounding the device. Thi s thermal model is most usefu l for ceramic packages wit h heat sinks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.
θJC
+ R
θCA
. For instance, the user can change the airflow around the device, add a
θCA
MPC885/MPC880 Hardware Specifications, Rev. 3
12Freescale Semiconduct or
Page 13
Thermal Calculation and Measurement
7.3Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the
top of the package . The junct ion-to- board ther mal resi stance de scribes the ther mal perfor mance when most
of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see
Figure 3.
Figure 3. Effect of Board Temperature Rise on Thermal Behavior
If the board temp eratu re is known, an es timate of th e j uncti on tempe rature i n th e env ironment can b e made
using the following equation:
T
= TB + (R
J
θJB
× PD)
where:
R
= junction-to-board thermal resistance (ºC/W)
θJB
T
= board temperature ºC
B
P
= power dissipation in package
D
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predicti ons of junc ti on te mper ature can be made. For this method to work, the boar d and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
7.4Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
MPC885/MPC880 Hardware Specifications, Rev. 3
Freescale Semiconduc tor13
Page 14
Power Supply and Power Sequencing
7.5Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (Ψ
) can be use d to determine the junction temperature with a measurement of the
JT
temperature at the top center of the package case using the following equation:
T
= TT + (ΨJT× PD)
J
where:
Ψ
= thermal characterization parameter
JT
T
= thermocouple temperature on top of package
T
P
= power dissipation in package
D
The thermal charact erization para meter is measured pe r the JESD51-2 spec ification publ ished by JEDEC using a 40
gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire ex tending f rom the junc tion. The ther mocouple wire is plac ed flat a gainst th e
package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.
7.6References
Semiconductor Equipment and Materials International(415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or
(Available from Global Engineering Documents)303-397-7956
JEDEC Specifications http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
8Power Supply and Power Sequencing
This section pro vides design consi derations for th e MPC885/880 power supp ly . The MPC885/880 has a core voltage
(V
) and PLL voltage (V
DDL
section of the MPC885/880 is supplied with 3.3 V across V
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and
MII_MDIO are 5-V tolerant. Al l inputs cann ot be more than 2.5 V greater than V
can not exceed 5.5 V and remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down
and normal operation.
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at
different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the
manner in which different voltages are derived. The following restrictions apply:
), which both operate at a lower voltage than the I/O voltage V
DDSYN
and VSS (GND).
DDH
DDH
. The I/O
DDH
. In addition, 5-V tolerant pins
•V
•V
14Freescale Semiconduct or
must not exceed V
DDL
must not exceed 1.9 V, and V
DDL
DDH
MPC885/MPC880 Hardware Specifications, Rev. 3
during power up and power down.
must not exceed 3.465 V.
DDH
Page 15
Layout Practices
These cautions are nece ssary for th e long-t erm reliab ility of th e part. If the y are violat ed, the elect rostati c discha rge
(ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system
power supply design does not control the voltage sequenc ing, the circuit shown Figure 4 can be added to meet the se
requirements. The MUR420 Schott ky diodes control the maximum pote ntial difference be tween the external bus and
core power supplies on power up, and the 1N5820 diodes regulate the maximum potential difference on power
down.
V
DDH
MUR420
1N5820
Figure 4. Example Voltage Sequencing Circuit
V
DDL
9Layout Practices
Each VDD pin on the MPC885/880 s hould be prov ided with a low-impedance p ath to the boa rd’ s supply . Each GND
pin should likewise be provid ed with a low-impe dance path to gr ound. The power su pply pins drive di stinct gro ups
of logic on chip. The V
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropr iate decoupling cap aci tors should be used if required. The capacitor leads a nd ass oci at ed printed
circuit traces connecting to chip V
minimum, a four-layer board employing two inner layers as V
All output pins on the MPC885/880 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommended. Capacitan ce calculations sho uld consider all device loa ds as well as parasitic ca pacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads bec ause these loads create hig her transient current s in the V
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to the MPC885 User’s Manual, Section 14.4.3, “Clock
Synthesizer Power (V
power supply should be bypass ed to ground using at l east four 0.1 µF by-pass capacitors
DD
and GND should be kept to less than half an inch per capacitor lead. At a
DD
and GND planes should be used.
DD
and GND circuits. Pull up all unused
DD
DDSYN
, V
SSSYN
, V
SSSYN1
)”.
10 Bus Signal Timing
The maximum bus speed supported by the MPC885/880 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (fo r example, an MPC885/880 used at 133 MHz must be configured f or a 66 MHz bus). Table 7
shows the frequency ra nges for standard part frequen cies in 1:1 bus mode, and Table 8 shows the frequency rang es
for standard part frequencies in 2:1 bus mode.
MPC885/MPC880 Hardware Specifications, Rev. 3
15Freescale Semiconduct or
Page 16
Bus Signal Timing
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency66 MHz80 MHz
MinMaxMinMax
Core frequency4066.674080
Bus frequency4066.674080
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequenc y66 MHz80 MHz133 MHz
MinMaxMinMaxMinMax
Core frequency4066.67408040133
Bus frequency2033.3320402066
Table 9 provides the timings for the MPC885/880 at 33-, 40-, 66-, and 80-MHz bus operation.
The timing for the MPC885/880 bus shown assumes a 50-pF load f or maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay.
Table 9. Bus Operation Timings
33 MHz40 MHz66 MHz80 MHz
NumCharacteristic
MinMaxMinMaxMinMaxMinMax
B1Bus period ( CLKOUT), see Table 7————————ns
B1aEXTCLK to CLKOUT phase skew - If
CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with th e rising edge of CLKO UT .
For a non-integer m ultiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
B1bCLKOUT frequency jitter pea k-to -peak—1—1—1—1ns
B1cFrequency jitter on EXTCLK—0.50—0.50—0.50—0.50%
B1dCLKOUT phase jitter peak-to-peak
for OSCLK ≥ 15 MHz
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
B2CLKOUT pulse width low
(MIN = 0.4
B3CLKOUT pulse width high
(MIN = 0.4
× B1, MAX = 0.6 × B1)
× B1, MAX = 0.6 × B1)
–2+2–2+2–2+2–2+2ns
—4—4—4—4ns
—5 – 5—5—5ns
12.118.210.015.06.19.15.07.5ns
12.118.210.015.06.19.15.07.5ns
Unit
B4CLKOUT rise time —4.00—4.00—4.00—4.00ns
B5CLKOUT fall time
16Freescale Semiconduct or
MPC885/MPC880 Hardware Specifications, Rev. 3
—4.00—4.00—4.00—4.00ns
Page 17
Bus Signal Timing
NumCharacteristic
Table 9. Bus Operation Timings (continued)
33 MHz40 MHz66 MHz80 MHz
Unit
MinMaxMinMaxMinMaxMinMax
B7CLKOUT to A(0:31), BADDR(28:30),
RD/WR
(MIN = 0.25
B7aCLKOUT to TSIZ(0:1), REG, RSV, BDIP,
PTR output hold (MIN = 0.25
B7bCLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS
hold (MIN = 0.25
B8CLKOUT to A(0:31), BADDR(28:30)
RD/WR
(MAX = 0.25
B8aCLKOUT to TSIZ(0:1), REG, RSV, AT(0:3)
requested by control bit CST4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)
B31aCLKOUT falling edge to CS
requested by control bit CST1 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
B31bCLKOUT rising edge to CS
requested by control bit CST2 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 8.00)
B31cCLKOUT rising edge to CS
requested by control bit CST3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.30)
B31dCLKOUT falling edge to CS
requested by control bit CST1 in the
corresponding word in the UPM EBDF = 1
(MAX = 0.375 × B1 + 6.6)
B32CLKOUT falling edge to BS
requested by control bit BST4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)
valid, as
valid, as
valid, as
valid, as
valid, as
1.506.001.506.001.506.001.506.00ns
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00ns
1.508.001.508.001.508.001.508.00ns
7.60 13.80 6.30 12.50 3.80 10.00 3.139.40ns
13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30ns
1.506.001.506.001.506.001.506.00ns
B32aCLKOUT falling edge to BS
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
B32bCLKOUT rising edge to BS
requested by control bit BST2 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 8.00)
B32cCLKOUT rising edge to BS
requested by control bit BST3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
B32dCLKOUT falling edge to BS
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375 × B1 + 6.60)
B33CLKOUT falling edge to GPL
requested by control bit GxT4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)
MPC885/MPC880 Hardware Specifications, Rev. 3
valid, as
valid, as
valid, as
valid, as
valid, as
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00ns
1.508.001.508.001.508.001.508.00ns
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00ns
13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30ns
1.506.001.506.001.506.001.506.00ns
21Freescale Semiconduct or
Page 22
Bus Signal Timing
NumCharacteristic
Table 9. Bus Operation Timings (continued)
33 MHz40 MHz66 MHz80 MHz
Unit
MinMaxMinMaxMinMaxMinMax
B33aCLKOUT rising edge to GPL valid, as
requested by control bit GxT3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
B34 A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by control bi t CST4
in the corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
B34aA(0:31), BADDR(28:30), and D(0:31) to
valid, as requested by control bi t CST1
CS
in the corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
B34bA(0:31), BADDR(28:30), and D(0:31) to
valid, as requested by CST2 in the
CS
corresponding word in UPM
(MIN = 0.75 × B1 – 2.00)
B35A(0:31), BADDR(28:30) to CS
valid, as
requested by control bit BST4 in the
corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
B35aA(0:31), BADDR(28:30), and D(0:31) to
BS valid, as requested by BST1 in the
corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00ns
5.60—4.30—1.80—1.13—ns
13.20—10.50—5.60—4.25—ns
20.70—16.70—9.40—6.80—ns
5.60—4.30—1.80—1.13—ns
13.20—10.50—5.60—4.25—ns
B35bA(0:31), BADDR(28:30), and D(0:31) to
valid, as requested by control bi t BST2
BS
in the corresponding word in the UPM
(MIN = 0.75 × B1 – 2.00)
B36A(0:31), BADDR(28:30), and D(0:31) to
valid, as requested by control bit
GPL
GxT4 in the corresponding word in the
UPM (MIN = 0.25 × B1 – 2.00)
B37UPWAIT valid to CLKOUT falling edge
(MIN = 0.00 × B1 + 6.00)
B38CLKOUT falling edge to UPWAIT valid
(MIN = 0.00 × B1 + 1.00)
B39AS valid to CLKOUT rising edge 9
(MIN = 0.00 × B1 + 7.00)
B40A(0:31), TSIZ(0:1), RD/WR
, BURST , v alid
to CLKOUT rising edge
(MIN = 0.00 × B1 + 7.00)
B41TS valid to CLKOUT rising edge (setup
time) (MIN = 0.00 × B1 + 7.00)
MPC885/MPC880 Hardware Specifications, Rev. 3
20.70—16.70—9.40—7.40—ns
5.60—4.30—1.80—1.13—ns
8
6.00—6.00—6.00—6.00—ns
8
1.00—1.00—1.00—1.00—ns
7.00—7.00—7.00—7.00—ns
7.00—7.00—7.00—7.00—ns
7.00—7.00—7.00—7.00—ns
22Freescale Semiconduct or
Page 23
Bus Signal Timing
NumCharacteristic
Table 9. Bus Operation Timings (continued)
33 MHz40 MHz66 MHz80 MHz
Unit
MinMaxMinMaxMinMaxMinMax
B42CLKOUT rising edge to TS valid (hold
2.00—2.00—2.00—2.00—ns
time) (MIN = 0.00 × B1 + 2.00)
B43AS
negation to memory controller signals
—TBD—TBD—TBD—TBDns
negation (MAX = TBD)
1
For part speeds above 50 MHz, use 9.80 ns for B11a.
2
The timing required fo r BR in put is rel ev ant w hen the M P C885 /880 is s ele cted to work with the i nter nal bus arbiter.
The timing for BG
3
For part speeds above 50 MHz, use 2 ns for B17.
4
The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is ass erted.
5
For part speeds above 50 MHz, use 2 ns for B19.
6
The D(0:31) input timi ngs B20 an d B21 refer to the falling ed ge of th e C LK OUT. This timing is vali d on ly for r ead
input is relevant when the MPC885/880 is selected to work with the external bus arbiter.
accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory
controller , for data bea ts where DL T3 = 1 in the RAM words. (This is only the case whe re data is latche d on the falling
edge of CLKOUT.)
7
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8
The signal UPW AIT is consid ered asy nchronous t o the C LKOUT and synchro nized intern ally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.
9
The AS signal is c ons id ered a sy nc hro nou s to the CLKOUT. The timing B39 is spec ifi ed in order to allow th e behavior
specified in Figure 23.
MPC885/MPC880 Hardware Specifications, Rev. 3
23Freescale Semiconduct or
Page 24
Bus Signal Timing
Figure 5 provides the control timing diagram.
CLKOUT
Outputs
Outputs
Inputs
Inputs
2.0 V
B
2.0 V
0.8 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
C
2.0 V
0.8 V
0.8 V
A
D
2.0 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
AMaximum output delay specification
BMinimum output hold time
CMinimum input setup time specification
DMinimum input hold time specification
Figure 5. Control Timing
Figure 6 provides the timing for the external clock.
CLKOUT
B1
B1
B4
Figure 6. External Clock Timing
B3
B2
B5
MPC885/MPC880 Hardware Specifications, Rev. 3
24Freescale Semiconduct or
Page 25
Bus Signal Timing
Figure 7 provides the timing for the synchronous output signals.
CLKOUT
B8
B7B9
Output
Signals
B8a
Output
Signals
B8b
B7b
Output
Signals
B9B7a
Figure 7. Synchronous Output Signals Timing
Figure 8 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B12B11
TS
, BB
B13
B11B12
TA, BI
B14
B15
TEA
Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
25Freescale Semiconduct or
Page 26
Bus Signal Timing
Figure 9 provides the timing for the synchronous input signals.
CLKOUT
B16
, BI
TA
B16
TEA, KR,
RETRY, CR
B16
BB, BG, BR
B17
B17
B17
Figure 9. Synchronous Input Signals Timing
Figure 10 provides normal case t iming for in put data. It also applie s to normal r ead accesses under the co ntrol of th e
user-programmable machine (UPM) in th e memory cont roller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31]
Figure 10. Input Data Timing in Normal Case
MPC885/MPC880 Hardware Specifications, Rev. 3
26Freescale Semiconduct or
Page 27
Bus Signal Timing
Figure 11 provides the ti m ing for the input data controll ed by the UPM for data beats wh er e DLT3 = 1 in the UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31]
Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 12 through Figure 15 provide the timing for the external bus read controlled by various GPCM factors.
CLKOUT
TS
A[0:31]
CSx
OE
WE[0:3]
D[0:31]
B11B12
B8
B22
B25
B28
B23
B26
B19
B18
Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00)
Table 10 provides the interrupt timing for the MPC885/880.
Table 10. Interrupt Timing
NumCharacteristic
I39IRQ
I40IRQx hold time after CLKOUT2.00ns
I41IRQx pulse width low3.00ns
I42IRQx pulse width high3.00ns
I43IRQx edge-to-edge time4 × T
1
The I39 and I40 tim ing s des cri be the tes tin g c on diti on s u nde r w hi ch the IRQ lines are tested when being defined as
level sensitive. The IRQ
to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC885/880 is able to support.
x valid to CLKOUT rising edge (setup time)6.00ns
lines are synchronized interna lly and do no t have to be assert ed or nega ted with refe rence
1
All Frequencies
MinMax
CLOCKOUT
Figure 25 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
Unit
—
x
IRQ
Figure 25. Interrupt Detection Timing for External Level Sensitive Lines
Figure 26 provides t he interrupt d etection timing for the ex ternal edge-s ensitive lines.
CLKOUT
I41I42
IRQx
I43
I43
Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines
MPC885/MPC880 Hardware Specifications, Rev. 3
36Freescale Semiconduct or
Page 37
Bus Signal Timing
Table 11 shows the PCMCIA timing for the MPC885/880.
Table 11. PCMCIA Timing
33 MHz40 MHz66 MHz80 MHz
NumCharacteristic
MinMaxMinMaxMinMaxMinMax
Unit
A(0:31), REG
strobe asserted
P44
valid to PCMCIA
(MIN = 0.75 × B1 – 2.00)
A(0:31), REG valid to ALE
Figure 30 provides the PCMCIA output port timing for the MPC885/880.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 30. PCMCIA Output Port Timing
Figure 31 provides the PCMCIA input port timing for the MPC885/880.
CLKOUT
P59
P60
Input
Signals
Figure 31. PCMCIA Input Port Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
40Freescale Semiconduct or
Page 41
Bus Signal Timing
Table 13 shows the debug port timing for the MPC885/880.
Table 13. Debug Port Timing
NumCharacteristic
All Frequencies
Unit
MinMax
DSCK cycle time3 × T
D61
DSCK clock pulse width1.25 × T
D62
D63DSCK rise and fall times0.003.00ns
D64DSDI input data setup time8.00ns
D65DSDI data hold time5.00ns
D66DSCK low to DSDO data valid0.0015.00ns
D67DSCK low to DSDO invalid0.002.00ns
CLOCKO
UT
CLO
CKOUT
Figure 32 provides the input timing for the debug port clock.
DSCK
D61
D61
D63
Figure 32. Debug Port Clock Input Timing
D62
D62
D63
-
-
Figure 33 provides the timing for the debug port.
DSCK
DSDI
D66
DSDO
Figure 33. Debug Port Timings
MPC885/MPC880 Hardware Specifications, Rev. 3
D64
D65
D67
41Freescale Semiconduct or
Page 42
Bus Signal Timing
Table 14 shows the reset timing for the MPC885/880.
T a b l e 14. Re se t Timing
33 MHz40 MHz66 MHz80 MHz
NumCharacteristic
MinMaxMinMaxMinMaxMinMax
Unit
CLKOUT to HRESET
impedance
R69
(MAX = 0.00 × B1 + 20.00)
CLKOUT to SRESET high
R70
impedance
(MAX = 0.00 × B1 + 20.00)
RSTCONF pulse width
R71
(MIN = 17.00 × B1)
R72——————————
Configuration data to HRESET
R73
rising edge setup time
(MIN = 15.00 × B1 + 50.00)
Configuration data to RSTCONF
rising edge setup time
R74
(MIN = 0.00 × B1 + 350.00)
Configuration data hold time after
R75
RSTCONF
(MIN = 0.00 × B1 + 0.00)
Configuration data hold time after
R76
HRESET
(MIN = 0.00 × B1 + 0.00)
HRESET
R77
asserted t o data out drive
(MAX = 0.00 × B1 + 25.00)
negation
negation
and RSTCONF
high
—20.00—20.00—20.00—20.00ns
—20.00—20.00—20.00—20.00ns
515.20—425.00—257.60—212.50—ns
504.50—425.00—277.30—237.50—ns
350.00—350.00—350.00—350.00—ns
0.00—0.00—0.00—0.00—ns
0.00—0.00—0.00—0.00—ns
—25.00—25.00—25.00—25.00ns
RSTCONF
high impedance
R78
(MAX = 0.00 × B1 + 25.00)
CLKOUT of last rising edge
before chip three-states
R79
HRESET to data out high
impedance
(MAX = 0.00 × B1 + 25.00)
DSDI, DSCK setup
R80
(MIN = 3.00 × B1)
DSDI, DSCK hold time
R81
(MIN = 0.00 × B1 + 0.00)
SRESET
rising edge for DSDI and DSCK
R82
sample (MIN = 8.00 × B1)
42Freescale Semiconduct or
negated to data out
negated to CLKOUT
MPC885/MPC880 Hardware Specifications, Rev. 3
—25.00—25.00—25.00—25.00ns
—25.00—25.00—25.00—25.00ns
90.90—75.00—45.50—37.50—ns
0.00—0.00—0.00—0.00—ns
242.40—200.00—121.20—100.00—ns
Page 43
Bus Signal Timing
Figure 34 shows the reset timing for the data bus configuration.
HRESET
R71
R76
RSTCONF
R73
R74
D[0:31] (IN)
R75
Figure 34. Reset Timing—Configuration from Data Bus
Figure 35 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
HRESET
RSTCONF
D[0:31] (OUT)
(Weak)
R69
R79
R77R78
Figure 35. Reset Timing—Data Bus Weak Drive During Configuration
MPC885/MPC880 Hardware Specifications, Rev. 3
43Freescale Semiconduct or
Page 44
IEEE 1149.1 Electrical Specifications
Figure 36 provides the reset timing for the debug port configuration.
CLKOUT
R70
R82
SRESET
R80R80
R81
DSCK, DSDI
R81
Figure 36. Reset Timing—Debug Port Configuration
11 IEEE 1149.1 Electrical Specifications
Table 15 provides the JTAG timings for the MPC885/880 shown in Figure 37 to Figure 40.
Table 15. JTAG Timing
All
NumCharacteristic
J82TCK cycle time100.00—ns
J83TCK clock pulse width measured at 1.5 V40.00—ns
J84TCK rise and fall times0.0010.00ns
J85TMS, TDI data setup time5.00—ns
J86TMS, TDI data hold time25.00—ns
J87TCK low to TDO data valid —27.00ns
J88TCK low to TDO data invalid 0.00—ns
J89TCK low to TDO high impedance —20.00ns
J90TRST
J91TRST setup time to TCK low40.00—ns
J92TCK falling edge to output valid—50.00ns
J93TCK falling edge to output valid out of high impedance—50.00ns
J94TCK falling edge to output high impedance—50.00ns
J95Boundary scan input valid to TCK rising edge50.00—ns
assert time100.00—ns
Frequencies
MinMax
Unit
J96TCK rising edge to boundary scan input invalid50.00—ns
MPC885/MPC880 Hardware Specifications, Rev. 3
44Freescale Semiconduct or
Page 45
IEEE 1149.1 Electrical Specifications
TCK
TCK
TMS, TDI
J82J83
J82J83
J84J84
Figure 37. JTAG Test Clock Input Timing
J85
J86
J87
J88J89
TDO
TCK
TRST
Figure 38. JTAG Test Access Port Timing Diagram
J91
J90
Figure 39. JTAG TRST
Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
45Freescale Semiconduct or
Page 46
CPM Electrical Characteristics
TCK
J92J94
Output
Signals
J93
Output
Signals
J95J96
Output
Signals
Figure 40. Boundary Scan (JTAG) Timing Diagram
12 CPM Electrical Characteristics
This section pr ovi des t he AC and DC electrical specifications for the communicat ions processor module (CPM ) of
the MPC885/880.
12.1 PIP/PIO AC Electrical Specifications
Table 16 provides the PIP/PIO AC timings as shown in Figure 41 to Figure 45.
Table 16. PIP/PIO Timing
NumCharacteristic
21Data-in setup time to STBI low0—ns
22Data-In hold time to STBI high0—clk
23STBI pulse width1.5—clk
24STBO pulse width1 clk – 5 ns—n s
25Data-out setup time to STBO low2—clk
26Data-out hold time from STBO high5—clk
27STBI low to STBO low (Rx interlock)—4.5clk
28STBI low to STBO high (Tx interlock)2—clk
29Data-in setup time to clock high15—ns
30Data-in hold time from clock high7.5—ns
31Clock low to data-out valid (CPU writes data, control, or direction)—25ns
12.2 Port C Interrupt AC Electrical Specifications
Table 17 provides the timings for port C interrupts.
Table 17. Port C Interrupt Timing
NumCharacteristic
35Port C interrupt pulse width low (edge-triggered mode)55—ns
36Port C interrupt minimum time between active edges55—ns
33.34 MHz
Unit
MinMax
MPC885/MPC880 Hardware Specifications, Rev. 3
48Freescale Semiconduct or
Page 49
CPM Electrical Characteristics
Figure 46 shows the port C interrupt detection timing.
36
Port C
(Input)
35
Figure 46. Port C Interrupt Detection Timing
12.3 IDMA Controller AC Electrical Specifications
Table 18 provides the IDMA controller timings as shown in Figure 47 to Figure 50.
Table 18. IDMA Controller Timing
NumCharacteristic
40DREQ setup time to clock high7—ns
41DREQ hold time from clock high
1
All Frequencies
Unit
MinMax
TBD—ns
42SDACK assertion delay from clock high—12ns
43SDACK negation delay from clock low—12ns
44SDACK negation delay from TA low—20ns
45SDACK negation delay from clock high—15ns
46TA assertion to falling edge of the clock setup time (applies to external TA)7—ns
1
Applies to high-to-low mode (EDM=1)
CLKO
(Output)
41
40
DREQ
(Input)
Figure 47. IDMA External Requests Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
49Freescale Semiconduct or
Page 50
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
DA T A
TA
(Input)
SDACK
43
46
Figure 48. SDACK Timing Diagram—Peripheral Write, Externally-Generate d TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
4244
DA T A
TA
(Output)
SDACK
Figure 49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
MPC885/MPC880 Hardware Specifications, Rev. 3
50Freescale Semiconduct or
Page 51
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
DA T A
TA
(Output)
SDACK
4245
Figure 50. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
12.4 Baud Rate Generator AC Electrical Specifications
Table 19 provides the baud rate generator timings as shown in Figure 51.
Table 19. Baud Rate Generator Timing
All Frequencies
NumCharacteristic
MinMax
50BRGO rise and fall time —10ns
51BRGO duty cycle4060%
52BRGO cycle40—ns
50
BRGOX
51
52
50
51
Unit
Figure 51. Baud Rate Generator Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
12.5 Timer AC Electrical Specifications
Table 20 provides the general-purpose timer timings as shown in Figure 52.
NumCharacteristic
61TIN/TGATE rise and fall time10—ns
62TIN/TGATE low time1—clk
63TIN/TGATE high time2—clk
64TIN/TGATE cycle time3—clk
65CLKO low to TOUT valid325ns
100RCLK1 and TCLK1 width high
101 RCLK1 and TCLK1 width low1/SYNCCLK + 5—ns
102 RCLK1 and TCLK1 rise/fall time—15.00ns
103 TXD1 active delay (from TCLK1 falling edge)0.0050.00ns
104RTS1 active/inactive delay (from TCLK1 falling edge)0.0050.00ns
105CTS1 setup time to TCLK1 rising edge5.00—ns
106RXD1 setup time to RCLK1 rising edge5.00—ns
107RXD1 hold time from RCLK1 rising edge
108 CD1 setup time to RCLK1 rising edge5.00—ns
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
2
Also applies to CD and CTS hold time when they are used as external sync signals.
1
2
1/SYNCCLK—ns
5.00—ns
Unit
Table 23 provides the NMSI internal clock timing.
Table 23. NMSI Internal Clo ck Timing
All Frequencies
NumCharacteristic
MinMax
100RCLK1 and TCLK1 frequency
102 RCLK1 and TCLK1 rise/fall time——ns
103 TXD1 active delay (from TCLK1 falling edge)0.0030.00ns
104RTS1 active/inactive delay (from TCLK1 falling edge)0.0030.00ns
105CTS1 setup time to TCLK1 rising edge40.00—ns
106RXD1 setup time to RCLK1 rising edge40.00—ns
107RXD1 hold time from RCLK1 rising edge
108CD1 setup time to RCLK1 rising edge40.00—ns
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1.
2
Also applies to CD and CTS hold time when they are used as external sync signals
1
2
0.00SYNCCLK/3MHz
0.00—ns
Unit
MPC885/MPC880 Hardware Specifications, Rev. 3
59Freescale Semiconduct or
Page 60
CPM Electrical Characteristics
Figure 58 through Figure 60 show the NMSI timings.
RCLK1
RxD1
(Input)
CD1
(Input)
CD1
(SYNC Input)
TCLK1
106
102
102
102101
100
107
Figure 58. SCC NMSI Receive Timing Diagram
102101
100
108
107
TxD1
(Output)
RTS1
(Output)
CTS1
(Input)
CTS1
(SYNC Input)
103
105
104
Figure 59. SCC NMSI Transmit Timing Diagram
104
107
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
TCLK1
102
TxD1
(Output)
RTS1
(Output)
CTS1
(Echo Input)
102101
100
103
104
105
Figure 60. HDLC Bus Timing Diagram
12.8 Ethernet Electrical Specifications
Table 24 provides the Ethernet timings as shown in Figure 61 to Figure 63.
Table 24. Ethernet Timing
104107
All Frequencies
NumCharacteristic
MinMax
120CLSN width high40—ns
121RCLK1 rise/fall time —15ns
122RCLK1 width low40—ns
123RCLK1 clock period
124RXD1 setup time20—ns
125RXD1 hold time5—ns
126RENA active delay (from RCLK1 rising edge of the last data bit)10—ns
127RENA width low10 0—ns
128TCLK1 rise/fall time —15ns
129TCLK1 width low40—ns
130TCLK1 clock period
131TXD1 active delay (from TCLK1 rising edge)—50ns
132TXD1 inactive delay (from TCLK1 rising edge)6.550ns
133TENA active delay (from TCLK1 rising edge)1050ns
1
1
80120ns
99101ns
Unit
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
Table 24. Ethernet Timing (continued)
All Frequencies
NumCharacteristic
MinMax
134TENA inactive delay (from TCLK1 rising edge)1050ns
138CLKO1 low to SDACK asserted
139CLKO1 low to SDACK negated
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
2
2
—20ns
—20ns
CLSN(CTS1)
(Input)
120
Figure 61. Ethernet Collision Timing Diagram
RCLK1
Unit
RxD1
(Input)
RENA(CD1)
(Input)
121
121
124123
125
126
Figure 62. Ethernet Receive Timing Diagram
Last Bit
127
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
TCLK1
TxD1
(Output)
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
128
131121
133134
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
1.
If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
2.
CSL bit is set in the buffer descriptor at the end of the frame transmission.
128
129
132
Figure 63. Ethernet Transmit Timing Diagram
12.9 SMC Transparent AC Electrical Specifications
Table 25 provides the SMC transparent timings as shown in Figure 64.
T able 25. SMC Transp arent Timing
All Frequencies
NumCharacteristic
MinMax
150SMCLK clock period
151SMCLK width low50—ns
151A SMCLK width high50—ns
152SMCLK rise/fall time —15ns
153SMTXD active delay (from SMCLK falling edge)1050ns
154SMRXD/SMSYNC setup time20—ns
155RXD1/SMSYNC hold time5—ns
1
SyncCLK must be at least twice as fast as SMCLK.
1
100—ns
Unit
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
SMCLK
152
SMTXD
(Output)
SMSYNC
SMRXD
(Input)
NOTE:
This delay is equal to an integer number of charac ter-length clocks.1.
152151
NOTE
154153
155
154
155
151
150
Figure 64. SMC Transparent Timing Diagram
12.10SPI Master AC Electrical Specifications
Table 26 provides the SPI master timings as shown in Figure 65 and Figure 66.
Table 26. SPI Master Timing
All Frequencies
NumCharacteristic
MinMax
160MASTER cycle time41024t
161MASTER clock (SCK) high or low time2512t
162MASTER data setup time (inputs)15—ns
163Master data hold time (inputs)0—ns
164Master data valid (after SCK edge)—10ns
165Master data hold time (outputs)0—ns
166Rise time output—15ns
167Fall time output—15ns
Unit
cyc
cyc
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
SPICLK
(CI=0)
(Output)
161160
SPICLK
(CI=1)
(Output)
163
162
166167161
167
166
SPIMISO
(Input)
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
msbDatalsbmsb
165164
167166
msblsbmsb
Data
Figure 65. SPI Master (CP = 0) Timing Diagram
166167161
161160
162
163
166
msbDatalsbmsb
167
165164
167166
SPIMOSI
(Output)
msblsbmsb
Data
Figure 66. SPI Master (CP = 1) Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
12.11SPI Slave AC Electrical Specifications
Table 27 provides the SPI slave timings as shown in Figure 67 and Figure 68.
Table 27. SPI Slave Timing
NumCharacteristic
All Frequencies
Unit
MinMax
170Slave cycle time2—t
171Slave enable lead time15—ns
172Slave enable lag time15—ns
173Slave clock (SPICLK) high or low time1—t
174Slave sequential transfer delay (does not require deselect)1—t
175Slave data setup time (inputs)20—ns
176Slave data hold time (inputs)20—ns
177Slave access time—50ns
SPISEL
(Input)
171172
174
SPICLK
(CI=0)
(Input)
181182173
173170
SPICLK
(CI=1)
(Input)
177182
180
181
178
cyc
cyc
cyc
SPIMISO
(Output)
SPIMOSI
(Input)
175179
176182
msblsbmsb
DatamsblsbmsbUndef
181
Data
Figure 67. SPI Slave (CP = 0) Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
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CPM Electrical Characteristics
SPISEL
(Input)
171170
SPICLK
(CI=0)
(Input)
173
SPICLK
(CI=1)
(Input)
177182
173
180
172
174
181182
181
178
SPIMISO
(Output)
175179
SPIMOSI
(Input)
msb
176182
msblsb
Data
181
Data
lsbUndef
Figure 68. SPI Slave (CP = 1) Timing Diagram
12.12I2C AC Electrical Specifications
Table 28 provides the I2C (SCL < 100 KHz) timings.
Table 28. I2C Timing (SCL < 100 KHZ)
All Frequencies
NumCharacteristic
MinMax
200SCL clock frequency (slave)0100KHz
200SCL clock frequency (master)
202Bus free time between transmissions 4.7—µs
203Low period of SCL4.7—µs
1
1.5100KHz
msb
msb
Unit
204High period of SCL4.0—µs
205Start condition setup time4.7—µs
206Start condition hold time4.0—µs
207Data hold time0—µs
208Data setup time250—ns
209SDL/SCL rise time —1µs
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CPM Electrical Characteristics
Table 28. I2C Timing (SCL < 100 KHZ) (continued)
All Frequencies
NumCharacteristic
MinMax
210SDL/SCL fall time —300ns
211Stop condition setup time4.7—µs
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Table 29 provides the I2C (SCL > 100 KHz) timings.
2
Table 29. I
NumCharacteristicExpression
200SCL clock frequency (slave)fSCL0BRGCLK/48Hz
200SCL clock frequency (master)
202Bus free time between transmissions —1/(2.2 × fSCL)—s
1
C Timing (SCL > 100 KHZ)
All Frequencies
MinMax
fSCLBRGCLK/16512BRGCLK/48Hz
Unit
Unit
203Low period of SCL—1/(2.2 × fSCL)—s
204High period of SCL—1/(2.2 × fSCL)—s
205Start condition setup time—1/(2.2 × fSCL)—s
206Start condition hold time—1/(2.2 × fSCL)—s
207Data hold time—0—s
208Data setup time—1 /(40 × fSCL)—s
209SDL/SCL rise time ——1/(10× fSCL)s
210SDL/SCL fall time ——1/(33 × fSCL)s
211Stop condition setup time—1/2(2.2 × fSCL)—s
1
SCL frequency is give n by SCL = BrgClk_freq uency / ((BRG reg ister + 3)× pre_scaler × 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
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UTOPIA AC Electrical Specifications
Figure 69 shows the I2C bus timing.
SDA
202
205
SCL
206209211210
203
207
204
208
Figure 69. I2C Bus Timing Diagram
13 UTOPIA AC Electrical Specifications
Table 30, Table 31, and Table 32, show the AC electrical sp ecifications for the UTOPIA interface.
T able 30. UTOPIA Master (Muxed Mode) Electrical Specifications
NumSignal CharacteristicDirectionMinMaxUnit
U1UtpClk rise/fall time (internal clock option) Output4 nsns
Duty cycle5050%
Frequency33MHz
U2UTPB, SOC, RxEnb
PHREQ and PHSEL active delay in multi-PHY mode)
U3UTPB, SOC, Rxclav and Txclav setup timeInput4 nsns
, TxEnb, RxAddr, and TxAddr active delay (and
Output2 ns16 nsns
U4UTPB, SOC, Rxclav and Txclav hold timeInput1 nsns
Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications
NumSignal CharacteristicDirectionMinMaxUnit
U1UtpClk rise/fall time (Internal clock option)Output4 nsns
Duty cycle5050%
Frequency33MHz
U2UTPB, SOC, RxEnb
(PHREQ and PHSEL active delay in multi-PHY mode)
U3UTPB_Aux, SOC_Aux, Rxclav and Txclav setup timeInput4 nsns
U4UTPB_Aux, SOC_Aux, Rxclav and Txclav hold timeInput1 nsns
, TxEnb, RxAddr and TxAddr active delay
MPC885/MPC880 Hardware Specifications, Rev. 3
Output2 ns16 nsns
69Freescale Semiconduct or
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UTOPIA AC Electrical Specifications
Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
NumSignal CharacteristicDirectionMinMaxUnit
U1UtpClk rise/fall time (external clock option)Input4 nsns
Duty cycle4060%
Frequency33MHz
U2 UTPB, SOC, Rxclav and Txclav active delayOutput2 ns16 nsns
U3UTPB_AUX, SOC_Aux, RxEnb
time
U4UTPB_AUX, SOC_Aux, RxEnb
time
, TxEnb, RxAddr, and TxAddr setup
, TxEnb, RxAddr, and TxAddr hold
Figure 70 shows signal timings during UTOPIA receive operations.
U1
UtpClk
U2
PHREQn
U3U4
3
RxClav
RxEnb
UTPB
SOC
High-Z at MPH Y
U2
2
Input4 nsns
Input1 nsns
U1
4
High-Z at MPH Y
U3
U4
3
4
Figure 70. UTOPIA Receive Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
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USB Electrical Characteristics
YP
Figure 71 shows signal timings during UTOPIA transmit operations.
UtpClk
U2
5
PHSELn
TxClav
TxEnb
UTPB
SOC
High-Z at MPH YHigh-Z at Multi -PH
U2
2
U2
5
Figure 71. UTOPIA Transmit Timing
14 USB Electrical Characteristics
This section provides the AC timings for the USB interface.
U1
1
U3U4
3
4
U1
14.1 USB Interface AC Timing Specifications
The USB Port uses the transmit clock on SCC1. Table 33 lists th e USB interface timings.
Table 33. USB Interface AC Timing Specifications
NameCharacteristic
US1USBCLK frequency of operation
Low speed
Full speed
US4USBCLK duty cycle (measured at 1.5 V)4555%
1
USBCLK accuracy should be ±500 ppm or better. USBCLK may be stopped to conserve power.
1
All Frequencies
MinMax
6
48
Unit
MHz
MHz
15 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
MPC885/MPC880 Hardware Specifications, Rev. 3
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FEC Electrical Characteristics
15.1 MII and Reduced MII Receive Signal Timing
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The reduced MII
(RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK
frequency
Table 34 provides information on the MII and RMII receive signal timing.
– 1%.
Table 34. MII Receive Signal Timing
NumCharacteristicMinMaxUnit
M1MII_RXD[3:0], MII_RX_DV, MII_RX_ERR to MII_RX_CLK setup5—ns
M2MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold5—ns
M3MII_RX_CLK pulse width high35%65%MII_RX_C LK period
M4MII_RX_CLK pulse width low35%65%MII_RX_CLK period
M1_RMII RMII_RXD[1:0], RMII_CRS_DV , RMII_RX_ERR to RMII_REFCLK
setup
M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV , RMII_RX_ERR
hold
Figure 72 shows MII receive signal timing.
M3
MII_RX_CLK (input)
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M1
Figure 72. MII Receive Signal Timing Diagram
M2
4—ns
2—ns
M4
15.2 MII and Reduced MII Transmit Signal Timing
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. The RMII
transmitter functions correctly up to a RMII_REFCLK maximum freq uency of 50 MHz +1%. The re is no minimum
frequency requirement . In a ddi ti on, t he processor clock frequenc y must exc eed the MII_TX_CLK frequency
MPC885/MPC880 Hardware Specifications, Rev. 3
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Page 73
FEC Electrical Characteristics
Table 35 provides info rmation on the MII and RMII transmit signal timing.
Table 35. MII Transmit Signal Timing
NumCharacteristicMinMaxUnit
M5MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid5—ns
M6MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid—25ns
M20_R
M21_R
RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup 4—ns
MII
RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
MII
edge
M7MII_TX_CLK and RMII_REFCLK pulse width high35%65%MII_TX_CLK or
M8MII_TX_CLK and RMII_REFCLK pulse width low35%65%MII_TX_CLK or
2—ns
Figure 73 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (input)
RMII_REFCLK
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M5
M8
RMII_REFCLK
period
RMII_REFCLK
period
M6
Figure 73. MII Transmit Signal Timing Diagram
15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 36 provides information on the MII async inputs signal timing.
Table 36. MII Async Inputs Signal Timing
NumCharacteristicMinMaxUnit
M9MII_CRS, MII_COL minimum pulse width1.5—MII_TX_CLK period
MPC885/MPC880 Hardware Specifications, Rev. 3
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FEC Electrical Characteristics
Figure 74 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 74. MII Async Inputs Timing Diagram
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 37 provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 37. MII Serial Management Channel Timing
NumCharacteristicMinMaxUnit
M10MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
M11MII_MDC falling edge to MII_MDIO output valid (max prop delay)—25ns
M12MII_MDIO (input) to MII_MDC rising edge setup10—ns
M13MII_MDIO (input) to MII_MDC rising edge hold0—ns
M14MII_MDC pulse width high40%60%MII_MDC period
M15MII_MDC pulse width low40%60%MII_MDC period
0—ns
Figure 75 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
M12
M13
Figure 75. MII Serial Management Channel Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
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Mechanical Data and Ordering Information
16 Mechanical Data and Ordering Information
Table 38 identifies the available packages and operating frequencies for the MPC885/880 derivative devices.
Table 38. Available MPC885/880 Packages/Frequencies
Package TypeTemperature (Tj) Frequency (MHz)Order Number
Plastic ball grid array
ZP suffix — Leaded
VR suffix — Lead-Free are available as needed
Plastic ball grid array
CZP suffix — Leaded
CVR suffix — Lead-Free are available as needed
0°C to 95°C66KMPC885ZP66
KMPC880ZP66
MPC885ZP66
MPC880ZP66
80KMPC885ZP80
KMPC880ZP80
MPC885ZP80
MPC880ZP80
133KMPC885ZP133
KMPC880ZP133
MPC885ZP133
MPC880ZP133
-40°C to 100°C66KMPC885CZP66
KMPC880CZP66
MPC885CZP66
MPC880CZP66
133KMPC885CZP133
KMPC880CZP133
MPC885CZP133
MPC880CZP133
MPC885/MPC880 Hardware Specifications, Rev. 3
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Mechanical Data and Ordering Information
16.1 Pin Assignments
Figure 76 shows the top-view pinout of the PBGA package. For additional information, see the MPC885
Figure 77 shows the mechanical dimensions of the PBGA package.
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
MPC885/MPC880 Hardware Specifications, Rev. 3
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Document Revision History
17 Document Revision History
Table 40 lists significant changes between revisions of this hardware specification.
Table 40. Document Revision History
Revision
Number
002/2003Initial rev isi on .
0.104/2003Added pino ut and pinou t assignment s tabl e. Added the USB timing to Section 14 . Added
0.205/2003Made the chan ges to the RMII T iming, Made su re all the V
0.305/2003Corrected the signals that had overlines on them.
0.45/2003Changed the pin descriptions for PD8 and PD9.
0.55/2003Changed some more typos, put in the phsel and phreq pins. Corrected the USB timing.
0.66/2003Changed the pin descriptions per the June 22 spec.
0.77/2003Added the RxClav and TxClav signals to PC15.
0.88/2003Added the Reference to USB 2.0 to the Features l ist an d rem ov ed 1.1 from USB o n th e
0.98/2003Changed the USB description to full-/low-speed compatible.
1.09/2003Added the DSP information in the Features list
DateChanges
the Reduced MII to Section 15. Removed the Data Parity. Made some changes to the
Features list.
on the pinout diagram. Changed the SPI Master Timing Specs. 162 and 164.
block diagrams.
Fixed table formatting.
Nontechnical edits.
Released to the external web.
DDL
, V
, and GND show up
DDH
2.012/2003Changed the maximum operating frequency to 133 MHz.
Put in the orderable part numbers that are orderable.
Put the timing in the 80 MHz column.
Rounded the timings to hundredths in the 80 MHz column.
Put the pin numbers in footnotes by the maximum currents in Table 6.
Changed 22 and 41 in the Timing.
Put in the Thermal numbers.
3.07/22/2004 • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for
Integer Values
• Added a footnote to Spec 41 specifying that EDM = 1
• Added RMII1_EN under M1II_EN in Table 36 Pin Assignments
• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL
Max of the I2C Sta nda rd
• Put the new part numbers in the Ordering Information Section
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Document Revision History
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MPC885/MPC880 Hardware Specifications, Rev. 3
Freescale Semiconduc tor91
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MPC885EC
Rev. 3
07/2004
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