Freescale MPC875, MPC870 User Guide

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Freescale Semiconductor

MPC875/MPC870 Hardware Specifications

This hardware specification contains detailed informatio n on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. This hardware specification covers the following topics:

1Overview

The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. Thermal Calculation and Measurement . . . . . . . . . . 11

8. Power Supply and Power Sequenc in g . . . . . . . . . . . 13

9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 14

10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44

13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46

14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67

15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67

16. Mechanical Dat a and Ordering Information . . . . . . . 71

17. Document Revision History . . . . . . . . . . . . . . . . . . . 82

MPC875EC

Rev. 3.0, 07/2004

Contents

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Features

Table 1 shows the functionality supported by the members of the MPC875/MPC870.

Table 1. MPC8 75/ 870 Devi ces

Cache Ethernet

Part

I Cache D Cache 10BaseT 10/100

MPC875 8 Kbyte 8 Kbyte 1 2 1 1 1 Yes MPC870 8 Kbyte 8 Kbyte — 2 — 1 1 No

SCC SMC USB

Security

Engine

2Features

The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM).

The following list summarizes the key MPC875/870 features:

• Embedded MPC8xx core up to 133 MHz

• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) — The 133-MHz core frequency supports 2:1 mode only. — The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.

• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch and without conditional execution. — 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)

– Instruction cache is two-way, set-associative with 256 sets in 2 blocks – Data cache is two-way, set-associative with 256 sets – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

– Caches are physi cally addresse d, implement a leas t recentl y used (LRU) repl acement algori thm, and

are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces

and 16 protection groups

— Advanced on-chip emulation debug mode

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• 32 address lines

• Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS

lines, four WE lines, and one OE line

to support a DRAM bank.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

2 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Features

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbyte–256 Mbyte) — Selectable write protection — On-chip bus arbitration logic

• General-purpose timers

— Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting. — Interrupt can be masked on reference match and event capture

• Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that

interface through MII and/or RMII interfaces

• System integration unit (SIU)

— Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Clock synthesizer — Decrementer and time base — Reset controller — IEEE 1149.1 test access port (JTAG)

• Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,

802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:

— Data encryption standard execution unit (DEU)

– DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rinjdael symmetric key cipher – ECB, CBC, and counter modes – 128-, 192-, and 256-bit key lengths

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm

— Master/slave logic, w ith DMA

– 32-bit address/32- bit data – Operation at 8xx bus frequency

— Crypto-channel supporting multi-command descriptors

– Integrated controller managing crypto-execution units – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

• Interrupts

— Six external interrupt request (IRQ) lines

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 3

Features

— 12 port pins with interrupt capability — 23 internal interrupt sources — Programmable priority between SCCs — Programmable highest priority request

• Communications processor module (CPM) — RISC controller — Communication-specifi c commands (for example,

RESTART TRANSMIT)

GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

— Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — Several serial DMA (SDMA) channels to support the CPM — Three parallel I/O registers with open-drain capability

•On-chip 16

× 16 multiply accumulate controller (MAC)

— One operation per clock (two-clock latency, one-clock blockage) — MAC operates concurrently with other instructions — FIR loop—Four clocks per four multiplies

• Four baud-rate generators — Independent (can be connected to any SCC or SMC) — Allows changes during operation — Autobaud support option

• SCC (seria l communica tion controller) — Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support point-to-point protocol (PPP) —AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC))

• SMC (serial management channel) — UART (l ow-s peed operation) — Transparent

• Universal serial bus (USB)—Supports operatio n as a USB function end point, a USB host cont roller , or both for testing purposes (loopback diagnostics)

— USB 2.0 full-/low-speed compatible — The USB function mode has the following features:

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

4 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

– CRC16 generation and checking – CRC5 checking – NRZI encoding/decoding with bit stuffing – 12- or 1.5-Mbps data rate – Flexible data buffers with multiple buffe rs per frame – Automatic retransmission upon transmit error

— The USB host controller has the following features:

– Supports control, bulk, interrupt, and isochronous data transfers – CRC16 generation and checking – NRZI encoding/decoding with bit stuffing – Supports both 12- and 1. 5-Mbps data rates (automatic g eneration of preamble tok en and data

rate configuration). Note that low-speed operation requires an external hub. – Flexible data buffers with multiple buffe rs per frame – Supports local loopback mode for diagnostics (12 Mbps only)

• Serial peripheral inte rface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus

• Inter-integrated circuit (I

C) port — Supports master and slave modes — Supports a multiple-master environment

• The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb). — Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — Allows dynamic changes — Can be internally connected to two serial channels (one SCC and one SMC)

• PCMCIA interface — Master (so cket) interface, release 2.1-compliant — Supports one independent PCMCIA socket on the MPC875/MPC870 — 8 memory or I/O windows supported

• Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data — Supports conditions: = ≠ < > — Each watchpoint can generate a break point internally.

• Normal high and normal low power modes to conserve power

• 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility

• The MPC875/870 comes in a 256-pin ball grid array (PBGA) package.

Features

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 5

Features

The MPC875 block diagram is shown in Figure 1.

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

FIFOs

10/100 BaseT

Media Access

Control

MIII/RMII

Instruction

Bus

Load/Store

Bus

8-Kbyte

Instruction Cache

Instruction MMU

32-Entry ITLB

8-Kbyte

Data Cache

Data MMU

32-Entry DTLB

Parallel I/O

4 Baud Rate

Generators

Parallel Interface Port

Slave/Master IF

Timers

Controllers

32-Bit RISC Controller

Unified

Bus

Interrupt

and Program

ROM

System Interface Unit (SIU)

Bus Interface

Security Engine

Controller

Channel

8-Kbyte

Dual-Port RAM

Memory Controller

Internal

Unit

System Functions

PCMCIA-ATA Interface

External

Bus Interface

Unit

AESU DEU MDEU

Virtual IDMA Serial DMAs

and

USB

SCC4

Time Slot Assigner

Serial Interface

Figure 1. MPC875 Block Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

SPISMC1

I2C

6 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

The MPC870 block diagram is shown in Figure 2.

Maximum Tolerated Ratings

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

FIFOs

10/100 BaseT

Media Access

Control

MIII / RMII

Instruction

Bus

Load/Store

Bus

8-Kbyte

Instruction Cache

Instruction MMU

32-Entry ITLB

8-Kbyte

Data Cache

Data MMU

32-Entry DTLB

Parallel I/O

4 Baud Rate

Generators

Parallel Interface Port

Slave/Master IF

Timers

Controllers

32-Bit RISC Controller

Unified

Bus

Interrupt

and Program

ROM

System Interface Unit (SIU)

Bus Interface

8-Kbyte

Dual-Port RAM

Memory Controller

Internal

Unit

System Functions

PCMCIA-ATA Interface

External

Bus Interface

Unit

Virtual IDMA and

Serial DMAs

USB

Serial Interface

SPISMC1

I2C

Figure 2. MPC870 Block Diagram

3 Maximum Tolerated Ratings

This section pro vides th e maximum tole rated vo ltage an d temperat ure range s for t he MPC875/8 70. Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 7

Maximum Tolerated Ratings

Supply voltage

Table 2. Maximum Tolerated Ratings

Rating Symbol Value Unit

DDL

voltage)

(core

–0.3 to 3.4 V

DDH

(I/O

–0.3 to 4 V

voltage) V

DDSYN

Difference

–0.3 to 3.4 V

<100 mV

between

and

DDL

DDSYN

Input voltage

Storage temperature range T

The power supply of the device must start its ramp from 0.0 V.

Functional ope rati ng co nditions are provid ed w ith t he D C electrical specific ati ons i n Table 6. Absolute maximum

stg

GND – 0.3 to

DDH

–55 to +150 °C

ratings are stress ratings only ; functional op eration at t he maxima is not guaran teed. S tress bey ond those li sted may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power up and normal operation (tha t is, if the MPC87 5/870 is unp owered, a volt age gr eater than 2.5 V must not be applied to its inputs).

Table 3. Operating Temperatures

Rating Symbol Value Unit

Temperature

Temperature (extended) T

Minimum temperature s are guar anteed a s ambient te mperatu re, TA. Maximum temperatu res are guaran teed as

junction temperature, T

(standard)

A(min)

j(max)

A(min)

j(max)

0°C

95 °C –40 °C 100 °C

This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal prec autions be taken to avoid applicat ion of any voltages higher than maxi mum-rated voltages to this high-i mpeda nce ci rcuit. Reliabilit y o f oper ation is enhanced i f unus ed inputs are tied t o a n a ppropriate logic voltage level (for example, either GND or V

MPC875/MPC870 Hardware Specifications, Rev. 3.0

8 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

DDH

Thermal Characteristics

4 Thermal Characteristics

Table 4 shows the thermal characteristics for the MPC875/870.

Table 4. MPC875/870 Thermal Resistance Data

Rating Environment Symbol Value Unit

Junction-to-ambient

Natural convection Single-layer board (1s) R

Four-layer board (2s2p) R

Airflow (200 ft/min) Single-layer board (1s) R

Four-layer board (2s2p) R Junction-to-board Junction-to-case Junction-to-package top

Natural convection Ψ Airflow (200 ft/min) Ψ

Junction temperature is a function of on-chip power dissi pa tion, packa ge ther mal resis tan ce, mounting sit e (boa rd)

temperature, ambi ent tem peratu re, airfl ow, power dissipation of o ther co mpone nt s o n the b oard, a nd boa rd therm al resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resista nce b etw ee n t he di e a nd the printed cir cuit b oard per JEDEC JESD51 -8. Boar d te mp era t ure is

measured on the top surface of the board near the package.

Indicates the average thermal resist an ce be tw een the di e a nd the case top surface as me as ured by th e c ol d pl ate

method (MIL SPEC-883 Method 1012.1) with the cold pl ate temperature us ed for the c ase temperature. F or exposed pad packages whe re the pad would be expected to be s old ere d, junction-to-case therma l res is t an ce is a si mu lated value from the junction to the exposed pad without contact resistance.

Thermal characteri zation parameter ind ic ati ng the te mp era ture difference b etwee n the package top an d the junction

temperature per JEDEC JESD51-2.

θJA

θJMA

θJB

θJC

43 °C/W 29 36 26 20 10

2 2

5 Power Dissipation

Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are

equal, and 2:1, where CPU frequency is twice bus speed.

Table 5. Power Dissipation (PD)

Die Revision

Bus

Mode

Frequency Typical

66 MHz 310 390 mW

1:1

80 MHz 350 430 mW

2:1 133 MHz 430 495 mW

Typical power dissipation is measured at V

DDL

= V

DDSYN

= 1.8 V, and V

is at 3.3 V.

DDH

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 9

Maximum

Unit

DC Characteristics

Maximum power dissipation at V

The values in Table 5 represent V include I/O power dissipation over V widely by application due to buffer current, depending on external circuitry.

DDL

= V

= 1.9 V, and V

DDSYN

is at 3.5 V.

DDH

NOTE

-based power diss ipati on an d d o not

DDL

. I/O power d issipation varies

DDH

The V

DDSYN

power dissipation is negligible.

6 DC Characteristics

Table 6 provides the DC electrical characteristics for the MPC875/870.

T able 6. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltag e V

Input high voltage (all inputs except EXTAL and EXTCLK) Input low voltage

EXTAL, EXTCLK input high voltage V Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and

DSDI pins) for 5-V tolerant pins

(I/O) 3.135 3.465 V

DDH

(Core) 1.7 1.9 V

DDL

DDSYN

1.7 1.9 V — 100 mV

Difference

between

and

DDL

DDSYN

V V

IHC

2.0 3.465 V

GND 0.8 V

0.7 × V

DDH

— 100 µA

Input leakage current, Vin = V

(except TMS, TRST, DSCK, and

DDH

—10µA

DSDI) Input leakage current, Vin = 0 V (exc ept TMS, TRST

, DSCK and DSDI

—10µA

pins) Input capacitance

Output high voltage, IOH = –2.0 mA, V

DDH

= 3.0 V

—20pF

2.4 — V

except XTAL and open-drain pins Output low voltage

IOL = 2.0 mA (CLKOUT) IOL = 3.2 mA IOL = 5.3 mA

5 6

—0.5V

IOL = 7.0 mA (TXD1/PA14, TXD2/PA12) IOL = 8.9 mA (TS

The difference between V

The signals P A[0:15], PB[14:31 ], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST , TMS, MII1_TXEN, MII_M DIO

, TA, TEA, BI, BB, HRESET, SRESET)

DDL

and V

cannot be more than 100 mV.

DDSYN

are 5-V tolerant. The minimum voltage is still 2.0 V.

VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

10 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Thermal Calculation and Measurement

Input capaci tance is periodically sampled.

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(0:1), PA(0: 4), P A(6:7), PA(10:11), PA15,

PB19, PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL.

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,

(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A , CE1_A, CE2_A,

GPL_A OP(0:3) BADDR(28:30

7 Thermal Calculation and Measurement

For the foll owing discu ssions, PD = (V

DDL

× I

DDL

) + P

, where P

I/O

is the power dissipation of the I/O

I/O

drivers.

NOTE

The V

DDSYN

power dissipation is negligible.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:

= TA + (R

θJA

× PD)

where:

= ambient temperature ºC

= package j unction-to-a mbient ther mal resistance (ºC/W)

θJA

= power dissipation in package

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of ther mal pe rf ormance. However , the answer is onl y an es timate; test cases have demonstrated that errors of a factor of two (in the quantity T

) are possible.

J–TA

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically, thermal resistance has frequently been ex pressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

θJA

= R

θJC

+ R

θCA

where:

= junction-to-ambient thermal resistance (ºC/W)

θJA

= junction-to-case thermal resistance (ºC/W)

θJC

= case-to-ambient thermal resistance (ºC/W)

θCA

is device-related and cannot be influenced by the user. The user adjusts the thermal environment to

θJC

affect the case-to-ambient thermal resistance, R

. For instance, the user can change the airflow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful for ceramic pack age s wi th heat sinks where some 90% of the heat flows th rou gh the case and the h eat sink to the ambient environment. For most packages, a better model is required.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 11

Thermal Calculation and Measuremen t

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junc ti on-to- board and a ju nctio n-to- case t herma l res ista nce. The j unc tion- to-ca se the rmal re sist ance covers the situ ation where a heat sink i s u sed or where a subst antia l am ount of heat is di ssipa ted from t he top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages and especially PBGA packa ges is st rongl y depende nt on the bo ard tempe ratur e. If the boa rd temper atur e is known, an estimate of the junction temperature in the environment can be made using the following equation:

= TB + (R

where:

= junction-to-board thermal resistance (ºC/W)

θJB

= board temperature ºC

= power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane.

θJB

× PD)

7.4 Estimation Using Simulation

When the board temperatur e is not known, a therma l simulation of the appl ication is needed . The simple two-resistor model can be used with the therma l simula tion of t he app licat ion [2] , or a more ac curate and co mple x model of the package can be used in the thermal simulation.

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (Ψ temperature at the top center of the package case using the following equation:

= TT + (ΨJT× PD)

where:

= thermal characterization parameter

= thermocouple temperature on top of package

= power dissipation in package

The thermal charact erization para meter is measured pe r the JESD51-2 spec ification publ ished by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire ex tending f rom the junc tion. The ther mocouple wire is plac ed flat a gainst th e package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

) can be use d to determine the junction temperature with a measurement of the

MPC875/MPC870 Hardware Specifications, Rev. 3.0

12 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Power Supply and Power Sequencing

7.6 References

Semiconductor Equipment and Materials International (415) 964-5111 805 East Middlefield Rd Mountain Vi ew, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or (Available from Global Engineering Documents) 303-397-7956

JEDEC Specifications http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams , “Measur ement a nd Simul ation of Jun ction to Boar d Ther mal Re sistanc e and I ts Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

8 Power Supply and Power Sequencing

This section provides design considerations for the MPC875/870 power supply. The MPC875/870 has a core voltage (V V

. The I/O section of the MPC875/870 is supplied with 3.3 V across V

DDH

The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK, TRST greater than V exceed 3.465 V. This restriction applies to power up/down and normal operation.

) and PLL voltage (V

DDL

DDSYN

), which both operate a t a lower voltage than t he I/O voltage

and VSS (GND).

DDH

, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. No input can be more than 2.5 V . In addition, 5 V-tolerant pins cannot exceed 5.5 V, and remaining input pins cannot

DDH

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply:

•V

must not exceed V

DDL

must not exceed 1.9 V, and V

DDL

DDH

during power up and power down.

must not exceed 3.465 V.

DDH

These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection di odes are forwa rd-biased, and excessive curren t can flow thr ough these dio des. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential difference betwe en the ext ern al bus and core power supplie s on power up, and th e 1N5820 di odes reg ulate the maximum potential difference on power down.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 13

Mandatory Reset Configurations

DDH

MUR420

1N5820

DDL

Figure 3. Example Voltage Sequencing Circuit

9 Mandatory Reset Configurations

The MPC875/870 requires a mandatory configuration during reset. If hardware reset conf iguratio n word (HRCW) is enabl ed, the HRCW[DBGC] valu e needs to be se t to binar y X1 in

the HRCW and the SIUMCR[DBGC] should be pr ogram med with t he same va lue in the boo t code a fter reset . This can be done by asserting the RSTCONF

If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by negating the RSTCONF

during the HRESET assertion.

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the mandatory values in Table 7 in the boot code after the reset is negat ed.

during HRESET assertion.

Table 7. Mandatory Reset Configuration of MPC875/870

HRCW (Hardware reset configuration word)

SIUMCR (SIU module configuration register)

MBMR (Machine B mode register)

PAPAR (Port A pin assignment register)

PADIR (Port A data direction re gister)

PBPAR (Port B pin assignment register)

PBDIR (Port B data direction re gister)

PCPAR (Port C pin assignment register)

Value

(binary)

HRCW[DBGC] X1

SIUMCR[DBGC] X1

MBMR[GPLB4DIS} 0

PAPAR[5:9] PAPAR[12:13]

PADIR[5:9] PADIR[12:13]

PBPAR[14:18] PBPAR[20:22]

PBDIR[14:8] PBDIR[20:22]

PCPAR[4:5] PCPAR[8:9] PCPAR[14]

MPC875/MPC870 Hardware Specifications, Rev. 3.0

14 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Layout Practices

Table 7. Mandatory Reset Configuration of MPC875/870 (continued)

PCDIR (Port C data direction register)

PDPAR (Port D pin assignment register)

PDDIR (Port D data direction register)

PCDIR[4:5] PCDIR[8:9] PCDIR[14]

PDPAR[3:7] PDPAR[9:5]

PDDIR[3:7] PDDIR[9:15]

Value

(binary)

10 Layout Practices

Each VDD pin on the MPC875/870 s hould be prov ided with a low-impedance p ath to the boa rd’ s supply . Each GND pin should likewise be provid ed with a low-impe dance path to gr ound. The power su pply pins drive di stinct gro ups of logic on chip. The V located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropr iate decoupling cap aci tors should be used if required. The capacitor leads a nd ass oci at ed printed circuit traces connecting to chip V minimum, a four-layer board employing two inner layers as V

All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitan ce calculations sho uld consider all device loa ds as well as parasitic ca pacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads bec ause these loads create hig her transient current s in the V inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (V V

SSSYN

, V

SSSYN1

),” of the MPC885 PowerQUICC Family User’s Manual.

power supply should be bypassed to ground using at l ea st fou r 0.1 -µF bypass capacitors

and GND should be kept to less than half an inch per capacitor lead. At a

and GND planes should be used.

and GND circuits. Pull up all unused

DDSYN

11 Bus Signal Timing

The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in half-speed bus mode (fo r example, an MPC875/870 used at 133 MHz must be configured f or a 66 MHz bus). Table 8 shows the frequency ranges f or stand ar d part frequ encies in 1:1 bus mode , and Table 9 shows the frequency ranges for standard part frequencies in 2:1 bus mode.

Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part Frequency 66 MHz 80 MHz

Min Max Min Max

Core frequency 40 66.67 40 80 Bus frequency 40 66.67 40 80

MPC875/MPC870 Hardware Specifications, Rev. 3.0

15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Part Frequenc y 66 MHz 80 MHz 133 MHz

Min Max Min Max Min Max

Core frequency 40 66.67 40 80 40 133 Bus frequency 20 33.33 20 40 20 66

Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz.

The timing for the MPC875/870 bus shown assumes a 50-pF load f or maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay

Table 10. Bus Operation Timings

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

B1 Bus period ( CLKOUT), see Table 8 ————————ns

Unit

B1a EXTCLK to CLKOUT phase skew - If

CLKOUT is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with th e rising edge of CLKO UT . For a non-integer m ultiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a

continuously varying phase skew. B1b CLKOUT frequency jitter pea k-to -pe ak — 1 — 1 — 1 — 1 ns B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 % B1d CLKOUT phase jitter peak-to-peak

for OSCLK ≥ 15 MHz

CLKOUT phase jitter peak-to-peak

for OSCLK < 15 MHz

B2 CLKOUT pulse width low

(MIN = 0.4

B3 CLKOUT pulse width high

(MIN = 0.4

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30),

RD/WR

(MIN = 0.25

× B1, MAX = 0.6 × B1)

, BURST, D(0:31) output hold

× B1)

–2 +2 –2 +2 –2 +2 –2 +2 ns

—4—4—4—4ns

—5—5—5—5ns

12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns

7.60 — 6.30 — 3.80 — 3.13 — ns

B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,

PTR output hold (MIN = 0.25 B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),

VF(0:2) IWP(0:2), LWP(0:1), STS

hold (MIN = 0.25

16 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

× B1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

× B1)

output

7.60 — 6.30 — 3.80 — 3.13 — ns

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B8 CLKOUT to A(0:31), BADDR(28:30)

RD/WR

(MAX = 0.25 B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,

PTR valid (MAX = 0.25 B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),

IWP(0:2), FRZ, LWP(0:1), STS

(MAX = 0.25 × B1 + 6.3)

B9 CLKOUT to A(0:31), BADDR(28:30),

RD/WR

RSV

(MAX = 0.25 B1 1 CLKOUT to TS, BB assertion

(MAX = 0.25

B1 1a CLKOUT to TA, BI assertion (when driven

by the memory controller or PCMCIA

interface) (MAX = 0.00 × B1 + 9.30 1) B12 CLKOUT to TS, BB negation

(MAX = 0.25

B12a CLKOUT to TA, BI negation (when driven

by the memory controller or PCMCIA

interface) (MAX = 0.00 × B1 + 9.00)

, BURST, D(0:31) valid

× B1 + 6.3)

valid

, BURST , D(0:31), TSIZ(0:1), REG ,

, PTR High-Z

× B1 + 6.3)

× B1 + 6.0)

× B1 + 4.8)

—13.80—12.50—10.00— 9.43 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns

2.50 9.30 2.50 9.30 2.50 9.80 2.5 9.3 ns

7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns

B13 CLKOUT to TS, BB High-Z

(MIN = 0.25

B13a CLKOUT to T A, BI High-Z (whe n driven by

the memory controller or PCMCIA

interface) (MIN = 0.00× B1 + 2.5) B14 CLKOUT to TEA assertion

(MAX = 0.00 B15 CLKOUT to TEA High-Z

(MIN = 0.00 B16 TA, BI valid to CLKOUT (setup time)

(MIN = 0.00

B16a TEA, KR, RETRY, CR valid to CLKOUT

(setup time) (MIN = 0.00

B16b BB, BG, BR, valid to CLKOUT (setup time)

B17a CLKOUT to KR, RETRY, CR valid (hold

(4MIN = 0.00 × B1 + 0.00)

B17 CLKOUT to T A, TEA, BI, BB , BG, BR valid

(hold time) (MIN = 0.00

time) (MIN = 0.00

× B1)

× B1 + 9.00)

× B1 + 2.50)

× B1 + 6.00)

× B1 + 2.00)

× B1 + 4.5)

× B1 + 1.00

)

7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

6.00 — 6.00 — 6.00 — 6 — ns

4.50 — 4.50 — 4.50 — 4.50 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

1.00 — 1.00 — 2.00 — 2.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B18 D(0:31) valid to CLKOUT rising edge

(setup time) B19 CLKOUT rising edge to D (0:31) valid (hold

time) B20 D(0:31) valid to CLKOUT falling edge

(setup time) B21 CLKOUT falling edge to D(0:31) valid

(hold time)

(MIN = 0.00 × B1 + 6.00)

(MIN = 0.00 × B1 + 1.00 5)

(MIN = 0.00 × B1 + 4.00)

(MIN = 0.00 × B1 + 2.00)

B22 CLKOUT rising edge to CS asserted

GPCM ACS = 00 (MAX = 0.25

× B1 + 6.3)

B22a CLKOUT falling edge to CS as sert ed

GPCM ACS = 10, TRLX = 0

(MAX = 0.00 × B1 + 8.00)

B22b CLKOUT falling edge to CS as sert ed

GPCM ACS = 11, TRLX = 0, EBDF = 0

(MAX = 0.25

× B1 + 6.3)

B22c CLKOUT falling edge to CS assert ed

GPCM ACS = 11, TRLX = 0, EBDF = 1

(MAX = 0.375 × B1 + 6.6) B23 CLKOUT rising edge to CS negated

GPCM read access, GPCM write access

ACS = 00, TRLX = 0 & CSNT = 0

(MAX = 0.00

× B1 + 8.00)

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 2.00 — 2.00 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

— 8.00 — 8.00 — 8.00 — 8.00 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns

B24 A(0:31) and BADDR(28:30) to CS

5.60 — 4.30 — 1.80 — 1.13 — ns asserted GPC M ACS = 10, TRLX = 0 (MIN = 0.25 × B1 – 2.00)

B24a A(0:31) and BADDR(28:30) to CS

13.20 — 10.50 — 5.60 — 4.25 — ns asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50

B25 CLKOUT rising edge to OE,

(0:3)/BS_B[0:3] asserted

(MAX = 0.00

B26 CLKOUT rising edge to OE negated

(MAX = 0.00

B27 A(0:31) and BADDR(28:30) to CS

× B1 – 2.00)

— 9.00 9.00 9.00 — 9.00 ns

× B1 + 9.00)

2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns

× B1 + 9.00)

35.90 — 29.30 — 16.90 — 13.60 — ns asserted GPC M ACS = 10, TRLX = 1 (MIN = 1.25 × B1 – 2.00)

B27a A(0:31) and BADDR(28:30) to CS

43.50 — 35.50 — 20.70 — 16.75 — ns asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 × B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

18 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B28 CLKOUT rising edge to

(0:3)/BS_B[0:3] negated GPCM write access CSNT = 0 (MAX = 0.00

B28a CLKOUT falling edge to

(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0, CSNT = 1, EB DF = 0 (MAX = 0.25

B28b CLKOUT falling edge to CS neg ate d

GPCM write access TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25

B28c CLKOUT falling edge to

(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0, CSNT = 1 write access TRLX = 0, CSNT = 1, EBDF = 1 (MAX = 0.375

B28d CLKOUT falling edge to CS neg ate d

GPCM write access TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375

B29 WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25

× B1 + 9.00)

× B1 + 6.80)

× B1 + 6.6)

× B1 – 2.00)

— 9.00 — 9.00 — 9.00 — 9.00 ns

7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns

—14.30—13.00—10.50— 9.93 ns

10.90 18.00 10.90 18.00 5.20 12.30 4.69

— 18.00 — 18.00 — 12.30 — 11.30 ns

5.60 — 4.30 — 1.80 — 1.13 — ns

11.29

B29a WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50

B29b CS negated to D(0:31) High-Z G PCM write

access, ACS = 00, TRLX = 0 & CSNT = 0 (MIN = 0.25 × B1 – 2.00)

B29c CS negated to D (0:31) High-Z GPCM write

access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0.50

B29d WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50

B29e CS negated to D(0:31) High-Z G PCM write

access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 1.50

× B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

13.20 — 10.50 — 5.60 — 4.25 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

43.50 — 35.50 — 20.70 — 16.75 — ns

19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B29f WE(0:3/BS_B[0:3]) negated to D(0:31)

High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375

B29g CS negated to D(0:31) High-Z G PCM write

access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375

B29h WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375

B29i CS negated to D(0:31) (0:3) High-Z GPCM

write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11 , EBDF = 1 (MIN = 0.375

B30 CS, WE(0:3)/BS_B[0:3] negated to

A(0:31), BADDR(28:30) invalid GPCM write access 7 (MIN = 0.25 × B1 – 2.00)

B30a WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50

× B1 – 6.30)

× B1 – 3.30)

× B1 – 2.00)

5.00 — 3.00 — 0.00 — 0.00 — ns

38.40 — 31.10 — 17.50 — 13.85 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

B30b WE(0:3)/BS_B[0:3] negated to A(0:31)

Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1.

negated to A(0:31) inv alid GPCM write

CS access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50

B30c WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375

B30d WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRL X = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1

20 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

× B1 – 2.00)

× B1 – 3.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

43.50 — 35.50 — 20.70 — 16.75 — ns

8.40 — 6.40 — 2.70 — 1.70 — ns

38.67 — 31.38 — 17.83 — 14.19 — ns

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B31 CLKOUT falling edge to CS valid, as

requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00

B31a CLKOUT falling edge to CS va lid , as

requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25

B31b CLKOUT rising edge to CS valid, as

requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00

B31c CLKOUT rising edge to CS valid, as

requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25

B31d CLKOUT falling edge to CS va lid , as

requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375

B32 CLKOUT falling edge to BS valid, as

requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00

× B1 + 6.00)

× B1 + 6.80)

× B1 + 8.00)

× B1 + 6.30)

× B1 + 6.6)

× B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns

13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

B32a CLKOUT falling edge to BS valid, as

requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25

B32b CLKOUT rising edge to BS valid, as

requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00

B32c CLKOUT rising edge to BS valid, as

requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25

B32d CLKOUT falling edge to BS valid, as

requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375

B33 CLKOUT falling edge to GPL valid, as

requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00

× B1 + 6.80)

× B1 + 8.00)

× B1 + 6.80)

× B1 + 6.60)

× B1 + 6.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B33a CLKOUT rising edge to GPL valid, as

requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25

B34 A(0:31), BADDR(28:30), and D(0:31) to

valid, as requested by control bi t CST4 in the corresponding word in the UPM (MIN = 0.25

B34a A(0:31), BADDR(28:30), and D(0:31) to

valid, as requested by control bi t CST1 in the corresponding word in the UPM (MIN = 0.50

B34b A(0:31), BADDR(28:30), and D(0:31) to

valid, as requested by CST2 in the corresponding word in UPM (MIN = 0.75

B35 A(0:31), BADDR(28:30) to CS valid, as

requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25

B35a A(0:31), BADDR(28:30), and D(0:31) to

valid, as requested by BST1 in the corresponding word in the UPM (MIN = 0.50

× B1 + 6.80)

× B1 - 2.00)

× B1 – 2.00)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

20.70 — 16.70 — 9.40 — 6.80 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

B35b A(0:31), BADDR(28:30), and D(0:31) to

valid, as requested by control bi t BST2 in the corresponding word in the UPM (MIN = 0.75

B36 A(0:31), BADDR(28:30), and D(0:31) to

GPL

valid, as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25

B37 UPWAIT valid to CLKOUT falling edge 8

(MIN = 0.00

B38 CLKOUT falling edge to UPWAIT valid

(MIN = 0.00 × B1 + 1.00)

B39 AS valid to CLKOUT rising edge 9

(MIN = 0.00

B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid

to CLKOUT rising edge (MIN = 0.00 × B1 + 7.00)

B41 TS valid to CLKOUT rising edge (setup

time) (MIN = 0.00

× B1 – 2.00)

× B1 + 6.00)

× B1 + 7.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

20.70 — 16.70 — 9.40 — 7.40 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

22 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B42 CLKOUT rising edge to TS valid (hold

time) (MIN = 0.00

× B1 + 2.00)

B43 AS negation to memory controller signals

2.00 — 2.00 — 2.00 — 2.00 — ns

—TBD—TBD—TBD—TBDns

negation (MAX = TBD)

For part speeds above 50 MHz, use 9.80 ns for B11a.

The timing required fo r BR in put is rel ev ant w hen the M P C875 /870 is s ele cted to work with the i nter nal bus arbiter.

The timing for BG

For part speeds above 50 MHz, use 2 ns for B17.

The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is ass erted.

For part speeds above 50 MHz, use 2 ns for B19.

The D(0:31) input timi ngs B20 an d B21 refer to the falling ed ge of th e C LK OUT. This timing is va li d on ly for r ead

input is relevant when the MPC875/870 is selected to work with the external bus arbiter.

accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory controller , for data bea ts where DL T3 = 1 in the RAM words. (This is only the case whe re data is latche d on the falling edge of CLKOUT.)

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

The signal UPW AIT is consid ered asy nchronous t o the C LKOUT and synchro nized intern ally. The timings specified in

B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.

The AS signal is c ons id ered a sy nc hro nou s to the CLKOUT. The timing B39 is sp ec ifi ed in o r der to allow the behavior

specified in Figure 22.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 4 provides the control timing diagram.

LKOUT

Outputs

Inputs

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V D

2.0 V

0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input setup time specification

D Minimum input hold time specification

Figure 4. Control Timing

Figure 5 provides the timing for the external clock.

LKOUT

Figure 5. External Clock Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

24 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 6 provides the timing for the synchronous output signals.

LKOUT

B7 B9

Output

Signals

B8a

Output

Signals

B8b

B7b

Output

Signals

B9B7a

Figure 6. Synchronous Output Signals Timing

Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals.

LKOUT

B13

B12B11

, BB

B13a

B11

TA, B I

TEA

B14

B12a

B15

Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 8 provides the timing for the synchronous input signals.

CLKOUT

B16

, BI

B16a

TEA, KR,

ETRY, CR

B16b

B, BG, BR

B17

B17a

B17

Figure 8. Synchronous Input Signals Timing

Figure 9 provides normal case timing for in put dat a. It also appl ies t o normal r ead acc esses u nder the con trol o f the

user-programmable machine (UPM) in th e memory cont roller.

LKOUT

B16

B17

B18

B19

D[0:31]

Figure 9. Input Data Timing in Normal Case

MPC875/MPC870 Hardware Specifications, Rev. 3.0

26 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 10 provides the timing for t he i nput data controlled b y th e UPM for data beats where DLT3 = 1 in the UPM

RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

LKOUT

B20

B21

D[0:31]

Figure 10. Input Data Timing when Controlled by UPM in the Memory Controller and DL T3 = 1

Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors.

LKOUT

B11 B12

A[0:31]

B22

CSx

B25

B28

WE[0:3]

D[0:31]

B23

B26

B19

B18

Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

LKOUT

A[0:31]

B11 B12

B22a

B23

CSx

B25B24

B26

B19B18

D[0:31]

Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)

LKOUT

B11 B12

A[0:31]

B22b

B22c

B23

CSx

B24a

B25 B26

B19B18

D[0:31]

Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

28 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

LKOUT

A[0:31]

B11 B12

B22a

B23

CSx

B27

B27a

B22b B22c

B26

B19B18

D[0:31]

Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 15 through Figure 17 provide the timing for the external bus write controlled by various GPCM factors.

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31]

B11

B22 B23

B26

B12

B8 B9

B30

B28B25

B29b

B29

Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

30 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31]

B11

B22

B26

B12

B28b B28d

B25

B28aB9B28c

B30a B30c

B23

B29c B29g

B29a B29f

Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

LKOUT

B12B11

B30dB30b

A[0:31]

B28b B28d

CSx

B25

B29e B29i

WE[0:3]

B26

B29d B29h

B29b

B28a B28c

D[0:31]

Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)

B23B22

B9B8

MPC875/MPC870 Hardware Specifications, Rev. 3.0

32 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 18 provides the timing for the external bus controlled by the UPM.

CLKOUT

A[0:31]

B31a

B31d

B31

CSx

B34

B34a

B34b

B32a B32d

B32

B31b

B32b

B31c

B32c

BS_A

[0:3]

PL_A[0:5],

[0:5]

GPL_B

B36

B35

B35a

B35b

B33a

B33

Figure 18. External Bus Timing (UPM Controlled Signals)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

PL_A[0:5],

[0:5]

GPL_B

Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 20 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

PL_A[0:5],

[0:5]

GPL_B

Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

34 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 21 provides the timing for the synchronous external master access controlled by the GPCM.

CLKOUT

B41 B42

B40

A[0:31],

TSIZ[0:1],

, BURST

R/W

B22

CSx

Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM.

CLKOUT

B39

B40

A[0:31],

TSIZ[0:1],

R/W

B22

CSx

Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 23 provides the timing for the asynchronous external master control signals negation.

B43

CSx, WE[0:3],

OE, GPLx,

[0:3]

Figure 23. Asynchronous External Master—Control Signals Negation Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 11 provides the interrupt timing for the MPC875/870.

Table 11. Interrupt Timing

Num Characteristic

I39 IRQ I40 IRQx hold time after CLKOUT 2.00 ns I41 IRQx pulse width low 3.00 ns I42 IRQx pulse width high 3.00 ns I43 IRQx edge-to-edge time 4xT

The I39 and I40 tim ing s des cri be the tes tin g c on diti on s u nde r w hi ch the IRQ lines are tested when being defined as

level sensitive. The IRQ to the CLKOUT. The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC875/870 is able to support.

x valid to CLKOUT rising edge (setup time) 6.00 ns

lines are synchronized interna lly and do no t have to be assert ed or nega ted with refe rence

All Frequencies

Min Max

CLOCKOUT

Figure 24 provides the interrupt detection timing for the external level-sensitive lines.

LKOUT

I39

I40

Unit

—

IRQ

Figure 24. Interrupt Detection Timing for External Level Sensitive Lines

Figure 25 provides t he interrupt d etection timing for the ex ternal edge-s ensitive lines.

LKOUT

I41 I42

IRQx

I43

Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines

MPC875/MPC870 Hardware Specifications, Rev. 3.0

36 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 12 shows the PCMCIA timing for the MPC875/870.

Table 12. PCMCIA Timing

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

A(0:31), REG strobe asserted

P44

(MIN = 0.75 × B1 – 2.00) A(0:31), REG

P45

negation (MIN = 1.00 × B1 – 2.00)

CLKOUT to REG valid

P46

(MAX = 0.25 CLKOUT to REG invalid

P47

(MIN = 0.25 CLKOUT to CE1, CE2 asserted

P48

(MAX = 0.25 CLKOUT to CE1

P49

(MAX = 0.25 CLKOUT to PCOE

P50

P51

P52

assert time (MAX =

IOWR

0.00

× B1 + 11.00)

CLKOUT to PCOE, IORD, PCWE,

negate time (MAX =

IOWR

× B1 + 11.00)

0.00 CLKOUT to ALE assert time (MAX

= 0.25

valid to PCMCIA

valid to ALE

× B1 + 8.00)

× B1 + 1.00)

× B1 + 8.00)

, CE2 negated

× B1 + 8.00)

× B1 + 6.30)

, IORD, PCWE,

20.70 — 16.70 — 9.40 — 7.40 — ns

28.30 — 23.00 — 13.20 — 10.50 — ns

7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns

8.60 — 7.30 — 4.80 — 4.125 — ns

7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns

— 11.00 — 11.00 — 11.00 — 11.00 ns

2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns

CLKOUT to ALE negate time (MAX

P53

P54

P55

P56

PSST = 1. Otherwise add PSST times cycle time.

PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timing s defi ne wh en the WAITA

current cycle. The WAITA See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.

37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

× B1 + 8.00)

= 0.25 PCWE, IOWR negated to D(0:31)

invalid WAITA and WAITB valid to

CLKOUT rising edge (MIN = 0.00 × B1 + 8.00)

CLKOUT rising edge to W AIT A and WAITB

2.00)

(MIN – = 0.25 × B1 – 2.00)

invalid1 (MIN = 0.00 × B1 +

assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

— 15.60 — 14.30 — 11.80 — 11.13 ns

5.60 — 4.30 — 1.80 — 1.125 — ns

8.00 — 8.00 — 8.00 — 8.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

signals are detecte d in orde r to freez e (or rel ieve) t he PCMCIA

Bus Signal Timing

Figure 26 provides the PCMCIA access cycle timing for the external bus read.

CLKOUT

P44

A[0:31]

REG

CE1/CE2

PCOE, IORD

ALE

D[0:31]

P46 P45

P48 P49

P53P52 P52

P47

P51P50

Figure 26. PCMCIA Access Cycles Timing External Bus Read

B19B18

MPC875/MPC870 Hardware Specifications, Rev. 3.0

38 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Figure 27 provides t he PCMCIA access cycle timing for the external bus write.

CLKOUT

P44

A[0:31]

P46 P45

REG

P48 P49

CE1/CE2

PCWE, IOWR

P53P52 P52

ALE

D[0:31]

Figure 27. PCMCIA Access Cycles Timing External Bus Write

Figure 28 provides the PCMCIA WAIT signals detection timing.

P47

P51P50

P54

B9B8

LKOUT

P55

P56

WAITA

Figure 28. PCMCIA WAIT Signals Detection Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 13 shows the PCMCIA port timing for the MPC875/870.

Table 13. PCMCIA Port Timing

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

CLKOUT to OPx valid

P57

(MAX = 0.00 × B1 + 19.00) HRESET

P58

P59

P60

OP2 and OP3 only.

drive IP_Xx valid to CLKOUT rising edge

(MIN = 0.00 × B1 + 5.00) CLKOUT rising edge to IP_Xx invalid

(MIN = 0.00 × B1 + 1.00)

negated to OPx

(MIN = 0.75 × B1 + 3.00)

— 19.00 — 19.00 — 19.00 — 19.00 ns

25.70 — 21.70 — 14.40 — 12.40 — ns

5.00 — 5.00 — 5.00 — 5.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

Figure 29 provides the PCMCIA output port timing for the MPC875/870.

CLKOUT

P57

Output

Signals

HRESET

P58

P2, OP3

Figure 29. PCMCIA Output Port Timing

Figure 30 provides the PCMCIA input port timing for the MPC875/870.

LKOUT

P59

P60

Input

Signals

Figure 30. PCMCIA Input Port Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

40 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 14 shows the debug port timing for the MPC875/870.

Table 14. Debug Port Timing

Num Characteristic

All Frequencies

Unit

Min Max

D61 DSCK cycle time 3 × T D62 DSCK clock pulse width 1.25 × T D63 DSCK rise and fall times 0.00 3.00 ns D64 DSDI input data setup time 8.00 ns D65 DSDI data hold time 5.00 ns D66 DSCK low to DSDO data valid 0.00 15.00 ns D67 DSCK low to DSDO invalid 0.00 2.00 ns

CLOCKOUT

Figure 31 provides the input timing for the debug port clock.

DSCK

D61

D63

D62

D63

Figure 31. Debug Port Clock Input Timing

Figure 32 provides the timing for the debug port.

— —

DSCK

D64

D65

DSDI

D66

D67

DSDO

Figure 32. Debug Port Timings

MPC875/MPC870 Hardware Specifications, Rev. 3.0

41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 15 shows the reset timing for the MPC875/870.

T a b l e 15. Re se t Timing

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

CLKOUT to HRESET impedance (MAX = 0.00 × B1 +

R69

20.00) CLKOUT to SRESET high

R70

impedance (MAX = 0.00 × B1 +

20.00) RSTCONF pulse width

R71

(MIN = 17.00 × B1)

R72 — —————————

Configuration data to HRESET

R73

rising edge setup time (MIN = 15.00 × B1 + 50.00)

Configuration data to RSTCONF rising edge setup time

R74

(MIN = 0.00 × B1 + 350.00) Configuration data hold time after

R75

RSTCONF (MIN = 0.00 × B1 + 0.00)

Configuration data hold time after

R76

HRESET (MIN = 0.00 × B1 + 0.00)

HRESET

R77

asserted t o data out drive (MAX = 0.00 × B1 + 25.00)

negation

and RSTCONF

high

— 20.00 — 20.00 — 20.00 — 20.00 ns

515.20 — 425.00 — 257.60 — 212.50 — ns

504.50 — 425.00 — 277.30 — 237.50 — ns

350.00 — 350.00 — 350.00 — 350.00 — ns

0.00 — 0.00 — 0.00 — 0.00 — ns

— 25.00 — 25.00 — 25.00 — 25.00 ns

RSTCONF high impedance

R78

(MAX = 0.00 × B1 + 25.00) CLKOUT of last rising edge

before chip three-states

R79

HRESET to data out high impedance (MAX = 0.00 × B1 + 25.00)

DSDI, DSCK setup

R80

(MIN = 3.00 × B1) DSDI, DSCK hold time

R81

(MIN = 0.00 × B1 + 0.00) SRESET

rising edge for DSDI and DSCK

R82

sample (MIN = 8.00 × B1)

42 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

negated to data out

negated to CLKOUT

MPC875/MPC870 Hardware Specifications, Rev. 3.0

— 25.00 — 25.00 — 25.00 — 25.00 ns

90.90 — 75.00 — 45.50 — 37.50 — ns

0.00 — 0.00 — 0.00 — 0.00 — ns

242.40 — 200.00 — 121.20 — 100.00 — ns

Bus Signal Timing

Figure 33 shows the reset timing for the data bus configuration.

HRESET

R71

R76

RSTCONF

R73

R74

[0:31] (IN)

R75

Figure 33. Reset Timing—Configuration from Data Bus

Figure 34 provides the reset timing for the data bus weak drive during configuration.

CLKOUT

HRESET

RSTCONF

[0:31] (OUT)

(Weak)

R69

R79

R77 R78

Figure 34. Reset Timing—Data Bus Weak Drive During Configuration

MPC875/MPC870 Hardware Specifications, Rev. 3.0

43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

IEEE 1149.1 Electrical Specifications

Figure 35 provides the reset timing for the debug port configuration.

CLKOUT

R70

R82

SRESET

R80R80

R81

DSCK, DSDI

R81

Figure 35. Reset Timing—Debug Port Configuration

12 IEEE 1149.1 Electrical Specifications

Table 16 provides the JTAG timings for the MPC875/870 shown in Figure 36 to Figure 39.

Table 16. JTAG Timing

All

Num Characteristic

J82 TCK cycle time 100.00 — ns J83 TCK clock pulse width measured at 1.5 V 40.00 — ns J84 TCK rise and fall times 0.00 10.00 ns J85 TMS, TDI data setup time 5.00 — ns J86 TMS, TDI data hold time 25.00 — ns J87 TCK low to TDO data valid — 27.00 ns J88 TCK low to TDO data invalid 0.00 — ns J89 TCK low to TDO high impedance — 20.00 ns J90 TRST J91 TRST setup time to TCK low 40.00 — ns J92 TCK falling edge to output valid — 50.00 ns J93 TCK falling edge to output valid out of high impedance — 50.00 ns J94 TCK falling edge to output high impedance — 50.00 ns J95 Boundary scan input valid to TCK rising edge 50.00 — ns

assert time 100.00 — ns

Frequencies

Min Max

Unit

J96 TCK rising edge to boundary scan input invalid 50.00 — ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

44 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

IEEE 1149.1 Electrical Specifications

TCK

MS, TDI

J82 J83

J84 J84

Figure 36. JTAG Test Clock Input Timing

J85

J86

J87

J88 J89

TDO

TCK

TRST

Figure 37. JTAG Test Access Port Timing Diagram

J91

J90

Figure 38. JTAG TRST

Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

TCK

J92 J94

Output

Signals

J93

Output

Signals

J95 J96

Output

Signals

Figure 39. Boundary Scan (JTAG) Timing Diagram

13 CPM Electrical Characteristics

This section pr ovi des t he AC and DC electrical specifications for the communicat ions processor module (CPM ) of the MPC875/870.

13.1 Port C Interrupt AC Electrical Specifications

Table 17 provides the timings for port C interrupts.

Table 17. Port C Interrupt Timing

Num Characteristic

35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns 36 Port C interrupt minimum time between active edges 55 — ns

Figure 40 shows the port C interrupt detection timing.

Port C

(Input)

Figure 40. Port C Interrupt Detection Timing

33.34 MHz Unit

Min Max

MPC875/MPC870 Hardware Specifications, Rev. 3.0

46 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

13.2 IDMA Controller AC Electrical Specifications

Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44.

Table 18. IDMA Controller Timing

Num Characteristic

All

Frequencies

Min Max

Unit

40 DREQ 41 DREQ hold time from clock high 42 SDACK 43 SDACK negation delay from clock low — 12 ns 44 SDACK negation delay from TA low — 20 ns 45 SDACK negation delay from clock high — 15 ns 46 TA assertion to falling edge of the clock setup time (applies to external TA)7—ns

Applies to high-to-low mode (EDM=1)

(Output)

DREQ (Input)

setup time to clock high 7 — ns

assertion delay from clock high — 12 ns

CLKO

TBD — ns

Figure 41. IDMA External Requests Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

(

CLKO

Output)

R/W

Output)

DATA

(Input)

SDACK

Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generate d TA

CLKO

Output)

R/W

Output)

DATA

Output)

SDACK

42 44

Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA

48 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

MPC875/MPC870 Hardware Specifications, Rev. 3.0

CPM Electrical Characteristics

(

CLKO

Output)

R/W

Output)

DATA

Output)

SDACK

42 45

Figure 44. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA

13.3 Baud Rate Generator AC Electrical Specifications

Table 19 provides the baud rate generator timings as shown in Figure 45.

Table 19. Baud Rate Generator Timing

All

Num Characteristic

50 BRGO rise and fall time — 10 ns 51 BRGO duty cycle 40 60 % 52 BRGO cycle 40 — ns

BRGOX

Frequencies

Min Max

Unit

Figure 45. Baud Rate Generator Timing Diagram

49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

MPC875/MPC870 Hardware Specifications, Rev. 3.0

CPM Electrical Characteristics

13.4 Timer AC Electrical Specifications

Table 20 provides the general-purpose timer timings as shown in Figure 46.

Num Characteristic

Table 20. Timer Timi ng

All

Frequencies

Min Max

Unit

61 TIN/TGATE 62 TIN/TGATE low time 1 — clk 63 TIN/TGATE high time 2 — clk 64 TIN/TGATE cycle time 3 — clk 65 CLKO low to TOUT valid 3 25 ns

CLKO

IN/TGATE

(Input)

TOUT

(Output)

rise and fall time 10 — ns

626361

Figure 46. CPM General-Purpose Timers Timing Diagram

13.5 Serial Interface AC Electrical Specifications

Table 21 provides the serial interface (SI) timings as shown in Figure 47 to Figure 51.

Num Characteristic

70 L1RCLKB, L1TCLKB frequency (DSC = 0)

71 L1RCLKB, L1TCLKB width low (DSC = 0)

71a L1RCLKB, L1TCLKB width high (DSC = 0)

72 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time — 15.00 ns 73 L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time) 20.00 — ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

50 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Table 21. SI Timing

1, 2

— SYNCCLK

All Frequencies

Unit

Min Max

MHz

/2.5 P + 10 — ns P + 10 — ns

CPM Electrical Characteristics

Table 21. SI Timing (continued)

All Frequencies

Num Characteristic

Min Max

74 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 35.00 — ns 75 L1RSYNCB, L1TSYNCB rise/fall time — 15.00 ns 76 L1RXDB valid to L1CLKB edge (L1RXDB setup time) 17.00 — ns 77 L1CLKB edge to L1RXDB invalid (L1RXDB hold time) 13.00 — ns 78 L1CLKB edge to L1ST1 and L1ST2 valid

78A L1SYNCB valid to L1ST1 and L1ST2 valid 10.00 45.00 ns

79 L1CLKB edge to L1ST1 and L1ST2 invalid 10.00 45.00 ns 80 L1CLKB edge to L1TXDB valid 10.00 55.00 ns

80A L1TSYNCB valid to L1TXDB valid

81 L1CLKB edge to L1TXDB high impedance 0.00 42.00 ns

10.00 45.00 ns

10.00 55.00 ns

Unit

82 L1RCLKB, L1TCLKB frequency (DSC =1) — 16.00 or

MHz

SYNCCLK

83 L1RCLKB, L1TCLKB width low (DSC =1) P + 10 — ns

83a L1RCLKB, L1TCLKB width high (DSC = 1)

P + 10 — ns

84 L1CLKB edge to L1CLKOB valid (DSC = 1) — 30.00 ns 85 L1RQB valid before falling edge of L1TSYNCB 86 L1GRB setup time

1.00 — L1TCLK

42.00 — ns 87 L1GRB hold time 42.00 — ns 88 L1CLKB edge to L1SYNCB valid (FSD= 00) CNT = 0000, BYT = 0,

—0.00ns

DSC = 0)

The ratio SyncCLK/L1RCLKB must be greater than 2.5/1.

These specs are valid for IDL mode only.

Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.

These strobes and Tx D on the first bit of the frame be come valid after the L 1CLKB edge or L1SYNCB, whic he ve r

comes later.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

(

L1RCLKB

FE=0, CE=0)

(Input)

L1RCLKB

FE=1, CE=1)

(Input)

L1RSYNCB

(Input)

70 71a

RFSD=1

74 77

L1RXDB

(Input)

L1ST(2-1)

(Output)

BIT0

Figure 47. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

52 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

(

L1RCLKB

FE=1, CE=1)

(Input)

L1RCLKB

FE=0, CE=0)

(Input)

L1RSYNCB

(Input)

RFSD=1

74 77

83a

L1RXDB

(Input)

L1ST(2-1)

(Output)

L1CLKOB

(Output)

BIT0

Figure 48. SI Receive Timing with Double-Speed Clocking (DSC = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

(

L1TCLKB

FE=0, CE=0)

(Input)

71 70

L1TCLKB

FE=1, CE=1)

(Input)

L1TSYNCB

(Input)

80a

TFSD=0

L1TXDB

(Output)

L1ST(2-1)

(Output)

BIT0

Figure 49. SI Transmit Timing Diagram (DSC = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

54 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

(

L1RCLKB

FE=0, CE=0)

(Input)

L1RCLKB

FE=1, CE=1)

(Input)

L1RSYNCB

(Input)

TFSD=0

83a

L1TXDB

(Output)

L1ST(2-1)

(Output)

L1CLKOB

(Output)

BIT0

78a

Figure 50. SI Transmit Timing with Double Speed Clocking (DSC = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

L1RCLKB

12345678910 11 12 13 14 15 16 17 18 19 20

B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15

(Input)

1RSYNCB

(Output)

L1TXDB

(Input)

L1RXDB

(Output)

L1ST(2-1)

L1RQB

(Output)

(Input)

L1GRB

Figure 51. IDL Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

56 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

13.6 SCC in NMSI Mode Electrical Specifications

Table 22 provides the NMSI external clock timing.

Table 22. NMSI External Clock Timing

All Frequencies

Num Characteristic

Min Max

100 RCLK3 and TCLK3 width high 101 RCLK3 and TCLK3 width low 1/SYNCCLK +5 — ns 102 RCLK3 and TCLK3 rise/fall time — 15.00 ns 103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns 104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns 105 CTS3 setup time to TCLK3 rising edge 5.00 — ns 106 RXD3 setup time to RCLK3 rising edge 5.00 — ns 107 RXD3 hold time from RCLK3 rising edge 108 CD3 setup time to RCLK3 rising edge 5.00 — ns

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.

Also applies to CD and CTS hold time when they are used as external sync signals.

1/SYNCCLK — ns

5.00 — ns

Unit

Table 23 provides the NMSI internal clock timing.

Table 23. NMSI Internal Clo ck Timing

All Frequencies

Num Characteristic

Min Max

100 RCLK3 and TCLK3 frequency 102 RCLK3 and TCLK3 rise/fall time — — ns 103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns 104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns 105 CTS3 setup time to TCLK3 rising edge 40.00 — ns 106 RXD3 setup time to RCLK3 rising edge 40.00 — ns 107 RXD3 hold time from RCLK3 rising edge 108 CD3 setup time to RCLK3 rising edge 40.00 — ns

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.

Also applies to CD and CTS hold time when they are used as external sync signals

0.00 SYNCCLK/3 MHz

0.00 — ns

Unit

MPC875/MPC870 Hardware Specifications, Rev. 3.0

57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

Figure 52 through Figure 54 show the NMSI timings.

RCLK3

RxD3

(Input)

CD3

(Input)

CD3

YNC Input)

TCLK3

106

102

102 101

100

107

108

107

Figure 52. SCC NMSI Receive Timing Diagram

102 101

100

TxD3

(Output)

RTS3

(Output)

CTS3

(Input)

CTS3

(SYNC Input)

103

105

104

Figure 53. SCC NMSI Transmit Timing Diagram

104

107

MPC875/MPC870 Hardware Specifications, Rev. 3.0

58 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

TCLK3

102

TxD3

(Output)

RTS3

(Output)

CTS3

(Echo Input)

102 101

100

103

104

105

Figure 54. HDLC Bus Timing Diagram

13.7 Ethernet Electrical Specifications

Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57.

Table 24. Ethernet Timing

104107

All

Num Characteristic

120 CLSN width high 40 — ns 121 RCLK3 rise/fall time — 15 ns 122 RCLK3 width low 40 — ns 123 RCLK3 clock period 124 RXD3 setup time 20 — ns 125 RXD3 hold time 5 — ns 126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns 127 RENA width low 10 0 — ns 128 TCLK3 rise/fall time — 15 ns 129 TCLK3 width low 40 — ns 130 TCLK3 clock period 131 TXD3 active delay (from TCLK3 rising edge) — 50 ns 132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns

Frequencies

Min Max

80 120 ns

99 101 ns

Unit

MPC875/MPC870 Hardware Specifications, Rev. 3.0

59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

Table 24. Ethernet Timing (continued)

Num Characteristic

133 TENA active delay (from TCLK3 rising edge) 10 50 ns 134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK negated

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.

SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

CLSN(CTS1)

(Input)

120

Frequencies

Min Max

—20ns —20ns

Figure 55. Ethernet Collision Timing Diagram

All

Unit

RCLK3

RxD3

(Input)

RENA(CD3)

(Input)

121

124 123

125

126

Figure 56. Ethernet Receive Timing Diagram

Last Bit

127

MPC875/MPC870 Hardware Specifications, Rev. 3.0

60 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

TCLK3

TxD3

(Output)

TENA(RTS3)

(Input)

RENA(CD3)

(Input)

(NOTE 2)

128

131 121

133 134

NOTES:

Transmit clock invert (TCI) bit in GSMR is set.

1. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the

2. CSL bit is set in the buffer descriptor at the end of the frame transmission.

128

129

132

Figure 57. Ethernet Transmit Timing Diagram

13.8 SMC Transparent AC Electrical Specifications

Table 25 provides the SMC transparent timings as shown in Figure 58.

T able 25. SMC Transp arent Timing

All

Num Characteristic

150 SMCLK clock period 151 SMCLK width low 50 — ns

151A SMCLK width high 50 — ns

152 SMCLK rise/fall time — 15 ns 153 SMTXD active delay (from SMCLK falling edge) 10 50 ns 154 SMRXD/SMSYNC setup time 20 — ns 155 RXD1/SMSYNC hold time 5 — ns

SyncCLK must be at least twice as fast as SMCLK.

Frequencies

Min Max

100 — ns

Unit

MPC875/MPC870 Hardware Specifications, Rev. 3.0

61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

SMCLK

152

SMTXD

(Output)

SMSYNC

SMRXD

(Input)

NOTE:

This delay is equal to an integer number of character-length clocks.1.

152 151

NOTE

154 153

155

154

155

151

150

Figure 58. SMC Transparent Timing Diagram

13.9 SPI Master AC Electrical Specifications

Table 26 provides the SPI master timings as shown in Figure 59 and Figure 60.

Table 26. SPI Master Timing

All

Num Characteristic

160 MASTER cycle time 4 1024 t 161 MASTER clock (SCK) high or low time 2 512 t 162 MASTER data setup time (inputs) 15 — ns 163 Master data hold time (inputs) 0 — ns 164 Master data valid (after SCK edge) — 10 ns 165 Master data hold time (outputs) 0 — ns 166 Rise time output — 15 ns 167 Fall time output — 15 ns

Frequencies

Min Max

Unit

cyc

MPC875/MPC870 Hardware Specifications, Rev. 3.0

62 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

SPICLK

(CI=0)

(Output)

161 160

SPICLK

(CI=1)

(Output)

163

162

166167161

167

166

SPIMISO

(Input)

SPIMOSI

(Output)

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

SPIMISO

(Input)

msb Data lsb msb

165 164

167 166

msb lsb msb

Data

Figure 59. SPI Master (CP = 0) Timing Diagram

166167161

161 160

162

163

166

msb Data lsb msb

167

165 164

167 166

SPIMOSI

(Output)

msb lsb msb

Data

Figure 60. SPI Master (CP = 1) Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

13.10SPI Slave AC Electrical Specifications

Table 27 provides the SPI slave timings as shown in Figure 61 and Figure 62.

Table 27. SPI Slave Timing

Num Characteristic

All

Frequencies

Min Max

Unit

170 Slave cycle time 2 — t 171 Slave enable lead time 15 — ns 172 Slave enable lag time 15 — ns 173 Slave clock (SPICLK) high or low time 1 — t 174 Slave sequential transfer delay (does not require deselect) 1 — t 175 Slave data setup time (inputs) 20 — ns 176 Slave data hold time (inputs) 20 — ns 177 Slave access time — 50 ns

SPISEL

(Input)

171172

174

SPICLK

(CI=0)

(Input)

181182173

173 170

SPICLK

(CI=1)

(Input)

177 182

180

181

178

cyc

SPIMISO

(Output)

SPIMOSI

(Input)

175 179

176 182

msb lsb msb

Datamsb lsb msbUndef

181

Data

Figure 61. SPI Slave (CP = 0) Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

64 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

SPISEL

(Input)

171 170

SPICLK

(CI=0) (Input)

173

SPICLK

(CI=1) (Input)

177 182

173

180

172

174

181182

181

178

PIMISO

(Output)

175 179

PIMOSI

(Input)

msb

176 182

msb lsb

Data

181

Data

lsbUndef

Figure 62. SPI Slave (CP = 1) Timing Diagram

13.11I2C AC Electrical Specifications

Table 28 provides the I2C (SCL < 100 KHz) timings.

Table 28. I2C Timing (SCL < 100 KHZ)

All

Num Characteristic

200 SCL clock frequency (slave) 0 100 KHz 200 SCL clock frequency (master) 202 Bus free time between transmissions 4.7 — µs

Frequencies

Min Max

1.5 100 KHz

msb

Unit

203 Low period of SCL 4.7 — µs 204 High period of SCL 4.0 — µs 205 Start condition setup time 4.7 — µs 206 Start condition hold time 4.0 — µs 207 Data hold time 0 — µs 208 Data setup time 250 — ns 209 SDL/SCL rise time — 1 µs

MPC875/MPC870 Hardware Specifications, Rev. 3.0

65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

CPM Electrical Characteristics

Table 28. I2C Timing (SCL < 100 KHZ) (continued)

Num Characteristic

210 SDL/SCL fall time — 300 ns

211 Stop condition setup time 4.7 — µs

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scalar × 2).

The ratio SyncClk/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.

Frequencies

Min Max

Table 29 provides the I2C (SCL > 100 KHz) timings.

Table 29. I2C Timing (SCL > 100 KHZ)

All Frequencies

Num Characteristic Expression

Min Max

200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz 200 SCL clock frequency (master)

fSCL BRGCLK/16512 BRGCLK/48 Hz

All

Unit

202 Bus free time between transmissions — 1/(2.2 × fSCL) — s 203 Low period of SCL — 1/(2.2 × fSCL) — s 204 High period of SCL — 1/(2.2 × fSCL) — s 205 Start condition setup time — 1/(2.2 × fSCL) — s 206 Start condition hold time — 1/(2.2× fSCL) — s 207 Data hold time — 0 — s 208 Data setup time — 1/(40 × fSCL) — s 209 SDL/SCL rise time — — 1/(10 × fSCL) s 210 SDL/SCL fall time — — 1/(33 × fSCL) s

211 Stop condition setup time — 1/2(2.2 × fSCL) — s

SCL frequency is give n by SCL = BrgClk_freq uency / ((BRG reg ister + 3)× pre_scalar × 2).

The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

66 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

USB Electrical Characteristics

Figure 63 shows the I2C bus timing.

SDA

202

205

SCL

206 209 211210

203

207

Figure 63. I2C Bus Timing Diagram

204

208

14 USB Electrical Characteristics

This section provides the AC timings for the USB interface.

14.1 USB Interface AC Timing Specifications

The USB Port uses the transmit clock on SCC1. Table 30 lists the USB interface timin gs.

Table 30. USB Interface AC Timing Specifications

Name Characteristic

US1 USBCLK frequency of operation

Low speed Full speed

All Frequencies

Min Max

Unit

MHz MHz

US4 USBCLK duty cycle (measured at 1.5 V) 45 55 %

USBCLK accuracy should be ± 500 ppm or better. USBCLK may be stopped to conserve power.

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

15.1 MII and Reduced MII Receive Signal Timing

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

FEC Electrical Characteristics

Table 31 provides information on the MII receive signal timing.

Table 31. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period

M1_R

M2_R

RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK

MII

setup RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR

MII

hold

Figure 64 shows MII receive signal timing.

MII_RX_CLK (input)

MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER

Figure 64. MII Receive Signal Timing Diagram

4— ns

2— ns

15.2 MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%.

Table 32 provides information on the MII transmit signal timing.

Table 32. MII Transmit Signal Timing

Num Characteristic Min Max Unit

M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 ns M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period

MPC875/MPC870 Hardware Specifications, Rev. 3.0

68 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

FEC Electrical Characteristics

Table 32. MII Transmit Signal Timing (continued)

Num Characteristic Min Max Unit

M20_R

M21_R

RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup 4 — ns

MII

RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising

MII

edge

Figure 65 shows the MII transmit signal timing diagram.

MII_TX_CLK (input)

MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER

Figure 65. MII Transmit Signal Timing Diagram

2— ns

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 33 provides information on the MII async inputs signal timing.

Table 33. MII Async Inputs Signal Timing

Num Characteristic Min Max Unit

M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period

Figure 66 shows the MII asynchronous inputs signal timing diagram.

MII_CRS, MII_COL

Figure 66. MII Async Inputs Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

FEC Electrical Characteristics

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 34. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M10 MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns M14 MII_MDC pulse width high 40% 60% MII_MDC period M15 MII_MDC pulse width low 40% 60% MII_MDC period

0— ns

Figure 67 shows the MII serial management channel timing diagram.

M14

MM15

MII_MDC (output)

M10

MII_MDIO (output)

M11

MII_MDIO (input)

M12

M13

Figure 67. MII Serial Management Channel Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

70 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Mechanical Data and Ordering Information

16 Mechanical Data and Ordering Information

Table 35 identifies the packages and operating frequencies available for the MPC875/870.

Table 35. Available MPC875/870 Packages/Frequencies

Package Type Temperature (Tj) Frequency (MHz) Order Number

Plastic ball grid array ZT suffix — Leaded VR suffix — Lead-Free are available as needed

Plastic ball grid array CZT suffix — Leaded CVR suffix — Lead-Free are available as needed

0°C to 95°C 66 KMPC875ZT66

KMPC870ZT66

MPC875ZT66 MPC870ZT66

80 KMPC875ZT80

KMPC870ZT80

MPC875ZT80 MPC870ZT80

133 KMPC875ZT133

KMPC870ZT133

MPC875ZT133 MPC870ZT133

-40°C to 100°C 66 KMPC875CZT66 KMPC870CZT66

MPC875CZT66 MPC870CZT66

133 KMPC875CZT133

KMPC870CZT133

MPC875CZT133 MPC870CZT133

16.1 Pin Assignments

Figure 68 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional

information, see the MPC885 PowerQUICC Family User’s Manual.

NOTE

The pin numbering starts with B2 in order to conform to the JEDEC standard for 23-mm body size using a 16× 16 array.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Mechanical Data and Ordering Information

NOTE: This is the top view of the device.

234567 8910111213141516

MODCK2

EXTCLK MODCK1 OP0 ALEA IPB0 BURST IRQ6 BR TEA BI CS0 CS3 CS5 N/C

TEXP

IPA7

RSTCONF

SRESETBADDR29 OP1

ALEB IRQ2 BB

TA BDIP CS2 CE1A GPLAB3 GPLA0

IPA4

IPA2

PORESET EXTAL BADDR30 IPB1 BG GPLA4 GPLA5 WR CE2A CS7 WE2

WAITA

XTAL

D31

IPA5

IPA3 VDDSYN

VSSSYN

HRESET BADDR28 IRQ3

IRQ4

GPLB4 CS4 GPLAB2 WE0 BSA1 BSA2

CS1

D29

D30

IPA6

IPA1

D28

CLKOUT

D26

VDDL

VSSSYN1 CS6

IPA0

VDDH VDDH

VDDL

WE3

BSA0

TSIZ1 A26

D22 D6 D24

VDDH

VDDL GND

D25

VDDH

VDDL

A28 A30

D18

D19

D20

D21

GND

A23 A21

VDDH

VDDL

VDDH

MII_MDIO

A14 A19

A10 A12

A2 A8

A1 A6

D11

D10

D23 D17 PE22

D15 D16

D27

D9 D12

D13

VDDH

GND

VDDH

VDDL

GND

VDDH

VDDL

D14

IRQ0

PE18

PA2 PB26 PB27

IRQ7

IRQ1

PA0 PE14 PE31 PC6 PA6 PC11 TDO PA15 A3PA4

D4 D8 PE25

PA3

PE28 PE30 PA11 MII_COL PA7 TCK PB28 PC15PE19

PA10

PD8

PE26

PE20 PE23 MII-TX-EN

N/C

PB31

PA1 N/C PB30PE27

PE16

PE17 PE21 PC7 PB19 PB24 TDI TMS PC12

PE15

PE29 PE24 PC13 MII-CRS PC10 PB23 PB25

TRST GND

BSA3

WE1

TSIZ0 A31

A22 A18

A25 A24

A20 A29

A27 A17

A15 A16

A11 A13

A7 A9

A5 A4

A0 PB29

PA14 N/C

Figure 68. Pinout of the PBGA Package—JEDEC Standard

Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments.

Table 36. Pin Assignments—JEDEC Standard

Name Pin Number Type

A[0:31] R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16,

L15, M17, K14, L16 , L 17, K17, G17, K15, J16, J1 5, G 1 6, J 14 , H 17 , H16, G15, K16, H14, J17, H15, F17

TSIZ0

F16 Bidirectional

REG

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Bidirectional Three-state (3.3 V only)

Three-state (3.3 V only)

Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

TSIZ1 G14 Bidirectional

D13 Bidirectional

RD/WR

Three-state (3.3 V only)

BURST

BDIP GPL_B5

TEA BI B13 Bidirectional

IRQ2 RSV

IRQ4 KR RETRY SPKROUT

D[0:31] L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4,

CR IRQ3

B9 Bidirectional

Three-state (3.3 V only)

C13 Output

C11 Bidirectional

Active pull-up (3.3 V only)

C12 Bidirectional

Active pull-up (3.3 V only)

B12 Open-drain

Active pull-up (3.3 V only)

C9 Bidirectional

Three-state (3.3 V only)

E9 Bidirectional

Three-state (3.3 V only)

Bidirectional

P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2 E10 Input

Three-state (3.3 V only)

FRZ IRQ6

BR BG D10 Bidirectional (3.3 V only) BB C10 Bidirectional

IRQ0 IRQ1 P5 Input (3.3 V only) IRQ7 N5 Input (3.3 V only) CS[0:5] B14, E11, C14, B15, E13, B16 Output CS6

CE1_B CS7

CE2_B

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B10 Bidirectional

Three-state (3.3 V only)

B11 Bidirectional (3.3 V only)

Active pull-up (3.3 V only)

M6 Input (3.3 V only)

F12 Output

D15 Output

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

WE0 BS_B0 IORD

WE1 BS_B1 IOWR

WE2 BS_B2 PCOE

WE3 BS_B3 PCWE

BS_A

[0:3] F14, E16, E17, F15 Output

GPL_A0 GPL_B0

OE GPL_A1 GPL_B1

GPL_A

[2:3]

GPL_B

[2:3]

[2–3]

CS UPWAITA

GPL_A4

E15 Output

D17 Output

D16 Output

G13 Output

C17 Output

F13 Output

E14, C16 Output

D11 Bidirectional (3.3 V only)

UPWAITB GPL_B4

GPL_A5 PORESET D5 Input (3.3 V only) RSTCONF C3 Input (3.3 V only) HRESET E7 Open-drain SRESET C4 Open-drain XTAL D6 Analog output EXTAL D7 Analog input (3.3 V only) CLKOUT G4 Output EXTCLK B4 Input (3.3 V only) TEXP B3 Output ALE_A B7 Output CE1_A C15 Output CE2_A D14 Output WAIT_A D4 Input (3.3 V only)

E12 Bidirectional

D12 Output

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

IP_A0 G6 Input (3.3 V only) IP_A1 F5 Input (3.3 V only) IP_A2

IOIS16_A IP_A3 E4 Input (3.3 V only) IP_A4 D2 Input (3.3 V only) IP_A5 E3 Input (3.3 V only) IP_A6 F4 Input (3.3 V only) IP_A7 C2 Input (3.3 V only) ALE_B

DSCK IP_B[0:1]

IWP[0:1] VFLS[0:1]

OP0 B6 Bidirectional (3.3 V only) OP1 C6 Output OP2

MODCK1 STS

OP3 MODCK2 DSDO

D3 Input (3.3 V only)

C8 Bidirectional

Three-state (3.3 V only)

B8, D9 Bidirectional (3.3 V only)

B5 Bidirectional (3.3 V only)

B2 Bidirectional (3.3 V only)

BADDR[28:29] E8, C5 Output BADDR30

REG AS PA15

USBRXD PA14

USBOE PA11

RXD4 MII1-TXD0 RMII1-TXD0

PA10 MII1-TXERR TIN4 CLK7

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D8 Output

C7 Input (3.3 V only) P14 Bidirectional

U16 Bidirectional

(Optional: open-drain)

R9 Bidirectional

(Optional: open-drain) (5-V tolerant)

R12 Bidirectional

(Optional: open-drain) (5-V tolerant)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PA7 CLK1 BRGO1 TIN1

PA6 CLK2 TOUT1

PA4 CTS4 MII1-TXD1 RMII-TXD1

PA3 MII1-RXER RMII1-RXER BRGO3

PA2 MII1-RXDV RMII1-CRS_DV TXD4

PA1 MII1-RXD0 RMII1-RXD0 BRGO4

R11 Bidirectional

P11 Bidirectional

P7 Bidirectional

R5 Bidirectional

(5-V tolerant)

N6 Bidirectional

(5-V tolerant)

T4 Bidirectional

(5-V tolerant)

PA0 MII1-RXD1 RMII1-RXD1 TOUT4

PB31 SPISEL MII1 - TXCLK RMII1-REFCLK

PB30 SPICLK

PB29 SPIMOSI

PB28 SPIMISO BRGO4

PB27 I2CSDA BRGO1

PB26 I2CSCL BRGO2

P6 Bidirectional

(5-V tolerant)

T5 Bidirectional

(Optional: open-drain) (5-V tolerant)

T17 Bidirectional

(Optional: open-drain) (5-V tolerant)

R17 Bidirectional

(Optional: open-drain) (5-V tolerant)

R14 Bidirectional

(Optional: open-drain) (5-V tolerant)

N13 Bidirectional

(Optional: open-drain)

N12 Bidirectional

(Optional: open-drain)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PB25 SMTXD1

PB24 SMRXD1

PB23 SDACK1 SMSYN1

PB19 MII1-RXD3 RTS4

PC15 DREQ0 L1ST1

PC13 MII1-TXD3 SDACK1

PC12 MII1-TXD2 TOUT1

PC1 1 USBRXP

U13 Bidirectional

(Optional: open-drain) (5-V tolerant)

T12 Bidirectional

(Optional: open-drain) (5-V tolerant)

U12 Bidirectional

(Optional: open-drain)

T11 Bidirectional

(Optional: open-drain)

R15 Bidirectional

(5-V tolerant)

U9 Bidirectional

(5-V tolerant)

T15 Bidirectional

(5-V tolerant)

P12 Bidirectional

PC10 USBRXN TGATE1

PC7 CTS4 L1TSYNCB USBTXP

PC6 CD4 L1RSYNCB USBTXN

PD8 RXD4 MII-MDC RMII-MDC

PE31 CLK8 L1TCLKB MII1-RXCLK

PE30 L1RXDB MII1-RXD2

U11 Bidirectional

T10 Bidirectional

(5-V tolerant)

P10 Bidirectional

(5-V tolerant)

T3 Bidirectional

(5-V tolerant)

P9 Bidirectional

(Optional: open-drain)

R8 Bidirectional

(Optional: open-drain)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PE29 MII2-CRS

PE28 TOUT3 MII2-COL

PE27 L1RQB MII2-RXERR RMII2-RXERR

PE26 L1CLKOB MII2-RXDV RMII2-CRS_DV

PE25 RXD4 MII2-RXD3 L1ST2

PE24 SMRXD1 BRGO1 MII2-RXD2

PE23 TXD4 MII2-RXCLK L1ST1

U7 Bidirectional

(Optional: open-drain)

R7 Bidirectional

(Optional: open-drain)

T6 Bidirectional

(Optional: open-drain)

T2 Bidirectional

(Optional: open-drain)

R4 Bidirectional

(Optional: open-drain)

U8 Bidirectional

(Optional: open-drain)

U4 Bidirectional

(Optional: open-drain)

PE22 TOUT2 MII2-RXD1 RMII2-RXD1 SDACK1

PE21 TOUT1 MII2-RXD0 RMII2-RXD0

PE20 MII2-TXER

PE19 L1TXDB MII2-TXEN RMII2-TXEN

PE18 SMTXD1 MII2-TXD3

P4 Bidirectional

(Optional: open-drain)

T9 Bidirectional

(Optional: open-drain)

U3 Bidirectional

(Optional: open-drain)

R6 Bidirectional

(Optional: open-drain)

M5 Bidirectional

(Optional: open-drain)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

PE17 TIN3

T8 Bidirectional

(Optional: open-drain) CLK5 BRGO3 SMSYN1 MII2-TXD2

PE16 L1RCLKB

U6 Bidirectional

(Optional: open-drain) CLK6 MII2-TXCLK RMII2-REFCLK

PE15 TGATE1

T7 Bidirectional

MII2-TXD1 RMII2-TXD1

PE14

P8 Bidirectional MII2-TXD0 RMII2-TXD0

TMS T14 Input

(5-V tolerant)

TDI DSDI

TCK DSCK

T13 Input

(5-V tolerant)

R13 Input

(5-V tolerant)

TRST U14 Input

(5-V tolerant)

TDO DSDO

P13 Output

(5-V tolerant) MII1_CRS U10 Input MII_MDIO M13 Bidirectional

(5-V tolerant) MII1_TX_EN

RMII1_TX_EN

U5 Output

(5-V tolerant) MII1_COL R10 Input V

SSSYN

SSSYN1

DDSYN

GND H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10,

E5 PLL analog GND F6 PLL analog GND E6 PLL analog V

Power

L11, U15

DDL

F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8,

Power

N9, N10, N11

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pin Number Type

DDH

G7, G8, G9, G10, G1 1, G12, H7, H12, J7, J12 , K7, K12, L7, L12, M7,

Power

M8, M9, M10, M11, M12

N/C B17, T16, U2, U17 No-connect

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

16.2 Mechanical Dimensions of the PBGA Package

Figure 69 shows the mechanical dimensions of the PBGA package.

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.

3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DEFINE D BY T H E SP H ERI C AL CR O W NS O F THE SOLDER BALLS.

Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX.

Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX.

Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Document Revision History

17 Document Revision History

Table 37 lists significant changes between revisions of this hardware specification.

Table 37. Document Revision History

Revision

Number

0 2/2003 Initial release.

0.1 3/2003 Took out the time-slot assigner and changed the SCC for SCC3 to SCC4.

0.2 5/2003 Changed the package drawin g, removed all refere nces to Data Parity. Changed the SPI

0.3 5/2003 Made sure the pin types were correct. Changed the Features list to agree with the

0.4 5/2003 Corrected the sign als that had overlines o n them. Made correcti ons on two pins that we re

0.5 5/2003 Changed the pin descriptions for PD8 and PD9.

0.6 5/2003 Changed a few typos. Pu t back the I2C. Pu t in the new rese t configuratio n, corrected th e

0.7 6/2003 Changed the pin descriptions per the June 22 spec, removed Utopia from the pin

0.8 8/2003 Added the reference to USB 2.0 to the Features list and removed 1.1 from USB on the

0.9 8/2003 Changed the USB description to full-/low-speed compatible.

Date Changes

Master Timi ng Specs. 162 and 164. Added the RMII an d USB timing. Adde d the 80-MHz timing.

MPC885.

typos.

USB timing.

descriptions, changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the Mandatory Reset Config.

block diagrams.

1.0 9/2003 Added t he DSP inform ation in the F eatures list. Put a new sentence under Mechanical Dimensions. Fixed table formatting. Nontechnical edits. Released to the external web.

1.1 10/2003 Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5 Serial Interface AC Electrical Specifications, and removed TDMa from the pin descriptions.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Table 37. Document Revision History (continued)

Document Revision History

Revision

Number

2.0 12/2003 Changed DBGC in the Mandatory Reset Configuration to X1.

3.0 1/07/2004

Date Changes

Changed the maximum operating frequency to 133 MHz. Put the timing in the 80 MHz column. Put in the orderable part numbers. Rounded the timings to hundredths in the 80 MHz column. Put the pin numbers in footnotes by the maximum currents in Table 6. Changed 22 and 41 in the Timing. Put TBD in the Thermal table.

• Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for

7/19/2004

Integer Values

• Added a footnote to Spec 41 specifying that EDM = 1

• Added the thermal numbers to Table 4.

• Added RMII1_EN under M1II_EN in Table 36 Pin Assignments

• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL

Max of the I2C Sta nda rd

• Put the new part numbers in the Ordering Information Section

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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MPC875EC Rev. 3.0 07/2004

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Freescale MPC875, MPC870 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual