Freescale MPC875, MPC870 User Guide

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Freescale Semiconductor

MPC875/MPC870
Hardware Specifications

This hardware specification contains detailed informatio n on
power considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC875/MPC870. The CPU on the
MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates
memory management units (MMUs) and instruction and data
caches and that implements the PowerPC instruction set. This
hardware specification covers the following topics:

1Overview

The MPC875/MPC870 is a versatile single-chip integrated
microprocessor and peripheral combination that can be used in a
variety of controller applications and communications and
networking systems. The MPC875/MPC870 provides enhanced
ATM functionality over that of other ATM-enabled members of
the MPC860 family.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. Thermal Calculation and Measurement . . . . . . . . . . 11

8. Power Supply and Power Sequenc in g . . . . . . . . . . . 13

9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 14

10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44

13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46

14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67

15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67

16. Mechanical Dat a and Ordering Information . . . . . . . 71

17. Document Revision History . . . . . . . . . . . . . . . . . . . 82

MPC875EC

Rev. 3.0, 07/2004

Contents

© Freescale Semiconductor, Inc., 2004. All rights reserved.

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Features

Table 1 shows the functionality supported by the members of the MPC875/MPC870.

Table 1. MPC8 75/ 870 Devi ces

Cache Ethernet

Part

I Cache D Cache 10BaseT 10/100

MPC875 8 Kbyte 8 Kbyte 1 2 1 1 1 Yes
MPC870 8 Kbyte 8 Kbyte — 2 — 1 1 No

SCC SMC USB

Security

Engine

2Features

The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM).

The following list summarizes the key MPC875/870 features:

• Embedded MPC8xx core up to 133 MHz

• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.

• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch and without conditional execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)

– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

– Caches are physi cally addresse d, implement a leas t recentl y used (LRU) repl acement algori thm, and

are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces

and 16 protection groups

— Advanced on-chip emulation debug mode

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• 32 address lines

• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS

lines, four WE lines, and one OE line

to support a DRAM bank.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

2 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Features

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic

• General-purpose timers

— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture

• Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that

interface through MII and/or RMII interfaces

• System integration unit (SIU)

— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)

• Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,

802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a
crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:

— Data encryption standard execution unit (DEU)

– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rinjdael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256-bit key lengths

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm

— Master/slave logic, w ith DMA

– 32-bit address/32- bit data
– Operation at 8xx bus frequency

— Crypto-channel supporting multi-command descriptors

– Integrated controller managing crypto-execution units
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

• Interrupts

— Six external interrupt request (IRQ) lines

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 3

Features

— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request

• Communications processor module (CPM)
— RISC controller
— Communication-specifi c commands (for example,

RESTART TRANSMIT)

GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability

•On-chip 16

× 16 multiply accumulate controller (MAC)

— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies

• Four baud-rate generators
— Independent (can be connected to any SCC or SMC)
— Allows changes during operation
— Autobaud support option

• SCC (seria l communica tion controller)
— Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
—AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))

• SMC (serial management channel)
— UART (l ow-s peed operation)
— Transparent

• Universal serial bus (USB)—Supports operatio n as a USB function end point, a USB host cont roller , or both
for testing purposes (loopback diagnostics)

— USB 2.0 full-/low-speed compatible
— The USB function mode has the following features:

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

4 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffe rs per frame
– Automatic retransmission upon transmit error

— The USB host controller has the following features:

– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1. 5-Mbps data rates (automatic g eneration of preamble tok en and data

rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffe rs per frame
– Supports local loopback mode for diagnostics (12 Mbps only)

• Serial peripheral inte rface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus

• Inter-integrated circuit (I

2

C) port
— Supports master and slave modes
— Supports a multiple-master environment

• The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb).
— Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to two serial channels (one SCC and one SMC)

• PCMCIA interface
— Master (so cket) interface, release 2.1-compliant
— Supports one independent PCMCIA socket on the MPC875/MPC870
— 8 memory or I/O windows supported

• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally.

• Normal high and normal low power modes to conserve power

• 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility

• The MPC875/870 comes in a 256-pin ball grid array (PBGA) package.

Features

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 5

Features

The MPC875 block diagram is shown in Figure 1.

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

DMAs

DMAs

FIFOs

10/100
BaseT

Media Access

Control

MIII/RMII

Instruction

Bus

Load/Store

Bus

8-Kbyte

Instruction Cache

Instruction MMU

32-Entry ITLB

8-Kbyte

Data Cache

Data MMU

32-Entry DTLB

Parallel I/O

4 Baud Rate

Generators

Parallel Interface Port

Slave/Master IF

4

Timers

Timers

Controllers

32-Bit RISC Controller

Unified

Bus

Interrupt

and Program

ROM

System Interface Unit (SIU)

Bus Interface

Security Engine

Controller

Channel

8-Kbyte

Dual-Port RAM

Memory Controller

Internal

Unit

System Functions

PCMCIA-ATA Interface

External

Bus Interface

Unit

AESU DEU MDEU

Virtual IDMA
Serial DMAs

and

USB

SCC4

Time Slot Assigner

Serial Interface

Serial Interface

Figure 1. MPC875 Block Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

SPISMC1

I2C

6 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

The MPC870 block diagram is shown in Figure 2.

Maximum Tolerated Ratings

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

DMAs

FIFOs

10/100
BaseT

Media Access

Control

MIII / RMII

Instruction

Bus

Load/Store

Bus

8-Kbyte

Instruction Cache

Instruction MMU

32-Entry ITLB

8-Kbyte

Data Cache

Data MMU

32-Entry DTLB

Parallel I/O

4 Baud Rate

Generators

Parallel Interface Port

Slave/Master IF

4

Timers

Timers

Controllers

32-Bit RISC Controller

Unified

Bus

Interrupt

and Program

ROM

System Interface Unit (SIU)

Bus Interface

8-Kbyte

Dual-Port RAM

Memory Controller

Internal

Unit

System Functions

PCMCIA-ATA Interface

External

Bus Interface

Unit

Virtual IDMA and

Serial DMAs

USB

Serial Interface

Serial Interface

SPISMC1

I2C

Figure 2. MPC870 Block Diagram

3 Maximum Tolerated Ratings

This section pro vides th e maximum tole rated vo ltage an d temperat ure range s for t he MPC875/8 70. Table 2
displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 7

Maximum Tolerated Ratings

Supply voltage

1

Table 2. Maximum Tolerated Ratings

Rating Symbol Value Unit

V

DDL

voltage)

(core

–0.3 to 3.4 V

V

DDH

(I/O

–0.3 to 4 V

voltage)
V

DDSYN

Difference

–0.3 to 3.4 V

<100 mV

between

and

V

DDL

V

DDSYN

Input voltage

Storage temperature range T

1

The power supply of the device must start its ramp from 0.0 V.

2

Functional ope rati ng co nditions are provid ed w ith t he D C electrical specific ati ons i n Table 6. Absolute maximum

2

V

in

stg

GND – 0.3 to

V

DDH

–55 to +150 °C

ratings are stress ratings only ; functional op eration at t he maxima is not guaran teed. S tress bey ond those li sted may
affect device reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power
up and normal operation (tha t is, if the MPC87 5/870 is unp owered, a volt age gr eater than 2.5 V must not be applied
to its inputs).

Table 3. Operating Temperatures

Rating Symbol Value Unit

Temperature

Temperature (extended) T

1

Minimum temperature s are guar anteed a s ambient te mperatu re, TA. Maximum temperatu res are guaran teed as

junction temperature, T

1

(standard)

T

A(min)

T

j(max)

A(min)

T

j(max)

.

j

0°C

95 °C
–40 °C
100 °C

V

This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it
is advised that normal prec autions be taken to avoid applicat ion of any voltages higher than maxi mum-rated voltages
to this high-i mpeda nce ci rcuit. Reliabilit y o f oper ation is enhanced i f unus ed inputs are tied t o a n a ppropriate logic
voltage level (for example, either GND or V

MPC875/MPC870 Hardware Specifications, Rev. 3.0

8 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

DDH

).

Thermal Characteristics

4 Thermal Characteristics

Table 4 shows the thermal characteristics for the MPC875/870.

Table 4. MPC875/870 Thermal Resistance Data

Rating Environment Symbol Value Unit

Junction-to-ambient

1

Natural convection Single-layer board (1s) R

Four-layer board (2s2p) R

Airflow (200 ft/min) Single-layer board (1s) R

Four-layer board (2s2p) R
Junction-to-board
Junction-to-case
Junction-to-package top

4

5

6

Natural convection Ψ
Airflow (200 ft/min) Ψ

1

Junction temperature is a function of on-chip power dissi pa tion, packa ge ther mal resis tan ce, mounting sit e (boa rd)

temperature, ambi ent tem peratu re, airfl ow, power dissipation of o ther co mpone nt s o n the b oard, a nd boa rd therm al
resistance.

2

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3

Per JEDEC JESD51-6 with the board horizontal.

4

Thermal resista nce b etw ee n t he di e a nd the printed cir cuit b oard per JEDEC JESD51 -8. Boar d te mp era t ure is

measured on the top surface of the board near the package.

5

Indicates the average thermal resist an ce be tw een the di e a nd the case top surface as me as ured by th e c ol d pl ate

method (MIL SPEC-883 Method 1012.1) with the cold pl ate temperature us ed for the c ase temperature. F or exposed
pad packages whe re the pad would be expected to be s old ere d, junction-to-case therma l res is t an ce is a si mu lated
value from the junction to the exposed pad without contact resistance.

6

Thermal characteri zation parameter ind ic ati ng the te mp era ture difference b etwee n the package top an d the junction

temperature per JEDEC JESD51-2.

θJA

θJMA

θJMA

θJMA

R

θJB

R

θJC

2

3

3

3

43 °C/W
29
36
26
20
10

JT

JT

2
2

5 Power Dissipation

Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are

equal, and 2:1, where CPU frequency is twice bus speed.

Table 5. Power Dissipation (PD)

Die Revision

Bus

Mode

Frequency Typical

66 MHz 310 390 mW

1:1

0

80 MHz 350 430 mW

2:1 133 MHz 430 495 mW

1

Typical power dissipation is measured at V

DDL

= V

DDSYN

= 1.8 V, and V

is at 3.3 V.

DDH

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 9

1

Maximum

2

Unit

DC Characteristics

2

Maximum power dissipation at V

The values in Table 5 represent V
include I/O power dissipation over V
widely by application due to buffer current, depending on external
circuitry.

DDL

= V

= 1.9 V, and V

DDSYN

is at 3.5 V.

DDH

NOTE

-based power diss ipati on an d d o not

DDL

. I/O power d issipation varies

DDH

The V

DDSYN

power dissipation is negligible.

6 DC Characteristics

Table 6 provides the DC electrical characteristics for the MPC875/870.

T able 6. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltag e V

V

Input high voltage (all inputs except EXTAL and EXTCLK)
Input low voltage

3

EXTAL, EXTCLK input high voltage V
Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and

DSDI pins) for 5-V tolerant pins

1

2

(I/O) 3.135 3.465 V

DDH

(Core) 1.7 1.9 V

DDL

DDSYN

1

1.7 1.9 V
— 100 mV

V

Difference

between

and

V

DDL

V

DDSYN

V
V

IHC

I

in

IH

IL

2.0 3.465 V

GND 0.8 V

0.7 × V

DDH

V

DDH

— 100 µA

V

Input leakage current, Vin = V

(except TMS, TRST, DSCK, and

DDH

I

In

—10µA

DSDI)
Input leakage current, Vin = 0 V (exc ept TMS, TRST

, DSCK and DSDI

I

In

—10µA

pins)
Input capacitance

4

Output high voltage, IOH = –2.0 mA, V

DDH

= 3.0 V

C

in

V

OH

—20pF

2.4 — V

except XTAL and open-drain pins
Output low voltage

IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA
IOL = 5.3 mA

5
6

V

OL

—0.5V

IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
IOL = 8.9 mA (TS

1

The difference between V

2

The signals P A[0:15], PB[14:31 ], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST , TMS, MII1_TXEN, MII_M DIO

, TA, TEA, BI, BB, HRESET, SRESET)

DDL

and V

cannot be more than 100 mV.

DDSYN

are 5-V tolerant. The minimum voltage is still 2.0 V.

3

VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

10 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Thermal Calculation and Measurement

4

Input capaci tance is periodically sampled.

5

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(0:1), PA(0: 4), P A(6:7), PA(10:11), PA15,

PB19, PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL.

6

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,

(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A , CE1_A, CE2_A,

GPL_A
OP(0:3) BADDR(28:30

7 Thermal Calculation and Measurement

For the foll owing discu ssions, PD = (V

DDL

× I

DDL

) + P

, where P

I/O

is the power dissipation of the I/O

I/O

drivers.

NOTE

The V

DDSYN

power dissipation is negligible.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:

T

= TA + (R

J

θJA

× PD)

where:

T

= ambient temperature ºC

A

R

= package j unction-to-a mbient ther mal resistance (ºC/W)

θJA

P

= power dissipation in package

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of ther mal pe rf ormance. However , the answer is onl y an es timate; test cases have demonstrated
that errors of a factor of two (in the quantity T

) are possible.

J–TA

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically, thermal resistance has frequently been ex pressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:

R

θJA

= R

θJC

+ R

θCA

where:

R

= junction-to-ambient thermal resistance (ºC/W)

θJA

R

= junction-to-case thermal resistance (ºC/W)

θJC

R

= case-to-ambient thermal resistance (ºC/W)

θCA

is device-related and cannot be influenced by the user. The user adjusts the thermal environment to

R

θJC

affect the case-to-ambient thermal resistance, R

. For instance, the user can change the airflow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful
for ceramic pack age s wi th heat sinks where some 90% of the heat flows th rou gh the case and the h eat sink
to the ambient environment. For most packages, a better model is required.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 11

Thermal Calculation and Measuremen t

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model
consisting of a junc ti on-to- board and a ju nctio n-to- case t herma l res ista nce. The j unc tion- to-ca se the rmal re sist ance
covers the situ ation where a heat sink i s u sed or where a subst antia l am ount of heat is di ssipa ted from t he top of the
package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages
and especially PBGA packa ges is st rongl y depende nt on the bo ard tempe ratur e. If the boa rd temper atur e is known,
an estimate of the junction temperature in the environment can be made using the following equation:

T

= TB + (R

J

where:

R

= junction-to-board thermal resistance (ºC/W)

θJB

T

= board temperature ºC

B

P

= power dissipation in package

D

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and vias attaching the thermal balls to the ground plane.

θJB

× PD)

7.4 Estimation Using Simulation

When the board temperatur e is not known, a therma l simulation of the appl ication is needed . The simple two-resistor
model can be used with the therma l simula tion of t he app licat ion [2] , or a more ac curate and co mple x model of the
package can be used in the thermal simulation.

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (Ψ
temperature at the top center of the package case using the following equation:

T

= TT + (ΨJT× PD)

J

where:

= thermal characterization parameter

Ψ

JT

T

= thermocouple temperature on top of package

T

P

= power dissipation in package

D

The thermal charact erization para meter is measured pe r the JESD51-2 spec ification publ ished by JEDEC using a 40
gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire ex tending f rom the junc tion. The ther mocouple wire is plac ed flat a gainst th e
package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

) can be use d to determine the junction temperature with a measurement of the

JT

MPC875/MPC870 Hardware Specifications, Rev. 3.0

12 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Power Supply and Power Sequencing

7.6 References

Semiconductor Equipment and Materials International [phone]
805 East Middlefield Rd
Mountain Vi ew, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or
(Available from Global Engineering Documents) 303-397-7956

JEDEC Specifications http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams , “Measur ement a nd Simul ation of Jun ction to Boar d Ther mal Re sistanc e and I ts
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

8 Power Supply and Power Sequencing

This section provides design considerations for the MPC875/870 power supply. The MPC875/870 has a
core voltage (V
V

. The I/O section of the MPC875/870 is supplied with 3.3 V across V

DDH

The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI,
TDO, TCK, TRST
greater than V
exceed 3.465 V. This restriction applies to power up/down and normal operation.

) and PLL voltage (V

DDL

DDSYN

), which both operate a t a lower voltage than t he I/O voltage

and VSS (GND).

DDH

, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. No input can be more than 2.5 V
. In addition, 5 V-tolerant pins cannot exceed 5.5 V, and remaining input pins cannot

DDH

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:

•V

•V

must not exceed V

DDL

must not exceed 1.9 V, and V

DDL

DDH

during power up and power down.

must not exceed 3.465 V.

DDH

These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection di odes are forwa rd-biased, and excessive curren t can flow thr ough these dio des.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference betwe en the ext ern al bus and core power supplie s on power up, and th e 1N5820 di odes reg ulate
the maximum potential difference on power down.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconduc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 13

Mandatory Reset Configurations

V

DDH

MUR420

1N5820

V

DDL

Figure 3. Example Voltage Sequencing Circuit

9 Mandatory Reset Configurations

The MPC875/870 requires a mandatory configuration during reset.
If hardware reset conf iguratio n word (HRCW) is enabl ed, the HRCW[DBGC] valu e needs to be se t to binar y X1 in

the HRCW and the SIUMCR[DBGC] should be pr ogram med with t he same va lue in the boo t code a fter reset . This
can be done by asserting the RSTCONF

If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by
negating the RSTCONF

during the HRESET assertion.

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the
mandatory values in Table 7 in the boot code after the reset is negat ed.

during HRESET assertion.

Table 7. Mandatory Reset Configuration of MPC875/870

Register/Configuration Field

HRCW
(Hardware reset configuration word)

SIUMCR
(SIU module configuration register)

MBMR
(Machine B mode register)

PAPAR
(Port A pin assignment register)

PADIR
(Port A data direction re gister)

PBPAR
(Port B pin assignment register)

PBDIR
(Port B data direction re gister)

PCPAR
(Port C pin assignment register)

Value

(binary)

HRCW[DBGC] X1

SIUMCR[DBGC] X1

MBMR[GPLB4DIS} 0

PAPAR[5:9]
PAPAR[12:13]

PADIR[5:9]
PADIR[12:13]

PBPAR[14:18]
PBPAR[20:22]

PBDIR[14:8]
PBDIR[20:22]

PCPAR[4:5]
PCPAR[8:9]
PCPAR[14]

0

0

0

0

0

MPC875/MPC870 Hardware Specifications, Rev. 3.0

14 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Layout Practices

Table 7. Mandatory Reset Configuration of MPC875/870 (continued)

Register/Configuration Field

PCDIR
(Port C data direction register)

PDPAR
(Port D pin assignment register)

PDDIR
(Port D data direction register)

PCDIR[4:5]
PCDIR[8:9]
PCDIR[14]

PDPAR[3:7]
PDPAR[9:5]

PDDIR[3:7]
PDDIR[9:15]

Value

(binary)

0

0

0

10 Layout Practices

Each VDD pin on the MPC875/870 s hould be prov ided with a low-impedance p ath to the boa rd’ s supply . Each GND
pin should likewise be provid ed with a low-impe dance path to gr ound. The power su pply pins drive di stinct gro ups
of logic on chip. The V
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropr iate decoupling cap aci tors should be used if required. The capacitor leads a nd ass oci at ed printed
circuit traces connecting to chip V
minimum, a four-layer board employing two inner layers as V

All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommended. Capacitan ce calculations sho uld consider all device loa ds as well as parasitic ca pacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads bec ause these loads create hig her transient current s in the V
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (V
V

SSSYN

, V

SSSYN1

),” of the MPC885 PowerQUICC Family User’s Manual.

power supply should be bypassed to ground using at l ea st fou r 0.1 -µF bypass capacitors

DD

and GND should be kept to less than half an inch per capacitor lead. At a

DD

and GND planes should be used.

DD

and GND circuits. Pull up all unused

DD

DDSYN

,

11 Bus Signal Timing

The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (fo r example, an MPC875/870 used at 133 MHz must be configured f or a 66 MHz bus). Table 8
shows the frequency ranges f or stand ar d part frequ encies in 1:1 bus mode , and Table 9 shows the frequency ranges
for standard part frequencies in 2:1 bus mode.

Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part Frequency 66 MHz 80 MHz

Min Max Min Max

Core frequency 40 66.67 40 80
Bus frequency 40 66.67 40 80

MPC875/MPC870 Hardware Specifications, Rev. 3.0

15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Part Frequenc y 66 MHz 80 MHz 133 MHz

Min Max Min Max Min Max

Core frequency 40 66.67 40 80 40 133
Bus frequency 20 33.33 20 40 20 66

Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz.

The timing for the MPC875/870 bus shown assumes a 50-pF load f or maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay

Table 10. Bus Operation Timings

33 MHz 40 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

B1 Bus period ( CLKOUT), see Table 8 ————————ns

Unit

B1a EXTCLK to CLKOUT phase skew - If

CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with th e rising edge of CLKO UT .
For a non-integer m ultiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a

continuously varying phase skew.
B1b CLKOUT frequency jitter pea k-to -pe ak — 1 — 1 — 1 — 1 ns
B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 %
B1d CLKOUT phase jitter peak-to-peak

for OSCLK ≥ 15 MHz

CLKOUT phase jitter peak-to-peak

for OSCLK < 15 MHz

B2 CLKOUT pulse width low

(MIN = 0.4

B3 CLKOUT pulse width high

(MIN = 0.4

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns
B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:30),

RD/WR

(MIN = 0.25

× B1, MAX = 0.6 × B1)

× B1, MAX = 0.6 × B1)

, BURST, D(0:31) output hold

× B1)

–2 +2 –2 +2 –2 +2 –2 +2 ns

—4—4—4—4ns

—5—5—5—5ns

12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns

12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns

7.60 — 6.30 — 3.80 — 3.13 — ns

B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,

PTR output hold (MIN = 0.25
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),

VF(0:2) IWP(0:2), LWP(0:1), STS

hold (MIN = 0.25

16 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

× B1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

× B1)

output

7.60 — 6.30 — 3.80 — 3.13 — ns

7.60 — 6.30 — 3.80 — 3.13 — ns

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B8 CLKOUT to A(0:31), BADDR(28:30)

RD/WR

(MAX = 0.25
B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,

PTR valid (MAX = 0.25
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),

IWP(0:2), FRZ, LWP(0:1), STS

(MAX = 0.25 × B1 + 6.3)

B9 CLKOUT to A(0:31), BADDR(28:30),

RD/WR

RSV

(MAX = 0.25
B1 1 CLKOUT to TS, BB assertion

(MAX = 0.25

B1 1a CLKOUT to TA, BI assertion (when driven

by the memory controller or PCMCIA

interface) (MAX = 0.00 × B1 + 9.30 1)
B12 CLKOUT to TS, BB negation

(MAX = 0.25

B12a CLKOUT to TA, BI negation (when driven

by the memory controller or PCMCIA

interface) (MAX = 0.00 × B1 + 9.00)

, BURST, D(0:31) valid

× B1 + 6.3)

× B1 + 6.3)

valid

, BURST , D(0:31), TSIZ(0:1), REG ,

, PTR High-Z

× B1 + 6.3)

× B1 + 6.0)

× B1 + 4.8)

2

—13.80—12.50—10.00— 9.43 ns

—13.80—12.50—10.00— 9.43 ns

—13.80—12.50—10.00— 9.43 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns

2.50 9.30 2.50 9.30 2.50 9.80 2.5 9.3 ns

7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns

B13 CLKOUT to TS, BB High-Z

(MIN = 0.25

B13a CLKOUT to T A, BI High-Z (whe n driven by

the memory controller or PCMCIA

interface) (MIN = 0.00× B1 + 2.5)
B14 CLKOUT to TEA assertion

(MAX = 0.00
B15 CLKOUT to TEA High-Z

(MIN = 0.00
B16 TA, BI valid to CLKOUT (setup time)

(MIN = 0.00

B16a TEA, KR, RETRY, CR valid to CLKOUT

(setup time) (MIN = 0.00

B16b BB, BG, BR, valid to CLKOUT (setup time)

B17a CLKOUT to KR, RETRY, CR valid (hold

2

(4MIN = 0.00 × B1 + 0.00)

B17 CLKOUT to T A, TEA, BI, BB , BG, BR valid

(hold time) (MIN = 0.00

time) (MIN = 0.00

× B1)

× B1 + 9.00)

× B1 + 2.50)

× B1 + 6.00)

× B1 + 2.00)

× B1 + 4.5)

× B1 + 1.00

3

)

7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

6.00 — 6.00 — 6.00 — 6 — ns

4.50 — 4.50 — 4.50 — 4.50 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

1.00 — 1.00 — 2.00 — 2.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B18 D(0:31) valid to CLKOUT rising edge

(setup time)
B19 CLKOUT rising edge to D (0:31) valid (hold

time)
B20 D(0:31) valid to CLKOUT falling edge

(setup time)
B21 CLKOUT falling edge to D(0:31) valid

(hold time)

4

(MIN = 0.00 × B1 + 6.00)

4

(MIN = 0.00 × B1 + 1.00 5)

6

(MIN = 0.00 × B1 + 4.00)

6

(MIN = 0.00 × B1 + 2.00)

B22 CLKOUT rising edge to CS asserted

GPCM ACS = 00 (MAX = 0.25

× B1 + 6.3)

B22a CLKOUT falling edge to CS as sert ed

GPCM ACS = 10, TRLX = 0

(MAX = 0.00 × B1 + 8.00)

B22b CLKOUT falling edge to CS as sert ed

GPCM ACS = 11, TRLX = 0, EBDF = 0

(MAX = 0.25

× B1 + 6.3)

B22c CLKOUT falling edge to CS assert ed

GPCM ACS = 11, TRLX = 0, EBDF = 1

(MAX = 0.375 × B1 + 6.6)
B23 CLKOUT rising edge to CS negated

GPCM read access, GPCM write access

ACS = 00, TRLX = 0 & CSNT = 0

(MAX = 0.00

× B1 + 8.00)

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 2.00 — 2.00 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

— 8.00 — 8.00 — 8.00 — 8.00 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns

B24 A(0:31) and BADDR(28:30) to CS

5.60 — 4.30 — 1.80 — 1.13 — ns
asserted GPC M ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)

B24a A(0:31) and BADDR(28:30) to CS

13.20 — 10.50 — 5.60 — 4.25 — ns
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50

B25 CLKOUT rising edge to OE,

WE

(0:3)/BS_B[0:3] asserted

(MAX = 0.00

B26 CLKOUT rising edge to OE negated

(MAX = 0.00

B27 A(0:31) and BADDR(28:30) to CS

× B1 – 2.00)

— 9.00 9.00 9.00 — 9.00 ns

× B1 + 9.00)

2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns

× B1 + 9.00)

35.90 — 29.30 — 16.90 — 13.60 — ns
asserted GPC M ACS = 10, TRLX = 1
(MIN = 1.25 × B1 – 2.00)

B27a A(0:31) and BADDR(28:30) to CS

43.50 — 35.50 — 20.70 — 16.75 — ns
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 × B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

18 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B28 CLKOUT rising edge to

WE

(0:3)/BS_B[0:3] negated GPCM write
access CSNT = 0
(MAX = 0.00

B28a CLKOUT falling edge to

WE

(0:3)/BS_B[0:3] negated GPCM write
access TRLX = 0, CSNT = 1, EB DF = 0
(MAX = 0.25

B28b CLKOUT falling edge to CS neg ate d

GPCM write access TRLX = 0, CSNT = 1
ACS = 10 or ACS = 11, EBDF = 0
(MAX = 0.25

B28c CLKOUT falling edge to

WE

(0:3)/BS_B[0:3] negated GPCM write
access TRLX = 0, CSNT = 1 write access
TRLX = 0, CSNT = 1, EBDF = 1
(MAX = 0.375

B28d CLKOUT falling edge to CS neg ate d

GPCM write access TRLX = 0, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
(MAX = 0.375

B29 WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, CSNT = 0,
EBDF = 0 (MIN = 0.25

× B1 + 9.00)

× B1 + 6.80)

× B1 + 6.80)

× B1 + 6.6)

× B1 + 6.6)

× B1 – 2.00)

— 9.00 — 9.00 — 9.00 — 9.00 ns

7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns

—14.30—13.00—10.50— 9.93 ns

10.90 18.00 10.90 18.00 5.20 12.30 4.69

— 18.00 — 18.00 — 12.30 — 11.30 ns

5.60 — 4.30 — 1.80 — 1.13 — ns

11.29

ns

B29a WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0
(MIN = 0.50

B29b CS negated to D(0:31) High-Z G PCM write

access, ACS = 00, TRLX = 0 & CSNT = 0
(MIN = 0.25 × B1 – 2.00)

B29c CS negated to D (0:31) High-Z GPCM write

access, TRLX = 0, CSNT = 1, ACS = 10,
or ACS = 11 EBDF = 0
(MIN = 0.50

B29d WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0
(MIN = 1.50

B29e CS negated to D(0:31) High-Z G PCM write

access, TRLX = 1, CSNT = 1, ACS = 10,
or ACS = 11, EBDF = 0
(MIN = 1.50

× B1 – 2.00)

× B1 – 2.00)

× B1 – 2.00)

× B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

13.20 — 10.50 — 5.60 — 4.25 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

43.50 — 35.50 — 20.70 — 16.75 — ns

43.50 — 35.50 — 20.70 — 16.75 — ns

19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B29f WE(0:3/BS_B[0:3]) negated to D(0:31)

High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1
(MIN = 0.375

B29g CS negated to D(0:31) High-Z G PCM write

access, TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 1
(MIN = 0.375

B29h WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1
(MIN = 0.375

B29i CS negated to D(0:31) (0:3) High-Z GPCM

write access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11 , EBDF = 1
(MIN = 0.375

B30 CS, WE(0:3)/BS_B[0:3] negated to

A(0:31), BADDR(28:30) invalid GPCM
write access 7 (MIN = 0.25 × B1 – 2.00)

B30a WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS negated
to A(0:31) invalid GPCM write access
TRLX = 0, CSNT =1 ACS = 10, or
ACS == 11, EBDF = 0
(MIN = 0.50

× B1 – 6.30)

× B1 – 6.30)

× B1 – 3.30)

× B1 – 3.30)

× B1 – 2.00)

5.00 — 3.00 — 0.00 — 0.00 — ns

5.00 — 3.00 — 0.00 — 0.00 — ns

38.40 — 31.10 — 17.50 — 13.85 — ns

38.40 — 31.10 — 17.50 — 13.85 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

B30b WE(0:3)/BS_B[0:3] negated to A(0:31)

Invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1, CSNT = 1.

negated to A(0:31) inv alid GPCM write

CS
access TRLX = 1, CSNT = 1, ACS = 10, or
ACS == 11 EBDF = 0
(MIN = 1.50

B30c WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS negated
to A(0:31) invalid GPCM write access,
TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1
(MIN = 0.375

B30d WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to
A(0:31) invalid GPCM write access TRL X
= 1, CSNT = 1, ACS = 10 or 11, EBDF = 1

20 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

× B1 – 2.00)

× B1 – 3.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

43.50 — 35.50 — 20.70 — 16.75 — ns

8.40 — 6.40 — 2.70 — 1.70 — ns

38.67 — 31.38 — 17.83 — 14.19 — ns

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B31 CLKOUT falling edge to CS valid, as

requested by control bit CST4 in the
corresponding word in the UPM
(MAX = 0.00

B31a CLKOUT falling edge to CS va lid , as

requested by control bit CST1 in the
corresponding word in the UPM
(MAX = 0.25

B31b CLKOUT rising edge to CS valid, as

requested by control bit CST2 in the
corresponding word in the UPM
(MAX = 0.00

B31c CLKOUT rising edge to CS valid, as

requested by control bit CST3 in the
corresponding word in the UPM
(MAX = 0.25

B31d CLKOUT falling edge to CS va lid , as

requested by control bit CST1 in the
corresponding word in the UPM EBDF = 1
(MAX = 0.375

B32 CLKOUT falling edge to BS valid, as

requested by control bit BST4 in the
corresponding word in the UPM
(MAX = 0.00

× B1 + 6.00)

× B1 + 6.80)

× B1 + 8.00)

× B1 + 6.30)

× B1 + 6.6)

× B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns

13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

B32a CLKOUT falling edge to BS valid, as

requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25

B32b CLKOUT rising edge to BS valid, as

requested by control bit BST2 in the
corresponding word in the UPM
(MAX = 0.00

B32c CLKOUT rising edge to BS valid, as

requested by control bit BST3 in the
corresponding word in the UPM
(MAX = 0.25

B32d CLKOUT falling edge to BS valid, as

requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375

B33 CLKOUT falling edge to GPL valid, as

requested by control bit GxT4 in the
corresponding word in the UPM
(MAX = 0.00

× B1 + 6.80)

× B1 + 8.00)

× B1 + 6.80)

× B1 + 6.60)

× B1 + 6.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B33a CLKOUT rising edge to GPL valid, as

requested by control bit GxT3 in the
corresponding word in the UPM
(MAX = 0.25

B34 A(0:31), BADDR(28:30), and D(0:31) to

CS

valid, as requested by control bi t CST4
in the corresponding word in the UPM
(MIN = 0.25

B34a A(0:31), BADDR(28:30), and D(0:31) to

CS

valid, as requested by control bi t CST1
in the corresponding word in the UPM
(MIN = 0.50

B34b A(0:31), BADDR(28:30), and D(0:31) to

CS

valid, as requested by CST2 in the
corresponding word in UPM
(MIN = 0.75

B35 A(0:31), BADDR(28:30) to CS valid, as

requested by control bit BST4 in the
corresponding word in the UPM
(MIN = 0.25

B35a A(0:31), BADDR(28:30), and D(0:31) to

BS

valid, as requested by BST1 in the
corresponding word in the UPM
(MIN = 0.50

× B1 + 6.80)

× B1 - 2.00)

× B1 – 2.00)

× B1 – 2.00)

× B1 – 2.00)

× B1 – 2.00)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

20.70 — 16.70 — 9.40 — 6.80 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

13.20 — 10.50 — 5.60 — 4.25 — ns

B35b A(0:31), BADDR(28:30), and D(0:31) to

BS

valid, as requested by control bi t BST2
in the corresponding word in the UPM
(MIN = 0.75

B36 A(0:31), BADDR(28:30), and D(0:31) to

GPL

valid, as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25

B37 UPWAIT valid to CLKOUT falling edge 8

(MIN = 0.00

B38 CLKOUT falling edge to UPWAIT valid

(MIN = 0.00 × B1 + 1.00)

B39 AS valid to CLKOUT rising edge 9

(MIN = 0.00

B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid

to CLKOUT rising edge
(MIN = 0.00 × B1 + 7.00)

B41 TS valid to CLKOUT rising edge (setup

time) (MIN = 0.00

× B1 – 2.00)

× B1 – 2.00)

× B1 + 6.00)

× B1 + 7.00)

× B1 + 7.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

20.70 — 16.70 — 9.40 — 7.40 — ns

5.60 — 4.30 — 1.80 — 1.13 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

8

1.00 — 1.00 — 1.00 — 1.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

22 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

Num Characteristic

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz 80 MHz

Unit

Min Max Min Max Min Max Min Max

B42 CLKOUT rising edge to TS valid (hold

time) (MIN = 0.00

× B1 + 2.00)

B43 AS negation to memory controller signals

2.00 — 2.00 — 2.00 — 2.00 — ns

—TBD—TBD—TBD—TBDns

negation (MAX = TBD)

1

For part speeds above 50 MHz, use 9.80 ns for B11a.

2

The timing required fo r BR in put is rel ev ant w hen the M P C875 /870 is s ele cted to work with the i nter nal bus arbiter.

The timing for BG

3

For part speeds above 50 MHz, use 2 ns for B17.

4

The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is ass erted.

5

For part speeds above 50 MHz, use 2 ns for B19.

6

The D(0:31) input timi ngs B20 an d B21 refer to the falling ed ge of th e C LK OUT. This timing is va li d on ly for r ead

input is relevant when the MPC875/870 is selected to work with the external bus arbiter.

accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory
controller , for data bea ts where DL T3 = 1 in the RAM words. (This is only the case whe re data is latche d on the falling
edge of CLKOUT.)

7

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

8

The signal UPW AIT is consid ered asy nchronous t o the C LKOUT and synchro nized intern ally. The timings specified in

B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.

9

The AS signal is c ons id ered a sy nc hro nou s to the CLKOUT. The timing B39 is sp ec ifi ed in o r der to allow the behavior

specified in Figure 22.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

C

C

Figure 4 provides the control timing diagram.

.

LKOUT

Outputs

Outputs

Inputs

Inputs

2.0 V

B

2.0 V

0.8 V

0.8 V

A

B

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

C

0.8 V

A

D

2.0 V

0.8 V

2.0 V

2.0 V

0.8 V

2.0 V

0.8 V
D

C

2.0 V

0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input setup time specification

D Minimum input hold time specification

Figure 4. Control Timing

Figure 5 provides the timing for the external clock.

LKOUT

B1

B1

B4

B5

Figure 5. External Clock Timing

B3

B2

MPC875/MPC870 Hardware Specifications, Rev. 3.0

24 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

C

C

Figure 6 provides the timing for the synchronous output signals.

LKOUT

B8

B7 B9

Output

Signals

B8a

Output

Signals

B8b

B7b

Output

Signals

B9B7a

Figure 6. Synchronous Output Signals Timing

Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals.

LKOUT

B13

B12B11

TS

, BB

B13a

B11

TA, B I

TEA

B14

B12a

B15

Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or

Bus Signal Timing

R

B

C

Figure 8 provides the timing for the synchronous input signals.

CLKOUT

B16

, BI

TA

B16a

TEA, KR,

ETRY, CR

B16b

B, BG, BR

B17

B17a

B17

Figure 8. Synchronous Input Signals Timing

Figure 9 provides normal case timing for in put dat a. It also appl ies t o normal r ead acc esses u nder the con trol o f the

user-programmable machine (UPM) in th e memory cont roller.

LKOUT

B16

B17

TA

B18

B19

D[0:31]

Figure 9. Input Data Timing in Normal Case

MPC875/MPC870 Hardware Specifications, Rev. 3.0

26 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconduct or