Freescale MPC860 User Manual

Freescale Semiconductor

Technical Data

MPC860 Family Hardware Specifications

MPC860EC

Rev. 7, 09/2004

This hardware specification contains detailed informatio n on
power considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC860 family.

1Overview

The MPC860 Power Quad I ntegrated Communi cations Contro ller
(PowerQUICC™) is a versatile one-chip integrated
microprocessor and per ipheral combinati on designed for a variety
of controller applications. It particularly excels in
communications and networking s ystems. The Po werQUICC unit
is referred t o as the MPC860 in this hardw are specification.

The MPC860 implements t he PowerPC architectur e and contains
a superset of Freescale’s MC68360 Quad Integrated
Communications Controller (QUICC
QUICC, RISC Communications Procces sor Module (CPM). The
CPM from the MC68360 QUICC has been enhanced by the
addition of the inter-integrated controller (I
memory controller has been enhanced, enabling the MPC860 to
support any type of memory, including high-performance
memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also
been integrated.

™

), referred to here as the

2

C) channel. The

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 6

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7. Thermal Calculation and Measurement . . . . . . . . . . . 9

8. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

10. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41

11. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43

12. UTOPIA AC Electrical Specifications . . . . . . . . . . . 67

13. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 68

14. Mechanical Dat a and Ordering Information . . . . . . . 71

15. Document Revision History . . . . . . . . . . . . . . . . . . . 77

Table 1 shows the functionality supported by the members of the

MPC860 family.

© Freescale Semiconductor, Inc., 2004. All rights reserved.

Features

Table 1. MPC860 Family Functionality

Cache (Kbytes) Ethernet

Part

MPC860DE 4 4 Up to 2 — — 2 1
MPC860DT 4 4 Up to 2 1 Yes 2 1
MPC860DP 16 8 Up to 2 1 Yes 2 1
MPC860EN 4 4 Up to 4 — — 4 1
MPC860SR 4 4 Up to 4 — Yes 4 1
MPC860T 4 4 Up to 4 1 Yes 4 1
MPC860P 16 8 Up to 4 1 Yes 4 1
MPC855T 4 4 1 1 Yes 1 2

1

Supporting documentation for these devices refers to the following:

1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev. 3)

2. MPC855T User’s Manual (MPC855TUM/D, Rev. 1)

Instruction

Cache

Data Cache 10T 10/100

ATM SCC Reference

1

2Features

The following list summarizes the key MPC860 features:

• Embedded single-issue, 32-bit PowerPCTM core (implementing the PowerPC architecture) with
thirty-two

— The core performs branch prediction with conditional prefetch without conditional execution.
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)

— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs
— MMUs support multipl e page size s of 4-, 16-, and 512-Kbyt es, and 8-Mbyt es; 16 virtual address spa ces

— Advanced on-chip-emulation debug mode

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• 32 address lines

• Operates at up to 80 MHz

• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller

32-bit general-purpose registers (GPRs)

– 16-Kbyte instruction cach es are four -way, set-associative with 256 sets ; 4-Kbyt e inst ructi on cache s

are two-way, set-associative with 128 sets.

– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way,

set-associative with 128 sets.

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

– Caches are physi cally addresse d, implement a leas t recently u sed (LRU) repl acement algori thm, and

are lockable on a cache block basis.

and 16 protection groups

MPC860 Family Hardware Specifications, Rev. 7

2 Freescale Semiconduct or

Features

— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
—Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte to 256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic

• General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture.

• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)

• Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request

• 10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using
ATM over UTOPIA interface)

• ATM support compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and software

implementation of other protocols.

— ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and

unspecified bit rate (UBR) and providing control mechanisms enabling software support of available
bit rate (ABR)

— Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and

byte-aligned serial (for example, T1/E1/ADSL)

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 3

Features

— UTOPIA-mode ATM supports level- 1 master with cell-level ha ndshake, multi-PHY (up to four p hysical

layer devices), conne ction to 25-, 5 1-, or 155-Mbps fr amers, and UT OPIA/system cloc k ratios of 1 /2 or
1/3.

— Serial-mode ATM connection sup ports transmiss ion convergenc e (TC) function for T1/E1/ADSL li nes,

cell delineation, cell payload scrambling/descrambling, automatic idle/unassigned cell
insertion/stripping, header error control (HEC) generation, checking, and statistics.

• Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specifi c commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability

• Four baud-rate generators (BRGs)
— Independent (can be tied to any SCC or SMC)
— Allows changes during operation
— Autobaud support option

• Four serial communi cations controllers (SCCs)
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation (available only on

specially programmed devices)
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
—AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))

• Two SMCs (serial management channels)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels

• One SPI (se rial periphe ral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus

•One I2C (inter-integrated circuit) port
— Supports master and slave modes

MPC860 Family Hardware Specifications, Rev. 7

4 Freescale Semiconduct or

Maximum Tolerated Ratings

— Multiple-master environment support

• Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to six serial channels (four SCCs and two SMCs)

• Parallel i nterface port (PIP)
— Centronics interfa ce supp ort
— Supports fast connection between compatible ports on the MPC860 or the MC68360

• PCMCIA interface
— Master (so cket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— Supports eight memory or I/O windows

• Low power support
— Full on—all units fully powered
— Doze—core functional un its disabled except ti me base decrementer , PLL, memory controll er, R TC, and

CPM in low-power standby
— Sleep—all units disabled except RTC and PIT, PLL active for fast wake up
— Deep sleep—all units disabled including PLL except RTC and PIT
— Power down mode—all units powered down except PLL, RTC, PIT, time base, and decrementer

• Debug interface
— Eight comparators: four operate on instruc tion address, two oper ate on data address, and two operate on

data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break -po int inte rnally.

• 3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK

• 357-pin ball grid array (BGA) package

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltag e and temperature ranges for the MPC860. Table 2 provides the
maximum ratings.

This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it
is advised that normal prec autions be taken to avoid applicat ion of any voltages higher than maxi mum-rated voltages
to this high-i mpeda nce ci rcuit. Reliabilit y of operation is enhanced if unused inputs are tied t o a n appropriate logic
voltage level (for example, either GND or V

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 5

dd

).

Thermal Characterist ics

(GND = 0 V)

Supply voltage

Input voltage

1

2

Table 2. Maximum Tolerated Ratings

Rating Symbol Value Unit

V

DDH

V

DDL

KAPWR –0.3 to 4.0 V

VDDSYN –0.3 to 4.0 V

V

in

–0.3 to 4.0 V
–0.3 to 4.0 V

GND – 0.3 to

VDDH

V

Temperature 3 (standard)

Temperature 3 (extended) T

Storage temperature range T

1

The power supply of the device must start its ramp from 0.0 V.

2

Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum

T

A(min)

T

j(max)

A(min)

T

j(max)

stg

0 °C

95 °C

–40 °C

95 °C

–55 to 150 °C

ratings are stress rat ings only ; functiona l operation at the maxim a is not gua ranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
Caution: All inputs that tole rate 5 V cannot be more than 2.5 V gre ater than the supply volt age. This restrictio n applies
to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be
applied to its inputs).

3

Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as

junction temperature, T

.

j

4 Thermal Characteristics

Table 3. Package Description

Package Designator Package Code (Case No.) Package Description

ZP 5050 (1103-01) PBGA 357 25*25*0.9P1.27

ZQ / VR 5058 (1103D-02) PBGA 357 25*25*1.2P1.27

Table 4 shows the thermal characteristics for the MPC860.

MPC860 Family Hardware Specifications, Rev. 7

6 Freescale Semiconduct or

Table 4. MPC860 Thermal Resistance Data

Power Dissipation

Rating Environment Symbol

ZP

MPC860P

ZQ / VR

MPC860P

Unit

Mold Compound Thickness 0.85 1.15 mm
Junction-to-ambient

1

Natural convection Single-layer board (1s) R

Four-layer board (2s2p) R

Airflow (200 ft/min) Single-layer board (1s) R

Four-layer board (2s2p) R
Junction-to-board
Junction-to-case
Junction-to-package top

1

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

4

5

6

Natural convection Ψ

θJA

θJMA

θJMA

θJMA

R

θJB

R

θJC

2

3

3

3

34 34 °C/W
22 22
27 27
18 18
14 13

6 8

JT

2 2

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.

2

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3

Per JEDEC JESD51-6 with the board horizontal.

4

Thermal resistan ce between the die and the prin ted circuit board per JEDEC JESD51- 8. Board temperature is measured

on the top surface of the board near the package.

5

Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Metho d 1012.1) with the cold plate tempe rature used for the case temperature. F or exposed pad
packages whe re the pad wo uld be expecte d to be soldered , junction-to-ca se thermal resis tance is a simulated val ue from
the junction to the exposed pad without contact resistance.

6

Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2.

5 Power Dissipation

Table 5 provides power dissipation in for m at ion . The mode s a re 1: 1, where CPU and bus speeds are equal, and 2:1,

where CPU frequency is twice the bus speed.

Table 5. P ow er Dissi pation (PD)

Die Revision Frequency (MHz) Typical

D.4
(1:1 mode)

D.4
(2:1 mode)

1

Typical power dissipation is measured at 3.3 V.

2

Maximum power dissipation is measured at 3.5 V.

Values in Table 5 represent V
power dissipation over V

DDH

due to buffer current, depending on external circuitry.

MPC860 Family Hardware Specifications, Rev. 7

1

Maximum

50 656 735 mW
66 TBD TBD mW
66 722 762 mW
80 851 909 mW

NOTE

-based power dissipatio n and do not include I/O

DDL

. I/O power dissipation varies widely by application

2

Unit

Freescale Semiconduc tor 7

DC Characteristics

6 DC Characteristics

Table 6 provides the DC electrical characteristics for the MPC860.

Table 6. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltage at 40 MHz or less V

DDH

, V

DDL

KAPWR

(power-down mode)

KAPWR

(all other operating mo des)

Operating voltage greater than 40 MHz V

DDH

, V

VDDSYN

KAPWR

(power-down mode)

KAPWR

(all other operating mo des)

Input high voltage (all inputs except EXTAL and
EXTCLK)

Input low voltage

1

EXTAL, EXTCLK input high voltage V
Input leakage current, Vin = 5.5 V (except TMS,

TRST, DSCK, and DSDI pins)
Input leakage current, Vin = 3.6 V (except TMS,

TRST, DSCK, and DSDI pins)
Input leakage current, Vin = 0 V (except TMS,

TRST, DSCK, and DSDI pins)
Input capacitance
Output high voltag e, IOH = –2.0 mA, V

2

= 3.0 V

DDH

(except XTAL, XFC, and open-drain pins)

, VDDSYN 3.0 3.6 V

2.0 3.6 V

V

– 0.4 V

, KAPWR,

DDL

DDH

3.135 3.465 V

DDH

2.0 3.6 V

V

– 0.4 V

DDH

V

IH

V

IL

IHC

I

in

I

In

I

In

C

in

V

OH

2.0 5.5 V

GND 0.8 V

0.7 × (V

DDH

) V

— 100 µA

— 10 µA

— 10 µA

— 20 pF

2.4 — V

DDH

+ 0.3 V

DDH

V

V

Output low voltage
IOL = 2.0 mA, CLKOUT
IOL = 3.2 mA
IOL = 5.3 mA

3
4

V

OL

— 0.5 V

IOL = 7.0 mA, TXD1/PA14, TXD2/PA12
IOL = 8.9 mA, TS, TA, TEA, BI, BB,
HRESET, SRESET

1

VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.

2

Input capacitance is periodically sampled.

MPC860 Family Hardware Specifications, Rev. 7

8 Freescale Semiconduct or

Thermal Calculation and Measurement

3

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/
VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0,
IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/
TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/
P A1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/
PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/
PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
L1ST2/

RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB1 6, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/
DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST 3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
TGATE1/CD1/PC10, CTS2/PC9, TGA TE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/
L1T SYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD 1 1, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3,
MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3]

4

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/
GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A,
CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)

TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,

7 Thermal Calculation and Measurement

For the foll owing discu ssions, PD = (VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

TJ = TA + (R

θJA

× PD)

where:

TA = ambient temperature (ºC)
R

= package j unction-to-a mbient ther mal resistance (ºC/W)

θJA

PD = power dissipation in package

The junction-to-a mbient thermal resis tance is an industry s tandard value whic h provides a quick and eas y estimation
of thermal perform ance. However , the answer is o nly an estimate; t est cases have demo nstrated that err ors of a factor
of two (in the quantity T

– TA) are possible.

J

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically , the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance:

R

= R

θJA

where:

R

= junction-to-ambient thermal resistance (ºC/W)

θJA

R

= junction-to-case thermal resistance (ºC/W)

θJC

R

= case-to-ambient thermal resistance (ºC/W)

θCA

R

is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the

θJC

case-to-am bient therm al resistance, R
heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the

θJC

+ R

θCA

. For instance, the user can change the air flow around the device, add a

θCA

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 9

Thermal Calculation and Measuremen t

printed circuit boar d surrounding the device. Thi s thermal model is most usefu l for ceramic packages wit h heat sinks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal mode l which has demonst rated re asonable ac curacy (abo ut 20%) is a two-resi stor model
consisting of a junc ti on-to- board and a ju nctio n-to- case t herma l res ista nce. The j unc tion- to-ca se the rmal re sist ance
covers the situ ation where a heat sink i s u sed or where a subst antia l am ount of heat is di ssipa ted from t he top of the
package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the pri nt ed c ir cui t boa rd. It has been observ ed t hat the thermal perf or mance of most plastic pa cka ges ,
especially PBGA packages, is strongly dependent on the board temperature; see

Figure 1.

Junction Temperature Rise Above

Ambient Divided by Package Power

Board T emperature Rise Above Ambient Divided by Package Power

Figure 1. Effect of Board Temperature Rise on Thermal Behavior

If the board temperature is known, an estimate of the junction temperature in the environment can be made using
the following equation:

TJ = TB + (R

θJB

× PD)

where:

R

= junction-to-board thermal resistance (ºC/W)

θJB

TB = board temperature (ºC)
PD = power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and by attaching the thermal balls to the ground plane.

MPC860 Family Hardware Specifications, Rev. 7

10 Freescale Semiconduct or

Layout Practices

7.4 Estimation Using Simulation

When the board temperatur e is not known, a therma l simulation of the appl ication is needed . The simple two-resistor
model can be used with the therma l simula tion of t he app licat ion [2] , or a more ac curate and co mple x model of the
package can be used in the thermal simulation.

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (Ψ
temperature at the top center of the package case using the following equation:

TJ = TT + (ΨJT × PD)

where:

Ψ

= thermal characterization parameter

JT

TT = thermocouple temperature on top of package
PD = power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the
thermocouple juncti on rests on the p ackage. A small a mount of ep oxy is placed o ver the thermocoupl e juncti on and
over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to
avoid measurement errors caused by cooling effects of the thermocouple wire.

) can be use d to determine the junction temperature with a measurement of the

JT

7.6 References

Semiconductor Equipment and Materials International [phone]
805 East Middlefield Rd.
Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Specifications 800-854-7179 or
(Available from Global Engineering Documents) 303-397-7956

JEDEC Specifications http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive

Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its

Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

8 Layout Practices

Each VDD pin on the MPC860 should be provided with a low-impe dance path to th e board’s supply. Each GND pin
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of
logic on the chip. The V
located as close as possible to the four sides of t he package. The capa citor leads and associated printed circ uit traces
connecting to chip V
employing two inner layers as V

power supply should be bypasse d to groun d using at least four 0.1 µF-bypass capacitors

DD

and GND should be kept to less than half an inch per capacitor lead. A four-layer board

DD

and GND planes is recommended.

CC

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 11

Bus Signal Timing

All output pins on the MPC860 have fa st rise and fall times. Printed c ircuit (PC) tr ace interc onnection le ngth should
be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6 inches are
recommended. Capaci tance calc ulations s hould conside r all devi ce loads as well as pa rasitic c apacitances due to the
PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the V

and GND circuits. Pull up all unused

CC

inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins.

9 Bus Signal Timing

Table 7 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.

The maximum bus speed supported by the MPC860 i s 6 6 MHz. Hi ghe r-speed parts must be operated in half -s pee d
bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus).

The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays.

Table 7. Bus Operation Timings

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

B1 CLKOUT period 30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns

B1a EXTCLK to CLKOUT phase skew

(EXTCLK > 15 MHz and MF <= 2)

B1b EXTCLK to CLKOUT phase skew

(EXTCLK > 10 MHz and MF < 10)

B1c CLKOUT phase jitter (EXTCLK >

15 MHz and MF <= 2)
B1d CLKOUT phase jitter
B1e CLKOUT frequency jitte r (M F < 1 0) 1— 0.50 — 0.50 — 0.50 — 0.50 %

B1f CLKOUT frequency jitter (10 < MF

B1g CLKOUT frequency jitter ( MF > 500) 1— 3.00 — 3.00 — 3.00 — 3.00 %

B1h Frequency jitter on EXTCLK

B2 CLKOUT pulse width low 12.12 — 10.00 — 8.00 — 6.06 — ns
B3 CLKOUT width high 12.12 — 10.00 — 8.00 — 6.06 — ns
B4 CLKOUT rise time

B533CLKOUT fall time

B7 CLKOUT to A(0:31), BADDR(28:30),

1

500)

<

WR, BURST, D(0:3 1), DP(0:3)

RD/

invalid

1

1

2

3

3

–0.90 0.90 –0.90 0.90 –0.90 0.90 –0.90 0.90 ns

–2.30 2.30 –2.30 2.30 –2.30 2.30 –2.30 2.30 ns

–0.60 0.60 –0.60 0.60 –0.60 0.60 –0.60 0.60 ns

–2.00 2.00 –2.00 2.00 –2.00 2.00 –2.00 2.00 ns

— 2.00 — 2.00 — 2.00 — 2.00 %

— 0.50 — 0.50 — 0.50 — 0.50 %

— 4.00 — 4.00 — 4.00 — 4.00 ns
— 4.00 — 4.00 — 4.00 — 4.00 ns

7.58 — 6.25 — 5.00 — 3.80 — ns

MPC860 Family Hardware Specifications, Rev. 7

12 Freescale Semiconduct or

Num Characteristic

Bus Signal Timing

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B7a CLKOUT to TSIZ(0:1), REG, RSV,

AT(0:3),

BDIP, PTR invalid

B7b CLKOUT to BR, BG, FRZ,

VFLS(0:1), VF(0:2) IWP(0:2),

LWP(0:1), STS invalid

4

B8 CLKOUT to A(0:31), BADDR(28:30)

WR, BURST, D(0:3 1), DP(0:3)

RD/

7.58 — 6.25 — 5.00 — 3.80 — ns

7.58 — 6.25 — 5.00 — 3.80 — ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns

valid
B8a CLKOUT to TSIZ(0:1), REG, RSV,

AT(0:3)

BDIP, PTR valid

B8b CLKOUT to BR, BG, VFLS(0:1),

VF(0:2), IWP(0:2), FRZ, LWP(0:1),

STS valid

4

B9 CLKOUT to A(0:31), BADDR(28:30),

WR, BURST, D(0:3 1), DP(0:3),

RD/

TSIZ(0:1),

REG, RSV, AT(0:3), PTR

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns

High-Z
B11 CLKOUT to TS, BB assertion 7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns

B11a CLKOUT to TA, BI assertion (when

2.50 9.25 2.50 9.25 2.50 9.25 2.50 9.75 ns
driven by the memory control ler or
PCMCIA interface)

B12 CLKOUT to TS, BB negation 7.58 14.33 6.25 13.00 5.00 11.75 3.80 8.54 ns

B12a CLKOUT to TA, BI negation (when

2.50 11.00 2.50 11.00 2.50 11.00 2.50 9.00 ns
driven by the memory control ler or
PCMCIA interface)

B13 CLKOUT to TS, BB High-Z 7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns

B13a CLKOUT to TA, BI High-Z (when

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
driven by the memory control ler or
PCMCIA interface)

B14 CLKOUT to TEA assertion 2.50 10.00 2.50 10.00 2.50 10.00 2.50 9.00 ns
B15 CLKOUT to TEA High-Z 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time) 9.75 — 9.75 — 9.75 — 6.00 — ns

B16a TEA, KR, RETRY, CR valid to

10.00 — 10.00 — 10.00 — 4.50 — ns

CLKOUT (setup time)

B16b BB, BG, BR, valid to CLKOUT (setup

time)

5

B17 CLKOUT to TA, TEA, BI, BB, BG, BR

8.50 — 8.50 — 8.50 — 4.00 — ns

1.00 — 1.00 — 1.00 — 2.00 — ns
valid (hold time)

B17a CLKOUT to KR, RETRY, CR valid

2.00 — 2.00 — 2.00 — 2.00 — ns
(hold time)

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 13

Bus Signal Timing

Num Characteristic

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B18 D(0:31), DP(0:3) valid to CLKOUT

rising edge (setup tim e)

B19 CLKOUT rising edge to D(0:31),

DP(0:3) valid (hold time)

B20 D(0:31), DP(0:3) valid to CLKOUT

falling edge (setup time)

B21 CLKOUT falling edge to D(0:31),

DP(0:3) valid (hold time)

6

6

7

7

B22 CLKOUT rising edge t o CS asserted

GPCM ACS = 00

B22a CLKOUT fall ing edge to CS assert ed

GPCM ACS = 10, TRLX = 0

B22b CLKOUT fall ing edge to CS assert ed

GPCM ACS = 11, TRLX = 0,
EBDF = 0

B22c CLKOUT falling edge to CS asserted

GPCM ACS = 11, TRLX = 0,

= 1

EBDF

B23 CLKOUT rising edge to CS negated

GPCM read access, GPCM write
access ACS = 00, TRLX = 0, and
CSNT = 0

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 2.00 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns

— 8.00 — 8.00 — 8.00 — 8.00 ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns

10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns

B24 A(0:31) and BADDR(28:30) to CS

5.58 — 4.25 — 3.00 — 1.79 — ns
asserted GPCM ACS = 10,
TRLX = 0

B24a A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 11, TRLX =

B25 CLKOUT rising edge to OE, WE(0:3)

13.15 — 10.50 — 8.00 — 5.58 — ns

0

— 9.00 — 9.00 — 9.00 — 9.00 ns

asserted

B26 CLKOUT rising edge to OE negated 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
B27 A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 10, TRLX =

B27a A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 11, TRLX =

B28 CLKOUT rising edge to WE(0:3)

35.88 — 29.25 — 23.00 — 16.94 — ns

1

43.45 — 35.50 — 28.00 — 20.73 — ns

1

— 9.00 — 9.00 — 9.00 — 9.00 ns
negated GPCM write access
CSNT = 0

B28a CLKOUT falling edge to WE(0:3)

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
negated GPCM write access
TRLX = 0, 1, CSNT = 1, EBDF = 0

MPC860 Family Hardware Specifications, Rev. 7

14 Freescale Semiconduct or

Num Characteristic

Bus Signal Timing

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B28b CLKOUT fal ling edge to CS neg ated

GPCM write access TRLX = 0, 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 0

B28c CLKOUT falling edge to WE(0:3)

negated GPCM write access
TRLX = 0, 1, CSNT = 1 write access

= 0, CSNT = 1, EBDF = 1

TRLX

B28d CLKOUT fal ling edge to CS neg ated

GPCM write access TRLX = 0, 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 1

B29 WE(0:3) negated to D(0:31), DP(0:3)

High-Z GPCM write access
CSNT = 0, EBDF = 0

B29a WE(0:3) negated to D(0:31), DP(0:3)

High-Z GPCM write access,

= 0, CSNT = 1, EBDF = 0

TRLX

B29b CS negated to D(0:31), DP(0:3),

High-Z GPCM write access,
ACS = 00, TRLX = 0, 1, an d CSNT =
0

B29c CS negated to D(0:31), DP(0:3)

High-Z GPCM write access,
TRLX = 0, CSNT = 1, AC S = 10, or

= 11, EBDF = 0

ACS

— 14.33 — 13.00 — 11.75 — 10.54 ns

10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns

— 17.99 — 16.00 — 14.13 — 12.31 ns

5.58 — 4.25 — 3.00 — 1.79 — ns

13.15 — 10.5 — 8.00 — 5.58 — ns

5.58 — 4.25 — 3.00 — 1.79 — ns

13.15 — 10.5 — 8.00 — 5.58 — ns

B29d WE(0:3) negated to D(0:31), DP(0:3)

High-Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 0

B29e CS negated to D(0:31), DP(0:3)

High-Z GPCM write access,
TRLX = 1, CSNT = 1, AC S = 10, or
ACS = 11, EBDF = 0

B29f WE(0:3) negated to D (0:31), DP(0:3)

High-Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 1

B29g CS negated to D(0:31), DP(0:3)

High-Z GPCM write access,

= 0, CSNT = 1, ACS = 10, or

TRLX
ACS = 11, EBDF = 1

B29h WE(0:3) negated to D(0:31), DP(0:3)

High-Z GPCM write access,

= 1, CSNT = 1, EBDF = 1

TRLX

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 15

43.45 — 35.5 — 28.00 — 20.73 — ns

43.45 — 35.5 — 28.00 — 29.73 — ns

8.86 — 6.88 — 5.00 — 3.18 — ns

8.86 — 6.88 — 5.00 — 3.18 — ns

38.67 — 31.38 — 24.50 — 17.83 — ns

Num Characteristic

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B29i CS negated to D(0:31), DP(0:3)

High-Z GPCM write access,

How to Reach Us:

Home Page:

www.freescale.com

email:

[e-mail]

USA/Europe or Locations Not List e d:

Freescale Semiconductor
Techn ical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
[phone]
480-768-2130
[e-mail]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH
Techn ical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
[e-mail]

Japan:
Freescale Semiconductor Japan Ltd.
Techn ical Information Center
3-20-1, Minami-Azabu, Minato-ku
Tokyo 106-0047 Japan
0120 191014
[phone]
[e-mail]

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.
Techn ical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
[phone]
[e-mail]

For Literature Requests Only:

Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
[phone]
303-675-2140
Fax: [phone]
LDCForFreescaleSemiconductor@
hibbertgroup.com

TRLX = 1, CSNT = 1, AC S = 10, or

= 11, EBDF = 1

ACS

38.67 — 31.38 — 24.50 — 17.83 — ns

Information in this document is provided solely to enable system and software implementers to
use Freescale Semiconductor products. There are no express or implied copyright licenses
granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the
information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any
products herein. Freescale Semiconductor makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Freescale
Semiconductor assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor
data sheets and/or specifications can and do vary in different applications and actual performance
may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. Freescale Semiconductor does not convey
any license under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Freescale
Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The
PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service
names are the property of their respective owners.

© Freescale Semiconductor, Inc. 2004.

MPC860EC
Rev. 7
09/2004

Num Characteristic

Bus Signal Timing

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B30 CS, WE(0:3) negated to A(0:31),

BADDR(28:30) invalid GPCM write

8

access

B30a WE(0:3) negated to A(0:31),

BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1,
CS negated to A(0:31) inv alid GPCM
write access, TRLX = 0, CSNT =1
ACS = 10, or ACS = 11, EBDF = 0

B30b WE(0:3) negated to A(0:31),

invalid GPCM BADDR(28:3 0) invalid
GPCM write access, TRLX = 1,
CSNT = 1.

CS negated to A(0:31),
Invalid GPCM, write access,
TRLX = 1, CSNT = 1, AC S = 10, or
ACS = 11, EBDF = 0

B30c WE(0:3) negated to A(0:31),

BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1.
CS negated to A(0:31) inv alid GPCM
write access, TRLX = 0, CSNT = 1,
ACS = 10, ACS = 11, EBDF = 1

B30d WE(0:3) negated to A(0:31),

BADDR(28:30) invalid GPCM write
access, TRLX = 1, CSNT =1.
CS negated to A(0:31) inv alid GPCM
write access TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1

5.58 — 4.25 — 3.00 — 1.79 — ns

13.15 — 10.50 — 8.00 — 5.58 — ns

43.45 — 35.50 — 28.00 — 20.73 — ns

8.36 — 6.38 — 4.50 — 2.68 — ns

38.67 — 31.38 — 24.50 — 17.83 — ns

B31 CLKOUT falling edge to CS

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
valid—as requested by control bit
CST4 in the corresponding word in
UPM

B31a CLKOUT falling edge to CS

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
valid—as requested by control bit
CST1 in the corresponding word in
UPM

B31b CLKOUT rising edg e to CS valid—as

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
requested by control b it CS T2 in th e
corresponding word in UPM

B31c CLKOUT rising edge to CS val id—as

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
requested by control b it CS T3 in th e
corresponding word in UPM

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 17

Bus Signal Timing

Num Characteristic

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B31d CLKOUT falling edge to CS

valid—as requested by control bit
CST1 in the corresponding word in
UPM, EBDF = 1

B32 CLKOUT falling edge to BS

valid—as requested by control bit
BST4 in the corresponding word in
UPM

B32a CLKOUT falling edge to BS

valid—as requested by control bit
BST1 in the corresponding word in
UPM, EBDF = 0

B32b CLKOUT risi ng edge to BS valid—as

requested by control bit BST2 in the
corresponding word in UPM

B32c CLKOUT rising edge to BS valid—as

requested by control bit BST3 in the
corresponding word in UPM

B32d CLKOUT falling edge to BS

valid—as requested by control bit
BST1 in the corresponding word in
UPM, EBDF = 1

B33 CLKOUT falling edge to GPL

valid—as requested by control bit
GxT4 in the corresponding word in
UPM

13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns

13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

B33a CLKOUT rising edge to GPL

valid—as requested by control bit
GxT3 in the corresponding word in
UPM

B34 A(0:31), BADDR(28:3 0), and D(0:31)

to

CS valid—as requested by con trol
bit CST4 in the corresponding word
in UPM

B34a A(0:31), BADDR(28:3 0), and D(0:31)

to

CS valid—as requested by con trol
bit CST1 in the corresponding word
in UPM

B34b A(0:31), BADDR(28:3 0), and D(0:31)

to

CS valid—as requested by con trol
bit CST2 in the corresponding word
in UPM

MPC860 Family Hardware Specifications, Rev. 7

18 Freescale Semiconduct or

7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns

5.58 — 4.25 — 3.00 — 1.79 — ns

13.15 — 10.50 — 8.00 — 5.58 — ns

20.73 — 16.75 — 13.00 — 9.36 — ns

Num Characteristic

Bus Signal Timing

Table 7. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B35 A(0:31), BADDR(28:30) to CS

valid—as requested by control bit
BST4 in the corresponding word in
UPM

B35a A(0:31), BADDR(28:3 0), and D(0:31)

BS valid—as reques ted by control

to
bit BST1 in the corresponding word
in UPM

B35b A(0:31), BADDR(28:3 0), and D(0:31)

BS valid—as reques ted by control

to
bit BST2 in the corresponding word
in UPM

B36 A(0:31), BADDR(28:30), and D(0: 31)

GPL valid—as requested by

to
control bit GxT4 in the corres ponding
word in UPM

B37 UPWAIT valid to CLKOUT falling

B38 CLKOUT falling edge to UPWAIT

B39 AS valid to CLKOUT rising edge

edge

valid

9

9

10

B40 A(0:31), TSIZ(0:1), RD/WR, BURST,

valid to CLKOUT rising edge

5.58 — 4.25 — 3.00 — 1.79 — ns

13.15 — 10.50 — 8.00 — 5.58 — ns

20.73 — 16.75 — 13.00 — 9.36 — ns

5.58 — 4.25 — 3.00 — 1.79 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

B41 TS valid to CLKOUT rising edge

7.00 — 7.00 — 7.00 — 7.00 — ns

(setup time)

B42 CLKOUT rising edge to TS valid

2.00 — 2.00 — 2.00 — 2.00 — ns

(hold time)

B43 AS negation to memory controller

— TBD — TBD — TBD — TBD ns

signals negation

1

Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.

2

If the rate of change of the fre quency of EXTAL is slow (that is, it does not jump b etween the minim um and maxi mum
values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time)
then the maximum allowed jitter on EXTAL can be up to 2%.

3

The timings specified in B4 and B5 are based on full strength clock.

4

The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for
BG output is relevant when the MPC860 is selected to work with internal bus arbiter.

5

The timing required fo r BR input is relevant when the MPC860 is selected to work with internal bus arbiter . The timing
for

BG input is relevant when the MPC860 is selected to work with external bus arbiter.

6

The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.

7

The D(0:31) and DP(0:3) in put timing s B20 and B21 refer to the fa lling edge of t he CLKOUT. This timing is valid only
for read accesses con trolled by chip-sel ects u nder control of the UPM in th e memory c ontroller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 19

Bus Signal Timing

8

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

9

The signal UPW AIT i s cons idered async hronou s to the CLKO UT an d sync hronized inte rnally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17.

10

The AS si gnal is consid ered asynch ronous to the C LKOUT. The timing B39 is spec ified in order t o allow the b ehavior
specified in Figure 20.

Figure 2 is the control timing diagram.

CLKOUT

Outputs

Outputs

Inputs

Inputs

2.0 V

B

2.0 V

0.8 V

0.8 V

A

B

2.0 V

0.8 V

2.0 V

0.8 V

C

2.0 V

0.8 V

0.8 V

A

D

2.0 V

0.8 V

2.0 V

2.0 V

0.8 V

2.0 V

0.8 V
D

C

2.0 V

0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input se tup tim e spe cif ic atio n

D Minimum input hold time specification

Figure 2. Control Timing

Figure 3 provides the timing for the external clock.

MPC860 Family Hardware Specifications, Rev. 7

20 Freescale Semiconduct or

C

LKOUT

C

Bus Signal Timing

B1

B1

B4

B5

Figure 3. External Clock Timing

Figure 4 provides the timing for the synchronous output signals.

LKOUT

B8

B7 B9

Output

Signals

B8a

Output

Signals

B8b

B3

B2

B9B7a

B7b

Output

Signals

Figure 4. Synchronous Output Signals Timing

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 21

Bus Signal Timing

Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13

B12B11

TS

, BB

B13a

B11a B12a

TA, BI

B14

B15

TEA

Figure 5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

Figure 6 provides the timing for the synchronous input signals.

CLKOUT

B16

B17

TA, BI

B16a

B17a

TEA, KR,

, CR

RETRY

B16b

B17

BB, BG, BR

Figure 6. Synchronous Input Signals Timing

Figure 7 provides normal case ti ming for in put dat a. It also appl ies t o normal r ead acc ess es under the con trol o f the

UPM in the memo ry controller.

MPC860 Family Hardware Specifications, Rev. 7

22 Freescale Semiconduct or

Bus Signal Timing

CLKOUT

B16

B17

TA

B18

B19

D[0:31],

DP[0:3]

Figure 7. Input Data Timing in Normal Case

Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM

RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

CLKOUT

TA

B20

B21

D[0:31],

DP[0:3]

Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller

and DLT3 = 1

Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors.

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconduc tor 23

Bus Signal Timing

CLKOUT

A[0:31]

B11 B12

TS

B8

CSx

OE

WE[0:3]

D[0:31],

DP[0:3]

B22

B25

B28

B23

B26

B19

B18

Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00)

MPC860 Family Hardware Specifications, Rev. 7

24 Freescale Semiconduct or