Freescale MPC866, MPC859 DATA SHEET

Freescale Semiconductor

Technical Data

MPC866/MPC859 Hardware Specifications

MPC866EC

Rev. 2, 2/2006

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC866/859 family (refer to Table 1 for a list of devices). The MPC866P is the superset device of the MPC866/859 family.This document describe s pertinent electrical and physical characteristics of the MPC8245. For functional characteristics of the processor, refer to the MPC866 PowerQUICC Family Users Manual (MPC866UM/D).

1Overview

The MPC866/859 is a derivative of Freesca le’s MPC860 PowerQUICC™ family of devices. It is a versatile single-chip integrated mic roprocessor and per ipher al combin ation th at can be used in a variety of controller applications and communications and networking systems. The MPC866/859/859DSL provides enhanced ATM func tionality over that of other ATM- enable d members of the MPC860 family.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 8

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. Thermal Calculation and Measurement . . . . . . . . . . 12

8. Power Supply and Power Sequencing . . . . . . . . . . . 15

9. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 46

12. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 48

13. UTOPIA AC Electrical Specifications . . . . . . . . . . . 72

14. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 74

15. Mechanical Data and Ordering Information . . . . . . . 78

16. Document Revision History . . . . . . . . . . . . . . . . . . . 93

Features

Table 1 shows the functionality supported by the members of the MPC866/859 family.

2Features

Table 1. MPC866 Family Functionality

Cache Ethernet

Par t

Instruction Data 10T 10/100

MPC866P 16 Kbytes 8 Kbytes Up to 4 1 4 2

MPC866T 4 Kbytes 4 Kbytes Up to 4 1 4 2

MPC859P 16 Kbytes 8 Kbytes 1112

MPC859T 4 Kbytes 4 Kbytes 1112

MPC859DSL 4 Kbytes 4 Kbytes 1 1 1

MPC852T

On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot

Assigner (TSA).

On the MPC859DSL, the SMC (SMC1) is for UART only.

For more details on the MPC852T, please refer to the

4 KBytes4 Kbytes2121

MPC852T Hardware Specifications.

SCC SMC

The following list summarize s the key MPC866/859 features:

• Embedded single-issue , 32- bit PowerPC™ core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)

— The core performs branch predi ct ion with conditional prefetch, without conditional execution — 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)

– 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way, set-associative with 256 sets;

4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-wa y, set- associative with 128 sets.

– 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte

data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets.

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks

– Caches are physic ally addresse d, implement a least rec ently used (LRU) replacement a lgorithm, and

are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces

and 16 protection groups.

— Advanced on-chip-emulation debug mode

• The MPC866/859 provides enhanced ATM functionality over that of the MPC860 SAR. The MPC866/859 adds major new features avail able in 'enhanced SAR' (ESAR) mode, including the following:

— Improved operation, administration, and maintenance (OAM) support — OAM performance monitoring (PM) support — Multiple APC priority leve ls available to support a range of traff ic pace requirements

MPC866/MPC859 Hardware Specifications, Rev. 2

2 Freescale Semiconductor

— ATM port-to-port switching capability without the need for RAM-based microcode — Simultaneous MII (10/100Ba se-T) and UTOPIA (half-duplex) capability — Optional statistical cell counters per PHY — UTOPIA level 2 compliant inte rface with added FIFO buffering to reduce the total cell transmission

time. (The earlier UTOPIA level 1 specification is also supported.) – Multi-PHY support on the MPC866, MPC859P, and MPC859T – Four PHY support on the MPC866/859

— Parameter RAM for both SPI and I

C can be relocated without RAM-based microcode — Supports full- duplex UTOPI A both master (ATM side) and slave ( PHY side) oper ation using a 'split ' bus — AAL2/VBR functionality is ROM-res ident.

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• Thirty-two address lines

• Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chi p select or RAS

to support a DRAM bank — Up to 30 wait states programmable per memory bank — Glueless interfa ce to page mode/EDO/S DRAM, SRAM, EPROMs, flash EPROMs, and other memory

devices. — DRAM controller programmable to support most size and speed memory interfaces — Four CAS

lines, four WE lines, and one OE line — Boot chip-select avai lable at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbytes–256 Mbytes) — Selectable write protection — On-chip bus arbitrat ion logic

• General-purpose timers — Four 16-bit timers casca dable to be two 32-bit timers — Gate mode can enab l e/d isa b le coun t ing — Interrupt can be masked on reference match and event capture

• Fast Ethernet controller (FEC) — Simultaneous MII (10/100Ba se-T) and UTOPIA operation when using the UTOPIA multip lexed bus

• System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer — Decrementer and time base from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG)

Features

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 3

Features

• Interrupts — Seven external interrupt request (IRQ) l ines — T welve port pins with interrupt capability — The MPC866P and MPC866T have 23 internal interrupt sour ces; the MPC859P, MPC859T, and

MPC859DSL have 20 internal interru pt sources. — Programmable priority between SCCs (MPC866P and MPC866T) — Programmable highest pri ority request

• Communications processor module (CPM) — RISC controller — Communication-spec ific commands (for example ,

RESTART TRANSMIT)

GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

— Supports continuous mode tr ansmission and reception on all serial channe ls — Up to 8-Kbytes of dual-port RAM — MPC866P and MPC866T have 16 serial DMA (SDMA) channels; MPC859P, MPC859T, and

MPC859DSL have 10 serial DMA (SDMA) channels.

— Three para lle l I/O regist ers with ope n -drai n capab i lity

• Four baud rate generators — Independent (can be connected to any SCC or SMC) — Allow changes during operation — Autobaud support option

• MPC866P and MPC866T have four SCCs (serial communication controller); MPC859P, MPC859T, and MPC859DSL have one SCC; and SCC1 on MPC859DSL supports Ethernet only.

— Serial ATM capability on all SCCs — Optional UTOPIA port on SCC4 — Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk — Universal asynchro nous receiver transmitter (UART) — Synchronous UART — Serial infrared (Ir DA) — Binary synchronous communication (BISYNC) — T otally transparent (bit str eams) — T otally transparent (fra me based with optional cyclic redundancy check (CRC)

• Two SMCs (serial management channels) (MPC859DSL has one SMC (SMC1) for UART.) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division multiplexed (TDM) channels

MPC866/MPC859 Hardware Specifications, Rev. 2

4 Freescale Semiconductor

Features

• One serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-m aster operation on the same bus

• One inter-i ntegrated circuit (I

C) port — Supports master and slave modes — Multiple-master en vironment support

• Time slot assigner (TSA) (MPC859DSL does not have TSA.) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user -defined — 1- or 8-bit resolution — Allows independent transm it and receive routing, frame synchronization, and clocking — Allows dynamic changes — On MPC866P and MPC866T , can be internally connected to six serial channels (four SCCs and two

SMCs); on MPC859P and MPC859T, can be connected to three serial channe ls (one SCC and two SMCs).

• Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on MPC866/859 or MC68360

• PCMCIA interface — Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1) — Supports one or two PCMCIA sockets whether ESAR functio nality is enabled — Eight memory or I/O windows supported

• Debug interface — Eight comparators : four operate on instr uction add ress, two operate on data address, and two ope rate on

data. — Supports conditions: = ≠ < > — Each watchpoint can generate a breakpoint internally

• Normal high and normal low power modes to conserve power

• 1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to Table 6 for a listing of the 5-V tolerant pins.

• 357-pin plastic ball grid array (PBGA) package

• Operation up to 133 MHz

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 5

Features

The MPC866/859 is comprised of three modules that each use a 32-bit internal bus: MPC8xx core, system integration unit (SIU), and communication processor module (CPM). The MPC866P block diagram is shown in

Figure 1. The MPC859P/859T/859DSL block diagram is shown in Figure 2.

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

FIFOs

10/100

Base-T

Media Access

Control

MII

Instruction

Bus

Load/Store

Bus

Parallel I/O

4 Baud Rate

Generators

Parallel Interface Port

and UTOPIA

16-Kbyte

Instruction Cache

Instruction MMU

32-Entry ITLB

8-Kbyte

Data Cache

Data MMU

32-Entry DTLB

SCC1

Unified

Bus

Interrupt

Timers

Controllers

32-Bit RISC Controller

and Program

ROM

SCC3 SCC4

Time Slot Assigner

System Interface Unit (SIU)

Bus Interface

8-Kbyte

Dual-Port RAM

Memory Controller

Internal

Unit

System Functions

PCMCIA/ATA Interface

External

Bus Interface

Unit

16 Virtual

Serial

and

Independent

DMA

Channels

I2CSPISMC2SMC1SCC2

Serial Interface

Figure 1. MPC866P Block Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

6 Freescale Semiconductor

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

FIFOs

10/100

Base-T

Media Access

Control

MII

Instruction

Bus

Load/Store

Bus

Parallel I/O

4 Baud Rate

Generators

Parallel Interface Port

and UTOPIA

†

4-Kbyte

Instruction Cache

Instruction MMU

32-Entry ITLB

†

4-Kbyte

Data Cache

Data MMU

32-Entry DTLB

Timers

Controllers

32-Bit RISC Controller

Timers

Unified

Bus

Interrupt

and Program

ROM

System Interface Unit (SIU)

Bus Interface

8-Kbyte

Dual-Port RAM

Memory Controller

Internal

External

Bus Interface

Unit

System Functions

PCMCIA/ATA Interface

10 Virtual

Serial

and

Independent

DMA

Channels

Features

SCC1

Time Slot Assigner

Time Slot Assigner*

I2CSPISMC2*SMC1

Serial Interface

†

The MPC859P has a 16-Kbyte instruction cache and a 8-Kbyte data cache.

* The MPC859DSL does not contain SMC2 nor the time slot assigner, and provides eight SDMA

controllers.

Figure 2. MPC859P/859T/MPC859DSL Block Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 7

Maximum Tolerated Ratings

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC866/859. Table 2 shows the maximum tolerated ratings, and Table 3 shows the operating temperatures.

Table 2. Maximum Tolerated Ratings

Rating Symbol Value Unit

Supply voltage

Input voltage

Storage temperature range T

The power supply of the device must start its ramp from 0.0 V.

Functional operating conditions are provided with the DC electrical specifications in Tab l e 6 . Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. See page 15. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power-up and normal operation (that is, if the MPC866/859 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).

VDDH – 0.3 to 4.0 V

VDDL – 0.3 to 2.0 V

VDDSYN – 0.3 to 2.0 V

Difference between VDDL to VDDSYN 100 mV

stg

GND – 0.3 to VDDH V

–55 to +150 °C

Table 3. Operating Temperatures

Rating Symbol Value Unit

Temperature

Temperature (extended) T

Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as

junction temperature, T

(standard)

A(min)

j(max)

A(min)

j(max)

0°C

95 °C

–40 °C

100 °C

This device contains circ uitry protecting against damage due to high- sta tic voltage or electrical fiel ds; however, it is advised that nor mal precautions be taken to avoid a pplication of any voltages highe r than maximum-rated voltag es to this high -impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for exampl e, either GND or VDD).

MPC866/MPC859 Hardware Specifications, Rev. 2

8 Freescale Semiconductor

Thermal Characteristics

4 Thermal Characteristics

Table 4 shows the thermal characteristics for the MPC866/859.

Table 4. MPC866/859 Thermal Resistance Data

Rating Environment Symbol Value Unit

Junction-to-ambient

Natural Convection Single-layer board (1s) R

Four-layer board (2s2p) R

Airflow (200 ft/min) Single-layer board (1s) R

Four-layer board (2s2p) R

Junction-to-board

Junction-to-case

Junction-to-package top

Natural Convection Ψ

Airflow (200 ft/min) Ψ

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance.

Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC JESD51-2.

θJA

θJMA

θJB

θJC

37 °C/W

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 9

Power Dissipation

5 Power Dissipation

Table 5 shows power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1

mode, where CPU frequency is twice the bus speed.

Table 5. Power Dissipation (PD)

Die Revision Bus Mode

0 1:1 50 MHz 110 140 mW

2:1 66 MHz 140 160 mW

Typical power dissipation at VDDL and VDDSYN is at 1.8 V. and VDDH is at 3.3 V.

Maximum power dissipation at VDDL and VDDSYN is at 1.9 V, and VDDH is at 3.465 V.

Values in Table 5 represent VDDL based powe r di ssipati on a nd do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. The VDDSYN power dissipation is negligi ble.

6 DC Characteristics

CPU

Frequency

66 MHz 150 180 mW

80 MHz 170 200 mW

100 MHz 210 250 mW

133 MHz 260 320 mW

Typical

Maximum

NOTE

Unit

Table 6 shows the DC electrical characteristics for the MPC866/859.

Table 6. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltage VDDL (core) 1.7 1.9 V

VDDH (I/O) 3.135 3.465 V

1.7 1.9 V

— 100 mV

Input high voltage (all inputs except EXTAL and EXTCLK)

MPC866/MPC859 Hardware Specifications, Rev. 2

VDDSYN

Difference between VDDL to VDDSYN

VIH 2.0 3.465 V

10 Freescale Semiconductor

DC Characteristics

Table 6. DC Electrical Specifications (continued)

Characteristic Symbol Min Max Unit

Input low voltage VIL GND 0.8 V

EXTAL, EXTCLK input high voltage VIHC 0.7*(VDDH) VDDH V

Input leakage current, Vin = 5.5V (except TMS, TRST DSCK and DSDI pins) for 5 Volts Tolerant Pins

Input leakage current, Vin = VDDH (except TMS, TRST

— 100 µA

—10µA

DSCK, and DSDI)

Input leakage current, Vin = 0 V (except TMS, TRST

—10µA

DSCK and DSDI pins)

Input capacitance

Output high voltage, IOH = – 2.0 mA,

—20pF

VOH 2.4 — V

except XTAL, and Open drain pins

Output low voltage

• IOL = 2.0 mA (CLKOUT)

• IOL = 3.2 mA

• IOL = 5.3 mA

VOL — 0. 5 V

• IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)

• IOL = 8.9 mA (TS

The difference between VDDL and VDDSYN can not be more than 100 m V.

The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, MII_MDIO are 5 V

, TA, TEA, BI, BB, HRESET, SRESET)

tolerant.

Input capacitance is periodically sampled.

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2,

IP_B(0:1)/IWP(0:1)/VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1 TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2 BRGCLK2/L1RCLKB/TOUT3 REJCT1

/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27,

/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0,

/CLK4/PA4, TIN3/BRGO3/CLK5/PA3,

BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1 SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1 L1ST3/L1RQB L1ST2/RTS2 CTS2

/PC9, TGATE2/CD2/PC8, CTS3/SDACK2/L1TSYNCB/PC7, CD3/L1RSYNCB/PC6,

CTS4

/SDACK1/L1TSYNCA/PC5, CD4/L1RSYNCA/PC4, PD15/L1TSYNCA, PD14/L1RSYNCA, PD13/L1TSYNCB,

/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/DREQ0/PC15,

/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10,

PD12/L1RSYNCB, PD11/RXD3, PD10/TXD3, PD9/RXD4, PD8/TXD4, PD5/REJECT2, PD6/RTS4

/CLK2/PA6,

/SDACK1/PB23, SMSYN2/SDACK2/PB22,

/PB19, L1ST2/RTS2/PB18,

, PD7/RTS3,

PD4/REJECT3, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3].

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,

WE1

/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,

GPL_A

(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,

ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS

, OP3/MODCK2/DSDO, BADDR(28:30).

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 11

Thermal Calculation and Measurement

7 Thermal Calculation and Measurement

For the fol lowing disc uss ions, PD = (VDDL x IDDL) + P I/O, where PI/ O is the po wer di ssipati on of the I /O driv ers. The VDDSYN power dissipation is negligi ble.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction te mperature, TJ, in °C can be obtained from the equation:

= TA +(R

θJA

x PD)

where:

= ambient tem perat u re (ºC)

= package junction-to-a mbient thermal resistance (ºC/W)

θJA

= power dissipation in package

The junction-to- ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity T

) are possible.

J-TA

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resi stance has f requently bee n expressed as the sum of a junction-to -case the rmal resist ance and a case-to-ambient thermal resistance:

= R

θJA

where:

θJA

θJC

θCA

is device related and cannot be influenced by the user. The user adjusts the thermal environment to affec t the

θJC

case-to-am bient thermal resi s tan ce, R heat sink, change the mounting arra ngement on the printed-circuit board, or change the thermal dissipation on the printed-circ uit board surrounding the devic e. This thermal model is most useful fo r ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required.

+ R

θJC

θCA

= junctio n - t o-am b ient th ermal res i s tanc e ( º C/W )

= junction-to-case thermal resistance (ºC/W)

= case-to-am bient ther mal resistance (ºC/W)

. For instance, the user can change the airflow around the device, add a

θCA

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-res istor model consisting of a junction-t o-board and a junction-to -case thermal r esistance. Th e junction-to- case covers t he situ ation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circ uit board. It has been observed that the thermal perfor mance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see Figure 3.

MPC866/MPC859 Hardware Specifications, Rev. 2

12 Freescale Semiconductor

Thermal Calculation and Measurement

Figure 3. Effect of Board Temperature Rise on Thermal Behavior

If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equatio n:

= TB +(R

θJB

x PD)

where:

= junction-to-board the rmal resistance (ºC/W)

θJB

= board temper atu re ºC

= power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to deter mine the junction-to-board thermal res istance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane.

7.4 Estimation Using Simulation

When the boar d temperature is not known, a the rmal sim ulation of t he applic ation is needed. T he simple t wo-resistor model can be use d with the thermal sim ulation of the application [2], or a more accurate and c omplex model of the package can be used in the thermal simulation.

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 13

Thermal Calculation and Measurement

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal characteriz at ion parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation:

= TT +(ΨJT x PD)

where:

= thermal characteriz ation parameter

= thermocouple temperature on top of package

= power dissipation in package

The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a 40 gauge type T thermocouple epoxie d to the top center of the package case. The thermocouple should be positi oned so that the thermocouple junc tion rests on the package. A small amount of epoxy is placed over the thermocoup le junction and over about 1 mm of wir e ext ending fr om the j unction. The thermoc ouple wire is pl aced flat again st the package case to avoid measurement errors caused by cooling effects of the ther mocouple wire.

7.6 References

Semiconductor Equipment and Materials International(415 ) 964-5111 805 East Middlefield Rd. Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or (Available from Global Engine ering Documents)303-397-7956

JED E C Spec ifica t io ns h t t p://www.jedec.o r g

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Model ing,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

MPC866/MPC859 Hardware Specifications, Rev. 2

14 Freescale Semiconductor

Power Supply and Power Sequencing

8 Power Supply and Power Sequencing

This section provide s design considerations for the MPC866/ 859 power supply . The MPC866/859 has a core voltage (VDDL) and PLL voltage (VDDSYN) that ope rates a t a lower voltage tha n th e I/O volta ge VDDH. The I /O sect ion of the MPC866/859 is supplied with 3.3 V across VDDH and V

Signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TC K, TRST_B, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V tolerant pins cann ot exceed 5.5 V and the remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down and normal operation.

One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different r ates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which diffe rent voltages are derived. The following restrictions apply:

• VDDL must not exceed VDDH during power up and power down.

• VDDL must not exceed 1.9 V and VDDH must not exceed 3.465 V.

These cautio ns are necessary for the long term reliability of the part. If they are viol ated, the electrostatic discharge (ESD) protection diodes are forward-biased and excessive current can flow through these diodes. If the system power supply design does not contr ol the voltage sequencing, the circuit shown in Figure 4 can be added to meet these requirement s. The MUR420 Schottky diodes control the maximum potential differen ce between the external bus and core power supplies on powerup and the 1N5820 diodes regulate the maximum potential difference on powerdown.

(GND).

VDDH VDDL

MUR420

1N5820

Figure 4. Example Voltage Sequencing Circuit

9 Layout Practices

Each VDD pin on the MPC866/859 should be provided with a low-impedan ce path to the board’s supply. Furthermore, ea ch GND pi n shou ld be provide d wit h a l ow-impeda nce pat h to gr ound. The p ower supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed-circuit traces connecting to chip V At a minimum, a four-layer board employing two inner layers as V

All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.

and GND should be kept to less than 1/2” per capacito r lead.

and GND planes should be used.

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 15

Bus Signal Timing

This recommendation partic ularly applies to the address and data buses. Maximum PC trace le ngths of 6” are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially crit ic al in systems with higher capacitive loads because these loads create higher transient currents in the V

and GND circuits . Pull up all unused

inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1), in the MPC866 User’s Manual.

10 Bus Signal Timing

The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated in half-speed bus mode (for example , an MPC866/859 use d at 100 MHz must be configured for a 50-MHz bus).

Table 7 and Table 8 show the frequency ranges for standard part frequencies.

Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part Freq 50 MHz 66 MHz

Min Max Min Max

Core 40 50 40 66.67

Bus 40 50 40 66.67

Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Par t

Freq

Core 40 50 40 66.67 40 100 40 133.34

Bus 20 25 20 33.33 20 50 20 66.67

50 MHz 66 MHz 100 MHz 133 MHz

Min Max Min Max Min Max Min Max

Table 9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz bus operation. The timing for the

MPC866/859 bus shown in this table assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay.

Table 9. Bus Operation Timings

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

B1 Bus Period (CLKOUT) See Ta b le 7 ————————ns

B1a EXTCLK to CLKOUT phase skew – 2 +2 – 2 +2 – 2 +2 – 2 +2 ns

Unit

B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns

B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 %

MPC866/MPC859 Hardware Specifications, Rev. 2

16 Freescale Semiconductor

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B1d CLKOUT phase jitter peak-to-peak

—4—4—4—4ns

for OSCLK ≥ 15 MHz

CLKOUT phase jitter peak-to-peak

—5—5—5—5ns

for OSCLK < 15 MHz

B2 CLKOUT pulse width low (MIN = 0.4 x

12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns

B1, MAX = 0.6 x B1)

B3 CLKOUT pulse width high (MIN = 0.4 x

12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns

B1, MAX = 0.6 x B1)

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns

B5 CLKOUT fall time

B7 CLKOUT to A(0:31), BADDR(28:30),

RD/WR

, BURST, D(0:31), DP(0:3)

— 4.00 — 4.00 — 4.00 — 4.00 ns

7.60 — 6.30 — 5.00 — 3.80 — ns

output hold (MIN = 0.25 x B1)

B7a CLKOUT to TSIZ(0:1), REG

AT ( 0: 3 ), B DI P

, PTR output hold (MIN =

, RSV,

7.60 — 6.30 — 5.00 — 3.80 — ns

0.25 x B1)

B7b CLKOUT to BR

, BG, FRZ, VFLS(0:1),

VF(0:2), IWP(0:2), LWP(0:1), STS

7.60 — 6.30 — 5.00 — 3.80 — ns

output hold (MIN = 0.25 x B1)

B8 CLKOUT to A(0:31), BADDR(28:30)

RD/WR

, BURST, D(0:31), DP(0:3),

— 13.80 — 12.50 — 11.30 — 10.00 ns

valid (MAX = 0.25 x B1 + 6.3)

B8a CLKOUT to TSIZ(0:1), REG

AT(0:3), BDIP

, PTR valid (MAX = 0.25

, RSV,

— 13.80 — 12.50 — 11.30 — 10.00 ns

x B1 + 6.3)

B8b CLKOUT to BR

, BG, VFLS(0:1),

— 13.80 — 12.50 — 11.30 — 10.00 ns VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS

valid 4 (MAX = 0.25 x B1 + 6.3)

B9 CLKOUT to A(0:31), BADDR(28:30),

RD/WR TSIZ(0:1), REG

, BURST, D(0:31), DP(0:3),

, RSV, AT(0:3), PTR

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

High-Z (MAX = 0.25 x B1 + 6.3)

B11 CLKOUT to TS

, BB assertion (MAX =

7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns

0.25 x B1 + 6.0)

B11a CLKOUT to TA

, BI assertion (when

2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 +

9.30

)

B12 CLKOUT to TS

, BB negation (MAX =

7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns

0.25 x B1 + 4.8)

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 17

Bus Signal Timing

Num Characteristic

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B12a CLKOUT to TA, BI negation (when

driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 +

9.00)

B13 CLKOUT to TS

, BB High-Z (MIN = 0.25

x B1)

B13a CLKOUT to TA

, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 x B1 + 2.5)

B14 CLKOUT to TEA

assertion (MAX =

0.00 x B1 + 9.00)

B15 CLKOUT to TEA

High-Z (MIN = 0.00 x

B1 + 2.50)

B16 TA

, BI valid to CLKOUT (setup time)

(MIN = 0.00 x B1 + 6.00)

B16a TEA

, KR, RETRY, CR valid to CLKOUT

(setup time) (MIN = 0.00 x B1 + 4.5)

B16b BB

B17 CLKOUT to TA

, BG, BR, valid to CLKOUT (setup

time)

(4 MIN = 0.00 x B1 + 0.00 )

, TEA, BI, BB, BG, BR

valid (hold time) (MIN = 0.00 x B1 +

1.00

)

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

6.00 — 6.00 — 6.00 — 6.00 — ns

4.50 — 4.50 — 4.50 — 4.50 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

1.00 — 1.00 — 1.00 — 2.00 — ns

B17a CLKOUT to KR

, RETRY, CR valid (hold

time) (MIN = 0.00 x B1 + 2.00)

B18 D(0:31), DP(0:3) valid to CLKOUT

rising edge (setup time)

(MIN = 0.00

x B1 + 6.00)

B19 CLKOUT rising edge to D(0:31),

DP(0:3) valid (hold time) x B1 + 1.00

)

B20 D(0:31), DP(0:3) valid to CLKOUT

falling edge (setup time)

(MIN = 0.00

x B1 + 4.00)

B21 CLKOUT falling edge to D(0:31),

DP(0:3) valid (hold Time)

(MIN = 0.00

x B1 + 2.00)

B22 CLKOUT rising edge to CS

asserted

GPCM ACS = 00 (MAX = 0.25 x B1 +

6.3)

B22a CLKOUT falling edge to CS

asserted

GPCM ACS = 10, TRLX = 0 (MAX =

0.00 x B1 + 8.00)

MPC866/MPC859 Hardware Specifications, Rev. 2

2.00 — 2.00 — 2.00 — 2.00 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 2.00 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

— 8.00 — 8.00 — 8.00 — 8.00 ns

18 Freescale Semiconductor

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B22b CLKOUT falling edge to CS asserted

GPCM ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x B1 + 6.3)

B22c CLKOUT falling edge to CS

GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 x B1 + 6.6)

B23 CLKOUT rising edge to CS

GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 + 8.00)

B24 A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1 - 2.00)

B24a A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 11, TRLX = 0 (MIN = 0.50 x B1 - 2.00)

B25 CLKOUT rising edge to OE

asserted (MAX = 0.00 x B1 + 9.00)

B26 CLKOUT rising edge to OE

(MAX = 0.00 x B1 + 9.00)

B27 A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1 - 2.00)

asserted

negated

, WE(0:3)

negated

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

— 9.00 — 9.00 — 9.00 — 9.00 ns

2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns

35.90 — 29.30 — 23.00 — 16.90 — ns

B27a A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 - 2.00)

B28 CLKOUT rising edge to WE

negated GPCM write access CSNT = 0 (MAX = 0.00 x B1 + 9.00)

B28a CLKOUT falling edge to WE

negated GPCM write access TRLX = 0,1, CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80)

B28b CLKOUT falling edge to CS

GPCM write access TRLX = 0,1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 + 6.80)

B28c CLKOUT falling edge to WE

negated GPCM write access TRLX = 0, CSNT = 1 write access TRLX = 0,1, CSNT = 1, EBDF = 1 (MAX = 0.375 x B1 + 6.6)

(0:3)

negated

(0:3)

MPC866/MPC859 Hardware Specifications, Rev. 2

43.50 — 35.50 — 28.00 — 20.70 — ns

— 9.00 — 9.00 — 9.00 — 9.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

— 14.30 — 13.00 — 11.80 — 10.50 ns

10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns

Freescale Semiconductor 19

Bus Signal Timing

Num Characteristic

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B28d CLKOUT falling edge to CS negated

GPCM write access TRLX = 0,1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 + 6.6)

B29 WE

B29a WE

B29b CS

B29c CS

B29d WE

(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25 x B1 - 2.00)

(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 – 2.00)

negated to D(0:31), DP(0:3), High Z GPCM write access, ACS = 00, TRLX = 0,1 & CSNT = 0 (MIN = 0.25 x B1– 2.00)

negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 0.50 x B1 – 2.00)

(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 – 2.00)

— 18.00 — 18.00 — 14.30 — 12.30 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

43.50 — 35.50 — 28.00 — 20.70 — ns

B29e CS

B29f WE

B29g CS

B29h WE

B29i CS

negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 1.50 x B1 – 2.00)

(0:3) negated to D(0:31), DP(0:3) High Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 – 6.30)

negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 – 6.30)

(0:3) negated to D(0:31), DP(0:3) High Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 – 3.30)

negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 – 3.30)

43.50 — 35.50 — 28.00 — 20.70 — ns

5.00 — 3.00 — 1.10 — 0.00 — ns

38.40 — 31.10 — 24.20 — 17.50 — ns

MPC866/MPC859 Hardware Specifications, Rev. 2

20 Freescale Semiconductor

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B30 CS, WE(0:3) negated to A(0:31),

BADDR(28:30) invalid GPCM write access

B30a WE

(MIN = 0.25 x B1 – 2.00)

(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50 x B1 – 2.00)

B30b WE

(0:3) negated to A(0:31) invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN =

1.50 x B1 – 2.00)

B30c WE

(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 – 3.00)

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

43.50 — 35.50 — 28.00 — 20.70 — ns

8.40 — 6.40 — 4.50 — 2.70 — ns

B30d WE

(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1

B31 CLKOUT falling edge to CS

requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00 X B1 + 6.00)

B31a CLKOUT falling edge to CS

requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80)

B31b CLKOUT rising edge to CS

requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00)

B31c CLKOUT rising edge to CS

requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.30)

valid, as

valid , as

38.67 — 31.38 — 24.50 — 17.83 — ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 21

Bus Signal Timing

Num Characteristic

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B31d CLKOUT falling edge to CS valid, as

requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6)

B32 CLKOUT falling edge to BS

requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00)

B32a CLKOUT falling edge to BS

requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 x B1 + 6.80)

B32b CLKOUT rising edge to BS

requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00)

B32c CLKOUT rising edge to BS

requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80)

B32d CLKOUT falling edge to BS

requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 x B1 + 6.60)

valid, as

valid- as

13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns

B33 CLKOUT falling edge to GPL

requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00)

B33a CLKOUT rising edge to GPL

requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80)

B34 A(0:31), BADDR(28:30), and D(0:31)

to CS

valid, as requested by control bit CST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00)

B34a A(0:31), BADDR(28:30), and D(0:31)

to CS

valid, as requested by control bit CST1 in the corresponding word in the UPM (MIN = 0.50 x B1 – 2.00)

B34b A(0:31), BADDR(28:30), and D(0:31)

to CS

valid, as requested by CST2 in the corresponding word in UPM (MIN =

0.75 x B1 – 2.00)

valid, as

MPC866/MPC859 Hardware Specifications, Rev. 2

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

20.70 — 16.70 — 13.00 — 9.40 — ns

22 Freescale Semiconductor

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B35 A(0:31), BADDR(28:30) to CS valid, as

requested by control bit BST4 in the corresponding word in the UPM (MIN =

0.25 x B1 – 2.00)

B35a A(0:31), BADDR(28:30), and D(0:31)

to BS

valid, as Requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 – 2.00)

B35b A(0:31), BADDR(28:30), and D(0:31)

to BS

valid, as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 – 2.00)

B36 A(0:31), BADDR(28:30), and D(0:31)

to GPL

valid as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 – 2.00)

B37 UPWAIT valid to CLKOUT falling

B38 CLKOUT falling edge to UPWAIT

B39 AS

edge

(MIN = 0.00 x B1 + 6.00)

(MIN = 0.00 x B1 + 1.00)

valid

valid to CLKOUT rising edge 9 (MIN

= 0.00 x B1 + 7.00)

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

20.70 — 16.70 — 13.00 — 9.40 — ns

5.60 — 4.30 — 3.00 — 1.80 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

7.00 — 7.00 — 7.00 — 7.00 — ns

B40 A(0:31), TSIZ(0:1), RD/WR

, BURST,

7.00 — 7.00 — 7.00 — 7.00 — ns

valid to CLKOUT rising edge (MIN =

0.00 x B1 + 7.00)

B41 TS

valid to CLKOUT rising edge (setup

7.00 — 7.00 — 7.00 — 7.00 — ns

time) (MIN = 0.00 x B1 + 7.00)

B42 CLKOUT rising edge to TS

valid (hold

2.00 — 2.00 — 2.00 — 2.00 — ns

time) (MIN = 0.00 x B1 + 2.00)

B43 AS

negation to memory controller

— TBD — TBD — TBD — TBD ns

signals negation (MAX = TBD)

For part speeds above 50 MHz, use 9.80 ns for B11a.

The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter.

The timing for BG

For part speeds above 50 MHz, use 2 ns for B17.

The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal

input is relevant when the MPC866/859 is selected to work with the external bus arbiter.

is asserted.

For part speeds above 50 MHz, use 2 ns for B19.

The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 23

Bus Signal Timing

The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in

B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.

The AS signal is considered asynchronous to CLKOUT. The timing B39 is specified in order to allow the behavior

specified in Figure 23.

Figure 5 shows the control timing diagram.

CLKOUT

Outputs

Inputs

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input setup time specification

D Minimum input hold time specification

Figure 5. Control Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

24 Freescale Semiconductor

Figure 6 shows the timing for the external clock.

CLKOUT

Bus Signal Timing

Figure 6. External Clock Timing

Figure 7 shows the timing for the synchronous output signals.

CLKOUT

B7 B9

Output

Signals

B8a

Output

Signals

B8b

B9B7a

Output

Signals

B7b

Figure 7. Synchronous Output Signals Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 25

Bus Signal Timing

Figure 8 shows the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13

B12B11

, BB

B13a

B11a B12a

TA , BI

B14

B15

TEA

Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Output Signals Timing

Figure 9 shows the timing for the synchronous input signals.

CLKOUT

B16

, BI

B16a

TEA, KR,

RETRY

, CR

B16b

BB, BG, BR

B17

B17a

B17

Figure 9. Synchronous Input Signals Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

26 Freescale Semiconductor

Bus Signal Timing

Figure 10 shows normal case timing for input data. It also applies to normal read accesses under the control of the

UPM in the memory controller.

CLKOUT

B16

B17

B18

B19

D[0:31],

DP[0:3]

Figure 10. Input Data Timing in Normal Case

Figure 11 shows the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM

RAM words. (This is only the case where data is latched on the fal ling edge of CLKOUT. )

CLKOUT

B20

B21

D[0:31],

DP[0:3]

Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 27

Bus Signal Timing

Figure 12 through Figure 15 show the timing for the external bus read controlled by various GPCM factors.

CLKOUT

B11 B12

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B22

B25

B28

B23

B26

B19

B18

Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00)

MPC866/MPC859 Hardware Specifications, Rev. 2

28 Freescale Semiconductor

CLKOUT

A[0:31]

Bus Signal Timing

B11 B12

B22a

CSx

B25B24

D[0:31],

DP[0:3]

B23

B26

B19B18

Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10)

CLKOUT

B11 B12

B22bB8

A[0:31]

B22c B23

CSx

B24a B25 B26

B19B18

D[0:31],

DP[0:3]

Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 11)

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 29

Bus Signal Timing

CLKOUT

A[0:31]

B11 B12

B23

B26

CSx

D[0:31],

DP[0:3]

B22a

B27

B27a

B22b B22c B19B18

Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)

MPC866/MPC859 Hardware Specifications, Rev. 2

30 Freescale Semiconductor

Bus Signal Timing

Figure 16 through Figure 18 show the timing for the external bus write controlle d by various GPCM factors.

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B11

B22 B23

B26

B12

B8 B9

B30

B28B25

B29b

B29

Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 31

Bus Signal Timing

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B11

B22

B26

B12

B28b B28d

B25

B28aB9B28c

B30a B30c

B23

B29c B29g

B29a B29f

Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)

MPC866/MPC859 Hardware Specifications, Rev. 2

32 Freescale Semiconductor

CLKOUT

Bus Signal Timing

B12B11

A[0:31]

B28b B28d

CSx

B25 B29e B29i

WE[0:3]

B26 B29d B29h

B28a B28c B9B8

D[0:31],

DP[0:3]

B30dB30b

B29b

Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)

B23B22

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 33

Bus Signal Timing

Figure 19 shows the timing for the external bus controlle d by the UPM.

CLKOUT

A[0:31]

B31a

B31d

B31

CSx

B34

B34a

B34b

B32a B32d

B32

B31c

B31b

B32c

B32b

BS_A

[0:3],

[0:3]

BS_B

GPL_A[0:5],

GPL_B

[0:5]

B36

B35

B35a

B35b

B33

B33a

Figure 19. External Bus Timing (UPM Controlled Signals)

MPC866/MPC859 Hardware Specifications, Rev. 2

34 Freescale Semiconductor

Figure 20 shows the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3],

BS_B

[0:3]

GPL_A

[0:5],

GPL_B

[0:5]

Figure 20. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Bus Signal Timing

Figure 21 shows the timing for the asynchronous negated UPWAIT signal controlle d by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3],

[0:3]

BS_B

GPL_A

[0:5],

GPL_B

[0:5]

Figure 21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 35

Bus Signal Timing

Figure 22 shows the timing for the synchronous external maste r access controlled by the GPCM.

CLKOUT

B41 B42

B40

A[0:31],

TSIZ[0:1],

R/W

, BURST

B22

CSx

Figure 22. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

MPC866/MPC859 Hardware Specifications, Rev. 2

36 Freescale Semiconductor

Bus Signal Timing

Figure 23 shows the timing for the asynchronous externa l master memory access controlled by the GPCM.

CLKOUT

B39

B40

A[0:31],

TSIZ[0:1],

R/W

B22

CSx

Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 24 shows the timing for the asynchronous externa l master control signals negation.

B43

CSx, WE[0:3],

, GPLx,

[0:3]

Figure 24. Asynchronous External Master—Control Signals Negation Timing

Table 10 shows the interrupt timing for the MPC866/859.

Table 10. Interrupt Timing

Num Characteristic

I39 IRQ

I40 IRQ

I41 IRQ

I42 IRQ

I43 IRQ

The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ no direct relation with the total system interrupt latency that the MPC866/859 is able to support.

x valid to CLKOUT rising edge (setup time) 6.00 — ns

x hold time after CLKOUT 2.00 — ns

x pulse width low 3.00 — ns

x pulse width high 3.00 — ns

x edge-to-edge time 4xT

lines are synchronized internally and do not have to be asserted or negated with reference

All Frequencies

Unit

Min Max

CLOCKOUT

lines detection circuitry, and has

——

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 37

Bus Signal Timing

Figure 25 shows the interrupt detection timing for the external level-sensitive lines.

CLKOUT

I39

I40

IRQ

Figure 25. Interrupt Detection Timing for External Level Sensitive Lines

Figure 26 shows the interrupt detection timing for the external edge-sensitive lines.

CLKOUT

I41 I42

IRQ

I43

Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines

Table 11 shows the PCMCIA timing for the MPC866/859.

Table 11. PCMCIA Timing

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

A(0:31), REG Strobe asserted

P44

– 2.00)

A(0:31), REG

P45

negation

CLKOUT to REG

P46

x B1 + 8.00)

CLKOUT to REG

P47

0.25 x B1 + 1.00)

CLKOUT to CE1

P48

(MAX = 0.25 x B1 + 8.00)

(MIN = 1.00 x B1 – 2.00)

valid to PCMCIA

(MIN = 0.75 x B1

valid to ALE

valid (MAX = 0.25

invalid (MIN =

, CE2 asserted

20.70 — 16.70 — 13.00 — 9.40 — ns

28.30 — 23.00 — 18.00 — 13.20 — ns

7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns

8.60 — 7.30 — 6.00 — 4.80 — ns

7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns

I43

Unit

CLKOUT to CE1

P49

(MAX = 0.25 x B1 + 8.00)

38 Freescale Semiconductor

, CE2 negated

MPC866/MPC859 Hardware Specifications, Rev. 2

7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns

Num Characteristic

Bus Signal Timing

Table 11. PCMCIA Timing (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

CLKOUT to PCOE IOWR

P50

, IORD, PCWE,

assert time (MAX = 0.00 x

— 11.00 — 11.00 — 11.00 — 11.00 ns

B1 + 11.00)

CLKOUT to PCOE IOWR

P51

, IORD, PCWE,

negate time (MAX = 0.00 x

2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns

B1 + 11.00)

CLKOUT to ALE assert time (MAX

P52

= 0.25 x B1 + 6.30)

CLKOUT to ALE negate time (MAX

P53

= 0.25 x B1 + 8.00)

, IOWR negated to D(0:31)

PCWE

P54

P55

invalid

WAITA

(MIN = 0.25 x B1 – 2.00)

and WAITB valid to

CLKOUT rising edge

(MIN = 0.00

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

— 15.60 — 14.30 — 13.00 — 11.80 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

8.00 — 8.00 — 8.00 — 8.00 — ns

x B1 + 8.00)

2.00 — 2.00 — 2.00 — 2.00 — ns

CLKOUT rising edge to WAITA WAITB

P56

invalid1 (MIN = 0.00 x B1 +

and

2.00)

PSST = 1. Otherwise, add PSST times cycle time. PSHT = 0. Otherwise, add PSHT times cycle time. These synchronous timings define when the WAITx current cycle. The WAITx PCMCIA Interface in the

assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See

MPC866 PowerQUICC User’s Manual

signals are detected in order to freeze (or relieve) the PCMCIA

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 39

Bus Signal Timing

Figure 27 shows the PCM CI A access cy cle tim ing fo r the ext ern a l bus rea d .

CLKOUT

P44

A[0:31]

REG

CE1/CE2

PCOE, IORD

ALE

D[0:31]

P46 P45

P48 P49

P53P52 P52

P47

P51P50

Figure 27. PCMCIA Access Cycles Timing External Bus Read

B19B18

MPC866/MPC859 Hardware Specifications, Rev. 2

40 Freescale Semiconductor

Figure 28 shows the PCM CI A access cy cle tim ing fo r the ext ern a l bus wri te .

CLKOUT

P44

A[0:31]

Bus Signal Timing

P46 P45

REG

P48 P49

CE1/CE2

PCWE, IOWR

ALE

D[0:31]

Figure 28. PCMCIA Access Cycles Timing External Bus Write

Figure 29 shows the PCMCIA WAIT signals detection timing.

P47

P51P50

P53P52 P52

B9B8

P54

CLKOUT

P55

P56

WAIT

Figure 29. PCMCIA WAIT Signals Detection Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 41

Bus Signal Timing

Table 12 shows the PCMCIA port timing for the MPC866/859.

Table 12. PCMCIA Port Timing

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

CLKOUT to OPx, valid (MAX = 0.00 x B1

P57

+ 19.00)

HRESET

P58

0.75 x B1 + 3.00)

IP_Xx valid to CLKOUT rising edge (MIN

P59

= 0.00 x B1 + 5.00)

CLKOUT rising edge to IP_Xx invalid

P60

(MIN = 0.00 x B1 + 1.00)

OP2 and OP3 only.

negated to OPx drive 1(MIN =

— 19.00 — 19.00 — 19.00 — 19.00 ns

25.70 — 21.70 — 18.00 — 14.40 — ns

5.00 — 5.00 — 5.00 — 5.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

Figure 30 shows the PCMCIA output port timing for the MPC866/859.

CLKOUT

P57

Output

Signals

HRESET

P58

OP2, OP3

Figure 30. PCMCIA Output Port Timing

Figure 31 shows the PCMCIA output port timing for the MPC866/859.

CLKOUT

P59

P60

Input

Signals

Figure 31. PCMCIA Input Port Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

42 Freescale Semiconductor

Table 13 shows the debug port timing for the MPC866/859.

Table 13. Debug Port Timing

Num Characteristic

Bus Signal Timing

All Frequencies

Unit

Min Max

D61 DSCK cycle time 3xT

D62 DSCK clock pulse width 1.25xT

D63 DSCK rise and fall times 0.00 3.00 ns

D64 DSDI input data setup time 8.00 — ns

D65 DSDI data hold time 5.00 — ns

D66 DSCK low to DSDO data valid 0.00 15.00 ns

D67 DSCK low to DSDO invalid 0.00 2.00 ns

CLOCKOUT

Figure 32 shows the input timing for the debug port clock.

DSCK

D61

D63

D62

D63

Figure 32. Debug Port Clock Input Timing

Figure 33 shows the timing for the debug port.

—

DSCK

D64

D65

DSDI

D66

D67

DSDO

Figure 33. Debug Port Timings

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 43

Bus Signal Timing

Table 14 shows the reset timing for the MPC866/859.

Table 14. Reset Timing

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

CLKOUT to HRESET

R69

(MAX = 0.00 x B1 + 20.00)

CLKOUT to SRESET

R70

(MAX = 0.00 x B1 + 20.00)

RSTCONF

R71

B1)

R72— —————————

Configuration data to HRESET rising

R73

edge setup time (MIN = 15.00 x B1 +

50.00)

Configuration data to RSTCONF edge setup time (MIN = 0.00 x B1 +

R74

350.00)

Configuration data hold time after

R75

RSTCONF

0.00)

Configuration data hold time after

R76

HRESET

0.00)

HRESET data out drive (MAX = 0.00 x B1 +

R77

25.00)

pulse width (MIN = 17.00 x

negation (MIN = 0.00 x B1 +

and RSTCONF asserted to

high impedance

rising

— 20.00 — 20.00 — 20.00 — 20.00 ns

515.20 — 425.00 — 340.00 — 257.60 — ns

504.50 — 425.00 — 350.00 — 277.30 — ns

350.00 — 350.00 — 350.00 — 350.00 — ns

0.00 — 0.00 — 0.00 — 0.00 — ns

— 25.00 — 25.00 — 25.00 — 25.00 ns

RSTCONF

R78

impedance (MAX = 0.00 x B1 + 25.00)

CLKOUT of last rising edge before chip

R79

three-states HRESET impedance (MAX = 0.00 x B1 + 25.00)

R80 DSDI, DSCK setup (MIN = 3.00 x B1) 90.90 — 75.00 — 60.00 — 45.50 — ns

DSDI, DSCK hold time (MIN = 0.00 x B1

R81

+ 0.00)

SRESET

R82

edge for DSDI and DSCK sample (MIN = 8.00 x B1)

44 Freescale Semiconductor

negated to data out high

to data out high

negated to CLKOUT rising

MPC866/MPC859 Hardware Specifications, Rev. 2

— 25.00 — 25.00 — 25.00 — 25.00 ns

0.00 — 0.00 — 0.00 — 0.00 — ns

242.40 — 200.00 — 160.00 — 121.20 — ns

Figure 34 shows the reset timing for the data bus configura tion.

HRESET

R71

R76

RSTCONF

R73

R74

D[0:31] (IN)

R75

Figure 34. Reset Timing—Configuration from Data Bus

Figure 35 shows the reset timing for the data bus weak drive during configuration.

Bus Signal Timing

CLKOUT

HRESET

RSTCONF

D[0:31] (OUT)

(Weak)

R69

R79

R77 R78

Figure 35. Reset Timing—Data Bus Weak Drive During Configuration

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 45

IEEE 1149.1 Electrical Specifications

Figure 36 shows the reset timing for the debug port configura tion.

CLKOUT

R70

R82

SRESET

R80R80

R81

DSCK, DSDI

R81

Figure 36. Reset Timing—Debug Port Configuration

11 IEEE 1149.1 Electrical Specifications

Table 15 shows the JTAG timings for the MPC866/859 shown in Figure 37 through Figure 40.

Table 15. JTAG Timing

All Frequencies

Num Characteristic

Min Max

J82 TCK cycle time 100.00 — ns

J83 TCK clock pulse width measured at 1.5 V 40.00 — ns

J84 TCK rise and fall times 0.00 10.00 ns

J85 TMS, TDI data setup time 5.00 — ns

J86 TMS, TDI data hold time 25.00 — ns

J87 TCK low to TDO data valid — 27.00 ns

J88 TCK low to TDO data invalid 0.00 — ns

J89 TCK low to TDO high impedance — 20.00 ns

J90 TRST

J91 TRST

J92 TCK falling edge to output valid — 50.00 ns

J93 TCK falling edge to output valid out of high impedance — 50.00 ns

J94 TCK falling edge to output high impedance — 50.00 ns

J95 Boundary scan input valid to TCK rising edge 50.00 — ns

assert time 100.00 — ns

setup time to TCK low 40.00 — ns

Unit

J96 TCK rising edge to boundary scan input invalid 50.00 — ns

MPC866/MPC859 Hardware Specifications, Rev. 2

46 Freescale Semiconductor

TCK

TMS, TDI

IEEE 1149.1 Electrical Specifications

J82 J83

J84 J84

Figure 37. JTAG Test Clock Input Timing

J85

J86

J87

J88 J89

TDO

TCK

TRST

Figure 38. JTAG Test Access Port Timing Diagram

J91

J90

Figure 39. JTAG TRST

Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 47

CPM Electrical Characteristics

TCK

J92 J94

Output

Signals

J93

Output

Signals

J95 J96

Output

Signals

Figure 40. Boundary Scan (JTAG) Timing Diagram

12 CPM Electrical Characteristics

This section provides the AC and DC electr ical specifications for the communicati ons processor module (CPM) of the MPC866/859.

12.1 PIP/PIO AC Electrical Specifications

Table 16 shows the PIP/PIO AC timings as shown in Figure 41 through Figure 45.

Table 16. PIP/PIO Timing

All Frequencies

Num Characteristic

Min Max

21 Data-in setup time to STBI low 0 — ns

22 Data-In hold time to STBI high 2.5 – t3

23 STBI pulse width 1.5 — clk

24 STBO pulse width 1 clk – 5ns — ns

25 Data-out setup time to STBO low 2 — clk

26 Data-out hold time from STBO high 5 — clk

27 STBI low to STBO low (Rx interlock) — 2 clk

28 STBI low to STBO high (Tx interlock) 2 — clk

29 Data-in setup time to clock high 15 — ns

30 Data-in hold time from clock high 7.5 — ns

31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns

t3 = Specification 23

—clk

Unit

MPC866/MPC859 Hardware Specifications, Rev. 2

48 Freescale Semiconductor

DATA-IN

CPM Electrical Characteristics

STBI

STBO

DATA-OUT

STBO

(Output)

Figure 41. PIP Rx (Interlock Mode) Timing Diagram

STBI

(Input)

DATA-IN

STBI

(Input)

STBO

(Output)

Figure 42. PIP Tx (Interlock Mode) Timing Diagram

2221

Figure 43. PIP Rx (Pulse Mode) Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 49

CPM Electrical Characteristics

DATA-OUT

STBO

(Output)

STBI

(Input)

CLKO

2625

Figure 44. PIP TX (Pulse Mode) Timing Diagram

DATA-IN

DATA-OUT

Figure 45. Parallel I/O Data-In/Data-Out Timing Diagram

12.2 Port C Interrupt AC Electrical Specifications

Table 17 shows timings for port C interrupts.

Table 17. Port C Interrupt Timing

Num Characteristic

35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns

36 Port C interrupt minimum time between active edges 55 — ns

Figure 46 shows the port C interrupt detection timing.

33.34 MHz Unit

Min Max

MPC866/MPC859 Hardware Specifications, Rev. 2

50 Freescale Semiconductor

Port C

(Input)

Figure 46. Port C Interrupt Detection Timing

12.3 IDMA Controller AC Electrical Specifications

Table 18 shows the IDMA controller timings as shown in Figure 47 through Figure 50.

Table 18. IDMA Controller Timing

Num Characteristic

CPM Electrical Characteristics

All Frequencies

Unit

Min Max

40 DREQ

41 DREQ

42 SDACK

43 SDACK

44 SDACK

45 SDACK

46 TA

assertion to falling edge of the clock setup time (applies to external TA)7 —ns

CLKO

(Output)

DREQ (Input)

setup time to clock high 7 — ns

hold time from clock high 3 — ns

assertion delay from clock high — 12 ns

negation delay from clock low — 12 ns

negation delay from TA low — 20 ns

negation delay from clock high — 15 ns

Figure 47. IDMA External Requests Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 51

CPM Electrical Characteristics

CLKO

(Output)

R/W

(Output)

DATA

(Input)

SDACK

Figure 48. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA

CLKO

(Output)

R/W

(Output)

42 44

DATA

(Output)

SDACK

Figure 49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA

MPC866/MPC859 Hardware Specifications, Rev. 2

52 Freescale Semiconductor

CLKO

(Output)

R/W

(Output)

DATA

(Output)

SDACK

CPM Electrical Characteristics

42 45

Figure 50. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA

12.4 Baud Rate Generator AC Electrical Specifications

Table 19 shows the baud rate generator timings as shown in Figure 51.

Table 19. Baud Rate Generator Timing

All Frequencies

Num Characteristic

Min Max

50 BRGO rise and fall time — 10 ns

51 BRGO duty cycle 40 60 %

52 BRGO cycle 40 — ns

BRGOX

Unit

Figure 51. Baud Rate Generator Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 53

CPM Electrical Characteristics

12.5 Timer AC Electrical Specifications

Table 20 shows the general-purpose timer timings as shown in Figure 52.

Num Characteristic

Table 20. Timer Timing

All Frequencies

Unit

Min Max

61 TIN/TGATE

62 TIN/TGATE

63 TIN/TGATE

64 TIN/TGATE

65 CLKO low to TOUT

CLKO

TIN/TGATE

(Input)

TOU T

(Output)

rise and fall time 10 — ns

low time 1 — clk

high time 2 — clk cycle time 3 — clk

valid 3 25 ns

626361

Figure 52. CPM General-Purpose Timers Timing Diagram

12.6 Serial Interface AC Electrical Specifications

Table 21 shows the serial interface timings as shown in Figure53 through Figure 57.

Num Characteristic

70 L1RCLK, L1TCLK frequency (DSC = 0)

71 L1RCLK, L1TCLK width low (DSC = 0)

71a L1RCLK, L1TCLK width high (DSC = 0)

72 L1TXD, L1ST(1–4), L1RQ

73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC

setup time)

54 Freescale Semiconductor

, L1CLKO rise/fall time — 15.00 ns

MPC866/MPC859 Hardware Specifications, Rev. 2

Table 21. SI Timing

All Frequencies

Min Max

1, 2

— SYNCCLK/2.5 MHz

P + 10 — ns

20.00 — ns

Unit

Table 21. SI Timing (continued)

Num Characteristic

CPM Electrical Characteristics

All Frequencies

Unit

Min Max

74 L1CLK edge to L1RSYNC, L1TSYNC, invalid

35.00 — ns

(SYNC hold time)

75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns

76 L1RXD valid to L1CLK edge (L1RXD setup time) 17.00 — ns

77 L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns

78 L1CLK edge to L1ST(1–4) valid

10.00 45.00 ns

78A L1SYNC valid to L1ST(1–4) valid 10.00 45.00 ns

79 L1CLK edge to L1ST(1–4) invalid 10.00 45.00 ns

80 L1CLK edge to L1TXD valid 10.00 55.00 ns

80A L1TSYNC valid to L1TXD valid

10.00 55.00 ns

81 L1CLK edge to L1TXD high impedance 0.00 42.00 ns

82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or SYNCCLK/2 MHz

83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns

83a L1RCLK, L1TCLK width high (DSC = 1)

P + 10 — ns

84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns

85 L1RQ

valid before falling edge of L1TSYNC

86 L1GR setup time

1.00 — L1TCLK

42.00 — ns

87 L1GR hold time 42.00 — ns

88 L1CLK edge to L1SYNC valid (FSD = 00) CNT =

—0.00ns

0000, BYT = 0, DSC = 0)

The ratio SyncCLK/L1RCLK must be greater than 2.5/1.

These specs are valid for IDL mode only.

Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.

These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 55

CPM Electrical Characteristics

L1RCLK

(FE=0, CE=0)

(Input)

L1RCLK

(FE=1, CE=1)

(Input)

L1RSYNC

(Input)

70 71a

RFSD=1

74 77

L1RXD

(Input)

L1ST(4-1)

(Output)

BIT0

Figure 53. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

MPC866/MPC859 Hardware Specifications, Rev. 2

56 Freescale Semiconductor

L1RCLK

(FE=1, CE=1)

(Input)

L1RCLK

(FE=0, CE=0)

(Input)

L1RSYNC

(Input)

RFSD=1

74 77

CPM Electrical Characteristics

83a

L1RXD

(Input)

L1ST(4-1)

(Output)

L1CLKO

(Output)

BIT0

Figure 54. SI Receive Timing with Double-Speed Clocking (DSC = 1)

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 57

CPM Electrical Characteristics

L1TCLK

(FE=0, CE=0)

(Input)

71 70

L1TCLK

(FE=1, CE=1)

(Input)

L1TSYNC

(Input)

80a

TFSD=0

L1TXD

(Output)

L1ST(4-1)

(Output)

BIT0

Figure 55. SI Transmit Timing Diagram (DSC = 0)

MPC866/MPC859 Hardware Specifications, Rev. 2

58 Freescale Semiconductor

L1RCLK

(FE=0, CE=0)

(Input)

L1RCLK

(FE=1, CE=1)

(Input)

L1RSYNC

(Input)

TFSD=0

CPM Electrical Characteristics

83a

L1TXD

(Output)

L1ST(4-1)

(Output)

L1CLKO

(Output)

BIT0

78a

Figure 56. SI Transmit Timing with Double Speed Clocking (DSC = 1)

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 59

CPM Electrical Characteristics

12345678910 11 12 13 14 15 16 17 18 19 20

(Input)

L1RCLK

L1RSYNC

B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15

(Input)

L1TXD

(Output)

(Input)

L1RXD

L1ST(4-1)

(Output)

L1RQ

(Output)

L1GR

(Input)

Figure 57. IDL Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

60 Freescale Semiconductor

12.7 SCC in NMSI Mode Electrical Specifications

Table 22 show s the NMSI external cl ock timi ng s .

Table 22. NMSI External Clock Timings

All Frequencies

Num Characteristic

Min Max

100 RCLK1 and TCLK1 width high

101 RCLK1 and TCLK1 width low 1/SYNCCLK +5 — ns

102 RCLK1 and TCLK1 rise/fall time — 15.00 ns

103 TXD1 active delay (from TCLK1 falling edge) 0.00 50.00 ns

1/SYNCCLK — ns

CPM Electrical Characteristics

Unit

104 RTS1

105 CTS1

active/inactive delay (from TCLK1 falling edge) 0.00 50.00 ns

setup time to TCLK1 rising edge 5.00 — ns

106 RXD1 setup time to RCLK1 rising edge 5.00 — ns

107 RXD1 hold time from RCLK1 rising edge

108 CD1

The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.

Also applies to CD and CTS hold time when they are used as an external sync signal.

setup time to RCLK1 rising edge 5.00 — ns

5.00 — ns

Table 23 shows the NMSI internal clock timings.

Table 23. NMSI Internal Clock Timings

All Frequencies

Num Characteristic

Min Max

100 RCLK1 and TCLK1 frequency

102 RCLK1 and TCLK1 rise/fall time — — ns

103 TXD1 active delay (from TCLK1 falling edge) 0.00 30.00 ns

104 RTS1

105 CTS1

active/inactive delay (from TCLK1 falling edge) 0.00 30.00 ns

setup time to TCLK1 rising edge 40.00 — ns

0.00 SYNCCLK/3 MHz

Unit

106 RXD1 setup time to RCLK1 rising edge 40.00 — ns

107 RXD1 hold time from RCLK1 rising edge

108 CD1

The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.

Also applies to CD and CTS hold time when they are used as an external sync signals.

setup time to RCLK1 rising edge 40.00 — ns

0.00 — ns

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 61

CPM Electrical Characteristics

Figure 58 through Figure 60 show the NMSI timings.

RCLK1

RxD1

(Input)

CD1

(Input)

CD1

(SYNC Input)

TCLK1

106

102

102 101

100

107

Figure 58. SCC NMSI Receive Timing Diagram

102 101

100

108

107

TxD1

(Output)

RTS1

(Output)

CTS1

(Input)

CTS1

(SYNC Input)

103

105

104

Figure 59. SCC NMSI Transmit Timing Diagram

104

107

MPC866/MPC859 Hardware Specifications, Rev. 2

62 Freescale Semiconductor

TCLK1

CPM Electrical Characteristics

102

TxD1

(Output)

RTS1

(Output)

CTS1

(Echo Input)

102 101

100

103

104

105

Figure 60. HDLC Bus Timing Diagram

12.8 Ethernet Electrical Specifications

Table 24 shows the Ethernet timings as shown in Figure 61 through Figure 65.

Table 24. Ethernet Timing

104107

All Frequencies

Num Characteristic

Min Max

120 CLSN width high 40 — ns

121 RCLK1 rise/fall time — 15 ns

122 RCLK1 width low 40 — ns

123 RCLK1 clock period

124 RXD1 setup time 20 — ns

125 RXD1 hold time 5 — ns

126 RENA active delay (from RCLK1 rising edge of the last data bit) 10 — ns

127 RENA width low 100 — ns

128 TCLK1 rise/fall time — 15 ns

129 TCLK1 width low 40 — ns

130 TCLK1 clock period

131 TXD1 active delay (from TCLK1 rising edge) — 50 ns

132 TXD1 inactive delay (from TCLK1 rising edge) 6.5 50 ns

133 TENA active delay (from TCLK1 rising edge) 10 50 ns

80 120 ns

99 101 ns

Unit

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 63

CPM Electrical Characteristics

Table 24. Ethernet Timing (continued)

All Frequencies

Num Characteristic

Min Max

134 TENA inactive delay (from TCLK1 rising edge) 10 50 ns

Unit

135 RSTRT

136 RSTRT

137 REJECT

138 CLKO1 low to SDACK

139 CLKO1 low to SDACK

The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1.

SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

active delay (from TCLK1 falling edge) 10 50 ns

inactive delay (from TCLK1 falling edge) 10 50 ns

width low 1 — CLK

asserted

negated

CLSN(CTS1)

(Input)

120

Figure 61. Ethernet Collision Timing Diagram

RCLK1

121

124 123

121

—20ns

RxD1

(Input)

RENA(CD1)

(Input)

125

126

Figure 62. Ethernet Receive Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Last Bit

127

64 Freescale Semiconductor

TCLK1

CPM Electrical Characteristics

(Output)

TENA(RTS1)

(Input)

RENA(CD1)

Notes:

RCLK1

128

131 121

TxD1

133 134

(Input)

Transmit clock invert (TCI) bit in GSMR is set.

1. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the

2. CSL bit is set in the buffer descriptor at the end of the frame transmission.

128

129

132

Figure 63. Ethernet Transmit Timing Diagram

RxD1

(Input)

RSTRT

(Output)

Start Frame Delimiter

1 1 BIT1 BIT2

136

125

Figure 64. CAM Interface Receive Start Timing Diagram

REJECT

137

Figure 65. CAM Interface REJECT

Timing Diagram

12.9 SMC Transparent AC Electrical Specifications

Table 25 shows the SMC transparent timings as shown in Figure 66.

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 65

CPM Electrical Characteristics

Num Characteristic

150 SMCLK clock period

151 SMCLK width low 50 — ns

151A SMCLK width high 50 — ns

152 SMCLK rise/fall time — 15 ns

153 SMTXD active delay (from SMCLK falling edge) 10 50 ns

154 SMRXD/SMSYNC setup time 20 — ns

155 RXD1/SMSYNC hold time 5 — ns

Sync CLK must be at least twice as fast as SMCLK.

SMCLK

Table 25. SMC Transparent Timing

All Frequencies

Unit

Min Max

100 — ns

SMTXD

(Output)

SMSYNC

SMRXD

(Input)

NOTE:

152

This delay is equal to an integer number of character-length clocks.1.

152 151

151A

150

NOTE 1

154 153

155

154

155

Figure 66. SMC Transparent Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

66 Freescale Semiconductor

12.10SPI Master AC Electrical Specifications

Table 26 shows the SPI master timings as shown in Figure 67 and Figure 68.

Table 26. SPI Master Timing

Num Characteristic

CPM Electrical Characteristics

All Frequencies

Unit

Min Max

160 MASTER cycle time 4 1024 t

161 MASTER clock (SCK) high or low time 2 512 t

162 MASTER data setup time (inputs) 15 — ns

163 Master data hold time (inputs) 0 — ns

164 Master data valid (after SCK edge) — 10 ns

165 Master data hold time (outputs) 0 — ns

166 Rise time output — 15 ns

167 Fall time output — 15 ns

SPICLK

(CI=0)

(Output)

166167161

161 160

SPICLK

(CI=1)

(Output)

163

162

166

167

cyc

SPIMISO

(Input)

SPIMOSI

(Output)

msb Data lsb msb

165 164

167 166

msb lsb msb

Data

Figure 67. SPI Master (CP = 0) Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 67

CPM Electrical Characteristics

SPICLK

(CI=0)

(Output)

161 160

SPICLK

(CI=1)

(Output)

163

162

166167161

167

166

SPIMISO

(Input)

SPIMOSI

(Output)

msb Data lsb msb

165 164

167 166

msb lsb msb

Data

Figure 68. SPI Master (CP = 1) Timing Diagram

12.11SPI Slave AC Electrical Specifications

Table 27 shows the SPI slave timings as shown in Figure 69 and Figure 70.

Table 27. SPI Slave Timing

Num Characteristic

170 Slave cycle time 2 — t

171 Slave enable lead time 15 — ns

172 Slave enable lag time 15 — ns

All Frequencies

Unit

Min Max

cyc

173 Slave clock (SPICLK) high or low time 1 — t

174 Slave sequential transfer delay (does not require deselect) 1 — t

175 Slave data setup time (inputs) 20 — ns

176 Slave data hold time (inputs) 20 — ns

177 Slave access time — 50 ns

MPC866/MPC859 Hardware Specifications, Rev. 2

68 Freescale Semiconductor

cyc

SPISEL

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

181182173

173 170

177 182

181

180

CPM Electrical Characteristics

171172

174

178

SPIMISO

(Output)

SPIMOSI

(Input)

Datamsb lsb msbUndef

175 179

176 182

msb lsb msb

Data

181

Figure 69. SPI Slave (CP = 0) Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 69

CPM Electrical Characteristics

SPISEL

(Input)

171 170

SPICLK

(CI=0) (Input)

173

SPICLK

(CI=1) (Input)

177 182

173

180

172

174

181182

181

178

SPIMISO

(Output)

175 179

SPIMOSI

(Input)

msb

176 182

msb lsb

Data

181

Data

Figure 70. SPI Slave (CP = 1) Timing Diagram

12.12I2C AC Electrical Specifications

lsbUndef

msb

MPC866/MPC859 Hardware Specifications, Rev. 2

70 Freescale Semiconductor

Table 28 shows the I2C (SCL < 100 kHz) timings.

Table 28. I2C Timing (SCL < 100 kHz)

CPM Electrical Characteristics

Num Characteristic

200 SCL clock frequency (slave) 0 100 kHz

200 SCL clock frequency (master)

202 Bus free time between transmissions 4.7 — μs

203 Low period of SCL 4.7 — μs

204 High period of SCL 4.0 — μs

205 Start condition setup time 4.7 — μs

206 Start condition hold time 4.0 — μs

207 Data hold time 0 — μs

208 Data setup time 250 — ns

209 SDL/SCL rise time — 1 μs

210 SDL/SCL fall time — 300 ns

211 Stop condition setup time 4.7 — μs

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.

Table 29 shows the I

C (SCL > 100 kHz) timings.

All Frequencies

Min Max

1.5 100 kHz

Table 29. I2C Timing (SCL > 100 kHz)

Unit

All Frequencies

Num Characteristic Expression

Min Max

200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz

200 SCL clock frequency (master)

202 Bus free time between transmissions — 1/(2.2 * fSCL) — s

203 Low period of SCL — 1/(2.2 * fSCL) — s

204 High period of SCL — 1/(2.2 * fSCL) — s

205 Start condition setup time — 1/(2.2 * fSCL) — s

206 Start condition hold time — 1/(2.2 * fSCL) — s

207 Data hold time — 0 — s

208 Data setup time — 1/(40 * fSCL) — s

209 SDL/SCL rise time — — 1/(10 * fSCL) s

210 SDL/SCL fall time — — 1/(33 * fSCL) s

211 Stop condition setup time — 1/2(2.2 * fSCL) — s

SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.

fSCL BRGCLK/16512 BRGCLK/48 Hz

Unit

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 71

UTOPIA AC Electrical Specifications

Figure 71 shows the I2C bus timing.

SDA

202

205

SCL

206 209 211210

203

207

204

208

Figure 71. I2C Bus Timing Diagram

13 UTOPIA AC Electrical Specifications

Table 30 through Table 32 show the AC el ect rical specificati on s for the UTOP IA interf ace.

Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications

Num Signal Characteristic Direction Min Max Unit

U1 UtpClk rise/fall time (Internal clock option) Output — 4 ns

Duty cycle 50 50 %

Frequency — 33 MHz

U2 UTPB, SOC, RxEnb

delay (and PHREQ and PHSEL active delay in MPHY mode)

U3 UTPB, SOC, Rxclav and Txclav setup time Input 4 — ns

, TxEnb, RxAddr, and TxAddr-active

Output 2 16 ns

U4 UTPB, SOC, Rxclav and Txclav hold time Input 1 — ns

Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications

Num Signal Characteristic Direction Min Max Unit

U1 UtpClk rise/fall time (Internal clock option) Output — 4 ns

Duty cycle 50 50 %

Frequency — 33 MHz

U2 UTPB, SOC, RxEnb

delay (PHREQ and PHSEL active delay in MPHY mode)

U3 UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time Input 4 — ns

U4 UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time Input 1 — ns

, TxEnb, RxAddr and TxAddr active

MPC866/MPC859 Hardware Specifications, Rev. 2

Output 2 16 ns

72 Freescale Semiconductor

UTOPIA AC Electrical Specifications

Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications

Num Signal Characteristic Direction Min Max Unit

U1 UtpClk rise/fall time (external clock option) Input — 4 ns

Duty cycle 40 60 %

Frequency — 33 MHz

U2 UTPB, SOC, Rxclav and Txclav active delay Output 2 16 ns

U3 UTPB_AUX, SOC_Aux, RxEnb

setup time

U4 UTPB_AUX, SOC_Aux, RxEnb

hold time

, TxEnb, RxAddr, and TxAddr

Figure 72 shows signal timings during UTOPI A receive operations.

UtpClk

PHREQn

U3 U4

RxClav

RxEnb

UTPB SOC

HighZ at MPHY

Input 4 — ns

Input 1 — ns

HighZ at MPHY

Figure 72. UTOPIA Receive Timing

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 73

FEC Electrical Characteristics

Figure 73 shows signal timings during UTOPI A transmi t operations.

UtpClk

PHSELn

TxClav

TxEnb

UTPB SOC

U3 U4

HighZ at MPHY High-Z at MPHY

Figure 73. UTOPIA Transmit Timing

14 FEC Electrical Characteristics

This section provides the AC electric al specifications for the fast Ethe rnet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels co mpatible with devices operating at either 5.0 or 3.3 V.

14.1 MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK)

The receiver f unctions corre ctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The re is no minim um frequency requir ement. In addition, the processor clock fre quency must exceed the MII_RX_CLK freque ncy – 1%.

Table 33 shows the timings for MII receive signal.

Table 33. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns

M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns

M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period

M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period

Figure 74 shows the timings for MII receive signal.

MPC866/MPC859 Hardware Specifications, Rev. 2

74 Freescale Semiconductor

MII_RX_CLK (input)

MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER

FEC Electrical Characteristics

Figure 74. MII Receive Signal Timing Diagram

14.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK)

The transmitter funct ions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%.

Table 34 shows information on the MII transmit signal timing.

Table 34. MII Transmit Signal Timing

Num Characteristic Min Max Unit

M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER

invalid

M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER

valid

M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period

M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period

5— ns

—25 —

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 75

FEC Electrical Characteristics

Figure 75 shows the MII transmit signal timing diagram.

MII_TX_CLK (input)

MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER

Figure 75. MII Transmit Signal Timing Diagram

14.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 35 shows the timing for on the MII async inputs signal.

Table 35. MII Async Inputs Signal Timing

Num Characteristic Min Max Unit

M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period

Figure 76 shows the MII asynchronous inputs signal timing diagram.

MII_CRS, MII_COL

Figure 76. MII Async Inputs Timing Diagram

14.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 36 shows the timing for the MII serial management channel signal. The FEC functions correctly with a

maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 36. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M10 MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

0— ns

M11 MII_MDC falling edge to MII_MDIO output valid (maximum

propagation delay)

M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns

MPC866/MPC859 Hardware Specifications, Rev. 2

76 Freescale Semiconductor

—25 ns

FEC Electrical Characteristics

Table 36. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns

M14 MII_MDC pulse width high 40% 60% MII_MDC period

M15 MII_MDC pulse width low 40% 60% MII_MDC period

Figure 77 shows the MII serial management channel timing diagram.

M14

MM15

MII_MDC (output)

M10

MII_MDIO (output)

MII_MDIO (input)

M11

M12

M13

Figure 77. MII Serial Management Channel Timing Diagram

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 77

Mechanical Data and Ordering Information

15 Mechanical Data and Ordering Information

Table 37 shows information on the MPC866/859 derivative devices.

Table 37. MPC866/859 Derivatives

Number

Device

MPC866T 4 10/100 Mbps Yes Yes 4 Kbyte 4 Kbytes

MPC866P 4 10/100 Mbps Yes Yes 16 Kbyte 8 Kbytes

MPC859T 1 (SCC1) 10/100 Mbps Yes Yes 4 Kbyte 4 Kbytes

MPC859DSL 1 (SCC1) 10/100 Mbps No Up to 4 addresses 4 Kbyte 4 Kbytes

Serial communications controller (SCC).

SCCs

Ethernet

Support

Multi-Channel

HDLC Support

ATM Support

Instruction Data

Cache Size

Table 38 identifies the packages and operating frequencies orderable for the MPC866/859 derivative devices.

Package Type Temperature (Tj) Frequency (MHz) Order Number

Plastic ball grid array (ZP suffix) Non lead free

Table 38. MPC866/859 Package/Frequency Orderable

0° to 95°C 50 MPC859DSLZP50A

66 MPC859DSLZP66A

100 MPC859PZP100A

MPC859TZP100A

MPC866PZP100A

MPC866TZP100A

Plastic ball grid array (CZP suffix) Non lead free

133 MPC859PZP133A

MPC859TZP133A

MPC866PZP133A

MPC866TZP133A

–40° to 100°C 50 MPC859DSLCZP50A

66 MPC859DSLCZP66A

100 MPC859PCZP100A

MPC859TCZP100A MPC866PCZP100A MPC866TCZP100A

MPC866/MPC859 Hardware Specifications, Rev. 2

78 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 38. MPC866/859 Package/Frequency Orderable (continued)

Plastic ball grid array (VR suffix) Lead free

Plastic ball grid array (CVR suffix) Lead free

0° to 95°C 50 MPC859DSLVR50A

66 MPC859DSLVR66A

100 MPC859PVR100A

MPC859TVR100A MPC866PVR100A MPC866TVR100A

133 MPC859PVR133A

MPC859TVR133A MPC866PVR133A MPC866TVR133A

–40° to 100°C 50 MPC859DSLCVR50A

66 MPC859DSLCVR66A

100 MPC859PCVR100A

MPC859TCVR100A

MPC866PCVR100A

MPC866TCVR100A

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 79

Mechanical Data and Ordering Information

15.1 Pin Assignments

Figure 78 shows the top view pinout of the PBGA package. For additional infor mation, see the MPC866

PowerQUICC Family User’s Manual.

NOTE: This is the top view of the device.

PD10 PD8

PD14

PD13 PD6 IRQ0

PB14 PD4 IRQ1 D8 D23 D11 D16 D19 D21 D26 D30 IPA5 IPA2 N/CIPA4PD15 PD5 VSSSYNPA 0

P C5 P D1 1 V DD H D1 2 D 17 D9 D 15 D 2 2 D 2 5 D 31 I PA6 I PA0 I PA 7 N / CIPA1PC4 PD7 VDDSYNPA 1

PA 2 P D1 2

PB17 VDDL GND

PA5 PB16

PA 7

PC8 PC7

PC9 PB20 AS

PA9 PB21 GND IPB6 ALEABADDR30PB23 IRQ4PC10

PB24 PB25 IPB1 IPB2IPB5PA 10 ALEBPC11

M_MDIO

TMS PA11 IRQ6

PC12 VDDL

PC13 PB29

PC14 PC15 N/C N/C A15 A19 A25 A18 BSA0

PA15 A3 A12 A16 A20 A24 A26 TSIZ1 BSA1

A1 A6 A13 A17 A21 A23 A22 TSIZ0 BSA3

A2 A7 A14 A27 A29 A30 A28 A31 VDDL BSA2

18 16 14 13 12 11 10 9 8 7 6 5 3 2417 15 119

PD3 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 CLKOUT IPA3DP2

D13D27D10D14D18D20D24D28DP1 DP0N/CDP3PD9 M_Tx_EN

PB15

PB18 EXTALPB19

PA 6

TCK IRQ2 IPB0M_COLTDI IPB7VDDL

VDDH

GND GND

VDDH VDDH

GPLA0 N/C CS6 GPLA5 BDIPCS2PA 14 A8 TEAPB28

WE0 GPLA1 GPLA3 CS0 TACS7PB31 A9 GPLA4PB30

M_CRS WE2 GPLA2 CE1 A WRCS5A4 A10 GPLB4A0

VDDH

WE1 WE3 CE2 A CS1CS4A5 A11

WAIT _B

VDDLPA3 G N D XTALPA4

HRESET

MODCK2

WAIT _A

RSTCONF

TEXP

BADDR28

PORESE T

SRESET

EXTCLK

BADDR29

OP1OP0PA8 MODCK1PB22

IPB4BRTDO IPB3TRST

IRQ3VDDLPA 12 BURSTPB26

BGCS3PA 1 3 BBPB27

VSSSYN1

VDDLPC6

VDDL

Figure 78. Pinout of the PBGA Package

MPC866/MPC859 Hardware Specifications, Rev. 2

80 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 39 contains a list of the MPC866 input and output signals and shows multiplexing and pin assign ments.

Table 39. Pin Assignments

Name Pin Number Type

A[0:31] B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15,

C14, B14, A14, D12, C13, B13, D9, D11, C12, B12, B10, B11, C11, D10, C10, A13, A10, A12, A11, A9

TSIZ0

REG

TSIZ1 C9 Bidirectional

RD/WR

BURST

BDIP GPL_B5

TEA

B2 Bidirectional

B9 Bidirectional

F1 Bidirectional

D2 Output

F3 Bidirectional

C2 Bidirectional

D1 Open-drain

E3 Bidirectional

Bidirectional Three-state

Three-state

Active Pull-up

IRQ2 RSV

IRQ4 KR RETRY

SPKROUT

CR IRQ3

D[0:31] W14, W12, W11, W10, W13, W9, W7, W6, U13, T11, V11, U11,

DP0

IRQ3

DP1 IRQ4

DP2 IRQ5

DP3 IRQ6

H3 Bidirectional

K1 Bidirectional

F2 Input

T13, V13, V10, T10, U10, T12, V9, U9, V8, U8, T9, U12, V7, T8, U7, V12, V6, W5, U6, T7

V3 Bidirectional

V5 Bidirectional

W4 Bidirectional

V4 Bidirectional

Three-state

Bidirectional Three-state

Three-state

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 81

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

BR G4 Bidirectional

FRZ

IRQ6

IRQ0

IRQ1

M_TX_CLK IRQ7

[0:5] C3, A2, D4, E4, A4, B4 Output

CS6 CE1_B

CS7 CE2_B

WE0 BS_B0 IORD

WE1

BS_B1 IOWR

E2 Bidirectional

E1 Bidirectional

G3 Bidirectional

V14 Input

U14 Input

W15 Input

D5 Output

C4 Output

C7 Output

A6 Output

Active Pull-up

WE2 BS_B2 PCOE

WE3 BS_B3

PCWE

[0:3] D8, C8, A7, B8 Output

BS_A

GPL_A0 GPL_B0

OE GPL_A1 GPL_B1

GPL_A

[2:3] [2:3]

GPL_B

[2–3]

UPWAITA

GPL_A4

B6 Output

A5 Output

D7 Output

C6 Output

B5, C5 Output

C1 Bidirectional

MPC866/MPC859 Hardware Specifications, Rev. 2

82 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

UPWAITB

B1 Bidirectional

GPL_B4

GPL_A5

PORESET

RSTCONF

HRESET

SRESET

D3 Output

R2 Input

P3 Input

N4 Open-drain

P2 Open-drain

XTAL P1 Analog Output

EXTAL N1 Analog Input (3.3V only)

CLKOUT W3 Output

EXTCLK N2 Input (3.3V only)

TEXP N3 Output

ALE_A

K2 Output

MII-TXD1

CE1_A

B3 Output

MII-TXD2

CE2_A

A3 Output

MII-TXD3

WAIT_A

SOC_Split

WAIT_B

IP_A0 UTPB_Split0 MII-RXD3

IP_A1 UTPB_Split1 MII-RXD2

IP_A2 IOIS16_A

UTPB_Split2 MII-RXD1

IP_A3 UTPB_Split3 MII-RXD0

IP_A4 UTPB_Split4 MII-RXCLK

R3 Input

R4 Input

T5 Input

T4 Input

U3 Input

W2 Input

U4 Input

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 83

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

IP_A5 UTPB_Split5 MII-RXERR

IP_A6 UTPB_Split6 MII-TXERR

IP_A7 UTPB_Split7

MII-RXDV

ALE_B DSCK/AT1

IP_B[0:1] IWP[0:1] VFLS[0:1]

IP_B2 IOIS16_B AT 2

IP_B3

IWP2 VF2

U5 Input

T6 Input

T3 Input

J1 Bidirectional

Three-state

H2, J3 Bidirectional

J2 Bidirectional

Three-state

G1 Bidirectional

IP_B4

G2 Bidirectional LWP0 VF0

IP_B5

J4 Bidirectional LWP1

VF1

IP_B6 DSDI

K3 Bidirectional

Three-state

AT 0

IP_B7 PTR

H1 Bidirectional

Three-state

AT 3

OP0

L4 Bidirectional MII-TXD0

UtpClk_Split

OP1 L2 Output

OP2

L1 Bidirectional MODCK1 STS

MPC866/MPC859 Hardware Specifications, Rev. 2

84 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

OP3 MODCK2 DSDO

BADDR30 REG

BADDR[28:29] M3, M2 Output

PA 15 RXD1 RXD4

PA 14

TXD1 TXD4

PA 13 RXD2

PA 12 TXD2

PA 11 L1TXDB RXD3

M4 Bidirectional

K4 Output

L3 Input

C18 Bidirectional

D17 Bidirectional

(Optional: Open-drain)

E17 Bidirectional

F17 Bidirectional

(Optional: Open-drain)

G16 Bidirectional

(Optional: Open-drain)

PA 10

L1RXDB TXD3

PA 9 L1TXDA

RXD4

PA 8

L1RXDA TXD4

PA 7 CLK1 L1RCLKA BRGO1 TIN1

PA 6

CLK2 TOUT1

J17 Bidirectional

(Optional: Open-drain)

K18 Bidirectional

(Optional: Open-drain)

L17 Bidirectional

(Optional: Open-drain)

M19 Bidirectional

M17 Bidirectional

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 85

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

PA 5 CLK3 L1TCLKA BRGO2 TIN2

PA 4 CLK4

TOUT2

PA 3 CLK5 BRGO3 TIN3

PA 2 CLK6 TOUT3

L1RCLKB

PA 1 CLK7 BRGO4 TIN4

PA 0 CLK8

TOUT4 L1TCLKB

N18 Bidirectional

P19 Bidirectional

P17 Bidirectional

R18 Bidirectional

T19 Bidirectional

U19 Bidirectional

PB31 SPISEL REJECT1

PB30 SPICLK RSTRT2

PB29

SPIMOSI

PB28 SPIMISO BRGO4

PB27 I2CSDA BRGO1

PB26 I2CSCL

BRGO2

86 Freescale Semiconductor

C17 Bidirectional

(Optional: Open-drain)

C19 Bidirectional

(Optional: Open-drain)

E16 Bidirectional

(Optional: Open-drain)

D19 Bidirectional

(Optional: Open-drain)

E19 Bidirectional

(Optional: Open-drain)

F19 Bidirectional

(Optional: Open-drain)

MPC866/MPC859 Hardware Specifications, Rev. 2

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

PB25 RXADDR3 SMTXD1

PB24 TXADDR3 SMRXD1

PB23 TXADDR2

SDACK1 SMSYN1

PB22 TXADDR4 SDACK2 SMSYN2

PB21 SMTXD2

L1CLKOB PHSEL1

TXADDR1

PB20 SMRXD2 L1CLKOA

PHSEL0

TXADDR0

(Optional: Open-drain)

J18 Bidirectional

J16 Bidirectional

(Optional: Open-drain)

K17 Bidirectional

(Optional: Open-drain)

L19 Bidirectional

(Optional: Open-drain)

K16 Bidirectional

(Optional: Open-drain)

L16 Bidirectional

(Optional: Open-drain)

PB19 RTS1

N19 Bidirectional

(Optional: Open-drain)

L1ST1

PB18 RXADDR4

N17 Bidirectional

(Optional: Open-drain)

RTS2

L1ST2

PB17 L1RQb

P18 Bidirectional

(Optional: Open-drain)

L1ST3 RTS3 PHREQ1 RXADDR1

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 87

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

PB16 L1RQa L1ST4 RTS4 PHREQ0 RXADDR0

PB15

BRGO3 TxClav RxClav

PB14 RXADDR2 RSTRT1

PC15 DREQ0

RTS1 L1ST1 RxClav TxClav

PC14 DREQ1 RTS2

L1ST2

N16 Bidirectional

(Optional: Open-drain)

R17 Bidirectional

U18 Bidirectional

D16 Bidirectional

D18 Bidirectional

PC13 L1RQb L1ST3 RTS3

PC12 L1RQa

L1ST4 RTS4

PC11 CTS1

PC10 CD1 TGATE1

PC9 CTS2

PC8

CD2 TGATE2

E18 Bidirectional

F18 Bidirectional

J19 Bidirectional

K19 Bidirectional

L18 Bidirectional

M18 Bidirectional

MPC866/MPC859 Hardware Specifications, Rev. 2

88 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

PC7 CTS3 L1TSYNCB SDACK2

PC6 CD3 L1RSYNCB

PC5

CTS4 L1TSYNCA SDACK1

PC4 CD4 L1RSYNCA

PD15 L1TSYNCA

MII-RXD3 UTPB0

PD14 L1RSYNCA MII-RXD2 UTPB1

M16 Bidirectional

R19 Bidirectional

T18 Bidirectional

T17 Bidirectional

U17 Bidirectional

V19 Bidirectional

PD13

L1TSYNCB MII-RXD1 UTPB2

PD12 L1RSYNCB MII-MDC UTPB3

PD11

RXD3 MII-TXERR RXENB

PD10 TXD3 MII-RXD0 TXENB

V18 Bidirectional

R16 Bidirectional

T16 Bidirectional

W18 Bidirectional

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 89

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

PD9 RXD4 MII-TXD0 UTPCLK

PD8 TXD4 MII-MDC

MII-RXCLK

PD7 RTS3 MII-RXERR UTPB4

PD6 RTS4 MII-RXDV

UTPB5

PD5 REJECT2 MII-TXD3 UTPB6

PD4 REJECT3

MII-TXD2 UTPB7

V17 Bidirectional

W17 Bidirectional

T15 Bidirectional

V16 Bidirectional

U15 Bidirectional

U16 Bidirectional

PD3 REJECT4 MII-TXD1 SOC

TMS G18 Input

TDI DSDI

TCK

DSCK

TRST

TDO DSDO

MII_CRS B7 Input

MII_MDIO H18 Bidirectional

MII_TXEN V15 Output

90 Freescale Semiconductor

W16 Bidirectional

H17 Input

H16 Input

G19 Input

G17 Output

MPC866/MPC859 Hardware Specifications, Rev. 2

Mechanical Data and Ordering Information

Table 39. Pin Assignments (continued)

Name Pin Number Type

MII_COL H4 Input

VSSSYN1 V1 PLL analog VDD and

GND

VSSSYN U1 Power

VDDSYN T1 Power

GND F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10,

Power G11, G12, G13, G14, H6, H7, H8, H9, H10, H11, H12, H13, H14, J6, J7, J8, J9, J10, J11, J12, J13, J14, K6, K7, K8, K9, K10, K11, K12, K13, K14, L6, L7, L8, L9, L10, L11, L12, L13, L14, M6, M7, M8, M9, M10, M11, M12, M13, M14, N6, N7, N8, N9, N10, N11, N12, N13, N14, P6, P7, P8, P9, P10, P11, P12, P13, P14

VDDL A8, M1, W8, H19, F4, F16, P4, P16, R1 Power

VDDH E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, F5, F15, G5,

Power G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P5, P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T14

N/C D6, D13, D14, U2, V2, T2 No-connect

Classic SAR mode only

ESAR mode only

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 91

Mechanical Data and Ordering Information

15.2 Mechanical Dimensions of the PBGA Package

For more information on the printed-circuit board layout of the PBGA package, including thermal via design and suggested pad layo ut, please refe r to Plastic Ball Grid Array App lication Note (order number: AN123 1/D) availabl e from your local Freescale sales office. Figure 79 shows the mechanical dimensions of the PBGA package.

Note: Solder sphere composition for MPC866XZP, MPC859PZP, MPC859DSLZP, and MPC859TZP

is 62%Sn 36%Pb 2%Ag

Figure 79. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

MPC866/MPC859 Hardware Specifications, Rev. 2

92 Freescale Semiconductor

16 Document Revision History

Table 40 lists significant changes between revisions of this doc ument.

Table 40. Document Revision History

Document Revision History

Revision

Number

0 5/2002 Initial revision

1 11/2002 Added the 5-V tolerant pins, new package dimensions, and other changes.

1.1 4/2003 Added the Spec. B1d and changed spec. B1a. Added the Note Solder sphere

1.2 4/2003 Added the MPC859P.

1.3 5/2003 Changed the SPI Master Timing Specs. 162 and 164.

1.4 7-8/2003 • Added TxClav and RxClav to PB15 and PC15. Changed B28a through B28d and

1.5 3/14/2005 • Updated document template.

2 2/10/2006 • Updated orderable parts table.

Date Substantive Changes

composition for MPC866XZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb 2%Ag to Figure 15-79.

B29b to show that TRLX can be 0 or 1.

• Added nontechnical reformatting.

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 93

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

MPC866/MPC859 Hardware Specifications, Rev. 2

94 Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Document Revision History

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor 95

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MPC866EC Rev. 2 2/2006

Freescale MPC866, MPC859 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

MPC866/MPC859 Hardware Specifications

1Overview

2Features

Table 1. MPC866 Family Functionality

Figure 1. MPC866P Block Diagram

Figure 2. MPC859P/859T/MPC859DSL Block Diagram

3 Maximum Tolerated Ratings

Table 2. Maximum Tolerated Ratings

Table 3. Operating Temperatures

4 Thermal Characteristics

Table 4. MPC866/859 Thermal Resistance Data

5 Power Dissipation

Table 5. Power Dissipation (PD)

6 DC Characteristics

Table 6. DC Electrical Specifications

7 Thermal Calculation and Measurement

7.1 Estimation with Junction-to-Ambient Thermal Resistance

7.2 Estimation with Junction-to-Case Thermal Resistance

7.3 Estimation with Junction-to-Board Thermal Resistance

Figure 3. Effect of Board Temperature Rise on Thermal Behavior

7.4 Estimation Using Simulation

7.5 Experimental Determination

7.6 References

8 Power Supply and Power Sequencing

Figure 4. Example Voltage Sequencing Circuit

9 Layout Practices

10 Bus Signal Timing

Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Table 9. Bus Operation Timings

Figure 5. Control Timing

Figure 6. External Clock Timing

Figure 7. Synchronous Output Signals Timing

Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Output Signals Timing

Figure 9. Synchronous Input Signals Timing

Figure 10. Input Data Timing in Normal Case

Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1

Figure 19. External Bus Timing (UPM Controlled Signals)

Figure 20. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

Figure 22. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Table 10. Interrupt Timing

Figure 25. Interrupt Detection Timing for External Level Sensitive Lines

Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines

Table 11. PCMCIA Timing

Figure 27. PCMCIA Access Cycles Timing External Bus Read

Figure 28. PCMCIA Access Cycles Timing External Bus Write

Figure 29. PCMCIA WAIT Signals Detection Timing

Table 12. PCMCIA Port Timing

Figure 30. PCMCIA Output Port Timing

Figure 31. PCMCIA Input Port Timing

Table 13. Debug Port Timing

Figure 32. Debug Port Clock Input Timing

Figure 33. Debug Port Timings

Table 14. Reset Timing

11 IEEE 1149.1 Electrical Specifications

Table 15. JTAG Timing

Figure 37. JTAG Test Clock Input Timing

Figure 38. JTAG Test Access Port Timing Diagram

Figure 40. Boundary Scan (JTAG) Timing Diagram

12 CPM Electrical Characteristics

12.1 PIP/PIO AC Electrical Specifications

Table 16. PIP/PIO Timing

Figure 41. PIP Rx (Interlock Mode) Timing Diagram

Figure 42. PIP Tx (Interlock Mode) Timing Diagram

Figure 43. PIP Rx (Pulse Mode) Timing Diagram

Figure 44. PIP TX (Pulse Mode) Timing Diagram

Figure 45. Parallel I/O Data-In/Data-Out Timing Diagram

12.2 Port C Interrupt AC Electrical Specifications

Table 17. Port C Interrupt Timing

Figure 46. Port C Interrupt Detection Timing

12.3 IDMA Controller AC Electrical Specifications

Table 18. IDMA Controller Timing

Figure 47. IDMA External Requests Timing Diagram

12.4 Baud Rate Generator AC Electrical Specifications

Table 19. Baud Rate Generator Timing