Freescale MPC852T service manual
Freescale Semiconductor
Technical Data
MPC852T Hardware Specifications
MPC852TEC
Rev. 3.1, 01/20 05
This document contains detai led infor mation for the MPC852T
about power considerati ons, DC/AC electrica l characteristi cs, AC
timing specifications, and pertinent electrical and physical
characteristics of the MPC852T. For information abou t functiona l
characteristics of the processor, refer to the MPC866
PowerQUICC Family Users Manual (MPC866UM). The
MPC852T contains a PowerPC
TM
processor core.
1Overview
The MPC852T PowerQUICCTM is a 0.18-micron derivative of
the MPC860 PowerQUICC family, and can operate up to 100
MHz on the MPC8xx core with a 66-MHz external bus. The
MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V
TTL compatibility. The MPC852T integrated communications
controller is a versatile one-chip integrated microprocessor and
peripheral combination that can be used in a variety of controller
applications. It par ticularly excels in Ethernet control applications,
including CPE equip ment, Ethernet routers a nd hubs, VoIP clients,
and WiFi access points.
The MPC852T is a PowerPC arc hi tecture-based deriva tive of the
Motorola MPC860 Quad Integrated Communications Controller
(PowerQUICC). The CPU o n the MPC852 T is the MPC8xx core,
a 32-bit microprocessor that implements the PowerPC
architecture, incorporating memory management units (MMUs)
and instruction and data caches. The MPC852T is the subset of
this family o f devices.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7. Thermal Calculation and Measurement . . . . . . . . . . . 8
8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9. Power Supply and Power Sequenc in g . . . . . . . . . . . 10
10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 11
11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41
14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 56
16. Mechanical Dat a and Ordering Information . . . . . . . 60
17. Document Revision History . . . . . . . . . . . . . . . . . . . 78
Β© Freescale Semiconductor, Inc., 2004. All rights reserved.
Features
2Features
The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system
integration unit (SIU), and the communication processor module (CPM).
diagram.
The following list summarizes the key MPC852T features:
β’ Embedded MPC8xx core up to 100 MHz
β’ Maximum frequency operation of the external bus is 66 MHz
β The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes.
β The 80 MHz / 100 MHz core frequencies support 2:1 mode only.
β’ Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit
general-purpose registers (GPRs)
β The core performs branch prediction with conditional prefetch, without conditional execution.
β 4-Kbyte data cache and 4-Kbyte instr uct io n cache
β 4-Kbyte instruction cache is two-way, set-associative with 128 sets.
β 4-Kbyte data cacheis two-way, set-associative with 128 sets.
β Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
β Caches are physi cally addresse d, implement a l east recentl y used (LRU) r eplacement algo rithm, and
are lockable on a cache block basis.
β MMUs with 32-entry TLB, fully associative instruction, and data TLBs
β MMUs support multiple page siz es of 4, 16, and 51 2 Kbytes, and 8 Mbytes; 16 virtual add res s sp ace s,
and 16 protection groups
β’ Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
β’ 32 address lines
β’ Memory controller (eight banks)
β Contains complete dynamic RAM (DRAM) controller
β Each bank can be a chip select or RAS to support a DRAM bank
β Up to 30 wait states programmable per memory bank
β Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
β DRAM controller-programmable to support most size and speed memory interfaces
βFour CAS lines, four WE lines, and one OE line
β Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
β Variable block sizes (32 Kbytesβ256 Mbytes)
β Selectable write protection
β On-chip bus arbitration logic
β’ Fast Ethernet Controller (FEC)
β’ General-purpose timers
β Two 16-bit timers or one 32-bit timer
β Gate mode can enable or disable counting.
β Interrupt can be masked on reference match and event capture.
Figure 1 shows the MPC852T block
MPC852T Hardware Specifications, Rev. 3.1
2 Freescale Semiconductor
β’ System integration unit (SIU)
β Bus monitor
β Software watchdog
β Periodic interrupt timer (PIT)
β Clock synthesizer
β Decrementer and time base
β Reset controller
β IEEE 1149.1 test access port (JTAG)
β’ Interrupts
β Seven external interrupt request (IRQ) lines
β Seven port pins with interrupt capability
β Eighteen internal interrupt sources
β Programmable priority between SCCs
β Programmable highest-priority request
β’ Communications processor module (CPM)
β RISC controller
β Communication-specifi c commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT)
β Supports continuous mode transmission and reception on all serial channels
β 8-Kbytes of dual-port RAM
β 8 serial DMA (SDMA) channels
β Three parallel I/O registers with open-drain capability
β’ Two baud rate generators
β Independent (can be connected toany SCC3/4 or SMC1)
β Allows changes during operation
β Autobaud support option
β’ Two SCCs (serial communication controllers)
β Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation
β HDLC/SDLC
β HDLC bus (implements an HDLC-based local area network (LAN))
β Universal asynchronous receiver transmitter (UART)
β Totally transparent (bit streams)
β Totally transparent (frame-based with optional cyclic redundancy check (CRC))
β’ One SMC (serial management channels)
β UART
β’ One SPI (serial peripheral interface)
β Supports master and slave modes
β Supports multimaster operation on the same bus
β’ PCMCIA interface
β Master (socket) interface, release 2.1 compliant
Features
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 3
Features
β Supports one independent PCMCIA socket; 8-memory or I/O windows supported
β’ Debug interface
β Eight comparators: four operate on instructi on address, two oper ate on data address, and t wo operate on
data
β Supports conditions: = β < >
β Each watchpoint can generate a break point internally.
β’ Normal high and normal low power modes to conserve power
β’ 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V
Tolerant pins.
Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Access
Media
Control
MII
Instruction
Bus
Load/Store
Bus
2 Baud Rate
4-Kbyte
Instruction
Instruction
32-Entry ITLB
4-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Parallel I/O
Generators
Cache
MMU
Timers
Timers
Unified
Bus
2
Interrupt
Controllers
Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
System Interface Unit (SIU)
Memory Controller
8-Kbyte
Internal
Bus
Interface
Unit
System Functions
PCMCIA-ATA Interface
External
Bus Interface
1 Virtual
IDMA
8 Serial
DMA
Channels
Unit
&
SCC3 SCC4 SMC1 SPI
Serial Interface (NMSI)
Figure 1. MPC852T Block Diagram
MPC852T Hardware Specifications, Rev. 3.1
4 Freescale Semiconductor
Maximum Tolerated Ratings
3 Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1 provides
the maximum ratings and operating temperatures.
Table 1. Maximum Tolerated Ratings
Rating Symbol Value Unit
Supply voltage
Input voltage
Storage tem pe rature range T
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical specifications in Table 5.
Absolute maximum ratings are stress ratings only; functional operation at the maxima is not
guaranteed. S t r ess es beyo nd thos e lis ted may af fect device reliability or caus e perm an ent
damage to the device.
Caution: All inputs that tol erate 5 V cannot be more than 2.5 V greater than V
applies to power-up and normal operation (that is, if the MPC852T is unpowered, a voltage
greater than 2.5 V must not be applied to its inputs).
1
2
V
(core
DDL
voltage)
V
(I/O voltage) β 0.3 to 4 V
DDH
V
DDSYN
Difference
between V
V
DDSYN
to
DDL
V
in
stg
GND β 0.3 to V
β 55 to +150 Β°C
β 0.3 to 3.4 V
β 0.3 to 3.4 V
100 mV
DDH
DDH
V
. This restriction
Table 2. Operating Temperatures
Rating Symbol Value Unit
Temperature 1 (standard)
Temperature (extended) T
1
Minimum temperatures are guaranteed as ambient temperature, TA. Maximum tempera tur e s
are guaranteed as junction temperature, T
T
A(min)
T
j(max)
A(min)
T
j(max)
0 Β°C
95 Β°C
β 40 Β°C
100 Β°C
.
j
This device conta ins cir cuitry pr otecti ng against damage th at hig h-stati c voltag e or elec trical fields cause; ho wever,
Motorola recommends taking normal precautions to a voi d app li cat ion of any voltages higher th an maxi mum-r at ed
voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (for example, either GND or V
DD
). -- V
DDH.
4 Thermal Characteristics
Table 3 shows the thermal characteristics for the MPC852T.
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 5
Power Dissipation
Junction to ambient 1
Junction to board
Junction to case
Junction to package top
1
Junction temperatur e is a function of on-c hip power di ssip atio n, p ackage therma l resist anc e, moun ting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal
3
Per JEDEC JESD51-6 with the board horizontal
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5
Indicates the averag e ther mal resi stanc e between the di e and the case to p surface as measu red by th e
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature. For exposed pad packages where the pad would be expected to be so ldered, junction to
case thermal resistance is a simulated value from the junction to the exposed pad without contact
resistance.
6
Thermal character ization paramete r indicating the temperature dif ference between p ackage top a nd the
junction temperature per JEDEC JESD51-2
Table 3. MPC852T Thermal Resistance Data
Rating Environment Symbol Value Unit
Natural convection Single layer board (1s) R
Four layer board (2s2p) R
Air flow (200 ft/min) Single layer board (1s) R
Four layer board (2s2p) R
4
5
6
Natural convection Ξ¨
Air flow (200 ft/min) Ξ¨
ΞΈJA
ΞΈJMA
ΞΈJMA
ΞΈJMA
R
ΞΈJB
R
ΞΈJC
JT
JT
2
3
3
3
49 Β°C/W
32
41
29
24
13
3
2
5 Power Dissipation
Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1
mode, where CPU frequency is twice bus speed.
Table 4. Power Dissipation (PD)
Die Revision Bus Mode
1:1
0
2:1
1
Typical power dissipation is measured at 1.9 V.
MPC852T Hardware Specifications, Rev. 3.1
Frequency
(MHz)
Typical
50 110 140 mW
66 150 180 mW
66 140 160 mW
80 170 200 mW
100 210 250 mW
1
Maximum
2
Unit
6 Freescale Semiconductor
2
Maximum power dissipation at V
Values in Table 4 represent V
dissipation, and do not inc lude I/O power dissipati on
over V
DDH
application that buffer current can cause, depending
on external circuitry.
DDL
and V
is at 1.9 V. and V
DDSYN
DDH
NOTE
-based power
DDL
. I/O power dissipation varies widely by
DC Characteristics
is at 3.465 V.
The V
power dissipation is negligible.
DDSYN
6 DC Characteristics
Table 5 provides the DC electrical characteristics for the MPC852T.
Table 5. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating voltage V
Input high voltage (all inputs except
PA[0:3], PA[8:11], PB15, PB[24:25];
PB[28:31], PC[4:7], PC[12:13], PC15,
PD[3:15], TDI, TDO, TCK,
MII_TXEN, MII_MDIO)
TRST , TMS,
1
Input low voltage V
EXTAL, EXTCLK input high voltage V
Input leakage current, Vin = 5.5 V
(Except TMS,
pins) for 5-V tolerant pins
TRST , DSCK and DSDI
1
DDH
V
DDL
V
DDSYN
Difference between V
V
DDSYN
V
IH
IL
IHC
I
in
DDL
to
3.135 3.465 V
1.7 1.9 V
1.7 1.9 V
β 100 mV
2.0 3.465 V
GND 0.8 V
0.7 Γ V
DDH
V
DDH
β 100 Β΅A
V
Input leakage current, Vin = V
(Except TMS,
TRST , DSCK, and DSDI)
Input leakage curren t, Vin = 0 V (Except
TMS,
TRST, DSCK and DSDI pins)
Input capacita nc e
2
DDH
I
In
I
In
C
in
β 10 Β΅A
β 10 Β΅A
β 20 pF
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 7
Thermal Calculation and Measuremen t
Table 5. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
Output high voltage, IOH = -2.0 mA,
= 3.0 V
V
DDH
Except XTAL and open drain pins
Output low voltage
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA
IOL = 5.3 mA
IOL = 7.0 mA (Txd1/pa14, txd2/pa12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB,
HRESET, SRESET)
1
The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO,
TCK,
2
Input capacitance is periodically sampled.
3
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2,
IWP(0:1)/VFLS(0:1), RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/P A8, TIN3/BRGO3/CLK5/PA3,
BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31,
SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24,
BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6,
CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14, MII-RXD1/PD13, MII-MDC/PD12,
MII-TXERR/RXD3/PD1 1, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8,
MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4,
MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, MII_COL
4
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR,
WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK,
OP(0:1), OP2/MODCK1/
3
4
TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant pins.
STS, OP3/MODCK2/DSDO, BADDR(28:30)
VOH 2.4 β V
VOL β 0.5 V
7 Thermal Calculation and Measurement
For the following discussions, PD= (V
The V
power dissipation is negligible.
DDSYN
7.1 Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, in Β°C can be obtained from the equation:
TJ = TA +(R
where:
TA = ambient temperature ΒΊC
R
PD = power dissipation in package
8 Freescale Semiconductor
x PD)
ΞΈJA
= package j unction-to-ambient thermal resistance (ΒΊC/W)
ΞΈJA
x IDDL) + P
DDL
, where P
I/O
is the power dissipation of the I/O drivers.
I/O
NOTE
MPC852T Hardware Specifications, Rev. 3.1
Thermal Calculation and Measurement
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation
of thermal performa nce. However , the answer is o nly an estimate; tes t cases have demonstra ted that errors of a factor
of two (in the quantity T
) are possible.
J-TA
7.2 Estimation with Junction-to-Case Thermal Resistance
Historically , the ther mal resistance has freque ntly been expressed as the sum of a junction-to-case the rmal resistance
and a case-to-ambient thermal resistance:
R
= R
ΞΈJA
where:
R
is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the
ΞΈJC
case-to-am bient thermal resistance, R
heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the
printed circuit boar d surrounding the device. Thi s thermal model is most usefu l for ceramic packages wit h heat sinks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.
+ R
R
R
R
ΞΈJC
ΞΈJA
ΞΈJC
ΞΈCA
ΞΈCA
= junction-to-ambient thermal resistance (ΒΊC/W)
= junction-to-case thermal resistance (ΒΊC/W)
= case-to-ambient thermal resista nce (ΒΊC/W)
. For instance, the user can change the air flow around the device, add a
ΞΈCA
7.3 Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model
consisting of a junction-to-boa rd and a ju nction-to-case t hermal resist ance. The juncti on-to-case co vers the sit uation
where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the
printed circuit board. Thermal performance of most plastic packages and especially PBGA packages is strongly
dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in
the environment can be made using the following equation:
TJ = TB +(R
ΞΈJB
x PD)
where:
R
= junction-to-board thermal resistance (ΒΊC/W)
ΞΈJB
TB = board temperature ΒΊC
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and vias attaching the thermal balls to the ground plane.
7.4 Estimation Using Simulation
When the board temperatur e is not known, a therma l simulation of the appl ication is needed . The simple two-resistor
model can be used with the therma l simula tion of t he app licat ion [2] , or a more ac curat e and comple x model of the
package can be used in the thermal simulation.
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 9
References
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (Ξ¨
) can be used to determine the junction temperature with a measurement of the
JT
temperature at the top center of the package case using the following equation:
TJ = TT +(Ξ¨JT x PD)
where:
Ξ¨
= thermal c haracteriz ation parameter
JT
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a
40-gauge type T the rmocouple epoxied to the top center of the package case. The th ermocouple should be p ositioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire ex tending f rom the junc tion. The ther mocouple wire is pl aced flat a gainst th e
package case to avoid measurement errors that cooling effects of the thermocouple wire cause.
8 References
Semiconductor Equipment and Materials International(415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or
(Available from Global Engineering documents)303-397-7956
JEDEC Specifications http://www.jedec.org
1. C.E. Triplett and B. Joiner, βAn Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,β Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, βMeasurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,β Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
9 Power Supply and Power Sequencing
This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage
(V
) and PLL voltage (V
DDL
DDSYN
the MPC852T is supplied with 3.3 V across V
The signal PA[0:3], P A[8: 11], PB15, PB[ 24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK,
TRST , TMS, MII_TXEN, MII _MDIO are 5 V-tolerant. All inpu ts cannot be more than 2. 5 V greater tha n V
addition, 5 V-tolerant pins can not exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This restriction
applies to power-on reset or power down and normal operation.
) that operates at a lower voltage than the I/O voltage V
and VSS (GND).
DDH
. The I/O section of
DDH
DDH
. In
MPC852T Hardware Specifications, Rev. 3.1
10 Freescale Semiconductor
Mandatory Reset Configurations
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at
different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the
manner in which different voltages are derived. The following restrictions apply:
β’V
β’V
must not exceed V
DDL
must not exceed 1.9 V, and V
DDL
DDH
during power-on reset or power down.
must not exceed 3.465.
DDH
These cautions are nece ssary for th e long-t erm reliab ility of th e part. If the y are violat ed, the elect rostati c discha rge
(ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system
power supply design does not control the voltage sequencing, the circuit shown in
Figure 2 can be added to meet
these requirements. The MUR420 Schot tky diode s con tr ol the maximum potential difference between the ext ern al
bus and core power su ppl ies on power-on reset , an d t he 1N5820 diodes regulate the maximum potential d ifference
on power-down.
V
DDH
MUR420
1N5820
Figure 2. Example Voltage Sequencing Circuit
V
DDL
10 Mandatory Reset Configurations
The MPC852T requires a mandatory configuration during reset.
If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET assertion,
the HRCW[D BGC] value that is needed to be set to binary X1 in the hardware reset configurati on word (HRCW )
and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset.
If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET
assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset.
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 11
Layout Practices
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the
mandatory value in
Table 6 in the boot code after the reset deasserts.
Table 6. Mandatory Reset Configuration of MPC852T
Register/Configuration Field
HRCW
(Hardware reset configuration word)
SIUMCR
(SIU module configuration register)
MBMR
(Machine B mode register)
PAPAR
(Port A pin assignment register)
PADIR
(Port A Data Direction Register)
PBPAR
(Port B Pin Assignment Register)
PBDIR
(Port B Data Direction Register)
PCPAR
(Port C Pin Assignment Register)
HRCW[DBGC] X1
SIUMCR[DBGC] X1
MBMR[GPLB4DIS} 0
PAPAR[4-7]
PAPAR[12-15]
PADIR[4-7]
PADIR[12-15]
PBPAR[14]
PBPAR[16-23]
PBPAR[26-27]
PBDIR[14]
PBDIR[16-23]
PBDIR[26-27]
PCPAR[8-11]
PCDIR[14]
Value
(binary)
0
1
0
1
0
PCDIR
(Port C Data Direction Register)
PCDIR[8-11]
PCDIR[14]
1
11 Layout Practices
Each VDD pin on the MPC852T should be provided with a low-impedance path to the boardβs supply. Each GND
pin should likewise be provid ed with a low-impe dance path to gr ound. The power suppl y pins drive di stinct gro ups
of logic on chip. The V
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropr iate decoupling cap aci tors should be u sed i f required. The capac it or l eads and associated printed
circuit traces connect ing to chip V
minimum, a four-layer board employing two inner layers as V
All output pins on the MPC852T have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized to minimize undershoot and reflections that these fast output switching times cause. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the
PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads, because these loads create hi gher transient current s in the V
inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL
power supply should be bypass ed to gr ound usi ng at l east f our 0.1 Β΅F by-pass capac itors
DD
and GND should be kept to less than half an inch per capacitor lead. At a
DD
and GND planes should be used.
DD
and GND circuits. Pull up all unused
DD
MPC852T Hardware Specifications, Rev. 3.1
12 Freescale Semiconductor
Bus Signal Timing
supply pins. For more information, please refer to MPC866 Userβs Manual, Section 14.4.3, βClock Synthesizer
Power (V
DDSYN
, V
SSSYN
, V
SSSYN1
).β
12 Bus Signal Timing
The maximum bus speed that the MPC852T supports is 66 MHz. Table 7 shows the frequency ranges for standard
part frequencies.
Table 7. Frequency Ranges for Standa rd Part Frequencies (1:1 Bus Mode)
Part
Freq
Core
Freq
Bus Freq 40 50 40 66.67
50MHz 66MHz
Min Max Min Max
40 50 40 66.67
Table 8. Frequency Ranges for Standa rd Part Frequencies (2:1 Bus Mode)
Part
Freq
Core
Freq
Bus Freq
2:1
50MHz 66MHz 80MHz 100MHz
Min Max Min Max Min Max Min Max
40 50 40 66.67 40 80 40 100
20 25 20 33.33 20 40 20 50
Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50 and 66 MHz.
The timing for the MPC852T bus shown as sumes a 50-p F loa d for maximum del ays and a 0- pF loa d for mini mu m
delays. CLKOUT assumes a 100-pF load maximum delay
Table 9. Bus Operation Timings
33 MHz 40 MHz 50 MHz 66 MHz
Num Characteristic
Min Max Min Max Min Max Min Max
B1 Bus period (CLKOUT) See Table 7 β β β β β β β β ns
B1a EXTCL K to CLKOUT phase skew - If CLKOUT
is an integer multiple of EXTCLK, then the
rising edge of EXTCLK is aligned with the
rising edge of CLKOUT. For a non-integer
multiple of EXTCLK, this synchronization is
lost, and the rising edges of EXTCLK and
CLKOUT have a continuously varying phase
skew.
B1b CLKOUT frequency jitter peak-to-peak β 1 β 1 β 1 β 1 ns
B1c Frequency jitter on EXTCLK
Freescale Semiconduc tor 13
1
MPC852T Hardware Specifications, Rev. 3.1
-2 +2 -2 +2 -2 +2 -2 +2 ns
β 0.50 β 0.50 β 0.50 β 0.50 %
Unit
Bus Signal Timing
Num Characteristic
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B1d CLKOUT phase jitter peak-to-peak
for OSCLK β₯ 15 MHz
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
B2 CLKOUT pulse width low (MIN = 0.4 x B1, MAX
= 0.6 x B1)
B3 CLKOUT pulse width high (MIN = 0.4 x B1,
MAX = 0.6 x B1)
B4 CLKOUT rise time β 4.00 β 4.00 β 4.00 β 4.00 ns
B5 CLKOUT fall time β 4.00 β 4.00 β 4.00 β 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3) output hold (MIN =
0.25 x B1)
B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR
output hold (MIN = 0.25 x B1)
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2)
IWP(0:2), LWP(0:1),
0.25 x B1)
B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR,
BURST, D(0:31), DP(0:3) valid (MAX = 0.25 x
B1 + 6.3)
STS output hold (MIN =
β 4 β 4 β 4 β 4 ns
β 5 β 5 β 5 β 5 ns
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
7.60 β 6.30 β 5.00 β 3.80 β ns
7.60 β 6.30 β 5.00 β 3.80 β ns
7.60 β 6.30 β 5.00 β 3.80 β ns
β 13.80 β 12.50 β 11.30 β 10.00 ns
B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR
valid (MAX = 0.25 x B1 + 6.3)
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
IWP(0:2), FRZ, LWP(0:1),
0.25 x B1 + 6.3)
B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3), TSIZ(0:1), REG,
RSV, PTR High-Z (MAX = 0.25 x B1 + 6.3)
B11 CLKOUT to TS, BB assertion (MAX = 0.25 x B1
+ 6.0)
B11a CLKOUT to TA, BI assertion (when driven by
the memory controller or PCMCIA interface)
(MAX = 0.00 x B1 + 9.30 2)
B12 CLKOUT to TS, BB negation (MAX = 0.25 x B1
+ 4.8)
B12a CLKOUT to TA, BI negation (when driven by
the memory controller or PCMCIA interface)
(MAX = 0.00 x B1 + 9.00)
B13 CLKOUT to TS, BB High-Z (MIN = 0.25 x B1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns
STS Valid 3 (MAX =
MPC852T Hardware Specifications, Rev. 3.1
β 13.80 β 12.50 β 11.30 β 10.00 ns
β 13.80 β 12.50 β 11.30 β 10.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns
2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns
7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
14 Freescale Semiconductor
Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B13a CLKOUT to TA, BI High-Z (when driven by t he
memory controller or PCMCIA interface) (MIN
= 0.00 x B1 + 2.5)
B14 CLKOUT to TEA a ssertion (MAX = 0.00 x B1 +
9.00)
B15 CLKOUT to TEA High-Z (MIN = 0.00 x B1 +
2.50)
B16 TA, BI valid to CLKOUT (setup time) (MIN =
0.00 x B1 + 6.00)
B16a TEA, KR, RETRY, CR valid to CLKOUT (setup
time) (MIN = 0.00 x B1 + 4.5)
B16b BB, BG, BR, valid to CLKOUT (setup time) 3
(4MIN = 0.00 x B1 +.000)
B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid
(hold time ) (MIN = 0.00 x B1 + 1.00 4)
B17a CLKOUT to KR, RETRY, CR valid (hold time)
(MIN = 0.00 x B1 + 2.00)
B18 D(0:31), DP(0:3) valid to CLKOUT ris in g ed ge
(setup time) 5 (MIN = 0.00 x B1 + 6.00)
B19 CLKO UT ri si ng e dge to D (0: 31), DP(0:3) valid
(hold time) 5 (MIN = 0.00 x B1 + 1.00 6)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
6.00 β 6.00 β 6.00 β 6.00 β ns
4.50 β 4.50 β 4.50 β 4.50 β ns
4.00 β 4.00 β 4.00 β 4.00 β ns
1.00 β 1.00 β 1.00 β 2.00 β ns
2.00 β 2.00 β 2.00 β 2.00 β ns
6.00 β 6.00 β 6.00 β 6.00 β ns
1.00 β 1.00 β 1.00 β 2.00 β ns
B20 D( 0:31), DP (0:3) valid t o CLKOUT falling edge
(setup time) 7(MIN = 0.00 x B1 + 4.00)
B21 CLKO UT fallin g edge to D(0:31), DP(0:3) vali d
(hold Time)
7
(MIN = 0.00 x B1 + 2.00)
B22 CLKOUT rising edge to CS asserted GPCM
ACS = 00 (MAX = 0.25 x B1 + 6.3)
B22a CLKOUT falling edge to CS asserted GPCM
ACS = 10, TRLX = 0 ( MAX = 0 .00 x B1 + 8.00)
B22b CLKOUT falling edge to CS asserted GPCM
ACS = 1 1, TRLX = 0, EBDF = 0 (MA X = 0.2 5 x
B1 + 6.3)
B22c CLKOUT falling edge to CS asserted GPCM
ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375
x B1 + 6.6)
B23 CLKOUT rising edge to CS negated GPCM
read access, GPCM write access ACS = 00,
TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 +
8.00)
MPC852T Hardware Specifications, Rev. 3.1
4.00 β 4.00 β 4.00 β 4.00 β ns
2.00 β 2.00 β 2.00 β 2.00 β ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
β 8.00 β 8.00 β 8.00 β 8.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
Freescale Semiconduc tor 15
Bus Signal Timing
Num Characteristic
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B24 A(0 :31) and BADDR(28:30) to CS asserted
GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1
- 2.00)
B24a A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 -
2.00)
B25 CLKOUT rising edge to OE,
WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 x B1
+ 9.00)
B26 CLKOUT rising edge to OE negated (MAX =
0.00 x B1 + 9.00)
B27 A(0 :31) and BADDR(28:30) to CS asserted
GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1
- 2.00)
B27a A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 1 1 , TRLX = 1 (MI N = 1.50 x B1 -
2.00)
B28 CLKOUT rising edge to WE(0:3)/BS_B[0:3]
negated GPCM write access CSNT = 0 (MAX
= 0.00 x B1 + 9.00)
B28a CLKOUT falling edge to WE(0:3)/BS_B[0:3]
negated GPCM write access TRLX = 0,1
CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80)
5.60 β 4.30 β 3.00 β 1.80 β ns
13.20 β 10.50 β 8.00 β 5.60 β ns
β 9.00 9.00 9.00 9.00 ns
2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
35.90 β 29.30 β 23.00 β 16.90 β ns
43.50 β 35.50 β 28.00 β 20.70 β ns
β 9.00 β 9.00 β 9.00 β 9.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B28b CLKOUT falling edge to CS negated GPCM
write access TRLX = 0,1 CSNT = 1 ACS = 10
or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 +
6.80)
B28c CLKOUT falling edge to WE(0:3)/BS_B[0:3]
negated GPCM write access TRLX = 0,1
CSNT = 1 write access TRLX = 0,1 CSNT = 1,
EBDF = 1 (MAX = 0.375 x B1 + 6.6)
B28d CLKOUT falling edge to CS negated GPCM
write access TRLX = 0,1 CSNT = 1, ACS = 10,
or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 +
6.6)
B29 WE(0:3)/BS_B[0:3] ne gated to D(0 :31),
DP(0:3) High-Z GPCM write access, CSNT =
0, EBDF = 0 (MIN = 0.25 x B1 - 2.00)
B29a WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access, TRL X = 0,
CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00)
MPC852T Hardware Specifications, Rev. 3.1
β 14.30 β 13.00 β 11.80 β 10.50 ns
10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns
β 18.00 β 18.00 β 14.30 β 12.30 ns
5.60 β 4.30 β 3.00 β 1.80 β ns
13.20 β 10.50 β 8.00 β 5.60 β ns
16 Freescale Semiconductor
Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B29b CS negated to D(0:31), DP(0:3), High Z GPCM
write access, ACS = 00, TRLX = 0,1 & CSNT =
0 (MIN = 0.25 x B1 - 2.00)
B29c CS negated to D(0:31), DP(0: 3) High-Z GPCM
write access, T RLX = 0, CSNT = 1, ACS = 10,
or ACS = 1 1 EBDF = 0 (MIN = 0.5 0 x B1 - 2. 00)
B29d WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access, TRL X = 1,
CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00)
B29e CS negated to D(0:31), DP(0:3) High-Z G PCM
write access, T RLX = 1, CSNT = 1, ACS = 10,
or ACS = 1 1 EBDF = 0 (MIN = 1.5 0 x B1 - 2. 00)
B29f WE(0:3/BS_B[0:3]) negated to D(0:31),
DP(0:3) High Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1 (MIN = 0.375 x B 1 - 6. 30)
B29g CS negated to D(0:31), DP(0:3) High-Z G PCM
write access, TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30)
B29h WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1 (MIN = 0.375 x B 1 - 3. 30)
B29i CS negated to D(0:31 ), DP(0:3) High-Z GPC M
write access, TRLX = 1, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 -
3.30)
5.60 β 4.30 β 3.00 β 1.80 β ns
13.20 β 10.50 β 8.00 β 5.60 β ns
43.50 β 35.50 β 28.00 β 20.70 β ns
43.50 β 35.50 β 28.00 β 20.70 β ns
5.00 β 3.00 β 1.10 β 0.00 β ns
5.00 β 3.00 β 1.10 β 0.00 β ns
38.40 β 31.10 β 24.20 β 17.50 β ns
38.40 β 31.10 β 24.20 β 17.50 β ns
B30 CS, WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) Invalid GPCM write access 8
(MIN = 0.25 x B1 - 2.00)
B30a WE(0:3)/BS_B[0:3] negated to A( 0:31),
BADDR(28:30) Invalid GPCM, write access,
TRLX = 0, CSN T = 1,
invalid GPCM write access TRLX = 0, CSNT
=1 ACS = 10, or ACS == 1 1, EBDF = 0 (MI N =
0.50 x B1 - 2.00)
B30b WE(0:3)/BS_B[0:3] negated to A( 0:31) Invalid
GPCM BADDR(28:30) invalid GPCM write
access, TR LX = 1, CSNT = 1. CS negated to
A(0:31) Invalid GPCM w rite ac ces s TRLX = 1,
CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0
(MIN = 1.50 x B1 - 2.00)
Freescale Semiconduc tor 17
CS negated to A(0:31)
MPC852T Hardware Specifications, Rev. 3.1
5.60 β 4.30 β 3.00 β 1.80 β ns
13.20 β 10.50 β 8.00 β 5.60 β ns
43.50 β 35.50 β 28.00 β 20.70 β ns
Bus Signal Timing
Num Characteristic
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B30c WE(0:3)/BS_B[0:3 ] negated to A(0:31),
BADDR(28:30) invalid GPCM write access,
TRLX = 0, CSN T = 1. CS negated to A(0:31)
invalid GPCM write access, TRLX = 0, CSNT =
1 ACS = 10, ACS == 11, EBDF = 1 (MIN =
0.375 x B1 - 3.00)
B30d WE(0:3)/BS_B[0:3] negated to A( 0:31),
BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to A(0:31)
invalid GPCM write access TRLX = 1, CSNT =
1, ACS = 10 or 11, EBDF = 1
B31 CLKOUT falling edge to CS valid - as
requested by control bit CST4 in the
corresponding word in the UPM (MAX = 0.00 X
B1 + 6.00)
B31a CLKOUT falling edge to CS valid - as
requested by control bit CST1 in the
corresponding word in the UPM (MAX = 0.25 x
B1 + 6.80)
B31b CLKOUT rising edge to CS valid - as requested
by control bit CST2 in the corre sp ond ing word
in the UPM (M AX = 0.00 x B1 + 8.00)
B31c CLKOUT rising edge to CS valid- as requ ested
by control bit CST3 in the corre sp ond ing word
in the UPM (M AX = 0.25 x B1 + 6.30)
8.40 β 6.40 β 4.50 β 2.70 β ns
38.67 β 31.38 β 24.50 β 17.83 β ns
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B31d CLKOUT falling edge to CS valid, as requested
by control bit CST1 in the corre sp ond ing word
in the UPM EBDF = 1 (MAX = 0 .375 x B1 + 6.6)
B32 CLKO UT falling edge to BS valid- as requested
by control bit BST4 in the corresponding word
in the UPM (M AX = 0.00 x B1 + 6.00)
B32a CLKOUT falling edge to BS valid - as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 x B1 + 6.80)
B32b CLKOUT rising edge to BS valid - as reque sted
by control bit BST2 in the corresponding word
in the UPM (M AX = 0.00 x B1 + 8.00)
B32c CLKOUT rising edge to BS valid - as requested
by control bit BST3 in the corresponding word
in the UPM (M AX = 0.25 x B1 + 6.80)
MPC852T Hardware Specifications, Rev. 3.1
18 Freescale Semiconductor
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B32d CLKOUT falling edge to BS valid- as requested
by control bit BST1 in the corresponding word
in the UPM, EBDF = 1 (MAX = 0.375 x B1 +
6.60)
B33 CLKOUT falling edge to GPL valid - as
requested by control bit GxT4 in t he
corresponding word in the UPM (MAX = 0.00 x
B1 + 6.00)
B33a CLKOUT rising edge to GPL Valid - as
requested by control bit GxT3 in t he
corresponding word in the UPM (MAX = 0.25 x
B1 + 6.80)
B34 A(0:31), BADDR(28:30), and D(0:31) to CS
valid - as requested by control bit CST4 in the
corresponding word i n the UP M ( MIN = 0.25 x
B1 - 2.00)
B34a A(0:31), BADDR(28:30), and D(0:31) to CS
valid - as requested by control bit CST1 in the
corresponding word i n the UP M ( MIN = 0.50 x
B1 - 2.00)
B34b A(0:31), BADDR(28:30), and D(0:31) to CS
valid - as requested by CST2 in the
corresponding word in UPM (MIN = 0.75 x B1 -
2.00)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
5.60 β 4.30 β 3.00 β 1.80 β ns
13.20 β 10.50 β 8.00 β 5.60 β ns
20.70 β 16.70 β 13.00 β 9.40 β ns
B35 A(0:31), BADDR(28:30) to CS valid - as
requested by control bit BST4 in the
corresponding word i n the UP M ( MIN = 0.25 x
B1 - 2.00)
B35a A(0:31), BADDR(28:30), and D(0:31) to BS
valid - As Requested by BST1 in the
corresponding word i n the UP M ( MIN = 0.50 x
B1 - 2.00)
B35b A(0:31), BADDR(28:30), and D(0:31) to BS
valid - as requested by control bit BST2 in the
corresponding word i n the UP M ( MIN = 0.75 x
B1 - 2.00)
B36 A(0:31), BADDR(28:30), and D(0:31) to GPL
valid as requested by control bit GxT4 in the
corresponding word i n the UP M ( MIN = 0.25 x
B1 - 2.00)
B37 UP W AIT valid to CLKOUT fal ling ed ge 9 (MIN
= 0.00 x B1 + 6.00)
B38 CLKOUT falling edge to UPWAIT valid 9 (MIN
= 0.00 x B1 + 1.00)
MPC852T Hardware Specifications, Rev. 3.1
5.60 β 4.30 β 3.00 β 1.80 β ns
13.20 β 10.50 β 8.00 β 5.60 β ns
20.70 β 16.70 β 13.00 β 9.40 β ns
5.60 β 4.30 β 3.00 β 1.80 β ns
6.00 β 6.00 β 6.00 β 6.00 β ns
1.00 β 1.00 β 1.00 β 1.00 β ns
Freescale Semiconduc tor 19
Bus Signal Timing
Num Characteristic
B39 AS va lid to CLKOUT rising edge
x B1 + 7.00)
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Min Max Min Max Min Max Min Max
10
(MIN = 0.00
7.00 β 7.00 β 7.00 β 7.00 β ns
Unit
B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to
7.00 β 7.00 β 7.00 β 7.00 β ns
CLKOUT rising edge (MIN = 0.00 x B1 + 7.00)
B41 TS valid to CLKOUT rising edge (setup time)
7.00 β 7.00 β 7.00 β 7.00 β ns
(MIN = 0.00 x B1 + 7.00)
B42 CLKOUT rising edge to TS valid (hold time)
2.00 β 2.00 β 2.00 β 2.00 β ns
(MIN = 0.00 x B1 + 2.00)
B43 AS negation to memory controller signals
β TBD β TBD β TBD β TBD ns
negation (MAX = TBD)
1
If the rate of chan ge of the frequency of EXTAL is slow (that is, it do es no t j um p b etw e en the m ini mu m and maximum va lu es
in one cycle) or the frequ ency of the jitter is fast (tha t is, it does not sta y at an extreme value for a lon g time), then the maximum
allowed jitter on EXTAL can be up to 2%.
2
For part speeds above 50MHz, use 9.80ns for B11a.
3
The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for
BG input is relevant when the MPC852T is selected to work with external bus arbiter.
4
For part speeds above 50MHz, use 2ns for B17.
5
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is
asserted.
6
For part speeds above 50MHz, use 2ns for B19.
7
The D(0:31) and DP(0: 3) inpu t timin gs B20 and B21 refer to t he fall ing ed ge of th e CLKOUT. This timing is vali d only for read
accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
8
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37
and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.
10
The AS signal is considere d asynchronous to the CLKOUT. The timing B39 is speci fied in order to allow the behavior spe cified
in Figure 21.
MPC852T Hardware Specifications, Rev. 3.1
20 Freescale Semiconductor
Figure 3 is the control timing diagram.
Bus Signal Timing
CLKOUT
Outputs
Outputs
Inputs
Inputs
2.0 V
B
2.0 V
0.8 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
C
2.0 V
0.8 V
0.8 V
A
D
2.0 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
A Maximum output delay specification
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
Figure 3. Control Timing
Figure 4 provides the timing for the external clock.
CLKOUT
B1
B1
B4
Figure 4. External Clock Timing
B3
B2
B5
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 21
Bus Signal Timing
Figure 5 provides the timing for the synchronous output signals.
CLKOUT
B8
B7 B9
Output
Signals
B8a
Output
Signals
B8b
B7b
Output
Signals
B9B7a
Figure 5. Synchronous Output Signals Timing
Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B12B11
TS
, BB
B13a
B11a B12a
TA, BI
B14
B15
TEA
Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
MPC852T Hardware Specifications, Rev. 3.1
22 Freescale Semiconductor
Figure 7 provides the timing for the synchronous input signals.
CLKOUT
B16
, BI
TA
B16a
TEA, KR,
RETRY, CR
B16b
BB, BG, BR
Bus Signal Timing
B17
B17a
B17
Figure 7. Synchronous Input Signals Timing
Figure 8 provides normal case ti ming for in put dat a. It also appl ies t o normal r ead acc ess es under the con trol o f the
UPM in the memory controller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31],
DP[0:3]
Figure 8. Input Data Timing in Normal Case
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconduc tor 23
Bus Signal Timing
Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 9. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 10 through Figure 13 provide the timing for the external bus read that various GPCM factors control.
CLKOUT
TS
A[0:31]
CSx
OE
WE[0:3]
D[0:31],
DP[0:3]
B11 B12
B8
B22
B25
B28
B23
B26
B19
B18
Figure 10. External Bus Read Timing (GPCM ControlledβACS = 00)
MPC852T Hardware Specifications, Rev. 3.1
24 Freescale Semiconductor
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