Freescale MPC852T service manual

Freescale Semiconductor

Technical Data

MPC852T Hardware Specifications

MPC852TEC

Rev. 3.1, 01/20 05

This document contains detai led infor mation for the MPC852T about power considerati ons, DC/AC electrica l characteristi cs, AC timing specifications, and pertinent electrical and physical characteristics of the MPC852T. For information abou t functiona l characteristics of the processor, refer to the MPC866 PowerQUICC Family Users Manual (MPC866UM). The MPC852T contains a PowerPC

processor core.

1Overview

The MPC852T PowerQUICCTM is a 0.18-micron derivative of the MPC860 PowerQUICC family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It par ticularly excels in Ethernet control applications, including CPE equip ment, Ethernet routers a nd hubs, VoIP clients, and WiFi access points.

The MPC852T is a PowerPC arc hi tecture-based deriva tive of the Motorola MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU o n the MPC852 T is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC852T is the subset of this family o f devices.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7. Thermal Calculation and Measurement . . . . . . . . . . . 8

8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

9. Power Supply and Power Sequenc in g . . . . . . . . . . . 10

10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 11

11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

12. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13

13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41

14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43

15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 56

16. Mechanical Dat a and Ordering Information . . . . . . . 60

17. Document Revision History . . . . . . . . . . . . . . . . . . . 78

Features

2Features

The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). diagram.

The following list summarizes the key MPC852T features:

• Embedded MPC8xx core up to 100 MHz

• Maximum frequency operation of the external bus is 66 MHz — The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes. — The 80 MHz / 100 MHz core frequencies support 2:1 mode only.

• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch, without conditional execution. — 4-Kbyte data cache and 4-Kbyte instr uct io n cache

– 4-Kbyte instruction cache is two-way, set-associative with 128 sets. – 4-Kbyte data cacheis two-way, set-associative with 128 sets. – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

– Caches are physi cally addresse d, implement a l east recentl y used (LRU) r eplacement algo rithm, and

are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction, and data TLBs — MMUs support multiple page siz es of 4, 16, and 51 2 Kbytes, and 8 Mbytes; 16 virtual add res s sp ace s,

and 16 protection groups

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• 32 address lines

• Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller-programmable to support most size and speed memory interfaces —Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbytes–256 Mbytes) — Selectable write protection — On-chip bus arbitration logic

• Fast Ethernet Controller (FEC)

• General-purpose timers — Two 16-bit timers or one 32-bit timer — Gate mode can enable or disable counting. — Interrupt can be masked on reference match and event capture.

Figure 1 shows the MPC852T block

MPC852T Hardware Specifications, Rev. 3.1

2 Freescale Semiconductor

• System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Clock synthesizer — Decrementer and time base — Reset controller — IEEE 1149.1 test access port (JTAG)

• Interrupts — Seven external interrupt request (IRQ) lines — Seven port pins with interrupt capability — Eighteen internal interrupt sources — Programmable priority between SCCs — Programmable highest-priority request

• Communications processor module (CPM) — RISC controller — Communication-specifi c commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — 8 serial DMA (SDMA) channels — Three parallel I/O registers with open-drain capability

• Two baud rate generators — Independent (can be connected toany SCC3/4 or SMC1) — Allows changes during operation — Autobaud support option

• Two SCCs (serial communication controllers) — Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Universal asynchronous receiver transmitter (UART) — Totally transparent (bit streams) — Totally transparent (frame-based with optional cyclic redundancy check (CRC))

• One SMC (serial management channels) — UART

• One SPI (serial peripheral interface) — Supports master and slave modes — Supports multimaster operation on the same bus

• PCMCIA interface — Master (socket) interface, release 2.1 compliant

Features

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 3

Features

— Supports one independent PCMCIA socket; 8-memory or I/O windows supported

• Debug interface — Eight comparators: four operate on instructi on address, two oper ate on data address, and t wo operate on

data — Supports conditions: = ≠ < > — Each watchpoint can generate a break point internally.

• Normal high and normal low power modes to conserve power

• 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V Tolerant pins.

Embedded

MPC8xx

Processor

Core

Fast Ethernet

Controller

DMAs

FIFOs

10/100 Base-T

Access

Media

Control

MII

Instruction

Bus

Load/Store

Bus

2 Baud Rate

4-Kbyte

Instruction

32-Entry ITLB

4-Kbyte

Data Cache

Data MMU

32-Entry DTLB

Parallel I/O

Generators

Cache

MMU

Timers

Unified

Bus

Interrupt

Controllers

Dual-Port RAM

32-Bit RISC Controller

and Program

ROM

System Interface Unit (SIU)

Memory Controller

8-Kbyte

Internal

Bus

Interface

Unit System Functions

PCMCIA-ATA Interface

External

Bus Interface

1 Virtual

IDMA

8 Serial

DMA

Channels

Unit

SCC3 SCC4 SMC1 SPI

Serial Interface (NMSI)

Figure 1. MPC852T Block Diagram

MPC852T Hardware Specifications, Rev. 3.1

4 Freescale Semiconductor

Maximum Tolerated Ratings

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1 provides the maximum ratings and operating temperatures.

Table 1. Maximum Tolerated Ratings

Rating Symbol Value Unit

Supply voltage

Input voltage Storage tem pe rature range T

The power supply of the device must start its ramp from 0.0 V.

Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. S t r ess es beyo nd thos e lis ted may af fect device reliability or caus e perm an ent damage to the device. Caution: All inputs that tol erate 5 V cannot be more than 2.5 V greater than V applies to power-up and normal operation (that is, if the MPC852T is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).

(core

DDL

voltage) V

(I/O voltage) – 0.3 to 4 V

DDH

DDSYN

Difference between V V

DDSYN

DDL

stg

GND – 0.3 to V – 55 to +150 °C

– 0.3 to 3.4 V

100 mV

DDH

. This restriction

Table 2. Operating Temperatures

Rating Symbol Value Unit

Temperature 1 (standard)

Temperature (extended) T

Minimum temperatures are guaranteed as ambient temperature, TA. Maximum tempera tur e s are guaranteed as junction temperature, T

A(min)

j(max)

A(min)

j(max)

0 °C

95 °C

– 40 °C

100 °C

This device conta ins cir cuitry pr otecti ng against damage th at hig h-stati c voltag e or elec trical fields cause; ho wever, Motorola recommends taking normal precautions to a voi d app li cat ion of any voltages higher th an maxi mum-r at ed voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V

). -- V

DDH.

4 Thermal Characteristics

Table 3 shows the thermal characteristics for the MPC852T.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 5

Power Dissipation

Junction to ambient 1

Junction to board Junction to case Junction to package top

Junction temperatur e is a function of on-c hip power di ssip atio n, p ackage therma l resist anc e, moun ting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal

Per JEDEC JESD51-6 with the board horizontal

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

Indicates the averag e ther mal resi stanc e between the di e and the case to p surface as measu red by th e cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be so ldered, junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance.

Thermal character ization paramete r indicating the temperature dif ference between p ackage top a nd the junction temperature per JEDEC JESD51-2

Table 3. MPC852T Thermal Resistance Data

Rating Environment Symbol Value Unit

Natural convection Single layer board (1s) R

Four layer board (2s2p) R

Air flow (200 ft/min) Single layer board (1s) R

Four layer board (2s2p) R

Natural convection Ψ Air flow (200 ft/min) Ψ

θJA

θJMA

θJB

θJC

49 °C/W 32 41 29 24 13

3 2

5 Power Dissipation

Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1

mode, where CPU frequency is twice bus speed.

Table 4. Power Dissipation (PD)

Die Revision Bus Mode

1:1

2:1

Typical power dissipation is measured at 1.9 V.

MPC852T Hardware Specifications, Rev. 3.1

Frequency

(MHz)

Typical

50 110 140 mW 66 150 180 mW 66 140 160 mW 80 170 200 mW

100 210 250 mW

Maximum

Unit

6 Freescale Semiconductor

Maximum power dissipation at V

Values in Table 4 represent V dissipation, and do not inc lude I/O power dissipati on over V

DDH

application that buffer current can cause, depending on external circuitry.

DDL

and V

is at 1.9 V. and V

DDSYN

DDH

NOTE

-based power

DDL

. I/O power dissipation varies widely by

DC Characteristics

is at 3.465 V.

The V

power dissipation is negligible.

DDSYN

6 DC Characteristics

Table 5 provides the DC electrical characteristics for the MPC852T.

Table 5. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltage V

Input high voltage (all inputs except PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, MII_TXEN, MII_MDIO)

TRST , TMS,

Input low voltage V EXTAL, EXTCLK input high voltage V Input leakage current, Vin = 5.5 V

(Except TMS, pins) for 5-V tolerant pins

TRST , DSCK and DSDI

DDH

DDL

DDSYN

Difference between V V

DDSYN

IHC

DDL

3.135 3.465 V

1.7 1.9 V

1.7 1.9 V — 100 mV

2.0 3.465 V

GND 0.8 V

0.7 × V

DDH

— 100 µA

Input leakage current, Vin = V (Except TMS,

TRST , DSCK, and DSDI)

Input leakage curren t, Vin = 0 V (Except TMS,

TRST, DSCK and DSDI pins)

Input capacita nc e

DDH

— 10 µA

— 20 pF

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 7

Thermal Calculation and Measuremen t

Table 5. DC Electrical Specifications (continued)

Characteristic Symbol Min Max Unit

Output high voltage, IOH = -2.0 mA,

= 3.0 V

DDH

Except XTAL and open drain pins Output low voltage

IOL = 2.0 mA (CLKOUT) IOL = 3.2 mA IOL = 5.3 mA IOL = 7.0 mA (Txd1/pa14, txd2/pa12) IOL = 8.9 mA (TS, TA, TEA, BI, BB,

HRESET, SRESET)

The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO,

TCK,

Input capacitance is periodically sampled.

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IWP(0:1)/VFLS(0:1), RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/P A8, TIN3/BRGO3/CLK5/PA3, BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24, BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14, MII-RXD1/PD13, MII-MDC/PD12, MII-TXERR/RXD3/PD1 1, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4, MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, MII_COL

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/

3 4

TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant pins.

STS, OP3/MODCK2/DSDO, BADDR(28:30)

VOH 2.4 — V

VOL — 0.5 V

7 Thermal Calculation and Measurement

For the following discussions, PD= (V

The V

power dissipation is negligible.

DDSYN

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: TJ = TA +(R where:

TA = ambient temperature ºC R PD = power dissipation in package

8 Freescale Semiconductor

x PD)

θJA

= package j unction-to-ambient thermal resistance (ºC/W)

θJA

x IDDL) + P

DDL

, where P

I/O

is the power dissipation of the I/O drivers.

I/O

NOTE

MPC852T Hardware Specifications, Rev. 3.1

Thermal Calculation and Measurement

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performa nce. However , the answer is o nly an estimate; tes t cases have demonstra ted that errors of a factor of two (in the quantity T

) are possible.

J-TA

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically , the ther mal resistance has freque ntly been expressed as the sum of a junction-to-case the rmal resistance and a case-to-ambient thermal resistance:

= R

θJA

where:

is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the

θJC

case-to-am bient thermal resistance, R heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit boar d surrounding the device. Thi s thermal model is most usefu l for ceramic packages wit h heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required.

+ R

R R R

θJC

θJA θJC θCA

θCA

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resista nce (ºC/W)

. For instance, the user can change the air flow around the device, add a

θCA

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-boa rd and a ju nction-to-case t hermal resist ance. The juncti on-to-case co vers the sit uation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. Thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation:

TJ = TB +(R

θJB

x PD)

where:

= junction-to-board thermal resistance (ºC/W)

θJB

TB = board temperature ºC PD = power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane.

7.4 Estimation Using Simulation

When the board temperatur e is not known, a therma l simulation of the appl ication is needed . The simple two-resistor model can be used with the therma l simula tion of t he app licat ion [2] , or a more ac curat e and comple x model of the package can be used in the thermal simulation.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 9

References

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (Ψ

) can be used to determine the junction temperature with a measurement of the

temperature at the top center of the package case using the following equation: TJ = TT +(ΨJT x PD) where:

= thermal c haracteriz ation parameter

TT = thermocouple temperature on top of package PD = power dissipation in package

The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a 40-gauge type T the rmocouple epoxied to the top center of the package case. The th ermocouple should be p ositioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire ex tending f rom the junc tion. The ther mocouple wire is pl aced flat a gainst th e package case to avoid measurement errors that cooling effects of the thermocouple wire cause.

8 References

Semiconductor Equipment and Materials International(415) 964-5111 805 East Middlefield Rd Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or (Available from Global Engineering documents)303-397-7956

JEDEC Specifications http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

9 Power Supply and Power Sequencing

This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage (V

) and PLL voltage (V

DDL

DDSYN

the MPC852T is supplied with 3.3 V across V The signal PA[0:3], P A[8: 11], PB15, PB[ 24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK,

TRST , TMS, MII_TXEN, MII _MDIO are 5 V-tolerant. All inpu ts cannot be more than 2. 5 V greater tha n V addition, 5 V-tolerant pins can not exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This restriction applies to power-on reset or power down and normal operation.

) that operates at a lower voltage than the I/O voltage V

and VSS (GND).

DDH

. The I/O section of

DDH

. In

MPC852T Hardware Specifications, Rev. 3.1

10 Freescale Semiconductor

Mandatory Reset Configurations

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply:

•V

must not exceed V

DDL

must not exceed 1.9 V, and V

DDL

DDH

during power-on reset or power down.

must not exceed 3.465.

DDH

These cautions are nece ssary for th e long-t erm reliab ility of th e part. If the y are violat ed, the elect rostati c discha rge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in

Figure 2 can be added to meet

these requirements. The MUR420 Schot tky diode s con tr ol the maximum potential difference between the ext ern al bus and core power su ppl ies on power-on reset , an d t he 1N5820 diodes regulate the maximum potential d ifference on power-down.

DDH

MUR420

1N5820

Figure 2. Example Voltage Sequencing Circuit

DDL

10 Mandatory Reset Configurations

The MPC852T requires a mandatory configuration during reset. If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET assertion,

the HRCW[D BGC] value that is needed to be set to binary X1 in the hardware reset configurati on word (HRCW ) and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset.

If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 11

Layout Practices

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the mandatory value in

Table 6 in the boot code after the reset deasserts.

Table 6. Mandatory Reset Configuration of MPC852T

HRCW (Hardware reset configuration word)

SIUMCR (SIU module configuration register)

MBMR (Machine B mode register)

PAPAR (Port A pin assignment register)

PADIR (Port A Data Direction Register)

PBPAR (Port B Pin Assignment Register)

PBDIR (Port B Data Direction Register)

PCPAR (Port C Pin Assignment Register)

HRCW[DBGC] X1

SIUMCR[DBGC] X1

MBMR[GPLB4DIS} 0

PAPAR[4-7] PAPAR[12-15]

PADIR[4-7] PADIR[12-15]

PBPAR[14] PBPAR[16-23] PBPAR[26-27]

PBDIR[14] PBDIR[16-23] PBDIR[26-27]

PCPAR[8-11] PCDIR[14]

Value

(binary)

PCDIR (Port C Data Direction Register)

PCDIR[8-11] PCDIR[14]

11 Layout Practices

Each VDD pin on the MPC852T should be provided with a low-impedance path to the board’s supply. Each GND pin should likewise be provid ed with a low-impe dance path to gr ound. The power suppl y pins drive di stinct gro ups of logic on chip. The V located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropr iate decoupling cap aci tors should be u sed i f required. The capac it or l eads and associated printed circuit traces connect ing to chip V minimum, a four-layer board employing two inner layers as V

All output pins on the MPC852T have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized to minimize undershoot and reflections that these fast output switching times cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads, because these loads create hi gher transient current s in the V inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL

power supply should be bypass ed to gr ound usi ng at l east f our 0.1 µF by-pass capac itors

and GND should be kept to less than half an inch per capacitor lead. At a

and GND planes should be used.

and GND circuits. Pull up all unused

MPC852T Hardware Specifications, Rev. 3.1

12 Freescale Semiconductor

Bus Signal Timing

supply pins. For more information, please refer to MPC866 User’s Manual, Section 14.4.3, “Clock Synthesizer Power (V

DDSYN

, V

SSSYN

, V

SSSYN1

).”

12 Bus Signal Timing

The maximum bus speed that the MPC852T supports is 66 MHz. Table 7 shows the frequency ranges for standard part frequencies.

Table 7. Frequency Ranges for Standa rd Part Frequencies (1:1 Bus Mode)

Part

Freq

Core Freq

Bus Freq 40 50 40 66.67

50MHz 66MHz

Min Max Min Max

40 50 40 66.67

Table 8. Frequency Ranges for Standa rd Part Frequencies (2:1 Bus Mode)

Part

Freq

Core Freq

Bus Freq 2:1

50MHz 66MHz 80MHz 100MHz

Min Max Min Max Min Max Min Max

40 50 40 66.67 40 80 40 100

20 25 20 33.33 20 40 20 50

Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50 and 66 MHz.

The timing for the MPC852T bus shown as sumes a 50-p F loa d for maximum del ays and a 0- pF loa d for mini mu m delays. CLKOUT assumes a 100-pF load maximum delay

Table 9. Bus Operation Timings

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

B1 Bus period (CLKOUT) See Table 7 — — — — — — — — ns

B1a EXTCL K to CLKOUT phase skew - If CLKOUT

is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase

skew. B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns B1c Frequency jitter on EXTCLK

Freescale Semiconduc tor 13

MPC852T Hardware Specifications, Rev. 3.1

-2 +2 -2 +2 -2 +2 -2 +2 ns

— 0.50 — 0.50 — 0.50 — 0.50 %

Unit

Bus Signal Timing

Num Characteristic

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B1d CLKOUT phase jitter peak-to-peak

for OSCLK ≥ 15 MHz

CLKOUT phase jitter peak-to-peak

for OSCLK < 15 MHz

B2 CLKOUT pulse width low (MIN = 0.4 x B1, MAX

= 0.6 x B1)

B3 CLKOUT pulse width high (MIN = 0.4 x B1,

MAX = 0.6 x B1)

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR,

BURST, D(0:31), DP(0:3) output hold (MIN =

0.25 x B1)

B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR

output hold (MIN = 0.25 x B1) B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2)

IWP(0:2), LWP(0:1),

0.25 x B1)

B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR,

BURST, D(0:31), DP(0:3) valid (MAX = 0.25 x

B1 + 6.3)

STS output hold (MIN =

— 4 — 4 — 4 — 4 ns

— 5 — 5 — 5 — 5 ns

12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns

7.60 — 6.30 — 5.00 — 3.80 — ns

— 13.80 — 12.50 — 11.30 — 10.00 ns

B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR

valid (MAX = 0.25 x B1 + 6.3) B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),

IWP(0:2), FRZ, LWP(0:1),

0.25 x B1 + 6.3)

B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR,

BURST, D(0:31), DP(0:3), TSIZ(0:1), REG,

RSV, PTR High-Z (MAX = 0.25 x B1 + 6.3)

B11 CLKOUT to TS, BB assertion (MAX = 0.25 x B1

+ 6.0)

B11a CLKOUT to TA, BI assertion (when driven by

the memory controller or PCMCIA interface)

(MAX = 0.00 x B1 + 9.30 2) B12 CLKOUT to TS, BB negation (MAX = 0.25 x B1

+ 4.8)

B12a CLKOUT to TA, BI negation (when driven by

the memory controller or PCMCIA interface)

(MAX = 0.00 x B1 + 9.00) B13 CLKOUT to TS, BB High-Z (MIN = 0.25 x B1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns

STS Valid 3 (MAX =

MPC852T Hardware Specifications, Rev. 3.1

— 13.80 — 12.50 — 11.30 — 10.00 ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns

2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns

7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

14 Freescale Semiconductor

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B13a CLKOUT to TA, BI High-Z (when driven by t he

memory controller or PCMCIA interface) (MIN

= 0.00 x B1 + 2.5) B14 CLKOUT to TEA a ssertion (MAX = 0.00 x B1 +

9.00)

B15 CLKOUT to TEA High-Z (MIN = 0.00 x B1 +

2.50)

B16 TA, BI valid to CLKOUT (setup time) (MIN =

0.00 x B1 + 6.00)

B16a TEA, KR, RETRY, CR valid to CLKOUT (setup

time) (MIN = 0.00 x B1 + 4.5)

B16b BB, BG, BR, valid to CLKOUT (setup time) 3

(4MIN = 0.00 x B1 +.000) B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid

(hold time ) (MIN = 0.00 x B1 + 1.00 4)

B17a CLKOUT to KR, RETRY, CR valid (hold time)

(MIN = 0.00 x B1 + 2.00) B18 D(0:31), DP(0:3) valid to CLKOUT ris in g ed ge

(setup time) 5 (MIN = 0.00 x B1 + 6.00) B19 CLKO UT ri si ng e dge to D (0: 31), DP(0:3) valid

(hold time) 5 (MIN = 0.00 x B1 + 1.00 6)

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

6.00 — 6.00 — 6.00 — 6.00 — ns

4.50 — 4.50 — 4.50 — 4.50 — ns

4.00 — 4.00 — 4.00 — 4.00 — ns

1.00 — 1.00 — 1.00 — 2.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 2.00 — ns

B20 D( 0:31), DP (0:3) valid t o CLKOUT falling edge

(setup time) 7(MIN = 0.00 x B1 + 4.00) B21 CLKO UT fallin g edge to D(0:31), DP(0:3) vali d

(hold Time)

(MIN = 0.00 x B1 + 2.00)

B22 CLKOUT rising edge to CS asserted GPCM

ACS = 00 (MAX = 0.25 x B1 + 6.3)

B22a CLKOUT falling edge to CS asserted GPCM

ACS = 10, TRLX = 0 ( MAX = 0 .00 x B1 + 8.00)

B22b CLKOUT falling edge to CS asserted GPCM

ACS = 1 1, TRLX = 0, EBDF = 0 (MA X = 0.2 5 x

B1 + 6.3)

B22c CLKOUT falling edge to CS asserted GPCM

ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375

x B1 + 6.6) B23 CLKOUT rising edge to CS negated GPCM

read access, GPCM write access ACS = 00,

TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 +

8.00)

MPC852T Hardware Specifications, Rev. 3.1

4.00 — 4.00 — 4.00 — 4.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

— 8.00 — 8.00 — 8.00 — 8.00 ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns

Freescale Semiconduc tor 15

Bus Signal Timing

Num Characteristic

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B24 A(0 :31) and BADDR(28:30) to CS asserted

GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1

- 2.00)

B24a A(0:31) and BADDR(28:30) to CS asserted

GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 -

2.00)

B25 CLKOUT rising edge to OE,

WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 x B1

+ 9.00) B26 CLKOUT rising edge to OE negated (MAX =

0.00 x B1 + 9.00)

B27 A(0 :31) and BADDR(28:30) to CS asserted

GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1

- 2.00)

B27a A(0:31) and BADDR(28:30) to CS asserted

GPCM ACS = 1 1 , TRLX = 1 (MI N = 1.50 x B1 -

2.00)

B28 CLKOUT rising edge to WE(0:3)/BS_B[0:3]

negated GPCM write access CSNT = 0 (MAX

= 0.00 x B1 + 9.00)

B28a CLKOUT falling edge to WE(0:3)/BS_B[0:3]

negated GPCM write access TRLX = 0,1

CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80)

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

— 9.00 9.00 9.00 9.00 ns

2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns

35.90 — 29.30 — 23.00 — 16.90 — ns

43.50 — 35.50 — 28.00 — 20.70 — ns

— 9.00 — 9.00 — 9.00 — 9.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

B28b CLKOUT falling edge to CS negated GPCM

write access TRLX = 0,1 CSNT = 1 ACS = 10

or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 +

6.80)

B28c CLKOUT falling edge to WE(0:3)/BS_B[0:3]

negated GPCM write access TRLX = 0,1

CSNT = 1 write access TRLX = 0,1 CSNT = 1,

EBDF = 1 (MAX = 0.375 x B1 + 6.6)

B28d CLKOUT falling edge to CS negated GPCM

write access TRLX = 0,1 CSNT = 1, ACS = 10,

or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 +

6.6)

B29 WE(0:3)/BS_B[0:3] ne gated to D(0 :31),

DP(0:3) High-Z GPCM write access, CSNT =

0, EBDF = 0 (MIN = 0.25 x B1 - 2.00)

B29a WE(0:3)/BS_B[0:3] negated to D(0:31),

DP(0:3) High-Z GPCM write access, TRL X = 0,

CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00)

MPC852T Hardware Specifications, Rev. 3.1

— 14.30 — 13.00 — 11.80 — 10.50 ns

10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns

— 18.00 — 18.00 — 14.30 — 12.30 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

16 Freescale Semiconductor

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B29b CS negated to D(0:31), DP(0:3), High Z GPCM

write access, ACS = 00, TRLX = 0,1 & CSNT =

0 (MIN = 0.25 x B1 - 2.00)

B29c CS negated to D(0:31), DP(0: 3) High-Z GPCM

write access, T RLX = 0, CSNT = 1, ACS = 10,

or ACS = 1 1 EBDF = 0 (MIN = 0.5 0 x B1 - 2. 00)

B29d WE(0:3)/BS_B[0:3] negated to D(0:31),

DP(0:3) High-Z GPCM write access, TRL X = 1,

CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00)

B29e CS negated to D(0:31), DP(0:3) High-Z G PCM

write access, T RLX = 1, CSNT = 1, ACS = 10,

or ACS = 1 1 EBDF = 0 (MIN = 1.5 0 x B1 - 2. 00)

B29f WE(0:3/BS_B[0:3]) negated to D(0:31),

DP(0:3) High Z GPCM write access, TRLX = 0,

CSNT = 1, EBDF = 1 (MIN = 0.375 x B 1 - 6. 30)

B29g CS negated to D(0:31), DP(0:3) High-Z G PCM

write access, TRLX = 0, CSNT = 1 ACS = 10 or

ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30)

B29h WE(0:3)/BS_B[0:3] negated to D(0:31),

DP(0:3) High Z GPCM write access, TRLX = 1,

CSNT = 1, EBDF = 1 (MIN = 0.375 x B 1 - 3. 30)

B29i CS negated to D(0:31 ), DP(0:3) High-Z GPC M

write access, TRLX = 1, CSNT = 1, ACS = 10

or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 -

3.30)

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

43.50 — 35.50 — 28.00 — 20.70 — ns

5.00 — 3.00 — 1.10 — 0.00 — ns

38.40 — 31.10 — 24.20 — 17.50 — ns

B30 CS, WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) Invalid GPCM write access 8

(MIN = 0.25 x B1 - 2.00)

B30a WE(0:3)/BS_B[0:3] negated to A( 0:31),

BADDR(28:30) Invalid GPCM, write access,

TRLX = 0, CSN T = 1,

invalid GPCM write access TRLX = 0, CSNT

=1 ACS = 10, or ACS == 1 1, EBDF = 0 (MI N =

0.50 x B1 - 2.00)

B30b WE(0:3)/BS_B[0:3] negated to A( 0:31) Invalid

GPCM BADDR(28:30) invalid GPCM write

access, TR LX = 1, CSNT = 1. CS negated to

A(0:31) Invalid GPCM w rite ac ces s TRLX = 1,

CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0

(MIN = 1.50 x B1 - 2.00)

Freescale Semiconduc tor 17

CS negated to A(0:31)

MPC852T Hardware Specifications, Rev. 3.1

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

43.50 — 35.50 — 28.00 — 20.70 — ns

Bus Signal Timing

Num Characteristic

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B30c WE(0:3)/BS_B[0:3 ] negated to A(0:31),

BADDR(28:30) invalid GPCM write access,

TRLX = 0, CSN T = 1. CS negated to A(0:31)

invalid GPCM write access, TRLX = 0, CSNT =

1 ACS = 10, ACS == 11, EBDF = 1 (MIN =

0.375 x B1 - 3.00)

B30d WE(0:3)/BS_B[0:3] negated to A( 0:31),

BADDR(28:30) invalid GPCM write access

TRLX = 1, CSNT =1, CS negated to A(0:31)

invalid GPCM write access TRLX = 1, CSNT =

1, ACS = 10 or 11, EBDF = 1 B31 CLKOUT falling edge to CS valid - as

requested by control bit CST4 in the

corresponding word in the UPM (MAX = 0.00 X

B1 + 6.00)

B31a CLKOUT falling edge to CS valid - as

requested by control bit CST1 in the

corresponding word in the UPM (MAX = 0.25 x

B1 + 6.80)

B31b CLKOUT rising edge to CS valid - as requested

by control bit CST2 in the corre sp ond ing word

in the UPM (M AX = 0.00 x B1 + 8.00)

B31c CLKOUT rising edge to CS valid- as requ ested

by control bit CST3 in the corre sp ond ing word

in the UPM (M AX = 0.25 x B1 + 6.30)

8.40 — 6.40 — 4.50 — 2.70 — ns

38.67 — 31.38 — 24.50 — 17.83 — ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

B31d CLKOUT falling edge to CS valid, as requested

by control bit CST1 in the corre sp ond ing word

in the UPM EBDF = 1 (MAX = 0 .375 x B1 + 6.6) B32 CLKO UT falling edge to BS valid- as requested

by control bit BST4 in the corresponding word

in the UPM (M AX = 0.00 x B1 + 6.00)

B32a CLKOUT falling edge to BS valid - as

requested by control bit BST1 in the

corresponding word in the UPM, EBDF = 0

(MAX = 0.25 x B1 + 6.80)

B32b CLKOUT rising edge to BS valid - as reque sted

by control bit BST2 in the corresponding word

in the UPM (M AX = 0.00 x B1 + 8.00)

B32c CLKOUT rising edge to BS valid - as requested

by control bit BST3 in the corresponding word

in the UPM (M AX = 0.25 x B1 + 6.80)

MPC852T Hardware Specifications, Rev. 3.1

18 Freescale Semiconductor

13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

Num Characteristic

Bus Signal Timing

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

B32d CLKOUT falling edge to BS valid- as requested

by control bit BST1 in the corresponding word

in the UPM, EBDF = 1 (MAX = 0.375 x B1 +

6.60)

B33 CLKOUT falling edge to GPL valid - as

requested by control bit GxT4 in t he

corresponding word in the UPM (MAX = 0.00 x

B1 + 6.00)

B33a CLKOUT rising edge to GPL Valid - as

requested by control bit GxT3 in t he

corresponding word in the UPM (MAX = 0.25 x

B1 + 6.80) B34 A(0:31), BADDR(28:30), and D(0:31) to CS

valid - as requested by control bit CST4 in the

corresponding word i n the UP M ( MIN = 0.25 x

B1 - 2.00)

B34a A(0:31), BADDR(28:30), and D(0:31) to CS

valid - as requested by control bit CST1 in the

corresponding word i n the UP M ( MIN = 0.50 x

B1 - 2.00)

B34b A(0:31), BADDR(28:30), and D(0:31) to CS

valid - as requested by CST2 in the

corresponding word in UPM (MIN = 0.75 x B1 -

2.00)

13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

20.70 — 16.70 — 13.00 — 9.40 — ns

B35 A(0:31), BADDR(28:30) to CS valid - as

requested by control bit BST4 in the

corresponding word i n the UP M ( MIN = 0.25 x

B1 - 2.00)

B35a A(0:31), BADDR(28:30), and D(0:31) to BS

valid - As Requested by BST1 in the

corresponding word i n the UP M ( MIN = 0.50 x

B1 - 2.00)

B35b A(0:31), BADDR(28:30), and D(0:31) to BS

valid - as requested by control bit BST2 in the

corresponding word i n the UP M ( MIN = 0.75 x

B1 - 2.00) B36 A(0:31), BADDR(28:30), and D(0:31) to GPL

valid as requested by control bit GxT4 in the

corresponding word i n the UP M ( MIN = 0.25 x

B1 - 2.00) B37 UP W AIT valid to CLKOUT fal ling ed ge 9 (MIN

= 0.00 x B1 + 6.00) B38 CLKOUT falling edge to UPWAIT valid 9 (MIN

= 0.00 x B1 + 1.00)

MPC852T Hardware Specifications, Rev. 3.1

5.60 — 4.30 — 3.00 — 1.80 — ns

13.20 — 10.50 — 8.00 — 5.60 — ns

20.70 — 16.70 — 13.00 — 9.40 — ns

5.60 — 4.30 — 3.00 — 1.80 — ns

6.00 — 6.00 — 6.00 — 6.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

Freescale Semiconduc tor 19

Bus Signal Timing

Num Characteristic

B39 AS va lid to CLKOUT rising edge

x B1 + 7.00)

Table 9. Bus Operation Timings (continued)

33 MHz 40 MHz 50 MHz 66 MHz

Min Max Min Max Min Max Min Max

(MIN = 0.00

7.00 — 7.00 — 7.00 — 7.00 — ns

Unit

B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to

7.00 — 7.00 — 7.00 — 7.00 — ns

CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) B41 TS valid to CLKOUT rising edge (setup time)

7.00 — 7.00 — 7.00 — 7.00 — ns

(MIN = 0.00 x B1 + 7.00) B42 CLKOUT rising edge to TS valid (hold time)

2.00 — 2.00 — 2.00 — 2.00 — ns

(MIN = 0.00 x B1 + 2.00) B43 AS negation to memory controller signals

— TBD — TBD — TBD — TBD ns

negation (MAX = TBD)

If the rate of chan ge of the frequency of EXTAL is slow (that is, it do es no t j um p b etw e en the m ini mu m and maximum va lu es in one cycle) or the frequ ency of the jitter is fast (tha t is, it does not sta y at an extreme value for a lon g time), then the maximum allowed jitter on EXTAL can be up to 2%.

For part speeds above 50MHz, use 9.80ns for B11a.

The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for

BG input is relevant when the MPC852T is selected to work with external bus arbiter.

For part speeds above 50MHz, use 2ns for B17.

The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is

asserted.

For part speeds above 50MHz, use 2ns for B19.

The D(0:31) and DP(0: 3) inpu t timin gs B20 and B21 refer to t he fall ing ed ge of th e CLKOUT. This timing is vali d only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37

and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.

The AS signal is considere d asynchronous to the CLKOUT. The timing B39 is speci fied in order to allow the behavior spe cified in Figure 21.

MPC852T Hardware Specifications, Rev. 3.1

20 Freescale Semiconductor

Figure 3 is the control timing diagram.

Bus Signal Timing

CLKOUT

Outputs

Inputs

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V D

2.0 V

0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input setup time specification

D Minimum input hold time specification

Figure 3. Control Timing

Figure 4 provides the timing for the external clock.

CLKOUT

Figure 4. External Clock Timing

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 21

Bus Signal Timing

Figure 5 provides the timing for the synchronous output signals.

CLKOUT

B7 B9

Output

Signals

B8a

Output

Signals

B8b

B7b

Output

Signals

B9B7a

Figure 5. Synchronous Output Signals Timing

Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13

B12B11

, BB

B13a

B11a B12a

TA, BI

B14

B15

TEA

Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

MPC852T Hardware Specifications, Rev. 3.1

22 Freescale Semiconductor

Figure 7 provides the timing for the synchronous input signals.

CLKOUT

B16

, BI

B16a

TEA, KR,

RETRY, CR

B16b

BB, BG, BR

Bus Signal Timing

B17

B17a

B17

Figure 7. Synchronous Input Signals Timing

Figure 8 provides normal case ti ming for in put dat a. It also appl ies t o normal r ead acc ess es under the con trol o f the

UPM in the memory controller.

CLKOUT

B16

B17

B18

B19

D[0:31],

DP[0:3]

Figure 8. Input Data Timing in Normal Case

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 23

Bus Signal Timing

Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM

RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

CLKOUT

B20

B21

D[0:31],

DP[0:3]

Figure 9. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1

Figure 10 through Figure 13 provide the timing for the external bus read that various GPCM factors control.

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B11 B12

B22

B25

B28

B23

B26

B19

B18

Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00)

MPC852T Hardware Specifications, Rev. 3.1

24 Freescale Semiconductor

CLKOUT

A[0:31]

Bus Signal Timing

B11 B12

B22a

B23

CSx

B25B24

B26

B19B18

D[0:31],

DP[0:3]

Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)

CLKOUT

B11 B12

A[0:31]

B22b

B22c

B23

CSx

B24a

B25 B26

B19B18

D[0:31],

DP[0:3]

Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 25

Bus Signal Timing

CLKOUT

A[0:31]

B11 B12

B22a

B23

CSx

B27

B27a

B22b B22c

B26

B19B18

D[0:31],

DP[0:3]

Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)

MPC852T Hardware Specifications, Rev. 3.1

26 Freescale Semiconductor

Bus Signal Timing

Figure 14 through Figure 16 provide the timing for the external bus write that various GPCM factors control.

LKOUT

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B11

B22 B23

B26

B12

B8 B9

B30

B28B25

B29b

B29

Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 27

Bus Signal Timing

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B11

B22

B26

B12

B28b B28d

B25

B28aB9B28c

B30a B30c

B23

B29c B29g

B29a B29f

Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)

MPC852T Hardware Specifications, Rev. 3.1

28 Freescale Semiconductor

CLKOUT

Bus Signal Timing

B12B11

B30dB30b

A[0:31]

B28b B28d

B23B22

CSx

B25

B29e B29i

WE[0:3]

B26

B29d B29h

B28a B28c

B29b

B9B8

D[0:31],

DP[0:3]

Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 29

Bus Signal Timing

Figure 17 provides the timing for the external bus that the UPM controls.

CLKOUT

A[0:31]

B31a

B31d

B31

CSx

B34

B34a

B34b

B32a B32d

B32

B31b

B32b

B31c

B32c

BS_A

[0:3]

PL_A[0:5],

[0:5]

GPL_B

B36

B35

B35a

B35b

B33a

B33

Figure 17. External Bus Timing (UPM Controlled Signals)

MPC852T Hardware Specifications, Rev. 3.1

30 Freescale Semiconductor

Bus Signal Timing

Figure 18 provides the timing for the asynchronous asserted UPWAIT signal that the UPM controls.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

PL_A[0:5],

[0:5]

GPL_B

Figure 18. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 19 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

PL_A[0:5],

[0:5]

GPL_B

Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 31

Bus Signal Timing

Figure 20 provides the timing for the synchronous external master access that the GPCM controls.

CLKOUT

B41 B42

B40

A[0:31],

TSIZ[0:1],

/W, BURST

B22

CSx

Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 21 provides the timing for the asynchronous external master memory access that the GPCM controls.

CLKOUT

B39

B40

A[0:31],

SIZ[0:1],

R/W

B22

CSx

Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 22 provides the timing for the asynchronous external master control signals negation.

B43

Sx, WE[0:3],

OE, GPLx,

[0:3]

Figure 22. Asynchronous External Master—Control Signals Negation Timing

MPC852T Hardware Specifications, Rev. 3.1

32 Freescale Semiconductor

Table 10 provides interrupt timing for the MPC852T.

Table 10. Interrupt Timing

Bus Signal Timing

All Frequencies

Num Characteristic

Min Max

I39 IRQx valid to CLKOUT risi ng edge (set

6.00 ns

up time) I40 IRQx hold time after CLKOUT 2.00 ns I41 IRQx pulse width low 3.00 ns I42 IRQx pulse width high 3.00 ns I43 IRQx edge-to-edge time 4xT

The timings I39 and I40 describe the testing conditions under which the IRQ

lines are tested when being defined as level-sensitive. The

CLOCKOUT

IRQ lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and have no direct relation with the total system interrupt latency that the MPC852T is able to support.

Figure 23 provides the interrupt detection timing for the external level-sensitive lines.

CLKOUT

Unit

—

I39

I40

IRQ

Figure 23. Interrupt Detection Timing for External Level Sensitive Lines

Figure 24 provides the interrupt detection timing for the external edge-sensitive lines.

CLKOUT

I41 I42

IRQ

I43

Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 33

Bus Signal Timing

Table 11 shows the PCMCIA timing for the MPC852T.

Table 11. PCMCIA Timing

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Unit

A(0:31), REG valid to PCMCIA Strobe

J82

asserted. 1 (MIN = 0.75 x B1 - 2.00) A(0:31), REG valid to ALE negation.1 (MIN =

J83

1.00 x B1 - 2.00) CLKOUT to REG valid (MAX = 0.25 x B1 +

J84

8.00) CLKOUT to REG Invalid. (MIN = 0.25 x B1 +

J85

1.00) CLKOUT to CE1, CE2 asserted. (MAX =

J86

0.25 x B1 + 8. 00) CLKOUT to CE1, CE2 negated. (MAX =

J87

0.25 x B1 + 8. 00) CLKOUT to PCOE, IORD, PCWE, IOWR

J88

assert time. (MAX = 0.00 x B1 + 11.00) CLKOUT to PCOE, IORD, PCWE, IOWR

J89

negate time. (MAX = 0.00 x B1 + 11.00) CLKOUT to ALE assert time (MAX = 0.25 x

J90

B1 + 6.30) CLKOUT to ALE negate time (MAX = 0.25 x

J91

B1 + 8.00) PCWE, IOWR negated to D(0:31) invalid.

J92

(MIN = 0.25 x B1 - 2.00)

20.70 — 16.70 — 13.00 — 9.40 — ns

28.30 — 23.00 — 18.00 — 13.20 — ns

7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns

8.60 — 7.30 — 6.00 — 4.80 — ns

7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns

— 11.00 — 11.00 — 11.00 — 11.00 ns

2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns

7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns

— 15.60 — 14.30 — 13.00 — 11.80 ns

5.60 — 4.30 — 3.00 — 1.80 — ns

WAITA and WAITB valid to CLKOUT rising

J93

J94

PSST = 1. Otherwise add PSST times cycle time.

(MIN = 0.00 x B1 + 8.00)

edge. CLKOUT rising edge to WAITA and WAITB

invalid.

(MIN = 0.00 x B1 + 2.00)

8.00 — 8.00 — 8.00 — 8.00 — ns

2.00 — 2.00 — 2.00 — 2.00 — ns

PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timing s defi ne w hen the WAITA signals are detected in order to freeze (or relieve) the PCMCIA current

cycle. The

WAITA assertion is effective only if it is detec ted 2 cy c les be fore t he PSL tim er ex pi rati on. See PC MC IA Int erfa ce

in the MPC852T PowerQUI CC User s Man ual .

MPC852T Hardware Specifications, Rev. 3.1

34 Freescale Semiconductor

Figure 25 provides the PCMCIA access cycle timing for the external bus read.

CLKOUT

P44

A[0:31]

Bus Signal Timing

REG

CE1/CE2

COE, IORD

ALE

D[0:31]

P46 P45

P48 P49

P53P52 P52

P47

P51P50

Figure 25. PCMCIA Access Cycles Timing External Bus Read

B19B18

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 35

Bus Signal Timing

Figure 26 provides the PCMCIA access cycle timing for the external bus write.

CLKOUT

P44

A[0:31]

P46 P45

REG

P48 P49

CE1/CE2

PCWE, IOWR

P53P52 P52

ALE

D[0:31]

Figure 26. PCMCIA Access Cycles Timing External Bus Write

Figure 27 provides the PCMCIA WAIT signals detection timing.

P47

P51P50

B9B8

P54

CLKOUT

P55

P56

WAITA

Figure 27. PCMCIA WAIT Signals Detection Timing

MPC852T Hardware Specifications, Rev. 3.1

36 Freescale Semiconductor

Table 12 shows the PCMCIA port timing for the MPC852T.

Table 12. PCMCIA Port Timing

33 MHz 40 MHz 50 MHz 66 MHz

Num Characteristic

Min Max Min Max Min Max Min Max

Bus Signal Timing

Unit

CLKOUT to OPx Va lid (MAX = 0.00 x B1 +

J95

19.00) HRESET negated to OPx drive 1(MIN = 0.75 x

J96

B1 + 3.00) IP_Xx valid to CLKOUT ris ing edge (MIN = 0 .00

J97

x B1 + 5.00) CLKOUT rising edge to IP_Xx invalid (MIN =

J98

0.00 x B1 + 1.00)

OP2 and OP3 only.

— 19.00 — 19.00 — 19.00 — 19.00 ns

25.70 — 21.70 — 18.00 — 14.40 — ns

5.00 — 5.00 — 5.00 — 5.00 — ns

1.00 — 1.00 — 1.00 — 1.00 — ns

Figure 28 provides the PCMCIA output port timing for the MPC852T.

CLKOUT

P57

Output

Signals

HRESET

P58

P2, OP3

Figure 28. PCMCIA Output Port Timing

Figure 29 provides the PCMCIA output port timing for the MPC852T.

CLKOUT

P59

P60

Input

Signals

Figure 29. PCMCIA Input Port Timing

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 37

Bus Signal Timing

Table 13 shows the debug port timing for the MPC852T.

Table 13. Debug Port Timing

Num Characteristic

All Frequencies

Unit

Min Max

J82 DSCK cycle time 3xT J83 DSCK clock pulse width 1.25xT J84 DSCK rise and fall times 0.00 3.00 ns J85 DSDI input data setup time 8.00 — ns J86 DSDI data hold time 5.00 — ns J87 DSCK low to DSDO data valid 0.00 15.00 ns J88 DSCK low to DSDO invalid 0.00 2.00 ns

Figure 30 provides the input timing for the debug port clock.

DSCK

D61

D63

D62

Figure 30. Debug Port Clock Input Timing

Figure 31 provides the timing for the debug port.

CLOCKOUT

D62

— — — —

D63

DSCK

D64

D65

DSDI

D66

D67

DSDO

Figure 31. Debug Port Timings

MPC852T Hardware Specifications, Rev. 3.1

38 Freescale Semiconductor

Table 14 shows the reset timing for the MPC852T.

Table 14. Reset Timing

Num Characteristic

Bus Signal Timing

33 MHz 40 MHz 50 MHz 66 MHz

Unit

Min Max Min Max Min Max Min Max

CLKOUT to HRESET high impedance (MAX =

J82

0.00 x B1 + 20.00) CLKOUT to SRESET high impedance (MAX =

J83

0.00 x B1 + 20.00) J84 RSTCONF pulse width (MIN = 17.00 x B1) 515.20 — 425.00 — 340.00 — 257.60 — ns J85 — — — — — — — — — —

Configuration data to HRESET rising edge set

J86

up time (MIN = 15.00 x B1 + 50.00) Configuration dat a to RSTCONF rising edge set

J87

up time (MIN = 0.00 x B1 + 350.00) Configuration data hold time after RSTCONF

J88

negation (MIN = 0.00 x B1 + 0.00) Configuration data hold time after HRESET

J89

negation (MIN = 0.00 x B1 + 0.00) HRESET and RSTCONF asserted to data out

J90

drive (MAX = 0.00 x B1 + 25.00) RSTCONF negated to data out hig h impedance.

J91

(MAX = 0.00 x B1 + 25.00) CLKOUT of last rising edge before chip

J92

three-states impedance. (MAX = 0.00 x B1 + 25.00)

HRESET to data out high

— 20.00 — 20.00 — 20.00 — 20.00 ns

504.50 — 425.00 — 350.00 — 277.30 — ns

350.00 — 350.00 — 350.00 — 350.00 — ns

0.00 — 0.00 — 0.00 — 0.00 — ns

— 25.00 — 25.00 — 25.00 — 25.00 ns

J93 DSDI, DSCK set up (MIN = 3.00 x B1) 90.90 — 75.00 — 60.00 — 45.50 — ns J94 DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00) 0.00 — 0.00 — 0.00 — 0.00 — ns

SRESET negated to CLKOUT rising edge for

J95

DSDI and DSCK sample (MIN = 8.00 x B1)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 39

242.40 — 200.00 — 160.00 — 121.20 — ns

Bus Signal Timing

Figure 32 shows the reset timing for the data bus configuration.

HRESET

R71

R76

RSTCONF

R73

R74

D[0:31] (IN)

R75

Figure 32. Reset Timing—Configuration from Data Bus

Figure 33 provides the reset timing for the data bus weak drive during configuration.

CLKOUT

HRESET

RSTCONF

D[0:31] (OUT)

(Weak)

R69

R79

R77 R78

Figure 33. Reset Timing—Data Bus Weak Drive during Configuration

MPC852T Hardware Specifications, Rev. 3.1

40 Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

Figure 34 provides the reset timing for the debug port configuration.

CLKOUT

R70

R82

SRESET

R80R80

R81

DSCK, DSDI

R81

Figure 34. Reset Timing—Debug Port Configuration

13 IEEE 1149.1 Electrical Specifications

Table 15 provides the JTAG timings for the MPC852T shown in Figure 35 through Figure 38.

Table 15. JTAG Timing

All Frequencies

Num Characteristic

Min Max

J82 TCK cycle time 100.00 — ns J83 TCK clock pulse width measured at 1.5 V 40.00 — ns J84 TCK rise and fall times 0.00 10.00 ns J85 TMS, TDI data setup time 5.00 — ns J86 TMS, TDI data hold time 25.00 — ns J87 TCK low to TDO data valid — 27.00 ns J88 TCK low to TDO data invalid 0.00 — ns J89 TCK low to TDO high impedance — 20.00 ns J90 TRST assert time 100.00 — ns J91 TRST setup time to TCK low 40.00 — ns J92 TCK falling edge to output valid — 50.00 ns J93 TCK falling edge to output valid out of high impedance — 50.00 ns J94 TCK falling edge to output high impedance — 50.00 ns

Unit

J95 Boundary scan input valid to TCK rising edge 50.00 — ns J96 TCK rising edge to boundary scan input invalid 50.00 — ns

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 41

IEEE 1149.1 Electrical Specifications

TCK

J84 J84

TCK

MS, TDI

J82 J83

Figure 35. JTAG Test Clock Input Timing

J85

J86

J87

J88 J89

TDO

TCK

TRST

Figure 36. JTAG Test Access Port Timing Diagram

J91

J90

Figure 37. JTAG TRST Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

42 Freescale Semiconductor

CPM Electri cal Characteristics

TCK

J92 J94

Output

Signals

J93

Output

Signals

J95 J96

Output

Signals

Figure 38. Boundary Scan (JTAG) Timing Diagram

14 CPM Electrical Characteristics

This section pr ovi des t he AC and DC electric al s peci fications for th e communications proc es sor module (CPM) of the MPC852T.

14.1 Port C Interrupt AC Electrical Specifications

Table 16 provides the timings for port C interrupts.

Table 16. Port C Interrupt Timing

Num Characteristic

35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns 36 Port C interrupt minimum time between ac tive edges 55 — ns

Figure 39 shows the port C interrupt detection timing.

Port C

(Input)

Figure 39. Port C Interrupt Detection Timing

33.34 MHz Unit

Min Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 43

CPM Electri cal Characteristics

14.2 IDMA Controller AC Electrical Specifications

Table 17 provides the IDMA controller timings as shown in Figure 40 through Figure 43.

Table 17. IDMA Controller Timing

All Frequencies

Num Characteristic

Min Max

40 DREQ setup time to clock high 7 — ns 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high — 12 ns 43 SDACK negation delay from clock low — 12 ns 44 SDACK negation delay from TA low — 20 ns 45 SDACK negation delay from clock high — 15 ns 46 TA assertion to falling edge of the clock setup time (applies to external TA) 7 — ns

Applies to high-to-low mode (EDM=1)

Unit

3 — ns

CLKO

(Output)

DREQ (Input)

Figure 40. IDMA External Requests Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

44 Freescale Semiconductor

CLKO

(Output)

R/W

(Output)

CPM Electri cal Characteristics

DATA

(Input)

SDACK

Figure 41. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA

CLKO

(Output)

R/W

(Output)

42 44

DATA

(Output)

SDACK

Figure 42. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 45

CPM Electri cal Characteristics

CLKO

(Output)

R/W

(Output)

DATA

(Output)

SDACK

42 45

Figure 43. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA

14.3 Baud Rate Generator AC Electrical Specifications

Table 18 provides the baud rate generator timings as shown in Figure 44.

Table 18. Baud Rate Generator Timing

All Frequencies

BRGOX

Num Characteristic

Min Max

50 BRGO rise and fall time — 10 ns 51 BRGO duty cycle 40 60 % 52 BRGO cycle 40 — ns

Unit

Figure 44. Baud Rate Generator Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

46 Freescale Semiconductor

14.4 Timer AC Electrical Specifications

Table 19 provides the general-purpose timer timings as shown in Figure 45.

Num Characteristic

61 TIN/TGATE rise and fall time 10 — ns 62 TIN/TGATE low time 1 — clk 63 TIN/TGATE high time 2 — clk 64 TIN/TGATE cycle time 3 — clk 65 CLKO low to TOUT valid 3 25 ns

CLKO

Table 19. Time r Timing

All Frequencies

Min Max

CPM Electri cal Characteristics

Unit

626361

TIN/TGATE

(Input)

TOUT

(Output)

Figure 45. CPM General-Purpose Timers Timing Diagram

14.5 SCC in NMSI Mode Electrical Specifications

Table 20 provides the NMSI external clock timing.

Table 20. NMSI External Clock Timing

All Frequencies

Num Characteristic

Min Max

100 RCLK3 and TCLK3 width high 101 RCLK3 and TCLK3 width low 1/SYNCCLK +5 — ns 102 RCLK3 and TCLK3 rise/fall time — 15.00 ns

1/SYNCCLK — ns

Unit

103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns 104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns 105 CTS3 setup time to TCLK3 rising edge 5.00 — ns

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 47

CPM Electri cal Characteristics

Table 20. NMSI External Clock Timing (continued)

Num Characteristic

106 RXD3 setup time to RCLK3 rising edge 5.00 — ns 107 RXD3 hold time from RCLK3 rising edge 108 CD3 setup Time to RCLK3 rising edge 5.00 — ns

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.

Also appli es to CD and CTS hold time when they are used as an external sync signal.

Table 21 provides the NMSI internal clock timing.

Table 21. NMSI Inte rnal Clo ck Timing

Num Characteristic

100 RCLK3 and TCLK3 frequency 102 RCLK3 and TCLK3 rise/fall time — — ns

All Frequencies

Unit

Min Max

5.00 — ns

All Frequencies

Unit

Min Max

0.00 SYNCCLK/3 MHz

103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns 104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns 105 CTS3 setup time to TCLK3 rising edge 40.00 — ns 106 RXD3 setup time to RCLK3 rising edge 40.00 — ns 107 RXD3 hold time from RCLK3 rising edge

0.00 — ns

108 CD3 setup time to RCLK3 rising edge 40.00 — ns

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.

Also applies to CD and CTS hold time when they are used as an external sync signals.

MPC852T Hardware Specifications, Rev. 3.1

48 Freescale Semiconductor

Figure 46 through Figure 48 show the NMSI timings.

RCLK3

CPM Electri cal Characteristics

RxD3

(Input)

CD3

(Input)

CD3

SYNC Input)

TCLK3

106

102

102 101

100

107

108

107

Figure 46. SCC NMSI Receive Timing Diagram

102 101

100

TxD3

(Output)

RTS3

(Output)

CTS3

(Input)

CTS3

(SYNC Input)

103

105

104

Figure 47. SCC NMSI Transmit Timing Diagram

104

107

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 49

CPM Electri cal Characteristics

TCLK3

102

TxD3

(Output)

RTS3

(Output)

CTS3

(Echo Input)

102 101

100

103

104

105

Figure 48. HDLC Bus Timing Diagram

14.6 Ethernet Electrical Specifications

Table 22 provides the Ethernet timings as shown in Figure 49 through Figure 53.

Table 22. Ethernet Timing

104107

All Frequencies

Num Characteristic

Min Max

120 CLSN width high 40 — ns 121 RCLK3 rise/fall time — 15 ns 122 RCLK3 width low 40 — ns 123 RCLK3 clock period 124 RXD3 setup time 20 — ns 125 RXD3 hold time 5 — ns 126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns 127 RENA width low 100 — ns 128 TCLK3 rise/fall time — 15 ns 129 TCLK3 width low 40 — ns 130 TCLK3 clock period 131 TXD3 active delay (from TCLK3 rising edge) — 50 ns 132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns 133 TENA active delay (from TCLK3 rising edge) 10 50 ns

80 120 ns

99 101 ns

Unit

MPC852T Hardware Specifications, Rev. 3.1

50 Freescale Semiconductor

CPM Electri cal Characteristics

Table 22. Ethernet Timing (continued)

All Frequencies

Num Characteristic

Min Max

134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns 135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK3 falling edge) 10 50 ns 137 REJECT width low 1 — CLK 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK negated

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.

SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

— 20 ns — 20 ns

CLSN(CTS1)

(Input)

120

Unit

RCLK3

RxD3

(Input)

RENA(CD3)

(Input)

Figure 49. Ethernet Collision Timing Diagram

121

124 123

125

121

126

Figure 50. Ethernet Receive Timing Diagram

Last Bit

127

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 51

CPM Electri cal Characteristics

TCLK3

TxD3

(Output)

TENA(RTS3)

(Input)

RENA(CD3)

(Input)

(NOTE 2)

RCLK3

128

129

131 121

132

133 134

NOTES:

Transmit clock invert (TCI) bit in GSMR is set.

1. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the

2. CSL bit is set in the buffer descriptor at the end of the frame transmission.

Figure 51. Ethernet Transmit Timing Diagram

RxD3

(Input)

RSTRT

(Output)

REJECT

1 1 BIT1 BIT2

Start Frame De-

125

Figure 52. CAM Interface Receive Start Timing Diagram

137

Figure 53. CAM Interface REJECT Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

136

52 Freescale Semiconductor

14.7 SPI Master AC Electrical Specifications

Table 23 provides the SPI master timings as shown in Figure 54 and Figure 55.

Table 23. SPI Master Timing

All Frequencies

Num Characteristic

CPM Electri cal Characteristics

Unit

Min Max

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

160 MASTER cycle time 4 1024 t 161 MAS TER clock (SCK) high or low time 2 512 t 162 MASTER data setup time (inputs) 15 — ns 163 Master data hold time (inputs) 0 — ns 164 Master data valid (after SCK edge) — 10 ns 165 Master data hold time (outputs) 0 — ns 166 Rise time output — 15 ns 167 Fall time output — 15 ns

166167161

161 160

163

162

166

167

cyc

SPIMISO

(Input)

SPIMOSI

(Output)

msb Data lsb msb

165 164

167 166

msb lsb msb

Data

Figure 54. SPI Master (CP = 0) Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 53

CPM Electri cal Characteristics

SPICLK

(CI=0)

(Output)

161 160

SPICLK

(CI=1)

(Output)

163

162

166167161

167

166

SPIMISO

(Input)

SPIMOSI

(Output)

msb Data lsb msb

165 164

167 166

msb lsb msb

Data

Figure 55. SPI Master (CP = 1) Timing Diagram

14.8 SPI Slave AC Electrical Specifications

Table 24 provides the SPI slave timings as shown in Figure 56 and Figure 57.

Table 24. SPI Slave Timing

Num Characteristic

170 Slave cycle time 2 — t 171 Slave enable lead time 15 — ns 172 Slave enable lag time 15 — ns

All Frequencies

Unit

Min Max

cyc

173 Slave clock (SPICLK) high or low time 1 — t 174 Slave sequential transfer delay (does not require deselect) 1 — t 175 Slave data setup time (inputs) 20 — ns 176 Slave data hold time (inputs) 20 — ns 177 Slave access time — 50 ns

MPC852T Hardware Specifications, Rev. 3.1

54 Freescale Semiconductor

cyc

SPISEL

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

181182173

173 170

177 182

181

180

CPM Electri cal Characteristics

171172

174

178

SPIMISO

(Output)

SPIMOSI

(Input)

Datamsb lsb msbUndef

175 179

176 182

msb lsb msb

Data

181

Figure 56. SPI Slave (CP = 0) Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 55

FEC Electrical Characteristics

SPISEL

(Input)

171 170

SPICLK

(CI=0)

(Input)

173

SPICLK

(CI=1)

(Input)

177 182

173

180

172

174

181182

181

178

SPIMISO

(Output)

SPIMOSI

(Input)

msb

175 179

176 182

msb lsb

Data

181

Data

lsbUndef

msb

Figure 57. SPI Slave (CP = 1) Timing Diagram

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK)

The receiver functi ons corre ctly up to a MII_RX_C LK maximum fr equency of 25MHz +1%. Ther e is no min imum frequency requirement. In addition, the processo r cl ock fre quency must exceed the MII_RX_CLK frequency - 1%.

Table 25 provides information on the MII receive signal timing.

Table 25. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK per iod M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period

MPC852T Hardware Specifications, Rev. 3.1

56 Freescale Semiconductor

Figure 58 shows MII receive signal timing.

MII_RX_CLK (input)

MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER

FEC Electrical Characteristi cs

Figure 58. MII Receive Signal Timing Diagram

15.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK)

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%.

Table 26 provides information about the MII transmit signal timing,.

Table 26. MII Transmit Signal Timing

Num Characteristic Min Max Unit

M5 MII_TX_CLK to MII_TXD[3:0] , MII_TX_EN, M II_TX_ER inva lid 5 — ns M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 — M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period

Figure 59 shows the MII transmit signal timing diagram.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 57

FEC Electrical Characteristics

MII_TX_CLK (input)

MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER

Figure 59. MII Transmit Signal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 27 provides information about the MII async inputs signal timing.

Table 27. MII Async Inputs Signal Timing

Num Characteristic Min Max Unit

M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period

Figure 60 shows the MII asynchronous inputs signal timing diagram.

MII_CRS, MII_COL

Figure 60. MII Async Inputs Timing Diagram

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 28 provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 28. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M10 MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

0 — ns

M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns

MPC852T Hardware Specifications, Rev. 3.1

58 Freescale Semiconductor

FEC Electrical Characteristi cs

Table 28. MII Serial Management Channel Timing (continued)

Num Characteristic Min Max Unit

M14 MII_MDC pulse width high 40% 60% MII_MDC period M15 MII_MDC pulse width low 40% 60% MII_MDC period

Figure 61 shows the MII serial management channel timing diagram.

M14

MM15

MII_MDC (output)

M10

MII_MDIO (output)

M11

MII_MDIO (input)

M12

M13

Figure 61. MII Serial Management Channel Timing Diagram

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 59

Mechanical Data and Ordering Information

16 Mechanical Data and Ordering Information

Table 29 identifies the packages and operating frequencies orderable for the MPC852T.

Package Type Temperature (Tj) Frequency (MHz) Order Number

Table 29. MPC852T Package/Frequency Orderable

Plastic ball grid array (VR and ZT suffix)

Plastic ball grid array (CVR suffix)

0°C to 95°C 50 MPC852TVR50

MPC852TZT50

66 MPC852TVR66

MPC852TZT66

80 MPC852TVR80

MPC852TZT80

100 MPC852TVR100

MPC852TZT100

– 40°C to 100°C 66 TBD

16.1 Pin Assignments

The following sections gi ve the pinout an d pin listing fo r the JEDEC Compliant and th e non-JEDEC versions of the 16 x 16 PBGA package.

MPC852T Hardware Specifications, Rev. 3.1

60 Freescale Semiconductor

Mechanical Data and Ordering Information

16.1.1 The JEDEC Compliant Pinout

Figure 62 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional

information, see the MPC866 PowerQUICC Family User’s Manual.

NOTE: This is the top view of the device.

N/C

VDDL

BDIP

VFLS_1 RSV BURST

ALE_A

OP0

OP3

BADDR29 BADDR28

EXTAL

XTAL EXTCLK WAIT_A

PORST VDDSYN VSSSYN1

VDDL

N/C

CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C

CS1

CS0

CE2_AGPL_A3 WE3

GPL_A4

CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C

CS2 OE

TEA

GPL_A5

MII_COL

DSCK

VFLS_0

AS BADDR30

OP1

OP2

RSTCONF

VDDL

SRESET

VSSSYN

IP_A7

IP_A2 PD10 N/CD31

IP_A0 IP_A4 DP2

MII_CRS BS_A3 A22 A30

GPL_A0

WE0 BS_A1 A24

CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0

FRZ

HRESET

VDDL

N/C

IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1

IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT

DP0

DP3

D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1

D28

D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN

D30

A29 A27 A13 A9 A6 A0 N/C

A31CS6

GND

D6 D19 D5 D2 D27 D13 D0 PD5

A20 A15 A10 A4 N/C PB29 VDDL

PB31 PC13

PB30 TDO

PB28 TDI

TCK PB25

PC5 PC7

PD13 PA2

VDDH

N/C PC4

PD8 PD15

D23

PC15

PC12 PA11

TMS TRST

VDDL MDIO

PA10 PB24

PA8 PA9

PC6 PA3

PA1 PB15

VDDL PA0

PD12 PD14

N/C PD11

PD7 N/C

34567 8

91011

12 13 14 15 16

Figure 62. Pinout of the PBGA Package - JEDEC Standard

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 61

Mechanical Data and Ordering Information

Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments.

Table 30. Pin Assignments - JEDEC Standard

Name Pin Number Type

A[0:31] B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12,

B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8, B11, A8, B10, B9, D8

TSIZ0 REG

TSIZ1 E7 Bidirectional

RD/WR B1 Bidirectional

BURST G3 Bidirectional

BDIP GPL_B5

TS E2 Bidirectional

TA F4 Bidirectional

TEA E3 Open-drain BI D2 Bidirectional

IRQ2 RSV

E8 Bidirectional

D1 Output

G2 Bidirectional

Bidirectional Three-state (3.3V only)

Three-state (3.3V only)

Active Pull-up (3.3V only)

Three-state (3.3V only)

IRQ4 KR RETRY SPKROUT

CR IRQ3

D[0:31] R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12,

DP0 IRQ3

DP1 IRQ4

DP2 IRQ5

DP3 IRQ6

BR E1 Bidirectional (3.3V only)

J1 Bidirectional

Three-state (3.3V only)

F1 Input (3.3 V only)

Bidirectional R12, M9, N9, P9, N1 1, T9, R8, P8, N8, T7, P1 1, P7, N7, M8, R1 1, R6, P6, T5, R5

P4 Bidirectional

P5 Bidirectional

T4 Bidirectional

R4 Bidirectional

MPC852T Hardware Specifications, Rev. 3.1

Three-state (3.3V only)

62 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 30. Pin Assignments - JEDEC Standard (continued)

Name Pin Number Type

BG G4 Bidirectional (3.3V only) BB F3 Bidirectional

Active Pull-up (3.3V only)

FRZ IRQ6

IRQ0 P13 Input (3.3V only) IRQ1 M11 Input (3.3V only) M_TX_CLK

IRQ7 CS[0:5] B2, A2, D3, C3, E6, C4 Output CS6 D4 Output CS7 A3 Output WE0

BS_B0 IORD

WE1 BS_B1 IOWR

WE2 BS_B2 PCOE

WE3 BS_B3 PCWE

BS_A[0:3] A6, D7, C7, B7 Output

H4 Bidirectional (3.3V only)

N12 Input (3.3V only)

D6 Output

C6 Output

A5 Output

B5 Output

GPL_A0 GPL_B0

OE GPL_A1 GPL_B1

GPL_A[2:3] GPL_B[2:3] CS[2–3]

UPWAITA GPL_A4

GPL_A5 E4 Output PORESET P1 Input (3.3V only) RSTCONF K4 Input (3.3V only) HRESET J4 Open-drain

Freescale Semiconduc tor 63

C5 Output

D5 Output

A4, B4 Output

C2 Bidirectional (3.3V only)

MPC852T Hardware Specifications, Rev. 3.1

Mechanical Data and Ordering Information

Table 30. Pin Assignments - JEDEC Standard (continued)

Name Pin Number Type

SRESET M3 Open-drain XTAL N1 Analog Output EXTAL M1 Analog Input (1.8V only) CLKOUT N6 Output EXTCLK N2 Input (1.8V only) ALE_A H1 Output CE1_A E5 Output CE2_A B3 Output WAIT_A N3 Input (3.3V only) IP_A0 T2 Input (3.3V only) IP_A1 M6 Input (3.3V only) IP_A2

IOIS16_A IP_A3 M5 Input (3.3V only) IP_A4 T3 Input (3.3V only) IP_A5 N5 Input (3.3V only) IP_A6 M7 Input (3.3V only) IP_A7 R2 Input (3.3V only) DSCK H2 Bidirectional

IWP[0:1] VFLS[0:1]

OP0 K1 Bidirectional (3.3V only) OP1 K2 Output OP2

MODCK1 STS

OP3 MODCK2 DSDO

R3 Input (3.3V only)

Three-state (3.3V only) H3, G1 Bidirectional (3.3V only)

K3 Bidirectional (3.3V only)

L1 Bidirectional (3.3V only)

BADDR[28:29] L3, L2 Output BADDR30

REG AS J2 Input (3.3V only) PA11

RXD3

64 Freescale Semiconductor

J3 Output

E16 Bidirectional

(Optional: Open-drain)

(5V tolerant)

MPC852T Hardware Specifications, Rev. 3.1

Mechanical Data and Ordering Information

Table 30. Pin Assignments - JEDEC Standard (continued)

Name Pin Number Type

PA10 TXD3

PA9 RXD4

PA8 TXD4

PA3 CLK5 BRGO3 TIN3

PA2 CLK6 TOUT3

PA1 CLK7 BRGO4 TIN4

PA0 CLK8 TOUT4

PB31 SPISEL

H15 Bidirectional

(5V tolerant) J16 Bidirectional

(Optional: Open-drain)

(5V tolerant) J15 Bidirectional

(5V tolerant) K16 Bidirectional

(5V tolerant)

K14 Bidirectional

(5V tolerant)

L15 Bidirectional

(5V tolerant)

M16 Bidirectional

(5V tolerant)

E13 Bidirectional

(Optional: Open-drain)

(5V tolerant)

PB30 SPICLK

PB29 SPIMOSI

PB28 SPIMISO BRGO4

PB25 SMTXD1

PB24 SMRXD1

PB15 BRGO3

Freescale Semiconduc tor 65

F13 Bidirectional

(Optional: Open-drain)

(5V tolerant) D15 Bidirectional

(Optional: Open-drain)

(5V tolerant) G13 Bidirectional

(Optional: Open-drain)

(5V tolerant) H14 Bidirectional

(Optional: Open-drain)

(5V tolerant) H16 Bidirectional

(Optional: Open-drain)

(5V tolerant) L16 Bidirectional

(5V tolerant)

MPC852T Hardware Specifications, Rev. 3.1

Mechanical Data and Ordering Information

Table 30. Pin Assignments - JEDEC Standard (continued)

Name Pin Number Type

PC15 DREQ0

PC13 RTS3

PC12 RTS4

PC7 CTS3

PC6 CD3

PC5 CTS4 SDACK1

PC4 CD4

PD15 MII_RXD3

PD14 MII_RXD2

PD13 MII_RXD1

C16 Bidirectional

(5V tolerant) E14 Bidirectional

(5V tolerant) E15 Bidirectional

(5V tolerant) J14 Bidirectional

(5V tolerant) K15 Bidirectional

(5V tolerant) J13 Bidirectional

(5V tolerant)

L14 Bidirectional

(5V tolerant) M14 Bidirectional

(5V tolerant) N16 Bidirectional

(5V tolerant) K13 Bidirectional

(5V tolerant)

PD12 MII_MDC

PD1 1 RXD3 MII_TX_ER

PD10 TXD3 MII_RXD0

PD9 RXD4 MII_TXD0

PD8 TXD4 MII_RX_CLK

PD7 RTS3 MII_RX_ER

N15 Bidirectional

(5V tolerant) P16 Bidirectional

(5V tolerant)

R15 Bidirectional

(5V tolerant)

N14 Bidirectional

(5V tolerant)

M13 Bidirectional

(5V tolerant)

T15 Bidirectional

(5V tolerant)

MPC852T Hardware Specifications, Rev. 3.1

66 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 30. Pin Assignments - JEDEC Standard (continued)

Name Pin Number Type

PD6 RTS4

N13 Bidirectional

(5V tolerant)

MII_RX_DV PD5

MII_TXD3 PD4

MII_TXD2 PD3

MII_TXD1

R14 Bidirectional

(5V tolerant) P14 Bidirectional

(5V tolerant) M12 Bidirectional

(5V tolerant)

TMS F15 Input

(5V tolerant)

TDI DSDI

TCK DSCK

G14 Input

(5V tolerant) H13 Input

(5V tolerant)

TRST F16 Input

(5V tolerant)

TDO DSDO

F14 Output

(5V tolerant)

MII_CRS B6 Input MII_MDIO G16 Bidirectional

(5V tolerant)

MII_TXEN T14 Output

(5V tolerant)

MII_COL F2 Input V

SSSYN

SSSYN1

DDSYN

GND G6, G7, G8, G9, G10, G1 1, H6, H7, H8 , H9, H10, H1 1 , J6, J7, J8, J9,

N4 PLL analog GND P3 PLL analog GND P2 PLL analog V

Power J10, J11, K6, K7, K8, K9, K10, K11

VDDL A7, C1, D16, G15, L4, M2, R1, M15, T8 Power VDDH F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12,

Power K5, K12, L5, L6, L7, L8, L9, L10, L11, L12

N/C A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 No-connect

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 67

Mechanical Data and Ordering Information

16.1.2 The non-JEDEC Pinout

Figure 63 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional

information, see the MPC866 PowerQUICC Family User’s Manual.

NOTE: This figure shows the top view of the device.

N/C

DDL

BDIP

VFLS_1 RSV BURST

ALE_A

OP0

OP3

BADDR29 BADDR28

EXTAL

XTAL EXTCLK WAIT_A

PORST V

DDL

N/C

CS7 GPL_A2 WE2 BS_A0 V

CS1

CS0

CE2_AGPL_A3 WE3

GPL_A4

CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C

CS2 OE

TEA

MII_COL

DSCK

VFLS_0

AS BADDR30

OP1

OP2

SRESET

DDL

VSSSYN1

DDSYN

IP_A7

IP_A2 PD10 N/CD31

IP_A0 IP_A4 DP2

MII_CRS BS_A3 A22 A30

GPL_A0

GPL_A5

CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0

FRZ

HRESET

RSTCONF

DDL

N/C

IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1

VSSSYN

IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT

DP0

DP3

D30

A28 A18 A23 A19 A14 A7 A2 A1 N/C

DDL

A29 A27 A13 A9 A6 A0 N/C

WE0 BS_A1 A24

D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1

D28

D7 D22 V

A31CS6

GND

D6 D19 D5 D2 D27 D13 D0 PD5

DDL

A20 A15 A10 A4 N/C PB29 V

D23

D18 D3 D1 D4 D8 MII_TXEN

DDH

PB31 PC13

PB30 TDO

PB28 TDI

TCK PB25

PC5 PC7

PD13 PA2

N/C PC4

PD8 PD15

PC15

DDL

PC12 PA11

TMS TRST

MDIO

DDL

PA10 PB24

PA8 PA9

PC6 PA3

PA1 PB15

PA0

DDL

PD12 PD14

N/C PD11

PD7 N/C

234567 8910111213141516

Figure 63. Pinout of the PBGA Package - non-JEDEC

MPC852T Hardware Specifications, Rev. 3.1

68 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments.

Table 31. Pin Assignments - non-JEDEC

Name Pin Number Type

A[0:31] C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F1 1, D13,

C13, B13, E12, F10, D12, B10, B12 , E11, D11, C9, B11, E10, D10, D9, C12, B9, C11, C10, E9

TSIZ0 REG

TSIZ1 F8 Bidirectional

RD/WR C2 Bidirectional

BURST H4 Bidirectional

BDIP GPL_B5

TS F3 Bidirectional

TA G5 Bidirectional

TEA F4 Open-drain BI E3 Bidirectional

F9 Bidirectional

E2 Output

Bidirectional Three-state (3.3 V only)

Three-state (3.3 V only)

Active Pull-up (3.3 V only)

IRQ2 RSV

IRQ4 KR RETRY SPKROUT

CR IRQ3

D[0:31] T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13,

DP0 IRQ3

DP1 IRQ4

DP2 IRQ5

DP3 IRQ6

H3 Bidirectional

K2 Bidirectional

G2 Input (3.3 V only)

T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9, T12, T7, R7, U6, T6

R5 Bidirectional

R6 Bidirectional

U5 Bidirectional

T5 Bidirectional

Three-state (3.3 V only)

Bidirectional Three-state (3.3 V only)

Three-state (3.3 V only)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 69

Mechanical Data and Ordering Information

Table 31. Pin Assignments - non-JEDEC (continued)

Name Pin Number Type

BR F2 Bidirectional (3.3 V only) BG H5 Bidirectional (3.3 V only) BB G4 Bidirectional

Active Pull-up (3.3 V only)

FRZ IRQ6

IRQ0 R14 Input (3.3 V only) IRQ1 N12 Input (3.3 V only) IRQ7

M_TX_CLK CS[0:5] C3, B3, E4, D4, F7, D5 Output CS6 E5 Output CS7 B4 Output WE0

BS_B0 IORD

WE1 BS_B1 IOWR

WE2 BS_B2 PCOE

WE3 BS_B3 PCWE

J5 Bidirectional (3.3 V only)

P13 Input (3.3 V only)

E7 Output

D7 Output

B6 Output

C6 Output

BS_A[0:3] B7, E8, D8, C8 Output GPL_A0

GPL_B0 OE

GPL_A1 GPL_B1

GPL_A[2:3] GPL_B[2:3] CS[2–3]

UPWAITA GPL_A4

GPL_A5 F5 Output PORESET R2 Input (3.3 V only)

70 Freescale Semiconductor

D6 Output

E6 Output

B5, C5 Output

D3 Bidirectional (3.3 V only)

MPC852T Hardware Specifications, Rev. 3.1

Mechanical Data and Ordering Information

Table 31. Pin Assignments - non-JEDEC (continued)

Name Pin Number Type

RSTCONF L5 Input (3.3 V only) HRESET K5 Open-drain SRESET N4 Open-drain XTAL P2 Analog Output EXTAL N2 Analog Input (3.3 V only) CLKOUT P7 Output EXTCLK P3 Input (3.3 V only) ALE_A J2 Output CE1_A F6 Output CE2_A C4 Output WAIT_A P4 Input (3.3 V only) IP_A0 U3 Input (3.3 V only) IP_A1 N7 Input (3.3 V only) IP_A2

IOIS16_A IP_A3 N6 Input (3.3 V only) IP_A4 U4 Input (3.3 V only) IP_A5 P6 Input (3.3 V only) IP_A6 N8 Input (3.3 V only) IP_A7 T3 Input (3.3 V only) DSCK J3 Bidirectional

IWP[0:1] VFLS[0:1]

OP0 L2 Bidirectional (3.3 V only) OP1 L3 Output OP2

MODCK1 STS

OP3 MODCK2 DSDO

T4 Input (3.3 V only)

Three-state (3.3 V only)

J4, H2 Bidirectional (3.3 V only)

L4 Bidirectional (3.3 V only)

M2 Bidirectional (3.3 V only)

BADDR[28:29] M4, M3 Output BADDR30

REG

Freescale Semiconduc tor 71

K4 Output

MPC852T Hardware Specifications, Rev. 3.1

Mechanical Data and Ordering Information

Table 31. Pin Assignments - non-JEDEC (continued)

Name Pin Number Type

AS K3 Input (3.3 V only) PA11

RXD3

PA10 TXD3

PA9 RXD4

PA8 TXD4

PA3 CLK5 BRGO3 TIN3

PA2 CLK6 TOUT3

PA1 CLK7 BRGO4 TIN4

F17 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

J16 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

K17 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

K16 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

L17 Bidirectional

(5 V-tolerant)

L15 Bidirectional

(5 V-tolerant)

M16 Bidirectional

(5 V-tolerant)

PA0 CLK8 TOUT4

PB31 SPISEL

PB30 SPICLK

PB29 SPIMOSI

PB28 SPIMISO BRGO4

72 Freescale Semiconductor

N17 Bidirectional

(5 V-tolerant)

F14 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

G14 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

E16 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

H14 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

MPC852T Hardware Specifications, Rev. 3.1

Mechanical Data and Ordering Information

Table 31. Pin Assignments - non-JEDEC (continued)

Name Pin Number Type

PB25 SMTXD1

PB24 SMRXD1

PB15 BRGO3

PC15 DREQ0

PC13 RTS3

PC12 RTS4

PC7 CTS3

PC6 CD3

PC5 CTS4 SDACK1

J15 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

J17 Bidirectional

(Optional: Open-drai n) (5 V-tolerant)

M17 Bidirectional

(5 V-tolerant)

D17 Bidirectional

(5 V-tolerant)

F15 Bidirectional

(5 V-tolerant)

F16 Bidirectional

(5 V-tolerant)

K15 Bidirectional

(5 V-tolerant)

L16 Bidirectional

(5 V-tolerant)

K14 Bidirectional

(5 V-tolerant)

PC4 CD4

PD15 MII_RXD3

PD14 MII_RXD2

PD13 MII_RXD1

PD12 MII_MDC

PD1 1 RXD3 MII_TX_ER

PD10 TXD3 MII_RXD0

M15 Bidirectional

(5 V-tolerant)

N15 Bidirectional

(5 V-tolerant)

P17 Bidirectional

(5 V-tolerant)

L14 Bidirectional

(5 V-tolerant)

P16 Bidirectional

(5 V-tolerant)

R17 Bidirectional

(5 V-tolerant)

T16 Bidirectional

(5 V-tolerant)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 73

Mechanical Data and Ordering Information

Table 31. Pin Assignments - non-JEDEC (continued)

Name Pin Number Type

PD9 RXD4

P15 Bidirectional

(5 V-tolerant)

MII_TXD0 PD8

TXD4

N14 Bidirectional

(5 V-tolerant)

MII_RX_CLK PD7

RTS3

U16 Bidirectional

(5 V-tolerant)

MII_RX_ER PD6

RTS4

P14 Bidirectional

(5 V-tolerant)

MII_RX_DV PD5

MII_TXD3 PD4

MII_TXD2 PD3

MII_TXD1

T15 Bidirectional

(5 V-tolerant)

R15 Bidirectional

(5 V-tolerant)

N13 Bidirectional

(5 V-tolerant)

TMS G16 Input

(5 V-tolerant)

TDI DSDI

TCK DSCK

H15 Input

(5 V-tolerant)

J14 Input

(5 V-tolerant)

TRST G17 Input

(5 V-tolerant)

TDO DSDO

G15 Output

(5 V-tolerant) MII_CRS C7 Input MII_MDIO H17 Bidirectional

(5 V-tolerant) MII_TX_EN U15 Output

(5 V-tolerant) MII_COL G3 Input V

SSSYN

SSSYN1

DDSYN

P5 PLL analog GND R4 PLL analog GND R3 PLL analog V

MPC852T Hardware Specifications, Rev. 3.1

74 Freescale Semiconductor

Mechanical Data and Ordering Information

Table 31. Pin Assignments - non-JEDEC (continued)

Name Pin Number Type

GND H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9,

Power

K10, K11, K12, L7, L8, L9, L10, L11, L12 V V

DDL

DDH

B8, D2, E17, H16, M5, N3, T2, N16, U9 Power

G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13,

Power

L6, L13, M6, M7, M8, M9, M10, M11, M12, M13 N/C B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 No-connect

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 75

Mechanical Data and Ordering Information

16.2 Mechanical Dimensions of the PBGA Package

For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, ref er to Plastic Ball Grid Array Applicati on Note (order number: AN1231/D) that is ava ilable from your local Motorola sales office.

Figure 64 shows the mechanical dimensions of the PBGA package.

MPC852T Hardware Specifications, Rev. 3.1

76 Freescale Semiconductor

Mechanical Data and Ordering Information

NOTES:

1. All dimensions are in millimeters.

2. Interpret dimensions and tolerances per ASME Y14.5M —1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

Note: Solder sphere composition is 95.5% Sn 45%Ag 0.5%Cu for MPC852T VRX XX.

Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX.

Figure 64. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 77

Document Revision History

17 Document Revision History

Table 32 lists significant changes between revisions of this document.

Table 32. Document Revision History

Revision Date Changes

3.1 1/18/2005 Document template update.

3.0 11/2004 • Added sentence to S pec B1A a bout EXTCLK and CLKOUT be ing in Alignment for Integer Values

• Added a footnote to Spec 41 specifying that EDM = 1

• Broke the Section 16.1, “Pin Assignments,” into 2 smaller sections for the JEDEC and non-JEDEC pinouts.

2.0 12/2003 Put 852T on the 1st page in place of 8245. Figure 62 on pag e 5 9 ha d overbars added o n s ig nal s C R ( pin G 2) a nd

WAIT_A (pin P4).

1.8 7/2003 Changed the pinout to be JEDEC Compliant, changed timing parameters B28a through B28d, and B29d to show tha t TRLX can be 0 or 1.

1.7 5/2003 Changed the SPI Master Timing Specs. 162 and 164

1.6 4/2003 Changed the package draw ing in Figure 15-63

1.5 4/2003 Changed 5 Port C pins with interrup t cap abi lity to 7 Port C pi ns. Add ed the Note: solder sphere composition for MPC852TVR and MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63

1.4 2/2003 Changed Table 15-30 Pin Assignments for the PLL Pins V V

1.3 1/2003 Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific edges.

1.2 1/2003 In Table 15-30, specified EXTCLK as 3.3 V.

1.1 12/2002 Added fast Ethernet controller to the features

1 11/2002 Added values for 80 and 100 MHz 0 10/2002 Initial release

SSSYN

, V

DDSYN

SSSYN1

MPC852T Hardware Specifications, Rev. 3.1

78 Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Document Revision History

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconduc tor 79

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MPC852TEC Rev. 3.1 01/2005

Freescale MPC852T service manual

Specifications and Main Features

Frequently Asked Questions

User Manual

MPC852T Hardware Specifications

1Overview

2Features

Figure 1. MPC852T Block Diagram

3 Maximum Tolerated Ratings

Table 1. Maximum Tolerated Ratings

Table 2. Operating Temperatures

4 Thermal Characteristics

Table 3. MPC852T Thermal Resistance Data

5 Power Dissipation

Table 4. Power Dissipation (PD)

6 DC Characteristics

Table 5. DC Electrical Specifications

7 Thermal Calculation and Measurement

7.1 Estimation with Junction-to-Ambient Thermal Resistance

7.2 Estimation with Junction-to-Case Thermal Resistance

7.3 Estimation with Junction-to-Board Thermal Resistance

7.4 Estimation Using Simulation

7.5 Experimental Determination

8 References

9 Power Supply and Power Sequencing

Figure 2. Example Voltage Sequencing Circuit

10 Mandatory Reset Configurations

Table 6. Mandatory Reset Configuration of MPC852T

11 Layout Practices

12 Bus Signal Timing

Table 7. Frequency Ranges for Standa rd Part Frequencies (1:1 Bus Mode)

Table 8. Frequency Ranges for Standa rd Part Frequencies (2:1 Bus Mode)

Table 9. Bus Operation Timings

Figure 3. Control Timing

Figure 4. External Clock Timing

Figure 5. Synchronous Output Signals Timing

Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

Figure 7. Synchronous Input Signals Timing

Figure 8. Input Data Timing in Normal Case

Figure 9. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1

Figure 17. External Bus Timing (UPM Controlled Signals)

Figure 18. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Table 10. Interrupt Timing

Figure 23. Interrupt Detection Timing for External Level Sensitive Lines

Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines

Table 11. PCMCIA Timing

Figure 25. PCMCIA Access Cycles Timing External Bus Read

Figure 26. PCMCIA Access Cycles Timing External Bus Write

Figure 27. PCMCIA WAIT Signals Detection Timing

Table 12. PCMCIA Port Timing

Figure 28. PCMCIA Output Port Timing

Figure 29. PCMCIA Input Port Timing

Table 13. Debug Port Timing

Figure 30. Debug Port Clock Input Timing

Figure 31. Debug Port Timings

Table 14. Reset Timing

13 IEEE 1149.1 Electrical Specifications

Table 15. JTAG Timing

Figure 35. JTAG Test Clock Input Timing

Figure 36. JTAG Test Access Port Timing Diagram

Figure 37. JTAG TRST Timing Diagram

Figure 38. Boundary Scan (JTAG) Timing Diagram

14 CPM Electrical Characteristics

14.1 Port C Interrupt AC Electrical Specifications

Table 16. Port C Interrupt Timing

Figure 39. Port C Interrupt Detection Timing

14.2 IDMA Controller AC Electrical Specifications

Table 17. IDMA Controller Timing

Figure 40. IDMA External Requests Timing Diagram

14.3 Baud Rate Generator AC Electrical Specifications

Table 18. Baud Rate Generator Timing

Figure 44. Baud Rate Generator Timing Diagram

14.4 Timer AC Electrical Specifications

Table 19. Time r Timing

Figure 45. CPM General-Purpose Timers Timing Diagram

14.5 SCC in NMSI Mode Electrical Specifications

Table 20. NMSI External Clock Timing

Table 21. NMSI Inte rnal Clo ck Timing