Freescale MPC850 User Manual

Freescale Semiconductor

Technical Data

Document Number: MPC850EC

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications

Rev. 2, 07/2005

This document contains detailed information on power
considerations, AC/DC electrical characteristics, and AC
timing specifications for revision A,B, and C of the MPC850
Family.

1Overview

The MPC850 is a versatile, one-chip integrated
microprocessor and peripheral combination that can be used
in a variety of controller applications, excelling particularly
in communications and networking products. The MPC850,
which includes support for Ethernet, is specifically designed
for cost-sensitive, remote-access, and telecommunications
applications. It is provides functions similar to the MPC860,
with system enhancements such as universal serial bus
(USB) support and a larger (8-Kbyte) dual-port RAM.

In addition to a high-performance embedded MPC8xx core,
the MPC850 integrates system functions, s uch as a versatile
memory controller and a communications pr ocessor module
(CPM) that incorporates a specialized, independent RISC
communications processor (referred to as the CP). This
separate processor off-loads peripheral tasks from the
embedded MPC8xx core.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. Electrical and Thermal Characteristics . . . . . . . . . . . . 7

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8

5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 9

6. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 39

8. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 41

9. Mechanical Data and O rdering Information . . . . . . . 63

10. Document Revision History . . . . . . . . . . . . . . . . . . . 68

© Freescale Semiconductor, Inc., 2005. All rights reserved.

Overview

The CPM of the MPC850 supports up to seven serial channels, as follows:

• One or two serial communications controllers (SCCs). The SCCs support Ethernet, A T M
(MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent
mode of operation.

• One USB channel

• Two serial management controllers (SMCs)

2

• One I

C port

• One serial peripheral interface (SPI).

Table 1 shows the functionality supported by the members of the MPC850 family.

Table 1. MPC850 Functionality Matrix

Number of

Part

MPC850 1 Yes - Yes - 1

MPC850DE 2 Yes - Yes - 1

MPC850SR 2 Yes Yes Yes Yes 1

MPC850DSL 2 Yes Yes Yes No 1

SCCs

Supported

Ethernet

Support

ATM Support USB Support

Multi-channel

HDLC

Support

Additional documentation may be provided for parts listed in Table 1.

Number of

PCMCIA Slots

Supported

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

2 Freescale Semiconductor

Features

2Features

Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among

those components:

Embedded

MPC8xx

Core

Baud Rate

Generators

Paralle l I/O

Ports

—

UTOPIA

(850SR & DSL)

2-Kbyte
I-Cache

Instruction

Bus

Load/Store

Bus

Four

Timers

32-Bit RISC Communications

Processor (CP) and Pr ogram ROM

Timer

Instruction

MMU

1-Kbyte

D-Cache

Data

MMU

Interrupt

Controller

Dual-Port

RAM

Unified Bus

Peripheral Bus

20 Virtual

Serial DMA

Channels

and

2 Virtu al

IDMA

Channels

System Interface Un it

Memory Controller

Bus Inte rf ace Unit
System Functions

Real-Ti m e C lock

PCMCIA Interface

Communications

Processor

Module

TDMa

SCC2

SCC3

Time Slot Assigner

SMC1 SMC2

USB

Non-Multiplexed Serial Interface

SPI

2

I

C

Figure 1. MPC850 Microprocessor Block Diagram

The following list summarizes the main features of the MPC850:

• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)

— Perfor ms branch folding and branch prediction with conditional prefetch, but without

conditional execution

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 3

Features

— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)

– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity

— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and

fully-associative instruction and data TLBs

— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and

8 Mbytes; 16 virtual address spaces and eight protection groups

• Advanced on-chip emulation debug mode

• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian

memory systems

— Twenty-six external address lines

• Completely static design (0–80 MHz operation)

• System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— S oftware watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)

• Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM

(SDRAM), static random-access memory (SRAM), electrically programmable read-only

memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support

• General-purpose timers
— Four 16-bit timers or two 32-bit timers

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

4 Freescale Semiconductor

— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture

• Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request

• Si n gle so ck et PCMCIA- ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PC MC IA socke t
— Supports eight memory or I/O windows

• Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission

after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD
closes the receive buffer descriptor)

Features

— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four

USB endpoints

— Three parallel I/O registers with open-drain capability

• Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option

• Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)

®

— AppleTalk
— Univer sal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 5

Features

• QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel

• One universal serial bus controller (USB)
— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps

• Two serial management controllers (SMCs)
— UART
— Transparent
— Gener al circuit i nte rface ( GCI ) controller
— Can be connected to the time-division-multiplexed (TDM) channel

• One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus

• One I2C® (interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment

• Time slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internall y connected to four serial channels (two SCCs and two SMCs)

• Low-power support
— Full high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze: core functional units disabled except time base, decrementer, PLL, memory controller ,

real-time clock, and CPM in low-power standby

— Sleep: all units disabled except real-time clock and periodic interrupt timer . PLL is active for

fast wake-up

— Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt

timer

— Low-power stop: to provide lower power dissipation

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

6 Freescale Semiconductor

Electrical and Thermal Characterist ics

— Separate power supply input to operate internal logic at 2.2 V when operating at or below

25 MHz

— Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V

internal) operation

• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data
— The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints
— Eac h watchpoint can generate a breakpoint internally

• 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins.

3 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850.

Table 2 provides the maximum ratings.

Table 2. Maximum Ratings

(GND = 0V)

Rating Symbol Value Unit

Supply voltage VDDH -0.3 to 4.0 V

VDDL -0.3 to 4.0 V

KAPWR -0.3 to 4.0 V

VDDSYN -0.3 to 4.0 V

Input voltage

Junction temperature

Storage temperature range T

1

Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction
applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not
be applied to its inputs).

2

The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient
temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power
dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of
the device.

1

2

V

in

T

j

stg

GND-0.3 to VDDH + 2.5 V V

0 to 95 (standard)

-40 to 95 (extended)

-55 to +150 °C

°C

This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V

). Table 3 provides

CC

the package thermal characteristics for the MPC850.

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 7

Thermal Characteristics

4 Thermal Characteristics

Table 3 shows the thermal characteristics for the MPC850.

Table 3. Thermal Characteristics

Characteristic Symbol Value Unit

Thermal resistance for BGA

Thermal Resistance for BGA (junction-to-case) θ

1

For more information on the design of thermal vias on multilayer boards and BGA layout considerations in

general, refer to AN-1231/D, Plastic Ball Grid Array Applicati on Note available from your local Motorola sales
office.

2

Assumes natural convection and a single layer board (no thermal vias).

3

Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board

temperature rise of 20°C above ambient.

4

Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board

temperature rise of 13°C above ambient.
T

= T

J

P

= (VDD • IDD) + P

D

where:

P

is the power dissipation on pins

I/O

A

+ (P

•θJA)

D

1

I/O

θ

JA

θ

31

JA

θ

JA

JC

2

40

24

3

4

°C/W

°C/W

°C/W

8 °C/W

Table 4 provides power dissipation information.

Table 4. Power Dissipation (PD)

Characteristic Frequency (MHz) Typical

Power Dissipation

All Revisions

33 TBD 515 mW

40 TBD 590 mW

(1:1) Mode

50 TBD 725 mW

1

Typical power dissipation is measured at 3.3V

2

Maximum power dissipation is measured at 3.65 V

1

Table 5 provides the DC electrical characteristics for the MPC850.

Table 5. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Operating voltage at 40 MHz or less VDDH, VDDL,

KAPWR, VDDSYN

Operating voltage at 40 MHz or higher VDDH, VDDL,

KAPWR, VDDSYN

Input high voltage (address bus, data bus, EXTAL, EXTCLK,
and all bus control/status signals)

VIH 2.0 3.6 V

Maximum

2

Unit

3.0 3.6 V

3.135 3.465 V

Input high voltage (all general purpose I/O and peripheral pins) VIH 2.0 5.5 V

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

8 Freescale Semiconductor

Power Considerations

Table 5. DC Electrical Specifications (continued)

Characteristic Symbol Min Max Unit

Input low voltage VIL GND 0.8 V

EXTAL, EXTCLK input high voltage VIHC 0.7*(VCC) VCC+0.3 V

Input leakage current, Vin = 5.5 V (Except TMS, TRST
and DSDI pins)

Input leakage current, Vin = 3.6V (Except TMS, TRST
and DSDI pins)

Input leakage current, Vin = 0V (Except TMS, TRST
and DSDI pins)

Input capacitance C

Output high voltage, IOH = -2.0 mA, VDDH = 3.0V
except XTAL, XFC, and open-drain pins

Output low voltage
CLKOUT

IOL = 3.2 mA
IOL = 5.3 mA
IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2
IOL = 8.9 mA TS

1

IP_B2/IOIS16_B
PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2,
PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/TOUT1
PA[4]/CLK4/TOUT2
PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3,
PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1
PB[18]/RTS2
PC[13]/L1ST7/RTS3
PC[8]/CD2
PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3]

2

WE2
GPL_A
OP2/MODCK1/STS

3 The MPC850 IBIS model must be used to accurately model the behavior of the Clkout output driver for the full and

half drive setting. Due to the nature of the Clkout output buffer, IOH and IOL for Clkout should be extracted from the
IBIS model at any output voltage level.

3

1

2

, TA, TEA, BI, BB, HRESET, SRESET

A[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1],

/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,

/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3,

/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1,

/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6,

, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2,

/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA,

BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR,

/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,

[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1,

, OP3/MODCK2/DSDO

, DSCK

, DSCK

, DSCK

/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2,

I

in

I

In

I

In

in

VOH 2.4 — V

VOL — 0.5 V

— 100 µA

—10µA

—10µA

—20pF

5 Power Considerations

The average chip-junction temperature, T
T

= TA + (P

J

θ

)(1)

•

D

JA

where

= Ambient temperature, °C

T

A

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 9

, in °C can be obtained from the equation:

J

Bus Signal Timing

θ

= Package thermal resista nce , junction to ambient, °C/W

JA

PD = P
P

INT

P

I/O

For most applications P
relationship between P

PD = K ÷ (T

+ P

INT

= IDD x V

I/O

, watts—chip internal power

DD

= Power dissipation on input and output pins—user determined

+ 273°C)(2)

J

< 0.3 • P

I/O

and TJ is:

D

and can be neglected. If P

INT

I/O

is neglected, an approximate

Solving equations (1) and (2) for K gives:
K = PD • (T

+ 273°C) + θ

A

JA

• P

2

(3)

D

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations (1) and (2) iteratively for any value of TA.

5.1 Layout Practices

Each VCC pin on the MPC850 should be provided with a low-i mpedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four

0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.

All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particula rly applies to the a ddres s and data busses. Maxim um PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in syst ems with higher capacit ive loads because th ese lo ads cr eate hi gher tran sient
currents in the V

and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

CC

Special care should be taken to minimize the noise levels on the PLL supply pins.

6 Bus Signal Timing

Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing

information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.

The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).

The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10
pF . Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

10 Freescale Semiconductor

Table 6. Bus Operation Timing 1

Bus Signal Timing

Num Characteristic

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

Cap Load

(default

50 pF)

B1 CLKOUT period 20 — 30.30 — 25 — — — ns

B1a EXTCLK to CLKOUT phase

-0.90 0.90 -0.90 0.90 -0.90 0.90 — 50.00 ns
skew (EXTCLK > 15 MHz and
MF <= 2)

B1b EXTCLK to CLKOUT phase

-2.30 2.30 -2.30 2.30 -2.30 2.30 — 50.00 ns
skew (EXTCLK > 10 MHz and
MF < 10)

B1c CLKOUT phase jitter (EXTCLK

> 15 MHz and MF <= 2)

B1d CLKOUT phase jitter

B1e CLKOUT frequency jitter (MF <

B1f CLKOUT frequency jitter (10 <

B1g CLKOUT frequency jitter (MF >

2

10)

MF < 500)

2

500)

2

2

2

B1h Frequency jitter on EXTCLK

-0.60 0.60 -0.60 0.60 -0.60 0.60 — 50.00 ns

-2.00 2.00 -2.00 2.00 -2.00 2.00 — 50.00 ns

— 0.50 — 0.50 — 0.50 — 50.00 %

— 2.00 — 2.00 — 2.00 — 50.00 %

— 3.00 — 3.00 — 3.00 — 50.00 %

3

— 0.50 — 0.50 — 0.50 — 50.00 %

Unit

B2 CLKOUT pulse width low 8.00 — 12.12 — 10.00 — — 50.00 ns

B3 CLKOUT width high 8.00 — 12.12 — 10.00 — — 50.00 ns

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 50.00 ns

B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 50.00 ns

B7 CLKOUT to A[6–31],

RD/WR

, BURST, D[0–31],

5.00 — 7.58 — 6.25 — 0.250 50.00 ns

DP[0–3] invalid

B7a CLKOUT to TSIZ[0–1], REG

RSV

, AT[0–3], BDIP, PTR

5.00 — 7.58 — 6.25 — 0.250 50.00 ns

,

invalid

B7b CLKOUT to BR

VFLS[0–1], VF[0–2] IWP[0–2],
LWP[0–1], STS

B8 CLKOUT to A[6–31],

RD/WR

, BURST, D[0–31],

, BG, FRZ,

invalid

4

5.00 — 7.58 — 6.25 — 0.250 50.00 ns

5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns

DP[0–3] valid

B8a CLKOUT to TSIZ[0–1], REG

RSV

, AT[0–3] BDIP, PTR valid

B8b CLKOUT to BR

, BG,
VFLS[0–1], VF[0–2], IWP[0–2],
FRZ, LWP[0–1], STS

valid

,

5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns

5.00 11.74 7.58 14.33 6.25 13.00 0.250 50.00 ns

4

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 11

Bus Signal Timing

Table 6. Bus Operation Timing 1 (continued)

Num Characteristic

B9 CLKOUT to A[6–31] RD/WR,

BURST

, D[0–31], DP[0–3],
TSIZ[0–1], REG
PTR

high-Z

B11 CLKOUT to TS

B11a CLKOUT to TA

, RSV, AT[0–3],

, BB assertion 5.00 11.00 7.58 13.58 6.25 12.25 0.250 50.00 ns

, BI assertion,
(When driven by the memory
controller or PCMCIA interface)

B12 CLKOUT to TS

B12a CLKOUT to TA

, BB negation 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns

, BI negation
(when driven by the memory
controller or PCMCIA interface)

B13 CLKOUT to TS

B13a CLKOUT to TA

, BB high-Z 5.00 19.00 7.58 21.58 6.25 20.25 0.250 50.00 ns

, BI high-Z,
(when driven by the memory
controller or PCMCIA interface)

B14 CLKOUT to TEA

B15 CLKOUT to TEA

assertion 2.50 10.00 2.50 10.00 2.50 10.00 — 50.00 ns

high-Z 2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

Cap Load

(default

50 pF)

Unit

5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns

2.50 9.25 2.50 9.25 2.50 9.25 — 50.00 ns

2.50 11.00 2.50 11.00 2.50 11.00 — 50.00 ns

2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns

B16 TA

B16a TEA

B16b BB

B17 CLKOUT to TA

B17a CLKOUT to KR

, BI valid to CLKOUT(setup

5

time)

, KR, RETRY, valid to

CLKOUT (setup time

, BG, BR valid to CLKOUT

(setup time)

6

) 5

, TEA, BI, BB,
BG

, BR valid (Hold time).

, RETRY, except
TEA

valid (hold time)

B18 D[0–31], DP[0–3] valid to

CLKOUT rising edge (setup

7

time)

B19 CLKOUT rising edge to

D[0–31], DP[0–3] valid (hold

7

time)

B20 D[0–31], DP[0–3] valid to

CLKOUT falling edge (setup

8

time)

B21 CLKOUT falling edge to

D[0–31], DP[0–3] valid (hold

8

time)

9.75 — 9.75 — 9.75 — — 50.00 ns

10.00 — 10.00 — 10.00 — — 50.00 ns

8.50 — 8.50 — 8.50 — — 50.00 ns

5

1.00 — 1.00 — 1.00 — — 50.00 ns

2.00 — 2.00 — 2.00 — — 50.00 ns

6.00 — 6.00 — 6.00 — — 50.00 ns

1.00 — 1.00 — 1.00 — — 50.00 ns

4.00 — 4.00 — 4.00 — — 50.00 ns

2.00 — 2.00 — 2.00 — — — —

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

12 Freescale Semiconductor

Table 6. Bus Operation Timing 1 (continued)

Bus Signal Timing

Num Characteristic

B22 CLKOUT rising edge to CS

asserted GPCM ACS = 00

B22a CLKOUT falling edge to CS

asserted GPCM ACS = 10,
TRLX = 0,1

B22b CLKOUT falling edge to CS

asserted GPCM ACS = 11,
TRLX = 0, EBDF = 0

B22c CLKOUT falling edge to CS

asserted GPCM ACS = 11,
TRLX = 0, EBDF = 1

B23 CLKOUT rising edge to CS

negated GPCM read access,
GPCM write access ACS = 00,
TRLX = 0 & CSNT = 0

B24 A[6–31] to CS

ACS = 10, TRLX = 0.

B24a A[6–31] to CS

ACS = 11, TRLX = 0

asserted GPCM

asserted GPCM

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns

— 8.00 — 8.00 — 8.00 — 50.00 ns

5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns

7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns

2.00 8.00 2.00 8.00 2.00 8.00 — 50.00 ns

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

8.00 — 13.00 — 11.00 — 0.500 50.00 ns

Cap Load

(default

Unit

50 pF)

B25 CLKOUT rising edge to OE

WE[0–3]

B26 CLKOUT rising edge to OE

negated

B27 A[6–31] to CS

ACS = 10, TRLX = 1

B27a A[6–31] to CS

ACS = 11, TRLX = 1

B28 CLKOUT rising edge to

WE[0–3]
access CSNT = 0

B28a CLKOUT falling edge to

WE[0–3]
access TRLX = 0,1 CSNT = 1,
EBDF = 0

B28b CLKOUT falling edge to CS

negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 0

asserted

asserted GPCM

asserted GPCM

negated GPCM write

negated GPCM write

,

— 9.00 — 9.00 — 9.00 — 50.00 ns

2.00 9.00 2.00 9.00 2.00 9.00 — 50.00 ns

23.00 — 36.00 — 29.00 — 1.250 50.00 ns

28.00 — 43.00 — 36.00 — 1.500 50.00 ns

— 9.00 — 9.00 — 9.00 — 50.00 ns

5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns

— 12.00 — 14.00 — 13.00 0.250 50.00 ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 13

Bus Signal Timing

Table 6. Bus Operation Timing 1 (continued)

Num Characteristic

B28c CLKOUT falling edge to

WE[0–3]
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1

B28d CLKOUT falling edge to CS

negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 1

B29 WE[0–3]

DP[0–3] high-Z GPCM write
access, CSNT = 0

B29a WE[0–3]

DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0

B29b CS

DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0

negated GPCM write

negated to D[0–31],

negated to D[0–31],

negated to D[0–31],

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns

— 14.00 — 18.00 — 16.00 0.375 50.00 ns

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

8.00 — 13.00 — 11.00 — 0.500 50.00 ns

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

Cap Load

(default

50 pF)

Unit

B29c CS

B29d WE[0–3]

B29e CS

B29f WE[0–3]

B29g CS

negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0

DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0

negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0

DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1

negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1

negated to D[0–31],

negated to D[0–31],

8.00 — 13.00 — 11.00 — 0.500 50.00 ns

28.00 — 43.00 — 36.00 — 1.500 50.00 ns

28.00 — 43.00 — 36.00 — 1.500 50.00 ns

5.00 — 9.00 — 7.00 — 0.375 50.00 ns

5.00 — 9.00 — 7.00 — 0.375 50.00 ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

14 Freescale Semiconductor

Table 6. Bus Operation Timing 1 (continued)

Bus Signal Timing

Num Characteristic

B29h WE[0–3] negated to D[0–31],

DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1

B29i CS

negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1

B30 CS

, WE[0–3] negated to
A[6–31] invalid

GPCM write access

B30a WE[0–3]

negated to A[6–31]

9

invalid
GPCM write access, TRLX = 0,

CSNT = 1, CS

negated to
A[6–31] invalid GPCM write
access TRLX = 0, CSNT =1,
ACS = 10 or ACS = 11, EBDF =
0

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

Cap Load

(default

50 pF)

Unit

25.00 — 39.00 — 31.00 — 1.375 50.00 ns

25.00 — 39.00 — 31.00 — 1.375 50.00 ns

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

8.00 — 13.00 — 11.00 — 0.500 50.00 ns

B30b WE[0–3]

invalid
GPCM write access, TRLX = 1,

CSNT = 1. CS
A[6–31] Invalid GPCM write
access TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0

B30c WE[0–3]

invalid

GPCM write access, TRLX = 0,
CSNT = 1. CS
A[6–31] invalid GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1

B30d WE[0–3]

invalid GPCM write access
TRLX = 1, CSNT =1, CS
negated to A[6–31] invalid
GPCM write access TRLX = 1,
CSNT = 1, ACS = 10 or ACS =
11, EBDF = 1

negated to A[6–31]

negated to

negated to A[6–31]

negated to

negated to A[6–31]

28.00 — 43.00 — 36.00 — 1.500 50.00 ns

5.00 — 8.00 — 6.00 — 0.375 50.00 ns

25.00 — 39.00 — 31.00 — 1.375 50.00 ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 15

Bus Signal Timing

Table 6. Bus Operation Timing 1 (continued)

Num Characteristic

B31 CLKOUT falling edge to CS

valid - as requested by control
bit CST4 in the corresponding
word in the UPM

B31a CLKOUT falling edge to CS

valid - as requested by control
bit CST1 in the corresponding
word in the UPM

B31b CLKOUT rising edge to CS

- as requested by control bit
CST2 in the corresponding
word in the UPM

B31c CLKOUT rising edge to CS

- as requested by control bit
CST3 in the corresponding
word in the UPM

B31d CLKOUT falling edge to CS

valid - as requested by control
bit CST1 in the corresponding
word in the UPM EBDF = 1

valid

valid

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns

5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns

1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns

5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns

9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns

Cap Load

(default

50 pF)

Unit

B32 CLKOUT falling edge to BS

valid - as requested by control
bit BST4 in the corresponding
word in the UPM

B32a CLKOUT falling edge to BS

valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 0

B32b CLKOUT rising edge to BS

- as requested by control bit
BST2 in the corresponding
word in the UPM

B32c CLKOUT rising edge to BS

- as requested by control bit
BST3 in the corresponding
word in the UPM

B32d CLKOUT falling edge to BS

valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 1

B33 CLKOUT falling edge to GPL

valid - as requested by control
bit GxT4 in the corresponding
word in the UPM

valid

valid

1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns

5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns

1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns

5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns

9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns

1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

16 Freescale Semiconductor

Table 6. Bus Operation Timing 1 (continued)

Bus Signal Timing

Num Characteristic

B33a CLKOUT rising edge to GPL

valid - as requested by control
bit GxT3 in the corresponding
word in the UPM

B34 A[6–31] and D[0–31] to CS

valid

- as requested by control bit
CST4 in the corresponding
word in the UPM

B34a A[6–31] and D[0–31] to CS

valid

- as requested by control bit
CST1 in the corresponding
word in the UPM

B34b A[6–31] and D[0–31] to CS

valid

- as requested by CST2 in the
corresponding word in UPM

B35 A[6–31] to CS

valid - as
requested by control bit BST4 in
the corresponding word in UPM

B35a A[6–31] and D[0–31] to BS

valid

- as requested by BST1 in the
corresponding word in the UPM

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

Cap Load

(default

50 pF)

Unit

5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

8.00 — 13.00 — 11.00 — 0.500 50.00 ns

13.00 — 21.00 — 17.00 — 0.750 50.00 ns

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

8.00 — 13.00 — 11.00 — 0.500 50.00 ns

B35b A[6–31] and D[0–31] to BS

- as requested by control bit
BST2 in the corresponding
word in the UPM

B36 A[6–31] and D[0–31] to GPL

valid - as requested by control
bit GxT4 in the corresponding
word in the UPM

B37 UPWAIT valid to CLKOUT

falling edge

B38 CLKOUT falling edge to

UPWAIT valid

B39 AS

valid to CLKOUT rising edge

11

10

10

B40 A[6–31], TSIZ[0–1], RD/WR

BURST

, valid to CLKOUT rising

edge.

B41 TS

valid to CLKOUT rising edge

(setup time)

13.00 — 21.00 — 17.00 — 0.750 50.00 ns

valid

3.00 — 6.00 — 4.00 — 0.250 50.00 ns

6.00 — 6.00 — 6.00 — — 50.00 ns

1.00 — 1.00 — 1.00 — — 50.00 ns

7.00 — 7.00 — 7.00 — — 50.00 ns

7.00 — 7.00 — 7.00 — — 50.00 ns

,

7.00 — 7.00 — 7.00 — — 50.00 ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 17

Bus Signal Timing

Table 6. Bus Operation Timing 1 (continued)

Num Characteristic

B42 CLKOUT rising edge to TS valid

50 MHz 66 MHz 80 MHz

FFACT

Min Max Min Max Min Max

2.00 — 2.00 — 2.00 — — 50.00 ns

Cap Load

(default

50 pF)

(hold time)

B43 AS

negation to memory

—TBD—TBDTBD— — 50.00 ns

controller signals negation

1

The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on
the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to
be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the
part. The following equations should be used in these calculations.

For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:

FFACTOR x 1000

D =

F

(D

- 20 x FFACTOR)

50

+

For maxima:

FFACTOR x 1000

D =

F

(D

-20 x FFACTOR)

50

++

1ns(CAP LOAD - 50) / 10

where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D

is the parameter value defined for 50 MHz

50

CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.

2

Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.

3

If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.

4

The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for
BG

output is relevant when the MPC850 is selected to work with internal bus arbiter.

5

The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and
not when the memory controller or the PCMCIA interface drives them).

6

The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
timing for BG

7

The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input

input is relevant when the MPC850 is selected to work with the external bus arbiter.

signal is asserted.

8

The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.

9

The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.

10

The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.

11

The AS signal is considered asynchronous to CLKOUT.

Unit

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

18 Freescale Semiconductor

Figure 2 is the control timing diagram.

Bus Signal Timing

CLKOUT

Outputs

Outputs

Inputs

Inputs

2.0 V

B

2.0 V

0.8 V

0.8 V

A

B

2.0 V

0.8 V

2.0 V

0.8 V

C

2.0 V

0.8 V

0.8 V

A

D

2.0 V

0.8 V

2.0 V

2.0 V

0.8 V

2.0 V

0.8 V

D

C

2.0 V

0.8 V

A Maximum output delay specification

B Minimum output hold time

C Minimum input setup time specification

D Minimum input hold time specification

Figure 2. Control Timing

Figure 3 provides the timing for the external clock.

CLKOUT

B1

B1

B4

Figure 3. External Clock Timing

B3

B2

B5

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 19

Bus Signal Timing

Figure 4 provides the timing for the synchronous output signals.

CLKOUT

B8

B7 B9

Output

Signals

B8a

B9B7a

Output

Signals

B8b

B7b

Output

Signals

Figure 4. Synchronous Output Signals Timing

Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13

B12B11

, BB

TS

B13a

B11a

TA, BI

B14

TEA

Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing

B12a

B15

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

20 Freescale Semiconductor

Figure 6 provides the timing for the synchronous input signals.

CLKOUT

B16

, BI

TA

B16a

B17a

TEA, KR,

RETRY

B16b

BB, BG, BR

Bus Signal Timing

B17

B17

Figure 6. Synchronous Input Signals Timing

Figure 7 provides normal case timing for input data.

CLKOUT

B16

TA

B18

D[0:31],

DP[0:3]

Figure 7. Input Data Timing in Normal Case

B17

B19

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 21

Bus Signal Timing

Figure 8 provides the timing for the input data controlled by the UPM in the memory controller.

CLKOUT

TA

B20

B21

D[0:31],

DP[0:3]

Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller

Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM

factors.

CLKOUT

TS

A[6:31]

CSx

OE

WE[0:3]

D[0:31],

DP[0:3]

B11 B12

B8

B22

B25

B28

B23

B26

B19

B18

Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

22 Freescale Semiconductor

CLKOUT

TS

A[6:31]

Bus Signal Timing

B11 B12

B8

B22a

B23

CSx

B25B24

B26

OE

B19B18

D[0:31],

DP[0:3]

Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)

CLKOUT

B11 B12

TS

B8

A[6:31]

B22b

B22c B23

CSx

B24a

B25 B26

OE

B19B18

D[0:31],

DP[0:3]

Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 23

Bus Signal Timing

CLKOUT

A[6:31]

B11 B12

TS

B8

B22a

B23

CSx

OE

B27

B27a

B22bB22c

B26

B19B18

D[0:31],

DP[0:3]

Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

24 Freescale Semiconductor

Bus Signal Timing

Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM

factors.

CLKOUT

TS

A[6:31]

CSx

WE[0:3]

OE

D[0:31],

DP[0:3]

B11

B8

B22 B23

B26

B12

B8 B9

B30

B28B25

B29b

B29a

Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 25

Bus Signal Timing

CLKOUT

TS

A[6:31]

CSx

WE[0:3]

OE

D[0:31],

DP[0:3]

B11

B8

B22

B26

B8

B12

B28bB28d

B25

B28a

B28c

B9

B30a

B23

B29c

B30c

B29g

B29aB29f

Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

26 Freescale Semiconductor

CLKOUT

TS

Bus Signal Timing

B12B11

B8

B30dB30b

A[6:31]

B28b

B28d

CSx

B25

B29eB29i

WE[0:3]

B26

OE

B29d

B29b

B28aB28c

D[0:31],

DP[0:3]

Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)

B23B22

B9B8

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 27

Bus Signal Timing

Figure 16 provides the timing for the external bus controlled by the UPM.

CLKOUT

B8

A[6:31]

B31a

B31d

B31

CSx

B34

B34a

B34b

B32aB32d

B32

B31b

B32b

B31c

B32c

BS_A

[0:3],

[0:3]

BS_B

GPL_A[0–5],

[0–5]

GPL_B

B36

B35

B35a

B35b

B33

B33a

Figure 16. External Bus Timing (UPM Controlled Signals)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

28 Freescale Semiconductor

Bus Signal Timing

Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3],

[0:3]

BS_B

[0–5],

GPL_A

GPL_B

[0–5]

Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3],

BS_B

[0:3]

[0–5],

GPL_A

[0–5]

GPL_B

Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 29

Bus Signal Timing

Figure 19 provides the timing for the synchronous external master access controlled by the GPCM.

CLKOUT

B41 B42

TS

B40

A[6:31],

TSIZ[0:1],

, BURST

R/W

B22

CSx

Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 20 provides the timing for the asynchronous external master memory access controlled by the

GPCM.

CLKOUT

B39

AS

B40

A[6:31],

TSIZ[0:1],

R/W

B22

CSx

Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 21 provides the timing for the asynchronous external master control signals negation.

AS

B43

CSx, WE[0:3],

OE

, GPLx,

BS

[0:3]

Figure 21. Asynchronous External Master—Control Signals Negation Timing

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

30 Freescale Semiconductor

Table 7 provides interrupt timing for the MPC850.

Table 7. Interrupt Timing

Bus Signal Timing

Num Characteristic

I39 IRQx

I40 IRQx

I41 IRQx

I42 IRQx

I43 IRQx

1

The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ
to the CLKOUT.

The timings I41, I42, and I43 are specified to allow the correct function of the IRQ

direct relation with the total system interrupt latency that the MPC850 is able to support

valid to CLKOUT rising edge (set up time) 6.00 — 6.00 — 6.00 — ns

hold time after CLKOUT. 2.00 — 2.00 — 2.00 — ns

pulse width low 3.00 — 3.00 — 3.00 — ns

pulse width high 3.00 — 3.00 — 3.00 — ns

edge-to-edge time 80.00 — 121.0 — 100.0 — ns

lines are synchronized internally and do not have to be asserted or negated with reference

1

50 MHz 66MHz 80 MHz

Min Max Min Max Min Max

lines detection circuitry, and has no

Figure 22 provides the interrupt detection timing for the external level-sensitive lines.

CLKOUT

I39

I40

Unit

IRQx

Figure 22. Interrupt Detection Timing for External Level Sensitive Lines

Figure 23 provides the interrupt detection timing for the external edge-sensitive lines.

CLKOUT

I39

I41 I42

IRQx

I43

I43

Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 31

Bus Signal Timing

Table 8 shows the PCMCIA timing for the MPC850.

Table 8. PCMCIA Timing

50MHz 66MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max

FFACTOR Unit

P44

A[6–31], REG
asserted.

P45 A[6–31], REG

valid to PCMCIA strobe

1

valid to ALE negation.

P46 CLKOUT to REG
P47 CLKOUT to REG
P48 CLKOUT to CE1
P49 CLKOUT to CE1

P50

P51

CLKOUT to PCOE
IOWR

assert time.

CLKOUT to PCOE
IOWR

negate time.

valid 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns

Invalid. 6.00 — 9.00 — 7.00 — 0.250 ns

, CE2 asserted. 5.00 13.00 8.00 16.00 6.00 14.00 0.250

, CE2 negated. 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns

, IORD, PCWE,

, IORD, PCWE,

13.00 — 21.00 — 17.00 — 0.750 ns

1

18.00 — 28.00 — 23.00 — 1.000 ns

— 11.00 — 11.00 — 11.00 — ns

2.00 11.00 2.00 11.00 2.00 11.00 — ns

P52 CLKOUT to ALE assert time 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
P53 CLKOUT to ALE negate time — 13.00 — 16.00 — 14.00 0.250 ns

, IOWR negated to D[0–31]

P54

P55 WAIT_B

P56

1

PCWE

1

invalid.

valid to CLKOUT rising edge.18.00 — 8.00 — 8.00 — — ns

CLKOUT rising edge to WAIT_B

1

invalid.

PSST = 1. Otherwise add PSST times cycle time.

3.00 — 6.00 — 4.00 — 0.250 ns

2.00 — 2.00 — 2.00 — — ns

PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAIT_B
current cycle. The WAIT_B

assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.

signal is detected in order to freeze (or relieve) the PCMCIA

See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

32 Freescale Semiconductor

Figure 24 provides the PCMCIA access cycle timing for the external bus read.

CLKOUT

TS

P44

A[6:31]

Bus Signal Timing

REG

CE1/CE2

PCOE, IORD

ALE

D[0:31]

P46 P45

P48 P49

P53P52 P52

P47

P51P50

Figure 24. PCMCIA Access Cycles Timing External Bus Read

B19B18

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 33

Bus Signal Timing

Figure 25 provides the PCMCIA access cycle timing for the external bus write.

CLKOUT

TS

P44

A[6:31]

P46 P45

REG

P48 P49

CE1/CE2

PCWE, IOWR

P53P52 P52

ALE

D[0:31]

Figure 25. PCMCIA Access Cycles Timing External Bus Write

Figure 26 provides the PCMCIA WAIT signals detection timing.

P47

P51P50

P54

B9B8

CLKOUT

P55

P56

WAIT_B

Figure 26. PCMCIA WAIT Signal Detection Timing

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

34 Freescale Semiconductor

Table 9 shows the PCMCIA port timing for the MPC850.

Table 9. PCMCIA Port Timing

50 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max

P57 CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 ns

P58 HRESET

P59 IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — ns

P60 CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — ns

1

OP2 and OP3 only.

negated to OPx drive

1

18.00 — 26.00 — 22.00 — ns

Figure 27 provides the PCMCIA output port timing for the MPC850.

CLKOUT

P57

Output

Signals

Bus Signal Timing

Unit

HRESET

P58

OP2, OP3

Figure 27. PCMCIA Output Port Timing

Figure 28 provides the PCMCIA output port timing for the MPC850.

CLKOUT

P59

P60

Input

Signals

Figure 28. PCMCIA Input Port Timing

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 35

Bus Signal Timing

Table 10 shows the debug port timing for the MPC850.

Table 10. Debug Port Timing

50 MHz 66 MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max

D61 DSCK cycle time 60.00 — 91.00 — 75.00 — ns
D62 DSCK clock pulse width 25.00 — 38.00 — 31.00 — ns
D63 DSCK rise and fall times 0.00 3.00 0.00 3.00 0.00 3.00 ns
D64 DSDI input data setup time 8.00 — 8.00 — 8.00 — ns
D65 DSDI data hold time 5.00 — 5.00 — 5.00 — ns
D66 DSCK low to DSDO data valid 0.00 15.00 0.00 15.00 0.00 15.00 ns
D67 DSCK low to DSDO invalid 0.00 2.00 0.00 2.00 0.00 2.00 ns

Figure 29 provides the input timing for the debug port clock.

DSCK

Unit

D61

D63

Figure 29. Debug Port Clock Input Timing

Figure 30 provides the timing for the debug port.

DSCK

DSDI

D66

DSDO

Figure 30. Debug Port Timings

D62

D62

D63

D64

D65

D67

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

36 Freescale Semiconductor

Table 11 shows the reset timing for the MPC850.

Table 11. Reset Timing

50 MHz 66MHz 80 MHz

Num Characteristic

MinMaxMinMaxMinMax

Bus Signal Timing

FFACTOR Unit

R69 CLKOUT to HRESET
R70 CLKOUT to SRESET
R71 RSTCONF
R72 —————— —

Configuration data to HRESET

R73

edge set up time

Configuration data to RSTCONF

R74

edge set up time

Configuration data hold time after

R75

RSTCONF

Configuration data hold time after

R76

HRESET

HRESET

R77

data out drive

RSTCONF

R78

impedance.

CLKOUT of last rising edge before chip

R79

tristates HRESET
impedance.

R80 DSDI, DSCK set up 60.00 — 90.00 — 75.00 — 3.000 ns

pulse width 340.00 — 515.00 — 425.00 — 17.000 ns

negation

negation

and RSTCONF asserted to

negated to data out high

high impedance — 20.00 — 20.00 — 20.00 — ns

high impedance — 20.00 — 20.00 — 20.00 — ns

rising

rising

to data out high

350.00 — 505.00 — 425.00 — 15.000 ns

350.00 — 350.00 — 350.00 — — ns

0.00 — 0.00 — 0.00 — — ns

0.00 — 0.00 — 0.00 — — ns

— 25.00 — 25.00 — 25.00 — ns

— 25.00 — 25.00 — 25.00 — ns

— 25.00 — 25.00 — 25.00 — ns

R81 DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — — ns

SRESET

R82

edge for DSDI and DSCK sample

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 37

negated to CLKOUT rising

160.00 — 242.00 — 200.00 — 8.000 ns

Bus Signal Timing

Figure 31 shows the reset timing for the data bus configuration.

HRESET

R71

R76

RSTCONF

R73

R74

D[0:31] (IN )

R75

Figure 31. Reset Timing—Configuration from Data Bus

Figure 32 provides the reset timing for the data bus weak drive during configuration.

CLKOUT

HRESET

RSTCONF

D[0:31] (O U T )

(Weak)

R69

R79

R77 R78

Figure 32. Reset Timing—Data Bus Weak Drive during Configuration

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

38 Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

Figure 33 provides the reset timing for the debug port configuration.

CLKOUT

R70

R82

SRESET

R80R80

R81

DSCK, DSDI

R81

Figure 33. Reset Timing—Debug Port Configuration

7 IEEE 1149.1 Electrical Specifications

Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37.

Table 12. JTAG Timing

50 MHz 66MHz 80 MHz

Num Characteristic

Min Max Min Max Min Max

J82 TCK cycle time 100.00 — 100.00 — 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — 40.00 — 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 0.00 10.00 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — 5.00 — 5.00 — ns
J86 TMS, TDI data hold time 25.00 — 25.00 — 25.00 — ns
J87 TCK low to TDO data valid — 27.00 — 27.00 — 27.00 ns
J88 TCK low to TDO data invalid 0.00 — 0.00 — 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 — 20.00 — 20.00 ns
J90 TRST
J91 TRST
J92 TCK falling edge to output valid — 50.00 — 50.00 — 50.00 ns

J93

J94 TCK falling edge to output high impedance — 50.00 — 50.00 — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — 50.00 — 50.00 — ns

assert time 100.00 — 100.00 — 100.00 — ns

setup time to TCK low 40.00 — 40.00 — 40.00 — ns

TCK falling edge to output valid out of high
impedance

— 50.00 — 50.00 — 50.00 ns

Unit

J96 TCK rising edge to boundary scan input invalid 50.00 — 50.00 — 50.00 — ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 39

IEEE 1149.1 Electrical Specifications

TCK

J82 J83

J82 J83

TCK

TMS, TDI

TDO

TCK

J84

J84

Figure 34. JTAG Test Clock Input Timing

J85

J86

J87

J88 J89

Figure 35. JTAG Test Access Port Timing Diagram

J91

J90

TRST

Figure 36. JTAG TRST

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

40 Freescale Semiconductor

Timing Diagram

CPM Electrical Characteristics

TCK

J92 J94

Output

Signals

J93

Output

Signals

J95 J96

Input

Signals

Figure 37. Boundary Scan (JTAG) Timing Diagram

8 CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC850.

8.1 PIO AC Electrical Specifications

Table 13 provides the parallel I/O timings for the MPC850 as shown in Figure 38.

Table 13. Parallel I/O Timing

All Frequencies

Num Characteristic

Min Max

29 Data-in setup time to clock high 15 — ns

30 Data-in hold time from clock high 7.5 — ns

31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns

Unit

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 41

CPM Electrical Characteristics

CLKOUT

29

30

DATA-IN

31

DATA-OUT

Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram

8.2 IDMA Controller AC Electrical Specifications

Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42.

Table 14. IDMA Controller Timing

Num Characteristic

40 DREQ

41 DREQ

42 SDACK

43 SDACK

44 SDACK

45 SDACK

46 TA

CLKOUT

(Output)

DREQ

(Input)

setup time to clock high 7.00 — ns

hold time from clock high 3.00 — ns

assertion delay from clock high — 12.00 ns

negation delay from clock low — 12.00 ns

negation delay from TA low — 20.00 ns

negation delay from clock high — 15.00 ns

assertion to falling edge of the clock setup time (applies to external TA)7.00 — ns

Figure 39. IDMA External Requests Timing Diagram

All Frequencies

Unit

Min Max

41

40

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

42 Freescale Semiconductor

CLKOUT

(Output)

TS

(Output)

R/W

(Output)

CPM Electrical Characteristics

42

DATA

TA

(Output)

SDACK

43

46

Figure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge

of the Clock

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 43

CPM Electrical Characteristics

CLKOUT

(Output)

TS

(Output)

R/W

(Output)

DATA

TA

(Output)

SDACK

42 44

Figure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge

of the Clock

CLKOUT

(Output)

TS

(Output)

R/W

(Output)

42 45

DATA

TA

(Output)

SDACK

Figure 42. SDACK

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

44 Freescale Semiconductor

Timing Diagram—Peripheral Read

CPM Electrical Characteristics

8.3 Baud Rate Generator AC Electrical Specifications

Table 15 provides the baud rate generator timings as shown in Figure 43.

Table 15. Baud Rate Generator Timing

All Frequencies

Num Characteristic

Min Max

50 BRGO rise and fall time — 10.00 ns

51 BRGO duty cycle 40.00 60.00 %

52 BRGO cycle 40.00 — ns

Unit

50

BRGOn

51

52

50

51

Figure 43. Baud Rate Generator Timing Diagram

8.4 Timer AC Electrical Specifications

Table 16 provides the baud rate generator timings as shown in Figure 44.

Num Characteristic

61 TIN/TGATE

62 TIN/TGATE

63 TIN/TGATE

64 TIN/TGATE

Table 16. Timer Timing

All Frequencies

Min Max

rise and fall time 10.00 — ns

low time 1.00 — clk

high time 2.00 — clk
cycle time 3.00 — clk

Unit

65 CLKO high to TOUT

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 45

valid 3.00 25.00 ns

CPM Electrical Characteristics

CLKOUT

TIN/TGATE

(Input)

626361

61

65

TOUT

(Output)

64

Figure 44. CPM General-Purpose Timers Timing Diagram

8.5 Serial Interface AC Electrical Specifications

Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49.

Table 17. SI Timing

All Frequencies

Num Characteristic

Min Max

70 L1RCLK, L1TCLK frequency (DSC = 0)

71 L1RCLK, L1TCLK width low (DSC = 0)

71a L1RCLK, L1TCLK width high (DSC = 0)

72 L1TXD, L1ST

73 L1RSYNC, L1TSYNC valid to L1xCLK edge Edge

(SYNC setup time)

n

, L1RQ, L1xCLKO rise/fall time — 15.00 ns

1, 2

— SYNCCLK/2.5MHz

2

3

P + 10 — ns

P + 10 — ns

20.00 — ns

Unit

74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid

(SYNC hold time)

75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns

76 L1RXD valid to L1xCLK edge (L1RXD setup time) 17.00 — ns

77 L1xCLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns

78 L1xCLK edge to L1ST

78A L1SYNC valid to L1ST

79 L1xCLK edge to L1ST

80 L1xCLK edge to L1TXD valid 10.00 55.00 ns

80A L1TSYNC valid to L1TXD valid

81 L1xCLK edge to L1TXD high impedance 0.00 42.00 ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

46 Freescale Semiconductor

4

n

valid

n

valid 10.00 45.00 ns

n

invalid 10.00 45.00 ns

4

35.00 — ns

10.00 45.00 ns

10.00 55.00 ns

Table 17. SI Timing (continued)

Num Characteristic

CPM Electrical Characteristics

All Frequencies

Unit

Min Max

1

2

3

4

whichever is later.

L1RCLK

(FE=0, CE=0)

(Input)

L1RCLK

(FE=1, CE=1)

(Input)

82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or

MHz

SYNCCLK/2

83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns

83A L1RCLK, L1TCLK width high (DSC = 1)

3

P + 10 — ns

84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns

85 L1RQ

valid before falling edge of L1TSYNC

86 L1GR setup time

2

4

1.00 — L1TCLK

42.00 — ns

87 L1GR hold time 42.00 — ns

88 L1xCLK edge to L1SYNC valid (FSD = 00) CNT =

—0.00ns

0000, BYT = 0, DSC = 0)

The ratio SyncCLK/L1RCLK must be greater than 2.5/1.

These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,

71 70

71a

72

RFSD=1

75

L1RSYNC

(Input)

73

7774

L1RxD

(Input)

BIT0

76

79

L1ST

78

n

(Output)

Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 47

CPM Electrical Characteristics

L1RCLK

(FE=1, CE=1)

(Input)

82

L1RCLK

(FE=0, CE=0)

(Input)

L1RSYNC

(Input)

72

RFSD=1

75

73

74 77

83a

L1RXD

(Input)

L1ST(4-1)

(Output)

L1CLKO

(Output)

BIT0

76

78

79

84

Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

48 Freescale Semiconductor

L1TCLK

(FE=0, CE=0)

(Input)

L1TCLK

(FE=1, CE=1)

(Input)

L1TSYNC

(Input)

73

71

CPM Electrical Characteristics

70

72

TFSD=0

75

74

8180a

L1TxD

(Output)

L1ST

(Output)

BIT0

80

78

79

n

Figure 47. SI Transmit Timing Diagram

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 49

CPM Electrical Characteristics

L1RCLK

(FE=0, CE=0)

(Input)

L1RCLK

(FE=1, CE=1)

(Input)

L1RSYNC

(Input)

73

75

74

72

82

TFSD=0

83a

81

L1TXD

(Output)

L1ST(4-1)

(Output)

L1CLKO

(Output)

BIT0

80

78a

79

78

84

Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1)

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

50 Freescale Semiconductor

81

CPM Electrical Characteristics

12345678910 11 12 13 14 15 16 17 18 19 20

(Input)

L1RCLK

73

71

L1RSYNC

78

87

72

71

74

76

B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15

85

86

77

80

(Input)

L1TXD

(Output)

(Input)

L1RXD

L1ST(4-1)

(Output)

L1RQ

(Output)

L1GR

(Input)

Figure 49. IDL Timing

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 51

CPM Electrical Characteristics

8.6 SCC in NMSI Mode Electrical Specifications

Table 18 provides the NMSI external clock timing.

Num Characteristic

100 RCLKx and TCLKx frequency

table)

101 RCLKx and TCLKx width low 1/SYNCCLK +5 — ns

102 RCLKx and TCLKx rise/fall time — 15.00 ns

103 TXDx active delay (from TCLKx falling edge) 0.00 50.00 ns

Table 18. NMSI External Clock Timing

1

(x = 2, 3 for all specs in this

All Frequencies

1/SYNCCLK — ns

Unit

Min Max

104 RTSx

105 CTSx

active/inactive delay (from TCLKx falling edge) 0.00 50.00 ns

setup time to TCLKx rising edge 5.00 — ns

106 RXDx setup time to RCLKx rising edge 5.00 — ns

107 RXDx hold time from RCLKx rising edge

108 CDx

1

The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.

2

Also applies to CD and CTS hold time when they are used as an external sync signal.

setup time to RCLKx rising edge 5.00 — ns

Table 19 provides the NMSI internal clock timing.

Num Characteristic

100 RCLKx and TCLKx frequency

102 RCLKx and TCLKx rise/fall time — — ns

103 TXDx active delay (from TCLKx falling edge) 0.00 30.00 ns

104 RTSx

105 CTSx

active/inactive delay (from TCLKx falling edge) 0.00 30.00 ns

setup time to TCLKx rising edge 40.00 — ns

Table 19. NMSI Internal Clock Timing

1

(x = 2, 3 for all specs in this table)

2

5.00 — ns

All Frequencies

Unit

Min Max

0.00 SYNCCLK/3 MHz

106 RXDx setup time to RCLKx rising edge 40.00 — ns

107 RXDx hold time from RCLKx rising edge

108 CDx

1

The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.

2

Also applies to CD and CTS hold time when they are used as an external sync signals.

setup time to RCLKx rising edge 40.00 — ns

2

0.00 — ns

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

52 Freescale Semiconductor

Figure 50 through Figure 52 show the NMSI timings.

RCLKx

CPM Electrical Characteristics

RXDx

(Input)

CDx

(Input)

CDx

(SYNC Input)

TCLKx

106

102

102 101

100

107

Figure 50. SCC NMSI Receive Timing Diagram

102

102 101

100

108

107

TXDx

(Output)

103

105

RTSx

(Output)

104

CTSx

(Input)

CTSx

(SYNC Input)

104

107

Figure 51. SCC NMSI Transmit Timing Diagram

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 53

CPM Electrical Characteristics

TCLKx

102

TXDx

(Output)

RTSx

(Output)

CTSx

(Echo Input)

102 101

100

103

104

105

Figure 52. HDLC Bus Timing Diagram

8.7 Ethernet Electrical Specifications

Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55.

Table 20. Ethernet Timing

104107

All Frequencies

Num Characteristic

Min Max

120 CLSN width high 40.00 — ns

121 RCLKx rise/fall time (x = 2, 3 for all specs in this table) — 15.00 ns

122 RCLKx width low 40.00 — ns

123 RCLKx clock period

124 RXDx setup time 20.00 — ns

125 RXDx hold time 5.00 — ns

126 RENA active delay (from RCLKx rising edge of the last data bit) 10.00 — ns

127 RENA width low 100.00 — ns

128 TCLKx rise/fall time — 15.00 ns

129 TCLKx width low 40.00 — ns

130 TCLKx clock period

131 TXDx active delay (from TCLKx rising edge) 10.00 50.00 ns

132 TXDx inactive delay (from TCLKx rising edge) 10.00 50.00 ns

133 TENA active delay (from TCLKx rising edge) 10.00 50.00 ns

1

1

80.00 120.00 ns

99.00 101.00 ns

Unit

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

54 Freescale Semiconductor

CPM Electrical Characteristics

Table 20. Ethernet Timing (continued)

All Frequencies

Num Characteristic

Min Max

134 TENA inactive delay (from TCLKx rising edge) 10.00 50.00 ns

138 CLKOUT low to SDACK

139 CLKOUT low to SDACK

1

The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1.

2

SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory.

asserted

negated

2

2

— 20.00 ns

— 20.00 ns

CLSN(CTSx)

(Input)

120

Figure 53. Ethernet Collision Timing Diagram

RCLKx

Unit

RXDx

(Input)

RENA(CDx)

(Input)

121

121

122

124 123

125

126

Figure 54. Ethernet Receive Timing Diagram

Last Bit

127

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 55

CPM Electrical Characteristics

TCLKx

TxDx

(Output)

TENA(RTSx)

(Input)

RENA(CDx)

(Input)

(NOTE 2)

128

131 130

133 134

NOTES:

Transmit clock invert (TCI) bit in GSMR is set.

1.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the

2.
CSL bit is set in the buffer descr iptor at the end of the frame transmi s s ion.

128

129

132

Figure 55. Ethernet Transmit Timing Diagram

8.8 SMC Transparent AC Electrical Specifications

Figure 21 provides the SMC transparent timings as shown in Figure 56.

Table 21. Serial Management Controller Timing

All Frequencies

Num Characteristic

Min Max

150 SMCLKx clock period

151 SMCLKx width low 50.00 — ns

151a SMCLKx width high 50.00 — ns

152 SMCLKx rise/fall time — 15.00 ns

153 SMTXDx active delay (from SMCLKx falling edge) 10.00 50.00 ns

154 SMRXDx/SMSYNx

155 SMRXDx/SMSYNx

1

The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.

1

setup time 20.00 — ns

hold time 5.00 — ns

100.00 — ns

Unit

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

56 Freescale Semiconductor

SMCLKx

CPM Electrical Characteristics

152

SMTXDx

(Output)

SMSYNx

SMRXDx

(Input)

NOTE:

This de l a y is equal to an i n t e ge r nu m ber of cha r a c ter-len gth cloc k s .1.

152 151

NOTE

154 153

155

154

155

151a

150

Figure 56. SMC Transparent Timing Diagram

8.9 SPI Master AC Electrical Specifications

Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58.

Table 22. SPI Master Timing

All Frequencies

Num Characteristic

Min Max

160 MASTER cycle time 4 1024 t

161 MASTER clock (SCK) high or low time 2 512 t

162 MASTER data setup time (inputs) 50.00 — ns

163 Master data hold time (inputs) 0.00 — ns

164 Master data valid (after SCK edge) — 20.00 ns

165 Master data hold time (outputs) 0.00 — ns

166 Rise time output — 15.00 ns

167 Fall time output — 15.00 ns

Unit

cyc

cyc

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 57

CPM Electrical Characteristics

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

163

161 160

162

166

166167161

167

SPIMISO

(Input)

SPIMOSI

(Output)

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

SPIMISO

(Input)

msb Data lsb msb

165 164

167 166

msb lsb msb

Data

Figure 57. SPI Master (CP = 0) Timing Diagram

166167161

161 160

162

163

166

msb Data lsb msb

167

165 164

167 166

SPIMOSI

(Output)

msb lsb msb

Data

Figure 58. SPI Master (CP = 1) Timing Diagram

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

58 Freescale Semiconductor

8.10 SPI Slave AC Electrical Specifications

Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60.

Table 23. SPI Slave Timing

All Frequencies

Num Characteristic

Min Max

CPM Electrical Characteristics

Unit

170 Slave cycle time 2 — t

171 Slave enable lead time 15.00 — ns

172 Slave enable lag time 15.00 — ns

173 Slave clock (SPICLK) high or low time 1 — t

174 Slave sequential transfer delay (does not require deselect) 1 — t

175 Slave data setup time (inputs) 20.00 — ns

176 Slave data hold time (inputs) 20.00 — ns

177 Slave access time — 50.00 ns

178 Slave SPI MISO disable time — 50.00 ns

179 Slave data valid (after SPICLK edge) — 50.00 ns

180 Slave data hold time (outputs) 0.00 — ns

181 Rise time (input) — 15.00 ns

182 Fall time (input) — 15.00 ns

cyc

cyc

cyc

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 59

CPM Electrical Characteristics

SPISEL

(Input)

SPICLK

(CI=0)
(Input)

SPICLK

(CI=1)
(Input)

181182173

173 170

177 182

181

180

171172

174

178

SPIMISO

(Output)

SPIMOSI

(Input)

Datamsb lsb msbUndef

175 179

176 182

msb lsb msb

Data

181

Figure 59. SPI Slave (CP = 0) Timing Diagram

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

60 Freescale Semiconductor

SPISEL

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

171 170

173

173

177 182

181

180

CPM Electrical Characteristics

172

174

181182

178

SPIMISO

(Output)

175 179

SPIMOSI

(Input)

msb

176 182

msb lsb

Data

181

Data

Figure 60. SPI Slave (CP = 1) Timing Diagram

8.11 I2C AC Electrical Specifications

Table 24 provides the I2C (SCL < 100 KHz) timings.

Table 24 . I2C Timing (SCL < 100 KHZ)

Num Characteristic

200 SCL clock frequency (slave) 0.00 100.00 KHz

200 SCL clock frequency (master)

202 Bus free time between transmissions 4.70 — µs

203 Low period of SCL 4.70 — µs

1

lsbUndef

All Frequencies

Min Max

1.50 100.00 KHz

msb

msb

Unit

204 High period of SCL 4.00 — µs

205 Start condition setup time 4.70 — µs

206 Start condition hold time 4.00 — µs

207 Data hold time 0.00 — µs

208 Data setup time 250.00 — ns

209 SDL/SCL rise time — 1.00 µs

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 61

CPM Electrical Characteristics

Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED)

Num Characteristic

210 SDL/SCL fall time — 300.00 ns

211 Stop condition setup time 4.70 — µs

1

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.

Table 25 provides the I2C (SCL > 100 KHz) timings.

Table 25 . I2C Timing (SCL > 100 KHZ)

Num Characteristic Expression

200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz

200 SCL clock frequency (master)

202 Bus free time between transmissions 1/(2.2 * fSCL) — s

1

fSCL BRGCLK/16512 BRGCLK/48 Hz

All Frequencies

Unit

Min Max

All Frequencies

Unit

Min Max

203 Low period of SCL 1/(2.2 * fSCL) — s

204 High period of SCL 1/(2.2 * fSCL) — s

205 Start condition setup time 1/(2.2 * fSCL) — s

206 Start condition hold time 1/(2.2 * fSCL) — s

207 Data hold time 0 — s

208 Data setup time 1/(40 * fSCL) — s

209 SDL/SCL rise time — 1/(10 * fSCL) s

210 SDL/SCL fall time — 1/(33 * fSCL) s

211 Stop condition setup time 1/2(2.2 * fSCL) — s

1

SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.

Figure 61 shows the I

SDA

202

205

2

C bus timing.

203

207

204

208

SCL

206 209 211210

Figure 61. I2C Bus Timing Diagram

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

62 Freescale Semiconductor

Mechanical Data and Ordering Information

9 Mechanical Data and Ordering Information

Table 26 provides information on the MPC850 derivative devices.

Table 26. MPC850 Family Derivatives

32-Channel HDLC

Device Ethernet Support Number of SCCs

MPC850 N/A One N/A N/A

MPC850DE Yes Two N/A N/A

MPC850SR Yes Two N/A Yes

MPC850DSL Yes Two No No

1

Serial Communication Controller (SCC)

2

50 MHz version supports 64 time slots on a time division multiplexed line using one SCC

1

Support

64-Channel HDLC

Table 27 identifies the packages and operating frequencies available for the MPC850.

Table 27. MPC850 Package/Frequency/Availability

Package Type Frequency (MHz) Temperature (Tj) Order Number

256-Lead Plastic Ball Grid Array
(ZT suffix)

50 0°C to 95°C XPC850ZT50BU

XPC850DEZT50BU

XPC850SRZT50BU
XPC850DSLZT50BU

66 0°C to 95°C XPC850ZT66BU

XPC850DEZT66BU
XPC850SRZT66BU

Support

2

80 0°C to 95°C XPC850ZT80BU

XPC850DEZT80BU
XPC850SRZT80BU

256-Lead Plastic Ball Grid Array

(CZT suffix)

50 -40°C to 95°C XPC850CZT50BU

XPC850DECZT50BU
XPC850SRCZT50BU
XPC850DSLCZT50BU

66 XPC850CZT66BU

XPC850DECZT66BU
XPC850SRCZT66BU

80 XPC850CZT80B

XPC850DECZT80B

XPC850SRCZT80B

9.1 Pin Assignments and Mechanical Dimensions of the PBGA

The original pin numbering of the MPC850 conformed to a Motorola proprietary pin numbering scheme
that has since been replaced by the JEDEC pin numbering standard for this package type. To support

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 63

Mechanical Data and Ordering Information

customers that are currently using the non-JEDEC pin num bering scheme, two sets of pinouts , JEDEC and
non-JEDEC, are presented in this document.

Figure 62 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface.

PC14 PB28 PB27

PC15 PA14 PA13 PA12

PA15 PB30 PB29 PC13 TRST

A8 A7 PB31 TDO

A11 A9 A12

A15 A14 A13

A27 A19 A16

VDDL A20 A21

A29 A23 A25

A28 A30 A22

A31 TSIZ0 A26

WE1 TSIZ1

WE0 WE2 GPLA3

GPLA1 GPLA2 CS6

CS4 CS7 CS2

N/C CS3 CS1 BDIP

16 15

PC12

TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8

TDI PC11 PB22 PC9

TMS

PB26

PB25 PA9 PC8

A6

A10

A17

N/C

A24

A18

WE3

GPLA0

N/C

CS5

CS0

GPLA4

WR

GPLB4

14 13 12 11 10 9

TEA BG IPB5 IPB1 IPB6

GPLA5

BI

BR

BB IRQ6 IPB3 IPB0 VDDL

TA

PB19 PA4 PB16 PD15

N/C

PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5

N/CN/C

GND

TS IRQ2 IPB7 IPB2 MODCK1

BURST IPB4 ALEB IRQ4

PB17 PC6 PD11 PD3 IRQ7 IRQ1 IRQ0

VDDH

TEXP

N/C

RSTCONFWAITB

MODCK2HRESET

EXTCLKEXTAL

876

SRESET

54321

D12 D13

D23

D17

D15 D14

D22 D18

D25 D20

D28 D24

D26

DP1

PORESET

KAPWR

XTAL

PD12

D27

D10

D31

DP2

DP0

VSSSYN1VSSSYN

PD7 PD6

N/C

D8 D0

D4

D1

D11

D9

D2 D3

D16

D5

D19

VDDL

D21 D6

D29 D7

D30 CLKOUT

DP3 N/C

XFC VDDSYN

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

Figure 62. Pin Assignments for the PBGA (Top View)—non-JEDEC Standard

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

64 Freescale Semiconductor

Mechanical Data and Ordering Information

Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface.

PC14 PB28 PB27

PC15 PA14 PA13 PA12

PA15 PB30 PB29 PC13 TRST

A8 A7 PB31 TDO

A11 A9 A12

A15 A14 A13

A27 A19 A16

VDDL A20 A21

A29 A23 A25

A28 A30 A22

A31 TSIZ0 A26

WE1 TSIZ1

WE0 WE2 GPLA3

GPLA1 GPLA2 CS6

CS4 CS7 CS2

N/C CS3 CS1 BDIP

17 16

PC12

TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8

TDI PC11 PB22 PC9

TMS

PB26

PB25 PA9 PC8

A6

A10

A17

N/C

A24

A18

WE3

GPLA0

N/C

CS5

CS0

GPLA4

WR

GPLB4

15 14 13 12 11 10

TEA BG IPB5 IPB1 IPB6

GPLA5

BI

BR

BB IRQ6 IPB3 IPB0 VDDL

TA

PB19 PA4 PB16 PD15

N/C

PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5

N/CN/C

GND

TS IRQ2 IPB7 IPB2 MODCK1

BURST IPB4 ALEB IRQ4

PB17 PC6 PD11 PD3 IRQ7 IRQ1 IRQ0

VDDH

TEXP

N/C

RSTCONFWAITB

HRESETSRESETPORESET

MODCK2

EXTCLKEXTAL

987

65432

D12 D13

D23

D17

D15 D14

D22

D25 D20

D28 D24

D26

DP1 DP2

KAPWR

XTAL

PD12

PD7 PD6

D27

D10

D16

D18

D19

D21 D6

D29

D31

D30 CLKOUT

DP3

DP0

XFC VDDSYN

VSSSYN1VSSSYN

D8 D0

D4

D11

D9

D2 D3

VDDL

N/C

D1

D5

D7

N/C

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

Figure 63. Pin Assignments for the PBGA (Top View)—JEDEC Standard

For more information on the printed circuit board layout of the PBGA package, including thermal via
design and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note
available from your local Motorola sales office.

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 65

Mechanical Data and Ordering Information

Figure 64 shows the non-JEDEC package dimensions of the PBGA.

A1

A

C

256X

SEATING

PLANE

SIDE VIEW

0.20 C

0.35 C

A2
A3

4X

(E1)

0.20

15X e

4X e/2

A

D

D2

E2

E

TOP VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 19 94.

2. DIMENSIONS IN MILLIMETERS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLD ER BALL DI AMETER, PARALLE L TO PRIMA RY
DATUM C.

4. PRIMARY DATUM C AND THE SEATING PLANE ARE

MILLIMETERS

DIM MIN MAX

A 1.91 2.35
A1 0.50 0.70
A2 1.12 1.22
A3 0.29 0.43

b 0.60 0.90

D 23.00 BSC
D1 19.05 REF
D2

19.00 20.00

E 23.00 BSC
E1 19.05 R EF
E2 19.0 0 20.0 0

e 1.27 BSC

B

(D1)

15X e

T
R
P
N
M

L

K

J

H

G

F

E

D

C

B

A

654321

7 8 9 10 11 12 13 14 15

256X

BOTTOM VIEW

b

M

0.30 C

M

0.15 C

16

AB

Figure 64. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

66 Freescale Semiconductor

Figure 65 shows the JEDEC package dimensions of the PBGA.

Mechanical Data and Ordering Information

A1

A

C

256X

SEATING

PLANE

SIDE VIEW

0.20 C

0.35 C

A2
A3

4X

(E1)

0.20

15X e

4X e/2

A

D

D2

E2

E

TOP VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 19 94.

2. DIMENSIONS IN MILLIMETERS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLD ER BALL DI AMETER, PARALLE L TO PRIMA RY
DATUM C.

4. PRIMARY DATUM C AND THE SEATING PLANE ARE

MILLIMETERS

DIM MIN MAX

A 1.91 2.35
A1 0.50 0.70
A2 1.12 1.22
A3 0.29 0.43

b 0.60 0.90

D 23.00 BSC
D1 19.05 REF
D2

19.00 20.00

E 23.00 BSC
E1 19.05 R EF
E2 19.0 0 20.0 0

e 1.27 BSC

B

(D1)

15X e

U
T
R
P
N
M
L
K

J
H
G
F
E
D
C
B

765432

8 9 10 11 12 13 14 15 16

256X

BOTTOM VIEW

b

M

0.30 C

M

0.15 C

17

AB

CASE 1130-01

ISSUE B

Figure 65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 67

Document Revision History

10 Document Revision History

Table 28 lists significant changes between revisions of this document.

Table 28. Document Revision History

Revision Date Change

2 7/2005 Added footnote 3 to Table 5 (previously Table 4.5) and deleted IOL limit.

1 10/2002 Added MPC850DSL. Corrected Figure 25 on page 34.

0.2 04/2002 Updated power numbers and added Rev. C

0.1 11/2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins.
Replaced SI and IDL timing diagrams with better images. Updated to new
template, added this revision table.

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

68 Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Document Revision History

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 69

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

70 Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Document Revision History

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 71

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Document Number: MPC850EC
Rev. 2
07/2005