This document contains detailed information on power
considerations, AC/DC electrical characteristics, and AC
timing specifications for revision A,B, and C of the MPC850
Family.
1Overview
The MPC850 is a versatile, one-chip integrated
microprocessor and peripheral combination that can be used
in a variety of controller applications, excelling particularly
in communications and networking products. The MPC850,
which includes support for Ethernet, is specifically designed
for cost-sensitive, remote-access, and telecommunications
applications. It is provides functions similar to the MPC860,
with system enhancements such as universal serial bus
(USB) support and a larger (8-Kbyte) dual-port RAM.
In addition to a high-performance embedded MPC8xx core,
the MPC850 integrates system functions, s uch as a versatile
memory controller and a communications pr ocessor module
(CPM) that incorporates a specialized, independent RISC
communications processor (referred to as the CP). This
separate processor off-loads peripheral tasks from the
embedded MPC8xx core.
The CPM of the MPC850 supports up to seven serial channels, as follows:
•One or two serial communications controllers (SCCs). The SCCs support Ethernet, A T M
(MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent
mode of operation.
•One USB channel
•Two serial management controllers (SMCs)
2
•One I
C port
•One serial peripheral interface (SPI).
Table 1 shows the functionality supported by the members of the MPC850 family.
Table 1. MPC850 Functionality Matrix
Number of
Part
MPC850 1Yes-Yes-1
MPC850DE2Yes-Yes-1
MPC850SR2YesYesYesYes1
MPC850DSL2YesYesYesNo1
SCCs
Supported
Ethernet
Support
ATM SupportUSB Support
Multi-channel
HDLC
Support
Additional documentation may be provided for parts listed in Table 1.
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and eight protection groups
•Advanced on-chip emulation debug mode
•Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian
memory systems
— Twenty-six external address lines
•Completely static design (0–80 MHz operation)
•System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— S oftware watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
•Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
•General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
•Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
•Si n gle so ck et PCMCIA- ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PC MC IA socke t
— Supports eight memory or I/O windows
after the current frame is finished or immediately if no frame is being sent and CLOSERXBD
closes the receive buffer descriptor)
Features
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four
USB endpoints
— Three parallel I/O registers with open-drain capability
•Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
•Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
®
— AppleTalk
— Univer sal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
•QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel
•One universal serial bus controller (USB)
— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
•Two serial management controllers (SMCs)
— UART
— Transparent
— Gener al circuit i nte rface ( GCI ) controller
— Can be connected to the time-division-multiplexed (TDM) channel
•One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
•One I2C® (interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment
•Time slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internall y connected to four serial channels (two SCCs and two SMCs)
•Low-power support
— Full high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze: core functional units disabled except time base, decrementer, PLL, memory controller ,
real-time clock, and CPM in low-power standby
— Sleep: all units disabled except real-time clock and periodic interrupt timer . PLL is active for
fast wake-up
— Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt
timer
— Low-power stop: to provide lower power dissipation
— Separate power supply input to operate internal logic at 2.2 V when operating at or below
25 MHz
— Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V
internal) operation
•Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints
— Eac h watchpoint can generate a breakpoint internally
•3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins.
3Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850.
Table 2 provides the maximum ratings.
Table 2. Maximum Ratings
(GND = 0V)
RatingSymbolValueUnit
Supply voltageVDDH-0.3 to 4.0V
VDDL-0.3 to 4.0V
KAPWR-0.3 to 4.0V
VDDSYN-0.3 to 4.0V
Input voltage
Junction temperature
Storage temperature rangeT
1
Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction
applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not
be applied to its inputs).
2
The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient
temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power
dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of
the device.
1
2
V
in
T
j
stg
GND-0.3 to VDDH + 2.5 VV
0 to 95 (standard)
-40 to 95 (extended)
-55 to +150°C
°C
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V
). Table 3 provides
CC
the package thermal characteristics for the MPC850.
3 The MPC850 IBIS model must be used to accurately model the behavior of the Clkout output driver for the full and
half drive setting. Due to the nature of the Clkout output buffer, IOH and IOL for Clkout should be extracted from the
IBIS model at any output voltage level.
= Package thermal resista nce , junction to ambient, °C/W
JA
PD = P
P
INT
P
I/O
For most applications P
relationship between P
PD = K ÷ (T
+ P
INT
= IDD x V
I/O
, watts—chip internal power
DD
= Power dissipation on input and output pins—user determined
+ 273°C)(2)
J
< 0.3 •P
I/O
and TJ is:
D
and can be neglected. If P
INT
I/O
is neglected, an approximate
Solving equations (1) and (2) for K gives:
K = PD • (T
+ 273°C) + θ
A
JA
• P
2
(3)
D
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations (1) and (2) iteratively for any value of TA.
5.1Layout Practices
Each VCC pin on the MPC850 should be provided with a low-i mpedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particula rly applies to the a ddres s and data busses. Maxim um PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in syst ems with higher capacit ive loads because th ese lo ads cr eate hi gher tran sient
currents in the V
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
CC
Special care should be taken to minimize the noise levels on the PLL supply pins.
6Bus Signal Timing
Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing
information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10
pF . Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on
the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to
be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the
part. The following equations should be used in these calculations.
For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:
FFACTOR x 1000
D =
F
(D
- 20 x FFACTOR)
50
+
For maxima:
FFACTOR x 1000
D =
F
(D
-20 x FFACTOR)
50
++
1ns(CAP LOAD - 50) / 10
where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D
is the parameter value defined for 50 MHz
50
CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.
2
Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.
3
If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
4
The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for
BG
output is relevant when the MPC850 is selected to work with internal bus arbiter.
5
The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and
not when the memory controller or the PCMCIA interface drives them).
6
The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
timing for BG
7
The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input
input is relevant when the MPC850 is selected to work with the external bus arbiter.
signal is asserted.
8
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
9
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
10
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.
11
The AS signal is considered asynchronous to CLKOUT.
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ
direct relation with the total system interrupt latency that the MPC850 is able to support
valid to CLKOUT rising edge (set up time)6.00—6.00—6.00—ns
hold time after CLKOUT.2.00—2.00—2.00—ns
pulse width low3.00—3.00—3.00—ns
pulse width high3.00—3.00—3.00—ns
edge-to-edge time80.00—121.0—100.0—ns
lines are synchronized internally and do not have to be asserted or negated with reference
1
50 MHz66MHz80 MHz
MinMaxMinMaxMinMax
lines detection circuitry, and has no
Figure 22 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
Unit
IRQx
Figure 22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 23 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I39
I41I42
IRQx
I43
I43
Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines
Table 10 shows the debug port timing for the MPC850.
Table 10. Debug Port Timing
50 MHz66 MHz80 MHz
NumCharacteristic
MinMaxMinMaxMinMax
D61DSCK cycle time60.00—91.00—75.00—ns
D62DSCK clock pulse width25.00—38.00—31.00—ns
D63DSCK rise and fall times0.003.000.003.000.003.00ns
D64DSDI input data setup time8.00—8.00—8.00—ns
D65DSDI data hold time5.00—5.00—5.00—ns
D66DSCK low to DSDO data valid0.0015.000.0015.000.0015.00ns
D67DSCK low to DSDO invalid0.002.000.002.000.002.00ns
Figure 29 provides the input timing for the debug port clock.
Figure 33 provides the reset timing for the debug port configuration.
CLKOUT
R70
R82
SRESET
R80R80
R81
DSCK, DSDI
R81
Figure 33. Reset Timing—Debug Port Configuration
7IEEE 1149.1 Electrical Specifications
Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37.
Table 12. JTAG Timing
50 MHz66MHz80 MHz
NumCharacteristic
MinMaxMinMaxMinMax
J82TCK cycle time100.00—100.00—100.00—ns
J83TCK clock pulse width measured at 1.5 V40.00—40.00—40.00—ns
J84TCK rise and fall times0.0010.000.0010.000.0010.00ns
J85TMS, TDI data setup time5.00—5.00—5.00—ns
J86TMS, TDI data hold time25.00—25.00—25.00—ns
J87TCK low to TDO data valid —27.00—27.00—27.00ns
J88TCK low to TDO data invalid 0.00—0.00—0.00—ns
J89TCK low to TDO high impedance —20.00—20.00—20.00ns
J90TRST
J91TRST
J92TCK falling edge to output valid—50.00—50.00—50.00ns
J93
J94TCK falling edge to output high impedance—50.00—50.00—50.00ns
J95Boundary scan input valid to TCK rising edge50.00—50.00—50.00—ns
assert time100.00—100.00—100.00—ns
setup time to TCK low40.00—40.00—40.00—ns
TCK falling edge to output valid out of high
impedance
—50.00—50.00—50.00ns
Unit
J96TCK rising edge to boundary scan input invalid 50.00—50.00—50.00—ns
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,
7170
71a
72
RFSD=1
75
L1RSYNC
(Input)
73
7774
L1RxD
(Input)
BIT0
76
79
L1ST
78
n
(Output)
Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
Table 26 provides information on the MPC850 derivative devices.
Table 26. MPC850 Family Derivatives
32-Channel HDLC
DeviceEthernet SupportNumber of SCCs
MPC850N/AOneN/AN/A
MPC850DEYesTwoN/AN/A
MPC850SR YesTwoN/AYes
MPC850DSLYesTwoNoNo
1
Serial Communication Controller (SCC)
2
50 MHz version supports 64 time slots on a time division multiplexed line using one SCC
1
Support
64-Channel HDLC
Table 27 identifies the packages and operating frequencies available for the MPC850.
Table 27. MPC850 Package/Frequency/Availability
Package TypeFrequency (MHz)Temperature (Tj)Order Number
256-Lead Plastic Ball Grid Array
(ZT suffix)
500°C to 95°CXPC850ZT50BU
XPC850DEZT50BU
XPC850SRZT50BU
XPC850DSLZT50BU
660°C to 95°CXPC850ZT66BU
XPC850DEZT66BU
XPC850SRZT66BU
Support
2
800°C to 95°CXPC850ZT80BU
XPC850DEZT80BU
XPC850SRZT80BU
256-Lead Plastic Ball Grid Array
(CZT suffix)
50-40°C to 95°CXPC850CZT50BU
XPC850DECZT50BU
XPC850SRCZT50BU
XPC850DSLCZT50BU
66XPC850CZT66BU
XPC850DECZT66BU
XPC850SRCZT66BU
80XPC850CZT80B
XPC850DECZT80B
XPC850SRCZT80B
9.1Pin Assignments and Mechanical Dimensions of the PBGA
The original pin numbering of the MPC850 conformed to a Motorola proprietary pin numbering scheme
that has since been replaced by the JEDEC pin numbering standard for this package type. To support
Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface.
PC14 PB28 PB27
PC15 PA14 PA13 PA12
PA15 PB30 PB29 PC13TRST
A8A7PB31TDO
A11A9A12
A15A14A13
A27A19A16
VDDL A20A21
A29A23A25
A28A30A22
A31 TSIZ0 A26
WE1 TSIZ1
WE0 WE2 GPLA3
GPLA1 GPLA2 CS6
CS4CS7CS2
N/CCS3CS1BDIP
1716
PC12
TCK PB24 PB23 PA8PA7 VDDL PA5PC7PC4PD14 PD10 PD8
TDI PC11 PB22 PC9
TMS
PB26
PB25 PA9PC8
A6
A10
A17
N/C
A24
A18
WE3
GPLA0
N/C
CS5
CS0
GPLA4
WR
GPLB4
151413121110
TEABGIPB5IPB1 IPB6
GPLA5
BI
BR
BBIRQ6 IPB3 IPB0 VDDL
TA
PB19PA4 PB16 PD15
N/C
PC10 PA6 PB18PC5 PD13 PD9PD4PD5
N/CN/C
GND
TSIRQ2 IPB7 IPB2 MODCK1
BURST IPB4 ALEB IRQ4
PB17 PC6 PD11 PD3IRQ7 IRQ1 IRQ0
VDDH
TEXP
N/C
RSTCONFWAITB
HRESETSRESETPORESET
MODCK2
EXTCLKEXTAL
987
65432
D12D13
D23
D17
D15D14
D22
D25D20
D28D24
D26
DP1DP2
KAPWR
XTAL
PD12
PD7PD6
D27
D10
D16
D18
D19
D21D6
D29
D31
D30 CLKOUT
DP3
DP0
XFC VDDSYN
VSSSYN1VSSSYN
D8D0
D4
D11
D9
D2D3
VDDL
N/C
D1
D5
D7
N/C
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
Figure 63. Pin Assignments for the PBGA (Top View)—JEDEC Standard
For more information on the printed circuit board layout of the PBGA package, including thermal via
design and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note
available from your local Motorola sales office.
Table 28 lists significant changes between revisions of this document.
Table 28. Document Revision History
RevisionDateChange
27/2005Added footnote 3 to Table 5 (previously Table 4.5) and deleted IOL limit.
110/2002Added MPC850DSL. Corrected Figure 25 on page 34.
0.204/2002Updated power numbers and added Rev. C
0.111/2001Removed reference to 5 Volt tolerance capability on peripheral interface pins.
Replaced SI and IDL timing diagrams with better images. Updated to new
template, added this revision table.
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