Freescale MPC850 User Manual
Freescale Semiconductor
Technical Data
Document Number: MPC850EC
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications
Rev. 2, 07/2005
This document contains detailed information on power
considerations, AC/DC electrical characteristics, and AC
timing specifications for revision A,B, and C of the MPC850
Family.
1Overview
The MPC850 is a versatile, one-chip integrated
microprocessor and peripheral combination that can be used
in a variety of controller applications, excelling particularly
in communications and networking products. The MPC850,
which includes support for Ethernet, is specifically designed
for cost-sensitive, remote-access, and telecommunications
applications. It is provides functions similar to the MPC860,
with system enhancements such as universal serial bus
(USB) support and a larger (8-Kbyte) dual-port RAM.
In addition to a high-performance embedded MPC8xx core,
the MPC850 integrates system functions, s uch as a versatile
memory controller and a communications pr ocessor module
(CPM) that incorporates a specialized, independent RISC
communications processor (referred to as the CP). This
separate processor off-loads peripheral tasks from the
embedded MPC8xx core.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Electrical and Thermal Characteristics . . . . . . . . . . . . 7
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 9
6. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 39
8. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 41
9. Mechanical Data and O rdering Information . . . . . . . 63
10. Document Revision History . . . . . . . . . . . . . . . . . . . 68
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Overview
The CPM of the MPC850 supports up to seven serial channels, as follows:
• One or two serial communications controllers (SCCs). The SCCs support Ethernet, A T M
(MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent
mode of operation.
• One USB channel
• Two serial management controllers (SMCs)
2
• One I
C port
• One serial peripheral interface (SPI).
Table 1 shows the functionality supported by the members of the MPC850 family.
Table 1. MPC850 Functionality Matrix
Number of
Part
MPC850 1 Yes - Yes - 1
MPC850DE 2 Yes - Yes - 1
MPC850SR 2 Yes Yes Yes Yes 1
MPC850DSL 2 Yes Yes Yes No 1
SCCs
Supported
Ethernet
Support
ATM Support USB Support
Multi-channel
HDLC
Support
Additional documentation may be provided for parts listed in Table 1.
Number of
PCMCIA Slots
Supported
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
2 Freescale Semiconductor
Features
2Features
Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among
those components:
Embedded
MPC8xx
Core
Baud Rate
Generators
Paralle l I/O
Ports
—
UTOPIA
(850SR & DSL)
2-Kbyte
I-Cache
Instruction
Bus
Load/Store
Bus
Four
Timers
32-Bit RISC Communications
Processor (CP) and Pr ogram ROM
Timer
Instruction
MMU
1-Kbyte
D-Cache
Data
MMU
Interrupt
Controller
Dual-Port
RAM
Unified Bus
Peripheral Bus
20 Virtual
Serial DMA
Channels
and
2 Virtu al
IDMA
Channels
System Interface Un it
Memory Controller
Bus Inte rf ace Unit
System Functions
Real-Ti m e C lock
PCMCIA Interface
Communications
Processor
Module
TDMa
SCC2
SCC3
Time Slot Assigner
SMC1 SMC2
USB
Non-Multiplexed Serial Interface
SPI
2
I
C
Figure 1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— Perfor ms branch folding and branch prediction with conditional prefetch, but without
conditional execution
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 3
Features
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and eight protection groups
• Advanced on-chip emulation debug mode
• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian
memory systems
— Twenty-six external address lines
• Completely static design (0–80 MHz operation)
• System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— S oftware watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
• General-purpose timers
— Four 16-bit timers or two 32-bit timers
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
4 Freescale Semiconductor
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
• Si n gle so ck et PCMCIA- ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PC MC IA socke t
— Supports eight memory or I/O windows
• Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission
after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD
closes the receive buffer descriptor)
Features
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four
USB endpoints
— Three parallel I/O registers with open-drain capability
• Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
• Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
®
— AppleTalk
— Univer sal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 5
Features
• QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel
• One universal serial bus controller (USB)
— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
• Two serial management controllers (SMCs)
— UART
— Transparent
— Gener al circuit i nte rface ( GCI ) controller
— Can be connected to the time-division-multiplexed (TDM) channel
• One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
• One I2C® (interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment
• Time slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internall y connected to four serial channels (two SCCs and two SMCs)
• Low-power support
— Full high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze: core functional units disabled except time base, decrementer, PLL, memory controller ,
real-time clock, and CPM in low-power standby
— Sleep: all units disabled except real-time clock and periodic interrupt timer . PLL is active for
fast wake-up
— Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt
timer
— Low-power stop: to provide lower power dissipation
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
6 Freescale Semiconductor
Electrical and Thermal Characterist ics
— Separate power supply input to operate internal logic at 2.2 V when operating at or below
25 MHz
— Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V
internal) operation
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints
— Eac h watchpoint can generate a breakpoint internally
• 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins.
3 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850.
Table 2 provides the maximum ratings.
Table 2. Maximum Ratings
(GND = 0V)
Rating Symbol Value Unit
Supply voltage VDDH -0.3 to 4.0 V
VDDL -0.3 to 4.0 V
KAPWR -0.3 to 4.0 V
VDDSYN -0.3 to 4.0 V
Input voltage
Junction temperature
Storage temperature range T
1
Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction
applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not
be applied to its inputs).
2
The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient
temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power
dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of
the device.
1
2
V
in
T
j
stg
GND-0.3 to VDDH + 2.5 V V
0 to 95 (standard)
-40 to 95 (extended)
-55 to +150 °C
°C
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V
). Table 3 provides
CC
the package thermal characteristics for the MPC850.
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 7
Thermal Characteristics
4 Thermal Characteristics
Table 3 shows the thermal characteristics for the MPC850.
Table 3. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance for BGA
Thermal Resistance for BGA (junction-to-case) θ
1
For more information on the design of thermal vias on multilayer boards and BGA layout considerations in
general, refer to AN-1231/D, Plastic Ball Grid Array Applicati on Note available from your local Motorola sales
office.
2
Assumes natural convection and a single layer board (no thermal vias).
3
Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board
temperature rise of 20°C above ambient.
4
Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board
temperature rise of 13°C above ambient.
T
= T
J
P
= (VDD • IDD) + P
D
where:
P
is the power dissipation on pins
I/O
A
+ (P
•θJA)
D
1
I/O
θ
JA
θ
31
JA
θ
JA
JC
2
40
24
3
4
°C/W
°C/W
°C/W
8 °C/W
Table 4 provides power dissipation information.
Table 4. Power Dissipation (PD)
Characteristic Frequency (MHz) Typical
Power Dissipation
All Revisions
33 TBD 515 mW
40 TBD 590 mW
(1:1) Mode
50 TBD 725 mW
1
Typical power dissipation is measured at 3.3V
2
Maximum power dissipation is measured at 3.65 V
1
Table 5 provides the DC electrical characteristics for the MPC850.
Table 5. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating voltage at 40 MHz or less VDDH, VDDL,
KAPWR, VDDSYN
Operating voltage at 40 MHz or higher VDDH, VDDL,
KAPWR, VDDSYN
Input high voltage (address bus, data bus, EXTAL, EXTCLK,
and all bus control/status signals)
VIH 2.0 3.6 V
Maximum
2
Unit
3.0 3.6 V
3.135 3.465 V
Input high voltage (all general purpose I/O and peripheral pins) VIH 2.0 5.5 V
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
8 Freescale Semiconductor
Power Considerations
Table 5. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7*(VCC) VCC+0.3 V
Input leakage current, Vin = 5.5 V (Except TMS, TRST
and DSDI pins)
Input leakage current, Vin = 3.6V (Except TMS, TRST
and DSDI pins)
Input leakage current, Vin = 0V (Except TMS, TRST
and DSDI pins)
Input capacitance C
Output high voltage, IOH = -2.0 mA, VDDH = 3.0V
except XTAL, XFC, and open-drain pins
Output low voltage
CLKOUT
IOL = 3.2 mA
IOL = 5.3 mA
IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2
IOL = 8.9 mA TS
1
IP_B2/IOIS16_B
PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2,
PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/TOUT1
PA[4]/CLK4/TOUT2
PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3,
PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1
PB[18]/RTS2
PC[13]/L1ST7/RTS3
PC[8]/CD2
PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3]
2
WE2
GPL_A
OP2/MODCK1/STS
3 The MPC850 IBIS model must be used to accurately model the behavior of the Clkout output driver for the full and
half drive setting. Due to the nature of the Clkout output buffer, IOH and IOL for Clkout should be extracted from the
IBIS model at any output voltage level.
3
1
2
, TA, TEA, BI, BB, HRESET, SRESET
A[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1],
/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3,
/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1,
/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6,
, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2,
/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA,
BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR,
/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1,
, OP3/MODCK2/DSDO
, DSCK
, DSCK
, DSCK
/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2,
I
in
I
In
I
In
in
VOH 2.4 — V
VOL — 0.5 V
— 100 µA
—10µA
—10µA
—20pF
5 Power Considerations
The average chip-junction temperature, T
T
= TA + (P
J
θ
)(1)
•
D
JA
where
= Ambient temperature, °C
T
A
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 9
, in °C can be obtained from the equation:
J
Bus Signal Timing
θ
= Package thermal resista nce , junction to ambient, °C/W
JA
PD = P
P
INT
P
I/O
For most applications P
relationship between P
PD = K ÷ (T
+ P
INT
= IDD x V
I/O
, watts—chip internal power
DD
= Power dissipation on input and output pins—user determined
+ 273°C)(2)
J
< 0.3 • P
I/O
and TJ is:
D
and can be neglected. If P
INT
I/O
is neglected, an approximate
Solving equations (1) and (2) for K gives:
K = PD • (T
+ 273°C) + θ
A
JA
• P
2
(3)
D
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations (1) and (2) iteratively for any value of TA.
5.1 Layout Practices
Each VCC pin on the MPC850 should be provided with a low-i mpedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particula rly applies to the a ddres s and data busses. Maxim um PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in syst ems with higher capacit ive loads because th ese lo ads cr eate hi gher tran sient
currents in the V
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
CC
Special care should be taken to minimize the noise levels on the PLL supply pins.
6 Bus Signal Timing
Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing
information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10
pF . Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
10 Freescale Semiconductor
Table 6. Bus Operation Timing 1
Bus Signal Timing
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
Cap Load
(default
50 pF)
B1 CLKOUT period 20 — 30.30 — 25 — — — ns
B1a EXTCLK to CLKOUT phase
-0.90 0.90 -0.90 0.90 -0.90 0.90 — 50.00 ns
skew (EXTCLK > 15 MHz and
MF <= 2)
B1b EXTCLK to CLKOUT phase
-2.30 2.30 -2.30 2.30 -2.30 2.30 — 50.00 ns
skew (EXTCLK > 10 MHz and
MF < 10)
B1c CLKOUT phase jitter (EXTCLK
> 15 MHz and MF <= 2)
B1d CLKOUT phase jitter
B1e CLKOUT frequency jitter (MF <
B1f CLKOUT frequency jitter (10 <
B1g CLKOUT frequency jitter (MF >
2
10)
MF < 500)
2
500)
2
2
2
B1h Frequency jitter on EXTCLK
-0.60 0.60 -0.60 0.60 -0.60 0.60 — 50.00 ns
-2.00 2.00 -2.00 2.00 -2.00 2.00 — 50.00 ns
— 0.50 — 0.50 — 0.50 — 50.00 %
— 2.00 — 2.00 — 2.00 — 50.00 %
— 3.00 — 3.00 — 3.00 — 50.00 %
3
— 0.50 — 0.50 — 0.50 — 50.00 %
Unit
B2 CLKOUT pulse width low 8.00 — 12.12 — 10.00 — — 50.00 ns
B3 CLKOUT width high 8.00 — 12.12 — 10.00 — — 50.00 ns
B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 50.00 ns
B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 50.00 ns
B7 CLKOUT to A[6–31],
RD/WR
, BURST, D[0–31],
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
DP[0–3] invalid
B7a CLKOUT to TSIZ[0–1], REG
RSV
, AT[0–3], BDIP, PTR
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
,
invalid
B7b CLKOUT to BR
VFLS[0–1], VF[0–2] IWP[0–2],
LWP[0–1], STS
B8 CLKOUT to A[6–31],
RD/WR
, BURST, D[0–31],
, BG, FRZ,
invalid
4
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
DP[0–3] valid
B8a CLKOUT to TSIZ[0–1], REG
RSV
, AT[0–3] BDIP, PTR valid
B8b CLKOUT to BR
, BG,
VFLS[0–1], VF[0–2], IWP[0–2],
FRZ, LWP[0–1], STS
valid
,
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
5.00 11.74 7.58 14.33 6.25 13.00 0.250 50.00 ns
4
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 11
Bus Signal Timing
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
B9 CLKOUT to A[6–31] RD/WR,
BURST
, D[0–31], DP[0–3],
TSIZ[0–1], REG
PTR
high-Z
B11 CLKOUT to TS
B11a CLKOUT to TA
, RSV, AT[0–3],
, BB assertion 5.00 11.00 7.58 13.58 6.25 12.25 0.250 50.00 ns
, BI assertion,
(When driven by the memory
controller or PCMCIA interface)
B12 CLKOUT to TS
B12a CLKOUT to TA
, BB negation 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
, BI negation
(when driven by the memory
controller or PCMCIA interface)
B13 CLKOUT to TS
B13a CLKOUT to TA
, BB high-Z 5.00 19.00 7.58 21.58 6.25 20.25 0.250 50.00 ns
, BI high-Z,
(when driven by the memory
controller or PCMCIA interface)
B14 CLKOUT to TEA
B15 CLKOUT to TEA
assertion 2.50 10.00 2.50 10.00 2.50 10.00 — 50.00 ns
high-Z 2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
Cap Load
(default
50 pF)
Unit
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
2.50 9.25 2.50 9.25 2.50 9.25 — 50.00 ns
2.50 11.00 2.50 11.00 2.50 11.00 — 50.00 ns
2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns
B16 TA
B16a TEA
B16b BB
B17 CLKOUT to TA
B17a CLKOUT to KR
, BI valid to CLKOUT(setup
5
time)
, KR, RETRY, valid to
CLKOUT (setup time
, BG, BR valid to CLKOUT
(setup time)
6
) 5
, TEA, BI, BB,
BG
, BR valid (Hold time).
, RETRY, except
TEA
valid (hold time)
B18 D[0–31], DP[0–3] valid to
CLKOUT rising edge (setup
7
time)
B19 CLKOUT rising edge to
D[0–31], DP[0–3] valid (hold
7
time)
B20 D[0–31], DP[0–3] valid to
CLKOUT falling edge (setup
8
time)
B21 CLKOUT falling edge to
D[0–31], DP[0–3] valid (hold
8
time)
9.75 — 9.75 — 9.75 — — 50.00 ns
10.00 — 10.00 — 10.00 — — 50.00 ns
8.50 — 8.50 — 8.50 — — 50.00 ns
5
1.00 — 1.00 — 1.00 — — 50.00 ns
2.00 — 2.00 — 2.00 — — 50.00 ns
6.00 — 6.00 — 6.00 — — 50.00 ns
1.00 — 1.00 — 1.00 — — 50.00 ns
4.00 — 4.00 — 4.00 — — 50.00 ns
2.00 — 2.00 — 2.00 — — — —
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
12 Freescale Semiconductor
Table 6. Bus Operation Timing 1 (continued)
Bus Signal Timing
Num Characteristic
B22 CLKOUT rising edge to CS
asserted GPCM ACS = 00
B22a CLKOUT falling edge to CS
asserted GPCM ACS = 10,
TRLX = 0,1
B22b CLKOUT falling edge to CS
asserted GPCM ACS = 11,
TRLX = 0, EBDF = 0
B22c CLKOUT falling edge to CS
asserted GPCM ACS = 11,
TRLX = 0, EBDF = 1
B23 CLKOUT rising edge to CS
negated GPCM read access,
GPCM write access ACS = 00,
TRLX = 0 & CSNT = 0
B24 A[6–31] to CS
ACS = 10, TRLX = 0.
B24a A[6–31] to CS
ACS = 11, TRLX = 0
asserted GPCM
asserted GPCM
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
— 8.00 — 8.00 — 8.00 — 50.00 ns
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns
2.00 8.00 2.00 8.00 2.00 8.00 — 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
Cap Load
(default
Unit
50 pF)
B25 CLKOUT rising edge to OE
WE[0–3]
B26 CLKOUT rising edge to OE
negated
B27 A[6–31] to CS
ACS = 10, TRLX = 1
B27a A[6–31] to CS
ACS = 11, TRLX = 1
B28 CLKOUT rising edge to
WE[0–3]
access CSNT = 0
B28a CLKOUT falling edge to
WE[0–3]
access TRLX = 0,1 CSNT = 1,
EBDF = 0
B28b CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 0
asserted
asserted GPCM
asserted GPCM
negated GPCM write
negated GPCM write
,
— 9.00 — 9.00 — 9.00 — 50.00 ns
2.00 9.00 2.00 9.00 2.00 9.00 — 50.00 ns
23.00 — 36.00 — 29.00 — 1.250 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
— 9.00 — 9.00 — 9.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
— 12.00 — 14.00 — 13.00 0.250 50.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 13
Bus Signal Timing
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
B28c CLKOUT falling edge to
WE[0–3]
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1
B28d CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 1
B29 WE[0–3]
DP[0–3] high-Z GPCM write
access, CSNT = 0
B29a WE[0–3]
DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0
B29b CS
DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0
negated GPCM write
negated to D[0–31],
negated to D[0–31],
negated to D[0–31],
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns
— 14.00 — 18.00 — 16.00 0.375 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
Cap Load
(default
50 pF)
Unit
B29c CS
B29d WE[0–3]
B29e CS
B29f WE[0–3]
B29g CS
negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0
negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
negated to D[0–31],
negated to D[0–31],
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
5.00 — 9.00 — 7.00 — 0.375 50.00 ns
5.00 — 9.00 — 7.00 — 0.375 50.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
14 Freescale Semiconductor
Table 6. Bus Operation Timing 1 (continued)
Bus Signal Timing
Num Characteristic
B29h WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
B29i CS
negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
B30 CS
, WE[0–3] negated to
A[6–31] invalid
GPCM write access
B30a WE[0–3]
negated to A[6–31]
9
invalid
GPCM write access, TRLX = 0,
CSNT = 1, CS
negated to
A[6–31] invalid GPCM write
access TRLX = 0, CSNT =1,
ACS = 10 or ACS = 11, EBDF =
0
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
Cap Load
(default
50 pF)
Unit
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B30b WE[0–3]
invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS
A[6–31] Invalid GPCM write
access TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
B30c WE[0–3]
invalid
GPCM write access, TRLX = 0,
CSNT = 1. CS
A[6–31] invalid GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
B30d WE[0–3]
invalid GPCM write access
TRLX = 1, CSNT =1, CS
negated to A[6–31] invalid
GPCM write access TRLX = 1,
CSNT = 1, ACS = 10 or ACS =
11, EBDF = 1
negated to A[6–31]
negated to
negated to A[6–31]
negated to
negated to A[6–31]
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
5.00 — 8.00 — 6.00 — 0.375 50.00 ns
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 15
Bus Signal Timing
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
B31 CLKOUT falling edge to CS
valid - as requested by control
bit CST4 in the corresponding
word in the UPM
B31a CLKOUT falling edge to CS
valid - as requested by control
bit CST1 in the corresponding
word in the UPM
B31b CLKOUT rising edge to CS
- as requested by control bit
CST2 in the corresponding
word in the UPM
B31c CLKOUT rising edge to CS
- as requested by control bit
CST3 in the corresponding
word in the UPM
B31d CLKOUT falling edge to CS
valid - as requested by control
bit CST1 in the corresponding
word in the UPM EBDF = 1
valid
valid
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns
Cap Load
(default
50 pF)
Unit
B32 CLKOUT falling edge to BS
valid - as requested by control
bit BST4 in the corresponding
word in the UPM
B32a CLKOUT falling edge to BS
valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 0
B32b CLKOUT rising edge to BS
- as requested by control bit
BST2 in the corresponding
word in the UPM
B32c CLKOUT rising edge to BS
- as requested by control bit
BST3 in the corresponding
word in the UPM
B32d CLKOUT falling edge to BS
valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 1
B33 CLKOUT falling edge to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
valid
valid
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
16 Freescale Semiconductor
Table 6. Bus Operation Timing 1 (continued)
Bus Signal Timing
Num Characteristic
B33a CLKOUT rising edge to GPL
valid - as requested by control
bit GxT3 in the corresponding
word in the UPM
B34 A[6–31] and D[0–31] to CS
valid
- as requested by control bit
CST4 in the corresponding
word in the UPM
B34a A[6–31] and D[0–31] to CS
valid
- as requested by control bit
CST1 in the corresponding
word in the UPM
B34b A[6–31] and D[0–31] to CS
valid
- as requested by CST2 in the
corresponding word in UPM
B35 A[6–31] to CS
valid - as
requested by control bit BST4 in
the corresponding word in UPM
B35a A[6–31] and D[0–31] to BS
valid
- as requested by BST1 in the
corresponding word in the UPM
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
Cap Load
(default
50 pF)
Unit
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
13.00 — 21.00 — 17.00 — 0.750 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B35b A[6–31] and D[0–31] to BS
- as requested by control bit
BST2 in the corresponding
word in the UPM
B36 A[6–31] and D[0–31] to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
B37 UPWAIT valid to CLKOUT
falling edge
B38 CLKOUT falling edge to
UPWAIT valid
B39 AS
valid to CLKOUT rising edge
11
10
10
B40 A[6–31], TSIZ[0–1], RD/WR
BURST
, valid to CLKOUT rising
edge.
B41 TS
valid to CLKOUT rising edge
(setup time)
13.00 — 21.00 — 17.00 — 0.750 50.00 ns
valid
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
6.00 — 6.00 — 6.00 — — 50.00 ns
1.00 — 1.00 — 1.00 — — 50.00 ns
7.00 — 7.00 — 7.00 — — 50.00 ns
7.00 — 7.00 — 7.00 — — 50.00 ns
,
7.00 — 7.00 — 7.00 — — 50.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 17
Bus Signal Timing
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
B42 CLKOUT rising edge to TS valid
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
2.00 — 2.00 — 2.00 — — 50.00 ns
Cap Load
(default
50 pF)
(hold time)
B43 AS
negation to memory
—TBD—TBDTBD— — 50.00 ns
controller signals negation
1
The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on
the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to
be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the
part. The following equations should be used in these calculations.
For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:
FFACTOR x 1000
D =
F
(D
- 20 x FFACTOR)
50
+
For maxima:
FFACTOR x 1000
D =
F
(D
-20 x FFACTOR)
50
++
1ns(CAP LOAD - 50) / 10
where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D
is the parameter value defined for 50 MHz
50
CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.
2
Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.
3
If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
4
The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for
BG
output is relevant when the MPC850 is selected to work with internal bus arbiter.
5
The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and
not when the memory controller or the PCMCIA interface drives them).
6
The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
timing for BG
7
The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input
input is relevant when the MPC850 is selected to work with the external bus arbiter.
signal is asserted.
8
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
9
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
10
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.
11
The AS signal is considered asynchronous to CLKOUT.
Unit
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
18 Freescale Semiconductor
Figure 2 is the control timing diagram.
Bus Signal Timing
CLKOUT
Outputs
Outputs
Inputs
Inputs
2.0 V
B
2.0 V
0.8 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
C
2.0 V
0.8 V
0.8 V
A
D
2.0 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
A Maximum output delay specification
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
Figure 2. Control Timing
Figure 3 provides the timing for the external clock.
CLKOUT
B1
B1
B4
Figure 3. External Clock Timing
B3
B2
B5
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 19
Bus Signal Timing
Figure 4 provides the timing for the synchronous output signals.
CLKOUT
B8
B7 B9
Output
Signals
B8a
B9B7a
Output
Signals
B8b
B7b
Output
Signals
Figure 4. Synchronous Output Signals Timing
Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B12B11
, BB
TS
B13a
B11a
TA, BI
B14
TEA
Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing
B12a
B15
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
20 Freescale Semiconductor
Figure 6 provides the timing for the synchronous input signals.
CLKOUT
B16
, BI
TA
B16a
B17a
TEA, KR,
RETRY
B16b
BB, BG, BR
Bus Signal Timing
B17
B17
Figure 6. Synchronous Input Signals Timing
Figure 7 provides normal case timing for input data.
CLKOUT
B16
TA
B18
D[0:31],
DP[0:3]
Figure 7. Input Data Timing in Normal Case
B17
B19
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 21
Bus Signal Timing
Figure 8 provides the timing for the input data controlled by the UPM in the memory controller.
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller
Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM
factors.
CLKOUT
TS
A[6:31]
CSx
OE
WE[0:3]
D[0:31],
DP[0:3]
B11 B12
B8
B22
B25
B28
B23
B26
B19
B18
Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00)
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
22 Freescale Semiconductor
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