Freescale MPC7455 User Manual

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Freescale Semiconductor

Technical Data

MPC7455
RISC Microprocessor
Hardware Specifications

The MPC7455 and MPC7445 are implementations of the
PowerPC™ microprocessor family of reduced instruction set
computer (RISC) microprocessors. This document is primarily
concerned with the MPC7455; however, unless otherwise noted,
all information here also applies to the MPC7445. This document
describes pertinent electrical and physical characteristics of the
MPC7455. For functional characteristics of the processor, refer to
the MPC7450 RISC Microprocessor Family User’s Manual. To
locate any published updates for this document, refer to the
website at http://www.freescale.com.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. Comparison with the MPC7400, MPC7410,

4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Elect r ical and Thermal Characteristics . . . . . . . . . . . 10

6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 41

9. System Design Information . . . . . . . . . . . . . . . . . . . 45

10. Document Revision History . . . . . . . . . . . . . . . . . . . 59

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 60

MPC7455EC

Rev. 4.1, 02/2005

Contents

MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . . 7

1Overview

The MPC7455 is the thir d implementation o f the fourth g eneration
(G4) microprocess ors from Freescale. The MPC7455 imple ments
the full PowerPC 32-bit architecture and is targeted at networking
and computing systems applications. The MPC7455 consists of a
processor core, a 256-Kbyte L2, and an internal L3 tag and
controller which support a glueless backside L3 cache through a
dedicated high-ba ndwidth interface. The MPC7445 is identical to
the MPC7455 except it does not support the L3 cache int erface.

Figure 1 shows a block diagram of the MPC7455.

© Freescale Semiconductor, Inc., 2005. All rights reserved.

Overview

I Cache

32-Kbyte

+x÷

FPSCR

Floating-

Stations (2)

D Cache

Tags

128-Bit (4 Instructions)

ITLB

128-Entry

32-Kbyte

Ta g s

DTLB

128-Entry

EA

Reservation

FPR File

PA

Point Unit

Buffers

16 Rename

FPSCR

Cacheable Store

Instruction Fetch (2)

(LSQ)

64-Bit

64-Bit

L1 Store Queue

L1 Service Queues

L1 Load Miss (5)

L1 Load Queue (LLQ)

Request (1)

Instruction MMU

Instruction Queue

Instruction Unit

Load Miss

Block 1 (32-Byte)

256-Kbyte Unified L2 Cache/Cache Controller

System Bus Interface

Stat us

Block 0 (32-Byte)

Status

Line

Ta g s

L2 Prefetch (3)

Bus Store Queue

L3CR

Stores

L1 Push

Completed

32-Bit

32-Bit

+

+

+

Memory Subsystem

32-Bit

x ÷

128-Bit128-Bit

Snoop Push/

Interventions

L2 Store Queue (L2SQ)

L1 Castouts

(4)

Push

Castout

Queue

(9)

External SRAM

36-Bit Address Bus 64-Bit Data Bus

Bus Accumulator

(1 or 2 Mbytes)

64-Bit Data

(8-Bit Parity)

Vector Touch Engine

Queue

Reservation

Reservation

Reservation

Reservation

Reservation

L1 Castout

(EA Calculation )

Stores

+

Finished

Buffers

GPR File

16 Rename

Integer

Integer

Integer

Buffers

16 Rename

Unit 2

(3)

Unit 2

Integer

Unit 2 Unit 1

FPU

Vector

Stat ion

Stat ion

Stat ion

Stations (2)

VR File

Stat ion

IBAT Array

Data MMU

SRs

(Shadow)

(12-Word)

Fetcher

Branch Processing Unit

Unit

Dispatch

LR

CTR

BTIC (128-Entry)

BHT (2048-Entry)

DBAT Array

SRs

(Original)

GPR Issue

(6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue )

VR Issue FPR Issue

Reservation

Load/Store Unit

Stations (2-Entry)

To u ch

Vector

Stat ion

Reservation

Stat ion

Reservation

Additional Features

• Time Base Counter/Decrementer

• Clock Multiplier

• JTAG/COP Interface

• Thermal/Power Management

96-Bit (3 Instructions)

• Performance Monitor

Stat io n

Reservation

Unit 1

Vector

Integer

Unit 2

Ve cto r

Integer

Unit

Vector

Permute

Completion Unit

L3 Cache Controller

StatusTa g s

Block 0/1 Line

Bus Accumulator

(16-Entry)

Completion Queue

18-Bit

Address

Not in

MPC7445

Completes up to three instructions per clock

Figure 1. MPC7455 Block Diagram

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

2 Freescale Semiconductor

Features

The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD
multimedia unit. The memory storage subsyste m supports the MPX bus protocol and a subset of the 60x bus protocol
to main m emory a nd other system r esources. The L3 in terface supports 1 or 2 Mbytes of external SRAM for L3
cache data.

Note that the MPC7455 is footprint-compatible with the MPC7450 and MPC7451, and the MPC7445 is
footprint-co mpatible with the MPC7441.

2Features

This section summarizes features of the MPC7455 implementation of the PowerPC architecture.
Major features of the MPC7455 are as follows:

• High-performance, superscalar microprocessor
— As many as four instructions can be fetched from the instruction cache at a time
— As many as thr ee inst ruct i on s ca n be disp atch ed to the issue queu e s at a time
— As many as 12 instructions can be in the instruction queue (IQ)
— As many as 16 instructions can be at some stage of execution simultaneously
— Single-cycle execution for most instructions
— One instruction per clock cy cle thr oughput for most instructions
— Seven-stage pipeline control

• Eleven independent exec ution units and three register fil es
— Branch processing unit (BPU) features static and dynamic branch predi ction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of

branch instru ctions that ha ve been encounter ed in branc h/loop code sequ ences. If a ta rget inst ruction
is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available
from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions
in the target stre am.

– 2048-entry bran ch history table (BHT) with two bits per entry for four leve ls of

prediction—not-ta ken, strongly not-taken, ta ken, and strongly taken
– Up to three outstanding spe culative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are often

removed from the instructi on stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link Register

(bclr) instru cti ons

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical I Us (IU1a , IU1 b, an d IU1c) can execute all integer instructions except multiply,

divide, and move to/from special-purpose register instructions
– IU2 executes misc ellaneous instruction s inc luding the CR logi cal oper ations, integer multiplica tion

and division instructions, and move to/from special-pu rpose register instructions

— Five-stag e FP U and a 32- en try FPR file

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for de normalized numbers

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 3

Features

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU)
– Ve ctor integ er unit 1 (VIU1) handles short-latenc y AltiVec™ integer ins tructions, s uch as vect or add

instructions (vaddsbs, vaddshs, and vaddsws, for example)
– Vector integer unit 2 (VIU2) handles longer -latency AltiVec integer instruction s, suc h as vector

multiply add instruct ions (vmhaddshs, vmhraddshs, and vmladduhm, for example)
– Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instructi on load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations
– Three-cycle GPR and AltiVec load latency (byte, half -word, word, vector) with one-cycle

throughput
– Four-cyc le FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated ad der calculates effec tiv e add ress es (EA s )
– Supports store gat hering
– Performs alignmen t, nor malization, and precision conversion for floating-poi nt data
– Executes cache control and TLB instructions
– Performs alignmen t, z ero pa dding, and sign extension for integer data
– Supports hits under mis ses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses

• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instru ctions, respect ively ,
in a cycle. Instruct io n disp a tc h requi re s the follo w ing:

— Instructions can be dis patched only from the three lowest IQ entries—IQ0, IQ1, and IQ2
— A maximum of three instructions can be dispa tched to the issue queues per clock cycle
— Space mus t be avai l abl e in the CQ fo r an instr u ction to disp at ch (t h is inclu des ins tru ct io ns tha t are

assigned a space in the CQ but not in an issue queue)

• Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers

• Dispatch unit
— Decode/dispatch stage fully decodes each instruction

• Completion unit
— The completion unit retire s an instruction from the 16-entry comple tion queue (CQ) when all

instructions ahead of it have been completed, the instructi on has finishe d execution , and no exceptions

are pending.
— Guarantees sequentia l pr ogramming model (precise exception model)
— Monitors all dispatche d instructions and retires them in orde r
— Tracks unr esolved branches and flushes inst ructions after a mispredicted branc h

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

4 Freescale Semiconductor

— Retires as many as three instructions per clock cycle

• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruc tion and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-wor d) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cac he can provide four instructions per clock cycle; data cache can provide four words per

clock cycle
— Caches can be disabled in softwar e
— Caches can be locked in software
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cac he except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding

is used for AltiVec loads and instruction fetches. Other accesses use critical double -word forwarding.

• Level 2 (L2) cac he interface
— On-chip, 256-Kbyte, ei ght-way set-associative unif ied instruction and data cache
— Fully pipelined to provi de 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load lat en cy for an L1 data cache mis s that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache

• Level 3 (L3) cache interface (not implemented on MPC7445)
— Provides critical double-word forwarding to the requesting unit
— Internal L 3 cach e co ntr oller and tags
— External data SRAMs
— Support for 1- and 2-Mbyte L3 caches
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1M) or 128-byte (2M) sector ed line size
— Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space
— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelin ed synchronous Burst

SRAMs, and pipelined (register-register) late write synchronous Burst SRAMs
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle

Features

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 5

Features

• Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation f or 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable a s write-back/write-through, caching-inhibited/caching-allowed, and m emory

coherency enforced /memory co herency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruc tion and data translation lookasi de buffers (TLBs)

– Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm

– TLBs are hardware - or softwar e-reloa dable (that is, on a TLB miss a page table search is pe rformed

in hardware or by system software)

• Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
— L2 cache is ful ly pipel in ed to pro vide 2 5 6 bits pe r proc es so r cloc k cycl e t o the L1 cac h e
— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and

L2/L3 bus
— As many as 16 out-of-order transactions can be present on the MPX bus
— Store mer ging for multiple store misses to the same line. Only coherency action taken (address-only)

for store misses merge d to all 32 bytes of a cache block (no data tenure needed).
— Three-entry finish ed store queue and five-entry comple ted store queue between the LSU and the L1 data

cache
— Separate additiona l queues for eff icie nt buffe ring of outbound dat a (such as castout s and write through

stores) from the L1 data cache and L2 cache

• Multiprocessing support features include the following:
— Hardware-enforc ed, MESI cache coherency protocols for data cache
— Load/store with reserva tion instruction pair for at omic memory ref erences, semaphores, and other

multiprocessor ope rations

• Power and thermal management
— 1.3-V proces s or co re
— The following three power-saving modes are available to the system:

– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and JTAG

logic remain runn ing. The part goes into the doze state to snoop memory opera tions on the bus and
then back to nap using a QREQ

/QACK processor- system handshake protocol.

– Sleep—Power consump tion is f urthe r reduce d by di sabling b us snoo ping, le aving onl y the PLL in a

locked and running state. All internal functional units are disabled.

– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system can then

disable the SYSCLK source for greater system power savings. Power-on reset procedures for
restarting and relocking the PLL must be followed on exiting the deep sleep state.

— Thermal management facility provides software-controllable thermal management. Thermal

management is per formed thr ough the use of thr ee sup ervisor -le vel re gisters and an MPC7455-sp ecific
ther mal management exception.

— Instruction cache throttling provides control of instruction fetching to limit power consumption

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

6 Freescale Semiconductor

Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441

• Performance monitor can be used to help debug syst em designs and improve software efficiency

• In-system testabi lity and debugging features through JTAG boundary-scan capability

• Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only

• Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity check in g on the L 2 and L3 cach e tag arrays

3 Comparison with the MPC7400, MPC7410, MPC7450,

MPC7451, and MPC7441

Table 1 compares the key features of the MPC7455 with the key features of the earlier MPC7400, MPC7410,

MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels per cycle is
reduced. Also, to achieve this higher frequency, the pipeline of the MPC7455 is extended (compared to the
MPC7400), while maintaining the same level of performance as measured by the number of instructions executed
per cycle (IPC).

Table 1. Microarchitecture Comparison

Microarchitectural Specs MPC7455/MPC7445

Basic Pipeline Functions

Logic inversions per cycle 18 18 28

Pipeline stages up to execute 5 5 3

Total pipeline stages (minimum) 7 7 4

Pipeline maximum instruction
throughput

Instruction buffer size 12 12 6

Completion buffer size 16 16 8

Renames (integer, float, vector) 16, 16, 16 16, 16, 16 6, 6, 6

Maximum Execution Throughput

SFX 332

Vector 2 (Any 2 of 4 Units) 2 (Any 2 of 4 Units) 2 (Permute/Fixed)

Scalar floating-point 1 1 1

3 + Branch 3 + Branch 2 + Branch

Pipeline Resources

MPC7450/MPC7451/

MPC7441

MPC7400/MPC7410

Out-of-Order Window Size in Execution Queues

SFX integer units 1 Entry × 3 Queues 1 Entry × 3 Queues 1 Entry × 2 Queues

Vector units In Order, 4 Queues In Order, 4 Queues In Order, 2 Queues

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 7

Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441

Table 1. Microarchitecture Comparison (continued)

Microarchitectural Specs MPC7455/MPC7445

MPC7450/MPC7451/

MPC7441

MPC7400/MPC7410

Scalar floating-point unit In Order In Order In Order

Branch Processing Resources

Prediction structures BTIC, BHT, Link Stack BTIC, BHT, Link Stack BTIC, BHT

BTIC size, associativity 128-Entry, 4-Way 128-Entry, 4-Way 64-Entry, 4-Way

BHT size 2K-Entry 2K-Entry 512-Entry

Link stack depth 8 8 None

Unresolved branches supported 3 3 2

Branch taken penalty (BTIC hit) 1 1 0

Minimum misprediction penalty 6 6 4

Execution Unit Timings (Latency-Throughput)

Aligned load (integer, float, vector) 3-1, 4-1, 3-1 3-1, 4-1, 3-1 2-1, 2-1, 2-1

Misaligned load (integer, float, vector) 4-2, 5-2, 4-2 4-2, 5-2, 4-2 3-2, 3-2, 3-2

L1 miss, L2 hit latency 9 Data/13 Instruction 9 Data/13 Instruction 9 (11)

1

SFX (aDd Sub, Shift, Rot, Cmp, logicals) 1-1 1-1 1-1

Integer multiply (32 × 8, 32 × 16, 32 × 32) 3-1, 3-1, 4-2 3-1, 3-1, 4-2 2-1, 3-2, 5-4

Scalar float 5-1 5-1 3-1

VSFX (vector simple) 1-1 1-1 1-1

VCFX (vector complex) 4-1 4-1 3-1

VFPU (vector float) 4-1 4-1 4-1

VPER (vector permute) 2-1 2-1 1-1

MMUs

TLBs (instruction and data) 128-Entry, 2-Way 128-Entry, 2-Way 128-Entry, 2-Way

Tablewalk mechanism Hardware + Software Hardware + Software Hardware

Instruction BATs/data BATs 8/8 4/4 4/4

L1 I Cache/D Cache Features

Size 32K/32K 32K/32K 32K/32K

Associativity 8-Way 8-Way 8-Way

Locking granularity Way Way Full Cache

Parity on I cache Word Word None

Parity on D cache Byte Byte None

Number of D cache misses (load/store) 5/1 5/1 8 (Any Combination)

Data stream touch engines 4 Streams 4 Streams 4 Streams

On-Chip Cache Features

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

8 Freescale Semiconductor

Table 1. Microarchitecture Comparison (continued)

General Parameters

Microarchitectural Specs MPC7455/MPC7445

Cache level L2 L2 L2 tags and controller

Size/associativity 256-Kbyte/8-Way 256-Kbyte/8-Way

Access width 256 Bits 256 Bits

Number of 32-byte sectors/line 2 2

Parity Byte Byte

Off-Chip Cache Support

Cache level L3L3L2

On-chip tag logical size 1MB, 2MB 1MB, 2MB 0.5MB, 1MB, 2MB

Associativity 8-Way 8-Way 2-Way

Number of 32-byte sectors/line 2, 4 2, 4 1, 2, 4

Off-chip data SRAM support MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 LW, PB2, PB3

Data path width 64 64 64

Direct mapped SRAM sizes 1 Mbyte, 2 Mbytes 1 Mbyte, 2 Mbytes 0.5 Mbyte, 1 Mbyte,

Parity Byte Byte Byte

Notes:

1. Numbers in parentheses are for 2:1 SRAM.

2. Not implemented on MPC7445 or MPC7441.

3. Private memory feature not implemented on MPC7400.

MPC7450/MPC7451/

MPC7441

2

MPC7400/MPC7410

only (see off-chip cache

support below)

2Mbytes

3

4 General Parameters

The following list provide s a summary of the general parameters of the MPC7455:

T echnology 0.18 µm CMOS, six-layer metal

2

Die size 8.69 mm × 12.17 mm (106 mm
Trans istor count 33 million
Logic design Fully-static
Packages MPC7445: Surface mount 360 ceramic ball grid array (CBGA)

MPC7455: Surface mount 483 ceramic ball gr id array (CBGA)
Core power supply 1.3 V ± 50 mV DC nominal
I/O power supply 1.8 V ± 5% DC, or

2.5 V ± 5% DC, or

1.5 V ± 5% DC (L3 interface only)

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 9

)

Electrical and Thermal Characteristics

5 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal c haracteristics for the MPC7455.

5.1 DC Electrical Characteristics

The tables in this section describe the MPC7455 DC electrical characteristics. Table 2 provides the absolute
maximum ratings.

Table 2. Absolute Maximum Ratings

Characteristic Symbol Maximum Value Unit Notes

1

Core supply voltage V

PLL supply voltage AV

Processor bus supply voltage BVSEL = 0 OV

BVSEL = HRESET

L3 bus supply voltage L3VSEL = ¬HRESET

or OV

DD

OVDD –0.3 to 2.7 V 3, 7

GV

L3VSEL = 0 GV

L3VSEL = HRESET

or GV

DD

GVDD –0.3 to 2.7 V 3, 10

Input voltage Processor bus V

L3 bus V

JTAG signals V

Input voltage Processor bus V

JTAG signals V

Storage temperature range T

DD

DD

–0.3 to 1.95 V 3, 6

DD

DD

DD

in

in

in

in

in

stg

–0.3 to 1.95 V 4

–0.3 to 1.95 V 4

–0.3 to 1.65 V 3, 8

–0.3 to 1.95 V 3, 9

–0.3 to OVDD + 0.3 V 2, 5

–0.3 to GVDD + 0.3 V 2, 5

–0.3 to OVDD + 0.3 V

–0.3 to OVDD + 0.3 V 2, 5

–0.3 to OVDD + 0.3 V

–55 to 150 °C

Notes:

1. Functional and tested operating conditions are given in Tab le 4. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.

2. Caution: Vin must not exceed OV

3. Caution: OV

/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be

DD

or GVDD by more than 0.3 V at any time including during power-on reset.

DD

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

4. Caution: V

/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be

DD

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

5. V

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

in

6. BVSEL must be set to 0, such that the bus is in 1.8 V mode.

7. BVSEL must be set to HRESET

8. L3VSEL must be set to ¬HRESET

or 1, such that the bus is in 2.5 V mode.

(inverse of HRESET), such that the bus is in 1.5 V mode.

9. L3VSEL must be set to 0, such that the bus is in 1.8 V mode.

10.L3VSEL must be set to HRESET

or 1, such that the bus is in 2.5 V mode.

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

10 Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 2 shows the undershoot and overshoot voltage on the MPC7455.

OVDD/GVDD + 20%

OVDD/GVDD + 5%

OVDD/GV

GND – 0.3 V

GND – 0.7 V

DD

V

V

GND

IH

IL

Not to Exceed 10%

of t

SYSCLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7455 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7455 core voltage must always be provided at nominal 1.3 V (see Table 4 f or actual
recommended core voltage ). Voltage to the L3 I/Os and processor inte rfa ce I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is
selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage
will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins.

Table 3. Input Threshold Voltage Setting

BVSEL Signal

0 1.8 V 0 1.8 V 1, 4

¬HRESET

HRESET

1 2.5 V 1 2.5 V 1

Notes:

1. Caution: The input threshold selection must agree with the OV

2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET
change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET
for selecting this mode of operation.

3. Applicable to L3 bus interface only. ¬HRESET

4. If used, pulldown resistors should be less than 250 Ω.

5. Not implemented on MPC7445.

Processor Bus Input

Threshold is Relative to:

Not Available ¬HRESET 1.5 V 1, 3

2.5 V HRESET 2.5 V 1, 2

L3VSEL Signal

/GVDD voltages supplied. See notes in Table 2.

DD

is the inverse of HRESET.

L3 Bus Input Threshold is

5

Relative to:

. This is the preferred method

Notes

so that the two signals

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 11

Electrical and Thermal Characteristics

Table 4 provides the recommended operating conditions for the MPC7455.

Table 4. Recommended Operating Conditions

Recommended Value

Characteristic Symbol

1

Unit Notes

Min Max

Core supply voltage V

PLL supply voltage AV

Processor bus supply voltage BVSEL = 0 OV

BVSEL = HRESET

or OV

DD

OV

L3 bus supply voltage L3VSEL = 0 GV

L3VSEL = HRESET

L3VSEL = ¬HRESET

or GV

DD

GV

GV

Input voltage Processor bus V

L3 bus V

JTAG signals V

Die-junction temperature T

DD

DD

DD

DD

DD

DD

DD

in

in

in

j

1.3 V ± 50 mV V

1.3 V ± 50 mV V 2

1.8 V ± 5% V

2.5 V ± 5% V

1.8 V ± 5% V

2.5 V ± 5% V

1.5 V ± 5% V

GND OV

GND GV

GND OV

DD

DD

DD

V

V

V

0105°C

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.

2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the
voltage at the AV

pin which may be reduced from VDD by the filter.

DD

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

12 Freescale Semiconductor

Table 5 provides the package thermal characteristics for the MPC7455.

Table 5. Package Thermal Characteristics

Characteristic Symbol

Electrical and Thermal Characteristics

6

Value

Unit Notes

MPC7445 MPC7455

Junction-to-ambient thermal resistance, natural

R

JA

θ

22 20 °C/W 1, 2

convection

Junction-to-ambient thermal resistance, natural

R

JMA

θ

14 14 °C/W 1, 3

convection, four-layer (2s2p) board

Junction-to-ambient thermal resistance, 200 ft/min

R

JMA

θ

16 15 °C/W 1, 3

airflow, single-layer (1s) board

Junction-to-ambient thermal resistance, 200 ft/min

R

JMA

θ

11 11 °C/W 1, 3

airflow, four-layer (2s2p) board

Junction-to-board thermal resistance R

Junction-to-case thermal resistance R

JB

θ

JC

θ

66°C/W4

<0.1 <0.1 °C/W 5

Notes:

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of R

for the part is less

θJC

than 0.1°C/W.

6. Refer to Section 9.8, “Thermal Management Information,” for more details about thermal management.

Table 6 provides the DC electrical characteristics for the MPC7455.

Table 6. DC Electrical Specifications

At recommended oper ating conditions. See Ta bl e 4 .

Nominal

Characteristic

Input high voltage
(all inputs except SYSCLK)

Input low voltage
(all inputs except SYSCLK)

SYSCLK input high voltage — CV

SYSCLK input low voltage — CV

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 13

Bus

Voltage

1.5 V

1.8 V

2.5 V

1.5 V

1.8 V

2.5 V

Symbol Min Max Unit Notes

1

IH

IH

IH

IL

IL

IL

IH

IL

GVDD × 0.65 GVDD + 0.3 V 6

OVDD/GVDD × 0.65 OVDD/GVDD + 0.3 V

1.7 OVDD/GVDD + 0.3 V

–0.3 GVDD × 0.35 V 6

–0.3 OVDD/GVDD × 0.35 V

–0.3 0.7 V

1.4 OVDD + 0.3 V

–0.3 0.4 V

Electrical and Thermal Characteristics

Table 6. DC Electrical Specifications (continued)

At recommended oper ating conditions. See Ta bl e 4 .

Nominal

Characteristic

Voltage

Bus

Symbol Min Max Unit Notes

1

Input leakage current,
V

= GVDD/OVDD + 0.3 V

in

High impedance (off-state) leakage
current, V

Output high voltage, I

Output low voltage, I

Capacitance,
V

=

in

f = 1 MHz

= GVDD/OVDD + 0.3 V

in

L3 interface — C

0 V,

All other inputs — 8.0 pF 4

= –5 mA 1.5 V

OH

5 mA 1.5 V

=

OL

—I

—I

1.8 V

2.5 V

1.8 V

2.5 V

in

TSI

OH

OVDD/GVDD – 0.45 — V

OH

OH

OL

OL

OL

in

—30µA2, 3

— 30 µA 2, 3, 5

GVDD – 0.45 — V 6

1.7 — V

—0.45V6

—0.45V

—0.7V

—9.5pF4

Notes:

1. Nominal voltages; see Table 4 for recommended operating conditions.

2. For processor bus signals, the reference is OV

while GVDD is the reference for the L3 bus signals.

DD

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OV
direction (for example, both OV

and VDD vary by either +5% or –5%).

DD

/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same

DD

6. Applicable to L3 bus interface only.

Table 7 provides the power consumption for the MPC7455.

Table 7. Power Consumption for MPC7455

Processor (CPU) Frequency

Unit Notes

733 MHz 867 MHz 933 MHz 1 GHz

Full-Power Mode

Typical 11.5 12.9 13.6 15.0 W 1, 3

Maximum 17.0 19.0 20.0 22.0 W 1, 2

Doze Mode

Typical ————W4

Nap Mode

Typical 8.0 8.0 8.0 8.0 W 1, 3

Sleep Mode

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

14 Freescale Semiconductor

Electrical and Thermal Characteristics

Table 7. Power Consumption for MPC7455 (continued)

Processor (CPU) Frequency

Unit Notes

733 MHz 867 MHz 933 MHz 1 GHz

Typical 7.6 7.6 7.6 7.6 W 1, 3

Deep Sleep Mode (PLL Disabled)

Typical 7.3 7.3 7.3 7.3 W 1, 3

Notes:

1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD
and GV
power. Worst case power consumption for AV

2. Maximum power is measured at nominal V
sequence of instructions which keep the execution units, with or without AltiVec, maximally busy.

3. Typical power is an average value measured at the nominal recommended V
while running a typical code sequence.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode.
As a result, power consumption for this mode is not tested.

) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD

DD

< 3 mW.

DD

(see Table 4) while running an entirely cache-resident, contrived

DD

(see Table 4) and 65°C in a system

DD

5.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7455. After fabrication, functional parts are
sorted by maximum processor core frequ ency as shown in Section 5.2.1, “Clock AC Specifications,” and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core
frequency; see Se ction 11, “Ordering Informati on .”

5.2.1 Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3.

Table 8. Clock AC Timing Specifications

At recommended oper ating conditions. See Ta bl e 4 .

Maximum Processor Core Frequency

Characteristic Symbol

Processor frequency f

VCO frequency f

SYSCLK frequency f

SYSCLK cycle time t

SYSCLK rise and fall time t

SYSCLK duty cycle
measured at OV

DD

/2

t

core

VCO

SYSCLK

SYSCLK

, t

KR

KF

t

KHKL

SYSCLK

Min Max Min Max Min Max Min Max

500 733 500 867 500 933 500 1000 MHz 1

1000 1466 1000 1734 1000 1866 1000 2000 MHz 1

33 133 33 133 33 133 33 133 MHz 1

7.5 30 7.5 30 7.5 30 7.5 30 ns

—1.0—1.0—1.0—1.0 ns 2

/

40 60 40 60 40 60 40 60 % 3

Unit Notes733 MHz 867 MHz 933 MHz 1 GHz

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 15

Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications (continued)

At recommended oper ating conditions. See Ta bl e 4 .

Maximum Processor Core Frequency

Characteristic Symbol

Unit Notes733 MHz 867 MHz 933 MHz 1 GHz

Min Max Min Max Min Max Min Max

SYSCLK jitter — ± 150 — ± 150 — ± 150 — ± 150 ps 4, 6

Internal PLL relock time —100—100—100—100 µs5

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 9.1, “PLL Configuration,”
for valid PLL_CFG[0:4] settings.

2. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter—short term and long term combined—and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable V

and SYSCLK are reached during the power-on reset sequence. This

DD

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET

must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the

power-on reset sequence.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.

Figure 3 provides the SYSCLK input timing diagram.

SYSCLK

CV

IH

t

KR

t

KHKL

t

SYSCLK

VMVMVM

CV

IL

VM = Midpoint Voltage (OVDD/2)

Figure 3. SYSCLK Input Timing Diagram

t

KF

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

16 Freescale Semiconductor

Electrical and Thermal Characteristics

5.2.2 Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and Figure 5.

Timing spe cifications for the L3 bus are provided in Section 5.2.3, “L3 Clock AC Specifications.”

Table 9. Processor Bus AC Timing Specifications

At recommended oper ating conditions. See Ta bl e 4 .

Parameter Symbol

All Speed Grades

2

Min Max

1

Unit Notes

Input setup times:
A[0:35], AP[0:4], GBL

, TBST, TSIZ[0:2], TT[0:3], D[0:63],

DP[0:7]
AACK

, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK, TA,

TBEN, TEA
BMODE

, TS, EXT_QUAL, PMON_IN, SHD[0:1]

[0:1], BVSEL, L3VSEL

Input hold times:
A[0:35], AP[0:4], GBL

, TBST, TSIZ[0:2], TT[0:3], D[0:63],

DP[0:7]
AACK

, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK, TA,

TBEN, TEA
BMODE

, TS,EXT_QUAL, PMON_IN, SHD[0:1]

[0:1], BVSEL, L3VSEL

Output valid times:
A[0:35], AP[0:4], GBL

, TBST, TSIZ[0:2], TT[0:3], WT, CI
TS

D[0:63], DP[0:7]

/SHD0/SHD1

ARTRY
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ]

Output hold times:
A[0:35], AP[0:4], GBL

, TBST, TSIZ[0:2], TT[0:3], WT, CI
TS

D[0:63], DP[0:7]

/SHD0/SHD1

ARTRY
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ

t

AVKH

t

IVKH

t

MVKH

t

AXKH

t

IXKH

t

MXKH

t

KHAV

t

KHTSV

t

KHDV

t

KHARV

t

KHOV

t

KHAX

t

KHTSX

t

KHDX

t

KHARX

t

KHOX

2.0

2.0

2.0

0

0

0

—
—
—
—
—

0.5

0.5

0.5

0.5

0.5

—

—

—

—

—

—

2.5

2.5

2.5

2.5

2.5

—
—
—
—
—

ns

8

ns

8

ns

ns

SYSCLK to output enable t

SYSCLK to output high impedance (all except TS
SHD0

, SHD1)

SYSCLK to TS

Maximum delay to ARTRY

high impedance after precharge t

/SHD0/SHD1 precharge t

, ARTRY,

KHOE

t

KHOZ

KHTSPZ

KHARP

0.5 — ns

—3.5ns

—1t

—1t

SYSCLK

SYSCLK

3, 4, 5

3, 5,

6, 7

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 17

Electrical and Thermal Characteristics

Table 9. Processor Bus AC Timing Specifications 1 (continued)

At recommended oper ating conditions. See Ta bl e 4 .

Parameter Symbol

All Speed Grades

2

Min Max

Unit Notes

SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge

t

KHARPZ

—2t

SYSCLK

3, 5,

6, 7

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t

t

(reference)(state)(signal)(state)

for outputs. For example, t

symbolizes the time input signals (I) reach the valid state (V)

IVKH

(signal)(state)(reference)(state)

relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

KHOV

for inputs and

symbolizes the time from
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the
input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for
inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).

3. t

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of

sysclk

SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS
before returning to high impedance as shown in Figure 6. The nominal precharge width for TS
than the minimum t

SYSCLK

is driven only by the currently active bus master. It is asserted low then precharged high

is 0.5 × t

SYSCLK

, that is, less

period, to ensure that another master asserting TS on the following clock will not contend with the
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge. The
high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY
AACK

. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK
cycle after the assertion of AACK
impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY

can be driven by multiple bus masters through the clock period immediately following

will then go to high impedance for one clock before precharging it high during the second

. The nominal precharge width for ARTRY is 1.0 t

; that is, it should be high

SYSCLK

. Output valid and output

hold timing is tested for the signal asserted. The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0
is the same as ARTRY

, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle
(crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0
t

8. BMODE

. The edges of the precharge vary depending on the programmed ratio of core-to-bus (PLL configurations).

SYSCLK

[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These paramenters

and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing

and SHD1 is 1.0

represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These
inputs must remain stable after the second sample. See Figure 5 for sample timing.

Figure 4 provides the AC test load for the MPC7455.

Output

Z0 = 50 Ω

R

= 50 Ω

L

Figure 4. AC Test Load

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

18 Freescale Semiconductor

OVDD/2

Figure 5 provides the mode select input timing diagram for the MPC7455.

Electrical and Thermal Characteristics

SYSCLK

VM

HRESET

Mode Signals

Firs t Sample Second Sample

VM = Midpoint Voltage (OVDD/2)

Figure 5. Mode Input Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7455.

SYSCLK

All Inputs

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

All Outputs

(Except TS

ARTRY, SHD0, SHD1)

TS

VM

t

AVKH

t

IVKH

t

MVKH

t

KHAV

t

KHDV

t

KHOV

t

KHOE

,

t

KHTSV

VM

t

AXKH

t

IXKH

t

MXKH

t

KHAX

t

KHDX

t

KHOX

t

KHOZ

t

KHTSPZ

t

KHTSV

t

KHTSX

VM

VM

t

KHARPZ

t

KHARV

ARTRY,

SHD0,

t

KHARP

t

KHARX

SHD1

VM = Midpoint Voltage (OV

DD

/2)

Figure 6. Input/Output Timing Diagram

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor 19

Electrical and Thermal Characteristics

5.2.3 L3 Clock AC Specifications

The L3_CLK frequency is programmed by the L3 configuration register (L3CR[6:8]) core-to-L3 divisor ratio. See

Table 18 for example core and L3 frequencies at var ious divisor s. Table 10 provides the potential range of L3_CLK

output AC timing specifications as defined in Figure 7.
The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies available

in the MPC7455, however, most SRAM designs will be not be a ble to operate in this mode usi ng cur rent te chnology
and, as a result, will sel ect a gr eater c ore-to-L3 div isor to provi de a long er L3_CLK perio d for re ad and write a ccess
to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in Table 10 is considered to be the practical
maximum in a typical system. The maximum L3_CLK frequency for any application of the MPC7455 will be a
function of the AC timings of the MPC7455, the AC timings for the SRAM, bus loading, and printed-circuit board
trace length, and may be greater or less tha n the value given in Table 10.

Freescale is similarly limited by system constraints and cannot perform tests of the L3 interface on a socketed part
on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation and AC timing
information are test ed at core-to-L3 divisors which resul t in L3 frequencies at 200 MHz or less.

Table 10. L3_CLK Output AC Timing Specifications

At recommended oper ating conditions. See Ta bl e 4 .

All Speed Grades

Parameter Symbol

Min Typ Max

Unit Notes

L3 clock frequency f

L3 clock cycle time t

L3 clock duty cycle t

L3 clock output-to-output skew (L1_CLK0 to
L1_CLK1)

L3 clock output-to-output skew (L1_CLK[0:1]
to L1_ECHO_CLK[2:3])

L3 clock jitter — — ±50 ps 5

Notes:

1. The maximum L3 clock frequency will be system dependent. See Section 5.2.3, “L3 Clock AC Specifications,” for
an explanation that this maximum frequency is not functionally tested at speed by Freescale.

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control
signals which are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for
PB2 or late write SRAM. This parameter is critical to the write data signals which are separately latched onto each
SRAM part by these pairs of signals.

5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3
address/data/control signals equally and, therefore, is already comprehended in the AC timing and does not have
to be considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock
period caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in
any L3 timing analysis.

L3_CLK

L3_CLK

CHCL/tL3_CLK

t

L3CSKW1

t

L3CSKW2

75 250 — MHz 1

— 4.0 13.3 ns

50 % 2

— — 200 ps 3

— — 100 ps 4

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

20 Freescale Semiconductor