Freescale MPC7448 User Guide

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Freescale Semiconductor

Technical Data

MPC7448 RISC Microprocessor Hardware Specifications

This document is primarily concerned with the PowerPC™ MPC7448. The MPC7448 is an implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the MPC7448. For information regarding specific MPC7448 part numbers covered by this document and part numbers covered by other documents, refer to Section 11, “Part

Numbering and Marking.” For functional characteristics of

the processor, refer to the MPC7450 RISC Microprocessor Family Reference Manual.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3. Comparison with the MPC7447A, MPC7447,

4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

5. Electrical and Thermal Characteristics . . . . . . . . . . . . .9

6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7. Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . .29

9. System Design Information . . . . . . . . . . . . . . . . . . . . .35

10. Document Revision History. . . . . . . . . . . . . . . . . . . . .56

11. Part Numbering and Marking . . . . . . . . . . . . . . . . . . .57

MPC7448EC

Rev. 1, 11/2005

Contents

MPC7445, and MPC7441 . . . . . . . . . . . . . . . . . . . . . . .7

To locate any published updates for this document, refer to the website listed on the back cover of this document.

1 Overview

The MPC7448 is the sixth implementation of fourthgeneration (G4) microprocessors from Freescale. The MPC7448 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7448 consists of a processor core and a 1-Mbyte L2.

Figure 1 shows a block diagram of the MPC7448. The core

is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources.

Overview

128-Bit (4 Instructions)

Instruction MMU

Instruction Unit

I Cache

32-Kbyte

Stations (2)

D Cache

IBAT Array

32-Kbyte

Data MMU

Unit

Dispatch

Tags

ITLB

128-Entry

SRs

(Shadow)

(12-Word)

Instruction Queue

Fetcher

CTR

Reservation

FPR File

Vector Touch Engine

Reservation

(EA Calculation)

GPR File

Station

Stations (2)

VR File

16 Rename

L1 Castout

Finished

16 Rename

Load/Store Unit

Touch

Vec to r

Queue

+ x ÷

FPSCR

Unit 2

(3)

FPSCR

L1 Push

Completed

x ÷

64-Bit

Load Miss

Stores

32-Bit

Push

Queue (6)

Castout

Queue (5) /

Bus Store Queue

System Bus Interface

Load

Queue (11)

Snoop Push/

Interventions

Block 1 (32-Byte)

Status

L2 Store Queue (L2SQ)

(4)

L1 Castouts

Block 0 (32-Byte)

Status

128-Bit

1-Mbyte Unified L2 Cache Controller

Line

Ta gs

Bus Accumulator

64-Bit

36-Bit

Data Bus

Address Bus

Floating-

Point Unit

Buffers

Stores

Buffers

Integer

Unit 2

Integer

Unit 2 Unit 1

Integer

Buffers

Additional Features

Branch Processing Unit

BTIC (128-Entry)

BHT (2048-Entry)

• Time Base Counter/Decrementer

• Clock Multiplier

• JTAG/COP Interface

• Thermal/Power Management

• Performance Monitor

• Out-of-Order Issue of AltiVec Instr.

VR Issue FPR Issue

96-Bit (3 Instructions)

(16-Entry)

Completion Unit

Completion Queue

Station

Reservation

Station

Completes up

to three

per clock

instructions

Reservation

Station

Reservation

Station

Reservation

Vect or

Vector

Integer

Permute

FPU

Unit 1

Unit 2

Unit

128-Bit

Queues

L1 Service

L1 Store Queue

(LSQ)

Memory Subsystem

L1 Load Miss (5)

L2 Prefetch (3)

Instruction Fetch (2)

Cacheable Store Miss (2)

The Castout Queue itself is limited to 5 entries, ensuring 1 entr y will be available for a push.

The Castout Queue and Push Queue share resources such for a combined total of 6 entries.

L1 Load Queue (LLQ)

Notes:

Figure 1. MPC7448 Block Diagram

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

2 Freescale Semiconductor

2Features

This section summarizes features of the MPC7448 implementation of the PowerPC architecture. Major features of the MPC7448 are as follows:

• High-performance, superscalar microprocessor — Up to four instructions can be fetched from the instruction cache at a time. — Up to three instructions plus a branch instruction can be dispatched to the issue queues at a

time. — Up to 12 instructions can be in the instruction queue (IQ). — Up to 16 instructions can be at some stage of execution simultaneously. — Single-cycle execution for most instructions — One instruction per clock cycle throughput for most instructions — Seven-stage pipeline control

• Eleven independent execution units and three register files — Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. T ypically, a fetch that hits the BTIC provides the first four instructions in the target stream.

– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of

prediction—not taken, strongly not taken, taken, and strongly taken – Up to three outstanding speculative branches – Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream. – Eight-entry link register stack to predict the target address of Branch Conditional to Link

Features

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions. – IU2 executes miscellaneous instructions, including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions.

— Five-stage FPU and 32-entry FPR file

– Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Hardware support for denormalized numbers – Thirty-two 64-bit FPRs for single- or double-precision operands

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

Freescale Semiconductor 3

Features

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU) – Vecto r integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add

instructions (for example, vaddsbs, vaddshs, and vaddsws). – Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector

multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm). – Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic – Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations – Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle

throughput – Four-cycle FPR load latency (single, double) with one-cycle throughput – No additional delay for misaligned access within double-word boundary – A dedicated adder calculates effective addresses (EAs). – Supports store gathering – Performs alignment, normalization, and precision conversion for floating-point data – Executes cache control and TLB instructions – Performs alignment, zero padding, and sign extension for integer data – Supports hits under misses (multiple outstanding misses) – Supports both big- and little-endian modes, including misaligned little-endian accesses

• Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2. — A maximum of three instructions can be dispatched to the issue queues per clock cycle. — Space must be available in the CQ for an instruction to dispatch (this includes instructions that

are assigned a space in the CQ but not in an issue queue).

• Rename buffers — 16 GPR rename buffers — 16 FPR rename buffers — 16 VR rename buffers

• Dispatch unit — Decode/dispatch stage fully decodes each instruction

• Completion unit — Retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of

it have been completed, the instruction has finished executing, and no exceptions are pending — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

4 Freescale Semiconductor

— Tracks unresolved branches and flushes instructions after a mispredicted branch — Retires as many as three instructions per clock cycle

• Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set-associative instruction and data caches — Pseudo least-recently-used (PLRU) replacement algorithm — 32-byte (eight-word) L1 cache block — Physically indexed/physical tags — Cache write-back or write-through operation programmable on a per-page or per-block basis — Instruction cache can provide four instructions per clock cycle; data cache can provide four

words per clock cycle — Caches can be disabled in software. — Caches can be locked in software. — MESI data cache coherency maintained in hardware — Separate copy of data cache tags for efficient snooping — Parity support on cache — No snooping of instruction cache except for icbi instruction

Features

— Data cache supports AltiVec LRU and transient instructions — Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word

forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical

double-word forwarding.

• Level 2 (L2) cache interface — On-chip, 1-Mbyte, eight-way set-associative unified instruction and data cache — Cache write-back or write-through operation programmable on a per-page or per-block basis — Parity support on cache tags — ECC or parity support on data — Error injection allows testing of error recovery software

• Separate memory management units (MMUs) for instructions and data — 52-bit virtual address, 32- or 36-bit physical address — Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and

memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBATs (eight each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs)

– Both TLBs are 128-entry, two-way set-associative and use an LRU replacement algorithm.

– TLBs are hardware- or software-reloadable (that is, a page table search is performed in

hardware or by system software on a TLB miss).

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

Freescale Semiconductor 5

Features

• Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits. — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs. — The L2 cache is fully pipelined to provide 32 bytes per clock every other cycle to the L1 caches. — As many as 16 out-of-order transactions can be present on the MPX bus. — Store merging for multiple store misses to the same line. Only coherency action taken

(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).

— Three-entry finished store queue and five-entry completed store queue between the LSU and

the L1 data cache

— Separate additional queues for efficient buffering of outbound data (such as castouts and

write-through stores) from the L1 data cache and L2 cache

• Multiprocessing support features include the following: — Hardware-enforced, MESI cache coherency protocols for data cache — Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

• Power and thermal management — Dynamic frequency switching (DFS) feature allows processor core frequency to be halved or

quartered through software to reduce power consumption.

— The following three power-saving modes are available to the system:

– Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and

JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol.

– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the

PLL in a locked and running state. All internal functional units are disabled.

– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system

can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed upon exiting the deep

sleep state. — Instruction cache throttling provides control of instruction fetching to limit device temperature. — A new temperature diode that can determine the temperature of the microprocessor — Support for core voltage derating to further reduce power consumption

• Performance monitor can be used to help debug system designs and improve software efficiency.

• In-system testability and debugging features through JTAG boundary-scan capability

• Testability — LSSD scan design — IEEE 1149.1 JTAG interface

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

6 Freescale Semiconductor

Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441

• Reliability and serviceability — Parity checking on system bus — Parity checking on the L1 caches and L2 data tags — ECC or parity checking on L2 data

3 Comparison with the MPC7447A, MPC7447, MPC7445,

and MPC7441

Table 1 compares the key features of the MPC7448 with the key features of the earlier MPC7447A,

MPC7447, MPC7445, and MPC7441. All are based on the MPC7450 RISC microprocessor and are architecturally very similar. The MPC7448 is identical to the MPC7447A, but the MPC7448 supports 1 Mbyte of L2 cache with ECC and the use of dynamic frequency switching (DFS) with more bus-to-core ratios.

Table 1. Microarchitecture Comparison

Microarchitectural Specs MPC7448 MPC7447A MPC7447 MPC7445 MPC7441

Basic Pipeline Functions

Logic inversions per cycle 18

Pipeline stages up to execute 5

Total pipeline stages (minimum) 7

Pipeline maximum instruction throughput 3 + branch

Pipeline Resources

Instruction buffer size 12

Completion buffer size 16

Renames (integer, float, vector) 16, 16, 16

Maximum Execution Throughput

SFX 3

Vector 2 (any 2 of 4 units)

Scalar floating-point 1

Out-of-Order Window Size in Execution Queues

SFX integer units 1 entry × 3 queues

Vector units In order, 4 queues

Scalar floating-point unit In order

Branch Processing Resources

Prediction structures BTIC, BHT, link stack

BTIC size, associativity 128-entry, 4-way

BHT size 2K-entry

Link stack depth 8

Unresolved branches supported 3

Branch taken penalty (BTIC hit) 1

Minimum misprediction penalty 6

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

Freescale Semiconductor 7

Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441

Table 1. Microarchitecture Comparison (continued)

Microarchitectural Specs MPC7448 MPC7447A MPC7447 MPC7445 MPC7441

Execution Unit Timings (Latency-Throughput)

Aligned load (integer, float, vector) 3-1, 4-1, 3-1

Misaligned load (integer, float, vector) 4-2, 5-2, 4-2

L1 miss, L2 hit latency with ECC (data/instruction) 12/16 —

L1 miss, L2 hit latency without ECC (data/instruction) 11/15 9/13

SFX (add, sub, shift, rot, cmp, logicals) 1-1

Integer multiply (32 × 8, 32 × 16, 32 × 32) 4-1, 4-1, 5-2

Scalar float 5-1

VSFX (vector simple) 1-1

VCFX (vector complex) 4-1

VFPU (vector float) 4-1

VPER (vector permute) 2-1

MMUs

TLBs (instruction and data) 128-entry, 2-way

Tablewalk mechanism Hardware + software

Instruction BATs/data BATs 8/8 8/8 8/8 8/8 4/4

L1 I Cache/D Cache Features

Size 32K/32K

Associativity 8-way

Locking granularity Way

Parity on I cache Word

Parity on D cache Byte

Number of D cache misses (load/store) 5/2 5/1

Data stream touch engines 4 streams

On-Chip Cache Features

Cache level L2

Size/associativity 1-Mbyte/

512-Kbyte/8-way 256-Kbyte/8-way

8-way

Access width 256 bits

Number of 32-byte sectors/line 2 2

Parity tag Byte Byte

Parity data Byte Byte

Data ECC 64-bit —

Thermal Control

Dynamic frequency switching divide-by-two mode Yes Yes No No No

Dynamic frequency switching divide-by-four mode Yes No No No No

Thermal diode Yes Yes No No No

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

8 Freescale Semiconductor

General Parameters

4 General Parameters

The following list summarizes the general parameters of the MPC7448:

Technology 90 nm CMOS SOI, nine-layer metal

Die size 8.0 mm × 7.3 mm Transistor count 90 million

Logic design Mixed static and dynamic Packages Surface mount 360 ceramic ball grid array (HCTE)

Surface mount 360 ceramic land grid array (HCTE) Surface mount 360 ceramic ball grid array with lead-free spheres (HCTE)

Core power supply 1.30 V (1700 MHz device)

1.25 V (1600 MHz device)

1.20 V (1420 MHz device)

1.15 V (1000 MHz device)

I/O power supply 1.5 V, 1.8 V, or 2.5 V

5 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7448.

5.1 DC Electrical Characteristics

The tables in this section describe the MPC7448 DC electrical characteristics. Table 2 provides the absolute maximum ratings. See Section 9.2, “Power Supply Design and Sequencing” for power sequencing requirements.

Table 2. Absolute Maximum Ratings

Characteristic Symbol Maximum Value Unit Notes

Core supply voltage V

PLL supply voltage AV

Processor bus supply voltage I/O Voltage Mode = 1.5 V OV

I/O Voltage Mode = 1.8 V –0.3 to 2.2 3

I/O Voltage Mode = 2.5 V –0.3 to 3.0 3

Input voltage Processor bus V

JTAG signals V

Storage temperature range T

Notes:

1. Functional and tested operating conditions are given in Ta b le 4 . Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.

2. See Section 9.2, “Power Supply Design and Sequencing” for power sequencing requirements.

3. Bus must be configured in the corresponding I/O voltage mode; see Ta b le 3 .

4. Caution: Vin must not exceed OV the overshoot specifications. V

by more than 0.3 V at any time including during power-on reset except as allowed by

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

stg

–0.3 to 1.4 V 2

–0.3 to 1.8 V 3

–0.3 to OVDD + 0.3 V 4

–0.3 to OVDD + 0.3 V

– 55 to 150 °C

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

Freescale Semiconductor 9

Electrical and Thermal Characteristics

Figure 2 shows the undershoot and overshoot voltage on the MPC7448.

OVDD + 20%

OVDD + 5%

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

of t

SYSCLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7448 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7448 core voltage must always be provided at the nominal voltage (see Table 4) or at the supported derated voltage (see Section 5.3, “Voltage and Frequency Derating”). The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET . The output voltage will swing from GND to the maximum voltage applied to the OVDD power pins. Table 3 provides the input threshold voltage settings. Because these settings may change in future products, it is recommended that BVSEL[0:1] be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future, if necessary.

Table 3. Input Threshold Voltage Setting

BVSEL0 BVSEL1 I/O Voltage Mode

0 0 1.8 V 2, 3

0 1 2.5 V 2, 4

1 0 1.5 V 2

1 1 2.5 V 4

Notes:

1. Caution: The I/O voltage mode selected must agree with the OV supplied. See Ta bl e 4 .

2. If used, pull-down resistors should be less than 250 Ω.

3. The pin configuration used to select 1.8V mode on the MPC7448 is not compatible with the pin configuration used to select 1.8V mode on the MPC7447A and earlier devices.

4. The pin configuration used to select 2.5V mode on the MPC7448 is fully compatible with the pin configuration used to select 2.5V mode on the MPC7447A and earlier devices.

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

10 Freescale Semiconductor

Notes

voltages

Electrical and Thermal Characteristics

Table 4 provides the recommended operating conditions for the MPC7448 part numbers described by this

document; see Section 11.1, “Part Numbers Fully Addressed by This Document,” for more information. See Section 9.2, “Power Supply Design and Sequencing” for power sequencing requirements.

NOTE

Table 4 describes the nominal operating conditions of the device. For

information on the operation of the device at supported derated core voltage conditions, see Section 5.3, “Voltage and Frequency Derating.”

Table 4. Recommended Operating Conditions

Characteristic Symbol

Recommended Value

1000 MHz 1420 MHz 1600 MHz 1700 MHz

Min Max Min Max Min Max Min Max

Unit Notes

Core supply voltage V

1.15 V ± 50 mV 1.2 V ± 50 mV 1.25 V ± 50 mV 1.3 V +20/

V 3, 4, 5

–50mV

PLL supply voltage AV

1.15 V ± 50 mV 1.2 V ± 50 mV 1.25 V ± 50 mV 1.3 V +20/

V 2, 3, 4

–50mV

Processor bus supply voltage

Input voltage

I/O Voltage Mode = 1.5 V OV

I/O Voltage Mode = 1.8 V 1.8 V ± 5% 1.8 V ± 5% 1.8 V ± 5% 1.8 V ± 5% 4

I/O Voltage Mode = 2.5 V 2.5 V ± 5% 2.5 V ± 5% 2.5 V ± 5% 2.5 V ± 5% 4

Processor bus V

JTAG signals V

Die-junction temperature T

1.5 V ± 5% 1.5 V ± 5% 1.5 V ± 5% 1.5 V ± 5% V 4

GND OV

0 105 0 105 0 105 0 105 °C

Notes:

1. These are the recommended and tested operating conditions. Some speed grades in addition support voltage derating; see

Section 5.3, “Voltage and Frequency Derating.” Proper device operation outside of these conditions and those specified in Section 5.3 is not guaranteed.

2. This voltage is the input to the filter discussed in Section 9.2.2, “PLL Power Supply Filtering,” and not necessarily the voltage at the AV

3. V

pin, which may be reduced from VDD by the filter.

and AVDD may be reduced for some speed grades in order to reduce power consumption if further maximum core

frequency constraints are observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information.

4. Caution: Power sequencing requirements must be met; see Section 9.2, “Power Supply Design and Sequencing”.

5. Caution: See Section 9.2.3, “Transient Specifications” for information regarding transients on this power supply.

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

Freescale Semiconductor 11

Electrical and Thermal Characteristics

Table 5 provides the package thermal characteristics for the MPC7448. For more information regarding

thermal management, see Section 9.7, “Thermal Management Information.”

Table 5. Package Thermal Characteristics

Characteristic Symbol Value Unit Notes

Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board R

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board R

Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board R

Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board R

Junction-to-board thermal resistance R

Junction-to-case thermal resistance R

JMA

26 °C/W 2, 3

19 °C/W 2, 4

22 °C/W 2, 4

16 °C/W 2, 4

11 °C/W 5

< 0.1 °C/W 6

Notes:

1. Refer to Section 9.7, “Thermal Management Information,” for details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

3. Per JEDEC JESD51-2 with the single-layer board horizontal

4. Per JEDEC JESD51-6 with the board horizontal

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

6. This is the thermal resistance between die and case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of R

for the part is less than 0.1°C/W.

θJC

Table 6 provides the DC electrical characteristics for the MPC7448.

Table 6. DC Electrical Specifications

At recommended operating conditions. See Ta bl e 4 .

Characteristic

Input high voltage (all inputs)

Nominal Bus

Volt ag e

1.5 V

Symbol Min Max Unit Notes

OVDD × 0.65 OVDD + 0.3 V 2

1.8 OVDD × 0.65 OVDD + 0.3

2.5 1.7 OVDD + 0.3

Input low voltage (all inputs)

1.5 V

–0.3 OVDD × 0.35 V 2

1.8 –0.3 OVDD × 0.35

2.5 –0.3 0.7

Input leakage current, V

= GVDD/OVDD

= GND

High-impedance (off-state) leakage current,

= GVDD/OVDD

= GND

—I

TSI

—

µA 2, 3

– 50

µA 2, 3, 4

– 50

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

12 Freescale Semiconductor

Table 6. DC Electrical Specifications (continued)

At recommended operating conditions. See Ta bl e 4 .

Electrical and Thermal Characteristics

Characteristic

Output high voltage @ IOH = –5 mA 1.5 V

Output low voltage @ I

Capacitance,

0 V, f = 1 MHz

Notes:

1. Nominal voltages; see Ta b le 4 for recommended operating conditions.

2. All I/O signals are referenced to OV

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals

4. The leakage is measured for nominal OV example, both OVDD and VDD vary by either +5% or –5%).

5. Capacitance is periodically sampled rather than 100% tested.

5 mA 1.5 V

All inputs C

Nominal Bus

Volt ag e

1.8 OVDD – 0.45 —

2.5 1.8 —

1.8 — 0.45

2.5 — 0.6

and VDD, or both OVDD and VDD must vary in the same direction (for

Symbol Min Max Unit Notes

OVDD – 0.45 — V

—0.45V

—8.0pF5

Table 7 provides the power consumption for the MPC7448 part numbers described by this document; see Section 11.1, “Part Numbers Fully Addressed by This Document,” for more information. The MPC7448

RISC Microprocessor Hardware Specifications presents guidelines on the use of these parameters for system design. For information on power consumption when dynamic frequency switching is enabled, see

Section 9.7.5, “Dynamic Frequency Switching (DFS).” Several power specifications are provided for

Full-Power mode. The Nominal – T ypical value represents the sustained power consumption of the device when running a typical benchmark at temperatures in a typical system. The Nominal – Thermal value is intended to represent the sustained power consumption of the device when running a typical code sequence at high temperature and is recommended to be used as the basis for designing a thermal solution; see

Section 9.7, “Thermal Management Information” for more information on thermal solutions. The

Maximum value is recommended to be used for power supply design because this represents the maximum peak power draw of the device that a power supply must be capable of sourcing without voltage droop.

NOTE

The power consumption information in this table applies when the device operates at the nominal core voltage indicated in Table 4. For power consumption at derated core voltage conditions, see Section 5.3, “Voltage

and Frequency Derating.”

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Electrical and Thermal Characteristics

Table 7. Power Consumption for MPC7448

Die Junction Temperature

(Tj)

Typical – Nominal 65 °C 15.0 19.0 20.0 21.0 W 1, 2

Typical – Thermal 105 °C 18.6 23.3 24.4 25.6 W 1, 5

Maximum 105 °C 21.6 27.1 28.4 29.8 W 1, 3

Typical 105 °C 11.1 11.8 13.0 13.0 W 1, 6

Typical 105 °C 10.8 11.4 12.5 12.5 W 1, 6

Typical 105 °C 10.4 11.0 12.0 12.0 W 1, 6

Notes:

1. These values specify the power consumption for the core power supply (V processor bus frequencies and configurations. The values do not include I/O supply power (OVDD) or PLL supply power

). OVDD power is system dependent but is typically < 5% of VDD power. Worst case power consumption for

(AV

AVDD<13mW.

2. Typical nominal power consumption is an average value measured at the nominal recommended V while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. This parameter is not 100% tested but periodically sampled.

3. Maximum power consumption is the average measured at nominal V

Ta bl e 4 ) while running an entirely cache-resident, contrived sequence of instructions to keep all the execution units maximally

busy.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a result, power consumption for this mode is not tested.

5. Typical thermal power consumption is an average value measured at the nominal recommended V 105 °C while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. This parameter is not 100% tested but periodically sampled.

6. Typical power consumption for these modes is measured at the nominal recommended V mode described. This parameter is not 100% tested but is periodically sampled.

1000 MHz 1420 MHz 1600 MHz 1700 MHz

Deep Sleep Mode (PLL Disabled)

Processor (CPU) Frequency

Full-Power Mode

Nap Mode

Sleep Mode

and maximum operating junction temperature (see

Unit Notes

) at nominal voltage and apply to all valid

(see Ta bl e 4 ) and 65°C

(see Ta b le 4 ) and

(see Ta bl e 4 ) and 105 °C in the

5.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7448. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Section 5.2.1, “Clock AC Specifications,” and tested for conformance to the AC specifications for that frequency. The processor core frequency, determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:5] signals, can be dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum processor core frequency; see Section 11, “Part Numbering and Marking,” for information on ordering parts. DFS is described in Section 9.7.5, “Dynamic Frequency Switching (DFS).”

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Electrical and Thermal Characteristics

5.2.1 Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3 and represents the tested

operating frequencies of the devices. The maximum system bus frequency, f

SYSCLK

considered a practical maximum in a typical single-processor system. This does not exclude multi-processor systems, but these typically require considerably more design effort to achieve the maximum rated bus frequency. The actual maximum SYSCLK frequency for any application of the MPC7448 will be a function of the AC timings of the microprocessor(s), the AC timings for the system controller, bus loading, printed-circuit board topology , trace lengths, and so forth, and may be less than the value given in Table 8.

NOTE

The core frequency information in this table applies when the device operates at the nominal core voltage indicated in

Table 4. For core frequency specifications at derated core voltage conditions, see Section 5.3, “Voltage

and Frequency Derating.”

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Ta bl e 4 .

Maximum Processor Core Frequency

, given in Table 8, is

Characteristic Symbol

Min Max Min Max Min Max Min Max

Processor core frequency

VCO frequency f

SYSCLK frequency f

SYSCLK cycle time t

SYSCLK rise and fall time tKR, t

SYSCLK duty cycle measured at OV

SYSCLK cycle-to-cycle jitter — 150 — 150 — 150 — 150 ps 5, 6

DFS mode disabled f

DFS mode enabled f

core

core_DF

VCO

SYSCLK

KHKL

SYSCLK

600 1000 600 1420 600 1600 600 1700 MHz 1, 8, 9

300 500 300 710 300 800 300 850 10

600 1000 600 1420 600 800 600 1700 MHz 1, 9, 11

33 200 33 200 33 200 33 200 MHz 1, 2, 8

5.0305.0305.0305.030ns 2

—0.5—0.5—0.5—0.5ns 3

40 60 40 60 40 60 40 60 % 4

Unit Notes1000 MHz 1420 MHz 1600 MHz 1700 MHz

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Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications (continued)

At recommended operating conditions. See Ta bl e 4 .

Maximum Processor Core Frequency

Characteristic Symbol

Unit Notes1000 MHz 1420 MHz 1600 MHz 1700 MHz

Min Max Min Max Min Max Min Max

Internal PLL relock time — 100 — 100 — 100 — 100 µs7

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus) frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:5] signal description in Section 9.1.1, “PLL Configuration,” for valid PLL_CFG[0:5] settings.

2. Actual maximum system bus frequency is system-dependent. See Section 5.2.1, “Clock AC Specifications.”

3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V

4. Timing is guaranteed by design and characterization.

5. Guaranteed by design

6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.

7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable V

and SYSCLK are reached during the power-on reset sequence. This specification also applies when

the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled. f

core_DFS

provides the maximum and minimum core frequencies when operating in a DFS mode.

9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at the nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be reduced. See Section 5.3, “Voltage and Frequency Derating,” for more information.

10.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS modes (divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and minimum frequencies stated for f

core

11.Use of the DFS feature does not affect VCO frequency.

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Electrical and Thermal Characteristics

Figure 3 provides the SYSCLK input timing diagram.

SYSCLK

KHKL

VM = Midpoint Voltage (OVDD/2)

Figure 3. SYSCLK Input Timing Diagram

5.2.2 Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7448 as defined in Figure 4 and Figure 5.

Table 9. Processor Bus AC Timing Specifications

At recommended operating conditions. See Ta bl e 4 .

Parameter Symbol

All Speed Grades

Min Max

Unit Notes

Input setup times:

A[0:35], AP[0:4] D[0:63], DP[0:7]

, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3],

AACK

, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,

QACK SHD[0:1]

BMODE[0:1], BVSEL[0:1]

Input hold times:

A[0:35], AP[0:4] D[0:63], DP[0:7]

, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3],

AACK

, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,

QACK SHD[0:1]

BMODE[0:1], BVSEL[0:1]

Output valid times:

A[0:35], AP[0:4] D[0:63], DP[0:7]

, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,

AACK

PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT TS ARTRY, SHD[0:1]

Output hold times:

A[0:35], AP[0:4] D[0:63], DP[0:7]

, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,

AACK

PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT TS ARTRY, SHD[0:1]

SYSCLK to output enable t

AVKH

DVKH

IVKH

MVKH

AXKH

DXKH

IXKH

MXKH

KHAV

KHDV

KHOV

KHTSV

KHARV

KHAX

KHDX

KHOX

KHTSX

KHARX

KHOE

1.5

— — —

—

ns 0 0 0

— — —

—

— — —

— —

1.8

0.5

— — —

— —

0.5 — ns 5

— — —

— — — —

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 1

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Electrical and Thermal Characteristics

Table 9. Processor Bus AC Timing Specifications1 (continued)

At recommended operating conditions. See Ta bl e 4 .

Parameter Symbol

All Speed Grades

Min Max

Unit Notes

SYSCLK to output high impedance (all except TS, ARTRY, SHD0,

)

SHD1

SYSCLK to TS

high impedance after precharge t

Maximum delay to ARTRY/SHD0/SHD1 precharge t

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

KHOZ

KHTSPZ

KHARP

KHARPZ

—1.8ns5

—1t

—2t

SYSCLK

3, 4, 5

3, 5, 6, 7

precharge

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t t

(reference)(state)(signal)(state)

for outputs. For example, t

symbolizes the time input signals (I) reach the valid state (V) relative

IVKH

to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

(signal)(state)(reference)(state)

symbolizes the time from SYSCLK(K)

KHOV

for inputs and

going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).

3. t

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of

sysclk

SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS before returning to high impedance, as shown in Figure 6. The nominal precharge width for TS is t

is driven only by the currently active bus master. It is asserted low and precharged high

, that is, one clock

SYSCLK

period. Since no master can assert TS on the following clock edge, there is no concern regarding contention with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested

6. According to the bus protocol, ARTRY

. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low

AACK

can be driven by multiple bus masters through the clock period immediately following

in the first clock following AACK will then go to high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for ARTRY is 1.0 t that is, it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY

SYSCLK

; .

Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0

and SHD1 can be driven by multiple bus masters beginning two cycles after TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is

1.0 t

8. BMODE BVSEL[0:1] are sampled before HRESET

. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).

SYSCLK

[0:1] and BVSEL[0:1] are mode select inputs. BMODE[0:1] are sampled before and after HRESET negation.

negation. These parameters represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. BMODE[0:1] must remain stable after the second sample; BVSEL[0:1] must remain stable after the first (and only) sample. See Figure 5 for sample timing.

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