Freescale MPC7445, MPC7448, MPC7457, MPC7451, MPC7455 User Manual

MPC7450 RISC Microprocessor

Family Reference Manual

Supports

MPC7448

MPC7447A

MPC7457
MPC7447
MPC7455
MPC7445
MPC7451
MPC7441
MPC7450

MPC7450UM

Rev. 5

1/2005

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© Freescale Semiconductor, Inc. 2005. All rights reserved.

MPC7450UM
Rev. 5
1/2005

Overview 1

Programming Model 2

L1, L2, and L3 Cache Operation 3

Exceptions 4

Memory Management 5

Instruction Timing 6

AltiVec Technology Implementation 7

Signal Descriptions 8

System Interface Operation 9

Power and Thermal Management 10

Performance Monitor 11

MPC7450 Instruction Set Listings A

Instructions Not Implemented B

Special-Purpose Registers C

Revision History D

Glossary GLO

Index IND

1 Overview

2 Programming Model

3 L1, L2, and L3 Cache Operation

4 Exceptions

5 Memory Management

6 Instruction Timing

7 AltiVec Technology Implementation

8 Signal Descriptions

9 System Interface Operation

10 Power and Thermal Management

11 Performance Monitor

A MPC7450 Instruction Set Listings

B Instructions Not Implemented

C Special-Purpose Registers

D Revision History

GLO Glossary

IND Index

Contents

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Number Title

Page

Number

About This Book

Audience......................................................................................................................... xlix

Organization.................................................................................................................... xlix

Suggested Reading........................................................................................................... l

General Information......................................................................................................... l

Related Documentation........................................................................................................ l

Conventions........................................................................................................................ li

Acronyms and Abbreviations ............................................................................................lii

Terminology Conventions................................................................................................. lvi

Chapter 1

Overview

1.1 MPC7450 Microprocessor Overview..............................................................................1-1

1.1.1 MPC7451 Microprocessor Overview..........................................................................1-6

1.1.2 MPC7441 Microprocessor Overview..........................................................................1-6

1.1.3 MPC7455 Microprocessor Overview..........................................................................1-6

1.1.4 MPC7445 Microprocessor Overview..........................................................................1-6

1.1.5 MPC7457 Microprocessor Overview..........................................................................1-6

1.1.6 MPC7447 Microprocessor Overview..........................................................................1-7

1.1.7 MPC7447A Microprocessor Overview ....................................................................... 1-7

1.1.8 MPC7448 Microprocessor Overview..........................................................................1-7

1.2 MPC7450 Microprocessor Features ................................................................................1-8

1.2.1 Overview of the MPC7450 Microprocessor Features ................................................. 1-8

1.2.2 Instruction Flow......................................................................................................... 1-13

1.2.2.1 Instruction Queue and Dispatch Unit .................................................................... 1-14

1.2.2.2 Branch Processing Unit (BPU).............................................................................. 1-14

1.2.2.3 Completion Unit .................................................................................................... 1-15

1.2.2.4 Independent Execution Units................................................................................. 1-15

1.2.2.4.1 AltiVec Vector Permute Unit (VPU) ................................................................. 1-15

1.2.2.4.2 AltiVec Vector Integer Unit 1 (VIU1) ............................................................... 1-15

1.2.2.4.3 AltiVec Vector Integer Unit 2 (VIU2) ............................................................... 1-16

1.2.2.4.4 AltiVec Vector Floating-Point Unit (VFPU) ..................................................... 1-16

1.2.2.4.5 Integer Units (IUs)............................................................................................. 1-16

1.2.2.4.6 Floating-Point Unit (FPU)................................................................................. 1-16

1.2.2.4.7 Load/Store Unit (LSU)......................................................................................1-17

1.2.3 Memory Management Units (MMUs)....................................................................... 1-17

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1.2.4 On-Chip L1 Instruction and Data Caches.................................................................. 1-18

1.2.5 L2 Cache Implementation.......................................................................................... 1-20

1.2.6 L3 Cache Implementation.......................................................................................... 1-22

1.2.7 System Interface ........................................................................................................ 1-23

1.2.8 MPC7450 Bus Operation Features............................................................................1-24

1.2.8.1 MPX Bus Features................................................................................................. 1-24

1.2.8.2 60x Bus Features.................................................................................................... 1-24

1.2.9 Overview of System Interface Accesses....................................................................1-25

1.2.9.1 System Interface Operation ................................................................................... 1-25

1.2.9.2 Signal Groupings................................................................................................... 1-26

1.2.9.3 MPX Bus Mode Functional Groupings.................................................................1-27

1.2.9.3.1 Clocking............................................................................................................. 1-32

1.2.10 Power and Thermal Management..............................................................................1-32

1.2.11 Performance Monitor................................................................................................. 1-33

1.3 MPC7450 Microprocessor: Architectural Implementation ........................................... 1-33

1.3.1 PowerPC Registers and Programming Model...........................................................1-34

1.3.2 Instruction Set............................................................................................................1-39

1.3.2.1 PowerPC Instruction Set........................................................................................1-39

1.3.2.2 AltiVec Instruction Set........................................................................................... 1-40

1.3.2.3 MPC7450 Microprocessor Instruction Set ............................................................ 1-41

1.3.3 On-Chip Cache Implementation................................................................................1-42

1.3.3.1 PowerPC Cache Model..........................................................................................1-42

1.3.3.2 MPC7450 Microprocessor Cache Implementation ............................................... 1-42

1.3.4 Exception Model........................................................................................................1-42

1.3.4.1 PowerPC Exception Model....................................................................................1-42

1.3.4.2 MPC7450 Microprocessor Exceptions.................................................................. 1-43

1.3.5 Memory Management................................................................................................1-46

1.3.5.1 PowerPC Memory Management Model................................................................1-46

1.3.5.2 MPC7450 Microprocessor Memory Management Implementation...................... 1-47

1.3.6 Instruction Timing ..................................................................................................... 1-47

1.3.7 AltiVec Implementation............................................................................................. 1-52

1.4 Differences Between MPC7450 and MPC7400/MPC7410........................................... 1-52

1.5 Differences Between MPC7441/MPC7451 and MPC7445/MPC7455......................... 1-55

1.6 Differences Between MPC7441/MPC7451 and MPC7447/MPC7457......................... 1-56

1.7 Differences Between MPC7447 and MPC7447A ......................................................... 1-57

1.8 Differences Between MPC7447A and MPC7448 ......................................................... 1-59

1.9 Revision History............................................................................................................ 1-61

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Chapter 2

Programming Model

2.1 AltiVec Technology and the Programming Model .......................................................... 2-1

2.2 MPC7450 Processor Register Set....................................................................................2-1

2.2.1 Register Set Overview................................................................................................. 2-1

2.2.2 MPC7450 Register Set.................................................................................................2-5

2.2.3 PowerPC Supervisor-Level Registers (OEA)............................................................2-12

2.2.3.1 Processor Version Register (PVR)......................................................................... 2-12

2.2.3.2 System Version Register (SVR)—MPC7448 Specific.......................................... 2-12

2.2.3.3 Processor Identification Register (PIR)................................................................. 2-12

2.2.3.4 Machine State Register (MSR).............................................................................. 2-13

2.2.3.5 Machine Status Save/Restore Registers (SRR0, SRR1)........................................ 2-16

2.2.3.6 SDR1 Register....................................................................................................... 2-16

2.2.4 PowerPC User-Level Registers (VEA)...................................................................... 2-17

2.2.4.1 Time Base Registers (TBL, TBU)......................................................................... 2-17

2.2.5 MPC7450-Specific Register Descriptions................................................................. 2-17

2.2.5.1 Hardware Implementation-Dependent Register 0 (HID0) .................................... 2-18

2.2.5.2 Hardware Implementation-Dependent Register 1 (HID1) .................................... 2-23

2.2.5.2.1 MPC7447A-Specific HID1 PLL Configuration Field....................................... 2-26

2.2.5.3 Memory Subsystem Control Register (MSSCR0)................................................. 2-27

2.2.5.4 Memory Subsystem Status Register (MSSSR0)....................................................2-29

2.2.5.5 Instruction and Data Cache Registers.................................................................... 2-30

2.2.5.5.1 L2 Cache Control Register (L2CR)...................................................................2-30

2.2.5.5.2 L2 Error Injection Mask High Register (L2ERRINJHI)—

MPC7448-Specific ........................................................................................ 2-33

2.2.5.5.3 L2 Error Injection Mask High Register (L2ERRINJLO)—

MPC7448-Specific ........................................................................................ 2-33

2.2.5.5.4 L2 Error Injection Mask Control Register (L2ERRINJCTL)—

MPC7448-Specific ........................................................................................ 2-34

2.2.5.5.5 L2 Error Capture Data High Register (L2CAPTDATAHI)—

MPC7448-Specific ........................................................................................ 2-34

2.2.5.5.6 L2 Error Capture Data Low Register (L2CAPTDATALO)—

MPC7448-Specific ........................................................................................ 2-35

2.2.5.5.7 L2 Error Syndrome Register (L2CAPTECC)—MPC7448-Specific................. 2-35

2.2.5.5.8 L2 Error Detect Register (L2ERRDET)—MPC7448-Specific.........................2-36

2.2.5.5.9 L2 Error Disable Register (L2ERRDIS)—MPC7448-Specific......................... 2-37

2.2.5.5.10 L2 Error Interrupt Enable Register (L2ERRINTEN)—MPC7448-Specific.....2-37

2.2.5.5.11 L2 Error Attributes Capture Register (L2ERRATTR)—MPC7448-Specific....2-38

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2.2.5.5.12 L2 Error Address Error Capture Register (L2ERRADDR)—

MPC7448-Specific ........................................................................................ 2-39

2.2.5.5.13 L2 Error Address Error Capture Register (L2ERREADDR)—

MPC7448-Specific ........................................................................................ 2-40

2.2.5.5.14 L2 Error Control Register (L2ERRCTL)—MPC7448-Specific ....................... 2-40

2.2.5.5.15 L3 Cache Control Register (L3CR)................................................................... 2-41

2.2.5.5.16 L3 Cache Output Hold Control Register (L3OHCR)—MPC7457-Specific..... 2-45

2.2.5.5.17 L3 Cache Input Timing Control (L3ITCR0) ..................................................... 2-47

2.2.5.5.18 L3 Cache Input Timing Control (L3ITCR1)—MPC7457-Specific .................. 2-48

2.2.5.5.19 L3 Cache Input Timing Control (L3ITCR2)—MPC7457-Specific .................. 2-49

2.2.5.5.20 L3 Cache Input Timing Control (L3ITCR3)—MPC7457-Specific .................. 2-49

2.2.5.5.21 Instruction Cache and Interrupt Control Register (ICTRL) .............................. 2-50

2.2.5.5.22 Load/Store Control Register (LDSTCR)...........................................................2-52

2.2.5.5.23 L3 Private Memory Address Register (L3PM) ................................................. 2-53

2.2.5.6 Instruction Address Breakpoint Register (IABR).................................................. 2-54

2.2.5.7 Memory Management Registers Used for Software Table Searching................... 2-54

2.2.5.7.1 TLB Miss Register (TLBMISS)........................................................................ 2-54

2.2.5.7.2 Page Table Entry Registers (PTEHI and PTELO).............................................2-55

2.2.5.8 Thermal Management Register.............................................................................. 2-56

2.2.5.8.1 Instruction Cache Throttling Control Register (ICTC) ..................................... 2-56

2.2.5.9 Performance Monitor Registers............................................................................. 2-57

2.2.5.9.1 Monitor Mode Control Register 0 (MMCR0)...................................................2-57

2.2.5.9.2 User Monitor Mode Control Register 0 (UMMCR0)........................................ 2-60

2.2.5.9.3 Monitor Mode Control Register 1 (MMCR1)...................................................2-60

2.2.5.9.4 User Monitor Mode Control Register 1 (UMMCR1)........................................ 2-61

2.2.5.9.5 Monitor Mode Control Register 2 (MMCR2)...................................................2-61

2.2.5.9.6 User Monitor Mode Control Register 2 (UMMCR2)........................................ 2-62

2.2.5.9.7 Breakpoint Address Mask Register (BAMR).................................................... 2-62

2.2.5.9.8 Performance Monitor Counter Registers (PMC1–PMC6) ................................ 2-63

2.2.5.9.9 User Performance Monitor Counter Registers (UPMC1–UPMC6).................. 2-64

2.2.5.9.10 Sampled Instruction Address Register (SIAR).................................................. 2-64

2.2.5.9.11 User-Sampled Instruction Address Register (USIAR)......................................2-64

2.2.5.9.12 Sampled Data Address Register (SDAR) and User-Sampled Data

Address Register (USDAR) .......................................................................... 2-64

2.2.6 Reset Settings.............................................................................................................2-64

2.3 Operand Conventions .................................................................................................... 2-67

2.3.1 Floating-Point Execution Models—UISA................................................................. 2-67

2.3.2 Data Organization in Memory and Data Transfers.................................................... 2-68

2.3.3 Alignment and Misaligned Accesses......................................................................... 2-68

2.3.4 Floating-Point Operands............................................................................................ 2-69

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2.4 Instruction Set Summary ............................................................................................... 2-69

2.4.1 Classes of Instructions............................................................................................... 2-70

2.4.1.1 Definition of Boundedly Undefined......................................................................2-70

2.4.1.2 Defined Instruction Class ...................................................................................... 2-71

2.4.1.3 Illegal Instruction Class.........................................................................................2-71

2.4.1.4 Reserved Instruction Class .................................................................................... 2-72

2.4.2 Addressing Modes ..................................................................................................... 2-72

2.4.2.1 Memory Addressing .............................................................................................. 2-72

2.4.2.2 Memory Operands ................................................................................................. 2-72

2.4.2.3 Effective Address Calculation...............................................................................2-73

2.4.2.4 Synchronization.....................................................................................................2-73

2.4.2.4.1 Context Synchronization ................................................................................... 2-73

2.4.2.4.2 Execution Synchronization................................................................................ 2-76

2.4.2.4.3 Instruction-Related Exceptions.......................................................................... 2-77

2.4.3 Instruction Set Overview........................................................................................... 2-77

2.4.4 PowerPC UISA Instructions......................................................................................2-78

2.4.4.1 Integer Instructions................................................................................................2-78

2.4.4.1.1 Integer Arithmetic Instructions..........................................................................2-78

2.4.4.1.2 Integer Compare Instructions ............................................................................2-79

2.4.4.1.3 Integer Logical Instructions............................................................................... 2-79

2.4.4.1.4 Integer Rotate and Shift Instructions................................................................. 2-80

2.4.4.2 Floating-Point Instructions .................................................................................... 2-81

2.4.4.2.1 Floating-Point Arithmetic Instructions.............................................................. 2-82

2.4.4.2.2 Floating-Point Multiply-Add Instructions......................................................... 2-82

2.4.4.2.3 Floating-Point Rounding and Conversion Instructions..................................... 2-83

2.4.4.2.4 Floating-Point Compare Instructions................................................................. 2-83

2.4.4.2.5 Floating-Point Status and Control Register Instructions...................................2-83

2.4.4.2.6 Floating-Point Move Instructions...................................................................... 2-84

2.4.4.3 Load and Store Instructions................................................................................... 2-84

2.4.4.3.1 Self-Modifying Code......................................................................................... 2-85

2.4.4.3.2 Integer Load and Store Address Generation...................................................... 2-85

2.4.4.3.3 Register Indirect Integer Load Instructions.......................................................2-85

2.4.4.3.4 Integer Store Instructions................................................................................... 2-87

2.4.4.3.5 Integer Store Gathering...................................................................................... 2-87

2.4.4.3.6 Integer Load and Store with Byte-Reverse Instructions....................................2-88

2.4.4.3.7 Integer Load and Store Multiple Instructions.................................................... 2-88

2.4.4.3.8 Integer Load and Store String Instructions........................................................ 2-88

2.4.4.3.9 Floating-Point Load and Store Address Generation.......................................... 2-89

2.4.4.3.10 Floating-Point Store Instructions....................................................................... 2-90

2.4.4.4 Branch and Flow Control Instructions................................................................... 2-92

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2.4.4.4.1 Branch Instruction Address Calculation............................................................ 2-92

2.4.4.4.2 Branch Instructions............................................................................................ 2-92

2.4.4.4.3 Condition Register Logical Instructions............................................................ 2-93

2.4.4.4.4 Trap Instructions................................................................................................ 2-93

2.4.4.5 System Linkage Instruction...................................................................................2-93

2.4.4.6 Processor Control Instructions............................................................................... 2-94

2.4.4.6.1 Move To/From Condition Register Instructions................................................ 2-94

2.4.4.6.2 Move To/From Special-Purpose Register Instructions...................................... 2-94

2.4.4.7 Memory Synchronization Instructions .................................................................. 2-96

2.4.5 PowerPC VEA Instructions....................................................................................... 2-97

2.4.5.1 Processor Control Instructions............................................................................... 2-97

2.4.5.2 Memory Synchronization Instructions .................................................................. 2-97

2.4.5.3 Memory Control Instructions ................................................................................2-98

2.4.5.3.1 User-Level Cache Instructions .......................................................................... 2-98

2.4.5.4 Optional External Control Instructions................................................................ 2-101

2.4.6 PowerPC OEA Instructions..................................................................................... 2-102

2.4.6.1 System Linkage Instructions................................................................................ 2-102

2.4.6.2 Processor Control Instructions............................................................................. 2-102

2.4.6.3 Memory Control Instructions ..............................................................................2-107

2.4.6.3.1 Supervisor-Level Cache Management Instruction .......................................... 2-107

2.4.6.3.2 Translation Lookaside Buffer Management Instructions ................................ 2-107

2.4.7 Recommended Simplified Mnemonics.................................................................... 2-108

2.4.8 Implementation-Specific Instructions......................................................................2-108

2.5 AltiVec Instructions ..................................................................................................... 2-110

2.6 AltiVec UISA Instructions............................................................................................2-111

2.6.1 Vector Integer Instructions........................................................................................2-111

2.6.1.1 Vector Integer Arithmetic Instructions ................................................................ 2-112

2.6.1.2 Vector Integer Compare Instructions................................................................... 2-113

2.6.1.3 Vector Integer Logical Instructions ..................................................................... 2-114

2.6.1.4 Vector Integer Rotate and Shift Instructions........................................................ 2-115

2.6.2 Vector Floating-Point Instructions........................................................................... 2-115

2.6.2.1 Vector Floating-Point Arithmetic Instructions..................................................... 2-116

2.6.2.2 Vector Floating-Point Multiply-Add Instructions................................................ 2-116

2.6.2.3 Vector Floating-Point Rounding and Conversion Instructions............................ 2-116

2.6.2.4 Vector Floating-Point Compare Instructions....................................................... 2-117

2.6.2.5 Vector Floating-Point Estimate Instructions........................................................ 2-117

2.6.3 Vector Load and Store Instructions.......................................................................... 2-117

2.6.3.1 Vector Load Instructions...................................................................................... 2-118

2.6.3.2 Vector Load Instructions Supporting Alignment................................................. 2-118

2.6.3.3 Vector Store Instructions...................................................................................... 2-119

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2.6.4 Control Flow............................................................................................................ 2-119

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2.6.5 Vector Permutation and Formatting Instructions..................................................... 2-119

2.6.5.1 Vector Pack Instructions ...................................................................................... 2-119

2.6.5.2 Vector Unpack Instructions.................................................................................. 2-120

2.6.5.3 Vector Merge Instructions.................................................................................... 2-120

2.6.5.4 Vector Splat Instructions......................................................................................2-121

2.6.5.5 Vector Permute Instructions................................................................................. 2-121

2.6.5.6 Vector Select Instruction...................................................................................... 2-122

2.6.5.7 Vector Shift Instructions ...................................................................................... 2-122

2.6.5.8 Vector Status and Control Register Instructions.................................................. 2-122

2.7 AltiVec VEA Instructions............................................................................................ 2-123

2.7.1 AltiVec Vector Memory Control Instructions.......................................................... 2-123

2.7.2 AltiVec Instructions with Specific Implementations for the MPC7450.................. 2-124

Chapter 3

L1, L2, and L3 Cache Operation

3.1 Overview.......................................................................................................................... 3-2

3.1.1 Block Diagram............................................................................................................. 3-4

3.1.2 Load/Store Unit (LSU) ................................................................................................ 3-7

3.1.2.1 Cacheable Loads and LSU....................................................................................... 3-7

3.1.2.2 LSU Store Queues ................................................................................................... 3-7

3.1.2.3 Store Gathering/Merging......................................................................................... 3-7

3.1.2.4 LSU Load Miss, Castout, and Push Queues............................................................ 3-8

3.1.3 Memory Subsystem Blocks.........................................................................................3-8

3.1.3.1 L1 Service Queues................................................................................................... 3-9

3.1.3.2 L2 Cache Block ..................................................................................................... 3-10

3.1.3.3 System Interface Block.......................................................................................... 3-10

3.1.4 L3 Cache Controller Block........................................................................................ 3-10

3.2 L1 Cache Organizations................................................................................................. 3-11

3.2.1 L1 Data Cache Organization...................................................................................... 3-11

3.2.2 L1 Instruction Cache Organization............................................................................3-13

3.3 Memory and Cache Coherency...................................................................................... 3-14

3.3.1 Memory/Cache Access Attributes (WIMG Bits)....................................................... 3-14

3.3.1.1 Coherency Paradoxes and WIMG ......................................................................... 3-15

3.3.1.2 Out-of-Order Accesses to Guarded Memory.........................................................3-15

3.3.2 Coherency Support ....................................................................................................3-16

3.3.2.1 Coherency Between L1, L2, and L3 Caches ......................................................... 3-17

3.3.2.1.1 Cache Closer to Core with Modified Data ........................................................ 3-17

3.3.2.1.2 Transient Data and Different Coherency States................................................. 3-18

3.3.2.2 Snoop Response.....................................................................................................3-18

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3.3.2.3 Intervention............................................................................................................3-18

3.3.2.4 Simplified Transaction Types ................................................................................ 3-19

3.3.2.5 MESI State Transitions.......................................................................................... 3-20

3.3.2.5.1 MESI Protocol in MPX Bus Mode with Data Intervention Enabled ................ 3-20

3.3.2.5.2 MESI Protocol in 60x Bus Mode and MPX Bus Mode

(with Intervention Disabled).......................................................................... 3-23

3.3.2.6 Reservation Snooping............................................................................................ 3-26

3.3.3 Load/Store Operations and Architecture Implications .............................................. 3-26

3.3.3.1 Performed Loads and Store....................................................................................3-27

3.3.3.2 Sequential Consistency of Memory Accesses.......................................................3-28

3.3.3.3 Load Ordering with Respect to Other Loads......................................................... 3-28

3.3.3.4 Store Ordering with Respect to Other Stores.........................................................3-29

3.3.3.5 Enforcing Store Ordering with Respect to Loads.................................................. 3-29

3.3.3.6 Atomic Memory References.................................................................................. 3-29

3.4 L1 Cache Control........................................................................................................... 3-30

3.4.1 Cache Control Parameters in HID0 ........................................................................... 3-30

3.4.1.1 Enabling and Disabling the Data Cache................................................................3-30

3.4.1.2 Data Cache Locking with DLOCK........................................................................ 3-31

3.4.1.3 Enabling and Disabling the Instruction Cache ...................................................... 3-32

3.4.1.4 Instruction Cache Locking with ILOCK ............................................................... 3-32

3.4.1.5 L1 Instruction and Data Cache Flash Invalidation ................................................ 3-32

3.4.2 Data Cache Way Locking Setting in LDSTCR ......................................................... 3-33

3.4.3 Cache Control Parameters in ICTRL.........................................................................3-33

3.4.3.1 Instruction Cache Way Locking ............................................................................ 3-33

3.4.3.2 Enabling Instruction Cache Parity Checking......................................................... 3-33

3.4.3.3 Instruction and Data Cache Parity Error Reporting...............................................3-34

3.4.4 Cache Control Instructions ........................................................................................ 3-34

3.4.4.1 Data Cache Block Touch (dcbt)............................................................................3-34

3.4.4.2 Data Cache Block Touch for Store (dcbtst).......................................................... 3-35

3.4.4.3 Data Cache Block Zero (dcbz).............................................................................. 3-36

3.4.4.4 Data Cache Block Store (dcbst)............................................................................ 3-36

3.4.4.5 Data Cache Block Flush (dcbf)............................................................................. 3-37

3.4.4.6 Data Cache Block Allocate (dcba)........................................................................ 3-37

3.4.4.7 Data Cache Block Invalidate (dcbi)...................................................................... 3-37

3.4.4.8 Instruction Cache Block Invalidate (icbi).............................................................. 3-38

3.5 L1 Cache Operation.......................................................................................................3-38

3.5.1 Cache Miss and Reload Operations........................................................................... 3-38

3.5.1.1 Data Cache Fills.....................................................................................................3-39

3.5.1.2 Instruction Cache Fills........................................................................................... 3-39

3.5.2 Cache Allocation on Misses ...................................................................................... 3-40

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3.5.2.1 Instruction Access Allocation in L1 Cache........................................................... 3-40

3.5.2.2 Data Access Allocation in L1 Cache.....................................................................3-40

3.5.3 Store Miss Merging....................................................................................................3-40

3.5.4 Load/Store Miss Handling (MPC7448-Specific) ...................................................... 3-41

3.5.5 Store Hit to a Data Cache Block Marked Shared ...................................................... 3-41

3.5.6 Data Cache Block Push Operation............................................................................. 3-41

3.5.7 L1 Cache Block Replacement Selection.................................................................... 3-41

3.5.7.1 PLRU Replacement............................................................................................... 3-41

3.5.7.2 PLRU Bit Updates.................................................................................................3-42

3.5.7.3 AltiVec LRU Instruction Support..........................................................................3-43

3.5.7.4 Cache Locking and PLRU..................................................................................... 3-44

3.5.8 L1 Cache Invalidation and Flushing.......................................................................... 3-44

3.5.9 L1 Cache Operation Summary .................................................................................. 3-45

3.6 L2 Cache....................................................................................................................... .3-49

3.6.1 L2 Cache Organization..............................................................................................3-49

3.6.2 L2 Cache and Memory Coherency............................................................................3-51

3.6.3 L2 Cache Control.......................................................................................................3-51

3.6.3.1 L2CR Parameters...................................................................................................3-51

3.6.3.1.1 Enabling the L2 Cache and L2 Initialization.....................................................3-51

3.6.3.1.2 Enabling L2 Parity Checking ............................................................................ 3-52

3.6.3.1.3 L2 Instruction-Only and Data-Only Modes....................................................... 3-52

3.6.3.1.4 L2 Cache Invalidation ....................................................................................... 3-52

3.6.3.1.5 Flushing of L1, L2, and L3 Caches ................................................................... 3-53

3.6.3.1.6 L2 Replacement Algorithm Selection ............................................................... 3-54

3.6.3.2 L2 Prefetch Engines and MSSCR0........................................................................ 3-54

3.6.3.3 L2 Parity Error Reporting...................................................................................... 3-55

3.6.3.4 L2 Data ECC (MPC7448-Specific)....................................................................... 3-55

3.6.3.4.1 Enabling or Disabling ECC...............................................................................3-55

3.6.3.4.2 L2 Error Control and Capture............................................................................ 3-55

3.6.3.4.3 ECC Error Reporting......................................................................................... 3-56

3.6.3.4.4 L2 Error Injection..............................................................................................3-56

3.6.3.5 Instruction Interactions with L2............................................................................. 3-57

3.6.4 L2 Cache Operation................................................................................................... 3-57

3.6.4.1 L2 Cache Miss and Reload Operations ................................................................. 3-58

3.6.4.2 L2 Cache Allocation.............................................................................................. 3-58

3.6.4.3 Store Data Merging and L2 ................................................................................... 3-59

3.6.4.4 L2 Cache Line Replacement Algorithms .............................................................. 3-59

3.6.4.5 L2 and L3 Operations Caused by L1 Requests ..................................................... 3-60

3.7 L3 Cache Interface......................................................................................................... 3-66

3.7.1 L3 Cache Interface Overview....................................................................................3-66

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3.7.2 L3 Cache Organization..............................................................................................3-67

3.7.3 L3 Cache Control Register (L3CR)........................................................................... 3-67

3.7.3.1 Enabling the L3 Cache and L3 Initialization......................................................... 3-67

3.7.3.2 L3 Cache Size........................................................................................................ 3-68

3.7.3.3 L3 Cache SRAM Types ......................................................................................... 3-68

3.7.3.4 L3 Cache Data-Only and Instruction-Only Modes................................................ 3-69

3.7.3.4.1 L3 Instruction-Only and Data-Only Operation ................................................. 3-69

3.7.3.4.2 L3 Cache Locking Using L3CR[L3DO] and L3CR[L3IO] .............................. 3-69

3.7.3.5 L3 Cache Parity Checking and Generation ........................................................... 3-69

3.7.3.6 L3 Cache Invalidation............................................................................................ 3-70

3.7.3.7 L3 Cache Flushing................................................................................................. 3-71

3.7.3.8 L3 Cache Clock and Timing Controls................................................................... 3-71

3.7.3.9 L3 Sample Point Configuration............................................................................. 3-72

3.7.3.9.1 Pipeline Burst and Late-Write SRAM............................................................... 3-72

3.7.3.9.2 MSUG2 DDR SRAM........................................................................................ 3-73

3.7.4 L3 Private Memory Address Register (L3PM).......................................................... 3-74

3.7.5 L3 Parity Error Reporting and MSSSR0................................................................... 3-75

3.7.6 Instruction Interactions with L3................................................................................. 3-75

3.7.7 L3 Cache Operation................................................................................................... 3-75

3.7.7.1 L3 Cache Miss and Reload Operations ................................................................. 3-76

3.7.7.2 L3 Cache Allocation.............................................................................................. 3-76

3.7.7.3 CI

and WT Accesses and L3 ................................................................................. 3-77

3.7.7.4 L3 Cache Replacement Selection..........................................................................3-77

3.7.8 L3 Private Memory Operation................................................................................... 3-77

3.7.8.1 Enabling and Initializing L3 Private Memory....................................................... 3-78

3.7.8.1.1 Initializing the L3 Private Memory when Parity is Enabled............................. 3-80

3.7.8.2 CI and WT Accesses Not Supported for Private Memory .................................... 3-80

3.7.8.3 Castouts and Private Memory................................................................................ 3-80

3.7.8.4 Snoop Hits and Private Memory............................................................................ 3-80

3.7.8.5 Private Memory and Instruction Interactions ........................................................ 3-81

3.7.9 L3 Cache SRAM Timing Examples..........................................................................3-82

3.7.9.1 MSUG2 DDR Interface Timing ............................................................................ 3-82

3.7.9.2 Late-Write SRAM Timing.....................................................................................3-84

3.7.9.3 Pipelined Burst SRAM.......................................................................................... 3-86

3.8 System Bus Interface ..................................................................................................... 3-87

3.8.1 MPC7450 Caches and System Bus Transactions......................................................3-88

3.8.2 Bus Operations Caused by Cache Control Instructions............................................. 3-89

3.8.3 Transfer Attributes..................................................................................................... 3-91

3.8.4 Snooping of External Transactions............................................................................3-93

3.8.4.1 Types of Transactions Snooped by MPC7450....................................................... 3-94

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3.8.4.2 L1 Cache State Transitions and Bus Operations Due to Snoops........................... 3-95

3.8.4.3 L2 and L3 Operations Caused by External Snoops............................................... 3-96

Chapter 4

Exceptions

4.1 MPC7450 Microprocessor Exceptions............................................................................4-3

4.2 MPC7450 Exception Recognition and Priorities............................................................. 4-5

4.3 Exception Processing....................................................................................................... 4-9

4.3.1 Enabling and Disabling Exceptions........................................................................... 4-12

4.3.2 Steps for Exception Processing.................................................................................. 4-13

4.3.3 Setting MSR[RI]........................................................................................................ 4-13

4.3.4 Returning from an Exception Handler.......................................................................4-14

4.4 Process Switching.......................................................................................................... 4-14

4.5 Data Stream Prefetching and Exceptions.......................................................................4-14

4.6 Exception Definitions .................................................................................................... 4-15

4.6.1 System Reset Exception (0x00100)........................................................................... 4-16

4.6.2 Machine Check Exception (0x00200) ....................................................................... 4-17

4.6.2.1 Machine Check Exception Enabled (MSR[ME] = 1)............................................ 4-20

4.6.2.2 Checkstop State (MSR[ME] = 0) .......................................................................... 4-22

4.6.3 DSI Exception (0x00300)..........................................................................................4-22

4.6.3.1 DSI Exception—Page Fault................................................................................... 4-22

4.6.3.2 DSI Exception—Data Address Breakpoint Facility.............................................. 4-23

4.6.4 ISI Exception (0x00400)............................................................................................ 4-23

4.6.5 External Interrupt Exception (0x00500).................................................................... 4-24

4.6.6 Alignment Exception (0x00600) ............................................................................... 4-25

4.6.7 Program Exception (0x00700)...................................................................................4-26

4.6.8 Floating-Point Unavailable Exception (0x00800).....................................................4-26

4.6.9 Decrementer Exception (0x00900)............................................................................ 4-26

4.6.10 System Call Exception (0x00C00) ............................................................................ 4-27

4.6.11 Trace Exception (0x00D00)....................................................................................... 4-27

4.6.12 Floating-Point Assist Exception (0x00E00)..............................................................4-27

4.6.13 Performance Monitor Exception (0x00F00).............................................................. 4-27

4.6.14 AltiVec Unavailable Exception (0x00F20)................................................................ 4-29

4.6.15 TLB Miss Exceptions ................................................................................................ 4-29

4.6.15.1 Instruction Table Miss Exception—ITLB Miss (0x01000)................................... 4-30

4.6.15.2 Data Table Miss-On-Load Exception—DTLB Miss-On-Load (0x01100)........... 4-30

4.6.15.3 Data Table Miss-On-Store Exception—DTLB Miss-On-Store (0x01200) .......... 4-30

4.6.16 Instruction Address Breakpoint Exception (0x01300) .............................................. 4-31

4.6.17 System Management Interrupt Exception (0x01400)................................................ 4-32

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4.6.18 AltiVec Assist Exception (0x01600).......................................................................... 4-32

Chapter 5

Memory Management

5.1 MMU Overview............................................................................................................... 5-2

5.1.1 Memory Addressing ....................................................................................................5-4

5.1.2 MMU Organization......................................................................................................5-5

5.1.3 Address Translation Mechanisms.............................................................................. 5-10

5.1.4 Memory Protection Facilities.....................................................................................5-14

5.1.5 Page History Information........................................................................................... 5-14

5.1.6 General Flow of MMU Address Translation............................................................. 5-15

5.1.6.1 Real Addressing Mode and Block Address Translation Selection........................ 5-15

5.1.6.2 Page Address Translation Selection ...................................................................... 5-16

5.1.7 MMU Exceptions Summary......................................................................................5-18

5.1.8 MMU Instructions and Register Summary................................................................ 5-21

5.2 Real Addressing Mode................................................................................................... 5-24

5.2.1 Real Addressing Mode—32-Bit Addressing.............................................................5-24

5.2.2 Real Addressing Mode—Extended Addressing........................................................ 5-24

5.3 Block Address Translation............................................................................................. 5-24

5.3.1 BAT Register Implementation of BAT Array—Extended Addressing...................... 5-25

5.3.2 Block Physical Address Generation—Extended Addressing....................................5-28

5.3.2.1 Block Physical Address Generation with an Extended BAT Block Size .............. 5-29

5.3.3 Block Address Translation Summary—Extended Addressing.................................. 5-31

5.4 Memory Segment Model ............................................................................................... 5-33

5.4.1 Page Address Translation Overview.......................................................................... 5-34

5.4.1.1 Segment Descriptor Definitions ............................................................................ 5-35

5.4.1.2 Page Table Entry (PTE) Definition—Extended Addressing..................................5-35

5.4.2 Page History Recording............................................................................................. 5-36

5.4.2.1 Referenced Bit ....................................................................................................... 5-38

5.4.2.2 Changed Bit........................................................................................................... 5-38

5.4.2.3 Scenarios for Referenced and Changed Bit Recording ......................................... 5-39

5.4.3 Page Memory Protection ........................................................................................... 5-40

5.4.4 TLB Description........................................................................................................ 5-40

5.4.4.1 TLB Organization and Operation..........................................................................5-40

5.4.4.2 TLB Invalidation ................................................................................................... 5-42

5.4.4.2.1 tlbie Instruction..................................................................................................5-42

5.4.4.2.2 tlbsync Instruction ............................................................................................. 5-44

5.4.4.2.3 Synchronization Requirements for tlbie and tlbsync......................................... 5-45

5.4.5 Page Address Translation Summary—Extended Addressing....................................5-46

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5.5 Hashed Page Tables—Extended Addressing................................................................. 5-48

5.5.1 SDR1 Register Definition—Extended Addressing.................................................... 5-48

5.5.1.1 Page Table Size......................................................................................................5-50

5.5.1.2 Page Table Hashing Functions............................................................................... 5-51

5.5.1.3 Page Table Address Generation............................................................................. 5-52

5.5.1.4 Page Table Structure Example—Extended Addressing.........................................5-54

5.5.1.5 PTEG Address Mapping Examples—Extended Addressing................................. 5-55

5.5.2 Page Table Search Operations—Implementation...................................................... 5-57

5.5.2.1 Conditions for a Page Table Search Operation...................................................... 5-58

5.5.2.2 AltiVec Line Fetch Skipping ................................................................................. 5-58

5.5.2.3 Page Table Search Operation—Conceptual Flow ................................................. 5-59

5.5.3 Page Table Updates.................................................................................................... 5-62

5.5.4 Segment Register Updates......................................................................................... 5-63

5.5.5 Implementation-Specific Software Table Search Operation .................................... 5-63

5.5.5.1 Resources for Table Search Operations................................................................. 5-63

5.5.5.1.1 TLB Miss Register (TLBMISS)........................................................................ 5-66

5.5.5.1.2 Page Table Entry Registers (PTEHI and PTELO).............................................5-66

5.5.5.1.3 Special Purpose Registers (4–7)........................................................................5-67

5.5.5.2 Example Software Table Search Operation........................................................... 5-68

5.5.5.2.1 Flow for Example Exception Handlers ............................................................. 5-68

5.5.5.2.2 Code for Example Exception Handlers ............................................................. 5-73

Chapter 6

Instruction Timing

6.1 Terminology and Conventions.........................................................................................6-2

6.2 Instruction Timing Overview........................................................................................... 6-4

6.3 Timing Considerations................................................................................................... 6-11

6.3.1 General Instruction Flow........................................................................................... 6-11

6.3.2 Instruction Fetch Timing............................................................................................6-16

6.3.2.1 Cache Arbitration................................................................................................... 6-16

6.3.2.2 Cache Hit............................................................................................................... 6-16

6.3.2.3 Cache Miss............................................................................................................. 6-20

6.3.2.4 L2 Cache Access Timing Considerations ............................................................. 6-22

6.3.2.4.1 Instruction Cache and L2 Cache Hit.................................................................. 6-22

6.3.2.4.2 Instruction Cache Miss/L3 Cache Hit ............................................................... 6-24

6.3.3 Dispatch, Issue, and Completion Considerations ...................................................... 6-26

6.3.3.1 Rename Register Operation................................................................................... 6-27

6.3.3.2 Instruction Serialization.........................................................................................6-27

6.4 Execution Unit Timings.................................................................................................6-28

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6.4.1 Branch Processing Unit Execution Timing................................................................6-28

6.4.1.1 Branch Folding and Removal of Fall-Through Branch Instructions..................... 6-28

6.4.1.2 Branch Instructions and Completion..................................................................... 6-30

6.4.1.3 Branch Prediction and Resolution......................................................................... 6-31

6.4.1.3.1 Static Branch Prediction....................................................................................6-32

6.4.1.3.2 Predicted Branch Timing Examples..................................................................6-32

6.4.2 Integer Unit Execution Timing.................................................................................. 6-34

6.4.3 FPU Execution Timing..............................................................................................6-35

6.4.3.1 Effect of Floating-Point Exceptions on Performance............................................ 6-35

6.4.4 Load/Store Unit Execution Timing............................................................................6-35

6.4.4.1 Effect of Operand Placement on Performance ...................................................... 6-35

6.4.4.2 Store Gathering...................................................................................................... 6-36

6.4.4.3 AltiVec Instructions Executed by the LSU............................................................ 6-37

6.4.4.3.1 LRU Instructions ............................................................................................... 6-37

6.4.4.3.2 Transient Instructions ........................................................................................ 6-37

6.4.5 AltiVec Instructions ................................................................................................... 6-38

6.4.5.1 AltiVec Unit Execution Timing............................................................................. 6-38

6.4.5.1.1 AltiVec Permute Unit (VPU) Execution Timing............................................... 6-38

6.4.5.1.2 Vector Simple Integer Unit (VIU1) Execution Timing ..................................... 6-38

6.4.5.1.3 Vector Complex Integer Unit (VIU2) Execution Timing.................................. 6-38

6.4.5.1.4 Vector Floating-Point Unit (VFPU) Execution Timing..................................... 6-38

6.5 Memory Performance Considerations ........................................................................... 6-41

6.5.1 Caching and Memory Coherency .............................................................................. 6-41

6.6 Instruction Latency Summary........................................................................................6-41

6.7 Instruction Scheduling Guidelines................................................................................. 6-54

6.7.1 Fetch/Branch Considerations..................................................................................... 6-55

6.7.1.1 Fetching Examples................................................................................................. 6-55

6.7.1.1.1 Fetch Alignment Example................................................................................. 6-55

6.7.1.1.2 Branch-Taken Bubble Example......................................................................... 6-57

6.7.1.2 Branch Conditionals .............................................................................................. 6-58

6.7.1.2.1 Branch Mispredict Example..............................................................................6-58

6.7.1.2.2 Branch Loop Example.......................................................................................6-58

6.7.1.3 Static versus Dynamic Prediction.......................................................................... 6-60

6.7.1.4 Using the Link Stack for Branch Indirect.............................................................. 6-60

6.7.1.4.1 Link Stack Example........................................................................................... 6-61

6.7.1.4.2 Position-Independent Code Example ................................................................ 6-62

6.7.1.5 Branch Folding ...................................................................................................... 6-63

6.7.2 Dispatch Unit Resource Requirements...................................................................... 6-63

6.7.2.1 Dispatch Groupings............................................................................................... 6-63

6.7.2.1.1 Dispatch Stall Due to Rename Availability....................................................... 6-64

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6.7.2.2 Dispatching Load/Store Strings and Multiples......................................................6-64

6.7.2.2.1 Example of Load/Store Multiple Micro-Operation Generation ........................ 6-65

6.7.3 Issue Queue Resource Requirements.........................................................................6-66

6.7.3.1 GPR Issue Queue (GIQ)........................................................................................6-66

6.7.3.2 Vector Issue Queue (VIQ) ..................................................................................... 6-67

6.7.3.3 Floating-Point Issue Queue (FIQ) ......................................................................... 6-67

6.7.4 Completion Unit Resource Requirements ................................................................. 6-68

6.7.4.1 Completion Groupings........................................................................................... 6-68

6.7.5 Serialization Effects................................................................................................... 6-68

6.7.6 Execution Unit Considerations..................................................................................6-69

6.7.6.1 IU1 Considerations................................................................................................6-69

6.7.6.2 IU2 Considerations................................................................................................6-70

6.7.6.3 FPU Considerations............................................................................................... 6-70

6.7.6.4 Vector Unit Considerations....................................................................................6-72

6.7.6.5 Load/Store Unit (LSU).......................................................................................... 6-72

6.7.6.5.1 Load Hit Pipeline...............................................................................................6-74

6.7.6.5.2 Store Hit Pipeline............................................................................................... 6-74

6.7.6.5.3 Load/Store Interaction....................................................................................... 6-75

6.7.6.5.4 Misalignment Effects......................................................................................... 6-76

6.7.6.5.5 Load Miss Pipeline............................................................................................6-77

6.7.6.5.6 Store Miss Pipeline............................................................................................ 6-79

6.7.6.5.7 DST Instructions and the Vector Touch Engine (VTE)..................................... 6-81

6.7.7 Memory Subsystem Considerations .......................................................................... 6-82

6.7.7.1 L2 Cache Effects.................................................................................................... 6-82

6.7.7.2 L3 Cache Effects.................................................................................................... 6-82

6.7.7.3 Hardware Prefetching............................................................................................ 6-82

Chapter 7

AltiVec Technology Implementation

7.1 AltiVec Technology and the Programming Model .......................................................... 7-2

7.1.1 Register Set.................................................................................................................. 7-2

7.1.1.1 Changes to the Condition Register..........................................................................7-2

7.1.1.2 Addition to the Machine State Register...................................................................7-2

7.1.1.3 Vector Registers (VRs)............................................................................................ 7-2

7.1.1.4 Vector Status and Control Register (VSCR)............................................................ 7-3

7.1.1.5 Vector Save/Restore Register (VRSAVE) ............................................................... 7-4

7.1.2 AltiVec Instruction Set.................................................................................................7-4

7.1.2.1 LRU Instructions ..................................................................................................... 7-5

7.1.2.2 Transient Instructions and Caches...........................................................................7-5

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7.1.2.3 Data Stream Touch Instructions............................................................................... 7-6

7.1.2.3.1 Stream Engine Tags ............................................................................................. 7-7

7.1.2.3.2 Speculative Execution and Pipeline Stalls

for Data Stream Instructions7-8

7.1.2.3.3 Static/Transient Data Stream Touch Instructions ................................................ 7-8

7.1.2.3.4 Relationship with the sync/tblsync Instructions................................................. 7-8

7.1.2.3.5 Data Stream T e rmination.....................................................................................7-9

7.1.2.3.6 Line Fetch Skipping............................................................................................. 7-9

7.1.2.3.7 Context Awareness and Stream Pausing.............................................................. 7-9

7.1.2.3.8 Differences Between dst/dstt and dstst/dststt Instructions.............................. 7-10

7.1.2.4 dss and dssall Instructions.....................................................................................7-10

7.1.2.5 Java Mode, NaNs, Denormalized Numbers, and Zeros......................................... 7-10

7.1.3 Differences between the MPC7400/MPC7410 and the MPC7450 ........................... 7-14

7.1.3.1 Java and Non-Java Mode....................................................................................... 7-14

7.1.3.2 AltiVec Instructions ............................................................................................... 7-14

7.1.3.3 AltiVec Instruction Sequencing.............................................................................7-15

7.2 AltiVec Technology and the Cache Model .................................................................... 7-16

7.3 AltiVec and the Exception Model.................................................................................. 7-17

7.4 AltiVec and the Memory Management Model .............................................................. 7-17

7.5 AltiVec Technology and Instruction Timing.................................................................. 7-17

Chapter 8

Signal Descriptions

8.1 Signal Groupings .............................................................................................................8-1

8.1.1 Signal Summary........................................................................................................... 8-2

8.1.2 Output Signal States During Reset .............................................................................. 8-5

8.2 MPX Bus Signal Configuration....................................................................................... 8-5

8.2.1 MPX/60x Bus Protocol Signal Compatibility ............................................................. 8-6

8.2.2 MPX Bus Mode Signals .............................................................................................. 8-6

8.2.3 60x Bus Signals Not in the MPC7450......................................................................... 8-7

8.2.3.1 Address Bus Busy and Data Bus Busy (ABB

and DBB)........................................8-7

8.2.3.2 Data Bus Write Only (DBWO)................................................................................ 8-7

8.2.3.3 Data Retry (DRTRY)............................................................................................... 8-7

8.2.3.4 Extended Transfer Protocol (XATS)........................................................................ 8-7

8.2.3.5 Transfer Code (TC[0:1]).......................................................................................... 8-7

8.2.3.6 Cache Set Element (CSE[0:1])................................................................................8-7

8.2.3.7 Address Parity Error and Data Parity Error (APE, DPE)........................................ 8-7

8.2.4 MPX Bus Mode Functional Groupings.......................................................................8-7

8.2.5 Address Bus Arbitration Signals................................................................................8-12

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8.2.5.1 Bus Request (BR

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8.2.5.2 Bus Grant (BG)—Input ......................................................................................... 8-12

8.2.6 Address Bus and Parity in MPX Bus Mode .............................................................. 8-13

8.2.6.1 Address Bus (A[0:35])........................................................................................... 8-13

8.2.6.1.1 Address Bus (A[0:35])—Output ....................................................................... 8-13

8.2.6.1.2 Address Bus (A[0:35])—Input..........................................................................8-14

8.2.6.2 Address Bus Parity (AP[0:4])................................................................................ 8-14

8.2.6.2.1 Address Bus Parity (AP[0:4])—Output............................................................. 8-14

8.2.6.2.2 Address Bus Parity (AP[0:4])—Input ............................................................... 8-15

8.2.7 Address Transfer Attribute Signals in MPX Bus Mode............................................8-15

8.2.7.1 Transfer Start (TS)................................................................................................. 8-15

8.2.7.1.1 Transfer Start (TS)—Output.............................................................................. 8-15

8.2.7.1.2 Transfer Start (TS)—Input ................................................................................8-16

8.2.7.2 Transfer Type (TT[0:4]).........................................................................................8-16

8.2.7.2.1 Transfer Type (TT[0:4])—Output ..................................................................... 8-16

8.2.7.2.2 Transfer Type (TT[0:4])—Input ........................................................................ 8-16

8.2.7.3 Transfer Burst (TBST)—Output............................................................................ 8-16

8.2.7.4 Transfer Size (TSIZ[0:2])—Output....................................................................... 8-17

8.2.7.5 Global (GBL).........................................................................................................8-17

8.2.7.5.1 Global (GBL)—Output ..................................................................................... 8-17

8.2.7.5.2 Global (GBL)—Input........................................................................................ 8-17

8.2.7.6 Write-Through (WT)—Output..............................................................................8-18

8.2.7.7 Cache Inhibit (CI)—Output................................................................................... 8-18

8.2.8 MPX Address Transfer Termination Signals............................................................. 8-18

8.2.8.1 Address Acknowledge (AACK)—Input ............................................................... 8-18

8.2.8.2 Address Retry (ARTRY).......................................................................................8-19

8.2.8.2.1 Address Retry (ARTRY)—Output.................................................................... 8-19

8.2.8.2.2 Address Retry (ARTRY)—Input....................................................................... 8-19

8.2.8.3 Shared (SHD0, SHD1) Signals.............................................................................. 8-20

8.2.8.3.1 Shared (SHD0, SHD1)—Output ....................................................................... 8-20

8.2.8.3.2 Shared (SHD0, SHD1)—Input..........................................................................8-21

8.2.8.4 Snoop Hit (HIT)—Output...................................................................................... 8-21

8.2.9 Data Bus Arbitration Signals.....................................................................................8-22

8.2.9.1 Data Bus Grant (DBG)—Input.............................................................................. 8-22

8.2.9.2 Data Transaction Index (DTI[0:3])—Input ........................................................... 8-23

8.2.9.3 Data Ready (DRDY)—Output .............................................................................. 8-24

8.2.10 Data Transfer Signals................................................................................................. 8-24

8.2.10.1 Data Bus (D[0:63])................................................................................................8-24

8.2.10.1.1 Data Bus (D[0:63])—Output............................................................................. 8-25

8.2.10.1.2 Data Bus (D[0:63])—Input................................................................................ 8-25

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8.2.10.2 Data Bus Parity (DP[0:7]) ..................................................................................... 8-25

8.2.10.2.1 Data Bus Parity (DP[0:7])—Output .................................................................. 8-25

8.2.10.2.2 Data Bus Parity (DP[0:7])—Input.....................................................................8-26

8.2.11 Data Transfer Termination Signals ............................................................................ 8-26

8.2.11.1 Transfer Acknowledge (TA

)—Input ..................................................................... 8-26

8.2.11.2 Transfer Error Acknowledge (TEA)—Input......................................................... 8-27

8.3 60x Bus Signal Configuration........................................................................................ 8-27

8.3.1 60x Bus Mode Functional Groupings........................................................................ 8-27

8.3.2 60x Address Bus Arbitration Signals......................................................................... 8-32

8.3.2.1 Bus Request (BR)—Output...................................................................................8-32

8.3.2.2 Bus Grant (BG)—Input ......................................................................................... 8-32

8.3.3 Address Bus and Parity in 60x Bus Mode................................................................. 8-32

8.3.3.1 Address Bus (A[0:35])—Output............................................................................ 8-33

8.3.3.2 Address Bus (A[0:35])—Input .............................................................................. 8-33

8.3.3.3 Address Parity (AP[0:4])—Output........................................................................ 8-33

8.3.3.4 Address Parity (AP[0:4])—Input........................................................................... 8-33

8.3.4 Address Transfer Attribute Signals in 60x Bus Mode............................................... 8-33

8.3.4.1 Transfer Start (TS)................................................................................................. 8-33

8.3.4.1.1 Transfer Start (TS)—Output.............................................................................. 8-34

8.3.4.1.2 Transfer Start (TS)—Input.................................................................................8-34

8.3.4.2 Transfer Type (TT[0:4]).........................................................................................8-34

8.3.4.2.1 Transfer Type (TT[0:4])—Output ..................................................................... 8-34

8.3.4.2.2 Transfer Type (TT[0:4])—Input ........................................................................ 8-34

8.3.4.3 Transfer Burst (TBST)—Output ........................................................................... 8-35

8.3.4.4 Transfer Size (TSIZ[0:2])—Output....................................................................... 8-35

8.3.4.5 Global (GBL).........................................................................................................8-35

8.3.4.5.1 Global (GBL)—Output...................................................................................... 8-35

8.3.4.5.2 Global (GBL)—Input ........................................................................................ 8-35

8.3.4.6 Write-Through (WT)—Output..............................................................................8-36

8.3.4.7 Cache Inhibit (CI)—Output................................................................................... 8-36

8.3.5 60x Address Transfer Termination Signals................................................................ 8-36

8.3.5.1 Address Acknowledge (AACK)—Input................................................................ 8-36

8.3.5.2 Address Retry (ARTRY)........................................................................................ 8-37

8.3.5.2.1 Address Retry (ARTRY)—Output .................................................................... 8-37

8.3.5.2.2 Address Retry (ARTRY)—Input.......................................................................8-37

8.3.5.3 Shared (SHD0) ...................................................................................................... 8-37

8.3.5.3.1 Shared (SHD0)—Output...................................................................................8-38

8.3.5.3.2 Shared (SHD0)—Input......................................................................................8-38

8.3.6 Data Bus Arbitration Signals.....................................................................................8-38

8.3.6.1 Data Bus Grant (DBG)—Input.............................................................................. 8-38

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8.3.6.2 Data Transaction Index (DTI[0:3])—Input ........................................................... 8-39

8.3.7 Data Transfer Signals in 60x Bus Mode.................................................................... 8-39

8.3.7.1 Data Bus (D[0:63]) ................................................................................................ 8-39

8.3.7.1.1 Data Bus (D[0:63])—Output.............................................................................8-39

8.3.7.1.2 Data Bus (D[0:63])—Input................................................................................ 8-39

8.3.7.2 Data Bus Parity (DP[0:7]) ..................................................................................... 8-39

8.3.7.2.1 Data Bus Parity (DP[0:7])—Output.................................................................. 8-40

8.3.7.2.2 Data Bus Parity (DP[0:7])—Input..................................................................... 8-40

8.3.8 Data Transfer Termination Signals in 60x Bus Mode ............................................... 8-40

8.3.8.1 Transfer Acknowledge (TA

)—Input ..................................................................... 8-40

8.3.8.2 Transfer Error Acknowledge (TEA)—Input ......................................................... 8-40

8.4 Non-Protocol Signal Descriptions ................................................................................. 8-41

8.4.1 L3 Cache Address/Data............................................................................................. 8-41

8.4.1.1 L3 Address (L3_ADDR[17:0])—Output .............................................................. 8-41

8.4.1.2 L3 Data (L3_DATA[0:63])....................................................................................8-42

8.4.1.2.1 L3 Data (L3_DATA[0:63])—Output................................................................. 8-43

8.4.1.2.2 L3 Data (L3_DATA[0:63])—Input.................................................................... 8-43

8.4.1.3 L3 Data Parity (L3_DP[0:7]).................................................................................8-43

8.4.1.3.1 L3 Data Parity (L3_DP[0:7])—Output.............................................................. 8-43

8.4.1.3.2 L3 Data Parity (L3_DP[0:7])—Input ................................................................ 8-44

8.4.2 L3 Cache Clock/Control............................................................................................8-44

8.4.2.1 L3 Clock (L3_CLK[0:1])—Output ....................................................................... 8-44

8.4.2.2 L3 Clock Synchronization (L3_ECHO_CLK[0:3]) .............................................. 8-44

8.4.2.2.1 L3 Clock Synchronization (L3_ECHO_CLK[1,3])—Output ........................... 8-44

8.4.2.2.2 L3 Clock Synchronization (L3_ECHO_CLK[0:3])—Input.............................. 8-44

8.4.2.3 L3 Control (L3_CNTL[0:1]) ................................................................................. 8-45

8.4.2.3.1 L3 Control (L3_CNTL0)—Output.................................................................... 8-45

8.4.2.3.2 L3 Control (L3_CNTL1)—Output.................................................................... 8-45

8.4.2.4 L3 Voltage Select (L3_VSEL)—Input .................................................................. 8-45

8.4.3 Interrupts/Reset Signals.............................................................................................8-46

8.4.3.1 Interrupt (INT)—Input........................................................................................... 8-46

8.4.3.2 System Management Interrupt (SMI)—Input ....................................................... 8-46

8.4.3.3 Machine Check (MCP)—Input.............................................................................. 8-46

8.4.3.4 Reset Signals.......................................................................................................... 8-47

8.4.3.4.1 Soft Reset (SRESET)—Input............................................................................ 8-47

8.4.3.4.2 Hard Reset (HRESET)—Input.......................................................................... 8-47

8.4.3.5 Checkstop Input (CKSTP_IN)—Input.................................................................. 8-47

8.4.3.6 Checkstop Output (CKSTP_OUT)—Output......................................................... 8-48

8.4.4 Processor Status/Control Signals............................................................................... 8-48

8.4.4.1 Timebase Enable (TBEN)—Input.........................................................................8-48

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8.4.4.2 Quiescent Request (QREQ

)—Output....................................................................8-49

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8.4.4.3 Quiescent Acknowledge (QACK)—Input............................................................. 8-49

8.4.4.4 Bus Voltage Select (BVSEL)—Input .................................................................... 8-49

8.4.4.5 BVSEL[0:1] (MPC7448 Specific)......................................................................... 8-50

8.4.4.6 DFS Divide-by-Two and Divide-by-Four (DFS2 and DFS4)

(MPC7448-Specific).......................................................................................... 8-50

8.4.4.7 Low Voltage RAM (LVRAM) (MPC7448-Specific) ............................................ 8-50

8.4.4.8 Bus Mode Select (BMODE[0:1])..........................................................................8-51

8.4.4.8.1 Bus Selection Mode (BMODE0)—Input During HRESET.............................. 8-51

8.4.4.8.2 Address Bus Driven Mode (BMODE0)—Input After HRESET ...................... 8-52

8.4.4.8.3 Bus Selection Mode (BMODE1)—Input During HRESET.............................. 8-52

8.4.4.8.4 Bus Selection Mode (BMODE1)—Input After HRESET................................. 8-53

8.4.4.9 Performance Monitor In (PMON_IN)—Input....................................................... 8-53

8.4.4.10 Performance Monitor Out (PMON_OUT)—Output............................................. 8-54

8.4.5 Clock Control Signals................................................................................................8-54

8.4.5.1 System Clock (SYSCLK)—Input.......................................................................... 8-54

8.4.5.2 PLL Configuration (PLL_CFG[0:4])—Input........................................................8-55

8.4.5.3 PLL_CFG[5] (MPC7448-Specific)....................................................................... 8-55

8.4.5.4 Extension Qualifier (EXT_QUAL)—Input........................................................... 8-55

8.4.5.5 Clock Out (CLK_OUT)—Output..........................................................................8-56

8.4.6 IEEE 1149.1a-1993 (JTAG) Interface Description.................................................... 8-56

8.4.6.1 JTAG Test Clock (TCK)—Input............................................................................8-57

8.4.6.2 JTAG Test Data Input (TDI)—Input ..................................................................... 8-57

8.4.6.3 JTAG Test Data Output (TDO)—Output............................................................... 8-57

8.4.6.4 JTAG Test Mode Select (TMS)—Input................................................................. 8-57

8.4.6.5 JTAG Test Reset (TRST)—Input ..........................................................................8-57

8.4.7 Configuration Signals Sampled at Reset ................................................................... 8-58

8.4.8 Power and Ground Signals ........................................................................................8-58

Chapter 9

System Interface Operation

9.1 MPC7450 System Interface Overview ............................................................................ 9-1

9.1.1 MPC7450 Bus Operation Features..............................................................................9-1

9.1.1.1 MPX Bus Features................................................................................................... 9-2

9.1.1.2 60x Bus Features...................................................................................................... 9-2

9.1.2 Overview of System Interface Accesses......................................................................9-2

9.1.3 Summary of L1 Instruction and Data Cache Operation .............................................. 9-6

9.1.4 L2 Cache Overview..................................................................................................... 9-7

9.1.5 L3 Cache Overview..................................................................................................... 9-7

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9.1.6 Operation of the System Interface ............................................................................... 9-7

9.1.7 Memory Subsystem Control Register (MSSCR0)....................................................... 9-8

9.1.8 Memory Subsystem Status Register (MSSSR0).......................................................... 9-8

9.1.9 Direct-Store Accesses Not Supported.......................................................................... 9-8

9.1.10 Common Timing Diagram Symbols............................................................................ 9-8

9.2 MPX Bus Protocol........................................................................................................... 9-9

9.2.1 MPX Bus Pipelining.................................................................................................. 9-11

9.3 MPX Bus Address Tenure .............................................................................................9-12

9.3.1 MPX Bus Address Bus Arbitration ........................................................................... 9-12

9.3.1.1 Qualified Bus Grant in MPX Bus Mode................................................................ 9-12

9.3.1.2 MPX Address Bus Parking.................................................................................... 9-13

9.3.2 MPX Bus Address Transfer....................................................................................... 9-15

9.3.2.1 Address Bus Driven Mode..................................................................................... 9-17

9.3.2.2 Address Bus Streaming.......................................................................................... 9-17

9.3.2.3 Address Bus Parity ................................................................................................9-17

9.3.2.4 Address Transfer Attributes................................................................................... 9-18

9.3.2.4.1 Transfer Type (TT[0:4]) Signals........................................................................ 9-18

9.3.2.4.2 Transfer Size (TSIZ[0:2]) and Transfer Burst TBST

Signals............................ 9-19

9.3.2.4.3 Write-Through (WT), Cache Inhibit (CI), and Global (GBL) Signals.............. 9-21

9.3.2.5 Burst Ordering During Data Transfers .................................................................. 9-21

9.3.2.6 Effect of Alignment in Data Transfers...................................................................9-22

9.3.2.6.1 Misalignment Example......................................................................................9-23

9.3.2.6.2 Alignment of External Control Instructions......................................................9-23

9.3.3 MPX Bus Address Tenure Termination..................................................................... 9-24

9.3.3.1 Address Retry Window and Qualified ARTRY .................................................... 9-25

9.3.3.2 Snoop Copybacks and the Window-of-Opportunity ............................................. 9-27

9.3.3.3 Shared (SHD0, SHD1) Signals in MPX Bus Mode..............................................9-28

9.3.3.4 Hit (HIT) Signal and Data Intervention................................................................. 9-29

9.4 MPX Bus Data Tenure................................................................................................... 9-30

9.4.1 MPX Bus Data Bus Arbitration................................................................................. 9-30

9.4.1.1 Qualified Data Bus Grant in MPX Bus Mode....................................................... 9-30

9.4.2 MPX Bus Data Transfer.............................................................................................9-31

9.4.2.1 Data Bus Parity......................................................................................................9-31

9.4.2.2 Earliest Transfer of Data........................................................................................ 9-32

9.4.2.2.1 Data Streaming in MPX Bus Mode................................................................... 9-32

9.4.2.3 Data Te nure Reordering......................................................................................... 9-33

9.4.2.4 MPX Bus Data Intervention .................................................................................. 9-33

9.4.2.4.1 Data-Only Transaction Protocol........................................................................ 9-35

9.4.2.4.2 DRDY Timing...................................................................................................9-36

9.4.2.4.3 Pipelining of Data-Only Transactions............................................................... 9-36

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9.4.2.4.4 Retrying Data-Only Transactions...................................................................... 9-36

9.4.2.4.5 Ordering of Data-Only Transactions................................................................. 9-37

9.4.2.4.6 Snarfing ............................................................................................................. 9-38

9.4.3 MPX Bus Data Tenure Termination .......................................................................... 9-38

9.4.3.1 Normal Single-Beat Transfer Termination ............................................................ 9-38

9.4.3.2 Normal Burst Transfer Termination....................................................................... 9-39

9.4.3.3 Data Transfer Termination Due to a Bus Error......................................................9-40

9.5 60x Bus Protocol............................................................................................................ 9-41

9.5.1 60x Bus Pipelining..................................................................................................... 9-41

9.6 60x Bus Address Tenure ................................................................................................ 9-42

9.6.1 60x Bus Address Bus Arbitration..............................................................................9-42

9.6.1.1 Qualified Bus Grant in 60x Bus Mode.................................................................. 9-42

9.6.1.2 60x Address Bus Parking....................................................................................... 9-43

9.6.2 60x Bus Address Transfer.......................................................................................... 9-43

9.6.2.1 60x Address Bus Driven Mode.............................................................................. 9-43

9.6.2.2 60x Address Bus Parity ......................................................................................... 9-43

9.6.2.3 60x Address Transfer Attributes............................................................................ 9-44

9.6.2.3.1 60x Transfer Size (TSIZ[0:2]) and Transfer Burst (TBST

) Signals.................. 9-44

9.6.2.4 Aligned and Misaligned Transfers......................................................................... 9-45

9.6.3 60x Bus Address Transfer Termination ..................................................................... 9-45

9.6.3.1 Snoop Response and SHD Signal..........................................................................9-45

9.7 60x Bus Data Tenure...................................................................................................... 9-46

9.7.1 60x Bus Data Bus Arbitration.................................................................................... 9-46

9.7.1.1 Qualified Data Bus Grant in 60x Bus Mode.......................................................... 9-46

9.7.2 60x Bus Data Transfers.............................................................................................. 9-47

9.7.3 60x Bus Data Tenure Termination............................................................................. 9-47

9.8 60x Bus Timing Examples............................................................................................. 9-48

9.9 Reset, Interrupt, Checkstop, and Power Management Signal Interactions.................... 9-54

9.9.1 Reset Inputs................................................................................................................9-54

9.9.2 External Interrupts ..................................................................................................... 9-54

9.9.3 Checkstops.................................................................................................................9-54

9.9.4 Power Management Signals....................................................................................... 9-55

9.10 IEEE 1149.1a-1993 Compliant Interface....................................................................... 9-55

9.10.1 JTAG/COP Interface..................................................................................................9-55

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Chapter 10

Power and Thermal Management

10.1 Dynamic Power Management........................................................................................10-1

10.2 Programmable Power Mode ..........................................................................................10-1

10.2.1 Full-Power Mode.......................................................................................................10-3

10.2.2 Nap Mode ..................................................................................................................10-3

10.2.2.1 Entering Nap Mode................................................................................................ 10-3

10.2.2.2 Exiting Nap Mode.................................................................................................. 10-3

10.2.2.3 Snooping in Nap Mode (Doze).............................................................................. 10-3

10.2.3 Sleep Mode................................................................................................................10-4

10.2.3.1 Entering Sleep Mode ............................................................................................. 10-4

10.2.3.2 Exiting Sleep Mode ............................................................................................... 10-4

10.2.3.3 Deep Sleep Mode................................................................................................... 10-4

10.2.4 Power Management Software Considerations........................................................... 10-4

10.2.5 Dynamic Frequency Switching (DFS)....................................................................... 10-5

10.2.5.1 Snooping Restrictions............................................................................................ 10-6

10.2.5.2 DFS in the MPC7447A..........................................................................................10-7

10.2.5.3 DFS in the MPC7448............................................................................................. 10-7

10.3 Instruction Cache Throttling.......................................................................................... 10-7

10.4 MPC7447A and MPC7448 Temperature Diode............................................................ 10-8

Chapter 11

Performance Monitor

11.1 Overview........................................................................................................................ 11-2

11.2 Performance Monitor Exception.................................................................................... 11-2

11.2.1 Performance Monitor Signals.................................................................................... 11-3

11.2.2 Using Timebase Event to Trigger or Freeze a Counter or Generate an Exception.... 11-3

11.3 Performance Monitor Registers..................................................................................... 11-3

11.3.1 Performance Monitor Special-Purpose Registers...................................................... 11-4

11.3.2 Monitor Mode Control Register 0 (MMCR0)........................................................... 11-5

11.3.2.1 User Monitor Mode Control Register 0 (UMMCR0)............................................ 11-8

11.3.3 Monitor Mode Control Register 1 (MMCR1)........................................................... 11-8

11.3.3.1 User Monitor Mode Control Register 1 (UMMCR1)............................................ 11-9

11.3.4 Monitor Mode Control Register 2 (MMCR2)........................................................... 11-9

11.3.4.1 User Monitor Mode Control Register 2 (UMMCR2)............................................ 11-9

11.3.5 Breakpoint Address Mask Register (BAMR).......................................................... 11-10

11.3.6 Performance Monitor Counter Registers (PMC1–PMC6)....................................... 11-10

11.3.6.1 User Performance Monitor Counter Registers (UPMC1–UPMC6) .....................11-11

11.3.7 Sampled Instruction Address Register (SIAR)........................................................ 11-12

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11.3.7.1 User Sampled Instruction Address Register (USIAR) ........................................ 11-12

11.4 Event Counting............................................................................................................ 11-12

11.5 Event Selection ............................................................................................................ 11-13

11.5.1 PMC1 Events........................................................................................................... 11-14

11.5.2 PMC2 Events........................................................................................................... 11-19

11.5.3 PMC3 Events........................................................................................................... 11-23

11.5.4 PMC4 Events........................................................................................................... 11-26

11.5.5 PMC5 Events........................................................................................................... 11-28

11.5.6 PMC6 Events........................................................................................................... 11-29

Appendix A

MPC7450 Instruction Set Listings

A.1 Instructions Sorted by Mnemonic (Decimal and Hexadecimal)..................................... A-1

A.2 Instructions Sorted by Primary and Secondary Opcodes (Decimal and

Hexadecimal)........................................................................................................... 12-13

A.3 Instructions Sorted by Mnemonic (Binary) .................................................................. A-24

A.4 Instructions Sorted by Opcode (Binary)....................................................................... A-35

A.5 Instructions Grouped by Functional Categories ........................................................... A-46

A.6 Instructions Sorted by Form ......................................................................................... A-61

A.7 Instruction Set Legend.................................................................................................. A-76

Appendix B

Instructions Not Implemented

Appendix C

Special-Purpose Registers

Appendix D

Revision History

Glossary

Index

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