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MPC603e RISC Microprocessor

User’s Manual

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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor pro ducts are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

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Overview

Programming Model

Instruction and Data Cache Operation

Exceptions

Memory Management

Instruction Timing

Signal Descriptio ns

System Interface Operation

Power Management

1 2 3 4 5 6 7 8 9

emiconduct

eescale S Fr

PowerPC Instruction Set Listings

Instructions Not Implemented

Revision History

Glossary of Terms and Abbrev iations

Index

A B C

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IND

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1 2 3 4

4 5 6 7 8 9

Overview Programming Model Instruction and Data Cache Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Power Management

emiconduct

eescale S Fr

GLO

IND

A B C

PowerPC Instruction Set Listings Instructions Not Implemented Revision History

Glossary of Terms and Abbrev iations Index

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Contents

Paragraph

Section Number Title

Number Title

About This Book

Chapter 1

Overview

1.1 Overview.............................................................................................................. 1-1

1.1.1 Features ........................................................................................................... 1-3

1.1.2 System Design and Programming Considerations...........................................1-6

1.1.2.1 Hardware Features.......................................................................................1-6

1.1.2.1.1 Replacement of XATS

1.1.2.1.2 Addition of Half-Clock Bus Multipliers.................................................. 1-7

1.1.2.2 Software Features ........................................................................................1-7

1.1.2.2.1 16-Kbyte Instruction and Data Caches.................................................... 1-7

1.1.2.2.2 Clock Configuration Available in HID1 Register ................................... 1-7

1.1.2.2.3 Performance Enhancements .................................................................... 1-7

1.1.3 Instruction Unit................................................................................................ 1-8

1.1.3.1 Instruction Queue and Dispatch Unit .......................................................... 1-8

1.1.3.2 Branch Processing Unit (BPU).................................................................... 1-9

1.1.4 Independent Execution Units...........................................................................1-9

1.1.4.1 Integer Unit (IU).......................................................................................... 1-9

1.1.4.2 Floating-Point Unit (FPU)......................................................................... 1-10

1.1.4.3 Load/Store Unit (LSU).............................................................................. 1-10

1.1.4.4 System Register Unit (SRU)...................................................................... 1-10

1.1.4.5 Completion Unit ........................................................................................ 1-11

1.1.5 Memory Subsystem Support.......................................................................... 1-11

1.1.5.1 Memory Management Units (MMUs)....................................................... 1-11

1.1.5.2 Cache Units................................................................................................ 1-12

1.1.6 Processor Bus Interface ................................................................................. 1-13

1.1.7 System Support Functions............................................................................. 1-14

1.1.7.1 Power Management ................................................................................... 1-14

1.1.7.2 Time Base/Decrementer ............................................................................1-15

1.1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface.................................................. 1-15

1.1.7.4 Clock Multiplier.........................................................................................1-15

1.2 PowerPC Architecture Implementation............................................................. 1-15

Signal by CSE1 Signal....................................... 1-6

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1.3 Implementation-Specific Information................................................................ 1-16

1.3.1 Programming Model...................................................................................... 1-17

1.3.1.1 Processor Version Register (PVR)............................................................. 1-17

1.3.1.2 Hardware Implementation Register 0 (HID0)........................................... 1-17

1.3.1.3 General-Purpose Registers (GPRs)............................................................ 1-19

1.3.1.4 Floating-Point Registers (FPRs)................................................................ 1-19

1.3.1.5 Condition Register (CR)............................................................................ 1-19

1.3.1.6 Floating-Point Status and Control Register (FPSCR) ...............................1-19

1.3.1.7 Machine State Register (MSR).................................................................. 1-20

1.3.1.8 Segment Registers (SRs) ...........................................................................1-20

1.3.1.9 Special-Purpose Registers (SPRs)............................................................. 1-20

1.3.1.9.1 User-Level SPRs.................................................................................... 1-20

1.3.1.9.2 Supervisor-Level SPRs..........................................................................1-21

1.3.2 Instruction Set and Addressing Modes.......................................................... 1-22

1.3.2.1 PowerPC Instruction Set and Addressing Modes...................................... 1-22

1.3.2.2 Implementation-Specific Instruction Set................................................... 1-24

1.3.3 Cache Implementation................................................................................... 1-24

1.3.3.1 PowerPC Cache Characteristics ................................................................ 1-24

1.3.3.2 Implementation-Specific Cache Implementation...................................... 1-24

1.3.4 Exception Model............................................................................................1-26

1.3.4.1 PowerPC Exception Model........................................................................1-26

1.3.4.2 Implementation-Specific Exception Model............................................... 1-28

1.3.5 Memory Management....................................................................................1-30

1.3.5.1 PowerPC Memory Management................................................................ 1-30

1.3.5.2 Implementation-Specific Memory Management....................................... 1-31

1.3.6 Instruction Timing ......................................................................................... 1-32

1.3.7 System Interface ............................................................................................ 1-33

1.3.7.1 Memory Accesses...................................................................................... 1-34

1.3.7.2 Signals........................................................................................................ 1-35

1.3.7.3 Signal Configuration.................................................................................. 1-36

Page

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2.1 Register Set.......................................................................................................... 2-1

2.1.1 PowerPC Register Set......................................................................................2-2

2.1.2 Implementation-Specific Registers..................................................................2-6

2.1.2.1 Hardware Implementation Registers (HID0 and HID1).............................. 2-6

2.1.2.2 Data and Instruction TLB Miss Address Registers

(DMISS and IMISS).............................................................................. 2-10

2.1.2.3 Data and Instruction TLB Compare Registers (DCMP and ICMP).......... 2-10

MPC603e RISC Microprocessor User’s Manual

Chapter 2

Programming Model

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2.1.2.4 Primary and Secondary Hash Address Registers

(HASH1 and HASH2)........................................................................... 2-11

2.1.2.5 Required Physical Address Register (RPA)............................................... 2-12

2.1.2.6 Instruction Address Breakpoint Register (IABR)...................................... 2-12

2.2 Operand Conventions ........................................................................................ 2-13

2.2.1 Floating-Point Execution Models—UISA..................................................... 2-13

2.2.2 Data Organization in Memory and Data Transfers........................................ 2-14

2.2.3 Alignment and Misaligned Accesses............................................................. 2-14

2.2.4 Floating-Point Operands................................................................................ 2-15

2.2.5 Effect of Operand Placement on Performance .............................................. 2-15

2.3 Instruction Set Summary ................................................................................... 2-15

2.3.1 Classes of Instructions................................................................................... 2-17

2.3.1.1 Definition of Boundedly Undefined.......................................................... 2-17

2.3.1.2 Defined Instruction Class .......................................................................... 2-17

2.3.1.3 Illegal Instruction Class............................................................................. 2-18

2.3.1.4 Reserved Instruction Class ........................................................................ 2-19

2.3.2 Addressing Modes .........................................................................................2-19

2.3.2.1 Memory Addressing ..................................................................................2-19

2.3.2.2 Memory Operands ..................................................................................... 2-19

2.3.2.3 Effective Address Calculation................................................................... 2-20

2.3.2.4 Synchronization ........................................................................................ 2-20

2.3.2.4.1 Context Synchronization .......................................................................2-21

2.3.2.4.2 Execution Synchronization....................................................................2-21

2.3.2.4.3 Instruction-Related Exceptions ............................................................. 2-21

2.3.3 Instruction Set Overview............................................................................... 2-22

2.3.4 PowerPC UISA Instructions..........................................................................2-22

2.3.4.1 Integer Instructions.................................................................................... 2-22

2.3.4.1.1 Integer Arithmetic Instructions.............................................................. 2-23

2.3.4.1.2 Integer Compare Instructions ................................................................2-24

2.3.4.1.3 Integer Logical Instructions................................................................... 2-24

2.3.4.1.4 Integer Rotate and Shift Instructions..................................................... 2-25

2.3.4.2 Floating-Point Instructions ........................................................................ 2-26

2.3.4.2.1 Floating-Point Arithmetic Instructions.................................................. 2-26

2.3.4.2.2 Floating-Point Multiply-Add Instructions............................................. 2-27

2.3.4.2.3 Floating-Point Rounding and Conversion Instructions......................... 2-28

2.3.4.2.4 Floating-Point Compare Instructions..................................................... 2-28

2.3.4.2.5 Floating-Point Status and Control Register Instructions....................... 2-28

2.3.4.2.6 Floating-Point Move Instructions.......................................................... 2-29

2.3.4.3 Load and Store Instructions....................................................................... 2-29

2.3.4.3.1 Self-Modifying Code ............................................................................ 2-30

2.3.4.3.2 Integer Load and Store Address Generation.......................................... 2-30

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2.3.4.3.3 Register Indirect Integer Load Instructions........................................... 2-30

2.3.4.3.4 Integer Store Instructions....................................................................... 2-31

2.3.4.3.5 Integer Load and Store with Byte-Reverse Instructions........................2-32

2.3.4.3.6 Integer Load and Store Multiple Instructions........................................ 2-32

2.3.4.3.7 Integer Load and Store String Instructions............................................ 2-33

2.3.4.3.8 Floating-Point Load and Store Address Generation..............................2-34

2.3.4.3.9 Floating-Point Load Instructions........................................................... 2-34

2.3.4.3.10 Floating-Point Store Instructions........................................................... 2-35

2.3.4.4 Branch and Flow Control Instructions....................................................... 2-36

2.3.4.4.1 Branch Instruction Address Calculation................................................ 2-36

2.3.4.4.2 Branch Instructions................................................................................2-37

2.3.4.4.3 Condition Register Logical Instructions................................................ 2-37

2.3.4.5 Trap Instructions........................................................................................ 2-38

2.3.4.6 Processor Control Instructions................................................................... 2-38

2.3.4.6.1 Move To/From Condition Register Instructions....................................2-38

2.3.4.7 Memory Synchronization Instructions—UISA......................................... 2-38

2.3.5 PowerPC VEA Instructions........................................................................... 2-40

2.3.5.1 Processor Control Instructions................................................................... 2-40

2.3.5.2 Memory Synchronization Instructions—VEA.......................................... 2-41

2.3.5.3 Memory Control Instructions—VEA........................................................ 2-41

2.3.5.4 External Control Instructions..................................................................... 2-43

2.3.6 PowerPC OEA Instructions........................................................................... 2-43

2.3.6.1 System Linkage Instructions...................................................................... 2-43

2.3.6.2 Processor Control Instructions—OEA ...................................................... 2-44

2.3.6.2.1 Move To/From Machine State Register Instructions.............................2-44

2.3.6.2.2 Move To/From Special-Purpose Register Instructions..........................2-44

2.3.6.3 Memory Control Instructions—OEA........................................................ 2-45

2.3.6.3.1 Supervisor-Level Cache Management Instruction ................................ 2-45

2.3.6.3.2 Segment Register Manipulation Instructions ........................................ 2-46

2.3.6.3.3 Translation Lookaside Buffer Management Instructions ...................... 2-46

2.3.7 Recommended Simplified Mnemonics.......................................................... 2-47

2.3.8 Implementation-Specific Instructions............................................................2-47

Page

Number

Chapter 3

Instruction and Data Cache Operation

3.1 Instruction Cache Organization and Control ....................................................... 3-3

3.1.1 Instruction Cache Organization....................................................................... 3-3

3.1.2 Instruction Cache Fill Operations.................................................................... 3-4

3.1.3 Instruction Cache Control................................................................................ 3-4

3.1.3.1 Instruction Cache Invalidation..................................................................... 3-4

3.1.3.2 Instruction Cache Disabling ........................................................................ 3-4

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3.1.3.3 Instruction Cache Locking........................................................................... 3-5

3.2 Data Cache Organization and Control................................................................. 3-5

3.2.1 Data Cache Organization................................................................................. 3-5

3.2.2 Data Cache Fill Operations..............................................................................3-6

3.2.3 Data Cache Control.......................................................................................... 3-6

3.2.3.1 Data Cache Invalidation .............................................................................. 3-6

3.2.3.2 Data Cache Disabling ..................................................................................3-7

3.2.3.3 Data Cache Locking .................................................................................... 3-7

3.2.3.4 Data Cache Operations and Address Broadcasts......................................... 3-7

3.2.4 Data Cache Touch Load Support..................................................................... 3-8

3.3 Basic Data Cache Operations .............................................................................. 3-8

3.3.1 Data Cache Fill ................................................................................................3-8

3.3.2 Data Cache Cast-Out Operation ...................................................................... 3-8

3.3.3 Cache Block Push Operation........................................................................... 3-9

3.4 Data Cache Transactions on Bus .........................................................................3-9

3.4.1 Single-Beat Transactions................................................................................. 3-9

3.4.2 Burst Transactions ........................................................................................... 3-9

3.4.3 Access to Direct-Store Segments................................................................... 3-10

3.5 Memory Management/Cache Access Mode Bits—W, I, M, and G................... 3-10

3.5.1 Write-Through Attribute (W) ........................................................................ 3-11

3.5.2 Caching-Inhibited Attribute (I)...................................................................... 3-12

3.5.3 Memory Coherency Attribute (M)................................................................. 3-12

3.5.4 Guarded Attribute (G).................................................................................... 3-13

3.5.5 W, I, and M Bit Combinations....................................................................... 3-13

3.5.5.1 Out-of-Order Execution and Guarded Memory ........................................ 3-14

3.5.5.2 Effects of Out-of-Order Data Accesses..................................................... 3-14

3.5.5.3 Effects of Out-of-Order Instruction Fetches.............................................. 3-15

3.6 Cache Coherency—MEI Protocol .....................................................................3-15

3.6.1 MEI State Definitions.................................................................................... 3-16

3.6.2 MEI State Diagram........................................................................................ 3-16

3.6.3 MEI Hardware Considerations ......................................................................3-17

3.6.4 Coherency Precautions .................................................................................. 3-19

3.6.4.1 Coherency in Single-Processor Systems ................................................... 3-19

3.6.5 Load and Store Coherency Summary............................................................ 3-19

3.6.6 Atomic Memory References.......................................................................... 3-20

3.6.7 Cache Reaction to Specific Bus Operations.................................................. 3-20

3.6.8 Operations Causing ARTRY Assertion ......................................................... 3-21

3.6.9 Enveloped High-Priority Cache Block Push Operation ................................ 3-22

3.7 Cache Control Instructions ................................................................................3-22

3.7.1 Data Cache Block Invalidate (dcbi) Instruction............................................ 3-24

3.7.2 Data Cache Block Touch (dcbt) Instruction.................................................. 3-24

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3.7.3 Data Cache Block Touch for Store (dcbtst) Instruction................................ 3-24

3.7.4 Data Cache Block Clear to Zero (dcbz) Instruction...................................... 3-24

3.7.5 Data Cache Block Store (dcbst) Instruction.................................................. 3-25

3.7.6 Data Cache Block Flush (dcbf) Instruction...................................................3-25

3.7.7 Enforce In-Order Execution of I/O Instruction (eieio) ..................................3-25

3.7.8 Instruction Cache Block Invalidate (icbi) Instruction ...................................3-26

3.7.9 Instruction Synchronize (isync) Instruction ..................................................3-26

3.8 Bus Operations Caused by Cache Control Instructions.....................................3-26

3.9 Bus Interface......................................................................................................3-27

3.10 MEI State Transactions......................................................................................3-28

Chapter 4

Exceptions

4.1 Exception Classes ................................................................................................ 4-2

4.1.1 Exception Priorities..........................................................................................4-6

4.1.2 Summary of Front-End Exception Handling................................................... 4-8

4.2 Exception Processing........................................................................................... 4-9

4.2.1 Exception Processing Registers....................................................................... 4-9

4.2.1.1 SRR0 and SRR1 Bit Settings....................................................................... 4-9

4.2.1.2 MSR Bit Settings....................................................................................... 4-11

4.2.2 Enabling and Disabling Exceptions............................................................... 4-13

4.2.3 Steps for Exception Processing...................................................................... 4-13

4.2.4 Setting MSR[RI]............................................................................................ 4-14

4.2.5 Returning from an Exception Handler........................................................... 4-14

4.3 Process Switching.............................................................................................. 4-15

4.4 Exception Latencies........................................................................................... 4-15

4.5 Exception Definitions ........................................................................................ 4-16

4.5.1 Reset Exceptions (0x00100).......................................................................... 4-17

4.5.1.1 Hard Reset and Power-On Reset ...............................................................4-17

4.5.1.2 Soft Reset...................................................................................................4-18

4.5.2 Machine Check Exception (0x00200) ...........................................................4-19

4.5.2.1 Machine Check Exception Enabled (MSR[ME] = 1)................................ 4-20

4.5.2.2 Checkstop State (MSR[ME] = 0) ..............................................................4-20

4.5.3 DSI Exception (0x00300).............................................................................. 4-21

4.5.4 ISI Exception (0x00400)................................................................................ 4-23

4.5.5 External Interrupt (0x00500)......................................................................... 4-23

4.5.6 Alignment Exception (0x00600) ...................................................................4-24

4.5.6.1 Integer Alignment Exceptions................................................................... 4-25

4.5.6.2 Load/Store Multiple Alignment Exceptions.............................................. 4-26

4.5.7 Program Exception (0x00700).......................................................................4-27

4.5.7.1 IEEE Floating-Point Exception Program Exceptions................................ 4-27

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4.5.7.2 Illegal, Reserved, and Unimplemented Instructions

Program Exceptions............................................................................... 4-28

4.5.8 Floating-Point Unavailable Exception (0x00800)......................................... 4-28

4.5.9 Decrementer Exception (0x00900)................................................................ 4-28

4.5.10 System Call Exception (0x00C00) ................................................................4-29

4.5.11 Trace Exception (0x00D00)........................................................................... 4-29

4.5.11.1 Single-Step Instruction Trace Mode.......................................................... 4-30

4.5.11.2 Branch Trace Mode ................................................................................... 4-30

4.5.12 Instruction TLB Miss Exception (0x01000).................................................. 4-30

4.5.13 Data TLB Miss on Load Exception (0x01100)..............................................4-31

4.5.14 Data TLB Miss on Store Exception (0x01200)............................................. 4-32

4.5.15 Instruction Address Breakpoint Exception (0x01300) ..................................4-32

4.5.16 System Management Interrupt (0x01400)..................................................... 4-34

Chapter 5

Memory Management

5.1 MMU Features..................................................................................................... 5-2

5.1.1 Memory Addressing ........................................................................................5-3

5.1.2 MMU Organization..........................................................................................5-3

5.1.3 Address Translation Mechanisms.................................................................... 5-8

5.1.4 Memory Protection Facilities.........................................................................5-10

5.1.5 Page History Information............................................................................... 5-11

5.1.6 General Flow of MMU Address Translation................................................. 5-11

5.1.6.1 Real Addressing Mode and Block Address Translation Selection............ 5-11

5.1.6.2 Page Address Translation Selection ..........................................................5-12

5.1.7 MMU Exceptions Summary..........................................................................5-14

5.1.8 MMU Instructions and Register Summary.................................................... 5-17

5.2 Real Addressing Mode....................................................................................... 5-19

5.3 Block Address Translation................................................................................. 5-20

5.4 Memory Segment Model ................................................................................... 5-20

5.4.1 Page History Recording................................................................................. 5-21

5.4.1.1 Referenced Bit ........................................................................................... 5-22

5.4.1.2 Changed Bit............................................................................................... 5-22

5.4.1.3 Scenarios for Referenced and Changed Bit Recording ............................. 5-23

5.4.2 Page Memory Protection ............................................................................... 5-24

5.4.3 TLB Description............................................................................................ 5-24

5.4.3.1 TLB Organization...................................................................................... 5-25

5.4.3.2 TLB Entry Invalidation.............................................................................. 5-26

5.4.4 Page Address Translation Summary.............................................................. 5-27

5.5 Page Table Search Operation............................................................................. 5-27

5.5.1 Page Table Search Operation—Conceptual Flow ......................................... 5-27

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5.5.2 Implementation-Specific Table Search Operation......................................... 5-31

5.5.2.1 Resources for Table Search Operations..................................................... 5-31

5.5.2.1.1 Data and Instruction TLB Miss Address Registers

(DMISS and IMISS)..........................................................................5-33

5.5.2.1.2 Data and Instruction TLB Compare Registers (DCMP and ICMP)...... 5-34

5.5.2.1.3 Primary and Secondary Hash Address Registers

(HASH1 and HASH2)....................................................................... 5-34

5.5.2.1.4 Required Physical Address Register (RPA) .......................................... 5-35

5.5.2.2 Software Table Search Operation .............................................................. 5-36

5.5.2.2.1 Flow for Example Exception Handlers ................................................. 5-36

5.5.2.2.2 Code for Example Exception Handlers ................................................. 5-40

5.5.3 Page Table Updates........................................................................................5-47

5.5.4 Segment Register Updates............................................................................. 5-47

Chapter 6

Instruction Timing

6.1 Terminology and Conventions............................................................................. 6-1

6.2 Instruction Timing Overview............................................................................... 6-3

6.3 Timing Considerations......................................................................................... 6-7

6.3.1 General Instruction Flow................................................................................. 6-8

6.3.2 Instruction Fetch Timing................................................................................6-10

6.3.2.1 Cache Arbitration....................................................................................... 6-10

6.3.2.2 Cache Hit................................................................................................... 6-10

6.3.2.3 Cache Miss................................................................................................. 6-13

6.3.3 Instruction Dispatch and Completion Considerations................................... 6-15

6.3.3.1 Rename Register Operation....................................................................... 6-15

6.3.3.2 Instruction Serialization.............................................................................6-16

6.3.3.3 Execution Unit Considerations.................................................................. 6-17

6.4 Execution Unit Timings.....................................................................................6-17

6.4.1 Branch Processing Unit Execution Timing....................................................6-17

6.4.1.1 Branch Folding ..........................................................................................6-17

6.4.1.2 Static Branch Prediction............................................................................ 6-18

6.4.1.2.1 Predicted Branch Timing Examples...................................................... 6-19

6.4.2 Integer Unit Execution Timing...................................................................... 6-21

6.4.3 Floating-Point Unit Execution Timing.......................................................... 6-21

6.4.4 Load/Store Unit Execution Timing................................................................6-22

6.4.5 System Register Unit Execution Timing....................................................... 6-22

6.5 Memory Performance Considerations ...............................................................6-22

6.5.1 Copy-Back Mode........................................................................................... 6-23

6.5.2 Write-Through Mode..................................................................................... 6-23

6.5.3 Cache-Inhibited Accesses.............................................................................. 6-23

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6.6 Instruction Scheduling Guidelines.....................................................................6-24

6.6.1 Branch, Dispatch, and Completion Unit Resource Requirements.................6-25

6.6.1.1 Branch Resolution Resource Requirements ..............................................6-25

6.6.1.2 Dispatch Unit Resource Requirements...................................................... 6-25

6.6.1.3 Completion Unit Resource Requirements................................................. 6-26

6.7 Instruction Latency Summary............................................................................6-26

Chapter 7

Signal Descriptions

7.1 Signal Configuration............................................................................................7-2

7.2 Signal Descriptions.............................................................................................. 7-2

7.2.1 Address Bus Arbitration Signals......................................................................7-2

7.2.1.1 Bus Request (BR)—Output......................................................................... 7-3

7.2.1.2 Bus Grant (BG)—Input ...............................................................................7-4

7.2.1.3 Address Bus Busy (ABB)............................................................................ 7-4

7.2.1.3.1 Address Bus Busy (ABB

7.2.1.3.2 Address Bus Busy (ABB)—Input ...........................................................7-5

7.2.2 Address Transfer Start Signals.........................................................................7-5

7.2.2.1 Transfer Start (TS)....................................................................................... 7-6

7.2.2.1.1 Transfer Start (TS)—Output.................................................................... 7-6

7.2.2.1.2 Transfer Start (TS)—Input ......................................................................7-6

7.2.3 Address Transfer Signals................................................................................. 7-6

7.2.3.1 Address Bus (A[0:31])................................................................................. 7-6

7.2.3.1.1 Address Bus (A[0:31])—Output ............................................................. 7-7

7.2.3.1.2 Address Bus (A[0:31])—Input................................................................ 7-7

7.2.3.2 Address Bus Parity (AP[0:3])...................................................................... 7-7

7.2.3.2.1 Address Bus Parity (AP[0:3])—Output................................................... 7-7

7.2.3.2.2 Address Bus Parity (AP[0:3])—Input .....................................................7-8

7.2.3.3 Address Parity Error (APE)—Output.......................................................... 7-8

7.2.4 Address Transfer Attribute Signals.................................................................. 7-8

7.2.4.1 Transfer Type (TT[0:4])............................................................................... 7-9

7.2.4.1.1 Transfer Type (TT[0:4])—Output ........................................................... 7-9

7.2.4.1.2 Transfer Type (TT[0:4])—Input.............................................................. 7-9

7.2.4.2 Transfer Size (TSIZ[0:2])—Output........................................................... 7-12

7.2.4.3 Transfer Burst (TBST)...............................................................................7-12

7.2.4.3.1 Transfer Burst (TBST)—Output............................................................7-12

7.2.4.3.2 Transfer Burst (TBST)—Input.............................................................. 7-13

7.2.4.4 Transfer Code (TC[0:1])—Output............................................................. 7-13

7.2.4.5 Cache Inhibit (CI)—Output....................................................................... 7-13

7.2.4.6 Write-Through (WT)—Output.................................................................. 7-14

7.2.4.7 Global (GBL).............................................................................................7-14

)—Output......................................................... 7-5

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7.2.4.7.1 Global (GBL)—Output.......................................................................... 7-14

7.2.4.7.2 Global (GBL

7.2.4.8 Cache Set Entry (CSE[0:1])—Output ....................................................... 7-14

7.2.5 Address Transfer Termination Signals........................................................... 7-15

7.2.5.1 Address Acknowledge (AACK)—Input.................................................... 7-15

7.2.5.2 Address Retry (ARTRY

7.2.5.2.1 Address Retry (ARTRY

7.2.5.2.2 Address Retry (ARTRY

7.2.6 Data Bus Arbitration Signals......................................................................... 7-16

7.2.6.1 Data Bus Grant (DBG

7.2.6.2 Data Bus Write Only (DBWO

7.2.6.3 Data Bus Busy (DBB) ............................................................................... 7-18

7.2.6.3.1 Data Bus Busy (DBB)—Output............................................................ 7-18

7.2.6.3.2 Data Bus Busy (DBB)—Input............................................................... 7-18

7.2.7 Data Transfer Signals..................................................................................... 7-18

7.2.7.1 Data Bus (DH[0:31], DL[0:31]) ................................................................ 7-18

7.2.7.1.1 Data Bus (DH[0:31], DL[0:31])—Output............................................. 7-19

7.2.7.1.2 Data Bus (DH[0:31], DL[0:31])—Input................................................ 7-19

7.2.7.2 Data Bus Parity (DP[0:7]) ......................................................................... 7-19

7.2.7.2.1 Data Bus Parity (DP[0:7])—Output...................................................... 7-19

7.2.7.2.2 Data Bus Parity (DP[0:7])—Input......................................................... 7-20

7.2.7.3 Data Parity Error (DPE)—Output ............................................................. 7-20

7.2.7.4 Data Bus Disable (DBDIS)—Input........................................................... 7-21

7.2.8 Data Transfer Termination Signals................................................................ 7-21

7.2.8.1 Transfer Acknowledge (TA)—Input.......................................................... 7-21

7.2.8.2 Data Retry (DRTRY)—Input..................................................................... 7-22

7.2.8.3 Transfer Error Acknowledge (TEA

7.2.9 System Status Signals.................................................................................... 7-23

7.2.9.1 Interrupt (INT

7.2.9.2 System Management Interrupt (SMI

7.2.9.3 Machine Check Interrupt (MCP)—Input................................................... 7-24

7.2.9.4 Checkstop Input (CKSTP_IN)—Input...................................................... 7-24

7.2.9.5 Checkstop Output (CKSTP_OUT)—Output............................................. 7-24

7.2.9.6 Reset Signals.............................................................................................. 7-25

7.2.9.6.1 Hard Reset (HRESET)—Input.............................................................. 7-25

7.2.9.6.2 Soft Reset (SRESET)—Input................................................................ 7-25

7.2.9.7 Processor Status Signals............................................................................ 7-26

7.2.9.7.1 Quiescent Request (QREQ)................................................................... 7-26

7.2.9.7.2 Quiescent Acknowledge (QACK)......................................................... 7-26

7.2.9.7.3 Reservation (RSRV)—Output ............................................................... 7-27

7.2.9.7.4 Time Base Enable (TBEN)—Input .......................................................7-27

)—Input ............................................................................ 7-14

)............................................................................ 7-15

)—Output ........................................................7-15

)—Input........................................................... 7-16

)—Input.................................................................. 7-17

)—Input ..................................................... 7-17

)—Input .............................................7-22

)—Input............................................................................... 7-23

)—Input ........................................... 7-23

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7.2.9.7.5 TLBI Sync (TLBISYNC)...................................................................... 7-27

7.2.10 COP/Scan Interface........................................................................................ 7-27

7.2.11 Pipeline Tracking Support............................................................................. 7-28

7.2.12 Clock Signals.................................................................................................7-29

7.2.12.1 System Clock (SYSCLK)—Input.............................................................. 7-29

7.2.12.2 Test Clock (CLK_OUT)—Output............................................................. 7-30

7.2.12.3 PLL Configuration (PLL_CFG[0:3])—Input............................................ 7-30

7.2.13 Power and Ground Signals ............................................................................7-32

Chapter 8

System Interface Operation

8.1 Overview.............................................................................................................. 8-1

8.1.1 Operation of the Instruction and Data Caches................................................. 8-2

8.1.2 Operation of the System Interface................................................................... 8-4

8.1.2.1 Optional 32-Bit Data Bus Mode.................................................................. 8-5

8.1.3 Direct-Store Accesses...................................................................................... 8-6

8.2 Memory Access Protocol..................................................................................... 8-6

8.2.1 Arbitration Signals...........................................................................................8-7

8.2.2 Address Pipelining and Split-Bus Transactions............................................... 8-8

8.3 Address Bus Tenure............................................................................................. 8-9

8.3.1 Address Bus Arbitration ..................................................................................8-9

8.3.2 Address Transfer............................................................................................ 8-11

8.3.2.1 Address Bus Parity ....................................................................................8-12

8.3.2.2 Address Transfer Attribute Signals............................................................8-12

8.3.2.2.1 Transfer Type (TT[0:4]) Signals............................................................8-12

8.3.2.2.2 Transfer Size (TSIZ[0:2]) Signals......................................................... 8-13

8.3.2.3 Burst Ordering During Data Transfers ...................................................... 8-13

8.3.2.4 Effect of Alignment in Data Transfers (64-Bit Bus)................................. 8-14

8.3.2.5 Effect of Alignment in Data Transfers (32-Bit Bus)................................. 8-16

8.3.2.5.1 Alignment of External Control Instructions.......................................... 8-18

8.3.2.6 Transfer Code (TC[0:1]) Signals............................................................... 8-19

8.3.3 Address Transfer Termination ......................................................................8-19

8.4 Data Bus Te nure.................................................................................................8-21

8.4.1 Data Bus Arbitration...................................................................................... 8-21

8.4.1.1 Using the DBB Signal ...............................................................................8-22

8.4.2 Data Bus Write Only......................................................................................8-22

8.4.3 Data Transfer .................................................................................................8-23

8.4.4 Data Transfer Termination............................................................................. 8-24

8.4.4.1 Normal Single-Beat Termination...............................................................8-25

8.4.4.2 Normal Burst Termination......................................................................... 8-26

8.4.4.3 Data Transfer Termination Due to a Bus Error.......................................... 8-27

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8.4.5 Memory Coherency—MEI Protocol ............................................................. 8-28

8.5 Timing Examples............................................................................................... 8-30

8.6 Optional Bus Configurations............................................................................. 8-37

8.6.1 32-Bit Data Bus Mode................................................................................... 8-37

8.6.2 No-DRTRY

8.6.3 Reduced-Pinout Mode ................................................................................... 8-40

8.7 Interrupt, Checkstop, and Reset Signals............................................................ 8-40

8.7.1 External Interrupts .........................................................................................8-40

8.7.2 Checkstops..................................................................................................... 8-40

8.7.3 Reset Inputs....................................................................................................8-41

8.7.4 System Quiesce Control Signals.................................................................... 8-41

8.8 Processor State Signals...................................................................................... 8-41

8.8.1 Support for the lwarx/stwcx. Instruction Pair............................................... 8-41

8.8.2 TLBISYNC

8.9 IEEE 1149.1-Compliant Interface......................................................................8-42

8.9.1 IEEE 1149.1 Interface Description................................................................ 8-42

8.10 Using DBWO..................................................................................................... 8-43

Mode..........................................................................................8-39

Input ..........................................................................................8-42

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Chapter 9

Power Management

9.1 Overview.............................................................................................................. 9-1

9.2 Dynamic Power Management..............................................................................9-1

9.3 Programmable Power Modes............................................................................... 9-2

9.3.1 Power Management Modes ............................................................................. 9-3

9.3.1.1 Full-Power Mode with DPM Disabled........................................................ 9-3

9.3.1.2 Full-Power Mode with DPM Enabled......................................................... 9-3

9.3.1.3 Doze Mode................................................................................................... 9-3

9.3.1.4 Nap Mode ....................................................................................................9-4

9.3.1.5 Sleep Mode.................................................................................................. 9-5

9.3.2 Power Management Software Considerations................................................. 9-6

9.4 Example Code Sequence for Entering Processor Sleep Mode ............................9-6

Appendix A

PowerPC Instruction Set Listings

A.1 Instructions Sorted by Mnemonic....................................................................... A-1

A.2 Instructions Sorted by Opcode............................................................................ A-8

A.3 Instructions Grouped by Functional Categories ............................................... A-15

A.4 Instructions Sorted by Form ............................................................................. A-25

A.5 Instruction Set Legend...................................................................................... A-36

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Appendix B

Instructions Not Implemente d

Appendix C

Revision History

C.1 Revision Changes From Revision 2 to Revision 3..............................................C-1

C.2 Revision Changes From Revision 1 to Revision 2..............................................C-2

Glossary of Terms and Abbreviations

Index

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Figures

Figure Number Title

1-1 MPC603e Microprocessor Block Diagram................................................................... 1-2

1-2 Programming Model—Registers................................................................................ 1-18

1-3 Data Cache Organization............................................................................................ 1-25

1-4 System Interface ......................................................................................................... 1-34

1-5 Signal Groups ............................................................................................................. 1-37

2-1 Programming Model—Registers.................................................................................. 2-3

2-2 Hardware Implementation Register 0 (HID0) ..............................................................2-6

2-3 Hardware Implementation Register 1 (HID1) ............................................................2-10

2-4 DMISS and IMISS Registers...................................................................................... 2-10

2-5 DCMP and ICMP Registers........................................................................................ 2-11

2-6 HASH1 and HASH2 Registers...................................................................................2-11

2-7 Required Physical Address Register (RPA) ...............................................................2-12

2-8 Instruction Address Breakpoint Register (IABR)....................................................... 2-12

3-1 Instruction Cache Organization .................................................................................... 3-4

3-2 Data Cache Organization.............................................................................................. 3-6

3-3 Double-Word Address Ordering—Critical Double Word First ................................. 3-10

3-4 MEI Cache Coherency Protocol—State Diagram (WIM = 001)................................3-17

3-5 Bus Interface Address Buffers.................................................................................... 3-28

4-1 Machine Status Save/Restore Register 0 (SSR0) ......................................................... 4-9

4-2 Machine Status Save/Restore Register 1 (SSR1) ......................................................... 4-9

4-3 Machine State Register (MSR)...................................................................................4-11

5-1 MMU Conceptual Block Diagram—32-Bit Implementations...................................... 5-5

5-2 IMMU Block Diagram.................................................................................................. 5-6

5-3 DMMU Block Diagram................................................................................................ 5-7

5-4 Address Translation Types ...........................................................................................5-9

5-5 General Flow of Address Translation (Real Addressing Mode and Block)............... 5-12

5-6 General Flow of Page and Direct-Store Interface Address Translation ..................... 5-13

5-7 Segment Register and TLB Organization................................................................... 5-25

5-8 Page Address Translation Flow for 32-Bit Implementations—TLB Hit.................... 5-28

5-9 Primary Page Table Search—Conceptual Flow ......................................................... 5-30

5-10 Secondary Page Table Search Flow—Conceptual Flow............................................ 5-31

5-11 DMISS and IMISS Registers...................................................................................... 5-34

5-12 DCMP and ICMP Registers........................................................................................ 5-34

5-13 HASH1 and HASH2 Registers...................................................................................5-35

5-14 Required Physical Address (RPA) Register ...............................................................5-35

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5-15 Flow for Example Software Table Search Operation................................................. 5-37

5-16 Check and Set R and C Bit Flow................................................................................ 5-38

5-17 Page Fault Setup Flow................................................................................................ 5-39

5-18 Setup for Protection Violation Exceptions .................................................................5-40

6-1 Pipelined Execution Unit.............................................................................................. 6-4

6-2 Superscalar/Pipeline Diagram....................................................................................... 6-5

6-3 MPC603e Microprocessor Pipeline Stages................................................................... 6-7

6-4 Instruction Flow Diagram............................................................................................. 6-9

6-5 Instruction Timing—Cache Hit .................................................................................. 6-11

6-6 Instruction Timing—Cache Miss................................................................................ 6-14

6-7 Branch Instruction Timing..........................................................................................6-20

7-1 Signal Groups ............................................................................................................... 7-3

7-2 IEEE 1149.1-Compliant Boundary Scan Interface..................................................... 7-28

8-1 MPC603e Microprocessor Block Diagram................................................................... 8-3

8-2 Overlapping Tenures on the Bus for a Single-Beat Transfer........................................8-6

8-3 Address Bus Arbitration .............................................................................................8-10

8-4 Address Bus Arbitration Showing Bus Parking ......................................................... 8-10

8-5 Address Bus Transfer.................................................................................................. 8-12

8-6 Snooped Address Cycle with ARTRY........................................................................8-20

8-7 Data Bus Arbitration................................................................................................... 8-22

8-8 Normal Single-Beat Read Termination ......................................................................8-25

8-9 Normal Single-Beat Write Termination ..................................................................... 8-25

8-10 Normal Burst Transaction...........................................................................................8-26

8-11 Termination with DRTRY ..........................................................................................8-27

8-12 Read Burst with TA Wait States and DRTRY............................................................ 8-28

8-13 MEI Cache Coherency Protocol—State Diagram (WIM = 001)................................8-30

8-14 Fastest Single-Beat Reads........................................................................................... 8-31

8-15 Fastest Single-Beat Writes..........................................................................................8-32

8-16 Single-Beat Reads Showing Data-Delay Controls .....................................................8-33

8-17 Single-Beat Writes Showing Data-Delay Controls .................................................... 8-34

8-18 Burst Transfers with Data-Delay Controls .................................................................8-35

8-19 Use of Transfer Error Acknowledge (TEA) ...............................................................8-36

8-20 32-Bit Data Bus Transfer (Eight-Beat Burst) ............................................................. 8-38

8-21 32-Bit Data Bus Transfer (Two-Beat Burst with DRTRY)........................................ 8-38

8-22 DBWO Transaction ....................................................................................................8-43

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Tables

Table Number Title

i Acronyms and Abbreviated Terms........................................................................... xxxii

ii Terminology Conventions.........................................................................................xxxv

iii Instruction Field Conventions................................................................................. xxxvi

1-1 CSE[0:1] Signals ......................................................................................................... 1-7

1-2 Generated SRR1[KEY] Bit .........................................................................................1-8

1-3 Additional/Changed HID0 Bits................................................................................. 1-19

1-4 Exception Classifications ..........................................................................................1-28

1-5 Exceptions and Conditions........................................................................................ 1-28

2-1 MSR[POW] and MSR[TGPR] Bits............................................................................. 2-5

2-2 HID0 Bit Functions .....................................................................................................2-7

2-3 HID0[BCLK] and HID0[ECLK] CLK_OUT Configuration...................................... 2-9

2-4 HID1 Bit Settings...................................................................................................... 2-10

2-5 DCMP and ICMP Bit Settings .................................................................................. 2-11

2-6 HASH1 and HASH2 Bit Settings.............................................................................. 2-11

2-7 RPA Bit Settings........................................................................................................ 2-12

2-8 Instruction Address Breakpoint Register Bit Settings...............................................2-13

2-9 Memory Operands..................................................................................................... 2-14

2-10 Integer Arithmetic Instructions.................................................................................. 2-23

2-11 Integer Compare Instructions ....................................................................................2-24

2-12 Integer Logical Instructions.......................................................................................2-24

2-13 Integer Rotate Instructions ........................................................................................ 2-25

2-14 Integer Shift Instructions........................................................................................... 2-26

2-15 Floating-Point Arithmetic Instructions......................................................................2-27

2-16 Floating-Point Multiply-Add Instructions................................................................. 2-27

2-17 Floating-Point Rounding and Conversion Instructions............................................. 2-28

2-18 Floating-Point Compare Instructions ........................................................................ 2-28

2-20 Floating-Point Move Instructions..............................................................................2-29

2-21 Integer Load Instructions...........................................................................................2-31

2-22 Integer Store Instructions .......................................................................................... 2-31

2-23 Integer Load and Store with Byte-Reverse Instructions............................................ 2-32

2-24 Integer Load and Store Multiple Instructions............................................................ 2-33

2-25 Integer Load and Store String Instructions................................................................2-34

2-26 Floating-Point Load Instructions............................................................................... 2-35

2-27 Floating-Point Store Instructions............................................................................... 2-35

2-28 Branch Instructions....................................................................................................2-37

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2-29 Condition Register Logical Instructions.................................................................... 2-37

2-30 Trap Instructions........................................................................................................ 2-38

2-31 Move To/From Condition Register Instructions........................................................ 2-38

2-32 Memory Synchronization Instructions—UISA......................................................... 2-40

2-33 Move From Time Base Instruction............................................................................ 2-40

2-34 Memory Synchronization Instructions—VEA.......................................................... 2-41

2-35 User-Level Cache Instructions ..................................................................................2-42

2-36 External Control Instructions .................................................................................... 2-43

2-37 System Linkage Instructions .....................................................................................2-43

2-38 Move To/From Machine State Register Instructions................................................. 2-44

2-39 Move To/From Special-Purpose Register Instructions.............................................. 2-44

2-40 Implementation-Specific SPR Encodings (mfspr) ................................................... 2-44

2-41 Segment Register Manipulation Instructions ............................................................2-46

2-42 Translation Lookaside Buffer Management Instructions .......................................... 2-47

3-1 Combinations of W, I, and M Bits.............................................................................3-13

3-2 MEI State Definitions................................................................................................3-16

3-3 CSE[0:1] Signal Encoding ........................................................................................ 3-18

3-4 Memory Coherency Actions on Load Operations..................................................... 3-19

3-5 Memory Coherency Actions on Store Operations..................................................... 3-20

3-6 Response to Bus Transactions................................................................................... 3-20

3-7 Bus Operations Caused by Cache Control Instructions (WIM = 001)...................... 3-26

3-8 MEI State Transitions................................................................................................3-29

4-1 Exception Classifications ............................................................................................4-3

4-2 Exceptions and Conditions.......................................................................................... 4-4

4-3 Exception Priorities ..................................................................................................... 4-6

4-4 SRR1 Bit Settings for Machine Check Exceptions................................................... 4-10

4-5 SRR1 Bit Settings for Software Table Search Operations ........................................ 4-10

4-6 MSR Bit Settings....................................................................................................... 4-11

4-7 IEEE Floating-Point Exception Mode Bits ...............................................................4-13

4-8 MSR Setting Due to Exception .................................................................................4-16

4-9 Settings Caused by Hard Reset.................................................................................. 4-17

4-10 Soft Reset Exception—Register Settings.................................................................. 4-19

4-11 Machine Check Exception—Register Settings ......................................................... 4-20

4-12 DSI Exception—Register Settings ............................................................................ 4-21

4-13 External Interrupt—Register Settings .......................................................................4-24

4-14 Alignment Interrupt—Register Settings....................................................................4-25

4-15 Access Types ............................................................................................................. 4-26

4-16 Trace Exception—Register Settings.......................................................................... 4-30

4-17 Instruction and Data TLB Miss Exceptions—Register Settings............................... 4-31

4-18 Instruction Address Breakpoint Exception—Register Settings ................................ 4-32

4-19 Breakpoint Action for Multiple Modes Enabled for the Same Address.................... 4-33

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4-20 System Management Interrupt—Register Settings ................................................... 4-34

5-1 MMU Features Summary............................................................................................ 5-2

5-2 Access Protection Options for Pages.........................................................................5-10

5-3 Translation Exception Conditions............................................................................. 5-15

5-4 Other MMU Exception Conditions ........................................................................... 5-16

5-5 Instruction Summary—MMU Control...................................................................... 5-17

5-6 MMU Registers ......................................................................................................... 5-18

5-7 Table Search Operations to Update History Bits—TLB Hit Case ............................ 5-21

5-8 Model for Guaranteed R and C Bit Settings.............................................................. 5-24

5-9 Implementation-Specific Resources for Table Search Operations............................ 5-32

5-10 Implementation-Specific SRR1 Bits .........................................................................5-33

5-11 DCMP and ICMP Bit Settings .................................................................................. 5-34

5-12 HASH1 and HASH2 Bit Settings..............................................................................5-35

5-13 RPA Bit Settings........................................................................................................ 5-35

6-1 Branch Instructions.................................................................................................... 6-26

6-2 System Register Instructions..................................................................................... 6-27

6-3 Condition Register Logical Instructions.................................................................... 6-27

6-4 Integer Instructions.................................................................................................... 6-28

6-5 Floating-Point Instructions........................................................................................ 6-30

6-6 Load and Store Instructions.......................................................................................6-31

7-1 Transfer Encoding for the Bus Master.........................................................................7-9

7-2 Snoop Hit Response .................................................................................................. 7-10

7-3 Implementation-Specific Transfer Encoding............................................................. 7-11

7-4 Data Transfer Size..................................................................................................... 7-12

7-5 Encodings for TC[0:1] Signals.................................................................................. 7-13

7-6 Data Bus Lane Assignments...................................................................................... 7-19

7-7 DP[0:7] Signal Assignments .....................................................................................7-20

7-8 Pipeline Tracking Outputs......................................................................................... 7-28

7-9 CLK_OUT Signal Configuration .............................................................................. 7-30

7-10 PLL Configuration..................................................................................................... 7-31

8-1 Timing Diagram Legend..............................................................................................8-5

8-2 Transfer Size Signal Encodings................................................................................. 8-13

8-3 Burst Ordering—64-Bit Bus...................................................................................... 8-14

8-4 Burst Ordering—32-Bit Bus...................................................................................... 8-14

8-5 Aligned Data Transfers (64-Bit Bus).........................................................................8-15

8-6 Misaligned Data Transfers (4-Byte Examples)......................................................... 8-16

8-7 Aligned Data Transfers (32-Bit Bus Mode).............................................................. 8-17

8-8 Misaligned 32-Bit Data Bus Transfer (4-Byte Examples) ........................................ 8-18

8-9 Transfer Code Encoding............................................................................................ 8-19

8-10 CSE[0:1] Signals ....................................................................................................... 8-30

8-11 IEEE Interface Pin Descriptions................................................................................8-42

Page

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Tables

Table Number Title

9-1 MPC603e Programmable Power Modes .....................................................................9-3

A-1 Complete Instruction List Sorted by Mnemonic........................................................ A-1

A-2 Complete Instruction List Sorted by Opcode............................................................. A-8

A-3 Integer Arithmetic Instructions................................................................................ A-15

A-4 Integer Compare Instructions................................................................................... A-16

A-5 Integer Logical Instructions ..................................................................................... A-16

A-6 Integer Rotate Instructions....................................................................................... A-16

A-7 Integer Shift Instructions.......................................................................................... A-17

A-8 Floating-Point Arithmetic Instructions ....................................................................A-17

A-9 Floating-Point Multiply-Add Instructions ............................................................... A-18

A-10 Floating-Point Rounding and Conversion Instructions............................................ A-18

A-11 Floating-Point Compare Instructions....................................................................... A-18

A-12 Floating-Point Status and Control Register Instructions.......................................... A-18

A-13 Integer Load Instructions ......................................................................................... A-19

A-14 Integer Store Instructions......................................................................................... A-19

A-15 Integer Load and Store with Byte-Reverse Instructions.......................................... A-20

A-16 Integer Load and Store Multiple Instructions.......................................................... A-20

A-17 Integer Load and Store String Instructions .............................................................. A-20

A-18 Memory Synchronization Instructions..................................................................... A-21

A-19 Floating-Point Load Instructions ............................................................................. A-21

A-20 Floating-Point Store Instructions............................................................................. A-21

A-21 Floating-Point Move Instructions ............................................................................ A-22

A-22 Branch Instructions .................................................................................................. A-22

A-23 Condition Register Logical Instructions.................................................................. A-22

A-24 System Linkage Instructions.................................................................................... A-22

A-25 Trap Instructions ...................................................................................................... A-23

A-26 Processor Control Instructions................................................................................. A-23

A-27 Cache Management Instructions.............................................................................. A-23

A-28 Segment Register Manipulation Instructions........................................................... A-24

A-29 Lookaside Buffer Management Instructions............................................................ A-24

A-30 External Control Instructions................................................................................... A-24

A-31 I-Form ......................................................................................................................A-25

A-32 B-Form..................................................................................................................... A-25

A-33 SC-Form................................................................................................................... A-25

A-34 D-Form..................................................................................................................... A-25

A-35 DS-Form................................................................................................................... A-27

A-36 X-Form..................................................................................................................... A-27

A-37 XL-Form .................................................................................................................. A-31

A-38 XFX-Form................................................................................................................ A-32

A-39 XFL-Form................................................................................................................ A-32

A-40 XS-Form................................................................................................................... A-32

Page

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Tables

Table Number Title

A-41 XO-Form.................................................................................................................. A-33

A-42 A-Form..................................................................................................................... A-33

A-43 M-Form.................................................................................................................... A-34

A-44 MD-Form................................................................................................................. A-35

A-45 MDS-Form............................................................................................................... A-35

A-46 PowerPC Instruction Set Legend............................................................................. A-36

B-1 32-Bit Instructions Not Implemented by the MPC603e .............................................B-1

B-2 64-Bit Instructions Not Implemented by the MPC603e .............................................B-1

B-3 64-Bit SPR Encoding Not Implemented by the MPC603e.........................................B-2

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About This Book

The primary objective of this user’s manual is to define the functionality of the MPC603e microprocessor for use by software and hardware developers.

It is important to note that this book is to be used with the PowerPC Microprocessor

Family: The Programming Environments, referred to as the Programming Environments Manual. Contact your sales representative to obtain a copy. Because the PowerPC

architecture is designed to be flexible to support a broad range of processors, the Programming Envir onments Manual provides a general description of features common to PowerPC processors and indicates those features that are optional or that may be implemented differently in the design of each processor.

This document describes in detail the MPC603e feature s not defined by the architecture. This document and the Programming Environments Manual distinguish between the three levels, or programming environments, of the PowerPC architecture, which are as follows:

• User instruction set architecture (UISA)—The UISA defines the architecture level to which user-level software should conform. The UISA defines the base user-level instruction set, user-level registers, data types, memory conventions, and the memory and programming models seen by application programmers.

• Virtual environment architecture (VEA)—The VEA, which is the smallest component of the PowerPC architecture, defines additional user-level functionality that falls outside typical user-level software requirements. The VEA describes the memory model for an environment in which multiple processors or other devices can access external memory, and defines aspects of the cache model and cache control instructions from a user-level perspective. The resources defined by the VEA are particularly useful for optimizing memory accesses and managing resources in an environment in which other processors and devices can access external memory.

Implementations that conform to the VEA also conform to the UISA but may not necessarily adhere to the OEA.

• Operating environment architecture (OEA)—The OEA defines supervisor-level resources typically required by an operating system. The OEA defines the memory management model, supervisor-level registers, and exception model.

Implementations that conform to the OEA also conform to the UISA and VEA.

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Audience

Note that some resources are defined more generally at one level in the architecture and more specifically at another. For example, conditions that cause a floating-point exception are defined by the UISA, while the exception mechanism is defined by the OEA.

Because it is important to distinguish between the levels of the architecture to ensure compatibility across multiple platforms, those distinctions are shown clearly throughout this book.

For ease in reference, topics in this book are arranged to build on one another, beginning with a description and complete summary of MPC603e-specific reg isters and progres sing to more specialized topics such as MPC603e-specific details regarding the cache, exception, and memory management models. As such, chapters may inc lude information from multiple levels of the architectu re. For example, the discussion of the c ache model uses information from both the VEA and the OEA.

The PowerPC Architecture: A Specification for a New Family of RISC Processors defines the architecture from the perspective of the three programming environments and remains the defining document for the PowerPC architecture.

The information in this book is subject to change without notice, as described in the

disclaimers on the title page. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation. For updates to this document, refer to: http://www.freescale.com.

Audience

This manual is intended for system software and hardware developers and applications programmers who want to develop products using the MPC603e microprocessors. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of RISC processing, and details of the PowerPC architecture.

Organization

The following summary briefly describes the major sections of this manual:

• Chapter 1, “Overview,” is useful for readers who want a general understanding of the features and functions of the PowerPC architecture and the MPC603e. This chapter describes the flexible nature of the PowerPC architecture definition and provides an overview of how the PowerPC architecture defines the register set, operand conventions, addressing modes, instruction set, cache model, exception model, and memory management model.

• Chapter 2, “Programming Model,” provides a brief synopsis of the registers implemented on the MPC603e, operand conventions, an overview of the PowerPC addressing modes, and a list of the instructions implemented by the MPC603e. Instructions are organized by function.

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• Chapter 3, “Instruction and Data Cache Operation,” provides a discussion of the cache and memory model as implemented on the MPC603e.

• Chapter 4, “Exceptions,” describes the exception model defined in the OEA and the specific exception model implemented on the MPC603e.

• Chapter 5, “Memory Management,” describes MPC603e implementation of the memory management unit specified by the OEA.

• Chapter 6, “Instruction Timing,” provides information about latencies, interlocks, special situations, and various conditions to help make programming more efficient. This chapter is of special interest to software engineers and system designers.

• Chapter 7, “Signal Descriptions,” provides descriptions of individual signals of the MPC603e.

• Chapter 8, “System Interface Operation,” describes signal timings for various operations. It also provides information for interfacing to the MPC603e.

1.1 Overview

This section describes the details of the MPC603e, provides a block diagram showing the major functional units (see Figure 1-1), and briefly describes how these units interact. Any differences between the PID6-603e and PID7t-603e implementations are noted.

The MPC603e is a low-power implementation of this microprocessor family of re duced instruction set computing (RISC) microprocessors. The MPC603e implements the 32-bit portion of the PowerPC architecture, which defines 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.

The MPC603e is a superscalar processor that can issue and retire as many as three instructions per clock cycle. Instructions can execute out of program order for increased performance; however, the MPC603e makes completion appear sequential.

The MPC603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for MPC603e-based systems. Most integer instructions execute in one cl ock cycle. On the MPC603e, the F PU is pipelined so a single-precision multiply-add instruction can be issued and completed every clock cycle.

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64-Bit (2 Instructions)

System

Unit

Integer

Unit

XER

Completion

Unit

GPR File

GP Rename

Registers

Sequential

Fetcher

64-Bit

Instruction

Queue

Dispatch Unit

64-Bit

Load/Store

Unit

D MMU

32-Bit

64-Bit

64-Bit32-Bit

Branch

Processing

64-Bit

Instruction Unit

FPR File

FP Rename

Registers

Unit

CTR

CR LR

Floating-

Point Unit

FPSCR

I MMU

Power

Dissipation

Control

JTAG/COP

Interface

Time Base

Counter/

Decrementer

Clock

Multiplier

SRs

DTLB

1.1.1 Features

This section describes the major features of the MPC603e noting where the PID6-603e and PID7t-603e implementations differ:

• High-performance, superscalar microprocessor — As many as three instructions issued and retired per clock — As many as five instructions in execution per clock — Single-cycle execution for most instructions — Pipelined FPU for all single-precision and most double-precision operations

• Five independent execution units and two register files — BPU featuring static branch prediction — A 32-bit IU — Fully IEEE 754-compliant FPU for both single- and double-precision operations — LSU for data transfer between data cache and GPRs and FPRs — SRU that executes condition register (CR), special-purpose register (SPR), and

integer add/compare instructions

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Overview

— Thirty-two GPRs for integer operands — Thirty-two FPRs for single- or double-precision operands

• High instruction and data throughput — Zero-cycle branch capability (branch folding) — Programmable static branch prediction on unresolved conditional branches — Instruction fetch unit capable of fetching two instructions per clock from the

instruction cache — A six-entry instruction queue (IQ) that provides lookahead capability — Independent pipelines with feed-forwarding that reduces data dependencies in

hardware — 16-Kbyte data cache and 16-Kbyte instruction cache—four-way set-associative,

physically addressed, LRU replacement algorithm — Cache write-back or write-through operation programmable on a per page or per

block basis — BPU that performs CR lookahead operations — Address translation facilities for 4-Kbyte page size, variable block size, and

256-Mbyte segment size — A 64-entry, two-way set-associative ITLB and DTLB — Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte

blocks — Software table search operations and updates supported through fast trap

mechanism — 52-bit virtual address; 32-bit physical address

• Facilities for enhanced system performance — A 32- or 64-bit split-transaction external data bus with burst transfers — Support for one-level address pipelining and out-of-order bus transactions — Hardware support for misaligned little-endian accesses (PID7t-603e)

• Integrated power management — Low-power 2.5-volt and 3.3-volt designs — Internal processor/bus clock multiplier ratios as follows:

– 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1 (PID6-603e)

– 2/1, 2.5/1, 3/1, 3.5/1, 4/1, 4.5/1, 5/1, 5.5/1, and 6/1 (PID7t-603e) — Three power-saving modes: doze, nap, and sleep — Automatic dynamic power reduction when internal functional units are idle

• In-system testability and debugging features through JTAG boundary-scan capability

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Features specific to the PID7t-603e follow:

• Enhancements to the register set — The PID7t-603e adds two HID0 bits:

– The address bus enable (ABE) bit, HID0[28], gives the PID7t-603e

microprocessor the ability to broadcast dcbf, dcbi, and dcbst onto the 60x bus.

– The instruction fetch enable M (IFEM) bit, HID0[24], allows the PID7t-603e

to reflect the value of the M bit onto the 60x bus during instruction translation.

— The Run_N counter register (Run_N) has been extended from 16 to 32 bits

• Enhancements to cache implementation — The instruction cache is blocked only until the critical load completes (hit under

reloads allowed)

— The critical double word is simultaneously written to the cache and forwarded to

the requesting unit, thus minimizing stalls due to load delays.

— Provides for an optional data cache operation broadcast feature (enabled by

HID0[ABE]) that allows for correct system management using an external copy-back L2 cache.

Overview

— All of the cache control instructions (icbi, dcbi, dcbf, and dcbst, excluding

dcbz) require that HID0[ABE] be enabled in order to execute.

• Exceptions — The PID7t-603e now offers hardware support for misaligned little-endian

accesses. Little-endian load/store accesses that are not on a word boundary , with the exception of strings and multiples, generate exceptions under the same circumstances as big-endian accesses.

— The PID7t-603e removed misalignment support for eciwx and ecowx graphics

instructions.These instructions cause an alignment exception if the access is not on a word boundary.

• Bus clock—New bus multipliers of 4.5x, 5x, 5.5x, and 6x that are selected by the unused encodings of PLL_CFG[0:3]. Bus multipliers of 1x and 1.5x are not supported by PID7t-603e.

• Power management—Internal voltage supply changed from 3.3 volts to 2.5 volts. The core logic of the chip now uses a 2.5-volt supply.

• Instruction timing — The integer divide instructions, divwu[o][.] and divw[o][.], execute in 20 clock

cycles; execution of these instructions in the PID6-603e takes 37 clock cycles. — Support for single-cycle store — An adder/comparator added to system register unit that allows dispatch and

execution of multiple integer add and compare instructions on each cycle.

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Overview

Figure 1-1 provides a block diagram of the MPC603e that shows how the execution

units—IU, FPU, BPU, LSU, and SRU—operate independently and in parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip.

The MPC603e provides address translation and protection facilities, including an ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit. Translation of addresses for cache or external memory accesses are handled by the MMUs. Both units are discussed in more detail in Section 1.1.3, “Instruction Unit,” and Section 1.1.5.1, “Memory Management Units (MMUs).”

1.1.2 System Design and Programming Considerations

The MPC603e is built on the low-power dissipation, low cost, and the high performance attributes of the MPC603. It also provides the system designer additional capabilities through higher processor clock speeds (to 100 MHz), increases in cache size (16-Kbyte instruction and data caches) and set-associativity (four-way), and greater system clock flexibility. The following sections describe the differences between the MPC603 and MPC603e that affect the system designer and programmer already familiar with the operation of the MPC603.

The design enhancements to the MPC603e are described in the following sections as changes that can require a modification to the hardware or software configuration of a system designed for the MPC603.

1.1.2.1 Hardware Features

The following hardware features of the MPC603e may require modificatio ns to MPC603 systems.

1.1.2.1.1 Replacement of XATS

The MPC603e employs four-way set-associativity for both the instruction and data caches, in place of the two-way set-associativity used in the MPC603. This change requires the use of an additional cache set entry (CSE1) signal to indicate which member of the cache set is being loaded during a cache line fill. CSE1 on the MPC603e is in the same pin location as XATS

on the MPC603. Note that XATS is no longer needed by the MPC603e because

support for access to direct-store segments has been removed. Table 1-1 shows the CSE[0:1] signal encoding indicating the cache set element selected

during a cache load operation.

Signal by CSE1 Signal

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Table 1-1. CSE[0:1] Signals

CSE[0:1] Cache Set Element

00 Set 0 01 Set 1 10 Set 2

11 Set 3

Overview

1.1.2.1.2 Addition of Half-Clock Bus Multipliers

Some of the reserved clock configuration signal sett ings of the MPC603 are redefined to allow more flexible selection of higher internal and bus clock frequencies. The MPC603e provides programmable internal processor clock rates of 1x, 1.5x, 2x, 2.5x, 3x, 3.5x, and 4x multiples of the externally supplied clock frequency . For additional information, refer to the appropriate device-specific hardware specifications.

1.1.2.2 Software Features

The features of the MPC603e described in the following sections affect software originally written for the MPC603.

1.1.2.2.1 16-Kbyte Instruction and Data Caches

The MPC603e instruction and data caches are 16 Kbytes, twice the size of the MPC 603 caches. The increase in cache size may require modification of cache flush routines. The increase is also reflected in four-way set-associativity of both caches in place of the two-way set-associativity in the MPC603.

1.1.2.2.2 Clock Configuration Available in HID1 Register

HID1[0–3] provides software read-only access to the configuration of the PLL_CFG signals. HID1 is not implemented in the MPC603.

1.1.2.2.3 Performance Enhancements

The following enhancements improve performance without requiring changes to software (other than compiler optimization) or hardware designed for the MPC603:

• Support for single-cycle store

• Addition of adder/comparator in the SRU allows dispatch and execution of multiple integer add and compare instructions on each cycle.

• Addition of SRR1[KEY] to provide information about memory protection violations prior to page table search operations. This bit is set when the combination of the settings in the appropriate SR[Kx] and in the MSR[PR] bit indicate that when

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the PTE[PP] bits are either 00 or 01, a protection violation exists. If this is the case for a data write operation with a DTLB miss, the changed (C) bit in the page tables should not be updated (see Table 1-2). This reduces the time required to execute the page table search routine because the software no longer has to explicitly read both SR[Kx] and MSR[PR] to determine whether a protection violation exists before updating the C bit.

Table 1-2. Generated SRR1[KEY] Bit

Segment Register

[Ks, Kp]

0x 0 0 x0 1 0 1x 0 1 x1 1 1

Note: SRR1[KEY] indicates a protection violation if the PTE[pp] bits are 00 or 01.

MSR[PR]

SRR1[KEY] Generated on

DTLB Misses

1.1.3 Instruction Unit

As shown in Figure 1-1, the MPC603e instruction unit, containing a fetch unit, instruction queue, dispatch unit, and BPU, provides centralized control of instruction flow to the execution units. The instruction unit determines the address of the next instruction to be fetched based on information from the sequential fetcher and from the BPU.

The instruction unit fetches the instructions from the instruction cache into the instruction queue. The BPU receives branch instructions from the fetcher and uses static branch prediction to allow to fetching from a predicted instruction stream while a conditional branch is evaluated. The BPU folds out for unconditional branch instructions and conditional branch instructions unaffected by instructions in the execution pipeline.

Instructions issued beyond a predicted branch cannot complete execution until the branch is resolved, preserving the programming model of sequential execution. If any of these are branch instructions, they are decoded but not issue d. Instructions to be executed by the FPU, IU, LSU, and SRU are issued and allowed to progress up to the register write-back stage. Write-back is allowed when a correctly predicted branch is resolved, and execution continues along the predicted path.

If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.

1.1.3.1 Instruction Queue and Dispatch Unit

The instruction queue (IQ), shown in Figure 1-1, holds as many as six instructions and loads up to two instructions from the instruction unit during a single cycle. The instruction fetch unit continuously loads as many instructions as space in the IQ allows. Instruct ions

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are dispatched to their respective execution units from the dispatch unit at a maximum rate of two instructions per cycle. Dispatching is facilitated to the IU, FPU, LSU, and SRU by the provision of a reservation station at each unit. The dispatch unit performs source and destination register dependency checking, determines dispatch serializations, and inhi bits subsequent instruction dispatching as required.

For a more detailed overview of instruction dispatch, see Section 1.3.6, “Instruction Timing.”

Overview

1.1.3.2 Branch Processing Unit (BPU)

The BPU receives branch instructions from the fetch unit and performs CR lookahead operations on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.

The BPU uses a bit in the instruction encoding to predict the direction of th e conditional branch. Therefore, when an unresolved conditional branch instruction is encountered, the MPC603e fetches instructions from the predicted target stream until the conditional branch is resolved.

The BPU contains an adder to compute branch target addresses and three user-control registers—the link register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch target address for the Branch Conditional to Link Register (bclrx) instruction. The CTR contains the branch target address for the Branch Conditional to Count Register (bcctrx) instruction. The contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather than GPRs or FPRs, execution of branch instructions is largely independent from execution of integer and floating-point instructions.

1.1.4 Independent Execution Units

The PowerPC architecture’s support for independent execution units allows implementation of processors with out-of-order instruction execution. For example, because branch instructions do not depend on GPRs or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches.

The four other execution units and completion unit are described in the following sections.

1.1.4.1 Integer Unit (IU)

The IU executes all integer instructions. The IU executes one integer instruction at a time, performing computations with its arithmetic logic unit (ALU), multiplier, divider , and XER register. Most integer instructions are single-cy cle instructions. The 32 GPRs hold integer operands. Stalls due to contention for GPRs are minimized by the automatic allocation of

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Overview

rename registers. The MPC603e writes the contents of the rename registers to the appropriate GPR when integer instructions are retired by the completion unit.

1.1.4.2 Floating-Point Unit (FPU)

The FPU contains a single-precision multiply-add array and the floating-point status and control register (FPSCR). The multiply-add array allows the MPC603e to efficiently implement multiply and multiply-add operations. The FPU is pipelined so that single- and double-precision instructions can be issued back-to-back. The 32 FPRs are provided to support floating-point operations. Stalls due to contention for FPRs are minimized by the automatic allocation of rename registers. The MPC603e writes the contents of the re name registers to the appropriate FPR when floating-point instructions are retired by the completion unit.

The MPC603e supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero, and infinity) in hardware, eliminating the latency incurred by software

exception routines. (The term, ‘exception’ is also referred to as ‘interrupt’ in the architecture specification.)

1.1.4.3 Load/Store Unit (LSU)

The LSU executes all load and store instructions and provides the data transfer interface between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment, and provides sequencing for load/store string and multiple instructions.

Load and store instructions are issued and executed in program order; however, the memory accesses can occur out of order. Synchronizing instructions are provided to enforce strict ordering.

Cacheable loads, when free of data dependencies, can execute out of order with a maximum throughput of one per cycle and a two-cycle total latency. Data returned from the cache is held in a rename register until the completion logic commits the value to a GPR or FPR. Stores cannot be executed in a predicted manner and are held in the store queue until the completion logic signals that the store operation is to be completed to memory. The MPC603e executes store instructions with a maximum throughput of one per cycle and a three-cycle total latency. The time required to perform the actual load or store depends on whether the operation involves the cache, system memory, or an I/O device.

1.1.4.4 System Register Unit (SRU)

The SRU executes various system-level instructions, including condition register lo gical operations and move to/from special-purpose register instructions. It also executes integer add/compare instructions. In order to maintain system state, most instructions executed by the SRU are completion-serialized; that is, the instruction is held for execution in the SRU

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until all prior instructions issued have completed. Results from completion-serialized instructions executed by the SRU are not available or forwarded for subsequent instructions until the instruction completes.

1.1.4.5 Completion Unit

The completion unit tracks instructions in program order from dispatch through execution and then completes. Completing an instruction commits the MPC603e to any architectural register changes caused by that instruction. In-order completion ensures the correct architectural state when the MPC603e mus t recover from a mispredicted branch or any exception.

Instruction state and other information required for completion is kept in a five-entry FIFO completion queue. A single completion queue entry is allocated for each instruction once it enters the execution unit from the dispatch uni t. An available completion queue entry is a required resource for dispatch; if no completion entry is available, dispatch stalls. A maximum of two instructions per cycle are completed in order from the queue.

1.1.5 Memory Subsystem Support

The MPC603e provides both separate instruction and data caches and MMUs. The MPC603e also provides an efficient processor bus interface to facilitate access to main memory and other bus subsystems. The memory subsystem support functions are described in the following sections.

1.1.5.1 Memory Management Units (MMUs)

The MPC603e MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gigabytes

) of physical memory (referred to as real memory in t he archit ecture sp ecification) for instruction and data. The MMUs also control access privileges for these spaces on b lock and page granularities. Referenced and changed status is maintained by the processor for each page to assist implementation of a demand-paged virtual memory system. A key bit is implemented to provide information about memory protection violations prior to page table search operations.

The LSU calculates effective addresses (EAs) for data loads and stores, performs data alignment to and from cache memory , and provides the sequencing for load and store string and multiple word instructions. The instruction unit calculates effective addresses for instruction fetching.

After an EA is generated, its higher-order bits are translated by the appropriate MMU into physical address bits. The lower-order EA bits are the same on the physical address and form the index into the four-way set-associative tag array. After translating the address, the MMU passes the higher-order physical address bits to the cache and the cache lookup completes. For caching-inhibited accesses or accesses that miss in the cache, the

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Overview

untranslated lower-order address bits are concatenated with the translated higher-order address bits; the resulting 32-bit physical address is then used by the memory unit a nd the system interface to access external memory.

The MMU also directs the address translation and enforces the protection hierarchy programmed by the operating system in relation to the supervisor/user privilege level of the access and in relation to whether the access is a load or store.

For instruction fetches, the IMMU looks for the address in the ITLB and in the IBAT array. If an address hits both, the IBAT array translation is used. Data accesses cause a lookup in the DTLB and DBAT array. In most cases, the translation is in a TLB and the physical address bits are readily available to the on-chip cache. The DBAT also is chosen if the translation is in both a DBAT and TLB.

When the EA misses in the TLBs, the MPC603e provides hardware assistance for software to perform a search of the translation tables in memory. The hardware assist consists of the following features:

• Automatic storage of the missed effective address in IMISS and DMISS

• Automatic generation of the primary and secondary hashed real address of the page table entry group (P TEG), which are readable from the HASH1 and HASH2 register locations.

The HASH data is generated from the contents of the IMISS or DMISS register. The register that is selected depends on the miss (instruction or data) that was last acknowledged.

• Automatic generation of the first word of the page table entry (PTE) of the tables being searched

• A real page address (RPA) register that matches the format of the lower word of the PTE

• TLB access instructions (tlbli and tlbld) that are used to load an address translation into the instruction or data TLBs

• Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs. Shadow registers are used only for servicing a TLB miss.

See Section 1.3.5.2, “Implementation-Specific Memory Management,” for more information about memory management for the MPC603e.

1.1.5.2 Cache Units

The MPC603e provides independent 16-Kbyte, four-way set-associative instruction and data caches. The cache block is 32 bytes long. The caches adhere to a write-back policy, but the MPC603e allows control of cacheability, write policy, and memory coherency at the page and block levels. The caches use an LRU replacement policy.

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As shown in Figure 1-1, the caches provide a 64-bit interface to the instruction fetch unit and LSU. The surrounding logic selects, organizes, and forwards the requested information to the requesting unit. Write operations to the cache can be performed on a byte basis, and a complete read-modify-write operation to the cache can occur in each cycle.

The load/store and instruction fetch units provide the caches with the address of the data or instruction to be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.

Because the data cache tags are single-ported, simultaneous load or store and snoop accesses cause resource contention. Snoop accesses have the highest priority and are given first access to the tags, unless the sn oop access coin cides with a tag write; i n this case the snoop is retried and must rearbitrate for cache access. Loads or stores deferred due to snoop accesses are performed on the clock cycle following the snoop.

1.1.6 Processor Bus Interface

Because the caches are on-chip, write-back caches, the most common transactions are burst-read memory operations, burst-write memory operations, and single-beat (noncacheable or write-through) memory read and write operations. There can also be address-only operations, variants of the burst and single-beat operations, (for example, global memory operations that are snooped and atomic memory operations), and ad dress retry activity (for example, when a snooped read access hits a modified cache block).

Memory accesses can occur in single-beat (1–8 bytes) and fou r-beat burst (32 bytes) data transfers when the bus is configured as 64 bits, and in single-beat (1–4 bytes), tw o-beat (8 bytes), and eight-beat (32 bytes) data transfers when the bus is configured as 32 bits. The address and data buses operate independently to support pipelining and split transactions during memory accesses. The MPC603e can pipeline its own transactions to a depth of one level.

Access to the system interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership. This arbitration is flexible, allowing the MPC603e to be integrated into systems that implement various fairness and bus parking procedures to avoid arbitration overhead.

Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and multiple instructions, do not neces sarily complete in the order they begin—maximizing the efficiency of the bus without sacrificing coherency of the data. The MPC603e allows read operations to precede store operations (except w hen a dependency exists, or in cases where a noncacheable access is performed), and provides support for a write operation to proceed a previously queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data tenures of a read operation). B ecause the processor can dynamically optimize run-time ordering of load/store traffic, overall performance is improved.

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Overview

1.1.7 System Support Functions

The MPC603e implements several support functions that include power management, time base/decrementer registers for system timing tasks, an IEEE 1149.1 (JTAG)/common on-chip processor (COP) test interface, and a phase-locked loop (PLL) clock multiplier. These system support functions are described in the following sections.

1.1.7.1 Power Management

The MPC603e provides four power modes, selectable by setting the appropriate control bits in the machine state register (MSR) and hardware imp lementation register 0 (HID0). The four power modes are as follows:

• Full-power—This is the default power state of the MPC603e. The MPC603e is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution, or external hardware.

• Doze—All the functional units of the MPC603e are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, system management interrupt, decrementer exception, hard or soft reset, or machine check brings the MPC603e into the full-power state. The MPC603e in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles.

• Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The MPC603e returns to the full-power state upon receipt of an external asynchronous interrupt, system management interrupt, decrementer exception, hard or soft reset, or machine check input (MCP

) signal. A return to full-power state from a nap state takes only a

few processor clock cycles.

• Sleep—Sleep mode reduces power consumption to a minimum by disabling all internal functional units; then external system logic may disable the PLL and SYSCLK. Returning the MPC603e to the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt, system management interrupt, hard or soft reset, or MCP

signal after the

time required to relock the PLL.

The PID7t-603e implementation offers the following enhancements to the MPC603e family:

• Lower-power design

• 2.5-volt core and 3.3-volt I/O

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PowerPC Architecture Implementation

1.1.7.2 Time Base/Decrementer

The time base is a 64-bit register (accessed as two 32-bit registers) that is incremented once every four bus clock cycles; external control of the time base is provided through the time base enable (TBEN) signal. The decrementer is a 32-bit register that generates a decrementer interrupt exception after a programmable delay. The contents of the decrementer register are decremented once every four bus clock cycles, and the decrementer exception is generated as the count passes through zero.

1.1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface

The MPC603e provides IEEE 1149.1 and COP functions for facilitating board testing and chip debugging. The IEEE 1149.1 test interface provides a means for boundary-scan testing the MPC603e and the attached board. The COP function shares the IEEE 1149.1 test port, providing a means for executing test routines, and facilitating chip and software debugging.

1.1.7.4 Clock Multiplier

The internal clocking of the MPC603e is generated from and synchronized to the ex ternal clock signal, SYSCLK, by means of a voltage-controlled oscillator-based PLL. The PLL provides programmable internal processor clock rates of 1x, 1.5x, 2x, 2.5x, 3x, 3.5x, and 4x multiples of the externally supplied clock frequency. The bus clock is the same frequency and is synchronous with SYSCLK. The configuration of the PLL can be read by software from the hardware implementation register 1 (HID1).

1.2 PowerPC Architecture Implementation

The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can be measured in terms of which of the following levels of the architecture is implemented:

• User instruction set architecture (UISA)—Defines the base user-level instruction set, user-level registers, data types, floating-point exception model, memory models for a uniprocessor environment, and programming model for a uniprocessor environment.

• Virtual environment architecture (VEA)—Describes the memory model for a multiprocessor environment, defines cache control instructions, and describes other aspects of virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may not necessarily adhere to the OEA.

• Operating environment architecture (OEA)—Defines the memory management model, supervisor-level registers, synchronization requirements, and exception model. Implementations that conform to the OEA also adhere to the UISA and VEA.

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Implementation-Specific Information

The PowerPC architecture allows a wide range of designs for such features as cache and system interface implementations.

1.3 Implementation-Specific Informatio n

The PowerPC architecture is derived from the IBM POWER architecture (Performance Optimized with Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction execution and is scalea ble to take advantage of future technological gains.

This section describes the PowerPC architecture in general and specific details abo ut the implementation of the MPC603e as a low-power, 32-bit member of this family. The main topics addressed are as follows:

• Section 1.3.1, “Programming Model,” describes the registers for the operating environment architecture common among processors that implement the PowerPC architecture and describes the programming model. It also describes the additional registers that are unique to the MPC603e.

• Section 1.3.2, “Instruction Set and Addressing Modes,” describes the PowerPC instruction set and addressing modes for the OEA, and defines and describes the PowerPC instructions implemented in the MPC603e.

• Section 1.3.3, “Cache Implementation,” describes the cache model that is defined generally for processors that implement the PowerPC architecture by the VEA. It also provides specific details about the MPC603e cache implementation.

• Section 1.3.4, “Exception Model,” describes the exception model of the OEA and the differences in the MPC603e exception model.

• Section 1.3.5, “Memory Management,” describes generally the conventions for memory management among these processors. This section also describes the MPC603e implementation of the 32-bit PowerPC memory management specification.

• Section 1.3.6, “Instruction Timing,” provides a general description of the instruction timing provided by the superscalar, parallel execution supported by the PowerPC architecture and the MPC603e.

• Section 1.3.7, “System Interface,” describes the signals implemented on the MPC603e.

The MPC603e is a high-performance, superscalar microprocessor. The PowerPC architecture allows optimizing compilers to schedule instructions to maximize performance through efficient use of the PowerPC instruction set and register model. The multiple, independent execution units allow compilers to optimize instruction throughput. Compilers that take advantage of the flexibility of the PowerPC architecture can additionally optimize system performance.

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The following sections summarize the features of the MPC603e, including both those that are defined by the architecture and those that are unique to the various MPC603e implementations.

Specific features of the MPC603e are listed in Section 1.1.1, “Features.”

Implementation-Specific Information

1.3.1 Programming Model

The PowerPC architecture defines register-to-register operations for most computat ional instructions. Source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. The three-register instruction format allows specification of a target register distinct from the two-source operands. Load and store instructions transfer data between registers and memory.

The MPC603e has two levels of privilege—supervisor mode of operation (typically used by the operating system) and user mode of operation (used by the application software). The programming models incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers. The MPC603e microprocessor also has its own unique set of hardware implementation (HID) registers.

Having access to privileged instructions, registers, and other resources allows the operating system to control the application environment (p roviding virtual memory and protecting operating system and critical machine resources). Instruction s that control the state of the MPC603e, the address translation mechanism, and supervisor registers can be executed only when the processor is operating in supervisor mode.

Figure 1-2 shows all the MPC603e registers available at the user and supervisor level. The numbers to the right of the SPRs indicate the number that is used in the syntax of the instruction operands for the move to/from SPR instructions.

The following sections describe the PID7t-603e implementation-specific features as they apply to registers.

1.3.1.1 Processor Version Register (PVR)

The processor version number is 6 for the PID6-603e and 7 for the PID7t-603e. The processor revision level starts at 0x0100 and changes for each chip revision. The revision level is updated on all silicon revisions.

1.3.1.2 Hardware Implementation Register 0 (HID0)

PID7t-603e (designated by PVR level 0x0200) defines additional bits in the hardware implementation register 0 (HID0), a supervisor-level register that provides the means for enabling MPC603e checkstops and features, and allows software to read the configuration of the PLL configuration signals.

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Implementation-Specific Information

USER MODEL

Hardware Implementation

General-Purpose Registers

GPR0 GPR1

Registers

Instruction BAT Registers

GPR31

Floating-Point Registers

FPR0 FPR1

FPR31

Condition Register

IBAT0L

IBAT1U

IBAT1L

IBAT2U

IBAT2L

IBAT3U

IBAT3L

SDR1

SUPERVISOR MODEL

Configuration Registers

SPR 1008HID0 SPR 1009HID1

Machine State Register

MSR

Memory Management Registers

Data BAT Registers

SPR 528IBAT0U SPR 529 SPR 530 SPR 531 SPR 532 SPR 533 SPR 534 SPR 535

SPR 25SDR1

Processor Version Register

SPR 287PVR

Software Table Search Registers

SPR 536DBAT0U SPR 537DB AT0L SPR 538DBAT1U SPR 539DB AT1L SPR 540DBAT2U SPR 541DB AT2L SPR 542DBAT3U SPR 543DB AT3L

Segment Registers

SR0 SR1

SR15

SPR 976DMISS SPR 977DCM P SPR 978HASH1 SPR 979HASH2 SPR 980IMISS SPR 981ICMP SPR 982RPA

Floating-Point Status and Control Register

FPSCR

XER

SPR 1

Link Register

SPR 8

Data Address Register

DAR

SPRGs

SPRG1 SPRG2 SPRG3

Count Register

CTR

Time Base Facility

SPR 9

(For Reading)

TBL

TBU

These registers are MPC603e-specific (PID6-603e and PID7t-603e). They may not be supported by

TBR 268 TBR 269

Time Base Facility (For Writing)

TBU

Instruction Address Breakpoint Register

Exception Handling Registers

SPR 19

SPR 272SPRG0 SPR 273 SPR 274 SPR 275

Miscellaneous Registers

SPR 284TBL SPR 285

SPR 1010IABR

DSISR

SPR 18DSISR

Save and Restore Registers

SRR0 SRR1

SPR 26 SPR 27

Decrementer

DEC

SPR 22

External Address Register (Optional)

EAR

SPR 282

other processors of this family.

Figure 1-2. Programming Model—Registers

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Implementation-Specific Information

The HID0 bits with changed bit assignments are shown in Table 1-3. The HID0 bits that are

not shown here are implemented as shown in Secti on 2.1.2.1, “Hardware Implementation Registers (HID0 and HID1).”

Table 1-3. Additional/Changed HID0 Bits

Bits Description

24 Enable M bit on bus for instruction fetches (IFEM) (PID7t-603e only).

0 M bit disabled. Instruction fetches are treated as nonglobal on the bus. 1 Instruction fetches reflect the M bit from the WIM settings.

25–26 Reserved

28 Address broadcast enable. Controls whether certain address-only operations (such as cache operations)

are broadcast on the 60x bus. 0 Address-only operations affect only local caches and are not broadcast. 1 Address-only operations are broadcast on the 60x bus. Affected instructions are dcbi, dcbf, and dcbst. Note that these cache control instruction broadcasts are not snooped by the PID7t-603e. Refer to Section 1.3.3, “Cache Implementation.”

29–30 Reserved

1.3.1.3 General-Purpose Registers (GPRs)

The PowerPC architecture defines 32 user-level GPRs. These registers are either 32 bits wide in 32-bit microprocessors or 64 bits wide in 64-bit microprocessors. The GPRs serve as the data source or destination for all integer instructions.

1.3.1.4 Floating-Point Registers (FPRs)

The PowerPC architecture also defines 32 user-level, 64-bit FPRs. The FPRs serve as the data source or destination for floating-point instru ctions. These registers can contain data objects of either single- or double-precision floating-point formats.

1.3.1.5 Condition Register (CR)

The CR is a 32-bit user-level register that provides a mechanism for testing and branching. It consists of eight 4-bit fields that reflect the results o f certain operations, such as move, integer and floating-point comparisons, arithmetic, and logical operations.

1.3.1.6 Floating-Point Status and Control Register (FPSCR)

The user-level FPSCR contains all floating-point exception signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance with the IEEE 754 standard.

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Implementation-Specific Information

1.3.1.7 Machine State Register (MSR)

The MSR is a supervisor-level register that defines the state of the processor. The contents of this register are saved when an exception is taken and restored when the exception handling completes. The MPC603e implements the MSR as a 32-bit register.

1.3.1.8 Segment Registers (SRs)

For memory management, 32-bit processors implement sixteen 32-bit SRs. To speed access, the MPC603e implements the SRs as two arrays; a main array (for data memory accesses) and a shadow array (for instruction memory accesses). Loading a segment entry with the Move to Segment Register (mtsr) instruction loads both arrays.

1.3.1.9 Special-Purpose Registers (SPRs)

The OEA defines numerous SPRs that serve a variety of functions, such as providing controls, indicating status, configuring the processor, and performing special operations. During normal execution, a program can access the registers, as shown in Figure 1-2,

depending on the program’s access privilege (supervisor or user, determined by the privilege-level bit, MSR[PR]). Note that GPRs a nd FPRs are accessed through operands that are part of the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register (mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers are accessed both explicitly and implicitly.

In the MPC603e, all SPRs are 32 bits wide.

1.3.1.9.1 User-Level SPRs

The following MPC603e SPRs are accessible by user-level software:

• Link register (LR)—The LR can be used to provide the branch target address and to hold the return address after branch and link instructions. The LR is 32 bits wide in 32-bit implementations.

• Count register (CTR)—The CTR is decremented and tested automatically as a result of branch-and-count instructions. The CTR is 32 bits wide in 32-bit implementations.

• XER register—The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String W ord Indexed (lswx) or Store String W ord Indexed (stswx) instruction.

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1.3.1.9.2 Supervisor-Level SPRs

The MPC603e also contains SPRs that can be accessed only by supervisor-level software. These registers consist of the following:

• The DSISR defines the cause of data access and alignment exceptions.

• The data address register (DAR) holds the address of an access after an alignment or DSI exception.

• Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay.

• SDR1 specifies the page table format used in virtual-to-physical address translation for pages. (Note that physical address is referred to as real address in the architecture specification.)

• The machine status save/restore register 0 (SRR0) is used for saving the address of the instruction that caused the exception, and the address to return to when a Return from Interrupt (rfi) instruction is executed.

• The machine status save/restore register 1 (SRR1) is used to save machine status on exceptions and to restore machine status when an rfi instruction is executed.

• The SPRG0–SPRG3 registers are provided for operating system use.

• The external access register (EAR) controls access to the external control facility through the External Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions.

• The time base register (TB) is a 64-bit register that maintains the time of day and operates interval timers. It consists of two 32-bit fields—time base upper (TBU) and time base lower (TBL).

• The processor version register (PVR) is a read-only register that identifies the version (model) and revision level of the processor.

• Block address translation (BA T) arrays—The PowerPC architecture defines 16 BAT registers—four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs). See Figure 1-2 for a list of the SPR numbers for the BAT arrays.

The following supervisor-level SPRs are implementation-specific (not defined in the PowerPC architecture):

• DMISS and IMISS are read-only registers that are loaded automatically on an instruction or data TLB miss.

• HASH1 and HASH2 contain the physical addresses of the primary and secondary page table entry groups (PTEGs).

• ICMP and DCMP contain a duplicate of the first word in the page table entry (P TE) for which the table search is looking.

• The required physical address (RPA) register is loaded by the processor with the second word of the correct PTE during a page table search.

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Implementation-Specific Information

• The hardware implementation (HID0 and HID1) registers provide the means for enabling MPC603e checkstops and features, and allows software to read the configuration of the PLL configuration signals.

• The instruction address breakpoint register (IABR) is loaded with an instruction address that is compared to instruction addresses in the dispatch queue. When an address match occurs, an instruction address breakpoint exception is generated.

1.3.2 Instruction Set and Addressing Modes

The following sections describe the PowerPC instruction set and addressing modes in general.

1.3.2.1 PowerPC Instruction Set and Addressing Modes

All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction pipelining.

The PowerPC instructions are divided into the following categories:

• Integer instructions—These include computational and logical instructions. — Integer arithmetic instructions — Integer compare instructions — Integer logical instructions — Integer rotate and shift instructions

• Floating-point instructions—These include floating-point computational instructions, as well as instructions that affect the FPSCR.

— Floating-point arithmetic instructions — Floating-point multiply/add instructions — Floating-point rounding and conversion instructions — Floating-point compare instructions — Floating-point status and control instructions

• Load/store instructions—These include integer and floating-point load and store instructions.

— Integer load and store instructions — Integer load and store multiple instructions

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— Floating-point load and store — Primitives used to construct atomic memory operations (lwarx and stwcx.

instructions)

• Flow control instructions—These include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction flow.

— Branch and trap instructions — Condition register logical instructions

• Processor control instructions—These instructions are used for synchronizing memory accesses and management of caches, TLBs, and the segment registers.

— Move to/from SPR instructions — Move to/from MSR — Synchronize — Instruction synchronize

• Memory control instructions—These instructions provide control of caches, TLBs, and segment registers.

— Supervisor-level cache management instructions — User-level cache instructions — Segment register manipulation instructions

• Translation lookaside buffer management instructions

Note that this grouping of instructions does not indicate the execution unit that executes a particular instruction or group of instructions.

Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on single-precision (one word) and double-precision (one double word) floating-point operands. The PowerPC architecture uses instructions that are 4 bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs. It also provides for word and double-word operand loads and stores between memory and a set of 32 FPRs.

Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written back to the target location with distinct instructions.

The MPC603e follows the program flow when it is in the normal execution state. However , the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. Either kind of exception m ay cause one of several components of the system software to be invoked.

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1.3.2.2 Implementation-Specific Instruction Set

The MPC603e instruction set is defined as follows:

• The MPC603e provides hardware support for all 32-bit PowerPC instructions.

• The MPC603e provides two implementation-specific instructions used for software table search operations following TLB misses:

— Load Data TLB Entry (tlbld) — Load Instruction TLB Entry (tlbli)

• The MPC603e implements the following instructions which are defined as optional by the PowerPC architecture:

— External Control In Word Indexed (eciwx) — External Control Out Word Indexed (ecowx) — Floating Select (fsel) — Floating Reciprocal Estimate Single-Precision (fres) — Floating Reciprocal Square Root Estimate (frsqrte) — Store Floating-Point as Integer Word (stfiwx)

1.3.3 Cache Implementation

The following sections describe the general cache characteristics as implemented in the PowerPC architecture, and the MPC603e implementation, specifically. PID7t-603e specific information is noted where applicable.

1.3.3.1 PowerPC Cache Characteristics

The PowerPC architecture does not define hardware aspects of cache implementations. The MPC603e controls the following memory access modes on a page or block basis:

• Write-back/write-through mode

• Caching-inhibited mode

• Memory coherency

Note that in the MPC603e, a cache block is defined as eight words. The VEA defines cache management instructions that provide a means by which the application programmer can affect the cache contents.

1.3.3.2 Implementation-Specific Cache Implementation

The MPC603e has two 16-Kbyte, four-way set-associative (instruction and data) caches. The caches are physically addressed, and the data cache can operate in either write-back or write-through mode as specified by the PowerPC architecture.

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The data cache is configured as 128 sets of four blocks each. Each block consists of 32 bytes, 2 state bits, an d an address tag. The 2 state bits implement the three-state MEI (modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. No te that

the PowerPC architecture defines the term ‘block’ as the cacheable unit. For the MPC603e, the block size is equivalent to a cache line. A block diagram of the data cache organization is shown in Figure 1-3.

128 Sets

Block 0 Block 1 Block 2 Block 3

Address Tag 0 Address Tag 1 Address Tag 2 Address Tag 3

State State State

State

Words 0–7 Words 0–7 Words 0–7 Words 0–7

8 Words/Block

Figure 1-3. Data Cache Organization

The instruction cache also consists of 128 sets of four blocks, and each block consists of 32 bytes, an address tag, and a valid bit. The instruction cache may not be written to, except through a block fill operation. In the PID7t-603e, the instruction cache is blocked only until the critical load completes. The PID7t-603e supports instruction fetching from other instruction cache lines following the forwarding of the critical first double word of a cache line load operation. Successive instruction fetches from the cache line being loaded are forwarded, and accesses to other instruction cache lines can pr oceed du ring the cache line load operation. The instruction cache is not snooped, and cache coherency must be maintained by software. A fast hardware invalidation capability is provided to support cache maintenance. The organization of the instruction cache is very similar to the data cache shown in Figure 1-3.

Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits A[27–31] of the effective addresses are zero); thus, a cache block never crosses a page boundary . Misaligned accesses across a page boundary can incur a performance penalty.

The MPC603e cache blocks are loaded in four beats of 64 bits each when the MPC603e is configured with a 64-bit data bu s. When the MPC603e is configured with a 32-bit bus, cache block loads are performed with eight beats of 32 bits each. The burst load is performed as critical-double-word-first. The data cache is blocked to internal accesses until the load completes; the instruction cache allows sequential fetching during a cache block

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load. In the PID7t-603e, the critical-double-word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays.

To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the MPC603e implements the ME I protocol. The following three states indicate the state of the cache block:

• Modified—The cache block is modified with respect to system memory; that is, data for this address is valid only in the cache and not in system memory.

• Exclusive—This cache block holds valid data that is identical to the data at this address in system memory. No other cache has this data.

• Invalid—This cache block does not hold valid data.

Cache coherency is enforced by on-chip bus snooping logic. Because the MPC603e data cache tags are single-ported, a simultaneous load or store and snoop access represents a resource contention. The snoop access is given first access to the tags. The load o r store then occurs on the clock following the snoop.

1.3.4 Exception Model

This section describes the PowerPC exception model an d the MPC603e implementation, specifically. PID7t-603e-specific information is noted where applicable.

1.3.4.1 PowerPC Exception Model

The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions, and differs from the arithmetic exceptions defined by the IEEE for floating-point operations. When exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for each exception type. Processing of exceptions occurs in supervisor mode.

Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception—for example, the DSISR and the FPSCR. Additionally, some exception conditions can be explicitly enabled or disabled by software.

The PowerPC architecture requires that exceptions be handled in program order; therefore, although a particular implementation may recognize exception conditions out of order, they are presented strictly in order. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute stage, are required to complete before the exception is t aken. Any exceptions caused by those instructions are handled first. Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the

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instruction currently in the completion stage successfully completes execution or generates an exception, and the completed store queue is emptied.

Unless a catastrophic condition causes a system reset or machine check exception, only one exception is handled at a time. If, for example, a single instruction encounters multiple exception conditions, those conditions are handled sequentially. After the exception handler handles an exception, the instruction execution continues until the next exception condition is encountered. However, in many cases there is no attempt to re-execute the instruction. This method of recognizing and handling exception conditions sequentially guarantees that exceptions are recoverable.

Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state from being lost due to a system reset or machine check exception or to an instruction-caused exception in the exception handler, and before enabling external interrupts.

The PowerPC architecture supports four types of exceptions:

• Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are handled precisely; that is, the machine state at the time the exception occurs is known and can be completely restored. This means that (excluding the trap and system call exceptions) the address of the faulting instruction is provided to the exception handler and neither the faulting instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. Once the exception is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception handler). When an exception is taken due to a trap or system call instruction, execution resumes at an address provided by the handler.

• Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point exception modes, recoverable and nonrecoverable. Even though the MPC603e provides a means to enable the imprecise modes, it implements these modes identically to the precise mode (that is, all enabled floating-point enabled exceptions are always precise on the MPC603e).

• Asynchronous, maskable—The external, system management interrupt (SMI), and decrementer interrupts are maskable asynchronous exceptions. When these exceptions occur, their handling is postponed until the next instruction, and any exceptions associated with that instruction, completes execution. If there are no instructions in the execution units, the exception is taken immediately on determination of the correct restart address (for loading SRR0).

• Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions: system reset and the machine check exception. These exceptions may not be recoverable, or may provide a limited degree of recoverability . All exceptions report recoverability through MSR[RI].

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1.3.4.2 Implementation-Specific Exception Model

As specified by the PowerPC architecture, all MPC60 3e exceptions can be described as either precise or imprecise and either synchronous or asynchronous. Asynchronous

exceptions (some of which are maskable) are caused by events external to the processor ’s execution; synchronous exceptions, which are all handled precisely by the MPC603e, are caused by instructions. The MPC603e exception classes are shown in Table 1-4.

Table 1-4. Exception Classifications

Synchronous/Asynchronous Precise/Imprecise Exception Type

Asynchronous, nonmaskable Imprecise Machine check

System reset

Asynchronous, maskable Precise External interrupt

Decrementer System management interrupt

Synchronous Precise Instruction-caused exceptions

Although exceptions have other characteristics as well, such as whether they are maskable or nonmaskable, the distinctions shown in T able 1-4 define categories of exceptions that the MPC603e handles uniquely. Note that Table 1-4 includes no synchronous imprecise instructions. While the PowerPC architecture supports imprecise handling of floating-point exceptions, the MPC603e implements floating-point exception modes as precise exceptions.

The MPC603e exceptions, and conditions that cause them, are listed in Table 1-5.

Table 1-5. Exceptions and Conditions

Exception

Type

Reserved 00000 — System reset 00100 A system reset is caused by the assertion of either SRESET Machine check 00200 A machine check is cau sed by th e asse rtio n of TEA during a data bus tra nsact ion,

DSI 00300 The cause of a DSI exception can be determined by the bit settings in the DSISR,

Vector Offset

(hex)

Causing Conditions

or HRESET.

assertion of MCP

listed as follows: 1 Set if the translation of an attempted access is not found in the primary hash

table entry group (H TEG), or in th e reha shed sec ondary HTEG, or in the ran ge of a DBAT register; otherwise cleared.

4 Set if a memory access is not permitted by the page or DBAT protection

mechanism; otherwise cleared .

5 Set by an eciwx or ecowx instruction if the acce ss is to an address that is

marked as write-through, or ex ecuti on of a loa d/stor e instructi on that ac cess es

a direct-store segment. 6 Set for a store operation and cleared for a load operation. 11 Set if eciwx or ecowx is used and EAR[E] is cleared.

, or an address or data parity error.

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Table 1-5. Exceptions and Conditions (continued)

Exception

Type

ISI 00400 An ISI exception is caused when an instruction fetch cannot be performed for any

External interrupt

Alignment 00600 An alignment exception is caused when the MPC603e cannot perform a memory

Vector Offset

(hex)

of the following reasons:

• The effective (logical) a ddress cannot be transla ted. That is, there is a p age fault

for this portion of the translation, so an ISI exception must be taken to load the PTE (and possibly the page) into memory.

• The fetch access is to a direct-store segment (indicated by SRR1[3] set).

• The fetch access violates memory protection (indicated by SRR1[4] set). If the

key bits (Ks and Kp) in the segment register and the PP bits in the PTE are set to prohibit read access, instructions cannot be fetched from this location.

00500 An external interrupt is caused when MSR[EE] = 1 and the INT

access for any of the reasons described below:

• The operand of a floating-point load or store instruction is not word-aligned.

• The operand of lmw, stmw, lwarx, and stwcx. instructions are not aligned.

• The operand of a single-register load or store operation is not aligned, and the

MPC603e is in little-endian mode (PID6-603e only).

• The execution of a floating-point load or store instruction to a direct-store

segment.

• The operand of a load, store, load multiple, store multip le, load string, or store

string instruction crosses a segment boundary into a direct-store segment, or crosses a protection boundary.

• Execution of a misaligned eciwx or ecowx instruction (PID7t-603e only).

• The instruction is lmw, stmw, lswi, lswx, stswi, stswx, and the MPC6 03e is in

little-endian mode.

• The operand of dcbz is in memory that is write-through-required or

caching-inhibited.

Causing Conditions

signal is asserted.

Program 00700 A program exception is caused by one of the following ex ception co nditions , which

correspond to bit settings in SRR1 and arise during execution of an instruction:

• Floating-point enabled exception—A floating-point enabled exception condition

is generated when the following condition is met:

(MSR[FE0] | MSR[FE1]) & FPSCR[FEX] is 1.

• FPSCR[FEX] is set by the execution of a floating -point instructio n that causes an

enabled exception or by the execution of one of the ‘move to FPSCR’ instructions that results in both an exception condition bit and its corresponding enable bit being set in the FPSCR.

• Illegal instruction—An illegal instruction program exception is generated when

execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode fields (including PowerPC instructions not impl emented in the MPC603e), or when ex ecution of an optional instruction not prov ided in the MPC603e is attempted (these do n ot include those optional instructions that are treated as no-ops).

• Privileged instruction—A privileged instruction type program exception is

generated when the execution of a privileged instruction is attempted and the MSR register user pr ivilege bit , MSR[PR], is se t. In the MPC60 3e, this exc eption is generated for mtspr or mfspr with an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all processors.

• Trap—A trap type program exception is generated when any of the conditions

specified in a trap instruction is met.

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Table 1-5. Exceptions and Conditions (continued)

Exception

Type

Floating-point unavailable

Decrementer 00900 The decrementer exception occ urs when DEC[31] changes from 0 to 1. Must also

Reserved 00A00–00BFF —

System call 00C00 A system call exception occurs when a System Call (sc) instruction is executed. Trace 00D00 A trace exception is taken when MSR[SE] =1 or when the currently completing

Reserved 00E00 The MPC603e does not generate an e xception to this v ector. O ther processors m ay

Reserved 00E10–00FFF — Instruction

translation miss Data load

translation miss Data store

translation miss

Vector Offset

(hex)

00800 A floating-point unavailable exception is caused by an attempt to execute a

floating-point ins truction (including f loating-point load, s tore, and move instruc tions) when the floating-point available bit is disabled (MSR[FP] = 0).

be enabled with MSR[EE].

instruction is a branch and MSR[BE] =1.

use this vector for floating-point assist exceptions.

01000 An instruction translation miss exception is caused when an effective address for

an instruction fetch cann ot be translated by the ITLB.

01100 A data load translation miss exception is caused when an effective address for a

data load operation cannot be translated by the DTLB.

01200 A data store translation miss exception is caused when an effective address for a

data store operation cannot be trans lated by the DTLB, or where a DTLB hit occurs, and the change bit in the PTE must be set due to a data store operation.

Causing Conditions

Instruction address breakpoint

System management interrupt

Reserved 01500–02FFF —

01300 An instruction address breakpoint exception occurs when the address (bits 0–29)

in the IABR matches the next instruction to complete in the completion unit, and IABR[30] is set.

01400 A system management interrupt is caused when MSR[EE] = 1 and the SMI

signal is asserted.

input

1.3.5 Memory Management

The following sections describe the memory management features of the PowerPC architecture and the MPC603e implementation, respectively.

1.3.5.1 PowerPC Memory Management

The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for memory accesses, and to provide access protection on blocks and pages of memory.

There are two types of accesses generated by the MPC603e that require address

translation— instruction accesses and data accesses to memory generated by load and store instructions.

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The PowerPC MMU and exception model support demand-paged virtual mem ory. Virtual memory management permits execution of programs larger than the size of physical memory; demand-paged implies that individual pages are loaded into physical memory from system memory only when they are first accessed by an executing program.

The hashed page table is a variable-si zed data struct ure that defin es the mapp ing between virtual page numbers and physical page numbers. The page table size is a power of two, and its starting address is a multiple of its size.

The page table contains a number of page table entry groups (PTEGs). A PTEG contains 8 page table entries (PTEs) of 8 bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search operations.

Address translations are enabled by setting bits in the MSR—MSR[IR] enables instruction address translations and MSR[DR] enables data address translations.

1.3.5.2 Implementation-Specific Memory Management

The instruction and data memory management units in the MPC603e provide 4 Gbytes of logical address space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size. Block sizes range from 128 Kbytes to 256 Mbytes and are software selectable. In addition, the MPC603e uses an interim 52-bit virtual addre ss and hashed page tables for generating 32-bit physical addresses. The MMUs in the MPC 603e rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas.

Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most recently used page table entries. Software is responsible for maintaining the consistency of the TLB with memory. The MPC603e TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The MPC603e provides hardware assist for software table search operations through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.

The MPC603e also provides independent four-entry BAT arrays for instructions and data that maintain address translations for blocks of memory. These entries define blocks that can vary from 128 Kbytes to 256 Mbytes. The BAT arrays are maintained by system software.

As specified by the PowerPC architecture, the hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page numbers. The page table size is a power of two, and its starting address is a multiple of its size.

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Also as specified by the PowerPC architecture, the page table contains a number of PTEGs. A PTEG contains 8 PTEs of 8 bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search operations.

1.3.6 Instruction Timing

The MPC603e is a pipelined superscalar processor. The processing of an instruction is reduced into discrete stages by a pipelined processor. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of an execution unit. For example, after an instruction completes the decode stage, it can pass on to the next stage, while the subsequent instruction can advance into the decode stage. This improves the throughput of the instruction flow. For example, it may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of floating-point instructions can have a throughput of one instruction per cycle.

The MPC603e instruction pipeline has four major pipeline stages, described as follows:

• The fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction fetch. Additionally, if possible, the BPU decodes branches during the fetch stage and folds out branch instructions before the dispatch stage.

• The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determining which of the instructions are eligible to be dispatched in the current cycle. In addition, the source operands of the instructions are read from the appropriate register file and dispatched with the instruction to the execute pipeline stage. At the end of the dispatch pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit.

• In the execute pipeline stage, each execution unit with an executable instruction executes the selected instruction (perhaps over multiple cycles), writes the instruction's result into the appropriate rename register, and notifies the completion stage when the execution has finished. In the case of an internal exception, the execution unit reports the exception to the completion/writeback pipeline stage and discontinues instruction execution until the exception is handled. The exception is not signaled until that instruction is the next to be completed. Execution of most floating-point instructions is pipelined within the FPU allowing up to three instructions to be executing in the FPU concurrently. The FPU pipeline stages are multiply, add, and round-convert. The LSU has two pipeline stages. The first stage is for effective address calculation and MMU translation, and the second is for accessing data in the cache.

• The complete/writeback pipeline stage maintains the correct architectural machine state and transfers the contents of the rename registers to the GPRs and FPRs as

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instructions are retired. If the completion logic detects an instruction causing an exception, all following instructions are canceled, their execution results in rename registers are discarded, and instructions are fetched from the correct instruction stream.

A superscalar processor issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel. The MPC603e has five independent execution units, one each for integer instructions, floating-point instructions, branch instructions, load/store instructions, and system register instructions. The IU and the FPU eac h have dedicated register files for maintaining operands (GPRs and FPRs, respectively), allowing integer and floating-point calculations to occur simultaneously without interference. Integer division performance of the PID7t-603e has been improved, with the divwux and divwx instructions executing in 2 0 clock cycles instead of the 37 cycles required in the PID6-603e.

The MPC603e provides support for single-cycle store and it provides an adder/comparator in the system register unit that allows t he dispatch and execution of multiple integer add

and compare instructions on each cycle. Refer to Chapter 6, “Instruction Timing,” for more information.

Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction timing among various processors varies accordingly.

1.3.7 System Interface

The system interface is specific for each processor implementation. The MPC603e provides a versatile system interface that allows for a wide range of

implementations. The interface includes a 32-bit address bus, a 32- or 64-bit data bus, and 56 control and information signals (see Figure 1-4). The system interface allows for address-only transactions, as well as address and data transactions. The MPC603e control and information signals include the address arbitration, address start, address transfer, transfer attribute, address termination, data arbitration, data transfer, data termination, and processor state signals. Test and control signals provide diagnostics for selected in ternal circuits.

The system interface supports bus pipelining, allowing the address tenure of one transaction to overlap the data tenure of another. The extent of the pipelining depends on external arbitration and control circuitry. Similarly, the MPC603e supports split-bus transactions for systems with multiple potential bus masters—one device can have mastership of the address bus while another has mastership of the data bus. Allowing multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity, and as a result, improves performance.

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Address

Address Arbitration

Address Start Address Transfer Transfer Attribute

Address Termination

Clocks

MPC603e

+3.3 V

Data Data Arbitration

Data Transfer Data Termination Processor State Test And Control

Figure 1-4. System Interface

The MPC603e supports multiple masters through a bus arbitration scheme that allows various devices to compete for the shared bus resource. Arbitration logic can implement priority protocols, such as fairness, and can park masters to avoid arbitration overhead. The MEI protocol ensures coherency among multiple devices and system memory. Also, the MPC603e on-chip caches, TLBs, and optional second-level caches can be controlled externally.

The MPC603e clocking structure allows the bus to operate at integer multiples of the processor cycle time.

The following sections describe the MPC603e bus support for memory operations. Note that some signals perform different functions depending on the addressing protocol used.

1.3.7.1 Memory Accesses

The MPC603e bus is configured at power-up to either a 32- or 64-bit width.

• When the processor is configured with a 32-bit data bus, memory accesses allow transfer sizes of 8, 16, 24, or 32 bits in one bus clock cycle. Data transfers occur in either single-beat transactions, two-beat or eight-beat burst transactions, with a single-beat transaction transferring as many as 32 bits. Single- or double-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Eight-beat burst transactions, which always transfer an entire cache block (32 bytes), are initiated when a line is read from or written to memory.

• When the MPC603e is configured with a 64-bit data bus, memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus clock cycle. Data transfers occur in either single-beat transactions or four-beat burst transactions. Single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Four-beat burst transactions, which

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always transfer an entire cache block (32 bytes), are initiated when a line is read from or written to memory.

1.3.7.2 Signals

The MPC603e signals are grouped as follows:

• Address arbitration signals—The MPC603e uses these signals to arbitrate for address bus mastership.

• Address transfer start signals—These signals indicate that a bus master has begun a transaction on the address bus.

• Address transfer signals—These signals, consisting of address bus, address parity, and address parity error signals, are used to transfer the address and to ensure the integrity of the transfer.

• Transfer attribute signals—These signals provide information about the type of transfer, such as the transfer size and whether the transaction is bursted, write-through, or caching-inhibited.

• Address transfer termination signals—These signals are used to acknowledge the end of the address phase of the transaction. They also indicate whether a condition exists that requires the address phase to be repeated.

• Data arbitration signals—The MPC603e uses these signals to arbitrate for data bus mastership.

• Data transfer signals—These signals, consisting of data bus, data parity, and data parity error signals, are used to transfer the data and to ensure the integrity of the transfer.

• Data transfer termination signals—Data termination signals are required after each data beat in a data transfer. In a single-beat transaction, the data termination signals also indicate the end of the tenure. In burst accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat. They also indicate whether a condition exists that requires the data phase to be repeated.

• System status signals—These signals include the interrupt signal, checkstop signals, and soft- and hard-reset signals. They are used to interrupt and, under various conditions, to reset the processor.

• Processor state signals—These signals indicate the state of the reservation coherency bit, enable the time base, provide machine quiescence control, and can be used to cause a machine halt on execution of a tlbsync instruction.

• JTAG/COP interface signals—The JTAG (IEEE 1149.1) interface and common on-chip processor (COP) unit provides a serial interface to the system for performing monitoring and boundary tests.

• Test interface signals—These signals are used for production testing.

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• Clock signals—These signals determine the system clock frequency and can be used to synchronize multiprocessor systems.

NOTE

A bar over a signal name indicates that the signal is active low—for example, ARTRY

(address retry) and TS (transfer start). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low , such as AP[0:3] (address bus parity signals) and TT[0:4] (transfer type signals) are referred to as asserted when they are high and negated when they are low.

1.3.7.3 Signal Configuration

Figure 1-5 illustrates the MPC603e logical pin configuration, showing how the signals are grouped.

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Address

Arbitration

Address

Start

Address Bus

Transfer Attribute

Address

Termination

Clocks

BR BG

ABB

A[0:31]

AP[0:3]

APE

TT[0:4]

TBST

TSIZ[0:2]

GBL

CSE[0:1]

TC[0:1]

AACK

ARTRY

SYSCLK

CLK_OUT

PLL_CFG[0:3]

1 1 1

4 1

MPC603e

5 1 3 1 1 1 2 2

1 1

1 1 4

1 1 1

DH[0:31], DL[0:31]

8 1 1

1 1 1

2 1

CKSTP_IN, CKSTP_OUT

2 2

1 2 1 1

HRESET, SRESET

QREQ, QACK

TLBISYNC

TRST

, TCK, TMS, TDI, TD0

DBG

DBWO

DBB

DP[0:7]

DPE

DBDIS

DRTRY

TEA

INT

, SMI

MCP

RSRV

TBEN

TEST

Data Arbitration

Data Transfer

Data Termination

Interrupts, Checkstops, Reset

Processor Status

JTAG/COP Interface

LSSD Test Control

+3.3 V

Figure 1-5. Signal Groups

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Chapter 2 Programming Model

This chapter describes the PowerPC programming model with respect to the MPC603e microprocessor. It consists of three major sections that describe the following:

• Registers implemented in the MPC603e

• Operand conventions

• MPC603e instruction set

2.1 Register Set

This section describes the register organization in the MPC603e as defined by the three levels of the PowerPC architecture— user instruction set architecture (UISA), virtual environment architecture (VEA), and operating environm ent architecture (OEA), as well as the MPC603e implementation-specific registers. Full descriptions of the basic register set defined by the PowerPC architecture are provided in Chapte r 2, “Register Set,” in the Programming Environments Manual.

The PowerPC architecture defines register-to-register operations for all computational instructions. Source data for these instructions is a ccessed from the on-chip registers or is provided as an immediate value embedded in the opcode. The three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions and reducing the number of instructions required for certain operations. Data is transferred between memory and registers with explicit load and store instructions only.

Note that there may be registers common to other processors of this family that are not implemented in the MPC603e. When the MPC603e detects special-purpose register (SPR) encodings other than those defined in this document, it either takes an exception or it treats the instruction as a no-op. (Note that exceptions are referred to as interrupts in the architecture specification.) Conversely, some SPRs in the MPC603e may not be implemented in other processors or may not be implemented in the same way.

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2.1.1 PowerPC Register Set

The PowerPC UISA registers, shown in Figure 2-1, can be accessed by either user- or supervisor-level instructions (the architecture specification refers to user- and supervisor-level as problem state and privileged state, re spectively). The general-purpose registers (GPRs) and floating-point registers (FPRs) are accessed through instruction operands. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as the mtspr and mfspr instructions) or implicit as part of the execution (or side effect) of an instruction. Some registers are accessed both explicitly and implicitly .

The number to the right of the register name indicates the number that is used in the syntax of the instruction operands to acces s the register (fo r example, the n umber used to access the XER is SPR1).

For more information on the PowerPC register set, refer to Chapter 2, “Register Set,” in the Programming Environments Manual.

The MPC603e user-level registers are described as follows:

• User-level registers (UISA)—The user-level registers can be accessed by all software with either user or supervisor privileges. The user-level register set includes the following:

— General-purpose registers (GPRs). The GPR file consists of thirty-two 32-bit

GPRs designated as GPR0–GPR31. This register file serves as the data source or destination for all integer instructions and provides data for generating addresses.

— Floating-point registers (FPRs). The FPR file consists of thirty-two 64-bit FPRs

designated as FPR0–FPR31, which serves as the data source or destination for all floating-point instructions. These registers can contain data objects of either single- or double-precision floating-point format.

Before the stfd instruction is used to store the contents of an FPR to memory , the FPR must have been initialized after reset (explicitly loaded with any value) by using a floating-point load instruction.

— Condition register (CR). The CR consists of eight 4-bit fields, CR0–CR7, that

reflect the results of certain arithmetic operations and provides a mechanism for testing and branching.

— Floating-point status and control register (FPSCR). The FPSCR contains all

floating-point exception signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance with the IEEE 754 standard.

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USER MODEL

General-Purpose Registers

GPR31

Floating-Point Registers

FPR31

Condition Register

GPR0 GPR1

FPR0 FPR1

SUPERVISOR MODEL

Configuration Registers

Hardware Implementation Registers

SPR 1008HID0 SPR 1009HID1

Machine State Register

MSR

Memory Management Registers

Instruction BAT Registers

SPR 528IBAT0U IBAT0L IBAT1U IBAT1L IBAT2U IBAT2L IBAT3U IBAT3L

SPR 529

SPR 530

SPR 531

SPR 532

SPR 533

SPR 534

SPR 535

SDR1

SPR 25SDR1

Data BAT Registers

SPR 536DBAT0U SPR 537DBAT0L SPR 538DBAT1U SPR 539DBAT1L SPR 540DBAT2U SPR 541DBAT2L SPR 542DBAT3U SPR 543DBAT3L

Processor Version Register

SPR 287PVR

Software Table Search Registers

SPR 976DMISS SPR 977DCMP SPR 978HASH1 SPR 979HASH2 SPR 980IMISS SPR 981ICMP SPR 982RPA

Segment Registers

SR0 SR1

SR15

Floating-Point Status and Control Register

FPSCR

XER

SPR 1

Link Register

SPR 8

Data Address Register

DAR

SPRGs

SPRG1 SPRG2 SPRG3

Count Register

CTR

Time Base Facility

SPR 9

(For Reading)

TBL

TBU

These registers are MPC603e-specific (PID6-603e and PID7t-603e). They may not be supported by

TBR 268 TBR 269

Time Base Facility (For Writing)

TBU

Instruction Address Breakpoint Register

Exception Handling Registers

SPR 19

SPR 272SPRG0 SPR 273 SPR 274 SPR 275

Miscellaneous Registers

SPR 284TBL SPR 285

SPR 1010IABR

DSISR

SPR 18DSISR

Save and Restore Registers

SRR0 SRR1

SPR 26 SPR 27

Decrementer

DEC

SPR 22

External Address Register (Optional)

EAR

SPR 282

other proce ssors of this family.

Figure 2-1. Programming Model—Registers

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The remaining user-level registers are SPRs. Note that the PowerPC architecture provides a separate mechanism for accessing SPRs (the mtspr and mfspr instructions). These instructions are commonly used to explicitly access certain registers, while other SPRs may be accessed as the side effect of executing other instructions.

— XER register (XER). The 32-bit XER indicates overflow and carries for integer

operations. It is set implicitly by many instructions.

— Link register (LR). The 32-bit LR provides the branch target address for the

Branch Conditional to Link Register (bclrx) instruction and can optionally be used to hold the logical address (referred to as the effective address in the architecture specification) of the instruction that follows a branch and link instruction, typically used for linking to subroutines.

— Count register (CTR). The 32-bit CTR can be used to hold a loop count that can

be decremented during execution of appropriately coded branch instructions. It can also provide the branch target address for the Branch Conditional to Count Register (bcctrx) instruction.

• User-level registers (VEA)—The VEA introduces the time base facility (TB) for reading. The TB is a 64-bit register pair whose contents are incremented once every four bus clock cycles. The TB consists of two 32-bit registers—time base upper (TBU) and time base lower (TBL). Note that the time base registers are read-only in user state.

The MPC603e supervisor-level registers are described as follows:

• Supervisor-level registers (OEA)—The OEA defines the registers an operating system uses for memory management, configuration, and exception handling. The PowerPC architecture defines the following supervisor-level registers:

— Configuration registers

– Machine state register (MSR). The MSR defines the state of the processor.

The MSR can be modified by the Move to Machine State Register (mtmsr), System Call (sc), and Return from Exception (rfi) instructions. It can be read by the Move from Machine State Register (mfmsr) instruction.

Implementation Note—The MPC603e defines MSR[13] as the power management enable (POW) bit and MSR[14] as the temporary GPR remapping (TGPR) bit. These bits are described in Table 2-1.

– Processor version register (PVR). This read-only register identifies the

version (model) and revision level of this processor. Implementation Note—The processor version number is 6 for the

PID6-603e and 7 for the PID7t-603e. The processor revision level starts at 0x0100 and changes for each chip revision. The revision level is updated on all silicon revisions.

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Table 2-1. MSR[POW] and MSR[TGPR] Bits

Bits Name Description

13 POW Power management enabl e (MPC603e-specific). Controls t he programmable power mode s only;

it has no effect on dynamic power management (DPM). MSR[POW] may be altered with an mtmsr instruction only. Also, when altering the POW bit, software may alter only this bit in the MSR and no others. The mtmsr instruction must be followed by a context-synchronizing

instruction. See Chapter 9, “Power Management,” for more information on power management. 0 Disables programmable power modes (normal operation mode). 1 Enables programmable power modes (nap, doze, or sleep mode).

14 TGPR Temporary GPR remapping (MPC603e-specific). The contents of GPR0–GPR3 remain

unchanged while MSR[TGPR] = 1. Attempts to use GPR4–GPR31 with MSR[TGPR] = 1 yield undefined results. When this bit is set, all instruction accesses to GPR0–GPR3 are mapped to TGPR0–TGPR3, respectively. TGPR is set when an instruction TLB miss, data TLB miss on load, or data TLB miss on store exception is taken. TGPR is cleared by an rfi instruction. 0 Normal operation 1 TGPR mode. GPR0–GPR3 are remapped to TGPR0–TGPR3 for use by TLB miss routines.

— Memory management registers

– Block-address translation (BAT) registers. The MPC603e includes eight

block-address translation registers (BATs): four pairs of instruction BATs (IBAT0U–IBAT3U and IBAT0L–IBAT3L) and four pairs of data BATs (DBA T0U–DBAT3U and DBA T0L–DBAT3L). Figure 2-1 lists SPR numbers for the BAT registers.

– SDR1. The SDR1 register specifies the page table base address used in

virtual-to-physical address translation. (Note that physical address is referred to as real address in the architecture specification.)

– Segment registers (SRs). The PowerPC OEA defines sixteen 32-bit segment

registers (SR0–SR15). The fields in the segment register are interpreted differently depending on the value of bit 0.

— Exception handling registers

– Data address register (DAR). After a data access or an alignment exception,

the DAR is set to the effective address generated by the faulting instruction.

– SPRG0–SPRG3. The SPRG0–SPRG3 registers are provided for operating

system use.

– DSISR. The DSISR defines the cause of data access and alignment

exceptions.

– Machine status save/restore register 0 (SRR0). The SRR0 is used to save

machine status on exceptions and to restore machine status when an rfi instruction is executed.

– Machine status save/restore register 1 (SRR1). The SRR1 is used to save

machine status on exceptions and to restore machine status when an rfi instruction is executed.

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— Miscellaneous registers

– The time base facility (TB) for writing. The TB is a 64-bit register pair that

– Decrementer (DEC). The DEC register is a 32-bit decrementing counter that

– External access register (EAR). The EAR is a 32-bit register used in

Implementation Note—The MPC603e implements the KEY bit (bit 12) in the SRR1 register to simplify the table search software. For more information refer to Chapter 5, “Memory Management.”

can be used to provide time-of-day or interval timing. It consists of two 32-bit registers—time base upper (TBU) and time base lower (TBL). The TB is incremented once every four clock cycles on the MPC603e.

provides a mechanism for causing a decrementer exception after a programmable delay. The DEC is decremented once every four bus clock cycles.

conjunction with the eciwx and ecowx instructions. Although the PowerPC architecture specifies that EAR[26–31] are used to select a device, the MPC603e implements only bits 28–31. Note that EAR and the eciwx and ecowx instructions are optional in the PowerPC architecture and may not be supported in all processors that implement the OEA.

2.1.2 Implementation-Specific Registers

The MPC603e defines the DMISS, IMISS, DCMP, ICMP, HASH1, HASH2, RPA, HID0, HID1, and IABR SPRs for software table search operations. These registers should be accessed only when address translation is disabled (MSR[IR] and MSR[DR] are both zero). For a complete discussion, refer to Section 5.5.2, “Implementation-Specific Table Search Operation.” Also, the HID0, HID1, and IABR SPRs are defined and described in this section. These registers can be accessed by supervisor-level instructions only using the SPR numbers shown in Figure 2-1.

2.1.2.1 Hardware Implementation Registers (HID0 and HID1)

The HID0 and HID1 registers, shown in Figure 2-2 and Figure 2-3, respectively, define enable bits for various MPC603e-specific features.

EICE

EMCP SBCLK

EBDEBA PAR NAP DPM NHR ICE DCE DC FI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 26 27 28 30 31

ECLK DOZE SLEEP RISEG ILOCK

DLOCK

ICFI

FBIOB NOOPTI

0 0 0 0 0 0 0 00 00

Reserved

Figure 2-2. Hardware Implementation Register 0 (HID0)

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Table 2-2 shows the bit definitions for HID0.

Table 2-2. HID0 Bit Functions

Bits Name Function

0 EMCP Enable MCP

caused by assertion of MCP 0 Masks MCP 1 Asserting MCP

1 — Reserved, do not clear.

2 EBA Enable 60x bus address parity checking. EBA and EBD allow the processor to operate with

memory subsystems that do not generate parity. 0 Disabl es address parity checking. 1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check

exception if MSR[ME] = 1.

3 EBD Enable 60x bus data parity checking. EBA and EBD allow the processor to operate with memory

subsystems that do not generate parity. 0 Disables data parity checking. 1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception

if MSR[ME] = 1.

4 BCLK CLK_OUT output enable and clock type selection. Used in conjunction with HID0[ECLK] and

HRESET

5 EICE Enables in-circuit emulator outputs for pipeline tracking. See Section 7.2.11, “Pipeline Tracking

Support.”

6 ECLK CLK_OUT output enable and clock type selection. Used in conjunction with HID0[BCLK] and the

HRESET

7 PAR Disable precharge of ARTRY.

0 Precharge of ARTRY 1 Alters bus protocol slightly by preventing the processor from driving ARTRY

state. If this is done, the system must restore the signals to the high state.

8DOZE

9NAP

10 SLEEP

11 DPM

Doze mode enable. Operates in conjunction with MSR[POW]. 0 Doze mode disabled. 1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In doze

mode, the PLL, time base, and snooping remain active.

Nap mode enable. Operates in conjunction with MSR[POW]. 0 Nap mode disabled. 1 Nap mode enabled. Doze mode is invoked by setti ng MSR[POW] while this bit is set. In nap

mode, the PLL and the time base remain active.

Sleep mode enable. Operates in conjunction with MSR[POW]. 0 Sleep mode disabled. 1 Sleep mode enabled. Sleep mode is invok ed by se tting MSR [POW] while this bi t is set. QREQ

is asserted to indicate that the processor is ready to enter sleep mode. If the system logic determines that th e proc esso r may ente r slee p mo de, th e qui esce ackn owledge sig nal, QAC K is asserted back to the processor . Once QACK mode after several process or clocks. At th is point, th e system lo gic may tu rn off th e PLL by first configuring PLL_CFG[0:3] to PLL bypass mode, then disabling SYSCLK.

Dynamic power management enable. 0 Dynamic power management is disabled. 1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect

operational performance and is transparent to software or any external hardware.

. The primary purpose of this bit is to mask out further machine check exceptions

, similar to how MSR[EE] can mask external interrupts.

. Asserting MCP does not generate a machine check exception or a checkstop.

causes checkstop if MSR[ME] = 0 or a machine check exception if ME = 1.

to configure CLK_OUT. See Table 2-3.

signal to configure CLK_OUT. See Table 2-3.

enabled.

to high (negated)

assertion is detected, the p rocessor enters slee p

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Table 2-2. HID0 Bit Functions (continued)

Bits Name Function

12–15 — Reserved, should be cleared.

16 ICE

17 DCE Data cache enable.

18 ILOCK Instruction cache lock.

Instruction cache enable. 0 The instruction ca ch e is neither accessed nor up date d. All pages are accessed as i f th ey w ere

marked cache-inhibi ted (WIM = x 1x). Potent ial cac he access es from t he bus (sno op and c ache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored and all accesses are prop aga ted to the 60x bus as si ngle-be at transa ctions . For those transactions, however, CI regardless of cache disabled status. ICE is zero at power-up.

1 The instruction cache is enabled.

0 The data cache is neither ac cessed nor updated. All page s are accessed as if they were marked

cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored and all accesses are prop aga ted to the 60x bus as si ngle-be at transa ctions . For those transactions, however, CI regardless of cache disabled status. DCE is zero at power-up.

1 The data cache is enabled.

0 Normal operation. 1 Instruction cache is locked. A locked cache supplies data normally on a hit, but the access is

treated as a cache-inhibi ted tr ansac tion on a miss . On a mis s, the tra nsact ion to the 60x bu s is single-beat; however, CI independent of cache locked or disabled status.

T o preve nt locking duri ng a cache acc ess, an isyn c instructi on must precede the setting of ILO CK.

reflects the original state determined by address translation

still reflects the original state as determined by address translation

19 DLOCK Data cache lock.

0 Normal operation. 1 Data cache is locked. A locked cache supplies data normally on a hit but is treated as a

cache-inhibited trans actio n on a miss . On a miss, th e transac tion to the 60x bus is single -beat; however , CI cache locked or dis abled s tatus. A s noop hit to a lock ed L1 da ta cache performs as if th e cache were not locked. A cache block invalidated by a snoop remains invalid until the cache is unlocked.

T o prevent locking during a cache access, a sync instruction must precede the setting of DLOC K.

20 ICFI Instruction cache flash invalidate.

0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation

begins (usually the next cycle after the write operation to the register). The instruction cache must be enabled for the invalidation to occur.

1 An invalidate opera tion i s is sued t hat marks t he state of eac h ins tructio n cac he bl ock a s inval id

without wr iting back modifi ed cache blocks to memory. Cache access is blocked during this time. Bus accesses to th e cache are sig naled as a miss d uring invalid ate-all operati ons. Settin g

ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set. For MPC603e processors, the proper use of the ICFI and DCFI bits is to se t them and clear the m with two consecutive mtspr operations.

still reflects the o rigina l state as det ermine d by a ddress tran slati on i ndepen dent o f

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Table 2-2. HID0 Bit Functions (continued)

Bits Name Function

21 DCFI Data cache flash invalidate.

0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins

(usually the next cycle after the write o peration to the regis ter). The data cach e must be enabled

for the invalidation to occur. 1 An invalidate operatio n is issued that mark s the state of each data cache block as inval id without

writing back modified cache blocks to memory. Cache access is blocked during this time. Bus

accesses to the cache are signaled as a miss during invalidate-all operations. Setting DCFI

clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set. For MPC603e processors, the proper use of the ICFI and DCFI bits is to se t them and clear the m with two consecutive mtspr operations.

22–23 — Reserved, should be cleared.

24 IFEM Enable M bit on 60x bus for instruction fetches (PID7t-603e only).

0 M bit not reflected on bus fo r instruction fetc hes. Instructi on fetches are tr eated as nongloba l on

the bus 1 Instruction fetches reflect the M bit from the WIM settings.

25–26 — Reserved, should be cleared.

27 FBIOB Force branch indirect on bus.

0 Register indirect branch targets are fetched normally. 1 Forces register indirect branch targets to be fetched externally.

28 ABE Address broadcast enable. Controls whether certain address-only operations (such as cache

operations) are broadcast on the 60x bus. 0 Address-only operations affect only local caches and are not broadcast. 1 Address-only operations are broadcast on the 60x bus. Affected instructions are dcbi, dcbf, and dcbst. Note that these cache control instruction broadcasts are not snoop ed by t he PID 7 t-60 3e. R efer t o Sec tio n 3.2.3, “Data Cache Control,” for more information.

29–30 — Reserved

31 NOOPTI No-op the data cache touch instructions.

0 The dcbt and dcbtst instructions are enabled. 1 The dcbt and dcbtst instructions are no-oped globally.

See Chapter 9, “Power Management.”

See Chapter 3, “Instruction and Data Cache Operation.”

Table 2-3 shows how HID0[BCLK], HID0[ECLK], and HRESET are used to configure

CLK_OUT. See Section 7.2.12.2, “Test Clock (CLK_OUT)—Output,” for more information.

Table 2-3. HID0[BCLK] and HID0[ECLK] CLK_OUT Configuration

HRESET HID0[ECLK] HID0[BCLK] CLK_OUT

Asserted x x Bus

Negated 0 0 High impedance Negated 0 1 Core clock frequency Negated 1 0 Bus Negated 1 1 Core clock frequency

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HID0 can be accessed with mtspr and mfspr using SPR1008.

Reserved

PC3PC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PC1 PC2

01234 31

Figure 2-3. Hardware Implementation Register 1 (HID1)

Table 2-4 shows the bit definitions for HID1.

Table 2-4. HID1 Bit Settings

Bits Name Description

0 PC0 PLL configuration bit 0 (read-only) 1 PC1 PLL configuration bit 1 (read-only) 2 PC2 PLL configuration bit 2 (read-only) 3 PC3 PLL configuration bit 3 (read-only)

4–31 — Reserved, should be cleared.

Note: The clock configuration bits reflect the state of the PLL_CFG[0:3] signals.

HID1 can be accessed with mfspr using SPR1009.

2.1.2.2 Data and Instruction TLB Miss Address Registers (DMISS and IMISS)

DMISS and IMISS, shown in Figure 2-4, are loaded automatically upon a data or instruction TLB miss. DMISS and IMISS contain the effective page address of the access that caused the TLB miss exception. The contents are used by the MPC603e when calculating the values of HASH1 and HASH2 and by the tlbld and tlbli instructions when loading a new TLB entry. Note that the MPC603e always loads DMISS with a big-endian address, even when MSR[LE] is set. These registers are read and write to the software.

Effective Page Address

0 31

Figure 2-4. DMISS and IMISS Registers

2.1.2.3 Data and Instruction TLB Compare Registers (DCMP and ICMP)

DCMP and ICMP, sh own in Figure 2-5, contain the first word in the required PTE. The contents are constructed automatically from the contents of the segment registers and the effective address (DMISS or IMISS) when a TLB miss exception occurs. Each PTE read from the tables during the table search process should be compared with this value to determine if the PTE is a match. Upon execution of a tlbld or tlbli instruction, the upper

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25 bits of th e DCMP or ICMP register and 11 bits of the effective address are loaded into the first word of the selected TLB entry. These registers are read and write to the software.

Reserved

V VSID API0

01 24 25 26 31

Figure 2-5. DCMP and ICMP Registers

Table 2-5 describes the bit settings for the DCMP and ICMP registers.

Table 2-5. DCMP and ICMP Bit Settings

Bits Name Description

0 V Valid bit. Set by the processor on a TLB m iss exception.

1–24 VSID Virtual segment ID. Copied from VSID field of corresponding

segment register.

25 — Reserved, should be cleared.

26–31 API Abbreviated page index. Copied from API of effective address.

2.1.2.4 Primary and Secondary Hash Address Registers (HASH1 and HASH2)

HASH1 and HASH2, shown in Figure 2- 6, contain the physical addresses of the primary and secondary P TEGs for the access that caused the TLB miss exception. For convenience,

the MPC603e automatically constructs the full physical address by routing SDR1[0–6] into HASH1 and HASH2 and clearing the lower 6 bits. These read-only registers are constructed from the DMISS or IMISS contents (the register choice is determined by which miss most recently occurred).

HTABORG[0–6] Hashed Page Address 0 0 0 0 0 0

067 25 26 31

Figure 2-6. HASH1 and HASH2 Registers

Table 2-6 describes the bit settings of the HASH1 and HASH2 registers.

Bits Name Description

0–6 HTABORG[0–6] Copy of the upper 7 bits of the HTABORG field from SDR1

7–25 Hashed page address Address bits 7–25 of the PTEG to be searched

Table 2-6. HASH1 and HASH2 Bit Settings

26–31 — Reserved

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2.1.2.5 Required Physical Address Register (RPA)

During a page table search operation, the software must load the RPA, shown in Figure 2-7, with the second word of the correct PTE. When the tlbld or tlbli instruction is executed, the RPA and DMISS or IMISS register are merged and loaded into the selected TLB entry. The referenced (R) bit is ignored when the write occurs (no location exists in the TLB entry for this bit). The RPA register is read and write to the software.

Reserved

RPN R CWIMG PP0 0 0 0

0 19 20 22 23 24 25 28 29 30 31

Figure 2-7. Required Physical Address Register (RPA)

Table 2-7 describes the bit settings of the RPA register.

Table 2-7. RPA Bit Settings

Bits Name Description

0–19 RPN Physical page number from PTE

20–22 — Reserved

23 R Referenced bit from PTE 24 C Changed bit from PTE

25–28 WIMG Memory/cache access attribute bits

29 — Reserved

30–31 PP Page protection bits from PTE

2.1.2.6 Instruction Address Breakpoint Register (IABR)

The IABR, shown in Figure 2-8, controls the instruction address breakpoint exception. IABR[CEA] holds an effective address to which each instruction is compared. The exception is enabled by setting IABR[BE]. The exception is taken when there is an instruction address breakpoint match on the n ext instruction to complete. The instru ction tagged with the match does not complete before the breakpoint exception is taken.

Reserved

CEA IE 0

0 29 30 31

Figure 2-8. Instruction Address Breakpoint Register (IABR)

The bits in the IABR are defined in Table 2-8.

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Table 2-8. Instruction Address Breakpoint Register Bit Settings

Bits Description

0–29 Word address to be compared

30 IABR enabled. Setting this b it indicates that the IABR exce ption

is enabled.

31 Reserved

Operand Conventions

2.2 Operand Conventions

This section describes the operand conventions as they are represented in two levels of the PowerPC architecture. It also provides detailed descriptions of conventions used for storing values in registers and memory, accessing the MPC603e registers, and representation of data in these registers.

2.2.1 Floating-Point Execution Models—UISA

The IEEE 754 standard includes 64- and 32-bit arithmetic. The standard requires that single-precision arithmetic be provided for single-precision operands. The standard permits double-precision arithmetic instructions to have either (or both) single-precision or double-precision operands, but states that single-precision arithmetic instructions should not accept double-precision operands.

The PowerPC UISA follows these guidelines:

• Double-precision arithmetic instructions may have single-precision operands but always produce double-precision results.

• Single-precision arithmetic instructions require all operands to be single-precision and always produce single-precision results.

For arithmetic instructions, conversions from double- to single-precision must be done explicitly by software, while conversions from single- to double-precision are done implicitly.

All implementations of the Power PC architecture provide the equivalent of the following execution models to ensure that identical results are obtained. The definition of the arithmetic instructions for infinities, denormalized numbers, and NaNs follow conventions described in the following sections.

Although the double-precision format specifies an 11-bit exponent, exponent arithmetic uses two additional bit positions to avoid potential transient overflow conditions. An extra bit is required when denormalized double-precision numbers are prenormalized. A second bit is required to permit computation of the adjusted exponent value in the following examples when the corresponding exception enable bit is one:

• Underflow during multiplication using a denormalized factor

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Operand Conventions

• Overflow during division using a denormalized divisor

2.2.2 Data Organization in Memory and Data Transfers

Bytes in memory are numbered consecutively starting with 0. Each number is the address of the corresponding byte.

Memory operands may be bytes, half words, words, or double words, or, for the load/store multiple and move assist instructions, a sequence of bytes or words. The address of a memory operand is the address of its first byte (that is, of its lowest-numbered byte). Operand length is implicit for each instruction.

2.2.3 Alignment and Misaligned Accesses

The operand of a single-register memory access instruction has a natural alignment boundary equal to the operand length. In other words, the natural address of an opera nd is an integral multiple of the operand length . A memory operand is s aid to be aligned if it is aligned at its natural boundary; otherwise it is misaligned.

Operands for single-register memory access instructions have the characteristics shown in Table 2-9. (Although not permitted as memory operands, quad words are shown because quad-word alignment is desirable for certain memory operands.)

Table 2-9. Memory Operands

Operand Length

Byte 8 bits xxxx Half word 2 bytes xxx0 Word 4 bytes x x00 Double word 8 bytes x000 Quad word 16 bytes 0000 Note: An x in an address bit position ind icates that

the bit can be 0 or 1 independent of the state of other address bits.

The concept of alignment is also applied more generally to data in memory. For example,

Addr[28–31]

If Aligned

a 12-byte data item is said to be word-aligned if its address is a multiple of 4. Implementation Notes—The following describes how the MP C603e handles alignment

and misaligned accesses:

• The MPC603e provides hardware support for some misaligned memory accesses. However, misaligned accesses suffer a performance degradation compared to aligned accesses of the same type.

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• The MPC603e does not provide hardware support for floating-point load/store operations that are not word-aligned. In such a case, the MPC603e invokes an alignment exception and the exception handler must break up the misaligned access. For this reason, floating-point single- and double-word accesses should always be word-aligned. Note that a floating-point double-word access on a word-aligned boundary requires an extra cycle to complete.

Any half-word, word, double-word, and string reference access that crosses an alignment boundary must be broken into multiple discrete accesses. For string accesses, the hardware makes no attempt to get aligned to reduce the number of accesses. (Multiple word accesses are architecturally required to be aligned.) The resulting performance degradation depends upon how well each individual access behaves with respect to the memory hierarchy. At a minimum, additional cache access cycles are required. More dramatically, each discrete access to a noncacheable page involves an individual bus operation that reduces the effective bus bandwidth.

Instruction Set Summary

The frequent use of misaligned accesses is discouraged because they c an compromise the overall performance.

2.2.4 Floating-Point Operands

The MPC603e provides hardware support for all single- and double-precision floating-point operations for most value representations and all rounding modes. The PowerPC architecture provides for hardware to implement a floating-point system as defined in ANSI/IEEE Standard 754-1985, IEEE Standard for Binary Floating Point Arithmetic. For detailed information about the floating-point execution model, refer to Chapter 3, “Operand Conventions,” in the Programming Environments Manual.

2.2.5 Effect of Operand Placement on Performance

The VEA states that the placement (location and alignment) of operands in memory affect the relative performance of memory accesses. The best performance is guaranteed if memory operands are aligned on natural boundari es. To obtain the best performance from the MPC603e, the programmer should assume the performance model described in Chapter 3, “Operand Conventions,” in the Programming Environments Manual.

2.3 Instruction Set Summary

This section describes instructions and addressing modes defined for the MPC603e. These instructions are divided into the following functional categories:

• Integer instructions—These include arithmetic and logical instructions. For more information, see Section 2.3.4.1, “Integer Instructions.”

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Instruction Set Summary

• Floating-point instructions—These include floating-point arithmetic instructions, as well as instructions that affect the floating-point status and control register (FPSCR). For more information, see Section 2.3.4.2, “Floating-Point Instructions.”

• Load and store instructions—These include integer and floating-point load and store instructions. For more information, see Section 2.3.4.3, “Load and Store Instructions.”

• Flow control instructions—These include branching instructions, condition register logical instructions, and other instructions that affect the instruction flow . For more information, see Section 2.3.4.4, “Branch and Flow Control Instructions.”

• Trap instructions—These are used to test for a specified set of conditions; see Section 2.3.4.5, “Trap Instructions.”

• Processor control instructions—These are used for synchronizing memory accesses and managing caches, TLBs, and segment registers. For more information, see Section 2.3.4.6, “Processor Control Instructions,” Section 2.3.5.1, “Processor Control Instructions,” and Section 2.3.6.2, “Processor Control Instructions—OEA.”

• Memory synchronization instructions—These are used for synchronizing memory accesses. See Section 2.3.4.7, “Memory Synchronization Instructions—UISA” and Section 2.3.5.2, “Memory Synchronization Instructions—VEA.”

• Memory control instructions—These provide control of caches, TLBs, and segment registers. For more information, see Section 2.3.5.3, “Memory Control Instructions—VEA,” and Section 2.3.6.3, “Memory Control Instructions—OEA.”

• System linkage instructions—These include the System Call (sc) and Return from Interrupt (rfi) instructions. See Section 2.3.6.1, “System Linkage Instructions.”

• External control instructions—These include instructions for use with special input/output devices. See Section 2.3.5.4, “External Control Instructions.”

Note that this grouping of instructions does not necessarily indicate the execution unit that processes a particular instruction or group of instructions. This information, which is useful in taking full advantage of the MPC603e superscalar parallel instruction execution, is provided in Chapter 8, “Instruction Set,” of the Programming Environments Manual.

Integer instructions operate on word operands. Floating-point instructions operate on single- and double-precision floating-point operands. The PowerPC instructions are 4-byte words. The UISA provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs. It also provides for word and double-word operand loads and stores between memory and a set of 32 FPRs.

Arithmetic and logical instructions do not read or modify memory. To use the contents of a memory location in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written to the tar get location using load and store instructions.

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The description of each instruction includes the mnemonic and a formatted list of operands. To simplify assembly language programming, a set of simplified mnemonics (extended mnemonics in the architecture specification) and symbols is provided for some of the

frequently-used instructions; see Appendix F, “Simplified Mnemonics,” in the Programming Envir onments Manual for a complete list of simplified mnemonic examples.

Instruction Set Summary

2.3.1 Classes of Instructions

The MPC603e instructions belong to one of the following three classes:

• Defined

• Illegal

• Reserved

Note that although the definitions of these terms are consistent among the processors of this family, the assignment of these cl assifications is not. For example, an instruction that is specific to 64-bit implementations is considered defined for 64-bit implementations but illegal for 32-bit implementations such as the MPC603e.

The class is determined by examining the primary opcode and the extended opcode, if any. If either is not that of a defined instruction or of a rese rved instruction, the instruction is illegal.

In future versions of the PowerPC architecture, instruction codings that are now illegal may become assigned to instructions in the architecture or may be reserved by being assigned to processor-specific instructions.

2.3.1.1 Definition of Boundedly Undefined

If instructions are encoded with incorrectly set bits in reserved fields, the results on execution can be said to be boundedly undefined. If a user-level program executes the incorrectly coded instruction, the resulting undefined results are bounded in that a spurious change from user to supervisor state is not allowed, and the level of privilege exercised by the program in relation to memory access and other system resources cannot be exceeded. Boundedly undefined results for a given i nstruction may vary between implementations, and between execution attempts in the same implementation.

2.3.1.2 Defined Instruction Class

Defined instructions are guaranteed to be supported in all implementations of the Power PC architecture, except as stated in the instruction descriptions in Chapter 8, “Instruction Set,” in the Programming Environments Manual. The MPC603e provides hardware support for all instructions defined for 32-bit implementations.

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Instruction Set Summary

A processor of this family invokes the illegal instruction error handler (part of the program exception) when it encounters PowerPC instructions that have not been implemented. The instructions can be emulated in software, as required.

A defined instruction can have invalid forms, as described in the following section.

2.3.1.3 Illegal Instruction Class

Illegal instructions are grouped into the following categories:

• Instructions not defined in the PowerPC architecture. These opcodes are available for future extensions of the PowerPC architecture; that is, future versions of the architecture may define any of these instructions to perform new functions.

The following primary opcodes are defined as illegal but may be used in future extensions to the architecture:

1, 4, 5, 6, 9, 22, 56, 57, 60, 61

• Instructions defined in the PowerPC architecture but not implemented in a specific implementation. For example, instructions that can be executed on 64-bit processors are considered illegal by 32-bit processors.

The following primary opcodes are defined for 64-bit implementations only and are illegal on the MPC603e:

2, 30, 58, 62

• All unused extended opcodes are illegal. The unused extended opcodes can be determined from information in Section A.2, “Instructions Sorted by Opcode,” and Section 2.3.1.4, “Reserved Instruction Class.” Notice that extended opcodes for instructions that are defined only for 64-bit implementations are illegal in 32-bit implementations, and vice versa.

The following primary opcodes have unused extended opcodes:

17, 19, 31, 59, 63 (primary opcodes 30 and 62 are illegal for all 32-bit implementations, but as 64-bit opcodes they have some unused extended opcodes)

• An instruction consisting entirely of zeros is guaranteed to be an illegal instruction. This increases the probability that an attempt to execute data or uninitialized memory invokes the system illegal instruction error handler (a program exception). Note that if only the primary opcode consists of all zeros, the instruction is considered a reserved instruction. This is further described in Section 2.3.1.4, “Reserved Instruction Class.”

An attempt to execute an illegal instruction invokes the illegal instruction error handler (a program exception) but has no other effect. Section 4.5.7, “Program Exception (0x00700),” describes illegal and invalid instruction exceptions.

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Except for an instruction consisting entirely of binary zeros, illegal instructions are available for further additions to the PowerPC architecture.

Instruction Set Summary

2.3.1.4 Reserved Instruction Class

Reserved instructions are allocated to specific implementation-dependent purposes not defined by the PowerPC architecture. An attempt to execute an unimp lemented reserved instruction invokes the illegal instruction error handler (a program exception). See

Section 4.5.7, “Program Exception (0x00700),” for additional information about illegal and invalid instruction exceptions.

The following types of instructions are included in this class:

• Implementation-specific instructions (for example, Load Data TLB Entry (tlbld) and Load Instruction TLB Entry (tlbli) instructions)

• Optional instructions defined by the PowerPC architecture but not implemented by the MPC603e (for example, Floating Square Root (fsqrt) and Floating Square Root Single (fsqrts) instructions)

2.3.2 Addressing Modes

This section provides an overview of conventions for addressing memory and calcula ting effective addresses as defined by the PowerPC architecture for 32-bit implementations. For more detailed information, see “Conventions” in Chapter 4, “Addressing Modes and Instruction Set Summary,” of the Programming Environments Manual.

2.3.2.1 Memory Addressing

A program references memory using the effective (logical) address computed by the processor when it executes a memory access or branch instruction or when it fetch es the next sequential instruction.

Bytes in memory are numbered consecutively starting with zero. Each number is the address of the corresponding byte.

2.3.2.2 Memory Operands

Memory operands may be bytes, half words, words, or double words, or, for the load/store multiple and load/store string instructions, a sequence of bytes or words. The address of a memory operand is the address of its first byte (that is, of its lowest-numbered byte). Operand length is implicit for each instruction. The PowerPC architecture supports both big-endian and little-endian byte ordering. The default byte and bit ordering is big-endian. See “Byte Ordering” in Chapter 3, “Operand Conventions,” in the Programming Environments Manual for more information about big-endian and little-endian byte ordering.

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The operand of a single-register memory access instruction has a natural alignment

boundary equal to the operand length. In other words, the ‘natural’ address of an op erand is an integral multiple of the operand length. A me mory operand i s said to be aligned if it is aligned at its natural boundary; otherwise it is misaligned. For a detailed discussion about memory operands, see Chapter 3, “Operand Conventions,” in the Programming Environments Manual.

2.3.2.3 Effective Address Calculation

An effective address (EA) is the 32-bit sum computed by the processor when executi ng a memory access or branch instruction or when fetching th e next se quential in struction. For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the memory operand is considered to wrap around from the maximum effective address through effective address 0, as described in the following paragraphs.

Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored.

Load and store operations have three categories of effective address generation:

• Register indirect with immediate index mode

• Register indirect with index mode

• Register indirect mode

Section 2.3.4.3.2, “Integer Load and Store Address Generation,” describes effective address generation for load and store operations.

Branch instructions have three categories of effective address generation:

• Immediate

• Link register indirect

• Count register indirect

Section 2.3.4.4.1, “B ranch Instruction Address Calculation,” describes branch instru ction effective address generation.

2.3.2.4 Synchronization

The sychronization described in this section refers to the state of the processor performing the sychronization.

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Instruction Set Summary

2.3.2.4.1 Context Synchronization

The System Call (sc) and Return from Interrupt (rfi) instructions perform context synchronization by allowing previously issued instructions to complete before performing a change in context. Execution of one of these instructions ensures the following:

• No higher priority exception exists (sc).

• All previous instructions have completed to a point where they can no longer cause an exception. If a prior memory access instruction causes direct-store error exceptions, the results are guaranteed to be determined before this instruction is executed.

• Previous instructions complete execution in the context (privilege, protection, and address translation) under which they were issued.

• The instructions following the sc or rfi instruction execute in the context established by these instructions.

2.3.2.4.2 Execution Synchronization

An instruction is execution synchronizing if all previously initiated instructions appear to have completed before the instruction is initiated or, in the case of the Synchronize (sync) and Instruction Synchronize (isync) instructions, before the instruction completes. For example, the Move to Machine State Register (mtmsr) instruction is execution synchronizing. It ensures that all preceding instructions have completed execution and will not cause an exception before the instruction executes but does not ensure subsequent instructions execute in the newly established environment. For example, if the mtmsr sets MSR[PR], unless an isync immediately follows the mtmsr instruction, a privileged instruction could be executed or privileged access could be performed without causi ng an exception even though MSR[PR] indicates user mode.

2.3.2.4.3 Instruction-Related Exceptions

There are two kinds of exceptions in the MPC603e—those caused directly by the execution of an instruction and those caused by an asynchronous event. Either may cause components of the system software to be invoked.

Exceptions can be caused directly by the execution of an instruction as follows:

• An attempt to execute an illegal instruction causes the illegal instruction (program exception) handler to be invoked. An attempt by a user-level program to execute the supervisor-level instructions listed below causes the privileged instruction (program exception) handler to be invoked. The MPC603e provides the following supervisor-level instructions: dcbi, mfmsr, mfspr, mfsr, mfsrin, mtmsr, mtspr,

mtsr, mtsrin, rfi, tlbie, tlbsync, tlbld, and tlbli. Note that the privilege level of the mfspr and mtspr instructions depends on the SPR encoding.

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• An attempt to access memory that is not available (page fault) causes the ISI exception handler to be invoked.

• An attempt to access memory with an effective address alignment that is invalid for the instruction causes the alignment exception handler to be invoked.

• The execution of an sc instruction invokes the system call exception handler that permits a program to request the system to perform a service.

• The execution of a trap instruction invokes the program exception trap handler.

• The execution of a floating-point instruction when floating-point instructions are disabled or unavailable invokes the floating-point unavailable exception handler.

• The execution of an instruction that causes a floating-point exception while exceptions are enabled in the MSR invokes the program exception handler.

Exceptions caused by asynchronous events are described in Chapter 4, “Exceptions.”

2.3.3 Instruction Set Overview

This section provides a brief overview of the PowerPC instructions implemented in the MPC603e and highlights any special information with respect to how the MPC603e implements a particular instruction. Note that the categories used in this section correspond to those used in Chapter 4, “Addressing Modes and Instruction Set Summary,” in the Programming Envir onments Manual. These categorizations are somewhat arbitrary and are provided for the convenience of the programmer and do not necessarily reflect the PowerPC architecture specification.

Note that some of the instructions have the following optional features:

• CR Update—The dot (.) suffix on the mnemonic enables the update of the CR.

• Overflow option—The o suffix indicates that the overflow bit in the XER is enabled.

2.3.4 PowerPC UISA Instructions

The UISA includes the base user-level instruction set (excluding a few user-level cache control, synchronization, and time base instructions), user-level registers, programming model, data types, and addressing modes. This section discusses the instructions defined in the UISA.

2.3.4.1 Integer Instructions

This section describes the integer instructions. These consist of the following:

• Integer arithmetic instructions

• Integer compare instructions

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Instruction Set Summary

• Integer logical instructions

• Integer rotate and shift instructions

Integer instructions use the content of the GPRs as source operands and place results into GPRs, into the XER, and into condition register (CR) fields.

2.3.4.1.1 Integer Arithmetic Instructions

Table 2-10 lists the integer arithmetic instructions for the MPC603e.

Table 2-10. Integer Arithmetic Instructions

Name Mnemonic Operand Syntax

Add add (add. addo addo.) rD,rA,rB Add Carrying addc (addc. addco addco.) rD,rA,rB Add Extended adde (adde. addeo addeo.) rD,rA,rB Add Immediate addi rD,rA,SIMM Add Immediate Carrying addic rD,rA,SIMM Add Immediate Carrying and Record addic. rD,rA,SIMM Add Immediate Shifted addis rD,rA,SIMM Add to Minus One Extended addme (addme. addmeo addmeo.) rD,rA Add to Zero Extended addze (addze. addzeo addzeo.) rD,rA Divide Word divw (divw. divwo divwo.) rD,rA,rB Divide Word Unsigned divwu (divwu. divwuo divwuo.) rD,rA,rB Multiply High Word mulhw (mulhw.) rD,rA,rB Multiply High Word Unsigned mulhwu (mulhwu.) rD,rA,rB Multiply Low mullw (mullw. mullwo mullwo.) rD,rA,rB Multiply Low Immediate mulli rD,rA,SIMM Negate neg (neg. nego nego.) rD,rA Subtract From subf (subf. subfo subfo.) rD,rA,rB Subtract From Carrying subfc (subfc. subfco subfco.) rD,rA,rB Subtract From Extended subfe (subfe. subfeo subfeo.) rD,rA,rB Subtract From Immediate Carrying subfic rD,rA,SIMM

Subtract From Minus One Extended subfme (subfme. subfmeo subfmeo.) rD,rA Subtract From Zero Extended subfze (subfze. subfzeo subfzeo.) rD,rA

Although there is no Subtract Immediate instruction, its effect can be achieved by using an addi instruction with the immediate operand negated. Simplified mnemonics are provided that include this negation. The subf instructions subtract the second operand (rA) from the third operand (rB). Simplified mnemonics are provided in which the third operand is

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Instruction Set Summary

subtracted from the second operand. See Appendix F, “Simplified Mnemonics,” in the

Programming Environments Manual for examples.

2.3.4.1.2 Integer Compare Instructions

The integer compare instructions algebraically or logically compare the contents of rA with either the UIMM operand, the SIMM operand, or the contents of rB. T he comparison is signed for the cmpi and cmp instructions, and unsigned for the cmpli and cmpl instructions. Table 2-11 lists the integer compare instructions.

Table 2-11. Integer Compare Instructions

Name Mnemonic Operand Syntax

Compare cmp crfD,L,rA,rB Compare Immediate cmpi crfD,L,rA,SIMM Compare Logical cmpl crfD,L,rA,rB Compare Logical Immediate cmpli crfD,L,rA,UIMM

The crfD operand can be omitted if the result of the comparison is to be placed in CR0. Otherwise, the target CR field must be specified in the instruction crfD field.

For more information refer to Appendix F, “Simplifi ed Mnemonics,” in the Programming Environments Manual.

2.3.4.1.3 Integer Logical Instructions

The logical instructions shown in Table 2-12 perform bit-parallel operations. Logical instructions with the CR update enabled and instructions andi. and andis. set CR field CR0 to characterize the result of the logical operation. These fields are set as if the sign-extended low-order 32 bits of the result were algebraically compared to zero. Logical instructions without CR update and the remaining logical instructions do not modif y the CR. Logical instructions do not affect the XER[SO], XER[OV], and XER[CA] bits.

For simplified mnemonics examples for the integer logical operations see Appendix F, “Simplified Mnemonics,” in the Programming Environments Manual.

AND and (and.) rA,rS,rB

Table 2-12. Integer Logical Instructions

Name Mnemonic Operand Syntax

AND Immediate andi. rA,rS,UIMM AND Immediate Shifted andis. rA,rS,UIMM AND with Complement andc (andc.) rA,rS,rB Count Leading Zeros Word cntlzw (cntlzw.) rA,rS Equivalent eqv (eqv.) rA,rS,rB

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Table 2-12. Integer Logical Instructions (continued)

Name Mnemonic Operand Syntax

Extend Sign Byte extsb (extsb.) rA,rS Extend Sign Half Word extsh (extsh.) rA,rS NAND nand (nand.) rA,rS,rB NOR nor (nor.) rA,rS,rB OR or (or.) rA,rS,rB OR Immediate ori rA,rS,UIMM OR Immediate Shifted oris rA,rS,UIMM OR with Complement orc (orc.) rA,rS,rB XOR xor (xor.) rA,rS,rB XOR Immediate xori rA,rS,UIMM XOR Immediate Shifted xo ris rA,rS,UIMM

2.3.4.1.4 Integer Rotate and Shift Instructions

Instruction Set Summary

Rotation operations are performed on data from a GPR, and the result, or a portion of the result, is returned to a GPR. See Appendix F, “Simplified Mnemonics,” in the

Programming Environmments Manual for a complete list of simplified mnemonics that allows simpler coding of often-used functions such as clearing the leftmost or rightm ost bits of a register, left justifying or right justifying an arbitrary field, and simple rotates and shifts.

Integer rotate instructions rotate the contents of a register. The result of the rotation is either inserted into the target register under control of a mask (if a mask bit is 1, the associated bit of the rotated data is placed int o the target register; an d if the mask bit is 0, the associated bit in the target register is unchanged), or ANDed with a mask before being placed into the target register.

The integer rotate instructions are listed in Table 2-13.

Table 2-13. Integer Rotate Instructions

Rotate Left Word Immediate then AND with Mask rlwinm (rlwinm.) rA,rS,SH,MB,ME Rotate Left Word Immediate then Mask Insert rlwimi (rlwimi.) rA,rS,SH,MB,ME Rotate Left Word then AND with Mask rlwnm (rlwnm.) rA,rS,rB,MB,ME

Name Mnemonic Operand Syntax

The integer shift instructions perform left and right shifts. Immediate-form logical (unsigned) shift operations are obtained by specifying masks and shift values for certain rotate instructions. Simplified mnemonics are provided, making coding of such shifts simpler and easier to understand.

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Multiple-precision shifts can be programmed as shown in Appendix C, “Multiple-Precision Shifts,” in the Programming Environments Manual.

The integer shift instructions are listed in Table 2-14.

Table 2-14. Integer Shift Instructions

Name Mnemonic Operand Syntax

Shift Left Word slw (slw.) rA,rS,rB Shift Right Algebraic Word sraw (sraw.) rA,rS,rB Shift Right Algebraic Word Immediate srawi (srawi.) rA,rS,SH Shift Right Word srw (srw.) rA,rS,rB

2.3.4.2 Floating-Point Instructions

This section describes the floating-point instructions, which include the following:

• Floating-point arithmetic instructions

• Floating-point multiply-add instructions

• Floating-point rounding and conversion instructions

• Floating-point compare instructions

• Floating-point status and control register instructions

• Floating-point move instructions

See Section 2.3.4.3, “Load and Store Instructions,” for information about floating-point loads and stores.

The PowerPC architecture supports a floating-point system as defined in the IEEE 754 standard, but requires software support to conform with that standard. All floating-point operations conform to the IEEE 754 standard, except if software sets the non-IEEE mode bit (NI) in the FPSCR. The MPC603e is in the nondenormalized mode when the NI bit is set in the FPSCR. If a denormalized result is produced, a default result of zero is generated. The generated zero has the same sign as the denormalized number. The MPC603e performs single- and double-precision floating-point operations compliant with the IEEE 754 floating-point standard.

Implementation Note—Single-precision denormalized results require two additional processor clock cycles to round. When loading or storing a single-precision denormalized number, the load/store unit may take up to 24 processor clock cycles to convert between the internal double-precision format and the external single-precision format.

2.3.4.2.1 Floating-Point Arithmetic Instructions

The floating-point arithmetic instructions are listed in Table 2-15.

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Specifications and Main Features

Frequently Asked Questions

User Manual

About This Book

1.1 Overview

1.1.1 Features

1.1.2 System Design and Programming Considerations

1.1.2.1 Hardware Features

1.1.2.1.2 Addition of Half-Clock Bus Multipliers

1.1.2.2 Software Features

1.1.2.2.1 16-Kbyte Instruction and Data Caches

1.1.2.2.2 Clock Configuration Available in HID1 Register

1.1.2.2.3 Performance Enhancements

1.1.3 Instruction Unit

1.1.3.1 Instruction Queue and Dispatch Unit

1.1.3.2 Branch Processing Unit (BPU)

1.1.4 Independent Execution Units

1.1.4.1 Integer Unit (IU)

1.1.4.2 Floating-Point Unit (FPU)

1.1.4.3 Load/Store Unit (LSU)

1.1.4.4 System Register Unit (SRU)

1.1.4.5 Completion Unit

1.1.5 Memory Subsystem Support

1.1.5.1 Memory Management Units (MMUs)

1.1.5.2 Cache Units

1.1.6 Processor Bus Interface

1.1.7 System Support Functions

1.1.7.1 Power Management

1.1.7.2 Time Base/Decrementer

1.1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface

1.1.7.4 Clock Multiplier

1.2 PowerPC Architecture Implementation

1.3 Implementation-Specific Informatio n

1.3.1 Programming Model

1.3.1.1 Processor Version Register (PVR)

1.3.1.2 Hardware Implementation Register 0 (HID0)

1.3.1.3 General-Purpose Registers (GPRs)

1.3.1.4 Floating-Point Registers (FPRs)

1.3.1.5 Condition Register (CR)

1.3.1.6 Floating-Point Status and Control Register (FPSCR)

1.3.1.7 Machine State Register (MSR)

1.3.1.8 Segment Registers (SRs)

1.3.1.9 Special-Purpose Registers (SPRs)

1.3.1.9.1 User-Level SPRs

1.3.1.9.2 Supervisor-Level SPRs

1.3.2 Instruction Set and Addressing Modes

1.3.2.1 PowerPC Instruction Set and Addressing Modes

1.3.2.2 Implementation-Specific Instruction Set

1.3.3 Cache Implementation

1.3.3.1 PowerPC Cache Characteristics

1.3.3.2 Implementation-Specific Cache Implementation

1.3.4 Exception Model

1.3.4.1 PowerPC Exception Model

1.3.4.2 Implementation-Specific Exception Model

1.3.5 Memory Management

1.3.5.1 PowerPC Memory Management

1.3.5.2 Implementation-Specific Memory Management

1.3.6 Instruction Timing

1.3.7 System Interface

1.3.7.1 Memory Accesses

1.3.7.2 Signals

1.3.7.3 Signal Configuration

2.1 Register Set

2.1.1 PowerPC Register Set

2.1.2 Implementation-Specific Registers

2.1.2.1 Hardware Implementation Registers (HID0 and HID1)

2.1.2.2 Data and Instruction TLB Miss Address Registers (DMISS and IMISS)

2.1.2.3 Data and Instruction TLB Compare Registers (DCMP and ICMP)

2.1.2.4 Primary and Secondary Hash Address Registers (HASH1 and HASH2)

2.1.2.5 Required Physical Address Register (RPA)

2.1.2.6 Instruction Address Breakpoint Register (IABR)

2.2 Operand Conventions

2.2.1 Floating-Point Execution Models—UISA

2.2.2 Data Organization in Memory and Data Transfers

2.2.3 Alignment and Misaligned Accesses

2.2.4 Floating-Point Operands

2.2.5 Effect of Operand Placement on Performance

2.3 Instruction Set Summary

2.3.1 Classes of Instructions