Freescale MPC603E User Manual

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Q2/02

REV 3

MPC603e RISC Microprocessor

User’s Manual

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Overview

Programming Model

Instruction and Data Cache Operation

Exceptions

Memory Management

Instruction Timing

Signal Descriptio ns

System Interface Operation

Power Management

1
2
3
4
5
6
7
8
9

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PowerPC Instruction Set Listings

Instructions Not Implemented

Revision History

Glossary of Terms and Abbrev iations

Index

A
B
C

GLO

IND

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1
2
3
4

4
5
6
7
8
9

Overview
Programming Model
Instruction and Data Cache Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Power Management

emiconduct

eescale S
Fr

GLO

IND

A
B
C

PowerPC Instruction Set Listings
Instructions Not Implemented
Revision History

Glossary of Terms and Abbrev iations
Index

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Contents

Contents

Paragraph

Section
Number Title

Number Title

About This Book

Chapter 1

Overview

1.1 Overview.............................................................................................................. 1-1

1.1.1 Features ........................................................................................................... 1-3

1.1.2 System Design and Programming Considerations...........................................1-6

1.1.2.1 Hardware Features.......................................................................................1-6

1.1.2.1.1 Replacement of XATS

1.1.2.1.2 Addition of Half-Clock Bus Multipliers.................................................. 1-7

1.1.2.2 Software Features ........................................................................................1-7

1.1.2.2.1 16-Kbyte Instruction and Data Caches.................................................... 1-7

1.1.2.2.2 Clock Configuration Available in HID1 Register ................................... 1-7

1.1.2.2.3 Performance Enhancements .................................................................... 1-7

1.1.3 Instruction Unit................................................................................................ 1-8

1.1.3.1 Instruction Queue and Dispatch Unit .......................................................... 1-8

1.1.3.2 Branch Processing Unit (BPU).................................................................... 1-9

1.1.4 Independent Execution Units...........................................................................1-9

1.1.4.1 Integer Unit (IU).......................................................................................... 1-9

1.1.4.2 Floating-Point Unit (FPU)......................................................................... 1-10

1.1.4.3 Load/Store Unit (LSU).............................................................................. 1-10

1.1.4.4 System Register Unit (SRU)...................................................................... 1-10

1.1.4.5 Completion Unit ........................................................................................ 1-11

1.1.5 Memory Subsystem Support.......................................................................... 1-11

1.1.5.1 Memory Management Units (MMUs)....................................................... 1-11

1.1.5.2 Cache Units................................................................................................ 1-12

1.1.6 Processor Bus Interface ................................................................................. 1-13

1.1.7 System Support Functions............................................................................. 1-14

1.1.7.1 Power Management ................................................................................... 1-14

1.1.7.2 Time Base/Decrementer ............................................................................1-15

1.1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface.................................................. 1-15

1.1.7.4 Clock Multiplier.........................................................................................1-15

1.2 PowerPC Architecture Implementation............................................................. 1-15

Signal by CSE1 Signal....................................... 1-6

Page

Page
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Paragraph
Number Title

1.3 Implementation-Specific Information................................................................ 1-16

1.3.1 Programming Model...................................................................................... 1-17

1.3.1.1 Processor Version Register (PVR)............................................................. 1-17

1.3.1.2 Hardware Implementation Register 0 (HID0)........................................... 1-17

1.3.1.3 General-Purpose Registers (GPRs)............................................................ 1-19

1.3.1.4 Floating-Point Registers (FPRs)................................................................ 1-19

1.3.1.5 Condition Register (CR)............................................................................ 1-19

1.3.1.6 Floating-Point Status and Control Register (FPSCR) ...............................1-19

1.3.1.7 Machine State Register (MSR).................................................................. 1-20

1.3.1.8 Segment Registers (SRs) ...........................................................................1-20

1.3.1.9 Special-Purpose Registers (SPRs)............................................................. 1-20

1.3.1.9.1 User-Level SPRs.................................................................................... 1-20

1.3.1.9.2 Supervisor-Level SPRs..........................................................................1-21

1.3.2 Instruction Set and Addressing Modes.......................................................... 1-22

1.3.2.1 PowerPC Instruction Set and Addressing Modes...................................... 1-22

1.3.2.2 Implementation-Specific Instruction Set................................................... 1-24

1.3.3 Cache Implementation................................................................................... 1-24

1.3.3.1 PowerPC Cache Characteristics ................................................................ 1-24

1.3.3.2 Implementation-Specific Cache Implementation...................................... 1-24

1.3.4 Exception Model............................................................................................1-26

1.3.4.1 PowerPC Exception Model........................................................................1-26

1.3.4.2 Implementation-Specific Exception Model............................................... 1-28

1.3.5 Memory Management....................................................................................1-30

1.3.5.1 PowerPC Memory Management................................................................ 1-30

1.3.5.2 Implementation-Specific Memory Management....................................... 1-31

1.3.6 Instruction Timing ......................................................................................... 1-32

1.3.7 System Interface ............................................................................................ 1-33

1.3.7.1 Memory Accesses...................................................................................... 1-34

1.3.7.2 Signals........................................................................................................ 1-35

1.3.7.3 Signal Configuration.................................................................................. 1-36

Page

Number

2.1 Register Set.......................................................................................................... 2-1

2.1.1 PowerPC Register Set......................................................................................2-2

2.1.2 Implementation-Specific Registers..................................................................2-6

2.1.2.1 Hardware Implementation Registers (HID0 and HID1).............................. 2-6

2.1.2.2 Data and Instruction TLB Miss Address Registers

(DMISS and IMISS).............................................................................. 2-10

2.1.2.3 Data and Instruction TLB Compare Registers (DCMP and ICMP).......... 2-10

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Chapter 2

Programming Model

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2.1.2.4 Primary and Secondary Hash Address Registers

(HASH1 and HASH2)........................................................................... 2-11

2.1.2.5 Required Physical Address Register (RPA)............................................... 2-12

2.1.2.6 Instruction Address Breakpoint Register (IABR)...................................... 2-12

2.2 Operand Conventions ........................................................................................ 2-13

2.2.1 Floating-Point Execution Models—UISA..................................................... 2-13

2.2.2 Data Organization in Memory and Data Transfers........................................ 2-14

2.2.3 Alignment and Misaligned Accesses............................................................. 2-14

2.2.4 Floating-Point Operands................................................................................ 2-15

2.2.5 Effect of Operand Placement on Performance .............................................. 2-15

2.3 Instruction Set Summary ................................................................................... 2-15

2.3.1 Classes of Instructions................................................................................... 2-17

2.3.1.1 Definition of Boundedly Undefined.......................................................... 2-17

2.3.1.2 Defined Instruction Class .......................................................................... 2-17

2.3.1.3 Illegal Instruction Class............................................................................. 2-18

2.3.1.4 Reserved Instruction Class ........................................................................ 2-19

2.3.2 Addressing Modes .........................................................................................2-19

2.3.2.1 Memory Addressing ..................................................................................2-19

2.3.2.2 Memory Operands ..................................................................................... 2-19

2.3.2.3 Effective Address Calculation................................................................... 2-20

2.3.2.4 Synchronization ........................................................................................ 2-20

2.3.2.4.1 Context Synchronization .......................................................................2-21

2.3.2.4.2 Execution Synchronization....................................................................2-21

2.3.2.4.3 Instruction-Related Exceptions ............................................................. 2-21

2.3.3 Instruction Set Overview............................................................................... 2-22

2.3.4 PowerPC UISA Instructions..........................................................................2-22

2.3.4.1 Integer Instructions.................................................................................... 2-22

2.3.4.1.1 Integer Arithmetic Instructions.............................................................. 2-23

2.3.4.1.2 Integer Compare Instructions ................................................................2-24

2.3.4.1.3 Integer Logical Instructions................................................................... 2-24

2.3.4.1.4 Integer Rotate and Shift Instructions..................................................... 2-25

2.3.4.2 Floating-Point Instructions ........................................................................ 2-26

2.3.4.2.1 Floating-Point Arithmetic Instructions.................................................. 2-26

2.3.4.2.2 Floating-Point Multiply-Add Instructions............................................. 2-27

2.3.4.2.3 Floating-Point Rounding and Conversion Instructions......................... 2-28

2.3.4.2.4 Floating-Point Compare Instructions..................................................... 2-28

2.3.4.2.5 Floating-Point Status and Control Register Instructions....................... 2-28

2.3.4.2.6 Floating-Point Move Instructions.......................................................... 2-29

2.3.4.3 Load and Store Instructions....................................................................... 2-29

2.3.4.3.1 Self-Modifying Code ............................................................................ 2-30

2.3.4.3.2 Integer Load and Store Address Generation.......................................... 2-30

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Number Title

2.3.4.3.3 Register Indirect Integer Load Instructions........................................... 2-30

2.3.4.3.4 Integer Store Instructions....................................................................... 2-31

2.3.4.3.5 Integer Load and Store with Byte-Reverse Instructions........................2-32

2.3.4.3.6 Integer Load and Store Multiple Instructions........................................ 2-32

2.3.4.3.7 Integer Load and Store String Instructions............................................ 2-33

2.3.4.3.8 Floating-Point Load and Store Address Generation..............................2-34

2.3.4.3.9 Floating-Point Load Instructions........................................................... 2-34

2.3.4.3.10 Floating-Point Store Instructions........................................................... 2-35

2.3.4.4 Branch and Flow Control Instructions....................................................... 2-36

2.3.4.4.1 Branch Instruction Address Calculation................................................ 2-36

2.3.4.4.2 Branch Instructions................................................................................2-37

2.3.4.4.3 Condition Register Logical Instructions................................................ 2-37

2.3.4.5 Trap Instructions........................................................................................ 2-38

2.3.4.6 Processor Control Instructions................................................................... 2-38

2.3.4.6.1 Move To/From Condition Register Instructions....................................2-38

2.3.4.7 Memory Synchronization Instructions—UISA......................................... 2-38

2.3.5 PowerPC VEA Instructions........................................................................... 2-40

2.3.5.1 Processor Control Instructions................................................................... 2-40

2.3.5.2 Memory Synchronization Instructions—VEA.......................................... 2-41

2.3.5.3 Memory Control Instructions—VEA........................................................ 2-41

2.3.5.4 External Control Instructions..................................................................... 2-43

2.3.6 PowerPC OEA Instructions........................................................................... 2-43

2.3.6.1 System Linkage Instructions...................................................................... 2-43

2.3.6.2 Processor Control Instructions—OEA ...................................................... 2-44

2.3.6.2.1 Move To/From Machine State Register Instructions.............................2-44

2.3.6.2.2 Move To/From Special-Purpose Register Instructions..........................2-44

2.3.6.3 Memory Control Instructions—OEA........................................................ 2-45

2.3.6.3.1 Supervisor-Level Cache Management Instruction ................................ 2-45

2.3.6.3.2 Segment Register Manipulation Instructions ........................................ 2-46

2.3.6.3.3 Translation Lookaside Buffer Management Instructions ...................... 2-46

2.3.7 Recommended Simplified Mnemonics.......................................................... 2-47

2.3.8 Implementation-Specific Instructions............................................................2-47

Page

Number

Chapter 3

Instruction and Data Cache Operation

3.1 Instruction Cache Organization and Control ....................................................... 3-3

3.1.1 Instruction Cache Organization....................................................................... 3-3

3.1.2 Instruction Cache Fill Operations.................................................................... 3-4

3.1.3 Instruction Cache Control................................................................................ 3-4

3.1.3.1 Instruction Cache Invalidation..................................................................... 3-4

3.1.3.2 Instruction Cache Disabling ........................................................................ 3-4

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Number Title

3.1.3.3 Instruction Cache Locking........................................................................... 3-5

3.2 Data Cache Organization and Control................................................................. 3-5

3.2.1 Data Cache Organization................................................................................. 3-5

3.2.2 Data Cache Fill Operations..............................................................................3-6

3.2.3 Data Cache Control.......................................................................................... 3-6

3.2.3.1 Data Cache Invalidation .............................................................................. 3-6

3.2.3.2 Data Cache Disabling ..................................................................................3-7

3.2.3.3 Data Cache Locking .................................................................................... 3-7

3.2.3.4 Data Cache Operations and Address Broadcasts......................................... 3-7

3.2.4 Data Cache Touch Load Support..................................................................... 3-8

3.3 Basic Data Cache Operations .............................................................................. 3-8

3.3.1 Data Cache Fill ................................................................................................3-8

3.3.2 Data Cache Cast-Out Operation ...................................................................... 3-8

3.3.3 Cache Block Push Operation........................................................................... 3-9

3.4 Data Cache Transactions on Bus .........................................................................3-9

3.4.1 Single-Beat Transactions................................................................................. 3-9

3.4.2 Burst Transactions ........................................................................................... 3-9

3.4.3 Access to Direct-Store Segments................................................................... 3-10

3.5 Memory Management/Cache Access Mode Bits—W, I, M, and G................... 3-10

3.5.1 Write-Through Attribute (W) ........................................................................ 3-11

3.5.2 Caching-Inhibited Attribute (I)...................................................................... 3-12

3.5.3 Memory Coherency Attribute (M)................................................................. 3-12

3.5.4 Guarded Attribute (G).................................................................................... 3-13

3.5.5 W, I, and M Bit Combinations....................................................................... 3-13

3.5.5.1 Out-of-Order Execution and Guarded Memory ........................................ 3-14

3.5.5.2 Effects of Out-of-Order Data Accesses..................................................... 3-14

3.5.5.3 Effects of Out-of-Order Instruction Fetches.............................................. 3-15

3.6 Cache Coherency—MEI Protocol .....................................................................3-15

3.6.1 MEI State Definitions.................................................................................... 3-16

3.6.2 MEI State Diagram........................................................................................ 3-16

3.6.3 MEI Hardware Considerations ......................................................................3-17

3.6.4 Coherency Precautions .................................................................................. 3-19

3.6.4.1 Coherency in Single-Processor Systems ................................................... 3-19

3.6.5 Load and Store Coherency Summary............................................................ 3-19

3.6.6 Atomic Memory References.......................................................................... 3-20

3.6.7 Cache Reaction to Specific Bus Operations.................................................. 3-20

3.6.8 Operations Causing ARTRY Assertion ......................................................... 3-21

3.6.9 Enveloped High-Priority Cache Block Push Operation ................................ 3-22

3.7 Cache Control Instructions ................................................................................3-22

3.7.1 Data Cache Block Invalidate (dcbi) Instruction............................................ 3-24

3.7.2 Data Cache Block Touch (dcbt) Instruction.................................................. 3-24

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3.7.3 Data Cache Block Touch for Store (dcbtst) Instruction................................ 3-24

3.7.4 Data Cache Block Clear to Zero (dcbz) Instruction...................................... 3-24

3.7.5 Data Cache Block Store (dcbst) Instruction.................................................. 3-25

3.7.6 Data Cache Block Flush (dcbf) Instruction...................................................3-25

3.7.7 Enforce In-Order Execution of I/O Instruction (eieio) ..................................3-25

3.7.8 Instruction Cache Block Invalidate (icbi) Instruction ...................................3-26

3.7.9 Instruction Synchronize (isync) Instruction ..................................................3-26

3.8 Bus Operations Caused by Cache Control Instructions.....................................3-26

3.9 Bus Interface......................................................................................................3-27

3.10 MEI State Transactions......................................................................................3-28

Chapter 4

Exceptions

4.1 Exception Classes ................................................................................................ 4-2

4.1.1 Exception Priorities..........................................................................................4-6

4.1.2 Summary of Front-End Exception Handling................................................... 4-8

4.2 Exception Processing........................................................................................... 4-9

4.2.1 Exception Processing Registers....................................................................... 4-9

4.2.1.1 SRR0 and SRR1 Bit Settings....................................................................... 4-9

4.2.1.2 MSR Bit Settings....................................................................................... 4-11

4.2.2 Enabling and Disabling Exceptions............................................................... 4-13

4.2.3 Steps for Exception Processing...................................................................... 4-13

4.2.4 Setting MSR[RI]............................................................................................ 4-14

4.2.5 Returning from an Exception Handler........................................................... 4-14

4.3 Process Switching.............................................................................................. 4-15

4.4 Exception Latencies........................................................................................... 4-15

4.5 Exception Definitions ........................................................................................ 4-16

4.5.1 Reset Exceptions (0x00100).......................................................................... 4-17

4.5.1.1 Hard Reset and Power-On Reset ...............................................................4-17

4.5.1.2 Soft Reset...................................................................................................4-18

4.5.2 Machine Check Exception (0x00200) ...........................................................4-19

4.5.2.1 Machine Check Exception Enabled (MSR[ME] = 1)................................ 4-20

4.5.2.2 Checkstop State (MSR[ME] = 0) ..............................................................4-20

4.5.3 DSI Exception (0x00300).............................................................................. 4-21

4.5.4 ISI Exception (0x00400)................................................................................ 4-23

4.5.5 External Interrupt (0x00500)......................................................................... 4-23

4.5.6 Alignment Exception (0x00600) ...................................................................4-24

4.5.6.1 Integer Alignment Exceptions................................................................... 4-25

4.5.6.2 Load/Store Multiple Alignment Exceptions.............................................. 4-26

4.5.7 Program Exception (0x00700).......................................................................4-27

4.5.7.1 IEEE Floating-Point Exception Program Exceptions................................ 4-27

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4.5.7.2 Illegal, Reserved, and Unimplemented Instructions

Program Exceptions............................................................................... 4-28

4.5.8 Floating-Point Unavailable Exception (0x00800)......................................... 4-28

4.5.9 Decrementer Exception (0x00900)................................................................ 4-28

4.5.10 System Call Exception (0x00C00) ................................................................4-29

4.5.11 Trace Exception (0x00D00)........................................................................... 4-29

4.5.11.1 Single-Step Instruction Trace Mode.......................................................... 4-30

4.5.11.2 Branch Trace Mode ................................................................................... 4-30

4.5.12 Instruction TLB Miss Exception (0x01000).................................................. 4-30

4.5.13 Data TLB Miss on Load Exception (0x01100)..............................................4-31

4.5.14 Data TLB Miss on Store Exception (0x01200)............................................. 4-32

4.5.15 Instruction Address Breakpoint Exception (0x01300) ..................................4-32

4.5.16 System Management Interrupt (0x01400)..................................................... 4-34

Chapter 5

Memory Management

5.1 MMU Features..................................................................................................... 5-2

5.1.1 Memory Addressing ........................................................................................5-3

5.1.2 MMU Organization..........................................................................................5-3

5.1.3 Address Translation Mechanisms.................................................................... 5-8

5.1.4 Memory Protection Facilities.........................................................................5-10

5.1.5 Page History Information............................................................................... 5-11

5.1.6 General Flow of MMU Address Translation................................................. 5-11

5.1.6.1 Real Addressing Mode and Block Address Translation Selection............ 5-11

5.1.6.2 Page Address Translation Selection ..........................................................5-12

5.1.7 MMU Exceptions Summary..........................................................................5-14

5.1.8 MMU Instructions and Register Summary.................................................... 5-17

5.2 Real Addressing Mode....................................................................................... 5-19

5.3 Block Address Translation................................................................................. 5-20

5.4 Memory Segment Model ................................................................................... 5-20

5.4.1 Page History Recording................................................................................. 5-21

5.4.1.1 Referenced Bit ........................................................................................... 5-22

5.4.1.2 Changed Bit............................................................................................... 5-22

5.4.1.3 Scenarios for Referenced and Changed Bit Recording ............................. 5-23

5.4.2 Page Memory Protection ............................................................................... 5-24

5.4.3 TLB Description............................................................................................ 5-24

5.4.3.1 TLB Organization...................................................................................... 5-25

5.4.3.2 TLB Entry Invalidation.............................................................................. 5-26

5.4.4 Page Address Translation Summary.............................................................. 5-27

5.5 Page Table Search Operation............................................................................. 5-27

5.5.1 Page Table Search Operation—Conceptual Flow ......................................... 5-27

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5.5.2 Implementation-Specific Table Search Operation......................................... 5-31

5.5.2.1 Resources for Table Search Operations..................................................... 5-31

5.5.2.1.1 Data and Instruction TLB Miss Address Registers

(DMISS and IMISS)..........................................................................5-33

5.5.2.1.2 Data and Instruction TLB Compare Registers (DCMP and ICMP)...... 5-34

5.5.2.1.3 Primary and Secondary Hash Address Registers

(HASH1 and HASH2)....................................................................... 5-34

5.5.2.1.4 Required Physical Address Register (RPA) .......................................... 5-35

5.5.2.2 Software Table Search Operation .............................................................. 5-36

5.5.2.2.1 Flow for Example Exception Handlers ................................................. 5-36

5.5.2.2.2 Code for Example Exception Handlers ................................................. 5-40

5.5.3 Page Table Updates........................................................................................5-47

5.5.4 Segment Register Updates............................................................................. 5-47

Chapter 6

Instruction Timing

6.1 Terminology and Conventions............................................................................. 6-1

6.2 Instruction Timing Overview............................................................................... 6-3

6.3 Timing Considerations......................................................................................... 6-7

6.3.1 General Instruction Flow................................................................................. 6-8

6.3.2 Instruction Fetch Timing................................................................................6-10

6.3.2.1 Cache Arbitration....................................................................................... 6-10

6.3.2.2 Cache Hit................................................................................................... 6-10

6.3.2.3 Cache Miss................................................................................................. 6-13

6.3.3 Instruction Dispatch and Completion Considerations................................... 6-15

6.3.3.1 Rename Register Operation....................................................................... 6-15

6.3.3.2 Instruction Serialization.............................................................................6-16

6.3.3.3 Execution Unit Considerations.................................................................. 6-17

6.4 Execution Unit Timings.....................................................................................6-17

6.4.1 Branch Processing Unit Execution Timing....................................................6-17

6.4.1.1 Branch Folding ..........................................................................................6-17

6.4.1.2 Static Branch Prediction............................................................................ 6-18

6.4.1.2.1 Predicted Branch Timing Examples...................................................... 6-19

6.4.2 Integer Unit Execution Timing...................................................................... 6-21

6.4.3 Floating-Point Unit Execution Timing.......................................................... 6-21

6.4.4 Load/Store Unit Execution Timing................................................................6-22

6.4.5 System Register Unit Execution Timing....................................................... 6-22

6.5 Memory Performance Considerations ...............................................................6-22

6.5.1 Copy-Back Mode........................................................................................... 6-23

6.5.2 Write-Through Mode..................................................................................... 6-23

6.5.3 Cache-Inhibited Accesses.............................................................................. 6-23

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6.6 Instruction Scheduling Guidelines.....................................................................6-24

6.6.1 Branch, Dispatch, and Completion Unit Resource Requirements.................6-25

6.6.1.1 Branch Resolution Resource Requirements ..............................................6-25

6.6.1.2 Dispatch Unit Resource Requirements...................................................... 6-25

6.6.1.3 Completion Unit Resource Requirements................................................. 6-26

6.7 Instruction Latency Summary............................................................................6-26

Chapter 7

Signal Descriptions

7.1 Signal Configuration............................................................................................7-2

7.2 Signal Descriptions.............................................................................................. 7-2

7.2.1 Address Bus Arbitration Signals......................................................................7-2

7.2.1.1 Bus Request (BR)—Output......................................................................... 7-3

7.2.1.2 Bus Grant (BG)—Input ...............................................................................7-4

7.2.1.3 Address Bus Busy (ABB)............................................................................ 7-4

7.2.1.3.1 Address Bus Busy (ABB

7.2.1.3.2 Address Bus Busy (ABB)—Input ...........................................................7-5

7.2.2 Address Transfer Start Signals.........................................................................7-5

7.2.2.1 Transfer Start (TS)....................................................................................... 7-6

7.2.2.1.1 Transfer Start (TS)—Output.................................................................... 7-6

7.2.2.1.2 Transfer Start (TS)—Input ......................................................................7-6

7.2.3 Address Transfer Signals................................................................................. 7-6

7.2.3.1 Address Bus (A[0:31])................................................................................. 7-6

7.2.3.1.1 Address Bus (A[0:31])—Output ............................................................. 7-7

7.2.3.1.2 Address Bus (A[0:31])—Input................................................................ 7-7

7.2.3.2 Address Bus Parity (AP[0:3])...................................................................... 7-7

7.2.3.2.1 Address Bus Parity (AP[0:3])—Output................................................... 7-7

7.2.3.2.2 Address Bus Parity (AP[0:3])—Input .....................................................7-8

7.2.3.3 Address Parity Error (APE)—Output.......................................................... 7-8

7.2.4 Address Transfer Attribute Signals.................................................................. 7-8

7.2.4.1 Transfer Type (TT[0:4])............................................................................... 7-9

7.2.4.1.1 Transfer Type (TT[0:4])—Output ........................................................... 7-9

7.2.4.1.2 Transfer Type (TT[0:4])—Input.............................................................. 7-9

7.2.4.2 Transfer Size (TSIZ[0:2])—Output........................................................... 7-12

7.2.4.3 Transfer Burst (TBST)...............................................................................7-12

7.2.4.3.1 Transfer Burst (TBST)—Output............................................................7-12

7.2.4.3.2 Transfer Burst (TBST)—Input.............................................................. 7-13

7.2.4.4 Transfer Code (TC[0:1])—Output............................................................. 7-13

7.2.4.5 Cache Inhibit (CI)—Output....................................................................... 7-13

7.2.4.6 Write-Through (WT)—Output.................................................................. 7-14

7.2.4.7 Global (GBL).............................................................................................7-14

)—Output......................................................... 7-5

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7.2.4.7.1 Global (GBL)—Output.......................................................................... 7-14

7.2.4.7.2 Global (GBL

7.2.4.8 Cache Set Entry (CSE[0:1])—Output ....................................................... 7-14

7.2.5 Address Transfer Termination Signals........................................................... 7-15

7.2.5.1 Address Acknowledge (AACK)—Input.................................................... 7-15

7.2.5.2 Address Retry (ARTRY

7.2.5.2.1 Address Retry (ARTRY

7.2.5.2.2 Address Retry (ARTRY

7.2.6 Data Bus Arbitration Signals......................................................................... 7-16

7.2.6.1 Data Bus Grant (DBG

7.2.6.2 Data Bus Write Only (DBWO

7.2.6.3 Data Bus Busy (DBB) ............................................................................... 7-18

7.2.6.3.1 Data Bus Busy (DBB)—Output............................................................ 7-18

7.2.6.3.2 Data Bus Busy (DBB)—Input............................................................... 7-18

7.2.7 Data Transfer Signals..................................................................................... 7-18

7.2.7.1 Data Bus (DH[0:31], DL[0:31]) ................................................................ 7-18

7.2.7.1.1 Data Bus (DH[0:31], DL[0:31])—Output............................................. 7-19

7.2.7.1.2 Data Bus (DH[0:31], DL[0:31])—Input................................................ 7-19

7.2.7.2 Data Bus Parity (DP[0:7]) ......................................................................... 7-19

7.2.7.2.1 Data Bus Parity (DP[0:7])—Output...................................................... 7-19

7.2.7.2.2 Data Bus Parity (DP[0:7])—Input......................................................... 7-20

7.2.7.3 Data Parity Error (DPE)—Output ............................................................. 7-20

7.2.7.4 Data Bus Disable (DBDIS)—Input........................................................... 7-21

7.2.8 Data Transfer Termination Signals................................................................ 7-21

7.2.8.1 Transfer Acknowledge (TA)—Input.......................................................... 7-21

7.2.8.2 Data Retry (DRTRY)—Input..................................................................... 7-22

7.2.8.3 Transfer Error Acknowledge (TEA

7.2.9 System Status Signals.................................................................................... 7-23

7.2.9.1 Interrupt (INT

7.2.9.2 System Management Interrupt (SMI

7.2.9.3 Machine Check Interrupt (MCP)—Input................................................... 7-24

7.2.9.4 Checkstop Input (CKSTP_IN)—Input...................................................... 7-24

7.2.9.5 Checkstop Output (CKSTP_OUT)—Output............................................. 7-24

7.2.9.6 Reset Signals.............................................................................................. 7-25

7.2.9.6.1 Hard Reset (HRESET)—Input.............................................................. 7-25

7.2.9.6.2 Soft Reset (SRESET)—Input................................................................ 7-25

7.2.9.7 Processor Status Signals............................................................................ 7-26

7.2.9.7.1 Quiescent Request (QREQ)................................................................... 7-26

7.2.9.7.2 Quiescent Acknowledge (QACK)......................................................... 7-26

7.2.9.7.3 Reservation (RSRV)—Output ............................................................... 7-27

7.2.9.7.4 Time Base Enable (TBEN)—Input .......................................................7-27

)—Input ............................................................................ 7-14

)............................................................................ 7-15

)—Output ........................................................7-15

)—Input........................................................... 7-16

)—Input.................................................................. 7-17

)—Input ..................................................... 7-17

)—Input .............................................7-22

)—Input............................................................................... 7-23

)—Input ........................................... 7-23

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7.2.9.7.5 TLBI Sync (TLBISYNC)...................................................................... 7-27

7.2.10 COP/Scan Interface........................................................................................ 7-27

7.2.11 Pipeline Tracking Support............................................................................. 7-28

7.2.12 Clock Signals.................................................................................................7-29

7.2.12.1 System Clock (SYSCLK)—Input.............................................................. 7-29

7.2.12.2 Test Clock (CLK_OUT)—Output............................................................. 7-30

7.2.12.3 PLL Configuration (PLL_CFG[0:3])—Input............................................ 7-30

7.2.13 Power and Ground Signals ............................................................................7-32

Chapter 8

System Interface Operation

8.1 Overview.............................................................................................................. 8-1

8.1.1 Operation of the Instruction and Data Caches................................................. 8-2

8.1.2 Operation of the System Interface................................................................... 8-4

8.1.2.1 Optional 32-Bit Data Bus Mode.................................................................. 8-5

8.1.3 Direct-Store Accesses...................................................................................... 8-6

8.2 Memory Access Protocol..................................................................................... 8-6

8.2.1 Arbitration Signals...........................................................................................8-7

8.2.2 Address Pipelining and Split-Bus Transactions............................................... 8-8

8.3 Address Bus Tenure............................................................................................. 8-9

8.3.1 Address Bus Arbitration ..................................................................................8-9

8.3.2 Address Transfer............................................................................................ 8-11

8.3.2.1 Address Bus Parity ....................................................................................8-12

8.3.2.2 Address Transfer Attribute Signals............................................................8-12

8.3.2.2.1 Transfer Type (TT[0:4]) Signals............................................................8-12

8.3.2.2.2 Transfer Size (TSIZ[0:2]) Signals......................................................... 8-13

8.3.2.3 Burst Ordering During Data Transfers ...................................................... 8-13

8.3.2.4 Effect of Alignment in Data Transfers (64-Bit Bus)................................. 8-14

8.3.2.5 Effect of Alignment in Data Transfers (32-Bit Bus)................................. 8-16

8.3.2.5.1 Alignment of External Control Instructions.......................................... 8-18

8.3.2.6 Transfer Code (TC[0:1]) Signals............................................................... 8-19

8.3.3 Address Transfer Termination ......................................................................8-19

8.4 Data Bus Te nure.................................................................................................8-21

8.4.1 Data Bus Arbitration...................................................................................... 8-21

8.4.1.1 Using the DBB Signal ...............................................................................8-22

8.4.2 Data Bus Write Only......................................................................................8-22

8.4.3 Data Transfer .................................................................................................8-23

8.4.4 Data Transfer Termination............................................................................. 8-24

8.4.4.1 Normal Single-Beat Termination...............................................................8-25

8.4.4.2 Normal Burst Termination......................................................................... 8-26

8.4.4.3 Data Transfer Termination Due to a Bus Error.......................................... 8-27

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8.4.5 Memory Coherency—MEI Protocol ............................................................. 8-28

8.5 Timing Examples............................................................................................... 8-30

8.6 Optional Bus Configurations............................................................................. 8-37

8.6.1 32-Bit Data Bus Mode................................................................................... 8-37

8.6.2 No-DRTRY

8.6.3 Reduced-Pinout Mode ................................................................................... 8-40

8.7 Interrupt, Checkstop, and Reset Signals............................................................ 8-40

8.7.1 External Interrupts .........................................................................................8-40

8.7.2 Checkstops..................................................................................................... 8-40

8.7.3 Reset Inputs....................................................................................................8-41

8.7.4 System Quiesce Control Signals.................................................................... 8-41

8.8 Processor State Signals...................................................................................... 8-41

8.8.1 Support for the lwarx/stwcx. Instruction Pair............................................... 8-41

8.8.2 TLBISYNC

8.9 IEEE 1149.1-Compliant Interface......................................................................8-42

8.9.1 IEEE 1149.1 Interface Description................................................................ 8-42

8.10 Using DBWO..................................................................................................... 8-43

Mode..........................................................................................8-39

Input ..........................................................................................8-42

Page

Number

Chapter 9

Power Management

9.1 Overview.............................................................................................................. 9-1

9.2 Dynamic Power Management..............................................................................9-1

9.3 Programmable Power Modes............................................................................... 9-2

9.3.1 Power Management Modes ............................................................................. 9-3

9.3.1.1 Full-Power Mode with DPM Disabled........................................................ 9-3

9.3.1.2 Full-Power Mode with DPM Enabled......................................................... 9-3

9.3.1.3 Doze Mode................................................................................................... 9-3

9.3.1.4 Nap Mode ....................................................................................................9-4

9.3.1.5 Sleep Mode.................................................................................................. 9-5

9.3.2 Power Management Software Considerations................................................. 9-6

9.4 Example Code Sequence for Entering Processor Sleep Mode ............................9-6

Appendix A

PowerPC Instruction Set Listings

A.1 Instructions Sorted by Mnemonic....................................................................... A-1

A.2 Instructions Sorted by Opcode............................................................................ A-8

A.3 Instructions Grouped by Functional Categories ............................................... A-15

A.4 Instructions Sorted by Form ............................................................................. A-25

A.5 Instruction Set Legend...................................................................................... A-36

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Appendix B

Instructions Not Implemente d

Appendix C

Revision History

C.1 Revision Changes From Revision 2 to Revision 3..............................................C-1

C.2 Revision Changes From Revision 1 to Revision 2..............................................C-2

Glossary of Terms and Abbreviations

Index

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Figures

Figure
Number Title

1-1 MPC603e Microprocessor Block Diagram................................................................... 1-2

1-2 Programming Model—Registers................................................................................ 1-18

1-3 Data Cache Organization............................................................................................ 1-25

1-4 System Interface ......................................................................................................... 1-34

1-5 Signal Groups ............................................................................................................. 1-37

2-1 Programming Model—Registers.................................................................................. 2-3

2-2 Hardware Implementation Register 0 (HID0) ..............................................................2-6

2-3 Hardware Implementation Register 1 (HID1) ............................................................2-10

2-4 DMISS and IMISS Registers...................................................................................... 2-10

2-5 DCMP and ICMP Registers........................................................................................ 2-11

2-6 HASH1 and HASH2 Registers...................................................................................2-11

2-7 Required Physical Address Register (RPA) ...............................................................2-12

2-8 Instruction Address Breakpoint Register (IABR)....................................................... 2-12

3-1 Instruction Cache Organization .................................................................................... 3-4

3-2 Data Cache Organization.............................................................................................. 3-6

3-3 Double-Word Address Ordering—Critical Double Word First ................................. 3-10

3-4 MEI Cache Coherency Protocol—State Diagram (WIM = 001)................................3-17

3-5 Bus Interface Address Buffers.................................................................................... 3-28

4-1 Machine Status Save/Restore Register 0 (SSR0) ......................................................... 4-9

4-2 Machine Status Save/Restore Register 1 (SSR1) ......................................................... 4-9

4-3 Machine State Register (MSR)...................................................................................4-11

5-1 MMU Conceptual Block Diagram—32-Bit Implementations...................................... 5-5

5-2 IMMU Block Diagram.................................................................................................. 5-6

5-3 DMMU Block Diagram................................................................................................ 5-7

5-4 Address Translation Types ...........................................................................................5-9

5-5 General Flow of Address Translation (Real Addressing Mode and Block)............... 5-12

5-6 General Flow of Page and Direct-Store Interface Address Translation ..................... 5-13

5-7 Segment Register and TLB Organization................................................................... 5-25

5-8 Page Address Translation Flow for 32-Bit Implementations—TLB Hit.................... 5-28

5-9 Primary Page Table Search—Conceptual Flow ......................................................... 5-30

5-10 Secondary Page Table Search Flow—Conceptual Flow............................................ 5-31

5-11 DMISS and IMISS Registers...................................................................................... 5-34

5-12 DCMP and ICMP Registers........................................................................................ 5-34

5-13 HASH1 and HASH2 Registers...................................................................................5-35

5-14 Required Physical Address (RPA) Register ...............................................................5-35

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5-15 Flow for Example Software Table Search Operation................................................. 5-37

5-16 Check and Set R and C Bit Flow................................................................................ 5-38

5-17 Page Fault Setup Flow................................................................................................ 5-39

5-18 Setup for Protection Violation Exceptions .................................................................5-40

6-1 Pipelined Execution Unit.............................................................................................. 6-4

6-2 Superscalar/Pipeline Diagram....................................................................................... 6-5

6-3 MPC603e Microprocessor Pipeline Stages................................................................... 6-7

6-4 Instruction Flow Diagram............................................................................................. 6-9

6-5 Instruction Timing—Cache Hit .................................................................................. 6-11

6-6 Instruction Timing—Cache Miss................................................................................ 6-14

6-7 Branch Instruction Timing..........................................................................................6-20

7-1 Signal Groups ............................................................................................................... 7-3

7-2 IEEE 1149.1-Compliant Boundary Scan Interface..................................................... 7-28

8-1 MPC603e Microprocessor Block Diagram................................................................... 8-3

8-2 Overlapping Tenures on the Bus for a Single-Beat Transfer........................................8-6

8-3 Address Bus Arbitration .............................................................................................8-10

8-4 Address Bus Arbitration Showing Bus Parking ......................................................... 8-10

8-5 Address Bus Transfer.................................................................................................. 8-12

8-6 Snooped Address Cycle with ARTRY........................................................................8-20

8-7 Data Bus Arbitration................................................................................................... 8-22

8-8 Normal Single-Beat Read Termination ......................................................................8-25

8-9 Normal Single-Beat Write Termination ..................................................................... 8-25

8-10 Normal Burst Transaction...........................................................................................8-26

8-11 Termination with DRTRY ..........................................................................................8-27

8-12 Read Burst with TA Wait States and DRTRY............................................................ 8-28

8-13 MEI Cache Coherency Protocol—State Diagram (WIM = 001)................................8-30

8-14 Fastest Single-Beat Reads........................................................................................... 8-31

8-15 Fastest Single-Beat Writes..........................................................................................8-32

8-16 Single-Beat Reads Showing Data-Delay Controls .....................................................8-33

8-17 Single-Beat Writes Showing Data-Delay Controls .................................................... 8-34

8-18 Burst Transfers with Data-Delay Controls .................................................................8-35

8-19 Use of Transfer Error Acknowledge (TEA) ...............................................................8-36

8-20 32-Bit Data Bus Transfer (Eight-Beat Burst) ............................................................. 8-38

8-21 32-Bit Data Bus Transfer (Two-Beat Burst with DRTRY)........................................ 8-38

8-22 DBWO Transaction ....................................................................................................8-43

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Tables

Table
Number Title

i Acronyms and Abbreviated Terms........................................................................... xxxii

ii Terminology Conventions.........................................................................................xxxv

iii Instruction Field Conventions................................................................................. xxxvi

1-1 CSE[0:1] Signals ......................................................................................................... 1-7

1-2 Generated SRR1[KEY] Bit .........................................................................................1-8

1-3 Additional/Changed HID0 Bits................................................................................. 1-19

1-4 Exception Classifications ..........................................................................................1-28

1-5 Exceptions and Conditions........................................................................................ 1-28

2-1 MSR[POW] and MSR[TGPR] Bits............................................................................. 2-5

2-2 HID0 Bit Functions .....................................................................................................2-7

2-3 HID0[BCLK] and HID0[ECLK] CLK_OUT Configuration...................................... 2-9

2-4 HID1 Bit Settings...................................................................................................... 2-10

2-5 DCMP and ICMP Bit Settings .................................................................................. 2-11

2-6 HASH1 and HASH2 Bit Settings.............................................................................. 2-11

2-7 RPA Bit Settings........................................................................................................ 2-12

2-8 Instruction Address Breakpoint Register Bit Settings...............................................2-13

2-9 Memory Operands..................................................................................................... 2-14

2-10 Integer Arithmetic Instructions.................................................................................. 2-23

2-11 Integer Compare Instructions ....................................................................................2-24

2-12 Integer Logical Instructions.......................................................................................2-24

2-13 Integer Rotate Instructions ........................................................................................ 2-25

2-14 Integer Shift Instructions........................................................................................... 2-26

2-15 Floating-Point Arithmetic Instructions......................................................................2-27

2-16 Floating-Point Multiply-Add Instructions................................................................. 2-27

2-17 Floating-Point Rounding and Conversion Instructions............................................. 2-28

2-18 Floating-Point Compare Instructions ........................................................................ 2-28

2-20 Floating-Point Move Instructions..............................................................................2-29

2-21 Integer Load Instructions...........................................................................................2-31

2-22 Integer Store Instructions .......................................................................................... 2-31

2-23 Integer Load and Store with Byte-Reverse Instructions............................................ 2-32

2-24 Integer Load and Store Multiple Instructions............................................................ 2-33

2-25 Integer Load and Store String Instructions................................................................2-34

2-26 Floating-Point Load Instructions............................................................................... 2-35

2-27 Floating-Point Store Instructions............................................................................... 2-35

2-28 Branch Instructions....................................................................................................2-37

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2-29 Condition Register Logical Instructions.................................................................... 2-37

2-30 Trap Instructions........................................................................................................ 2-38

2-31 Move To/From Condition Register Instructions........................................................ 2-38

2-32 Memory Synchronization Instructions—UISA......................................................... 2-40

2-33 Move From Time Base Instruction............................................................................ 2-40

2-34 Memory Synchronization Instructions—VEA.......................................................... 2-41

2-35 User-Level Cache Instructions ..................................................................................2-42

2-36 External Control Instructions .................................................................................... 2-43

2-37 System Linkage Instructions .....................................................................................2-43

2-38 Move To/From Machine State Register Instructions................................................. 2-44

2-39 Move To/From Special-Purpose Register Instructions.............................................. 2-44

2-40 Implementation-Specific SPR Encodings (mfspr) ................................................... 2-44

2-41 Segment Register Manipulation Instructions ............................................................2-46

2-42 Translation Lookaside Buffer Management Instructions .......................................... 2-47

3-1 Combinations of W, I, and M Bits.............................................................................3-13

3-2 MEI State Definitions................................................................................................3-16

3-3 CSE[0:1] Signal Encoding ........................................................................................ 3-18

3-4 Memory Coherency Actions on Load Operations..................................................... 3-19

3-5 Memory Coherency Actions on Store Operations..................................................... 3-20

3-6 Response to Bus Transactions................................................................................... 3-20

3-7 Bus Operations Caused by Cache Control Instructions (WIM = 001)...................... 3-26

3-8 MEI State Transitions................................................................................................3-29

4-1 Exception Classifications ............................................................................................4-3

4-2 Exceptions and Conditions.......................................................................................... 4-4

4-3 Exception Priorities ..................................................................................................... 4-6

4-4 SRR1 Bit Settings for Machine Check Exceptions................................................... 4-10

4-5 SRR1 Bit Settings for Software Table Search Operations ........................................ 4-10

4-6 MSR Bit Settings....................................................................................................... 4-11

4-7 IEEE Floating-Point Exception Mode Bits ...............................................................4-13

4-8 MSR Setting Due to Exception .................................................................................4-16

4-9 Settings Caused by Hard Reset.................................................................................. 4-17

4-10 Soft Reset Exception—Register Settings.................................................................. 4-19

4-11 Machine Check Exception—Register Settings ......................................................... 4-20

4-12 DSI Exception—Register Settings ............................................................................ 4-21

4-13 External Interrupt—Register Settings .......................................................................4-24

4-14 Alignment Interrupt—Register Settings....................................................................4-25

4-15 Access Types ............................................................................................................. 4-26

4-16 Trace Exception—Register Settings.......................................................................... 4-30

4-17 Instruction and Data TLB Miss Exceptions—Register Settings............................... 4-31

4-18 Instruction Address Breakpoint Exception—Register Settings ................................ 4-32

4-19 Breakpoint Action for Multiple Modes Enabled for the Same Address.................... 4-33

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4-20 System Management Interrupt—Register Settings ................................................... 4-34

5-1 MMU Features Summary............................................................................................ 5-2

5-2 Access Protection Options for Pages.........................................................................5-10

5-3 Translation Exception Conditions............................................................................. 5-15

5-4 Other MMU Exception Conditions ........................................................................... 5-16

5-5 Instruction Summary—MMU Control...................................................................... 5-17

5-6 MMU Registers ......................................................................................................... 5-18

5-7 Table Search Operations to Update History Bits—TLB Hit Case ............................ 5-21

5-8 Model for Guaranteed R and C Bit Settings.............................................................. 5-24

5-9 Implementation-Specific Resources for Table Search Operations............................ 5-32

5-10 Implementation-Specific SRR1 Bits .........................................................................5-33

5-11 DCMP and ICMP Bit Settings .................................................................................. 5-34

5-12 HASH1 and HASH2 Bit Settings..............................................................................5-35

5-13 RPA Bit Settings........................................................................................................ 5-35

6-1 Branch Instructions.................................................................................................... 6-26

6-2 System Register Instructions..................................................................................... 6-27

6-3 Condition Register Logical Instructions.................................................................... 6-27

6-4 Integer Instructions.................................................................................................... 6-28

6-5 Floating-Point Instructions........................................................................................ 6-30

6-6 Load and Store Instructions.......................................................................................6-31

7-1 Transfer Encoding for the Bus Master.........................................................................7-9

7-2 Snoop Hit Response .................................................................................................. 7-10

7-3 Implementation-Specific Transfer Encoding............................................................. 7-11

7-4 Data Transfer Size..................................................................................................... 7-12

7-5 Encodings for TC[0:1] Signals.................................................................................. 7-13

7-6 Data Bus Lane Assignments...................................................................................... 7-19

7-7 DP[0:7] Signal Assignments .....................................................................................7-20

7-8 Pipeline Tracking Outputs......................................................................................... 7-28

7-9 CLK_OUT Signal Configuration .............................................................................. 7-30

7-10 PLL Configuration..................................................................................................... 7-31

8-1 Timing Diagram Legend..............................................................................................8-5

8-2 Transfer Size Signal Encodings................................................................................. 8-13

8-3 Burst Ordering—64-Bit Bus...................................................................................... 8-14

8-4 Burst Ordering—32-Bit Bus...................................................................................... 8-14

8-5 Aligned Data Transfers (64-Bit Bus).........................................................................8-15

8-6 Misaligned Data Transfers (4-Byte Examples)......................................................... 8-16

8-7 Aligned Data Transfers (32-Bit Bus Mode).............................................................. 8-17

8-8 Misaligned 32-Bit Data Bus Transfer (4-Byte Examples) ........................................ 8-18

8-9 Transfer Code Encoding............................................................................................ 8-19

8-10 CSE[0:1] Signals ....................................................................................................... 8-30

8-11 IEEE Interface Pin Descriptions................................................................................8-42

Page

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Tables

Table
Number Title

9-1 MPC603e Programmable Power Modes .....................................................................9-3

A-1 Complete Instruction List Sorted by Mnemonic........................................................ A-1

A-2 Complete Instruction List Sorted by Opcode............................................................. A-8

A-3 Integer Arithmetic Instructions................................................................................ A-15

A-4 Integer Compare Instructions................................................................................... A-16

A-5 Integer Logical Instructions ..................................................................................... A-16

A-6 Integer Rotate Instructions....................................................................................... A-16

A-7 Integer Shift Instructions.......................................................................................... A-17

A-8 Floating-Point Arithmetic Instructions ....................................................................A-17

A-9 Floating-Point Multiply-Add Instructions ............................................................... A-18

A-10 Floating-Point Rounding and Conversion Instructions............................................ A-18

A-11 Floating-Point Compare Instructions....................................................................... A-18

A-12 Floating-Point Status and Control Register Instructions.......................................... A-18

A-13 Integer Load Instructions ......................................................................................... A-19

A-14 Integer Store Instructions......................................................................................... A-19

A-15 Integer Load and Store with Byte-Reverse Instructions.......................................... A-20

A-16 Integer Load and Store Multiple Instructions.......................................................... A-20

A-17 Integer Load and Store String Instructions .............................................................. A-20

A-18 Memory Synchronization Instructions..................................................................... A-21

A-19 Floating-Point Load Instructions ............................................................................. A-21

A-20 Floating-Point Store Instructions............................................................................. A-21

A-21 Floating-Point Move Instructions ............................................................................ A-22

A-22 Branch Instructions .................................................................................................. A-22

A-23 Condition Register Logical Instructions.................................................................. A-22

A-24 System Linkage Instructions.................................................................................... A-22

A-25 Trap Instructions ...................................................................................................... A-23

A-26 Processor Control Instructions................................................................................. A-23

A-27 Cache Management Instructions.............................................................................. A-23

A-28 Segment Register Manipulation Instructions........................................................... A-24

A-29 Lookaside Buffer Management Instructions............................................................ A-24

A-30 External Control Instructions................................................................................... A-24

A-31 I-Form ......................................................................................................................A-25

A-32 B-Form..................................................................................................................... A-25

A-33 SC-Form................................................................................................................... A-25

A-34 D-Form..................................................................................................................... A-25

A-35 DS-Form................................................................................................................... A-27

A-36 X-Form..................................................................................................................... A-27

A-37 XL-Form .................................................................................................................. A-31

A-38 XFX-Form................................................................................................................ A-32

A-39 XFL-Form................................................................................................................ A-32

A-40 XS-Form................................................................................................................... A-32

Page

Number

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Tables

Table
Number Title

A-41 XO-Form.................................................................................................................. A-33

A-42 A-Form..................................................................................................................... A-33

A-43 M-Form.................................................................................................................... A-34

A-44 MD-Form................................................................................................................. A-35

A-45 MDS-Form............................................................................................................... A-35

A-46 PowerPC Instruction Set Legend............................................................................. A-36

B-1 32-Bit Instructions Not Implemented by the MPC603e .............................................B-1

B-2 64-Bit Instructions Not Implemented by the MPC603e .............................................B-1

B-3 64-Bit SPR Encoding Not Implemented by the MPC603e.........................................B-2

Page

Number

Tables xx

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About This Book

The primary objective of this user’s manual is to define the functionality of the MPC603e
microprocessor for use by software and hardware developers.

It is important to note that this book is to be used with the PowerPC Microprocessor

Family: The Programming Environments, referred to as the Programming Environments
Manual. Contact your sales representative to obtain a copy. Because the PowerPC

architecture is designed to be flexible to support a broad range of processors, the
Programming Envir onments Manual provides a general description of features common to
PowerPC processors and indicates those features that are optional or that may be
implemented differently in the design of each processor.

This document describes in detail the MPC603e feature s not defined by the architecture.
This document and the Programming Environments Manual distinguish between the three
levels, or programming environments, of the PowerPC architecture, which are as follows:

• User instruction set architecture (UISA)—The UISA defines the architecture level
to which user-level software should conform. The UISA defines the base user-level
instruction set, user-level registers, data types, memory conventions, and the
memory and programming models seen by application programmers.

• Virtual environment architecture (VEA)—The VEA, which is the smallest
component of the PowerPC architecture, defines additional user-level functionality
that falls outside typical user-level software requirements. The VEA describes the
memory model for an environment in which multiple processors or other devices
can access external memory, and defines aspects of the cache model and cache
control instructions from a user-level perspective. The resources defined by the
VEA are particularly useful for optimizing memory accesses and managing
resources in an environment in which other processors and devices can access
external memory.

Implementations that conform to the VEA also conform to the UISA but may not
necessarily adhere to the OEA.

• Operating environment architecture (OEA)—The OEA defines supervisor-level
resources typically required by an operating system. The OEA defines the memory
management model, supervisor-level registers, and exception model.

Implementations that conform to the OEA also conform to the UISA and VEA.

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Audience

Note that some resources are defined more generally at one level in the architecture and
more specifically at another. For example, conditions that cause a floating-point exception
are defined by the UISA, while the exception mechanism is defined by the OEA.

Because it is important to distinguish between the levels of the architecture to ensure
compatibility across multiple platforms, those distinctions are shown clearly throughout
this book.

For ease in reference, topics in this book are arranged to build on one another, beginning
with a description and complete summary of MPC603e-specific reg isters and progres sing
to more specialized topics such as MPC603e-specific details regarding the cache,
exception, and memory management models. As such, chapters may inc lude information
from multiple levels of the architectu re. For example, the discussion of the c ache model
uses information from both the VEA and the OEA.

The PowerPC Architecture: A Specification for a New Family of RISC Processors defines
the architecture from the perspective of the three programming environments and remains
the defining document for the PowerPC architecture.

The information in this book is subject to change without notice, as described in the

disclaimers on the title page. As with any technical documentation, it is the readers’
responsibility to be sure they are using the most recent version of the documentation. For
updates to this document, refer to: http://www.freescale.com.

Audience

This manual is intended for system software and hardware developers and applications
programmers who want to develop products using the MPC603e microprocessors. It is
assumed that the reader understands operating systems, microprocessor system design,
basic principles of RISC processing, and details of the PowerPC architecture.

Organization

The following summary briefly describes the major sections of this manual:

• Chapter 1, “Overview,” is useful for readers who want a general understanding of
the features and functions of the PowerPC architecture and the MPC603e. This
chapter describes the flexible nature of the PowerPC architecture definition and
provides an overview of how the PowerPC architecture defines the register set,
operand conventions, addressing modes, instruction set, cache model, exception
model, and memory management model.

• Chapter 2, “Programming Model,” provides a brief synopsis of the registers
implemented on the MPC603e, operand conventions, an overview of the PowerPC
addressing modes, and a list of the instructions implemented by the MPC603e.
Instructions are organized by function.

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• Chapter 3, “Instruction and Data Cache Operation,” provides a discussion of the
cache and memory model as implemented on the MPC603e.

• Chapter 4, “Exceptions,” describes the exception model defined in the OEA and the
specific exception model implemented on the MPC603e.

• Chapter 5, “Memory Management,” describes MPC603e implementation of the
memory management unit specified by the OEA.

• Chapter 6, “Instruction Timing,” provides information about latencies, interlocks,
special situations, and various conditions to help make programming more efficient.
This chapter is of special interest to software engineers and system designers.

• Chapter 7, “Signal Descriptions,” provides descriptions of individual signals of the
MPC603e.

• Chapter 8, “System Interface Operation,” describes signal timings for various
operations. It also provides information for interfacing to the MPC603e.

Suggested Reading

• Chapter 9, “Power Management,” provides information about power saving modes
for the MPC603e.

• Appendix A, “PowerPC Instruction Set Listings,” lists all the PowerPC instructions
while indicating those instructions that are not implemented by the MPC603e; it also
includes the instructions that are specific to the MPC603e. Instructions are grouped
according to mnemonic, opcode, function, and form. Also included is a quick
reference table that contains general information, such as the architecture level,
privilege level, and form, and indicates if the instruction is 64-bit and optional.

• Appendix B, “Instructions Not Implemented,” provides a list of PowerPC
instructions not implemented by the MPC603e.

• Appendix C, “Revision History,” lists the major differences between Revision 1,
Revision 2, and Revision 3 of the MPC603e RISC Microprocessor User’s Manual.

• This manual also includes a glossary and an index.

Suggested Reading

This section lists additional reading that provides background for the information in this
manual as well as general information about the PowerPC architecture.

General Information

The following documentation, available through Morgan-Kaufmann Publishers, 340 Pine
Street, Sixth Floor, San Francisco, CA, provides useful information about the PowerPC
architecture and computer architecture in general:

• The PowerPC Architecture: A Specification for a New Family of RISC Processors,
Second Edition, by International Business Machines, Inc.

For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html.

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Suggested Reading

• PowerPC Microprocessor Common Hardware Reference Platform: A System
Architecture, by Apple Computer, Inc., International Business Machines, Inc. and

Freescale Semmiconductor, Inc.

• Computer Architecture: A Quantitative Approach, Second Edition, by
John L. Hennessy and David A. Patterson

• Computer Organization and Design: The Hardware/Software Interface, Second
Edition, David A. Patterson and John L. Hennessy

• Inside Macintosh: PowerPC System Software, Addison-Wesley Publishing
Company, One Jacob Way, Reading, MA, 01867; Tel. [phone] (U.S.A.),
[phone] (Canada), [phone] (International).

Related Documentation

Freescale documentation is available from the sources listed on the back cover of this
manual; the document order numbers are included in parentheses for ease in ordering:

• Programming Environments Manual for 32-Bit Implementations of the PowerPC
Architecture (MPCFPE32B/AD)—Describes resources defined by the PowerPC

architecture.

• User’s manuals—These books provide details about individual implementations and
are intended for use with the Programming Environments Manual.

• Addenda/errata to user’s manuals—Because some processors have follow-on parts
an addendum is provided that describes the additional features and functionality
changes. These addenda are intended for use with the corresponding user’s manual.

• Implementation Variances Relative to Rev. 1 of The Programming Environments
Manual is available at http://www.freescale.com

• Hardware specifications—Hardware specifications provide specific data regarding
bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as
other design considerations.

• Technical Summaries—Each device has a technical summary that provides an
overview of its features. This document is roughly the equivalent to the overview
(Chapter 1) of an implementation’s user’s manual.

• The Programmer’s Reference Guide for the PowerPC Architecture
(MPCPRG/D)—This concise reference includes the register summary, memory
control model, exception vectors, and the PowerPC instruction set.

• The Programmer’s Pocket Reference Guide for the PowerPC Architecture
(MPCPRGREF/D)—This foldout card provides an overview of PowerPC registers,
instructions, and exceptions for 32-bit implementations.

• Application notes—These short documents contain useful information about
specific design issues useful to programmers and engineers working with Freescale
processors.

MPC603e RISC Microprocessor User’s Manual