Freescale MPC184UM User Manual

MPC184 Security Co-Processor

User’s Manual

PCI Interface

Preliminary—Subject to Change Without Notice

MPC184UM

Rev. 2, 12/2005

How to Reach Us:

Home Page:

www.freescale.com

email:

[e-mail]

USA/Europe or Locations Not Listed:

Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
[phone]
480-768-2130
[e-mail]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
[e-mail]

Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
[phone]
[e-mail]

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
[phone]
[e-mail]

For Literature Requests Only:

Freescale Semiconductor

Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
[phone]
303-675-2140
Fax: [phone]
LDCForFreescaleSemiconductor

@hibbertgroup.com

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in whi ch the failure of the Freescale Semiconductor produc t

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor

and its officers, employees, subsidiaries, affiliates, and distributors har mless against all

claims, costs, damages, and expenses, and reasonable attor ney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the d esign or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners.

© Freescale Semiconductor, Inc., 2005. All rights reserved.

Document Number: MPC184UM
Rev. 2, 12/2005

Preliminary—Subject to Change Without Notice

Overview

1

Signal Descriptions

Address Map

PCI Configuration Registers

Execution Units

MPC184 Descriptors

Crypto-Channels

Controller

PCI Interface Module

2

3

4

5

6

7

8

9

Execution Units in 32-Bit Big Endian View

Controller in 32-Bit Big Endian View

User’s Manual Revision History

Preliminary—Subject to Change Without Notice

Index

A

B

C

IND

1

Overview

2

3

4

5

6

7

8

9

Signal Descriptions

Address Map

PCI Configuration Registers

Execution Units

MPC184 Descriptors

Crypto-Channels

Controller

PCI Interface Module

A

Execution Units in 32-Bit Big Endian View

B Controller in 32-Bit Big Endian View

C

IND

User’s Manual Revision History

Index

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

Chapter 1

Overview

1.1 Develop m e n t H i st o ry...... ................................................................................................. 1 - 1

1.2 T ypical Applications ........................................................................................................ 1-1

1.3 Features............................................................................................................................ 1-1

1.4 T ypical System Architecture............................................................................................ 1-3

1.5 Archi te c t u ral Overv i e w.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ........................................................ 1-4

1.6 Data Pac k et Descrip tors................................................................................................... 1-5

1.6.1 Externa l Bu s In t erface ................................................................................................. 1-6

1.6.2 The MPC1 84 Co n t roller ..... ....................................... .................................................. 1-7

1.6.3 Host-Managed Register Access................................................................................... 1-7

1.6.4 Static EU Access.......................................................................................................... 1-7

1.6.5 Dynamic EU Access.................................................................................................... 1-7

1.6.6 Crypto-Channels.......................................................................................................... 1-8

1.7 Execut io n Un its (EUs) .... .................. ............................................................................... 1 - 8

1.7.1 Public Key Ex ecution U n i t (PKEU) ............................................................................ 1-9

1.7.1.1 Elliptic Curve Operations........................... ........ .......... .......... .......... .......... .......... ...1-9

1.7.1.2 Modular Exponentiation Operations...................................................................... 1-10

1.7.2 Data Encryptio n Stand a rd Execut i o n U n i t ( D EU )..... ................................................ 1- 1 0

1.7.3 Arc Four Execution Unit (AFEU) ............................................................................. 1-10

1.7.4 Advance d En crypti o n Stand ard Execution Un i t (AESU).......................................... 1-11

1.7.5 M essage Digest Execution Unit (MDEU) Module.................................................... 1-11

1.7.6 Random Number Generator (RNG)........................... .......... ............ .......... ............ .... 1-11

1.7.7 8KB General Purpo s e RA M (gpRAM ) .. ....................................... ............................ 1- 1 2

1.8 Perfor m a n ce Estimates ....... ........................................................................................... 1 - 1 2

1.9 User’s Manual Revis i o n History... ............................................................... .................. 1 -12

Chapter 2

Signal Descriptions

2.1 Signal Descriptions ..........................................................................................................2-1

2.2 MPC184 Pin Out. .............................................................................................................2-4

Chapter 3

Address Map

3.1 Address Map .................................................................................................................... 3-1

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor v

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

Chapter 4

PCI Configuration Registers

4.1 PCI Configuration Space ................................................................................................. 4-1

4.1.1 PCI Vendor ID Register (offset 0x0000) ..................................................................... 4-2

4.1.2 PCI Device ID Register (offset 0x0002)...................................................................... 4-2

4.1.3 PCI Command Register (offset 0x0004) ..................................................................... 4-2

4.1.4 PCI Status Register (offset 0x0006) ............................................................................ 4-3

4.1.5 R evision ID Register (offset 0x0008).......................................................................... 4-4

4.1.6 Class Code Register (offset 0x0009)........................................................................... 4-4

4.1.7 Cache Line Size Register (offset 0x000C) .......................... ............ .......... ............ ...... 4- 4

4.1.8 L atency T imer Register (offset 0x000D).....................................................................4-5

4.1.9 Header -Type Register (offset 0x000E) ........................................................................4-5

4.1.10 BIST Register (offset 0x000F) ....................................................................................4-5

4.1.11 Base Address Register Zero (offset 0x0010)............................................................... 4- 5

4.1.12 Base Address Register 1 (offset 0x0014) ....................................................................4-6

4.1.13 Base Address Register 2 (offset 0x0018) ....................................................................4-6

4.1.14 Base Address Register 3 (offset 0x001C).................................................................... 4-6

4.1.15 Base Address Register 4 (offset 0x0020) ....................................................................4-6

4.1.16 Base Address Register 5 (offset 0x0024) ....................................................................4-7

4.1.17 CardBus CIS Pointer Register (offset 0x0028)............................................................ 4-7

4.1.18 Subsystem Vendor ID Register (offset 0x002C).......................................................... 4-7

4.1.19 Subsystem ID Register (offset 0x002E) ......................................................................4-7

4.1.20 Expansion ROM Base Address Register (offset 0x0030) ........................................... 4-8

4.1.21 Capabilities Pointer (offset 0x0034)............................................................................4-8

4.1.22 Interrupt Line Register (offset 0x003C) ...................................................................... 4-8

4.1.23 Interrupt Pin Register (offset 0x003D)........................................................................4-8

4.1.24 Min_GNT Register (offset 0x003D)............................................................................ 4-8

4.1.25 Max_Lat Register (offset 0x003F) ..............................................................................4-9

Chapter 5

Execution Units

5.1 Public Key Ex ecution Un its (PKE U )............................................................................... 5-2

5.1.1 PKEU Regi ster Map .................................................................... ................................ 5-2

5.1.2 PKEU Mode Re g i ster ....... ........................................................................................... 5 - 2

5.1.3 PKEU Key Si ze Regist e r .... ................................................................................. ........ 5-4

5.1.4 PKEU Data Siz e Regist er ......................... ................................................................... 5 -5

5.1.5 PKEU Rese t Co n tr o l Re g i st e r..... ............................................................... .................. 5 -5

5.1.6 PKEU Statu s Re g i st e r. ....................................... .......................................................... 5- 6

5.1.7 PKEU Inte r rupt Statu s Reg ister.. ................................................... .............................. 5 -8

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

vi Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

5.1.8 PKEU Interrupt Control Register ................................................................................ 5-9

5.1.9 PKEU EU_GO Regist e r....................................................... ...................................... 5-10

5.1.10 PKEU Parameter Me m o ries....................................................................................... 5-11

5.1.10 .1 PKEU Para meter Memo r y A ...... ........................................................................... 5 -11

5.1.10 .2 PKEU Para meter Memo r y B ................................................................................. 5 - 11

5.1.10 .3 PKEU Para meter Memo r y E ................................................................................. 5-11

5.1.10 .4 PKEU Para meter Memo r y N ...... ........................................................................... 5 -11

5.2 Data Encryption Standard Execution Units (DEU) ....................................................... 5-11

5.2.1 DEU Regis ter Map.. ................................................................................................... 5-12

5.2.2 DEU Mode Re g is t e r................................................. .................................................. 5-12

5.2.3 DEU Key Size Regist e r .... ........................................................................... .............. 5-13

5.2.4 DEU Data S ize Regist er . ........................................................................................... 5 -14

5.2.5 DEU Reset Co n t ro l Re g i ster..................... ................................................................. 5- 1 5

5.2.6 DEU Status Re g i ster ..... ..................................................................... ........................ 5 -16

5.2.7 DEU Interrupt Status Register ................................................................................... 5-17

5.2.8 DEU Inte rrupt Con trol Regi st er................................................................................. 5-19

5.2.9 DEU EU_G O Re g i st e r...... ......................................................................................... 5-2 1

5.2.10 DEU IV Reg i st e r... ..................................................................................................... 5- 22

5.2.11 DEU Key Regi sters.............................................................................. ...................... 5- 2 2

5.2.12 DEU FIFOs .................................................................................... ............................ 5-22

5.3 ARC Four Execution Unit (AFEU) ............................................................................... 5-22

5.3.1 AFEU Regi ster Map .................................................................... .............................. 5 -22

5.3.2 AFEU Mode Re g i ster ....... ......................................................................................... 5-2 3

5.3.2.1 Host-p rov ided Cont e x t v i a Pr e v en t Permute ......................................................... 5-23

5.3.2.2 Dump Context........................................................................................................ 5-23

5.3.3 AFEU Key Si ze Regist e r .... ....................................................................................... 5-25

5.3.4 AFEU Cont e x t / D ata Size Re g i st e r . ........................... ................................................ 5 -26

5.3.5 AFEU Rese t Co n tr o l Re g i st e r ........................................................ ............................ 5- 2 6

5.3.6 AFEU Statu s Re g i st e r. ................................ ............................................................... 5-27

5.3.7 AFEU Inte r rupt Statu s Reg ister.. ........................................................................... .... 5- 2 9

5.3.8 AFEU Interrupt Control Register .............................................................................. 5-30

5.3.9 AFEU End o f Message Reg ister..... ................................................... ........................ 5 -32

5.3.10 AFEU Cont e x t ........................................................................................................... 5 -32

5.3.10 .1 AFEU Contex t Me m o ry .................................................................... .................... 5-33

5.3.10 .2 AFEU Contex t Me m o ry Point er Registe r .............................................................. 5-33

5.3.11 AFEU Key Re g i st e r s .......................... ....................................................................... 5-3 3

5.3.12 AFEU FIFO s.............................................................................................................. 5-33

5.4 Message Digest Execution Units (MDEU).................................................................... 5-34

5.4.1 MDEU Register Map................................................................................................. 5-34

5.4.2 MDEU Mode Register............................................................................................... 5-34

5.4.2.1 Recom m e n d ed se t tings for M DEU Mode Re g ister.................. .............. .............. .5-36

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor vii

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

5.4.3 MDEU Key Size Register.......................................................................................... 5-36

5.4.4 MDEU Data Size Register......................................................................................... 5-37

5.4.5 MDEU Reset Control Register .................................................................................. 5-38

5.4.6 MDEU Status Register............................................................................................... 5-38

5.4.7 MDEU Inte rrupt Stat u s Reg ister .......................................................................... ...... 5 -40

5.4.8 MDEU Inte rrupt Control Register ............................... .............................................. 5- 4 1

5.4.9 MDEU EU_GO Register ........................................................................................... 5-42

5.4.10 MDEU Context Registers.......................................................................................... 5-43

5.4.11 MDEU Key Registers................................................................................................ 5-44

5.4.12 MDEU FIFOs ............................................................................................................5-45

5.5 Random Number Generator (RNG)......................................................... .......... ............ 5-45

5.5.1 Overview.................................................................................................................... 5-45

5.5.2 Functional Description............................................................................................... 5-45

5.5.3 RNG Register Map .................................................................... ................................ 5-46

5.5.4 RNG Mode Reg i ster ....... ........................................................................................... 5 - 4 6

5.5.5 RNG Data Si ze Regist er ............................... ............................................................. 5 -47

5.5.6 RNG Reset C o n t ro l Re g i st e r ...................................................................................... 5-47

5.5.7 RNG Status Re g i st e r. ................................................... .............................................. 5- 4 8

5.5.8 RNG Inter rupt Statu s Reg ister.. ........................................................................... ...... 5 -49

5.5.9 RNG Interrupt Control Register ................................................................................ 5-50

5.5.10 RNG EU_GO Register..................................................................................... .......... 5- 5 1

5.5.11 RNG FIFO ...... ........................................................................................................... 5-52

5.6 Advance d En crypti o n Stand ard Execution Units (AE S U ) .... .............................. .......... 5-5 2

5.6.1 AESU Regi ster Map ................................................................................ .................. 5 -52

5.6.2 AESU Mode Re g i ster ............. ................................................................................... 5-5 3

5.6.3 AESU Key Si z e Registe r .... ....................................................................................... 5-54

5.6.4 AESU Data Si ze Regist er ...................................... .................................................... 5- 5 4

5.6.5 AESU Rese t Co n tr o l Re g i st e r........... ..................................................................... .... 5- 5 5

5.6.6 AESU Statu s Re g i st e r. ................................................... ............................................ 5-56

5.6.7 AESU Inte r rupt Statu s Reg ister.. ............................................................................... 5-57

5.6.8 AESU Interrupt Control Register .............................................................................. 5-59

5.6.9 AESU End o f Message Re gister..... ........................................................................... 5-61

5.6.9.1 AESU Cont e x t Reg isters ....................................................................................... 5-6 1

5.6.9.2 Context fo r CBC Mode... .............. ......................................................................... 5 - 6 2

5.6.9.3 Context for Counter Mode..................................................................................... 5-63

5.6.9.4 AESU Key Re g i st e rs .. ........................................................................................... 5 - 6 3

5.6.9.5 AESU FIF Os.......................................................................................................... 5-64

Chapter 6 MPC184 Descriptors

6.1 Data Pac k et Descrip tor Overv iew. ................................................................................... 6-1

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

viii Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

6.2 Descriptor Structure .........................................................................................................6-1

6.2.1 Descriptor Header........................................................................................................ 6-2

6.2.2 Descriptor Length and Pointer Fields .......................................................................... 6-5

6.3 Descriptor Chaining......................................................................................................... 6-7

6.3.1 Null Fields....................................................................................................................6-8

6.4 Descriptor Classes............................................................................................................ 6-8

6.4.1 Static Descriptors.........................................................................................................6-9

6.4.2 Dynamic Descriptors ................................................................................................. 6-12

Chapter 7

Crypto-Channels

7.1 Crypto-Channel Registers................................................................................................ 7-2

7.1.1 Crypto-Channel Configuration Register (CCCR)........................................................ 7-2

7.1.2 Crypto-Channel Pointer Stat u s Registers (CCPS R)............... .............. .............. ........ .7-5

7.1.3 Crypto -Channe l Cu rrent Desc r iptor Po i n ter Regis t e r (CDPR).................................. 7-1 0

7.1.4 Fetch Register (FR).................................................................................................... 7-11

7.1.5 Descriptor Buffer (DB).............................................................................................. 7-12

7.1.5.1 Descriptor Header.................................................................................................. 7-13

7.1.5.2 Descriptor Length/Pointer Pairs ............................................................................ 7-14

7.1.5.3 Next Descriptor Pointer ......................................................................................... 7-14

7.2 Interrupts........................................................................................................................ 7-14

7.2.1 Channel D o n e In t e rrupt ............................................................................................. 7 -14

7.2.2 Channel Error Int errupt... ..................................... ...................................................... 7 -15

7.2.3 Channel Reset .................................................... ........................................................ 7 -15

7.2.3.1 Hardware Reset...................................................................................................... 7-15

7.2.3.2 Channel Specific Software Reset........................................................................... 7-15

Chapter 8

Controller

8.1 Contro ller Registers .... ...................................... ...............................................................8-1

8.1.1 EU Assignment Control Register (EUACR) ............................................................... 8-1

8.1.2 EU Assig n m en t Status Register (EUASR) ...... .................................................. .......... 8- 2

8.1.3 Interrupt Mask Registers (IMR) .................................................................................. 8-3

8.1.4 Interrupt Status Registers (ISR)................................................................................... 8-4

8.1.5 Interr u p t Clear Regis t e r ( ICR).............. ....................................................................... 8-5

8.1.6 ID Regist e r.... ............................................................................................. .............. .... 8-8

8.1.7 Master Control Registers (MCR)................................................................................. 8-9

8.1.8 EU Access..................................................................................................................8-11

8.1.9 Multiple EU Assignment.................................................................................. .........8-12

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor ix

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

8.1.10 Multiple Channels......................................................................................................8-12

8.1.11 Priori t y Arbitrat i o n .................................................................................................... 8-12

8.1.12 Round Robin Snapshot Arbiters................................................................................8- 13

8.1.13 Bus Access.................................................................................................................8-13

Chapter 9

PCI Interface Module

9.1 PCI Interface ....................................................................................................................9-1

9.2 PCI Initiator ..................................................................................................................... 9-1

9.2.1 Data Align m ent Block ................................................................................. ................ 9- 1

9.2.2 Bus Access...................................................................................................................9-1

9.2.3 Bus Arbitration ............................................................................................................9-2

9.2.4 PCI Initiator ................................................................................................................. 9-3

9.2.5 Parity Errors................................................................................................................. 9-3

9.2.6 PCI Read...................................................................................................................... 9-3

9.2.6.1 T arget Aborts ........................................................................................................... 9-4

9.2.6.2 Initiator Aborts and Retry Errors............................ .... ...... ...... ...... ...... .... ...... ...... .....9-4

9.2.7 Initiator Write....................... ...... .... ...... .... ...... . .... ...... .... ...... ...... .... ...... .... ...... ...... .... .....9-4

9.2.8 Misaligned Data........................................................................................................... 9-5

9.2.9 PCI Target.................................................................................................................... 9-6

Appendix A

Execution Units in 32-Bit Big Endian View

A.1 Pu b li c Key Exec u t ion U n i ts (PKEU ).... ..................................... ..................................... A-2

A.1.1 PKEU Register Map . ........................................................................... ....................... A-2

A.1.2 PKEU Mode Regi ster . ................................................... ............................................. A -2

A.1.3 PKEU Key Size Re g is t e r ...................... ...................................................................... A - 4

A.1.4 PKEU Data Size Registe r . .......................................................................................... A-5

A.1.5 PKEU Reset Co n tr o l Reg ister. ........................... ......................................................... A-6

A.1.6 PKEU Status Regi ster..... ............................................................................................ A-6

A.1.7 PKEU Interrupt Status Re g i ster.... .............................................................................. A-8

A.1.8 PKEU Interrupt Control Register ............................................................................... A-9

A.1.9 PKEU EU_GO Reg ister.. ...........................................................................................A - 11

A.1.10 PKEU Parameter Me m o ries.......................................................................................A-11

A.1.10 .1 PKEU Parameter Me m o ry A.... .............................................................................A- 11

A.1.10 .2 PKEU Parameter Me m o ry B .... .............................................................................A- 11

A.1.10 .3 PKEU Parameter Me m o ry E ............................. ................................................... A - 1 2

A.1.10 .4 PKEU Parameter Me m o ry N.... ............ ................................................................ A - 1 2

A.2 Data Encryption Standard Execution Units (DEU) ...................................................... A-12

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

x Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

A.2.1 DEU Registe r Ma p ................................ .................................................................... A-1 2

A.2.2 DEU Mode Register.. ................................................................................................ A-12

A.2.3 DEU Key Size R eg i ster ............................................................................................ A-14

A.2.4 DEU Data Size Re g i st e r . .......................................................................................... A-14

A.2.5 DEU Reset Control Regi ster... ............................................................... ................... A-1 5

A.2.6 DEU Status Register ................. ................................................................................ A-1 6

A.2.7 DEU Interrupt Status Register .................................................................................. A-17

A.2.8 DEU Interru p t Control Re g i st e r................................................................................ A-1 9

A.2.9 DEU EU_GO Reg ister.. ............................................................................................ A-2 1

A.2.10 DEU IV Reg i st e r... .................................................................................................... A -22

A.2.11 DEU Key Regi sters.............................................................................. ..................... A -22

A.2.12 DEU FIFOs .................................................................................... ........................... A-22

A.3 ARC Four Execution Unit (AFEU) .............................................................................. A-22

A.3.1 AFEU Register Map . ................................................................................. ............... A -23

A.3.2 AFEU Mode Regi ster . ......................................................... ..................................... A-2 3

A.3.2.1 Host-p rov ided Cont e x t v i a Pr e v en t Permute ........................................................ A-23

A.3.2.2 Dump Context....................................................................................................... A-24

A.3.3 AFEU Key Size Re g is t e r ............................ .............................................................. A-2 5

A.3.4 AFEU Context / D a t a S ize Regist er . .......................................................................... A-26

A.3.5 AFEU Reset Co n tr o l Reg ister. .................... .............................................................. A-27

A.3.6 AFEU Status Regi ster..... .......................................................................................... A-28

A.3.7 AFEU Interrupt Status Re g i ster.... ............................................................................ A - 2 9

A.3.8 AFEU Interrupt Control Register ............................................................................. A-31

A.3.9 AFEU End of Mes sage Regi st e r... ............................................................................ A - 3 2

A.3.10 AFEU Cont e x t .......................................................................................................... A-33

A.3.10 .1 AFEU Cont ex t Memory ....................................................................................... A-33

A.3.10 .2 AFEU Cont ex t Memory Pointer Re g is t e r........................ ..................................... A-3 3

A.3.11 AFEU Key Re g i st e r s .......................... ...................................................................... A - 3 4

A.3.12 AFEU FIFO s............................................................................................................. A-34

A.4 Message Digest Execution Units (MDEU)................................................................... A-34

A.4.1 MDEU Register Map................................................................................................ A-34

A.4.2 MDEU Mode Register.............................................................................................. A-35

A.4.3 MDEU Key Size Register......................................................................................... A-36

A.4.4 MDEU Data Size Register........................................................................................ A-37

A.4.5 MDEU Reset Control Register ................................................................................. A-37

A.4.6 MDEU Status Register.............................................................................................. A-38

A.4.7 MDEU Interru p t St at u s Re g i st e r............................ ................................................... A - 4 0

A.4.8 MDEU Interru p t Co n t rol Regis t e r .... ........................................................................ A-41

A.4.9 MDEU EU_GO Register .......................................................................................... A-43

A.4.10 MDEU Context Registers......................................................................................... A-43

A.4.11 MDEU Key Registers............................................................................................... A-45

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor xi

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

A.4.12 MDEU FIFOs ........................................................................................................... A-45

A.5 Random Number Generator (RNG) .... ........ ............... ........ ........ ........ ........ ........ ...... ..... A-45

A.5.1 Overview...................................................................................................................A-45

A.5.2 Functional Description.............................................................................................. A-45

A.5.3 RNG Registe r Map ................................................................................................... A-46

A.5.4 RNG Mode Register . ......................................................... ....................................... A -46

A.5.5 RNG Data Size Re g i st e r . .......................................................................................... A-47

A.5.6 RNG Reset Con t ro l Re g i st e r................. .................................................................... A-4 8

A.5.7 RNG Status Register..... ............................................................................................ A-48

A.5.8 RNG Interr u p t Statu s Re g i ster.... .............................................................................. A-50

A.5.9 RNG Interrupt Control Register ............................................................................... A-50

A.5.10 RNG EU_GO Register..................................................................................... ......... A -51

A.5.11 RNG FIFO ...... .......................................................................................................... A -52

A.6 Ad v an c e d En crypti o n Stand ard Execution Un its (AES U ) .... .................................... ... A-52

A.6.1 AESU Register Map . ............................................................................................. ... A -52

A.6.2 AESU Mode Regi ster . ..................................................................... ......................... A-5 3

A.6.3 AESU Key Size Register .......................................................................................... A-54

A.6.4 AESU Data Size Registe r . ........................................................................................ A-54

A.6.5 AESU Reset Co n tr o l Re g i st er.................................... ............................................... A-55

A.6.6 AESU Status Register... .. .......................................................................................... A-56

A.6.7 AESU Interrupt Status Re g i ster.... ............................................................................ A - 5 8

A.6.8 AESU Interrupt Control Register ............................................................................. A-59

A.6.9 AESU End of Mes sage Regi st e r... ............................................................................ A - 6 1

A.6.9.1 AESU Cont e x t Reg isters ...................................................................................... A-61

A.6.9.2 Context fo r CBC Mode... .............. ........................................................................ A-62

A.6.9.3 Context for Counter Mode.................................................................................... A-63

A.6.9.4 AESU Key Re g i st e rs .. .......................................................................................... A-63

A.6.9.5 AESU FIF Os......................................................................................................... A-6 4

Appendix B

Controller in 32-Bit Big Endian View

B.1 Cont roller Reg i sters ................ ......................................................... ................................B-1

B.1.1 EU Assignment Control Register (EUACR) ...............................................................B-2

B.1.2 EU Ass i g n m e n t Statu s Re g i sters (E U A S R)..... ........................................................ ....B-2

B.1.3 Interrupt Mask Registers (IMR) ..................................................................................B-3

B.1.4 Interrupt Status Registers.............................................................................................B-4

B.1.5 Interrupt Clear Register (IC R) .... ..................................................................... ............B-5

B.1.6 ID Re gister...... ......................................................... ....................................................B-8

B.1.7 Master Control Registers (MCR).................................................................................B-8

B.1.8 EU Access. ................................ .................................................................................B-10

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

xii Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

B.1.9 Multiple EU Assignment...........................................................................................B-11

B.1.10 Multiple Channels................................................................................. ............ .........B-11

B.1.11 P ri o rity Arb i tr ation .......................................................................................... ..........B-11

B.1.12 Round Robin Snapshot Arbiters................................................................................B-12

B.1.13 Bus Access.................................................................................................................B-12

Appendix C

User’s Manual Revision History

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor xiii

Preliminary—Subject to Change Without Notice

Contents

Paragraph
Number Title

Page

Number

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

xiv Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Figures

Figure
Number Title

Page

Number

1-1 MPC184 Connected to PowerQuicc 8xx Bus ......................................................................... 1-3

1-2 MPC184 Connected to host CPU via PCI bus........................................................................ 1-4

1-3 MPC184 Functional Blocks....................................................................................................1-5

2-1 MPC184 Pinout....................................................................................................................... 2-4

4-1 PCI Type 00h Configuration Space Header............................................................................ 4-1

4-2 PCI Vendor ID Register .......................................................................................................... 4-2

4-3 PCI Device ID Register...........................................................................................................4-2

4-4 PCI Command Register .......................................................................................................... 4-2

4-5 PCI Status Register ................................................................................................................. 4-3

4-6 Revision ID/Class Code Register............................................................................................ 4-4

4-7 Cache Line/Latency Timer/Header Type/BIST ...................................................................... 4-5

4-8 Bas e Add ress Regi ster 0 ................................................................. ........................................ 4-6

4-9 Base Address Registers 4-5..................................................................................................... 4-7

4-10 CardBus CIS Pointer Register................................................................................................. 4-7

4-11 Subsyst em ID Regis t e rs .......................................................................................................... 4-7

4-12 Expansion ROM Base Address Register ................................................................................ 4-8

4-13 Capa bilitie s Pointer.................................................... ........ ........ ........ ........ ........ .......... ........... 4-8

4-14 Registers of the Sixteenth D-Word ......................................................................................... 4-9

5-1 PKEU Mo d e Re g i ster: Definitio n 1................................................................................ ........ 5-3

5-2 PKEU Mo d e Re g i ster: Definitio n 2................................................................................ ........ 5-3

5-3 PKEU Key Size Register ........................................................................................................ 5-5

5-4 PKEU D at a Siz e Regist er ....................................................................................................... 5-5

5-5 PKEU Reset Control Register................................................................................................. 5-6

5-6 PKEU Sta t u s Re g i st e r ...... .......................... .............................................................................5-7

5-7 PKEU In t e r rupt Statu s Reg i ster .............................................................................................. 5-8

5-8 PKEU Interrupt Control Register............................................................................................ 5-9

5-9 PKEU EU _G O Regist e r..... ................................ ................................................................... 5 -10

5-10 DEU Mode Re g is t e r... .......................... ................................................................................. 5-13

5-11 DEU Key Size Regist e r.... ..................................................................................................... 5-14

5-12 DEU Data S ize Regist er........................................................................................................ 5-15

5-13 DEU Reset Co n t ro l Register.... ............................................................................................. 5-15

5-14 DEU Status Reg ister .............................................................................................................5-16

5-15 DEU Interrupt Status Register .............................................................................................. 5-18

5-16 DEU Inte rrupt Con trol Regi st er............................................................................................ 5-20

5-17 DEU EU_G O Re g i st e r ..... .....................................................................................................5-21

5-18 AFEU Mode Re g i ster............................. ...............................................................................5-24

5-19 AFEU Key Size Register ......................................................................................................5-25

5-20 AFEU Data Si ze Regist er ........ .................... .........................................................................5-26

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor xv

Preliminary—Subject to Change Without Notice

Figures

Figure
Number Title

Page

Number

5-21 AFEU Reset Control Register............................................................................................... 5-27

5-22 AFEU Statu s Re g i st e r ...... ................................................... .................................................. 5-28

5-23 AFEU Inte r rupt Statu s Reg ister . ........................................................................................... 5-29

5-24 AFEU Interrupt Control Register.......................................................................................... 5-31

5-25 AFEU End o f Message Re g i st e r .. ......................................................................................... 5- 3 2

5-26 MDEU Mode Register ..........................................................................................................5-35

5-27 MDEU Key Size Register..................................................................................................... 5-37

5-28 MDEU Data Size Register .................................................................................................... 5-37

5-29 MDEU Reset Control Register ............................................................................................. 5-38

5-30 MDEU Status Register..........................................................................................................5-39

5-31 MDEU Inte rrupt Stat u s Reg ister.... ........ ............................................................................... 5 -40

5-32 MDEU Inte r ru p t Co n t rol Regis t e r ... .............. ..................................................................... .. 5-41

5-33 MDEU EU_GO Register ...................................................................................................... 5-43

5-34 MDEU Context Registers ..................................................................................................... 5-44

5-35 RNG Mode Reg i ster ..................................... ......................................................................... 5-46

5-36 RNG Data Siz e Registe r ....................................................................................................... 5-47

5-37 RNG Reset Co n tr o l Re g i st e r.... .......................... ................................................................... 5-48

5-38 RNG Status Re g i st e r ............................................................................................................. 5-49

5-39 RNG Inter rupt Status Re g i ster .............................................................................................. 5-50

5-40 RNGA Interrupt Control Register......................................................................................... 5-51

5-41 RNG EU_GO Registe r..... .............. .......................................................................................5-52

5-42 AESU Mode Re g i ster................. ...........................................................................................5-53

5-43 AESU Key Size Register ......................................................................................................5-54

5-44 AESU Data Si ze Regist er ........ .. ...........................................................................................5-55

5-45 AESU Reset Control Register............................................................................................... 5-55

5-46 AESU Statu s Re g i st e r ...... ...................................... ............................................................... 5-56

5-47 AESU Inte r rupt Statu s Reg ister . ........................................................................................... 5-58

5-48 AESU Interrupt Control Register.......................................................................................... 5-60

5-49 AESU End o f Message Reg ister .... ....................................................................................... 5-61

5-50 AESU Cont ex t Register ..... .......................... ..................................................................... .... 5-62

6-1 Exam p l e D a t a P a ck e t D esc riptor ... ......................................................................................... 6- 2

6-2 Descriptor Header ................................................................................................................... 6-2

6-3 Op_x sub fields ....................................................................................................................... 6-4

6-4 Descriptor Length Field .......................................................................................................... 6-5

6-5 Descriptor Pointer Field.......................................................................................................... 6-6

6-6 Next Descr i p tor Poin ter Field .. ................................................................... ............................ 6-7

6-7 Chai n o f D escripto rs ........................................................................................................ .......6-8

7-1 Crypto-Channel Configuration Register ................................................................................. 7-3

7-2 Crypto-Channel Pointer Status Register 1 .............................................................................. 7-5

7-3 Crypto-Channel Pointer Status Register 2 .............................................................................. 7-7

7-4 Cry p t o -Channe l Cu rrent Descriptor Pointer Register.......... ........ ........ .............. .............. .....7-11

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

xvi Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Figures

Figure
Number Title

Page

Number

7-5 Fetch Register .......................................................................................................................7-12

7-6 Data Packet De scripto r Buffer .............................................................................................. 7 -13

8-1 EU Assignment Control Register............................................................................................ 8-2

8-2 EU Assignmen t Status Register ... ....................................................................................... .... 8-3

8-3 Interrupt Mask Register 1 (IMR1) ......................................................................................... 8-3

8-4 Interrupt Ma sk Reg i ster 2 (IMR 2 ) ..... .. ................................................................................... 8-4

8-5 Interrupt Statu s Re g i ster 1 (IS R1 )...... ....................................... ..............................................8-5

8-6 Interrupt Statu s Re g i ster 2 (IS R2 )...... ....................................... ..............................................8-5

8-7 Interrupt Clear Regis t e r 1. .. ..................................................................................................... 8-6

8-8 Interrupt Clear Regis t e r 2. .. ..................................................................................................... 8-7

8-9 ID Register..............................................................................................................................8-9

8-10 Master Control Registers ........................................................................................................ 8-9

9-1 Data A l ign m ent Exa mpl e........................................................................................................ 9-5

A-1 PKEU Mode Re g i ster: Definitio n 1....................................................................................... A-3

A-2 PKEU Mode Re g i ster: Definitio n 2....................................................................................... A-3

A-3 PKEU Key Size Register .......................................................................................................A-5

A-4 PKEU Data Si ze Regist er ........ .. ............................................................................................A-5

A-5 PKEU Reset Control Register................................................................................................ A-6

A-6 PKEU Statu s Re g i st e r ...... ...................................... ................................................................ A-7

A-7 PKEU Inte r rupt Statu s Reg ister . ............................................................................................ A-8

A-8 PKEU Interrupt Control Register......................................................................................... A-10

A-9 PKEU EU_GO Regist e r..... ............................................. ......................................................A-11

A-10 DEU Mode Re g is t e r... .......................... ................................................................................ A-13

A-11 DEU Key Size Regist e r.... .................................................................................................... A-14

A-12 DEU Data S ize Regist er....................................................................................................... A-15

A-13 DEU Reset Co n t ro l Register.... ............................................................................................ A-15

A-14 DEU Status Reg ister ............................................................................................................ A-16

A-15 DEU Interrupt Status Register ............................................................................................. A-18

A-16 DEU Inte rrupt Con trol Regi st er........................................................................................... A-20

A-17 DEU EU_G O Re g i st e r ..... .................................................................................................... A-22

A-18 AFEU Mode Re g i ster............................. .............................................................................. A-24

A-19 AFEU Key Size Register ..................................................................................................... A-25

A-20 AFEU Data Si ze Regist er ........ .................... ........................................................................ A-27

A-21 AFEU Reset Control Register.............................................................................................. A-27

A-22 AFEU Statu s Re g i st e r ...... ................................................... ................................................. A-28

A-23 AFEU Inte r rupt Statu s Reg ister . .......................................................................................... A-30

A-24 AFEU Interrupt Control Register......................................................................................... A-31

A-25 AFEU End o f Message Re g i st e r .. ........................................................................................ A - 3 3

A-26 MDEU Mode Register ......................................................................................................... A-35

A-27 MDEU Key Size Register.................................................................................................... A-36

A-28 MDEU Data Size Register ................................................................................................... A-37

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor xvii

Preliminary—Subject to Change Without Notice

Figures

Figure
Number Title

Page

Number

A-29 MDEU Reset Control Register ............................................................................................ A-38

A-30 MDEU Status Register......................................................................................................... A-39

A-31 MDEU Inte rrupt Stat u s Reg ister.... ........ .............................................................................. A-40

A-32 MDEU Inte r ru p t Co n t rol Regis t e r ... .............. ..................................................................... . A-4 2

A-33 MDEU EU_GO Register ..................................................................................................... A-43

A-34 MDEU Context Registers .................................................................................................... A-44

A-35 RNG Mode Reg i ster ..................................... ........................................................................ A-47

A-36 RNG Data Siz e Registe r ......................................................................................................A-47

A-37 RNG Reset Co n tr o l Re g i st e r.... .......................... .................................................................. A-48

A-38 RNG Status Re g i st e r ............................................................................................................ A-49

A-39 RNG Inter rupt Status Re g i ster ............................................................................................. A-50

A-40 RNGA Interrupt Control Register........................................................................................ A-51

A-41 RNG EU_GO Registe r..... .............. ...................................................................................... A-52

A-42 AESU Mode Re g i ster................. .......................................................................................... A-53

A-43 AESU Key Size Register ..................................................................................................... A-54

A-44 AESU Data Si ze Regist er ........ .. .......................................................................................... A-55

A-45 AESU Reset Control Register.............................................................................................. A-56

A-46 AESU Statu s Re g i st e r ...... ...................................... .............................................................. A-57

A-47 AESU Inte r rupt Statu s Reg ister . .......................................................................................... A-58

A-48 AESU Interrupt Control Register......................................................................................... A-60

A-49 AESU End o f Message Reg ister .... ...................................................................................... A-6 1

A-50 AESU Cont ex t Register ..... .......................... ..................................................................... ...A-62

B-1 EU Assignment Control Register............................................................................................B-2

B-2 EU A ssignme n t Statu s Re g i sters.... ......................................................... ................................B-3

B-3 Interrupt Mask Register 1 ......................................................................................................B-3

B-4 In t e r rupt Mask Reg i ster 2 .................................. .....................................................................B-4

B-5 In t e r rupt Status Re g i ster 1.... ........ ................................................... ........................................B-4

B-6 In t e r rupt Status Re g i ster 2.... ........ ................................................... ........................................B-5

B-7 In t e r rupt Cle a r Reg i ster 1... ............................................. ........................................................B-6

B-8 In t e r rupt Cle a r Reg i ster 2... ............................................. ........................................................B-6

B-9 ID Register..............................................................................................................................B-8

B-10 Master Control Registers ........................................................................................................B-8

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

xviii Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Tables

Tabl e
Number Title

Page

Number

1-1 Exam p l e D a t a P a ck e t D esc riptor ... ......................................................................................... 1- 5

1-2 Est i mated Bu l k Dat a En cryption Performa n c e (M b p s)....... ........ ........ .............. ........ ...........1-12

2-1 MPC184 PCI Signals.............................................................................................................. 2-1

3-1 Module Base Address Map..................................................................... ........ .......... ........ ...... 3-1

3-2 Preliminary System Address Map Showing All Registers .....................................................3-2

4-1 PCI Comm a n d Reg i ster Signals....................... ............................................. .......................... 4-3

4-2 PCI Statu s Re g i ster Sig n a l s......................................................................................... ............ 4-3

4-3 Bas e Add ress Regi ster 0 Sign a l s............................................................................................. 4-6

5-1 Mode Reg i ster Rout i n e D efinitio n s ... ............................................. ........................................ 5- 3

5-2 PKEU Reset Control Register Signals .................................................................................... 5-6

5-3 PKEU Sta t u s Re g i st e r Si g n a l s . ............................................................... ................................ 5-7

5-4 PKEU In t e r rupt Statu s Reg i ster Si g n al s ................................................................................. 5-8

5-5 PKEU Interrupt Control Register Signals............................................................................... 5-9

5-6 DEU Mode Register Signals................................................................................................. 5-13

5-7 DEU Ke y Size Regi st e r.... ..................................................................................................... 5-14

5-8 DEU Reset Cont ro l Register Signa l s .......................................................................... .......... 5- 1 5

5-9 DEU Sta t u s Re g i ster Signals................................................................................................. 5-17

5-10 DEU Interrupt Status Register Signals.................................................................................. 5-18

5-11 DEU Inte rrupt Con t ro l Register Signals ............................................................................... 5 -20

5-12 AFEU Mode Reg i ster Si g n al s............................................................................................... 5 -24

5-13 AFEU Reset Control Register Signals.................................................................................. 5-27

5-14 AFEU Statu s Re g i st e r Signals . ............................................................................................. 5-28

5-15 AFEU Inte r rupt Statu s Reg ister . ........................................................................................... 5 -29

5-16 AFEU Interrupt Control Register.......................................................................................... 5-31

5-17 MDEU Mode Register ..........................................................................................................5-35

5-18 MDEU Reset Control Register Signal .................................................................................. 5-38

5-19 MDEU Status Register Signals............................................................................................. 5-39

5-20 MDEU Inte rrupt Stat u s Reg ister Sig n al s .............................................................................. 5-4 0

5-21 MDEU Inte r ru p t Co n t rol Regis t e r Si g n a l s.................. .......................................................... 5-4 2

5-22 RNG Mode Reg i ster Definitions........................................................................................... 5-4 7

5-23 RNG Reset Co n tr o l Re g i st e r Si g n als... ....................................... .......................................... 5 - 4 8

5-24 RNG Status Reg ister Sig n al s ............. ......................................................... .......................... 5-49

5-25 RNG Inter rupt Status Re g i ster Sig n a l s ..................................................................... ............ 5 -50

5-26 RNG Interrupt Control Register Signals............................................................................... 5-51

5-27 AESU Mode Re g i ster Sig n a l s.............................. ................................................................. 5-53

5-28 AESU Reset Control Register Signals.................................................................................. 5-56

5-29 AESU Statu s Re g i st e r Si g n a l s . ........................................................................... .................. 5 -57

5-30 AESU Inte r rupt Statu s Reg ister S i g n als ...... ......................................................................... 5 - 5 8

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor xix

Preliminary—Subject to Change Without Notice

Tables

Tabl e
Number Title

Page

Number

5-31 AESU Interrupt Control Register Signals............................................................................. 5-60

5-32 Counter Modulus................................................................................................................... 5-63

6-1 Head er Bit Defi n i t i o n s .......................................................................... .................................. 6-3

6-2 EU_Select Values.................................................................................................................... 6-4

6-3 De s criptor Types ................... .............. ........ .............. ............. ........ .............. ........ ...................6-4

6-4 Descriptor Length Field Mapping........................................................................................... 6-5

6-5 Descriptor Pointer Field Mapping........................................................................................... 6-6

6-6 Descriptor Length/Pointer Mapping ....................................................................................... 6-6

6-7 Descriptor Pointer Field Mapping........................................................................................... 6-7

6-8 Actual Descriptor common_nonsnoop_afeu.......................................................................... 6-9

6-9 Continuation of common_nonsnoop_afeu............................................................................ 6-10

6-10 Wrap-up of common_nonsnoop_afeu .................... ............................................................... 6-11

6-11 Actual Descriptor common_nonsnoop_afeu........................................................................ 6-11

6-12 Descriptor_HMAC_Snoop_Non_AFEU.............................................................................. 6-12

7-1 Crypto-Channel Configuration Register Signals .................................................................... 7-3

7-2 Burst Size Definition............................................................................................................... 7-5

7-3 Crypto-Channel Pointer Status Register 1Signals................................................................... 7-5

7-4 STATE Field Values ................................................................................................................ 7-6

7-5 Crypto-Channel Pointer Status Register 2 Signals.................................................................. 7-8

7-6 Crypto-Channel Pointer Status Register Error Field Definitions............................................ 7-9

7-7 Crypto-Channel Pointer Status Register P AIR_P TR Field Values........................................ 7-10

7-8 Crypto-Channel Current Descriptor Pointer Register Signals.............................................. 7-11

7-9 Fetch Register Signals...........................................................................................................7-12

8-1 Chan n el Assig n m e n t Value .....................................................................................................8-2

8-2 Interrupt Mask, Status, and Clear Register 1 Signals.............................................................. 8-7

8-3 Interrupt Mask, Status, and Clear Register 2 Signals.............................................................. 8-8

8-4 Master Control Register 1 Signals .......................................................................................... 8-9

8-5 Master Control Register 2 signals......................................................................................... 8-11

A-1 Mode Register Rout i n e D efinitio n s ... ......................................................... ........................... A -3

A-2 PKEU Reset Control Register Signals................................................................................... A-6

A-3 PKEU Statu s Re g i st e r Si g n a l s . ........................................................................... ................... A-7

A-4 PKEU Inte r rupt Statu s Reg ister S i g n als ...... .......................................................................... A-8

A-5 PKEU Interrupt Control Register Signals............................................................................ A-10

A-6 DEU Mode Register Signals ................................................................................................ A-13

A-7 DEU Key Size Regist e r.... ....................................................................................................A-14

A-8 DEU Reset Co n t ro l Register Signa l s ................................................................................... A-16

A-9 DEU Status Re g i ster Signals................................................................................................ A-17

A-10 DEU Interrupt Status Register Signals................................................................................. A-18

A-11 DEU Inte rrupt Con t ro l Register Signals .............................................................................. A-20

A-12 AFEU Mode Re g i ster Sig n a l s..................................... ......................................................... A - 24

A-13 AFEU Reset Control Register Signals................................................................................. A-28

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

xx Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Tables

Tabl e
Number Title

Page

Number

A-14 AFEU Statu s Re g i st e r Signals . ............................................................................................ A-29

A-15 AFEU Inte r rupt Statu s Reg ister . .......................................................................................... A-30

A-16 AFEU Interrupt Control Register......................................................................................... A-32

A-17 MDEU Mode Register ......................................................................................................... A-35

A-18 MDEU Reset Control Register Signal ................................................................................. A-38

A-19 MDEU Status Register Signals............................................................................................ A-39

A-20 MDEU Inte r ru p t St atus Regist er Signals .................................. ........................................... A-4 0

A-21 MDEU Inte r ru p t Co n t rol Regis t e r Si g n a l s.................. ......................................................... A-42

A-22 RNG Mode Reg i ster Definitions.......................................................................................... A-47

A-23 RNG Reset Co n tr o l Re g i st er Signals .............................. ..................................................... A-48

A-24 RNG Status Reg ister Sig n al s ............. ......................................................... ......................... A-49

A-25 RNG Inter rupt Status Re g i ster Sig n a l s ..................................................................... ........... A-50

A-26 RNG Interrupt Control Register Signals.............................................................................. A-51

A-27 AESU Mode Re g i ster Sig n a l s.............................. ................................................................ A - 53

A-28 AESU Reset Control Register Signals................................................................................. A-56

A-29 AESU Statu s Re g i st e r Si g n a l s . ........................................................................... ................. A-57

A-30 AESU Inte r rupt Statu s Reg ister S i g n als ...... ........................................................................ A-58

A-31 AESU Interrupt Control Register Signals............................................................................ A-60

A-32 Counter Modulus.................................................................................................................. A-63

B-1 Ch a n n e l A ssignme n t Value .....................................................................................................B-2

B-2 Interrupt Mask, Status, and Clear Register 1 Signals..............................................................B-7

B-3 Interrupt Mask, Status, and Clear Register 2 Signals..............................................................B-7

B-4 Master Control Register 1 Signals..........................................................................................B-8

B-5 Master Control Register 2 signals.........................................................................................B-10

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor xxi

Preliminary—Subject to Change Without Notice

Tables

Tabl e
Number Title

Page

Number

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

xxii Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Chapter 1 Overview

This chapter provides an overview of the MPC184 Security Processor, including a brief
development history, target applications, key features, typical system architecture, device
architectural overview, and a performance summary.

1.1 Development History

The MPC184 belongs to the Smart Networks platform’s S1 family of security processors
developed for the commercial networking market. This product fami ly is derived from security
technologies Motorola has developed over the last 30 years, primarily for government
applications. The fifth-generation execution units (EU) have been proven in Motorola
semi-custom ICs and in other members of the S1 family, including the MPC180, MPC190, and
MPC185.

1.2 Typical Applications

The MPC184 is suited for applications such as the following:

• SOHO VPN routers

• Customer Premise Equipment

• eCommerce servers

• Wireless Access Points

• Dedicated Encryption Modules

1.3 Features

The MPC184 is a flexible and powerful addition to any networking or computing system using the
PowerQUICC™ line of integrated communications processors, or any system supporting 32-bit
PCI. The MPC184 is designed to off load computationally intensive security functions, such as
key generation and exchange, authentication, and bulk encryption from the host processor .

The MPC184 is optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP,
SSL/TLS, DOCSIS BPI+, 802.16, and 802.11(WEP). In addition, the security co-processors are
the only devices on the market capable of executing Elliptic Curve Cryptography which is
especially important for secure wireless communications.

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor 1-1

Preliminary—Subject to Change Without Notice

Overview

MPC184 features include the following:

• Public Key Execution Unit (PKEU) that supports the following:

— RSA and Diffie-Hellman

– Programmable field size up to 2048-bits

— Elliptic curve cryptography

m and F(p) modes

–F

2

– Programmable field size up to 511-bits

• Data Encryption Standard Execution Unit (DEU)

— DES, 3DES
— Two key (K1, K2, K1) or Three Key (K1, K2, K3)
— ECB and CBC modes for both DES and 3DES

• Advanced Encryption Standard Unit (AESU)

— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits.Two key
— ECB, CBC, and Counter modes

• ARC Four Execution Unit (AFEU)

— Implements a stream cipher compatible with the RC4 algorithm
— 40- to 128-bit programmable key

• Message Digest Execution Unit (MDEU)

— SHA with 160-bit or 256-bit message digest
— MD5 with 128-bit message digest
— HMAC with either algorithm

• Random number generator (RNG)

• 8xx compliant external bus interface, with master/slave logic.

— 32-bit address/32 -bit data
— up to 66MHz operation

• Optional PCI 2.2 compliant external bus interface, with master/slave logic.

— 32-bit address/data
— up to 66MHz operation

• 4 Crypto-channels, each supporting multi-command descriptor chains

— Static and/or dynamic assignment of crypto-execution units via an integrated controller
— Buffer size of 512 Bytes for each execution unit, with flow control for large data sizes

• 8KB of internal scratchpad memory for key, IV and context storage

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

1-2 Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Overview

• 1.5V supply, 3.3V I/O

• 252MAP BGA, 21x 21mm package body size

• 1.0W power dissipation

1.4 Typical System Architecture

The MPC184 is designed to integrate easily into any system using the 8xx or PCI bus protocol.
The MPC184 is ideal in any system using a PowerQUICC communications processor (as shown
in Figure 1) or any system using PCI. The ability of the MPC184 to be a master on the 8xx bus
allows the co-processor to offload the data mov ement bottleneck normally as sociated with slave
devices.

The host processor accesses the MPC184 through its device drivers using system memory for data
storage. The MPC184 resides in the memory map of the processor, therefore when an application
requires cryptographic functions, it simply creates descriptors for the MPC184 which define the
cryptographic function to be performed and the location of the data. The MPC184’s mastering
capability permits the host processor to set up a crypto-channel with a few short register writes,
leaving the MPC184 to perform reads and writes on system memory to complete the required task.

EEPROM

Main

Memory

MPC184

8xx Bus

MPC860

I/O or Network

Interface

Figure 1-1. MPC184 Connected to PowerQuicc 8xx Bus

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor 1-3

Preliminary—Subject to Change Without Notice

Overview

Main

Memory

Memory Bus

PCI Local Bus

Interface Card

MPC8245

Network

Network

Interface Card

MPC184

Figure 1-2. MPC184 Connected to host CPU via PCI bus

1.5 Architectural Overview

A block diagram of the MPC184 internal architecture is shown in Figure 1-1. The mode selectable
8xx/PCI bus interface module is designed to transfer 32-bit words between the external bus and
any register inside the MPC184. An operation begins with a write of a pointer to a crypto-channel
fetch register which points to a data packet descriptor. The channel then requests the descriptor and
decodes the operation to be performed. The channel then makes requests of the controller to assign
crypto execution units and fetch the keys, IV’s and data needed to perform the give n operation.
The controller satisfies the requests by assigning execution units to the channel and by making
requests to the master interface per the progr ammable priority scheme. As data is processed, it is
written to the individual execution units output buffer and then back to system memory via the bus
interface module.

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

1-4 Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Overview

8KB
gpRAM

Master/slave
interface

crypto­channel

crypto­channel

crypto­channel

crypto­channel

Control

PKEU

FIFO

DEU

FIFO

FIFO

MDEU

FIFO

AES

FIFO

FIFO

ARC-4

FIFO

RNG

FIFO

Figure 1-3. MPC184 Functional Blocks

1.6 Data Packet Descriptors

As an IPSec accelerator, the MPC184’s controller has been designed for easy use and integration
with existing systems and software. All cryptographic functions are accessible through data packet
descriptors, some of which have been defined as multifunction to facilitate IPSec applications. A
data packet descriptor is diagrammed in Table 1-1.

Table 1-1. Example Data Packet Descriptor

Field Name Value/Type Description

DPD_DES_CTX_CRYPT TBD Representative header for DES using Context to Encrypt

LEN_CTXIN
PTR_CTXIN

LEN_KEY
PTR_KEY

LEN_DATAIN
PTR_DATAIN

LEN_DATAOUT
PTR_DATAOUT

LEN_CTXOUT
PTR_CTXOUT

Nul length

Nul pointer

Nul length

Nul pointer

Length
Pointer

Length
Pointer

Length
Pointer

Length
Pointer

Length
Pointer

Length
Pointer

Length
Pointer

Number of bytes to be written
Pointer to Context (IV) to be written into DES engine

Number of bytes in key
Pointer to block cipher key

Number of bytes of data to be ciphered
Pointer to data to perform cipher upon

Number of bytes of data after ciphering
Pointer to location where cipher output is to be written

Length of output Context (IV)
Pointer to location where altered Context is to be written

Zeroes for fixed length descriptor filter
Zeroes for fixed length descriptor filter

Zeroes for fixed length descriptor filter
Zeroes for fixed length descriptor filter

PTR_NEXT Pointer Pointer to next data packet descriptor

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor 1-5

Preliminary—Subject to Change Without Notice

Overview

Each data packet descriptor contains the following:

• Header—The header describes the required services and encodes information that indicates

which EUs to use and which modes to set.

• Seven data length/data pointer pairs—The data length indicates the number of contiguous

bytes of data to be transferred. The data pointer indicates the starting address of the data,
key, or context in system memory .

• Next descriptor pointer

A data packet descriptor ends with a pointer to the next data packet descriptor. Therefore, once a
descriptor is processed and if the value of this pointer is non-zero, it is used to request a burst read
of the next descriptor.

Processing of the next descriptor (and whether or not a done signal is generated) is determined by
the programming of crypto-channel’s configuration register. Two modes of operation are
supported:

• Signal done at end of descriptor

• Signal done at end of descriptor chain

The crypto-channel can signal done via an interrupt or by a write-back of the descriptor header
after processing a data packet descriptor. The value written back is identical to that of the header,
with the exception that a DONE field is set.

Occasionally, a descriptor field may not be applicable to the requested service. For example, if
using DES in ECB mode, the contents of the IV field do not affect the result of the DES
computation. Therefore, when processing data packet descriptors, the crypto-channel skips any
pointer that has an associated length of zero.

1.6.1 External Bus Interface

The External Bus Interface (EBI) manages communication between the MPC184’s internal
execution units and the external bus. The interface is mode selectable between the PCI 2.2 bus
protocol, and the 8xx bus protocols, used by the PowerQuicc family of integrated communications
processors. The MPC184 is unique in its ability to act as a bus master on the 8xx bus. All on-chip
resources are memory mapped, and the target accesses and initiator writes from the MPC184 must
be addressed on word boundaries. The MPC184 will perform initiator reads on byte boundaries
and will adjust the data to place on word boundaries as appropriate. The bus mastering interface
allows the MPC184 t o off-load both crypto processing and data movement from the processor,
freeing the CPU for other networking system functions, allowing the chip set to achieve best in
class performance levels.

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

1-6 Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Overview

1.6.2 The MPC184 Controller

The MPC184 controller man ages on-chip resources, including ind ividual exe cution units (EUs),
FIFOs, the EBI, and the internal buses that connect all the various modules. The controller receives
service requests from the EBI and variou s crypto-channels, and schedules the required activities.
The controller can configure each of the on-chip resources in three modes:

• Host-controlled mode—The host is directly responsible for all data movement into and out

of the resource.

• Static mode—The user can reserve a specific execution unit to a specific crypto-channel.

• Dynamic mode—A crypto channel can request a particular service from any available

execution unit.

1.6.3 Host-Managed Register Access

All EUs can be used entirely through register read/write a ccess. It is strongly recommend ed that
read/write access only be performed on a EU that is statically assigned to an idle crypto-channel.
Such an assignment is the only method for the host to inform the controller that a particular EU is
in use.

1.6.4 Static EU Access

The Controller can be configured to reserve one or more EUs to a particular crypto-channel. Doing
so permits locking the EU to a particular context. When in this mode, the crypto-channel c an be
used by multiple descriptors representing the same context without unloading and reloading the
context at the end of each descriptor. This mode presents considerable performance improvement
over dynamic access, but only when the MPC184 is supporting a single context (or a single session
is being streamed.)

1.6.5 Dynamic EU Access

Processing begins when a data packet descriptor pointer is written to the next descriptor pointer
register of one of the crypto-channels. Prior to fetching the data referred to by the descriptor and
based on the services requested by the descriptor header in the descriptor buffer, the controller
dynamically reserves usage of an EU to the crypto-channel. If all appropriate EUs are already
dynamically reserved by other crypto-channels, the crypto-channel stalls and waits to fetch data
until the appropriate EU is available.

If multiple crypto-channels simultaneously request the same EU, the EU is assigned on a
round-robin basis. Once the required EU has been reserved, the crypto-channel fetches and loads
the appropriate data packets, operates the EU, unloads data to system memory , and releases the EU
for use by another crypto-channel. If a crypto-channel attempts to reserve a statically-assigned EU
(and no appropriate EUs are available for dynamic assignment), an interrupt is generated and

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

Freescale Semiconductor 1-7

Preliminary—Subject to Change Without Notice

Overview

status indicates illegal access. When dynamic assignment is used, each encryption/decryption
packet must contain context that is particular to the context being supported.

1.6.6 Crypto-Channels

The MPC184 includes four crypto-channels that manage data and EU function. Each
crypto-channel consists of the following:

• Control registers containing information about the transaction in process

• A status register containing an indication of the last unfulfilled bus request

• A pointer register indicating the location of a new descriptor to fetch

• Buffer memory used to store the active data packet descriptor (See Section 1.6, “Data

Packet Descriptors.”)

Crypto-channels analyze the data packet descriptor header and request from the controller the first
required cryptographic service. The controller implements a programmable prioritization scheme
that allows the user to dictate the order in which the four crypto-channels are serviced. After the
controller grants access to the required EU, the crypto-channel and the controller perform the
following steps:

1. Set the appropriate Mode bits available in the EU for the required service.

2. Fetch context and other parameters as indicated in the data packet descriptor buffer and

use these to program the EU.

3. Fetch data as indicated and place in either the EU’s input FIFO or the EU itself (as

appropriate).

4. Wait for EU to complete processing.

5. Upon completion, unload results and context and write them to external memory as

indicated by the data packet descriptor buffer.

6. If multiple services requested, go back to step 2.

7. Reset the appropriate EU if it is dynamically assigned. Note that if statically assigned, a

EU is reset only upon direct command written to the MPC184.

8. Perform descriptor completion notification as appropriate. This notification comes in one

of two forms—interrupt or header writeback modification—and can occur either at the
end of every descriptor or at the end of a descriptor chain.

1.7 Execution Units (EUs)

“Execution unit” is the generic term for a functional block that performs the mathematical
permutations required by protocols used in cryptographic processing. The EUs are compatible

MPC184 Security Co-Processor User’s Manual: PCI Interface, Rev. 2

1-8 Freescale Semiconductor

Preliminary—Subject to Change Without Notice