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MMC2107
User Manual
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Freescale MMC2107 User Manual

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MMC2107/D REV 2
MMC2107
Technical Data
HCMOS Micro cont ro ll er Unit
Freescale Semiconductor, Inc.
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MMC2107
Technical Data
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Motorola reserves the right to make ch anges without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor do es Motorola assume any liability arisin g out of the app lication or u se of any pr oduct or ci rcuit, a nd sp ecifica lly disclaims any and all liability, including without limitation consequ ential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees a rising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding t he design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2000
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA 3
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Technical Data
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Technical Data MMC2107 – Rev. 2.0
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Technical Data — MMC2107

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . .43
Section 2. System Memory Map . . . . . . . . . . . . . . . . . . .51
Section 3. Chip Configuration Module (CCM) . . . . . . . .89
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Section 4. Signal Description. . . . . . . . . . . . . . . . . . . . .107
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Section 5. Reset Controller Module. . . . . . . . . . . . . . . .129
Section 6. M•CORE M210 Central Processor
Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . .143
Section 7. Interrupt Controller Module . . . . . . . . . . . . .153
Section 8. Static Random-Access Memory
(SRAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Section 9. Non-Volatile Memory FLASH
(CMFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Section 10. Clock Module. . . . . . . . . . . . . . . . . . . . . . . .221
Section 11. Ports Module . . . . . . . . . . . . . . . . . . . . . . . .247
Section 12. Edge Port Module (EPORT) . . . . . . . . . . . .261
Section 13. Watchdog Timer Module . . . . . . . . . . . . . .271
Section 14. Programmable Interrupt Timer
Modules (PIT1 and PIT2) . . . . . . . . . . . . . .281
Section 15. Timer Modules (TIM1 and TIM2). . . . . . . . .293
MMC2107 – Rev. 2.0 Technical Data
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List of Sec ti o ns
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Section 16. Serial Communications Interface
Modules (SCI1 and SCI2) . . . . . . . . . . . . . .329
Section 17. Serial Peripheral Interface
Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . .371
Section 18. Queued Analog-to-Digital
Converter (QADC). . . . . . . . . . . . . . . . . . . .399
Section 19. External Bus Interface Module (EBI) . . . . .503
Section 20. Chip Select Module. . . . . . . . . . . . . . . . . . .521
Section 21. JTAG Test Access Port and OnCE . . . . . .533
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Section 22. Electrical Specifications. . . . . . . . . . . . . . .585
Section 23. Mechanical Specifications . . . . . . . . . . . . .609
Section 24. Ordering Information . . . . . . . . . . . . . . . . .615
Technical Data MMC2107 – Rev. 2.0
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Technical Data — MMC2107
1.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table of Contents

Section 1. General Description
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1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8
Section 2. System Memory Map
2.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.3 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Section 3. Chip Configuration Module (CCM)
3.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1
3.4.3 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.4 Factory Access Slave Test (FAST) Mode . . . . . . . . . . . . . .91
3.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2
3.6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
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3.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.7.1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.7.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.7.3 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.7.3.1 Chip Configuration Register. . . . . . . . . . . . . . . . . . . . . . .94
3.7.3.2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . . .97
3.7.3.3 Chip Identification Register . . . . . . . . . . . . . . . . . . . . . . .99
3.7.3.4 Chip Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
3.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
3.8.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.8.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.8.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.8.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .105
3.8.5 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
3.8.6 Internal FLASH Configuration . . . . . . . . . . . . . . . . . . . . . .106
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3.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
3.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Section 4. Signal Description
4.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
4.3 Package Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4.4 MMC2107 Specific Implementation Signal Issues . . . . . . . . .120
4.4.1 RSTOUT Signal Functions. . . . . . . . . . . . . . . . . . . . . . . . . 120
4.4.2 INT Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
4.5 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
4.5.1 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
4.5.1.1 Reset In (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
4.5.1.2 Reset Out (RSTOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .121
4.5.2 Phase-Lock Loop (PLL) and Clock Signals . . . . . . . . . . . .122
4.5.2.1 External Clock In (EXTAL). . . . . . . . . . . . . . . . . . . . . . .122
4.5.2.2 Crystal (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.5.2.3 Clock Out (CLKOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.5.2.4 Synthesizer Power (V
DDSYN
and V
SSSYN
). . . . . . . . . . .122
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4.5.3 External Memory Interface Signals . . . . . . . . . . . . . . . . . .122
4.5.3.1 Data Bus (D[31:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.5.3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .123
4.5.3.3 Transfer Acknowledge (TA). . . . . . . . . . . . . . . . . . . . . .123
4.5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . .123
4.5.3.5 Emulation Mode Chip Selects (CSE[1:0]) . . . . . . . . . . .123
4.5.3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . .123
4.5.3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.5.3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .124
4.5.3.9 Enable Byte (EB[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .124
4.5.3.10 Chip Select (CS[3:0] ). . . . . . . . . . . . . . . . . . . . . . . . . . .124
4.5.3.11 Output Enable (OE
4.5.4 Edge Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
4.5.4.1 External Interrupts (INT[7:6]) . . . . . . . . . . . . . . . . . . . . .124
4.5.4.2 External Interrupts (INT[5:2]) . . . . . . . . . . . . . . . . . . . . .124
4.5.4.3 External Interrupts (INT[1:0]
4.5.5 Serial Peripheral Interface Module Signals . . . . . . . . . . . .125
4.5.5.1 Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . .125
4.5.5.2 Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . .125
4.5.5.3 Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
4.5.5.4 Slave Select (SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
4.5.6 Serial Communications Interface Module Signals . . . . . . .125
4.5.6.1 Receive Data (RXD1 and RXD2). . . . . . . . . . . . . . . . . .125
4.5.6.2 Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . .126
4.5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . .126
4.5.8 Analog-to-Digital Converter Signals. . . . . . . . . . . . . . . . . .126
4.5.8.1 Analog Inputs (PQA[4:3], PQA[1:0],
4.5.8.2 Analog Reference (V
4.5.8.3 Analog Supply (V
4.5.8.4 Positive Supply (V
4.5.9 Debug and Emulation Support Signals . . . . . . . . . . . . . . .127
4.5.9.1 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
4.5.9.2 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
4.5.9.3 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . .127
4.5.9.4 Test Data Input (TDI). . . . . . . . . . . . . . . . . . . . . . . . . . .127
4.5.9.5 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . .127
4.5.9.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Table of Contents
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
) . . . . . . . . . . . . . . . . . . . . .125
and PQB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
and VRL) . . . . . . . . . . . . . . . . .126
RH
and V
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . 126
DDH
) . . . . . . . . . . . . . . . . . .126
SSA
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4.5.10 Test Signal (TEST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
4.5.11 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . .128
4.5.11.1 Power for FLASH Erase/Program (VPP) . . . . . . . . . . . .128
4.5.11.2 Power and Ground for FLASH Array
4.5.11.3 Standby Power (V
4.5.11.4 Positive Supply (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.11.5 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
(V
DDF
and V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
SSF
) . . . . . . . . . . . . . . . . . . . . . . . . .128
STBY
Section 5. Reset Controller Module
5.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
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5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .132
5.6.1 Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .133
5.6.2 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
5.6.3 Reset Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
5.7.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
5.7.1.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
5.7.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
5.7.1.3 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . .137
5.7.1.4 Loss of Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .137
5.7.1.5 Loss of Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.7.1.6 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.7.2 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.7.2.1 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . .138
5.7.2.2 Internal Reset Request . . . . . . . . . . . . . . . . . . . . . . . . .140
5.7.2.3 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
5.7.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
5.7.3.1 Reset Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
5.7.3.2 Reset Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
5.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
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Table of Contents
Section 6. M•CORE M210 Central
Processor Unit (CPU)
6.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
6.4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . .145
6.5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6.6 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
6.7 Operand Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . .150
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6.8 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Section 7. Interrupt Controller Module
7.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
7.4 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
7.6 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
7.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .155
7.7.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
7.7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
7.7.2.1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . .157
7.7.2.2 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . .159
7.7.2.3 Interrupt Force Registers . . . . . . . . . . . . . . . . . . . . . . . .160
7.7.2.4 Interrupt Pending Register. . . . . . . . . . . . . . . . . . . . . . .162
7.7.2.5 Normal Interrupt Enable Register. . . . . . . . . . . . . . . . . .163
7.7.2.6 Normal Interrupt Pending Register. . . . . . . . . . . . . . . . .164
7.7.2.7 Fast Interrupt Enable Register. . . . . . . . . . . . . . . . . . . .165
7.7.2.8 Fast Interrupt Pending Register. . . . . . . . . . . . . . . . . . .166
7.7.2.9 Priority Level Select Registers . . . . . . . . . . . . . . . . . . . .167
7.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
7.8.1 Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .168
7.8.2 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . .168
7.8.3 Autovectored and V e ctored Interrupt Requests. . . . . . . . .169
MMC2107 – Rev. 2.0 Technical Data
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7.8.4 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
7.8.4.1 M•CORE Processor Configuration. . . . . . . . . . . . . . . . .171
7.8.4.2 Interrupt Controller Configuration. . . . . . . . . . . . . . . . . .171
7.8.4.3 Interrupt Source Configuration. . . . . . . . . . . . . . . . . . . .172
7.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Section 8. Static Random-Access Memory (SRAM)
8.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
8.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
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8.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
8.5 Standby Power Supply Pin (V
8.6 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
8.7 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
8.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
) . . . . . . . . . . . . . . . . . . . .176
STBY
Section 9. Non-Volatile Memory FLASH (CMFR)
9.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
9.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
9.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
9.4.2 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
9.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
9.6 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
9.7 Registers and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .186
9.7.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
9.7.1.1 CMFR Module Configuration Register. . . . . . . . . . . . . . 188
9.7.1.2 CMFR Module Test Register . . . . . . . . . . . . . . . . . . . . .193
9.7.1.3 CMFR High-Voltage Control Register . . . . . . . . . . . . . .196
9.7.2 Array Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
9.7.2.1 Read Page Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
9.7.2.2 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . .204
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9.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
9.8.1 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
9.8.2 Register Read and Write Operation . . . . . . . . . . . . . . . . . .205
9.8.3 Array Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
9.8.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
9.8.4.1 Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
9.8.4.2 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . .211
9.8.4.3 Programming Shadow Information. . . . . . . . . . . . . . . . .212
9.8.4.4 Program Pulse-Width and Amplitude Modulation . . . . .213
9.8.4.5 Overprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
9.8.5 Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
9.8.5.1 Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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9.8.5.2 Erase Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . .218
9.8.5.3 Erasing Shadow Information Words. . . . . . . . . . . . . . . .219
9.8.6 Erase Pulse Amplitude and Width Modulation. . . . . . . . . .219
9.8.7 Emulation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table of Contents
cale Semiconductor,
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9.9 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
9.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Section 10. Clock Module
10.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
10.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.4.1 Normal PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.4.2 1:1 PLL Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.4.3 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.4.4 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.4.4.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.4.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
10.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
10.6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10.6.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10.6.2 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10.6.3 CLKOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
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10.6.4 V
10.6.5 RSTOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
10.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .226
10.7.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
10.7.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
10.7.2.1 Synthesizer Control Register . . . . . . . . . . . . . . . . . . . . .227
10.7.2.2 Synthesizer Status Register. . . . . . . . . . . . . . . . . . . . . .230
10.7.2.3 Synthesizer Test Register . . . . . . . . . . . . . . . . . . . . . . .233
10.7.2.4 Synthesizer Test Register 2. . . . . . . . . . . . . . . . . . . . . .234
10.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
10.8.1 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
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cale Semiconductor,
10.8.2 System Clocks Generation. . . . . . . . . . . . . . . . . . . . . . . . .236
10.8.3 PLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
10.8.3.1 PLL Loss of Lock Conditions . . . . . . . . . . . . . . . . . . . . .238
10.8.3.2 PLL Loss of Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . .238
10.8.4 Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .238
10.8.4.1 Alternate Clock Selection. . . . . . . . . . . . . . . . . . . . . . . .239
10.8.4.2 Loss-of-Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .242
10.8.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . .243
10.8.6 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
10.8.6.1 Phase and Frequency Detector (PFD). . . . . . . . . . . . . .245
10.8.6.2 Charge Pump/Loop Filter. . . . . . . . . . . . . . . . . . . . . . . .245
10.8.6.3 Voltage Control Output (VCO) . . . . . . . . . . . . . . . . . . . .246
10.8.6.4 Multiplication Factor Divider (MFD) . . . . . . . . . . . . . . . .246
10.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
10.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
DDSYN
and V
SSSYN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Frees
11.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
11.3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
11.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .249
11.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
11.4.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
11.4.2.1 Port Output Data Registers . . . . . . . . . . . . . . . . . . . . . . 251
11.4.2.2 Port Data Direction Registers. . . . . . . . . . . . . . . . . . . . .252
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Section 11. Ports Module
Freescale Semiconductor, Inc.
11.4.2.3 Port Pin Data/Set Data Registers . . . . . . . . . . . . . . . . .253
11.4.2.4 Port Clear Output Data Registers . . . . . . . . . . . . . . . . .254
11.4.2.5 Port C/D Pin Assignment Register. . . . . . . . . . . . . . . . . 255
11.4.2.6 Port E Pin Assignment Register. . . . . . . . . . . . . . . . . . .256
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
11.5.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
11.5.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Table of Contents
Section 12. Edge Port Module (EPORT)
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cale Semiconductor,
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12.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.3 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .262
12.3.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
12.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
12.4 Interrupt/General-Purpose I/O Pin Descriptions. . . . . . . . . . .263
12.5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .263
12.5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
12.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
12.5.2.1 EPORT Pin Assignment Register . . . . . . . . . . . . . . . . .264
12.5.2.2 EPORT Data Direction Register. . . . . . . . . . . . . . . . . . .266
12.5.2.3 Edge Port Interrupt Enable Register . . . . . . . . . . . . . . .267
12.5.2.4 Edge Port Data Register . . . . . . . . . . . . . . . . . . . . . . . .268
12.5.2.5 Edge Port Pin Data Register . . . . . . . . . . . . . . . . . . . . .268
12.5.2.6 Edge Port Flag Register. . . . . . . . . . . . . . . . . . . . . . . . .269
Section 13. Watchdog Timer Module
13.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
13.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
13.3.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
13.3.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
13.3.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
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13.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
13.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
13.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .274
13.6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
13.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
13.6.2.1 Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . .275
13.6.2.2 Watchdog Modulus Register . . . . . . . . . . . . . . . . . . . . .277
13.6.2.3 Watchdog Count Register . . . . . . . . . . . . . . . . . . . . . . .278
13.6.2.4 Watchdog Service Register . . . . . . . . . . . . . . . . . . . . . .279
Section 14. Programmable Interrupt Timer Modules
(PIT1 and PIT2)
14.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
cale Semiconductor,
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14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
14.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.4.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.4.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.6.2.1 PIT Control and Status Register . . . . . . . . . . . . . . . . . .285
14.6.2.2 PIT Modulus Register . . . . . . . . . . . . . . . . . . . . . . . . . .288
14.6.2.3 PIT Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
14.7.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . .290
14.7.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . .291
14.7.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
14.8 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
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Table of Contents
Section 15. Timer Modules (TIM1 and TIM2)
15.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
15.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
15.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
15.5.1 Supervisor and User Modes. . . . . . . . . . . . . . . . . . . . . . . .297
15.5.2 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
15.5.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
15.5.4 Wait, Doze, and Debug Modes . . . . . . . . . . . . . . . . . . . . .297
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15.5.5 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
15.6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
15.6.1 ICOC[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
15.6.2 ICOC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
cale Semiconductor,
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15.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .298
15.7.1 Timer Input Capture/Output Compare
Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
15.7.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 301
15.7.3 Timer Output Compare 3 Mask Register . . . . . . . . . . . . . .302
15.7.4 Timer Output Compare 3 Data Register . . . . . . . . . . . . . . .303
15.7.5 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . .304
15.7.6 Timer System Control Register 1. . . . . . . . . . . . . . . . . . . .305
15.7.7 Timer Toggle-On-Overflow Register . . . . . . . . . . . . . . . . .306
15.7.8 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.7.9 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.7.10 Timer Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . .309
15.7.11 Timer System Control Register 2. . . . . . . . . . . . . . . . . . . .310
15.7.12 Timer Flag Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
15.7.13 Timer Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
15.7.14 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .314
15.7.15 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . .315
15.7.16 Pulse Accumulator Flag Register. . . . . . . . . . . . . . . . . . . .317
15.7.17 Pulse Accumulator Counter Registers . . . . . . . . . . . . . . . .318
15.7.18 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . .319
15.7.19 Timer Port Data Direction Register . . . . . . . . . . . . . . . . . .320
15.7.20 Timer Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
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15.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
15.8.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
15.8.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
15.8.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
15.8.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
15.8.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .323
15.8.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . .324
15.8.5 General-Purpose I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . .325
15.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
15.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
15.10.1 Timer Channel Interrupts (CxF) . . . . . . . . . . . . . . . . . . . . .326
15.10.2 Pulse Accumulator Overflow (PAOVF). . . . . . . . . . . . . . . .327
15.10.3 Pulse Accumulator Input (PAIF). . . . . . . . . . . . . . . . . . . . .327
15.10.4 Timer Overflow (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
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Section 16. Serial Communications Interface Modules
(SCI1 and SCI2)
16.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
16.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
16.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
16.5.1 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
16.6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
16.6.1 RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
16.6.2 TXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
16.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .334
16.7.1 SCI Baud Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . .336
16.7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
16.7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
16.7.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
16.7.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
16.7.6 SCI Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
16.7.7 SCI Pullup and Reduced Drive Register . . . . . . . . . . . . . .346
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16.7.8 SCI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .347
16.7.9 SCI Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . .348
16.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
16.9 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
16.10 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
16.11 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
16.11.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
16.11.2 Transmitting a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
16.11.3 Break Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
16.11.4 Idle Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
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16.12 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
16.12.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
16.12.2 Receiving a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
16.12.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
16.12.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
16.12.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
16.12.5.1 Slow Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .363
16.12.5.2 Fast Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .364
16.12.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
16.12.6.1 Idle Input Line Wakeup (WAKE = 0) . . . . . . . . . . . . . . .365
16.12.6.2 Address Mark Wakeup (WAKE = 1). . . . . . . . . . . . . . . .365
16.13 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
16.14 Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
16.15 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
16.16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
16.17 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
16.17.1 Transmit Data Register Empty. . . . . . . . . . . . . . . . . . . . . .369
16.17.2 Transmission Complete . . . . . . . . . . . . . . . . . . . . . . . . . . .369
16.17.3 Receive Data Register Full. . . . . . . . . . . . . . . . . . . . . . . . .370
16.17.4 Idle Receiver Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
16.17.5 Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
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Section 17. Serial Peripheral Interfac e Module ( SPI)
17.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
17.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
17.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
17.6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
17.6.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .374
17.6.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .374
17.6.3 SCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
17.6.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
17.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .375
17.7.1 SPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
17.7.2 SPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
17.7.3 SPI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .379
17.7.4 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
17.7.5 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
17.7.6 SPI Pullup and Reduced Drive Register . . . . . . . . . . . . . .383
17.7.7 SPI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .384
17.7.8 SPI Port Data Direction Register . . . . . . . . . . . . . . . . . . . .385
17.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
17.8.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
17.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
17.8.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
17.8.3.1 Transfer Format When CPHA = 1 . . . . . . . . . . . . . . . . .388
17.8.3.2 Transfer Format When CPHA = 0 . . . . . . . . . . . . . . . . .390
17.8.4 SPI Baud Rate Generation. . . . . . . . . . . . . . . . . . . . . . . . .393
17.8.5 Slave-Select Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
17.8.6 Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
17.8.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.8.7.1 Write Collision Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
17.8.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.8.8 Low-Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . .396
17.8.8.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
17.8.8.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
17.8.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
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17.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
17.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
17.10.1 SPI Interrupt Flag (SPIF) . . . . . . . . . . . . . . . . . . . . . . . . . .397
17.10.2 Mode Fault (MODF) Flag . . . . . . . . . . . . . . . . . . . . . . . . . .397
Table of Contents
Section 18. Queued Analog-to-Digital
Converter (QADC)
18.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
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18.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
18.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
18.5.1 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
18.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
18.6 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
18.6.1 Port QA Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
18.6.1.1 Port QA Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .406
18.6.1.2 Port QA Digital Input/Output Pins . . . . . . . . . . . . . . . . .407
18.6.2 Port QB Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
18.6.2.1 Port QB Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .407
18.6.2.2 Port QB Digital Input Pins . . . . . . . . . . . . . . . . . . . . . . .407
18.6.3 External Trigger Input Pins. . . . . . . . . . . . . . . . . . . . . . . . .408
18.6.4 Multiplexed Address Output Pins. . . . . . . . . . . . . . . . . . . .408
18.6.5 Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . .409
18.6.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .409
18.6.7 Dedicated Analog Supply Pins. . . . . . . . . . . . . . . . . . . . . .409
18.7 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
18.8 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
18.8.1 QADC Module Configuration Register . . . . . . . . . . . . . . . .411
18.8.2 QADC Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
18.8.3 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
18.8.4 Port QA Data Direction Register . . . . . . . . . . . . . . . . . . . .414
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18.8.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
18.8.5.1 Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
18.8.5.2 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
18.8.5.3 QADC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . .422
18.8.6 Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
18.8.6.1 QADC Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . .427
18.8.6.2 QADC Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . .436
18.8.7 Conversion Command Word Table . . . . . . . . . . . . . . . . . .437
18.8.8 Result Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
18.8.8.1 Right-Justified Unsigned Result Register. . . . . . . . . . . .441
18.8.8.2 Left-Justified Signed Result Register. . . . . . . . . . . . . . .442
18.8.8.3 Left-Justified Unsigned Result Register. . . . . . . . . . . . .442
18.9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
18.9.1 QADC Bus Accessing . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
18.9.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
18.9.2.1 External Multiplexing Operation. . . . . . . . . . . . . . . . . . .443
18.9.2.2 Module Version Options. . . . . . . . . . . . . . . . . . . . . . . . .444
18.9.2.3 External Multiplexed Address Configuration . . . . . . . . .446
18.9.3 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446
18.9.3.1 Analog-to-Digital Converter Operation. . . . . . . . . . . . . .446
18.9.3.2 Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . .446
18.9.3.3 Channel Decode and Multiplexer. . . . . . . . . . . . . . . . . .448
18.9.3.4 Sample Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448
18.9.3.5 Digital-to-Analog Converter (DAC) Array. . . . . . . . . . . .449
18.9.3.6 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
18.9.3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
18.9.3.8 Successive-Approximation Register . . . . . . . . . . . . . . .449
18.9.3.9 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
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18.10 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
18.10.1 Queue Priority Timing Examples. . . . . . . . . . . . . . . . . . . .450
18.10.1.1 Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
18.10.1.2 Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . .453
18.10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465
18.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466
18.10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
18.10.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
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18.10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
18.10.6.1 Software-Initiated Single-Scan Mode. . . . . . . . . . . . . . .468
18.10.6.2 External Trigger Single-Scan Mode . . . . . . . . . . . . . . . .469
18.10.6.3 External Gated Single-Scan Mode. . . . . . . . . . . . . . . . .470
18.10.6.4 Interval Timer Single-Scan Mode. . . . . . . . . . . . . . . . . .470
18.10.7 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . .472
18.10.7.1 Software-Initiated Continuous-Scan Mode. . . . . . . . . . .473
18.10.7.2 External Trigger Continuous-Scan Mode. . . . . . . . . . . . 474
18.10.7.3 External Gated Continuous-Scan Mode . . . . . . . . . . . .474
18.10.7.4 Periodic Timer Continuous-Scan Mode. . . . . . . . . . . . .475
18.10.8 QADC Clock (QCLK) Generation. . . . . . . . . . . . . . . . . . . .476
18.10.9 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .480
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18.10.10 Conversion Command Word Table . . . . . . . . . . . . . . . . . .481
18.10.11 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485
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18.11 Pin Connection Considerations . . . . . . . . . . . . . . . . . . . . . . .486
18.11.1 Analog Reference Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .486
18.11.2 Analog Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486
18.11.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . .488
18.11.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . .490
18.11.5 Accommodating Positive/Negative Stress Conditions . . . .494
18.11.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . .495
18.11.7 Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .497
18.11.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . .498
18.11.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . .499
18.12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500
18.12.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500
18.12.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501
Section 19. External Bus Interface Module (EBI)
19.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
19.3 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505
19.3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506
19.3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . .506
19.3.3 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . .506
19.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . .506
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19.3.5 Emulation Mode Chip Selects (CSE[1:0]) . . . . . . . . . . . . .506
19.3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .506
19.3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
19.3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
19.3.9 Enable Byte (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
19.3.10 Chip Selects (CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
19.3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
19.3.12 Transfer Size (TSIZ[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .507
19.3.13 Processor Status (PSTAT[3:0]) . . . . . . . . . . . . . . . . . . . . .507
19.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .508
19.5 Operand Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508
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19.6 Enable Byte Pins (EB[3:0]
19.7 Bus Master Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510
19.7.1 Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
19.7.1.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512
19.7.1.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .512
19.7.1.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512
19.7.2 Write Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513
19.7.2.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514
19.7.2.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .514
19.7.2.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514
19.8 Bus Exception Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .516
19.8.1 Transfer Error Termination. . . . . . . . . . . . . . . . . . . . . . . . .516
19.8.2 Transfer Abort Termination . . . . . . . . . . . . . . . . . . . . . . . .516
19.9 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .516
19.9.1 Emulation Chip-Selects (CSE[1:0]) . . . . . . . . . . . . . . . . . .516
19.9.2 Internal Data Transfer Display (Show Cycles) . . . . . . . . . .517
19.9.3 Show Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518
19.10 Bus Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519
). . . . . . . . . . . . . . . . . . . . . . . . . . .510
19.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .520
Section 20. Chip Select Module
20.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .522
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20.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523
20.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
20.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .524
20.6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
20.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525
20.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530
20.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
Table of Contents
Section 21. JTAG Test Access Port and OnCE
21.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533
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21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
21.3 Top-Level Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . .537
21.3.1 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
21.3.2 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . .538
21.3.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
21.3.4 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . .538
21.3.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
21.3.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
21.4 Top-Level TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . .540
21.5 Instruction Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .541
21.5.1 EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541
21.5.2 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
21.5.3 SAMPLE/PRELOAD Instruction. . . . . . . . . . . . . . . . . . . . .543
21.5.4 ENABLE_MCU_ONCE Instruction. . . . . . . . . . . . . . . . . . .543
21.5.5 HIGHZ Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
21.5.6 CLAMP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
21.5.7 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
21.6 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
21.7 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546
21.8 Boundary SCAN Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .546
21.9 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546
21.10 Non-Scan Chain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .547
21.11 Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
21.12 Low-Level TAP (OnCE) Module. . . . . . . . . . . . . . . . . . . . . . .553
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21.13 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
21.13.1 Debug Serial Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . .555
21.13.2 Debug Serial Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . .555
21.13.3 Debug Serial Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . .555
21.13.4 Debug Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . .556
21.13.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.13.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
21.14.2 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .558
21.14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .559
21.14.3.1 Internal Debug Request Input (IDR) . . . . . . . . . . . . . . .559
21.14.3.2 CPU Debug Request (DBGRQ
21.14.3.3 CPU Debug Acknowledge (DBGACK). . . . . . . . . . . . . .560
21.14.3.4 CPU Breakpoint Request (BRKRQ
21.14.3.5 CPU Address, Attributes (ADDR, ATTR). . . . . . . . . . . .560
21.14.3.6 CPU Status (PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . .560
21.14.3.7 OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . . .560
21.14.4 OnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . .561
21.14.4.1 OnCE Command Register. . . . . . . . . . . . . . . . . . . . . . .561
21.14.4.2 OnCE Control Register . . . . . . . . . . . . . . . . . . . . . . . . .564
21.14.4.3 OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .568
21.14.5 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . .570
21.14.6 Memory Breakpoint Logic. . . . . . . . . . . . . . . . . . . . . . . . . .570
21.14.6.1 Memory Address Latch (MAL). . . . . . . . . . . . . . . . . . . .571
21.14.6.2 Breakpoint Address Base Registers . . . . . . . . . . . . . . .571
21.14.7 Breakpoint Address Ma sk Registers . . . . . . . . . . . . . . . . .571
21.14.7.1 Breakpoint Address Comparators . . . . . . . . . . . . . . . . .572
21.14.7.2 Memory Breakpoint Counters . . . . . . . . . . . . . . . . . . . .572
21.14.8 OnCE Trace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
21.14.8.1 OnCE Trace Counter. . . . . . . . . . . . . . . . . . . . . . . . . . .573
21.14.8.2 Trace Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
21.14.9 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . .574
21.14.9.1 Debug Request During RESET
21.14.9.2 Debug Request During Normal Activity . . . . . . . . . . . . .575
21.14.9.3 Debug Request During Stop, Doze, or Wait Mode . . . .575
21.14.9.4 Software Request During Normal Activity . . . . . . . . . . .575
). . . . . . . . . . . . . . . . . . .560
). . . . . . . . . . . . . . . .560
. . . . . . . . . . . . . . . . . . .574
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21.14.10 Enabling OnCE Trace Mode . . . . . . . . . . . . . . . . . . . . . . .575
21.14.11 Enabling OnCE Memory Breakpoints. . . . . . . . . . . . . . . . .576
21.14.12 Pipeline Information and Write-Back Bus Register . . . . . .576
21.14.12.1 Program Counter Register. . . . . . . . . . . . . . . . . . . . . . .577
21.14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .577
21.14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . . 577
21.14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . .579
21.14.12.5 Processor Status Register. . . . . . . . . . . . . . . . . . . . . . .579
21.14.13 Instruction Address FIFO Buffer (PC FIFO). . . . . . . . . . . .580
21.14.14 Reserved Test Control Registers. . . . . . . . . . . . . . . . . . . .581
21.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
21.14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
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21.14.17 Target Site Debug System Requirements . . . . . . . . . . . . .582
21.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . .582
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Section 22. Electrical Specifications
22.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
22.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .586
22.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
22.5 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
22.6 Electrostatic Discharge (ESD) Protection. . . . . . . . . . . . . . . .587
22.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .588
22.8 PLL Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .590
22.9 QADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .591
22.10 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .594
22.11 External Interface Timing Characteristics. . . . . . . . . . . . . . . .596
22.12 Reset and Configuration Override Timing . . . . . . . . . . . . . . .601
22.13 SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .602
22.14 OnCE, JTAG, and Boundary Scan Timing . . . . . . . . . . . . . . .605
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Section 23. Mechan ical Specifications
23.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
23.3 Bond Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610
23.4 Package Information for the 144-Pin LQFP . . . . . . . . . . . . . .611
23.5 Package Information for the 100-Pin LQFP . . . . . . . . . . . . . .611
23.6 144-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . .612
23.7 100-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . .613
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Section 24. Ordering Information
24.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
24.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
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Technical Data — MMC2107
Figure Title P age
1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2-1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3-1 Chip Configuration Module Block Diagram . . . . . . . . . . . . .92
3-2 Chip Configuration Register (CCR) . . . . . . . . . . . . . . . . . . .94
3-3 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . .97
3-4 Chip Identification Register (CIR). . . . . . . . . . . . . . . . . . . . .99
3-5 Chip Test Register (CTR). . . . . . . . . . . . . . . . . . . . . . . . . .100
4-1 144-Pin LQFP Assignments. . . . . . . . . . . . . . . . . . . . . . . .115
4-2 100-Pin LQFP Assignments. . . . . . . . . . . . . . . . . . . . . . . .116
5-1 Reset Controller Block Diagram. . . . . . . . . . . . . . . . . . . . .131
5-2 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . .133
5-3 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . .134
5-4 Reset Test Register (RTR). . . . . . . . . . . . . . . . . . . . . . . . .135
5-5 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
6-1 M•CORE Processor Block Diagram . . . . . . . . . . . . . . . . . .145
6-2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6-3 Data Organization in Memory. . . . . . . . . . . . . . . . . . . . . . .149
6-4 Data Organization in Registers . . . . . . . . . . . . . . . . . . . . .149

List of Figures

7-1 Interrupt Controller Block Diagram. . . . . . . . . . . . . . . . . . .155
7-2 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . .157
7-3 Interrupt Status Register (ISR). . . . . . . . . . . . . . . . . . . . . .159
7-4 Interrupt Force Register High (IFRH) . . . . . . . . . . . . . . . . .160
7-5 Interrupt Force Register Low (IFRL). . . . . . . . . . . . . . . . . .161
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Figure Title P age
7-6 Interrupt Pending Register (IPR) . . . . . . . . . . . . . . . . . . . .162
7-7 Normal Interrupt Enable Register (NIER). . . . . . . . . . . . . .163
7-8 Normal Interrupt Pending Register (NIPR). . . . . . . . . . . . .164
7-9 Fast Interrupt Enable Register (FIER) . . . . . . . . . . . . . . . .165
7-10 Fast Interrupt Pending Register (FIPR ) . . . . . . . . . . . . . . .166
7-11 Priority Level Select Registers (PLSR0–PLSR39). . . . . . .167
9-1 CMFR 128-Kbyte Block Diagram . . . . . . . . . . . . . . . . . . . .183
9-2 CMFR Array and Control Register A ddressing . . . . . . . . .186
9-3 CMFR Module Configuration Register (CMFRMCR) . . . . .188
9-4 CMFR Module Test Register (CMFRMTR) . . . . . . . . . . . .193
9-5 CMFR High-Voltage Control Register (CMFRCTL) . . . . . .196
9-6 Pulse Status Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
9-7 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . .209
9-8 Program State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .210
9-9 FLASH Erasing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . .216
9-10 Erase State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
10-1 Clock Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .224
10-2 Synthesizer Control Register (SYNCR) . . . . . . . . . . . . . . .227
10-3 Synthesizer Status Register (SYNSR). . . . . . . . . . . . . . . .230
10-4 Synthesizer Test Register (SYNTR). . . . . . . . . . . . . . . . . .233
10-5 Synthesizer Test Register 2 (SYNTR2) . . . . . . . . . . . . . . .234
10-6 Lock Detect Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . .237
10-7 PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
10-8 Crystal Oscillator Example. . . . . . . . . . . . . . . . . . . . . . . . .244
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Technical Data MMC2107 – Rev. 2.0
30 List of Figures MOTOROLA
11-1 Ports Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . .248
11-2 Port Output Data Registers (PORTx). . . . . . . . . . . . . . . . .251
11-3 Port Data Direction Registers (DDRx) . . . . . . . . . . . . . . . .252
11-4 Port Pin Data/Set Data Registers (PORTxP/SETx) . . . . . .253
11-5 Port Clear Output Data Registers (CLRx) . . . . . . . . . . . . .254
11-6 Port C, D, I7, and I6 Pin Assignment
Register (PCDPAR). . . . . . . . . . . . . . . . . . . . . . . . . . . .255
11-7 Port E Pin Assignment Register (PEPAR). . . . . . . . . . . . .256
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Figure Title P age
11-8 Digital Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
11-9 Digital Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
12-1 EPORT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .262
12-2 EPORT Pin Assignment Register (EPPAR). . . . . . . . . . . .264
12-3 EPORT Data Direction Register (EPDDR). . . . . . . . . . . . .266
12-4 EPORT Port Interrupt Enable Register (EPIER) . . . . . . . .267
12-5 EPORT Port Data Register (EPDR). . . . . . . . . . . . . . . . . .268
12-6 EPORT Port Pin Data Register (EPPDR) . . . . . . . . . . . . .268
12-7 EPORT Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . 269
13-1 Watchdog Timer Block Diagram. . . . . . . . . . . . . . . . . . . . .273
13-2 Watchdog Control Register (WCR) . . . . . . . . . . . . . . . . . .275
13-3 Watchdog Modulus Register (WMR) . . . . . . . . . . . . . . . . .277
13-4 Watchdog Count Register (WCNTR) . . . . . . . . . . . . . . . . .278
13-5 Watchdog Service Register (WSR) . . . . . . . . . . . . . . . . . .279
14-1 PIT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
14-2 PIT Control and Status Register (PCSR) . . . . . . . . . . . . . .285
14-3 PIT Modulus Register (PMR) . . . . . . . . . . . . . . . . . . . . . . .288
14-4 PIT Count Register (PCNTR). . . . . . . . . . . . . . . . . . . . . . .289
14-5 Counter Reloading from the Modulus Latch. . . . . . . . . . . .290
14-6 Counter in Free-Running Mode . . . . . . . . . . . . . . . . . . . . .291
15-1 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
15-2 Timer Input Capture/Output Compare
15-3 Timer Compare Fo rce Register (TIMCFORC) . . . . . . . . . .301
15-4 Timer Output Compare 3 Mask Register (TIMOC3M) . . . .302
15-5 Timer Output Compare 3 Data Register (TIMOC3D). . . . .303
15-6 Timer Counter Register High (TIMCNTH) . . . . . . . . . . . . .304
15-7 Timer Counter Register Low (TIMCNTL) . . . . . . . . . . . . . .304
15-8 Timer System Control Register (TIMSCR1). . . . . . . . . . . .305
15-9 Fast Clear Flag Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15-10 Timer Toggle-On-Overflow Register (TIMTOV) . . . . . . . . .306
15-11 Timer Control Register 1 (TIMCTL1) . . . . . . . . . . . . . . . . .307
List of Figures
Select Register (TIMIOS) . . . . . . . . . . . . . . . . . . . . . . .300
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA List of Figures 31
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List of Figu r e s
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Figure Title P age
15-12 Timer Control Register 2 (TIMCTL2) . . . . . . . . . . . . . . . . .308
15-13 Timer Interrupt Enable Register (TIMIE) . . . . . . . . . . . . . .309
15-14 Timer System Control Register 2 (TIMSCR2) . . . . . . . . . .310
15-15 Timer Flag Register 1 (TIMFLG1) . . . . . . . . . . . . . . . . . . .312
15-16 Timer Flag Register 2 (TIMFLG2) . . . . . . . . . . . . . . . . . . .313
15-17 Timer Channel [0:3] Register High (TIMCxH) . . . . . . . . . .314
15-18 Timer Channel [0:3] Register Low (TIMCxL) . . . . . . . . . . . 314
15-19 Pulse Accumulator Control Register (TIMPACTL) . . . . . . .315
15-20 Pulse Accumulator Flag Register (TIMPAFLG) . . . . . . . . .317
15-21 Pulse Accumulator Counter Register High
15-22 Pulse Accumulator Counter Register Low
15-23 Timer Port Data Register (TIMPORT) . . . . . . . . . . . . . . . .319
15-24 Timer Port Data Direction Register (TIMDDR). . . . . . . . . .320
15-25 Timer Test Register (TIMTST) . . . . . . . . . . . . . . . . . . . . . .321
15-26 Channel 3 Output Compare/Pulse Accumulator Logic. . . .324
16-1 SCI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
16-2 SCI Baud Rate Register High (SCIBDH) . . . . . . . . . . . . . .336
16-3 SCI Baud Rate Register Low (SCIBDL). . . . . . . . . . . . . . .336
16-4 SCI Control Register 1 (SCICR1). . . . . . . . . . . . . . . . . . . .337
16-5 SCI Control Register 2 (SCICR2). . . . . . . . . . . . . . . . . . . .340
16-6 SCI Status Register 1 (SCISR1) . . . . . . . . . . . . . . . . . . . .342
16-7 SCI Status Register 2 (SCISR2) . . . . . . . . . . . . . . . . . . . .344
16-8 SCI Data Register High (SCIDRH). . . . . . . . . . . . . . . . . . .345
16-9 SCI Data Register Low (SCIDRL) . . . . . . . . . . . . . . . . . . .345
16-10 SCI Pullup and Reduced Drive Register (SCIPURD). . . . .346
16-11 SCI Port Data Register (SCIPORT). . . . . . . . . . . . . . . . . .347
16-12 SCI Data Direction Register (SCIDDR) . . . . . . . . . . . . . . . 348
16-13 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
16-14 Transmitter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .351
16-15 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .356
16-16 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .357
16-17 Start Bit Search Example 1 . . . . . . . . . . . . . . . . . . . . . . . .359
16-18 Start Bit Search Example 2 . . . . . . . . . . . . . . . . . . . . . . . .360
(TIMPACNTH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
(TIMPACNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
Technical Data MMC2107 – Rev. 2.0
32 List of Figures MOTOROLA
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Figure Title P age
16-19 Start Bit Search Example 3 . . . . . . . . . . . . . . . . . . . . . . . .360
16-20 Start Bit Search Example 4 . . . . . . . . . . . . . . . . . . . . . . . .361
16-21 Start Bit Search Example 5 . . . . . . . . . . . . . . . . . . . . . . . .361
16-22 Start Bit Search Example 6 . . . . . . . . . . . . . . . . . . . . . . . .362
16-23 Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
16-24 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
16-25 Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . .366
16-26 Loop Operation (LOOPS = 1, RSRC = 0) . . . . . . . . . . . . .367
17-1 SPI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
17-2 SPI Control Register 1 (SPICR1). . . . . . . . . . . . . . . . . . . .376
17-3 SPI Control Register 2 (SPICR2). . . . . . . . . . . . . . . . . . . .378
17-4 SPI Baud Rate Register (SP IBR). . . . . . . . . . . . . . . . . . . .379
17-5 SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . .381
17-6 SPI Data Register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . .382
17-7 SPI Pullup and Reduced Drive Register (SPIPURD). . . . .383
17-8 SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . .384
17-9 SPI Port Data Direction Register (SPIDDR). . . . . . . . . . . .385
17-10 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
17-11 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . .389
17-12 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . .391
17-13 Transmission Error Due to Master/Slave Clock Skew . . . .392
18-1 QADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
18-2 QADC Input and Output Signals . . . . . . . . . . . . . . . . . . . .406
18-3 QADC Module Configuration Register (QADCMCR). . . . .411
18-4 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .412
18-5 QADC Port QA Data Register (PORTQA) . . . . . . . . . . . . .413
18-6 QADC Port QB Data Register (PORTQB) . . . . . . . . . . . . .413
18-7 QADC Port QA Data Direction Register (DDRQA). . . . . . .415
18-8 QADC Control Register 0 (QACR0). . . . . . . . . . . . . . . . . .416
18-9 QADC Control Register 1 (QACR1). . . . . . . . . . . . . . . . . .419
18-10 QADC Control Register 2 (QACR2). . . . . . . . . . . . . . . . . .422
18-11 QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . . . .427
18-12 Queue Status Transition. . . . . . . . . . . . . . . . . . . . . . . . . . .435
18-13 QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . . . .436
List of Figures
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA List of Figures 33
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18-14 Conversion Command Word Table (CCW) . . . . . . . . . . . .437
18-15 Right-Justified Unsigned Result Register (RJURR). . . . . .441
18-16 Left-Justified Signed Result Register (LJSRR) . . . . . . . . .442
18-17 Left-Justified Unsigned Result Register (LJURR) . . . . . . .442
18-18 External Multiplexing Configuration . . . . . . . . . . . . . . . . . .445
18-19 QADC Analog Subsystem Block Diagram . . . . . . . . . . . . .447
18-20 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
18-21 Bypass Mode Conversion Timing. . . . . . . . . . . . . . . . . . . .448
18-22 QADC Queue Operation with Pause . . . . . . . . . . . . . . . . .452
18-23 CCW Priority Situation 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 455
18-24 CCW Priority Situation 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 456
18-25 CCW Priority Situation 3. . . . . . . . . . . . . . . . . . . . . . . . . . . 457
18-26 CCW Priority Situation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . 457
18-27 CCW Priority Situation 5. . . . . . . . . . . . . . . . . . . . . . . . . . . 458
18-28 CCW Priority Situation 6. . . . . . . . . . . . . . . . . . . . . . . . . . . 459
18-29 CCW Priority Situation 7. . . . . . . . . . . . . . . . . . . . . . . . . . . 459
18-30 CCW Priority Situation 8. . . . . . . . . . . . . . . . . . . . . . . . . . . 460
18-31 CCW Priority Situation 9. . . . . . . . . . . . . . . . . . . . . . . . . . . 460
18-32 CCW Priority Situation 10. . . . . . . . . . . . . . . . . . . . . . . . . .461
18-33 CCW Priority Situation 11. . . . . . . . . . . . . . . . . . . . . . . . . .461
18-34 CCW Freeze Situation 12. . . . . . . . . . . . . . . . . . . . . . . . . .462
18-35 CCW Freeze Situation 13. . . . . . . . . . . . . . . . . . . . . . . . . .462
18-36 CCW Freeze Situation 14. . . . . . . . . . . . . . . . . . . . . . . . . .463
18-37 CCW Freeze Situation 15. . . . . . . . . . . . . . . . . . . . . . . . . .463
18-38 CCW Freeze Situation 16. . . . . . . . . . . . . . . . . . . . . . . . . .463
18-39 CCW Freeze Situation 17. . . . . . . . . . . . . . . . . . . . . . . . . .464
18-40 CCW Freeze Situation 18. . . . . . . . . . . . . . . . . . . . . . . . . .464
18-41 CCW Freeze Situation 19. . . . . . . . . . . . . . . . . . . . . . . . . .464
18-42 QADC Clock Subsystem Functions . . . . . . . . . . . . . . . . . .477
18-43 QADC Clock Pro grammability Examples . . . . . . . . . . . . . .479
18-44 QADC Conversion Queue Operation. . . . . . . . . . . . . . . . .482
18-45 Equivalent Analog Input Circuitry. . . . . . . . . . . . . . . . . . . .487
18-46 Errors Resulting from Clipping. . . . . . . . . . . . . . . . . . . . . .488
18-47 External Positive Edge Trigger Mode
18-48 Gated Mode, Single Scan Timing. . . . . . . . . . . . . . . . . . . .491
Timing With Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . .489
Technical Data MMC2107 – Rev. 2.0
34 List of Figures MOTOROLA
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Figure Title P age
18-49 Gated Mode, Continuous Scan Timing . . . . . . . . . . . . . . .491
18-50 Star-Ground at the Point of Power Supply Origin. . . . . . . .493
18-51 Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . .494
18-52 Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . . 494
18-53 External Multiplexing of Analog Signal Sources. . . . . . . . .496
18-54 Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . .497
19-1 Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
19-2 Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .513
19-3 Master Mode — 1-Clock Read and Write Cycle. . . . . . . . .515
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19-4 Master Mode — 2-Clock Read and Write Cycle. . . . . . . . .515
19-5 Internal (Show) Cycle Fo llowed . . . . . . . . . . . . . . . . . . . . . . . .
19-6 Internal (Show) Cycle Followed
List of Figures
by External 1-Clock Read . . . . . . . . . . . . . . . . . . . . . . .518
by External 1-Clock Write . . . . . . . . . . . . . . . . . . . . . . .519
cale Semiconductor,
Frees
20-1 Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .523
20-2 Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . .525
20-3 Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . .526
20-4 Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . .526
20-5 Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . .527
21-1 Top-Level Tap Module and Low-Level (OnCE)
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
21-2 Top-Level TAP Controller State Machine. . . . . . . . . . . . . .540
21-3 IDCODE Register Bit Specification . . . . . . . . . . . . . . . . . .545
21-4 OnCE Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
21-5 Low-Level (OnCE) Tap Module Data Registers (DRs). . . .554
21-6 OnCE Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
21-7 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .559
21-8 OnCE Command Register (OCMR). . . . . . . . . . . . . . . . . .562
21-9 OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . .564
21-10 OnCE Status Register (OSR). . . . . . . . . . . . . . . . . . . . . . .568
21-11 OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . .570
21-12 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573
21-13 CPU Scan Chain Register (CPUSCR). . . . . . . . . . . . . . . .576
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA List of Figures 35
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21-14 Control State Register (CTL) . . . . . . . . . . . . . . . . . . . . . . .578
21-15 OnCE PC FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .580
21-16 Recommended Connector Interface
22-1 VPP versus Programming Time . . . . . . . . . . . . . . . . . . . . .595
22-2 VPP versus Programming Pulses. . . . . . . . . . . . . . . . . . . .595
22-3 CLKOUT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597
22-4 Clock Read/Write Cycle Timing . . . . . . . . . . . . . . . . . . . . .598
22-5 Read/Write Cycle Timing with Wait States. . . . . . . . . . . . .599
22-6 Show Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
22-7 RESET
22-8 SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603
22-9 Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .605
22-10 Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . . . 606
22-11 Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . .606
22-12 TRST
22-13 Debug Event Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .607
to JTAG/OnCE Port. . . . . . . . . . . . . . . . . . . . . . . . . . . .583
and Configuration Override Timing . . . . . . . . . . . .601
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
Frees
Technical Data MMC2107 – Rev. 2.0
36 List of Figures MOTOROLA
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Technical Data — MMC2107
Table Title Page
2-1 Register Address Location Map . . . . . . . . . . . . . . . . . . . . . . .53
3-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3-2 Write-Once Bits Read/Write Accessibility. . . . . . . . . . . . . . . .93
3-3 Chip Configuration Module Memo ry Map. . . . . . . . . . . . . . . . 9 4
3-4 Chip Configuration Mode Selection . . . . . . . . . . . . . . . . . . . . 9 5
3-5 Bus Monitor Timeout Values . . . . . . . . . . . . . . . . . . . . . . . . .97
3-6 Reset Configuration Pin States During Reset . . . . . . . . . . .101
3-7 Configuration During Reset . . . . . . . . . . . . . . . . . . . . . . . . .102
3-8 Chip Configuration Mode Selection . . . . . . . . . . . . . . . . . . .103
3-9 Chip Sele ct CS0 Configuration Encoding. . . . . . . . . . . . . . .104
3-10 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
3-11 Output Pad Driver Strength Selection . . . . . . . . . . . . . . . . .105
3-12 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
3-13 Internal FLASH Configuration. . . . . . . . . . . . . . . . . . . . . . . .106
4-1 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4-2 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5-1 Reset Controller Signal Properties. . . . . . . . . . . . . . . . . . . .131
5-2 Reset Controller Module Memory Map. . . . . . . . . . . . . . . . .132
5-3 Reset Source Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .136

List of Tables

6-1 M•CORE Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . .150
7-1 Interrupt Controller Module Memory Map. . . . . . . . . . . . . . .156
7-2 MASK Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
7-3 Priority Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
7-4 Fast Interrupt Vector Number. . . . . . . . . . . . . . . . . . . . . . . .170
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA List of Tables 37
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Table Title Page
7-5 Vector Table Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
7-6 Interrupt Source Assignment . . . . . . . . . . . . . . . . . . . . . . . .172
9-1 Non-Volatile Memory FLASH Memory Map. . . . . . . . . . . . .187
9-2 Negative Voltage Modulation . . . . . . . . . . . . . . . . . . . . . . . .194
9-3 Drain Amplitude Modulation (GDB = 0) . . . . . . . . . . . . . . . .195
9-4 System Clock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
9-5 Clock Period Exponent and Pulse Width Range . . . . . . . . .199
9-6 Determining SCLKR[2:0], CLKPE[1:0],
9-7 Progr am Interlock State Descriptions. . . . . . . . . . . . . . . . . .210
9-8 Results of Programming Margin Read . . . . . . . . . . . . . . . . .212
9-9 Required Programming Algorithm . . . . . . . . . . . . . . . . . . . .213
9-10 Erase Interlock State Descriptions. . . . . . . . . . . . . . . . . . . .217
9-11 Required Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .219
and CLKPM[6:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
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10-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10-2 Clock Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .226
10-3 System Frequency Multiplier of the Reference
Frequency in Normal PLL Mode . . . . . . . . . . . . . . . . . . .228
10-4 STPMD[1:0] Operation in Stop Mode. . . . . . . . . . . . . . . . . .230
10-5 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
10-6 Clock-Out and Clock-In Relationships . . . . . . . . . . . . . . . . .235
10-7 Loss of Clock Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
10-8 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
10-9 Charge Pump Current and MFD
in Normal Mode Operation . . . . . . . . . . . . . . . . . . . . . . .245
11-1 I/O Port Module Memory Map . . . . . . . . . . . . . . . . . . . . . . .250
11-2 PEPAR Reset Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
11-3 Ports A–I Supported Pin Functions . . . . . . . . . . . . . . . . . . .258
12-1 Edge Port Module Memory Map. . . . . . . . . . . . . . . . . . . . . .263
12-2 EPPAx Field Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
13-1 Watchdog Timer Module Memory Map . . . . . . . . . . . . . . . .274
Technical Data MMC2107 – Rev. 2.0
38 List of Tables MOTOROLA
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Table Title Page
14-1 Programmable Interrupt Timer Modules Memory Map. . . . .284
14-2 Prescaler Select Encoding. . . . . . . . . . . . . . . . . . . . . . . . . .286
14-3 PIT Interrupt Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
15-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
15-2 Timer Modules Memory Map . . . . . . . . . . . . . . . . . . . . . . . .299
15-3 Output Compare Action Selection . . . . . . . . . . . . . . . . . . . .307
15-4 Input Capture Edge Selection. . . . . . . . . . . . . . . . . . . . . . . .308
15-5 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
15-6 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
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15-7 TIMPORT I/O Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
15-8 Timer Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
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16-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
16-2 Seria l Communi cations Inter face Module
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
16-3 SCI Normal, Loop, and Single-Wire Mode
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
16-4 Example Baud Rates (System Clock = 33 MHz) . . . . . . . . .350
16-5 Example 10-Bit and 11-Bit Frames. . . . . . . . . . . . . . . . . . . .352
16-6 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
16-7 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
16-8 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
16-9 SCI Port Control Summary. . . . . . . . . . . . . . . . . . . . . . . . . .368
16-10 SCI Interrupt Request Sources. . . . . . . . . . . . . . . . . . . . . . .369
17-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
17-2 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
17-3 SS
17-4 Bidirectional Pin Configurations . . . . . . . . . . . . . . . . . . . . . .378
17-5 SPI Baud Rate Selection (33-MHz Module Clock) . . . . . . . .380
17-6 SPI Port Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
17-7 Normal Mode and Bidirectional Mode . . . . . . . . . . . . . . . . .394
17-8 SPI Interrupt Request Sources. . . . . . . . . . . . . . . . . . . . . . .397
Pin I/O Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . .377
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA List of Tables 39
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Table Title Page
18-1 Multiplexed Analog Input Channels . . . . . . . . . . . . . . . . . . .409
18-2 QADC Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
18-3 Prescaler Clock High Times. . . . . . . . . . . . . . . . . . . . . . . . .417
18-4 Prescaler Clock Low Times . . . . . . . . . . . . . . . . . . . . . . . . .418
18-5 Queue 1 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . .420
18-6 Queue 2 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . .423
18-7 Pause Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
18-8 Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
18-9 Input Sample Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .439
18-10 Non-Multiplexed Channel Assignments
18-11 Multiplexed C hanne l Assignment s
18-12 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444
18-13 Trigger Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
18-14 Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
18-15 QADC Clock Programmability . . . . . . . . . . . . . . . . . . . . . . .479
18-16 External Circuit Settling Time to 1/2 LSB
18-17 Error Resulting From Input Leakage (I
18-18 QADC Status Flags and Interrupt Sources. . . . . . . . . . . . . .500
19-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505
19-2 Data Transfer Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509
19-3 EB[3:0]
19-4 Emulation Mode Chip-Select Summary . . . . . . . . . . . . . . . .517
and Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . .440
and Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . .440
(10-Bit Conversions) . . . . . . . . . . . . . . . . . . . . . . . . . . . .499
) . . . . . . . . . . . . . .500
Off
Assertion Encoding . . . . . . . . . . . . . . . . . . . . . . . . .510
Frees
Technical Data MMC2107 – Rev. 2.0
40 List of Tables MOTOROLA
20-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
20-2 Chip Select Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . .524
20-3 Chip Select Wait States Encoding . . . . . . . . . . . . . . . . . . . .529
20-4 Chip Select Address Range Encoding . . . . . . . . . . . . . . . . .531
21-1 JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
21-2 List of Pins Not Scanned in JTAG Mode . . . . . . . . . . . . . . .548
21-3 Boundary-Scan Register Definition . . . . . . . . . . . . . . . . . . .549
21-4 OnCE Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . .563
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Table Title Page
21-5 Sequential Control Field Settings. . . . . . . . . . . . . . . . . . . . .565
21-6 Memory Breakpoint Control Field Settings. . . . . . . . . . . . . .567
21-7 Processor Mode Field Settings. . . . . . . . . . . . . . . . . . . . . . .569
22-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .586
22-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
22-3 ESD Protection Characteristics . . . . . . . . . . . . . . . . . . . . . .587
22-4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .588
22-5 PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .590
22-6 QADC Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . .591
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22-7 QADC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .592
22-8 QADC Conversion Specifications. . . . . . . . . . . . . . . . . . . . .593
22-9 FLASH Program and Erase Characteristics. . . . . . . . . . . . .594
22-10 FLASH EEPROM Module Life Characte ristics. . . . . . . . . . .594
22-11 External Interface Timing Characteristics. . . . . . . . . . . . . . .596
22-12 Reset and Configuration Override Timing . . . . . . . . . . . . . .601
22-13 SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .602
22-14 OnCE, JTAG, and Boundary Scan Timing. . . . . . . . . . . . . .605
24-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
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List of Tables
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MMC2107 – Rev. 2.0 Technical Data
MOTOROLA List of Tables 41
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Technical Data MMC2107 – Rev. 2.0
42 List of Tables MOTOROLA
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Technical Data — MMC2107

1.1 Contents

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Section 1. General Description

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8

1.2 Introduction

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The MMC2107 is the first member of a family of general-purpose microcontrollers (MCU) based on the M•CORE™ M210 central processor unit (CPU).
As a low-voltage part, the MMC2107 operates at voltages between
2.7 volts and 3.6 volts. It is particul arly suited fo r use in bat tery-pow ered applications. The operating frequency is up to a maximum of 33 MHz over a temperature range of –40°C to 85°C.
Available packages are 100-pin low-profile quad flat pack (LQFP) or a 144-pin LQFP for applications requiring the full external memory interface support or a large number of general-purpose inputs/outputs (GPIO).
™M•CORE is a trademark of Motorola, Inc.
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA General Description 43
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General Description

1.3 Features

Freescale Semiconductor, Inc.
Features of the MM C2107 include:
• M•CORE M210 integer processor:
• OnCE™ debug support
• On-chip 128-Kbyte FLASH:
– 32-bit reduced instruction set computer (RISC) architecture – Low power and high performance
– Motorola’s one transistor, CDR MoneT – Page mode (2111) read access
(1)
FLASH bit cell
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– External V – 16-K block size
• On-chip, 8-Kbyte static random-access memory (SRAM): – One clock per access (in cluding bytes, half-words, and words) – Byte, half-word (16 bits), and word (32 bits) read/write
accesses
– Standby power supply support
• Serial peripheral interface (SPI): – Master mode and slave mode – Wired-OR mode – Slave select output – Mode fault error flag with CPU interrupt capability – Double-buffered operation – Serial clock with programmable polarity and phase – Control of SPI operation during wait mode – Reduced drive control
required for programming
PP
™OnCE is a trademark of Motorola, Inc.
1. CDR MoneT designates the Motorola one-transistor bi tcell.
Technical Data MMC2107 – Rev. 2.0
44 General Descri ptio n MOTOR OLA
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• Two serial communications interfaces (SCI):
General Description
– Full-duplex operation – Standard mark/space non-return-to-zero (NRZ) format – 13-bit baud rate selection – Programmable 8-bit or 9-bit data format – Separately enabled transmitter and receiver – Separate receiver and transmitter CPU interrupt requests – Programmable transmitter output polarity – Two receiver wakeup methods (idle line and address mark) – Interrupt-driven operation with eight flags
Features
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– Receiver framing error detection – Hardware parity checking – 1/16 bit-time noise detection – General-purpose input/output port
• Two timers: – Four 16-bit input capture/outpu t compare channels – 16-bit architecture – 16-bit pulse accumulator – Pulse widths variable from microseconds to seconds – Prescaler – Toggle-on-overflow feature for pulse-width modulator (PWM)
generation
– Timer port pullups enabled on reset
• Queued analog-to-digital converter (QADC): – Eight analog input channels – 10-bit resolution ±2 counts accuracy – Minimum 7 µs conversion time – Internal sample and hold – Programmable input sample time for various source
impedances – Two conversion command queues with a total of 64 entries – Subqueues possible using pause mechanism – Queue complete and pause software interrupts available on
both queues
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA General Description 45
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General Description
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– Queue pointers indicate current location for each queue – Automated queue modes initiated by:
External edge trigger and gated trigger Periodic/interval timer, within queued analog-to-digital
converter (QADC) module {queue1 and queue2}
Software command – Single-scan or continuous-scan of queues – Output data readable in three formats:
Right-justified unsigned
Left-justified signed
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Left-justified unsigned – Unused analog channels can be used as digital input/output
(I/O)
– Minimum pin set configuration implemented
• Interrupt controller: – Up to 40 interrupt sources – 32 unique programmable priority levels for each interrupt
source
– Independent enable/disable of pending interrupts based on
priority level – Select normal or fast interrupt request for each priority level – Fast interrupt requests always have priority over normal
interrupts. – Ability to mask interrupts at and below a defined priority level – Ability to select between autovectored or vectored interrupt
requests – Vectored interrupts generated based on priority level – Ability to generate a separate vector number for normal and
fast interrupts – Ability for software to self-schedule interrupts – Software visibility of pending inte rrupts and int errupt s ignals to
core – Asynchronous operation to support wakeup from low-power
modes
Technical Data MMC2107 – Rev. 2.0
46 General Descri ptio n MOTOR OLA
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• External interrupts supported:
• Periodic interval timer:
• Watchdog timer:
General Description
– Rising/falling edge select – Low-level sensitive – Ability for software generation of external interrupt event – General-purpose input/output support
– 16-bit counter – Selectable as free running or count down
– 16-bit counter
Features
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– Low-power mode support
• Phase-lock loop (PLL): – Reference crystal from 2 to 10 MHz – Low-power modes supported – Separate clock-out signal
• Reset: – Separate reset in and reset out signals – Six sources of reset:
Power-on reset (POR) External Software Watchdog Loss of clock Loss of lock
– Status flag indication of source of last reset
• Chip configurations: – Support for single-chip, master, emulation, and test modes – System configuration during reset – Bus monitor – Configurable output pad drive strength control
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA General Description 47
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General Description
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• General-purpose input/output (GPIO):
• M•CORE to IPbus interface:
– Up to 72 bits of GPIO – Coherent 32-bit control – Bit manipulation supported via set/clear functions – Unused peripheral pins may be used as extra GPIO. – Reduced drive control
– Complete interfa cing between th e M•CORE bus and the IPbus
peripheral bus
– Minimum of three clocks for periphera l bus access
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– Data alignment and data width conversion between the
M•CORE 32-bit data bus and the IPbus peripheral data buses
• External interface: – Provides for direct support of asynchronous random-access
memory (RAM), read-only memory (ROM), and FLASH – Support interfacing to 16-bit and 32-bit data buses – 32-bit external bidirectional data bus – 23-bit address bus – Four chip selects – Byte/write enables – Ability to boot from internal or external memories – Internal bus activity is visible via show-cycle mode – Special chip selects support replacement of GPIO with
external logic (port replacement logic) – Emulation of internal page mode FLASH support
• Joint Test Action Group (JTAG) support for system-level board testing

1.4 Block Diagram

The basic structure of the MMC2107 is shown in Figure 1-1.
Technical Data MMC2107 – Rev. 2.0
48 General Descri ptio n MOTOR OLA
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General Description
Block Diagram
SRAM
8-KBYTE
TIMER 1
TIMER 2
TIMER
STBY
V
M•CORE BUS
IPBUS
OSC/PLL
128-KBYTE
SPI
FLASH
CS
TEST
POR
RESET
EXTERNAL MEMORY INTERFACE
ADC
VSS x 8 V
x 8
DD
V
PP
V
, V
DDF
SSF
D[31:0] A[22:0] R/W EB[3:0]
CS[3:0]
PORTS
TC[2:0] SHS
CSE[1:0] TA
TEA OE
TEST EXTAL XTAL
CLKOUT V
DDSYN
V
SSSYN
RESET RSTOUT
VRL, V V
, V
DDA
V
DDH
RH
SSA
TMS
TDI
TDO
TCLKDETRST
JTAG
TAP
OnCE
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INT[7:0]
PSTAT[3:0]
INTERRUPT
CONTROLLER
M•CORE (M210)
EDGE
PORT
IPBUS INTERFACE
PROGRAMMABLE
INTERVAL
PROGRAMMABLE
INTERVAL
WATCHDOG
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TIM1
TIM2
SCI1 SCI2
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SS
SCK
TXD1
RXD1
ICOC1[3:0]
ICOC2[3:0]
TXD2
RXD2
Figure 1-1. Block Diagram
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA General Description 49
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MISO
MOSI
PQB[3:0]
PQA[4:3]
PQA[1:0]
General Description
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Technical Data MMC2107 – Rev. 2.0
50 General Descri ptio n MOTOR OLA
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Technical Data — MMC2107

2.1 Contents

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Section 2. System Memory Map

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.3 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.2 Introduction

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The address map, shown in Figure 2-1, includes:
• 128 Kbytes of internal FLASH
• 8 Kbytes of internal static random-access memory (SRAM)
• Internal memory mapped registers
• External address space
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 51
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System Memory Map

2.3 Address Map

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EXTERNAL MEMORY
0x8000_0000
REGISTERS
SEE 2.4 Register Map
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0x00c0_0000
INTERNAL SRAM
0x0080_0000
0
8 KBYTES
INTERNAL FLASH
128
K
BYTES
Figure 2-1. Address Map
Technical Data MMC2107 – Rev. 2.0
52 System Memory Map MOTOROLA
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System Memory Map
Address Map
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Table 2-1. Register Address Location Map
Base Address (Hex) Usage
0x00c0_0000 0x00c1_0000 Chip configuration (CCM)
0x00c2_0000 Chip selects (CS) 0x00c3_0000 Clocks (CLOCK) 0x00c4_0000 Reset (RESET) 0x00c5_0000 Interrupt controller (INTC) 0x00c6_0000 Edge port (EPORT) 0x00c7_0000 Watchdog timer (WDT) 0x00c8_0000 Programmable interrupt timer 1 (PIT1) 0x00c9_0000 Programmable interrupt timer 2 (PIT2) 0x00ca_0000 Queued analog-to-digital converter (QADC) 0x00cb_0000 Serial peripheral interface (SPI) 0x00cc_0000 Serial communications interface 1 (SCI1) 0x00cd_0000 Serial communications interface 2 (SCI2) 0x00ce_0000 Timer 1 (TIM1)
0x00cf_0000 Timer 2 (TIM2)
0x00d0_0000 FLASH reg isters (CMFR)
1. See module se ction s f or deta ils o f h ow much of each block i s being dec oded. Ac cess es to addresses outside the module memory maps (and also the res erved area 0x00d1_0000–0x7fff_ffff) wi ll not be responded to and will result in a bus monit or transfer error exception.
2. The port register space is mirrored/repeated in the 64-Kbyte block. This allows the f ull 64-Kbyte block to be decoded and used to execute an external access to a port replacement uni t in emulation mode.
Ports
(2)
(PORTS)
(1)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 53
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System Memory Map

2.4 Register Map

Address Register Name Bit Number
Ports (PORTS)
Bit 765432 1Bit 0
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cale Semiconductor,
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0x00c0_0000
0x00c0_0001
0x00c0_0002
0x00c0_0003
0x00c0_0004
0x00c0_0005
Port A Output Data
Register (PORTA)
See page 251.
Port B Output Data
Register (PORTB)
See page 251.
Port C Output Data
Register (PORTC)
See page 251.
Port D Output Data
Register (PORTD)
See page 251.
Port E Output Data
Register (PORTE)
See page 251.
Port F Output Data
Register (PORTF)
See page 251.
Read:
PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0
Write:
Reset:11111111
Bit 7654321Bit 0
Read:
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
Write:
Reset:11111111
Bit 7654321Bit 0
Read:
PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0
Write:
Reset:11111111
Bit 7654321Bit 0
Read:
PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0
Write:
Reset:11111111
Bit 7654321Bit 0
Read:
PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0
Write:
Reset:11111111
Bit 7654321Bit 0
Read:
PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0
Write:
Reset:11111111
Bit 7654321Bit 0
Port G Output Data
0x00c0_0006
P = Current pin state U = Unaffected
Register (PORTG)
See page 251.
Read:
PORTG7 PORTG6 P ORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0
Write:
Reset:11111111
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 1 of 34)
Technical Data MMC2107 – Rev. 2.0
54 System Memory Map MOTOROLA
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Address Register Name Bit Number
Read: Write:
Reset:11111111
0x00c0_0007
Port H Output Data
Register (PORTH)
See page 251.
Bit 7654321Bit 0
PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0
Bit 7654321Bit 0
System Memory Map
Register Map
nc...
I
cale Semiconductor,
Frees
0x00c0_0008
0x00c0_0009
↓
0x00c0_000b
0x00c0_000c
0x00c0_000d
0x00c0_000e
0x00c0_000f
Port I Outpu t D a ta
Register (PORTI)
See page 251.
Reserved
Port A Data Direction
Register (DDRA)
See page 252.
Port B Data Direction
Register (DDRB)
See page 252.
Port C Data Direction
Register (DDRC)
See page 252.
Port D Data Direction
Register (DDRD)
See page 252.
Read:
PORTI7 PORTI6 PORTI5 PORTI4 PORTI3 PORTI2 PORTI1 PORTI0
Write:
Reset:11111111
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
Bit 7654321Bit 0
Port E Data Direction
0x00c0_0010
P = Current pin state U = Unaffected
Register (DDRE)
See page 252.
Read:
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Write:
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 2 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 55
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System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0
Read:
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write:
Reset:00000000
Bit 7654321Bit 0
0x00c0_0011
Port F Data Direction
Register (DDRF)
See page 252.
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cale Semiconductor,
Frees
0x00c0_0012
0x00c0_0013
0x00c0_0014
0x00c0_0015
↓
0x00c0_0017
0x00c0_0018
0x00c0_0019
Port G Data Direction
Register (DDRG)
See page 252.
Port H Data Direction
Register (DDRH)
See page 252.
Port I Data Direction
Register (DDRI)
See page 252.
Reserved
Port A Pin Da ta/ Set
Data Register
(PORTAP/SETA)
See page 253.
Port B Pin Da ta/ Set
Data Register
(PORTBP/SETB)
See page 253.
Read:
DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
DDRI7 DDRI6 DDRI5 DDRI4 DDRI3 DDRI2 DDRI1 DDRI0
Write:
Reset:00000000
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0 Read: PORTAP7 PORTAP6 PORTAP5 PORTAP4 PORTAP3 PORTAP2 PORTAP1 PORTAP0 Write: SETA7 SETA6 SETA5 SETA4 SETA3 SETA2 SETA1 SETA0
Reset:PPPPPPPP
Bit 7654321Bit 0 Read: PORTBP7 PORTBP6 PORTBP5 PORTBP4 PORTBP3 PORTBP2 PORTBP1 PORTBP0 Write: SETB7 SETB6 SETB5 SETB4 SETB3 SETB2 SETB1 SETB0
Reset:PPPPPPPP
Bit 7654321Bit 0
Port C Pin Data/Set
0x00c0_001a
P = Current pin state U = Unaffected
Data Register
(PORTCP/SETC)
See page 253.
Read: PORTCP7 PORTCP6 PORT CP5 PORTCP4 PORTCP3 PORTCP2 PORTCP1 PORTCP0 Write: SETC7 SETC6 SETC5 SETC4 SETC3 SETC2 SETC1 SETC0
Reset:PPPPPPPP
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 3 of 34)
Technical Data MMC2107 – Rev. 2.0
56 System Memory Map MOTOROLA
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Address Register Name Bit Number
Read: PORTDP7 PORTDP6 PORT DP5 PORTDP4 PORTDP3 PORTDP2 PORTDP1 PORTDP0 Write: SETD7 SETD6 SETD5 SETD4 SETD3 SETD2 SETD1 SETD0
Reset:PPPPPPPP
0x00c0_001b
Port D Pin Data/Set
Data Register
(PORTDP/SETD)
See page 253.
Bit 7654321Bit 0
Bit 7654321Bit 0
System Memory Map
Register Map
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cale Semiconductor,
Frees
0x00c0_001c
0x00c0_001d
0x00c0_001e
0x00c0_001f
0x00c0_0020
0x00c0_0021
↓
0x00c0_0023
Port E Pin Da ta/ Set
Data Register
(PORTEP/SETE)
See page 253.
Port F Pin Data/Set
Data Register
(PORTFP/SETF)
See page 253.
Port G Pin Data/Set
Data Register
(PORTGP/SETG)
See page 253.
Port H Pin Data/Set
Data Register
(PORTHP/SETH)
See page 253.
Port I Pin Data / Set
Data Register
(PORTIP/SETI)
See page 253.
Reserved
Read: PORTEP7 PORTEP6 PORTEP5 PORTEP4 PORTEP3 PORTEP2 PORTEP1 PORTEP0 Write: SETE7 SETE6 SETE5 SETE4 SETE3 SETE2 SETE1 SETE0
Reset:PPPPPPPP
Bit 7654321Bit 0 Read: PORTFP7 PORTFP6 PORTFP5 PORTFP4 PORTFP3 PORTFP2 PORTFP1 PORTFP0 Write: SETF7 SETF6 SETF5 SETF4 SETF3 SE TF2 SETF1 SETF0
Reset:PPPPPPPP
Bit 7654321Bit 0 Read: PORTGP7 PORTGP6 PORTG P5 P ORTGP4 PORTGP3 PORTGP2 PORTGP1 PORTGP0 Write: SETG7 SETG6 SETG5 SETG4 SETG3 SETG2 SETG1 SETG0
Reset:PPPPPPPP
Bit 7654321Bit 0 Read: PORTHP7 PORTHP6 PORT HP5 PORTHP4 PORTHP3 PORTHP2 PORTHP1 PORTHP0 Write: SETH7 SETH6 SETH5 SETH4 SETH3 SETH2 SETH1 SETH0
Reset:PPPPPPPP
Bit 7654321Bit 0 Read: PORTIP 7 PORTIP6 PORTIP5 PORTIP4 PORTIP3 PORTIP2 PORTIP1 PORTIP0 Write: SETI7 SETI6 SETI5 SETI4 SETI3 SETI2 SETI1 SETI0
Reset:PPPPPPPP
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0
Port A Clear Output
0x00c0_0024
P = Current pin state U = Unaffected
Data Register (CLRA)
See page 254.
Read: 0 0 0 0 0 0 0 0 Write: CLRA7 CLRA6 CLRA5 CLRA4 CLRA3 CLRA2 CLRA1 CLR A0
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 4 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 57
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System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write: CLRB7 CLRB6 CLRB5 CLRB4 CLRB3 CLRB2 CLRB1 CLR B0
Reset:00000000
Bit 7654321Bit 0
0x00c0_0025
Port B Clear Output
Data Register (CLRB)
See page 254.
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cale Semiconductor,
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0x00c0_0026
0x00c0_0027
0x00c0_0028
0x00c0_0029
0x00c0_002a
0x00c0_002b
Port C Clear Output
Data Register (CLRC)
See page 254.
Port D Clear Output
Data Register (CLRD)
See page 254.
Port E Clear Output
Data Register (CLRE)
See page 254.
Port F Clear Output
Data Register (CLRF)
See page 254.
Port G Clear Output
Data Register (CLRG)
See page 254.
Port H Clear Output
Data Register (CLRH)
See page 254.
Read: 0 0 0 0 0 0 0 0 Write: CLRC7 CLRC6 CLRC5 CLRC4 CLRC3 CLRC2 CLRC1 CLRC0
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write: CLRD7 CLRD6 CLRD5 CLRD4 CLRD3 CLRD2 CLRD1 CLRD0
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write: CLRE7 CLRE6 CLRE5 CLRE4 CLRE3 CLRE2 CLRE1 CLR E0
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write: CLRF7 CLRF6 CLRF5 CLRF4 CLRF3 CLRF2 CLRF1 CLRF0
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write: CLRG7 CLRG6 CLRG5 CLRG4 CLRG3 CLRG2 CLRG1 CLRG0
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write: CLRH7 CLRH6 CLRH5 CLRH4 CLRH3 CLRH2 CLRH1 CLRH0
Reset:00000000
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 5 of 34)
Technical Data MMC2107 – Rev. 2.0
58 System Memory Map MOTOROLA
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Address Register Name Bit Number
Read: 0 0 0 0 0 0 0 0 Write: CLRI7 CLRI6 CLRI5 CLRI4 CLRI3 CLRI2 CLRI1 CLRI0
Reset:00000000
0x00c0_002c
Port I Cl e a r O u tp ut
Data Register (CLRI)
See page 254.
Bit 7654321Bit 0
Bit 7654321Bit 0
System Memory Map
Register Map
0x00c0_002d
↓
0x00c0_002f
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cale Semiconductor,
0x00c0_0030
0x00c0_0031
0x00c0_0032
↓
0x00c0_003f
0x00c0_0040
↓
0x00c0_ffff
P = Current pin state U = Unaffected
Assignment Register
Assignment Register
Reserved
Bit 7654321Bit 0
Port C/D Pin
(PCDPAR)
See page 255.
Port E Pin
(PEPAR)
See page 256.
Reserved
Reserved Ports register space (block of 0x00c0_0000 through 0x00c0_oo3f) is mirrored/repeated.
Read:
PCDPA
Write:
Reset: See note 0 0 0 0 0 0 0
Note: Reset state determined during reset configuration. PCDPA = 1 except in single-chip
mode or when an external boot device is selected with a 16-bit port size in master mode.
Bit 7654321Bit 0 Read:
PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
Write:
Reset: Reset state determined during reset configuration as shown in Table 11-2. PEPAR Reset Values.
Bit 7654321Bit 0
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
0000000
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
= Writes have no effect and the access terminates without a transfer error exception.
Frees
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 59
Figure 2-2. Register Summary (Sheet 6 of 34)
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System Memory Map
Address Register Name Bit Number
Chip Configuration Module (CCM )
Bit 15 14 13 12 11 10 9 Bit 8
0x00c1_0000 0x00c1_0001
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0x00c1_0002 Reserved
0x00c1_0003 Reserved
0x00c1_0004 0x00c1_0005
Chip Configuration
Register
(CCR)
See page 94.
Reset Configuration
Register (RCON)
See page 97.
cale Semiconductor,
Read: Write:
Reset: Note 1 0 Note 2 Note 2 0 Note 1 Note 1 Note 1
Read: 0 Write:
Reset: 0 Note 3 Note 2 0 1 0 0 0
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Read: 1
Write:
LOAD
Bit 7654321Bit 0
Notes:
1. Determined during reset configuration
2. 0 for all configurations except emulation mode, 1 for emulation mode
3. 0 for all configurations except emulation and master modes, 1 for emulation and master modes
Bit 7654321Bit 0
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
RPLLSEL1RPLLREF0RLOAD
0
SHEN EMINT
SZEN PSTEN SHINT BME BMD BMT1 BMT0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
0
0 MODE2 MODE1 MODE0
1
BOOTPS0BOOTSEL
0
0
MODE
Frees
P = Current pin state U = Unaffected
Reset:11001000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 7 of 34)
Technical Data MMC2107 – Rev. 2.0
60 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00c1_0006 0x00c1_0007
Chip Identification
Register (CIR)
See page 99.
Read: 0
Write:
Reset:00010111
Bit 15 14 13 12 11 10 9 Bit 8
0
PIN7
Bit 7654321Bit 0
PIN6
0
PIN5
1
PIN4
0
PIN3
System Memory Map
Register Map
1
PIN2
1
PIN1
1
PIN0
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0x00c1_0008 0x00c1_0009
0x00c1_000a 0x00c1_000b
0x00c1_000c
↓
0x00c1_000f
0x00c1_0010
↓
0x00c1_ffff
Read: 0
PRN7
Write:
Reset:
Chip Test Register
See page 100.
Reserved
Unimplemented Access results in the module generating an access termination transfer error.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Read: 0 0 0 0 0 0 0 0
(CTR)
Write:
Reset:00000000
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
Bit 7654321Bit 0
Bit 7654321Bit 0
Bit 7654321Bit 0
0
PRN6
0000000
Writes have no effect, reads return 0s, and the access terminates
0
PRN5
without a transfer error exception.
0
PRN4
PRN3
0
0
PRN2
0
PRN1
0
PRN0
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 8 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 61
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System Memory Map
Address Register Name Bit Number
Chip Selects (CS)
Bit 15 14 13 12 11 10 9 Bit 8
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cale Semiconductor,
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0x00c2_0000 0x00c2_0001
0x00c2_0002 0x00c2_0003
0x00c2_0004 0x00c2_0005
Chip Select Control
Register 0 (CSCR0)
See page 525.
Chip Select Control
Register 1 (CSCR1)
See page 526.
Chip Select Control
Register 2 (CSCR2)
See page 526.
Read:
SO RO PS WWS WE WS2 WS1 WS0
Write:
Reset: 0 0 See note 1 1 1 1 1
Bit 7654321Bit 0 Read: 0 0 0 0 0 0
TAEN CSEN
Write:
Reset:0000001See note
Note: Reset state determined during reset configuration.
Bit 15 14 13 12 11 10 9 Bit 8
Read:
SO RO PS WWS WE WS2 WS1 WS0
Write:
Reset:00111111
Bit 7654321Bit 0 Read: 0 0 0 000
TAEN CSEN
Write:
Reset:0000001See note
Note: Reset state determined during reset configuration
Bit 15 14 13 12 11 10 9 Bit 8
Read:
SO RO PS WWS WE WS2 WS1 WS0
Write:
Reset:00111111
Bit 7654321Bit 0 Read: 0 0 0 0 0 0
TAEN CSEN
Write:
Reset:00000010
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 9 of 34)
Technical Data MMC2107 – Rev. 2.0
62 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00c2_0006 0x00c2_0007
Chip Select Control
Register 3 (CSCR3)
See page 527.
Read: Write:
Reset:00111111
Bit 15 14 13 12 11 10 9 Bit 8
SO RO PS WWS WE WS2 WS1 WS0
Bit 7654321Bit 0
System Memory Map
Register Map
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0x00c2_0008
↓
0x00c2_ffff
Clocks (CLOCK)
0x00c3_0000 0x00c3_0001
0x00c3_0002 Synthesizer Status
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Synthesizer Control
Register (SYNCR)
See page 227.
Register (SYNSR)
See page 230.
Read: 0 0 0 0 0 0
TAEN CSEN
Write:
Reset:00000010
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Read:
LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0
Write:
Reset:00100001
Bit 7654321Bit 0 Read:
LOCEN DISCLK FWKUP RSVD4 STMPD1 STMPD0 RSVD1 RSVD0
Write:
Reset:00000000
Bit 7654321Bit 0 Read: PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS 0 0 Write:
Reset: Note 1 Note 1 Note 1 Note 2 Note 2 0 0 0
Notes:
1. Reset state determined during reset configuration
2. See the LOCKS and LOCK bit descriptions.
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 10 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 63
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System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0
0x00c3_0003 Synthesizer Test Register
(SYNTR)
See page 233.
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
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cale Semiconductor,
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0x00c3_0004 0x00c3_0005 0x00c3_0006 0x00c3_0007
0x00c3_0008
↓
0x00c3_ffff
Reset (RESET)
0x00c4_0000
Synthesizer Test
Register 2 (SYNTR2)
See page 234.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Reset Control Register
(RCR)
See page 133.
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 23 22 21 20 19 18 17 Bit 16 Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8 Read: 0 0 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0
Read:
RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD2 RSVD0
Write:
Reset:00000000
Bit 7654321Bit 0
Bit 7654321Bit 0
Read:
SOFTRST
Write:
Reset:00000000
FRC-
RSTOUT
000000
RSVD9 RSVD8
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 11 of 34)
Technical Data MMC2107 – Rev. 2.0
64 System Memory Map MOTOROLA
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Address Register Name Bit Number
Read: 0 0 SOFT WDR POR EXT LOC LOL Write:
Reset: 0 0 Reset dependent
0x00c4_0001
Reset Status Register
(RSR)
See page 134.
Bit 7654321Bit 0
Bit 7654321Bit 0
System Memory Map
Register Map
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cale Semiconductor,
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Reset Test Register
0x00c4_0002
0x00c4_0003 Reserved
0x00c4_0004
↓
0x00c4_ffff
Interrupt Controller (INTC)
0x00c5_0000 0x00c5_0001
0x00c5_0002 0x00c5_0003
Interrupt Control Register
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Interrupt Status Register
(RTR)
See page 135.
See page 157.
See page 159.
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8 Read:
(ICR)
Write:
Reset:10000000
Read: 0 0 0 Write:
Reset:00000000
Read: 0 0 0 0 0 0 INT FINT
(ISR)
Write:
Reset:00000000
AE FVE ME MFI
Bit 7654321Bit 0
MASK4 MASK3 MASK2 MASK1 MASK0
Bit 15 14 13 12 11 10 9 Bit 8
0000
Bit 7654321Bit 0 Read: 0 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 VEC0 Write:
Reset:00000000
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 12 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 65
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System Memory Map
Address Register Name Bit Number
0x00c5_0004 0x00c5_0005 0x00c5_0006 0x00c5_0007
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Interrupt Force Register
High (IFRH)
See page 160.
Freescale Semiconductor, Inc.
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
Bit 23 22 21 20 19 18 17 Bit 16
Bit 15 14 13 12 11 10 9 Bit 8
cale Semiconductor,
Frees
0x00c5_0008 0x00c5_0009 0x00c5_000a 0x00c5_000b
Interrupt Force Register
Low (IFRL)
See page 161.
Bit 7654321Bit 0 Read:
IF39 IF38 IF37 IF36 IF35 IF34 IF33 IF32 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
Read:
IF31 IF30 IF29 IF28 IF27 IF26 IF25 IF24 Write:
Reset:00000000
Bit 23 22 21 20 19 18 17 Bit 16
Read:
IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 Write:
Reset:00000000
Bit 7654321Bit 0 Read:
IF7IF6IF5IF4IF3IF2IF1IF0
Write:
Reset:00000000
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 13 of 34)
Technical Data MMC2107 – Rev. 2.0
66 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00c5_000c 0x00c5_000d 0x00c5_000e
0x00c5_000f
nc...
I
Interrupt Pending
Register (IPR)
See page 162.
Read: IP31 IP30 IP 29 IP28 IP27 IP26 IP25 IP24 Write:
Reset:00000000
Read: IP23 IP22 IP 21 IP20 IP19 IP18 IP17 IP16 Write:
Reset:00000000
Read: IP15 IP14 IP13 IP12 IP11 IP10 IP9 IP8 Write:
Reset:00000000
System Memory Map
Register Map
Bit 31 30 29 28 27 26 25 Bit 24
Bit 23 22 21 20 19 18 17 Bit 16
Bit 15 14 13 12 11 10 9 Bit 8
cale Semiconductor,
Frees
0x00c5_0010 0x00c5_0011 0x00c5_0012 0x00c5_0013
Normal Interrupt Enable
Register (NIER)
See page 163.
Bit 7654321Bit 0 Read: IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
Read:
NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24
Write:
Reset:00000000
Bit 23 22 21 20 19 18 17 Bit 16
Read:
NIE23 NIE22 NIE21 NIE20 NIE19 NIE18 NIE17 NIE16
Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
NIE15 NIE14 NIE13 NIE12 NIE11 NIE10 NIE9 N IE8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
NIE7 NIE6 NIE5 NIE4 NIE3 NIE2 NIE1 NIE0
Write:
Reset:00000000
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 14 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 67
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System Memory Map
Address Register Name Bit Number
0x00c5_0014 0x00c5_0015 0x00c5_0016 0x00c5_0017
nc...
I
Normal Interrupt Pending
Register (NIPR)
See page 164.
Freescale Semiconductor, Inc.
Read: NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24 Write:
Reset:00000000
Read: NIP23 NIP22 NIP21 NIP20 NIP19 NIP18 NIP17 NIP16 Write:
Reset:00000000
Read: NIP15 NIP14 NIP13 NIP12 NIP11 NIP10 NIP9 NIP8 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
Bit 23 22 21 20 19 18 17 Bit 16
Bit 15 14 13 12 11 10 9 Bit 8
cale Semiconductor,
Frees
0x00c5_0018 0x00c5_0019 0x00c5_001a 0x00c5_001b
Fast Interrupt Enable
Register (FIER)
See page 165.
Bit 7654321Bit 0 Read: NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIP1 N IP 0 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
Read:
FIE31 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24
Write:
Reset:00000000
Bit 23 22 21 20 19 18 17 Bit 16
Read:
FIE23 FIE22 FIE21 FIE20 FIE19 FIE18 FIE17 FIE16
Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9 FIE8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
FIE7 FIE6 FIE5 FIE4 FIE3 FIE2 FIE1 FIE0 Write:
Reset:00000000
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 15 of 34)
Technical Data MMC2107 – Rev. 2.0
68 System Memory Map MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Address Register Name Bit Number
0x00c5_001c 0x00c5_001d 0x00c5_001e
0x00c5_001f
nc...
I
Fast Interrupt Pending
Register (FIPR)
See page 166.
Read: FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24 Write:
Reset:00000000
Read: FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16 Write:
Reset:00000000
Read: FIP15 FIP14 FIP 13 FIP12 FIP11 FIP10 FIP9 FIP8 Write:
Reset:00000000
System Memory Map
Register Map
Bit 31 30 29 28 27 26 25 Bit 24
Bit 23 22 21 20 19 18 17 Bit 16
Bit 15 14 13 12 11 10 9 Bit 8
cale Semiconductor,
Frees
0x00c5_0040
through
0x00c5_0067
0x00c5_0068
↓
0x00c5_007f
0x00c5_0080
↓
0x00c5_ffff
P = Current pin state U = Unaffected
Priority Level Select
Registers
(PLSR39—PLSR0)
See page 167.
Unimplemented Access results in the module generating an access termination transfer error.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Figure 2-2. Register Summary (Sheet 16 of 34)
Bit 7654321Bit 0 Read: FIP7 FIP6 FIP5 FI P4 FIP3 FIP2 FIP1 FIP0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0
PLS4 PLS3 PLS2 PLS1 PLS0
Write:
Reset:00000000
Bit 7654321Bit 0
Bit 7654321Bit 0
= Writes have no effect and the access terminates without a transfer error exception.
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 69
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Freescale Semiconductor, Inc.
System Memory Map
Address Register Name Bit Number
Edge Port (EPORT)
Bit 15 14 13 12 11 10 9 Bit 8
nc...
I
cale Semiconductor,
Frees
0x00c6_0000 0x00c6_0001
0x00c6_0002
0x00c6_0003
0x00c6_0004
0x00c6_0005
0x00c6_0006
EPORT Pin Assignment
Register (EPPAR)
See page 264.
EPORT Data Direction
Register (EPDDR)
See page 266.
EPORT Por t Int erru pt
Enable Register (EPIER)
See page 267.
EPORT Port Data
Register (EPDR)
See page 268.
EPORT Po rt Pin Data
Register (EPPDR)
See page 268.
EPORT Port Flag Regiser
(EPFR)
See page 269.
Read: Write:
Reset:00000000
Read: Write:
Reset:00000000
Read: Write:
Reset:00000000
Read: Write:
Reset:00000000
Read: Write:
Reset:11111111
Read: EPPD7 E PPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPD0 Write:
Reset: P
Read: Write:
Reset:00000000
EPPA7 EPPA6 EPPA5 EPPA4
Bit 7654321Bit 0
EPPA3 EPPA2 EPPA1 EPPA0
Bit 7654321Bit 0
EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0
Bit 7654321Bit 0
EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 EPIE0
Bit 7654321Bit 0
EPD7 EPD6 EPD5 EPD4 E PD3 EPD2 EPD1 EPD0
Bit 7654321Bit 0
PPPPPPP
Bit 7654321Bit 0
EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0
Bit 7654321Bit 0
0x00c6_0007 Reserved
P = Current pin state U = Unaffected
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 17 of 34)
Technical Data MMC2107 – Rev. 2.0
70 System Memory Map MOTOROLA
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Freescale Semiconductor, Inc.
Address Register Name Bit Number
0x00c6_0008
↓
0x00c6_ffff
Watchdog Timer (WDT )
0x00c7_0000 0x00c7_0001
nc...
I
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Watchdog Control
Register (WCR)
See page 275.
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Read: 0 0 0 0 Write:
Reset:00001111
System Memory Map
Register Map
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
WAIT DOZE DBG EN
cale Semiconductor,
Frees
0x00c7_0002 0x00c7_0003
0x00c7_0004 0x00c7_0005
P = Current pin state U = Unaffected
Watchdog Modulus
Register (WMR)
See page 277.
Watchdog Count Register
(WCNTR)
See page 278.
Bit 15 14 13 12 11 10 9 Bit 8
Read:
WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8
Write:
Reset:11111111
Bit 7654321Bit 0 Read:
WM7 WM6 WM5 WM4 WM3 WM2 WM 1 WM0
Write:
Reset:11111111
Bit 15 14 13 12 11 10 9 Bit 8 Read: WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8 Write:
Reset:11111111
Bit 7654321Bit 0 Read: WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0 Write:
Reset:11111111
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 18 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 71
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Freescale Semiconductor, Inc.
System Memory Map
Address Register Name Bit Number
Bit 15 14 13 12 11 10 9 Bit 8
0x00c7_0006 0x00c7_0007
Watchdog Service
Register (WSR)
See page 279.
Read:
WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8
Write:
Reset:00000000
Bit 7654321Bit 0 Read: Write:
Reset:00000000
0x00c7_0008
nc...
I
cale Semiconductor,
↓
0x00c7_ffff
Programmabl e Int e rr upt Tim e r 1 (PI T1 ) and Programming Interrupt Timer 2 (PIT2 )
Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####.
0x00c8_0000 0x00c8_0001 0x00c9_0000 0x00c9_0001
0x00c8_0002 0x00c8_0003 0x00c9_0002 0x00c9_0003
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
PIT Control and Status
Register (PCSR)
See page 285.
PIT Modulus Register
(PMR)
See page 288.
Read: 0 0 0 0 Write:
Reset:00000000
Read: 0 Write:
Reset:00000000
Read: Write:
Reset:11111111
WS7 WS 6 WS5 WS 4 WS3 WS2 WS1 WS 0
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
PRE3 PRE2 PRE1 PRE0
Bit 7654321Bit 0
PDOZE PDBG OVW PIE PIF RLD EN
Bit 15 14 13 12 11 10 9 Bit 8
PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8
Frees
Read: Write:
Reset:11111111
P = Current pin state U = Unaffected
Bit 7654321Bit 0
PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 19 of 34)
Technical Data MMC2107 – Rev. 2.0
72 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00c8_0004 0x00c8_0005 0x00c9_0004 0x00c9_0005
0x00c8_0006
nc...
I
↓
0x00c8_0007
0x00ca_0008
↓
0x00ca_ffff
PIT Count Register
(PCNTR)
See page 289.
Unimplemented Access results in the module generating an access termination transfer error.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Read: PC15 P C14 PC13 PC12 PC11 PC10 P C9 PC8 Write:
Reset:11111111
Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Write:
Reset:11111111
System Memory Map
Register Map
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
Bit 7654321Bit 0
Bit 7654321Bit 0
cale Semiconductor,
Frees
Queued Analog-to-Digital Converter (QADC)
0x00ca_0000 0x00ca_0001
0x00ca_0002 0x00ca_0003
P = Current pin state U = Unaffected
QADC Module
Configuration Register
(QADCMCR)
See page 411.
QADC Test Register
(QADCTEST)
See page 412.
Figure 2-2. Register Summary (Sheet 20 of 34)
Bit 15 14 13 12 11 10 9 Bit 8
Read:
QSTOP QDBG
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
SUPV
Write:
Reset:10000000
Bit 15 14 13 12 11 10 9 Bit 8
Access results in the module generating an access termination transfer error if not in test mode.
Bit 7654321Bit 0
Access results in the module generating an access termination transfer error if not in test mode.
0000000
= Writes have no effect and the access terminates without a transfer error exception.
000000
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 73
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Freescale Semiconductor, Inc.
System Memory Map
Address Register Name Bit Number
nc...
I
cale Semiconductor,
Frees
0x00ca_0004 0x00ca_0005
0x00ca_0006
0x00ca_0007
0x00ca_0008 0x00ca_0009
0x00ca_000a 0x00ca_000b
Reserved Writes have no effect, reads return 0s, and the access terminates
QADC Por t A D ata
Register (PORTQA)
See page 413.
QADC Por t B D ata
Register (PORTQB)
See page 413.
QADC Por t A D ata
Direction Register
(DDRQA)
See page 415.
QADC Control Register0
(QACR0)
See page 416.
without a transfer error exception.
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0 Read: 0 0 0 Write:
Reset: 0 0 0 P P 0 P P
Bit 7654321Bit 0 Read: 0 0 0 0 Write:
Reset:0000PPPP
Bit 15 14 13 12 11 10 9 Bit 8 Read: 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
MUX
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
PSH7 PSH6 PSH5 PSH4 PSA PSL2 PSL1 PSL0
Write:
00
PQA4 PQA3
PQB3 PQB2 PQB1 PQB0
DDQA4 DDQA3
000
TRG
0
PQA1 PQA0
0
DDQA1 DDQA0
PSH8
Reset:00110111
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 21 of 34)
Technical Data MMC2107 – Rev. 2.0
74 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00ca_000c 0x00ca_000d
QADC Control Register1
(QACR1)
See page 419.
Read: Write: SSE1
Reset:00000000
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
CIE1 PIE1
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
0
MQ112 MQ111 MQ110 MQ19 MQ18
System Memory Map
Register Map
nc...
I
cale Semiconductor,
Frees
0x00ca_000e
0x00ca_000f
0x00ca_0010 0x00ca_0011
P = Current pin state U = Unaffected
QADC Control Register2
(QACR2)
See page 422.
QADC Status Register 0
(QASR0)
See page 427.
Figure 2-2. Register Summary (Sheet 22 of 34)
Read:
CIE2 PIE2
Write: SSE2
Reset:00000000
Bit 7654321Bit 0 Read:
RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20
Write:
Reset:01111111
Bit 15 14 13 12 11 10 9 Bit 8
Read:
CF1 PF1 CF2 PF2 TOR1 TOR2
Write:
Reset:00000000
Bit 7654321Bit 0 Read: QS7 QS6 CWP5 CWP4 CWP3 CW P2 CWP1 CWP0 Write:
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
0
MQ212 MQ211 MQ210 MQ29 MQ28
QS9 QS8
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 75
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Freescale Semiconductor, Inc.
System Memory Map
Address Register Name Bit Number
Bit 15 14 13 12 11 10 9 Bit 8
0x00ca_0012 0x00ca_0013
QADC Status Register 1
(QASR1)
See page 436.
Read: 0 0 CWPQ15 CW PQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10 Write:
Reset:00111111
Bit 7654321Bit 0 Read: 0 0 CWPQ25 CW PQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20 Write:
Reset:00111111
Bit 7654321Bit 0
nc...
I
cale Semiconductor,
Frees
0x00ca_0014
↓
0x00ca_01ff
0x00ca_0200 0x00ca_027e
0x00ca_0280
0x00ca_02fe
Reserved
Conversion Command
Word Register
(CCW)
See page 437.
Right-Justified Unsigned
Result Register (RJURR)
See page 441.
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 15 14 13 12 11 10 9 Bit 8
Read: 0 0 0 0 0 0
PBYP
Write:
Reset:000000UU
Bit 7654321Bit 0 Read:
IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0
Write:
Reset:UUUUUUUU
Bit 15 14 13 12 11 10 9 Bit 8
Read: 0 0 0 0 0 0
RESULT
Write:
Reset:000000
Bit 7654321Bit 0 Read:
RESULT
Write:
Reset:
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 23 of 34)
Technical Data MMC2107 – Rev. 2.0
76 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00ca_0300 0x00ca_037e
Left-Justified Signed
Result Register (LJSRR)
See page 442.
Read: Write:
Reset:
Bit 15 14 13 12 11 10 9 Bit 8
SRESULT
Bit 7654321Bit 0
System Memory Map
Register Map
nc...
I
cale Semiconductor,
Frees
0x00ca_0380
0x00ca_03fe
0x00ca_0400
↓
0x00ca_ffff
Serial Peripheral Interface (SPI)
0x00cb_0000
0x00cb_0001
Left-Justified Unsigned
Result Register (LJURR)
See page 442.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
SPI Control Register 1
See page 376.
SPI Control Register 2
See page 378.
(SPICR1)
(SPICR2)
Read:
RESULT
Write:
Reset: 000000
Bit 15 14 13 12 11 10 9 Bit 8 Read: Write:
Reset:
Bit 7654321Bit 0
Read:
RESULT
Write:
Reset: 000000
Bit 7654321Bit 0
Bit 7654321Bit 0
Read:
SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBFE
Write:
Reset:00000100
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 Write:
Reset:00000000
000000
RESULT
000000
SPISDOZ SPC0
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 24 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 77
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Freescale Semiconductor, Inc.
System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0 Read: 0
SPPR6 SPPR5 SPPR4
Write:
Reset:00000000
Bit 7654321Bit 0
0x00cb_0002
SPI Baud Rate Register
(SPIBR)
See page 379.
0
SPR2 SPR1 SPR0
nc...
I
cale Semiconductor,
Frees
SPI Status Register
0x00cb_0003
0x00cb_0004 Reserved
SPI Data Register
0x00cb_0005
SPI Pullup and Reduced
0x00cb_0006
SPI Port Data Register
0x00cb_0007
SPI Port Data Di rection
0x00cb_0008
Register (SPIDDR)
(SPISR)
See page 381.
(SPIDR)
See page 382.
Drive Register
(SPIPURD)
See page 383.
(SPIPORT)
See page 384.
See page 385.
Read: SPIF WCOL 0 MODF 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0 Read: Write:
Reset:00000000
Read: 0 0 Write:
Reset:00000000
Read: Write:
Reset:00000000
Read: Write:
Reset:00000000
Bit 7654321Bit 0
Bit 7654321Bit 0
RSVD5 RDPSP
Bit 7654321Bit 0
RSVD7 RSVD6 RSVD5 RSVD4 PORTSP3 PORTSP2 PORTSP1 PORTSP0
Bit 7654321Bit 0
RSVD7 RSVD6 RSVD5 RSVD4 DDRSP3 DDRSP2 DDRSP1 DDRSP0
Bit 7654321Bit 0
00
RSVD1 PUPSP
0x00cb_0009
↓
0x00cb_000f
P = Current pin state U = Unaffected
Reserved
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 25 of 34)
Technical Data MMC2107 – Rev. 2.0
78 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00cb_0010
↓
0x00cb_ffff
Serial Communications Interface 1 (SCI1) and Serial Communications Interface 2 (SCI2)
Note: Addresses for SCI1 are at 0x00cc_#### and addresses for SCI2 are at 0x00cd_####.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Bit 7654321Bit 0
Bit 7654321Bit 0
System Memory Map
Register Map
0x00cc_0000 0x00cd_0000
nc...
I
0x00cc_0001 0x00cd_0001
0x00cc_0002 0x00cd_0002
0x00cc_0003 0x00cd_0003
Register High (SCIBDH)
cale Semiconductor,
0x00cc_0004 0x00cd_0004
SCI Baud Rate
See page 336.
SCI Baud Rate
Register Low (SCIBDL)
See page 336.
SCI Control Register 1
(SCICR1)
See page 337.
SCI Control Register 2
(SCICR2)
See page 340.
SCI Status Register 1
(SCISR1)
See page 342.
Read: 0 0 0
SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
SBR7 SBR6 SBR5 SBR4 S BR3 SBR2 SBR1 SBR0
Write:
Reset:00000100
Bit 7654321Bit 0 Read:
LOOPS WOMS RSRC M WAKE ILT PE PT
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Bit 7654321Bit 0 Read: TDRE TC RDRF IDLE OR NF FE PF Write:
Reset:11000000
Frees
0x00cc_0005 0x00cd_0005
P = Current pin state U = Unaffected
SCI Status Register 2
(SCISR2)
See page 344.
Read: 0 0 0 0 0 0 0 RAF Write:
Reset:00000000
Bit 7654321Bit 0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 26 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 79
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Freescale Semiconductor, Inc.
System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0
0x00cc_0006 0x00cd_0006
SCI Data Register High
(SCIDRH)
See page 345.
Read: R8
T8
Write:
Reset:00000000
Bit 7654321Bit 0
000000
nc...
I
cale Semiconductor,
Frees
0x00cc_0007 0x00cd_0007
0x00cc_0008 0x00cd_0008
0x00cc_0009 0x00cd_0009
0x00cc_000a 0x00cd_000a
0x00cc_000b
↓
0x00cc_000f
0x00cd_000b
↓
0x00cd_000f
0x00cc_0010
↓
0x00cc_ffff
0x00cd_0010
↓
0x00cd_ffff
SCI Data Register Low
(SCIDRL)
See page 345.
SCI Pullup and Reduced
Drive Register
(SCIPURD)
See page 346.
SCI Port Data Register
(SCIPORT)
See page 347.
SCI Data Direction
Register (SCIDDR)
See page 348.
Reserved
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:00000000
Bit 7654321Bit 0 Read:
SCISDOZ
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 PORTSC1 PORTSC0
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 DDR SC1 DDRSC0
Write:
Reset:00000000
Bit 7654321Bit 0
Bit 7654321Bit 0
0
RSVD5 RDPSCI
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
00
RSVD1 PUPSCI
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 27 of 34)
Technical Data MMC2107 – Rev. 2.0
80 System Memory Map MOTOROLA
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Address Register Name Bit Number
Timer 1 (TIM1) and Timer 2 (TIM2)
Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####.
Bit 7654321Bit 0
System Memory Map
Register Map
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0x00ce_0000
0x00cf_0000
0x00ce_0001
0x00cf_0001
0x00ce_0002
0x00cf_0002
0x00ce_0003
0x00cf_0003
0x00ce_0004
0x00cf_0004
0x00ce_0005
0x00cf_0005
0x00ce_0006
0x00cf_0006
Timer Input Capture/
Output Compare Select
Register (TIMIOS)
See page 300.
Timer Compare Force
Register (TIMCFORC)
See page 301.
Timer Output Compare 3
Mask Register
(TIMOC3M)
See page 302.
Timer Output Compare 3
Data Register (TIMOC3D)
See page 303.
Timer Counter Register
High (TIMCNTH)
See page 304.
Timer Counter Register
Low (TIMCNTL)
See page 304.
Timer System Control
Register 1 (TIMSCR1)
See page 305.
Read: 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write:
Reset:00000000
Bit 7654321Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read:
TIMEN
Write:
Reset:00000000
00
TFFCA
IOS3 IOS2 IOS1 IOS0
FOC3 FOC2 FOC1 FOC0
OC3M3 OC3M2 OC3M1 OC3M0
OC3D3 OC3D2 OC3D1 OC3D0
0000
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 28 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 81
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System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0
0x00ce_0007
0x00cf_0007
Reserved
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
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0x00ce_0008
0x00cf_0008
0x00ce_0009
0x00cf_0009
0x00ce_000a
0x00cf_000a
0x00ce_000b
0x00cf_000b
0x00ce_000c
0x00cf_000c
0x00ce_000d
0x00cf_000d
Timer Toggle on Overflow
Register (TIMTOV)
See page 306.
Timer Control
Register 1 (TIMCTL1)
See page 307.
Reserved
Timer Control
Register 2 (TIMCTL2)
See page 308.
Timer Interrupt Enable
Register (TIMIE)
See page 309.
Timer System Control
Register 2 (TIMSCR2)
See page 310.
Read: 0 0 0 0 Write:
Reset:00000000
Bit 7654321Bit 0 Read: Write:
Reset:00000000
Read: Write:
Reset:00000000
Read: 0 0 0 0 Write:
Reset:00000000
Read: Write:
Reset:00000000
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG10
Bit 7654321Bit 0
Bit 7654321Bit 0
TOI
0
PUPT RDPT TCRE PR2 PR1 PR0
TOV3 TOV2 TOV1 TOV0
C3I C2I C1I C0I
Bit 7654321Bit 0
0x00ce_000e
0x00cf_000e
P = Current pin state U = Unaffected
Timer Flag Register 1
(TIMFLG1)
See page 312.
Read: 0 0 0 0
C3F C2F C1F C0F
Write:
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 29 of 34)
Technical Data MMC2107 – Rev. 2.0
82 System Memory Map MOTOROLA
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Address Register Name Bit Number
Read: Write:
Reset:00000000
0x00ce_000f
0x00cf_000f
Timer Flag Register 2
(TIMFLG2)
See page 313.
Bit 7654321Bit 0
0000000
TOF
Bit 15 14 13 12 11 10 9 Bit 8
System Memory Map
Register Map
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0x00ce_0010
0x00cf_0010
0x00ce_0011
0x00cf_0011
0x00ce_0012
0x00cf_0012
0x00ce_0013
0x00cf_0013
0x00ce_0014
0x00cf_0014
0x00ce_0015
0x00cf_0015
Timer Channel 0 Register
High (TIMC0H)
See page 314.
Timer Channel 0 Register
Low (TIMC0L)
See page 314.
Timer Channel 1 Register
High (TIMC1H)
See page 314.
Timer Channel 1 Register
Low (TIMC1L)
See page 314.
Timer Channel 2 Register
High (TIMC2H)
See page 314.
Timer Channel 2 Register
Low (TIMC2L)
See page 314.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
Bit 7654321Bit 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
Bit 7654321Bit 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
Bit 7654321Bit 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
0x00ce_0016
0x00cf_0016
P = Current pin state U = Unaffected
Timer Channel 3 Register
High (TIMC3H)
See page 314.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 30 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 83
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System Memory Map
Address Register Name Bit Number
Bit 7654321Bit 0 Read:
Bit 7654321Bit 0 Write:
Reset:00000000
Bit 7654321Bit 0
0x00ce_0017
0x00cf_0017
Timer Channel 3 Register
Low (TIMC3L)
See page 314.
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0x00ce_0018
0x00cf_0018
0x00ce_0019
0x00cf_0019
0x00ce_001a
0x00cf_001a
0x00ce_001b
0x00cf_001b
0x00ce_001c
0x00cf_001c
0x00ce_001d
0x00cf_001d
Pulse Accumulator
Control Register
(TIMPACTL)
See page 315.
Pulse Accumulator Flag
Register (TIMPAFLG)
See page 317.
Pulse Accumulator
Counter Register High
(TIMPACNTH)
See page 318.
Pulse Accumulator
Counter Register Low
(TIMPACNTL)
See page 318.
Reserved
Timer Port Data Register
(TIMPORT)
See page 319.
Read: 0
PAE PAMOD PEDGE CLK1 CLK0 PAOVI PAI
Write:
Reset:00000000
Bit 7654321Bit 0 Read: 0 0 0 0 0 0
PAOVF PAIF
Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
Bit 7654321Bit 0 Write:
Reset:00000000
Bit 7654321Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7654321Bit 0 Read: 0 0 0 0
PORTT3 PORTT2 PORTT1 PORTT0
Write:
Reset:00000000
Bit 7654321Bit 0
0x00ce_001e
0x00cf_001e
P = Current pin state U = Unaffected
Timer Port Data D ire c ti on
Register (TIMDDR)
See page 320.
Read: 0 0 0 0
DDRT3 DDRT2 DDRT1 DDRT0
Write:
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 31 of 34)
Technical Data MMC2107 – Rev. 2.0
84 System Memory Map MOTOROLA
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Address Register Name Bit Number
Read: 0 0 0 0 0 0 0 0 Write:
Reset:00000000
0x00ce_001f
0x00cf_001f
0x00ce_0020
↓
0x00ce_ffff
0x00cf_0030
↓
0x00cf_ffff
Timer Test Register
(TIMTST)
See page 321.
Unimplemented Access results in the module generating an access termination transfer error.
Bit 7654321Bit 0
Bit 7654321Bit 0
System Memory Map
Register Map
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Non-Volatile Memory FLASH (CMFR)
0x00d0_0000 0x00d0_0001 0x00d0_0002 0x00d0_0003
CMFR Module
Configuration Register
(CMFRMCR)
See page 188.
Bit 31 30 29 28 27 26 25 Bit 24
Read:
FSTOP FDBG
Write:
Reset: 0 0 0 Note 1 0 0 Note 1 0
Bit 23 22 21 20 19 18 17 Bit 16
Read:
SUPV7 SUPV6 SUPV5 SUPV4 SUPV3 SUPV2 SUPV1 SUPV0
Write:
Reset:11111111
Bit 15 14 13 12 11 10 9 Bit 8
Read:
DATA7 DATA6 DATA 5 DATA4 DATA3 DATA2 DATA1 DATA0
Write:
Reset:00000000
Bit 7654321Bit 0 Read:
PROTECT7 PROTECT6 PROTECT5 PROTECT4 PROTECT3 PROTECT2 PROTECT1 PROTECT0
Write:
Reset:11111111
0
EME SIE LOCKCTL DIS RSVD24
Notes:
1. Reset state is defined by reset override.
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 32 of 34)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 85
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System Memory Map
Address Register Name Bit Number
Bit 31 30 29 28 27 26 25 Bit 24
0x00d0_0004 0x00d0_0005 0x00d0_0006 0x00d0_0007
CMFR Module Test
Register (CMFRMTR)
See page 193.
Read: 0 0 0 0 0 0 0 0 Write:
Reset:
Bit 23 22 21 20 19 18 17 Bit 16 Read: 0 0 0 0 0 0 0 0 Write:
Reset:
Bit 15 14 13 12 11 10 9 Bit 8
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0x00d0_0008 0x00d0_0009 0x00d0_000a 0x00d0_000b
CMFR High-Voltage
Control Register
(CMFRCTL)
See page 196.
Read: 0 0 0 0 Write:
Reset: 0000
Bit 7654321Bit 0 Read: 0 Write:
Reset:00000000
Bit 31 30 29 28 27 26 25 Bit 24
Read:
HVS Write:
Reset:00000000
Bit 23 22 21 20 19 18 17 Bit 16 Read: 0 Write:
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8 Read:
BLOCK7 BLOCK6 BLOCK5 BLOCK4 BLOCK3 BLOCK2 BLOCK1 BLOCK0
Write:
RSVD6 GDB
0
SCLKR2 SCLKR1 SCLKR0
CLKPM6 CLKPM5 CLKPM4 CLKPM3 CLKPM2 CLKPM1 CLKPM0
00000
NVR PAWS2 PAWS1 PAWS0
0
CLKPE1 CLKPE0
Reset:00000000
Bit 7654321Bit 0
P = Current pin state U = Unaffected
Read: 0
RSVD6
Write:
Reset:00100000
= Writes have no effect and the access terminates without a transfer error exception.
100
ERASE SES EHV
Figure 2-2. Register Summary (Sheet 33 of 34)
Technical Data MMC2107 – Rev. 2.0
86 System Memory Map MOTOROLA
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Address Register Name Bit Number
0x00d0_000c
↓
0x00d0_001c
0x00d0_001d
↓
0x7fff_ffff
Unimplemented Access results in the module generating an access termination transfer error.
Unimplemented Access results in a bus monitor timeout generating an access termination transfer error.
Bit 7654321Bit 0
Bit 7654321Bit 0
System Memory Map
Register Map
P = Current pin state U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 34 of 34)
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MMC2107 – Rev. 2.0 Technical Data
MOTOROLA System Memory Map 87
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System Memory Map
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Technical Data MMC2107 – Rev. 2.0
88 System Memory Map MOTOROLA
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Technical Data — MMC2107

3.1 Contents

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Section 3. Chip Configuration Module (CCM)

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1
3.4.3 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.4 Factory Access Slave Test (FAST) Mode . . . . . . . . . . . . . .91
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3.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2
3.6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.7.1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.7.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.7.3 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.7.3.1 Chip Configuration Register. . . . . . . . . . . . . . . . . . . . . . .94
3.7.3.2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . . .97
3.7.3.3 Chip Identification Register . . . . . . . . . . . . . . . . . . . . . . .99
3.7.3.4 Chip Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
3.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
3.8.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.8.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.8.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.8.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .105
3.8.5 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
3.8.6 Internal FLASH Configuration . . . . . . . . . . . . . . . . . . . . . .106
3.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
3.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA Chip Configuration Module (CCM) 89
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Chip Co nfiguration Module (CCM)

3.2 Introduction

The chip configuration mo dule (CCM) controls the chip configuration and mode of operation.

3.3 Features

The CCM performs these operations.
• Selects the chip operating mode: – Master mode
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3.4 Modes of Operation

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– Single-chip mode – Emulation mode – Factory access slave test (FAST) mode for factory test only
• Selects external clock or phase-lock l oop (PLL) mode with internal or external reference
• Selects output pad strength
• Selects boot device
• Selects module configuration
• Selects bus monitor configuration
The CCM configures the chip for four modes of operation:
• Master mode
• Single-chip mode
• Emulation mode
• FAST mode for factory test only
The operating mode is determined at reset and cannot be changed thereafter.
Technical Data MMC2107 – Rev. 2.0
90 Chip Configuration Module (CCM) MOTOROLA
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3.4.1 Master Mode

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3.4.2 Single-Chip Mode

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In master mode, the internal central processor unit (CPU) can access external memories and peripherals. Full master mode functionality requires the bonding out of the optional pins. The external bus consists of a 32-bit data bus and 23 address lines. Available bus control signals include R/W, TC[2:0], TSIZ[1:0], TA, TEA, OE, and EB[3:0]. Up to four chip selects can be programmed to select and control external devices and to provide bus cycle ter mination. When interfacing to 16-bit ports, the ports C and D pins and EB[3:2] general-purpose input/output (I/O).
Chip Configuration Module (CCM)
Modes of Operation
can be configured as
In single-chip m ode, all memory is internal to the ch ip. Extern al bus pins are configured as digital I/O.

3.4.3 Emulation Mode

Emulation mode supports external port replacement logic. All ports are emulated and all primary pin functions are enabled. Since the full external bus must be visible to support the external port replacement logic, the emulation mode pin configuration resembles master mode. Full emulati on mode functionality req uires bonding ou t the optional pins. Emulation mod e chip selects are provide d to give addition al informati on about the bus cycle. Also, the signal SHS is provided as a strobe for
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3.4.4 Factory Access Slave Test (FAST) Mode

capturing addresses and data during show cycles.
Frees
FAST mode is for factory test only.
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA Chip Configuration Module (CCM) 91
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Chip Co nfiguration Module (CCM)

3.5 Block Diagram

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3.6 Signal Descriptions

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RESET
CONFIGURATION
CHIP MODE SELECTION
BOOT DEVICE
SELECTION
CHIP CONFI GU RA TIO N RE G IS TE R
RESET CONFIGURATION REGISTER
CHIP IDENTIFICATION REGISTER
CHIP T EST REGISTER
OUTP U T PAD
STRENGTH SELECTI ON
CLOCK MODE
SELECTION
MODULE
CONFIGURATION
Figure 3-1. Chip Configuration Module Block Diagram
Table 3-1 provides an overview of the CCM signals. For more detailed
information, refer to Section 4. Signal Description.
Table 3-1. Signal Properties
Name Function Reset State
RCON
Reset configuration select Internal weak pullup device
V
DDSYN
D[31:16] Reset configuration overrides —
Technical Data MMC2107 – Rev. 2.0
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3.7 Memory Map and Registers

This subsection provides a description of t he memory m ap and registe rs.

3.7.1 Programming Model

The CCM programming model consists of these registers:
• The chip configuration register (CCR) controls the main chip configuration.
• The reset configurati on register (RCON) in dicates the default chip configuration.
Chip Configuration Module (CCM)
Memory Map and Registers
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• The chip identification register (CIR) contains a unique part number.
• The chip test register (CTR) contains chip-specific test functions.
Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug mode and test operations.
Some write-once bits and test bits ca n be read and writte n while in debug mode or test mode. When debug or test mode is exited, the chip configuration module resumes operation based on the current register values. If a write to a wr ite-once r egister bit occurs w hile in debug or test mode, the register bit rem ains writable on exit from debug or test mode.
Table 3-2 shows the accessibility of write-once bits.
Table 3-2. Write-Once Bits Read/Write Accessibility
Configuration Read/Write Access
All configurations Read-always Debug operation (all modes) Write-always Test operation (all modes) Write-always Master mode Write-once Single-chip mode Write-once FAST mode Write-once Emulation mode Write-once
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA Chip Configuration Module (CCM) 93
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Chip Co nfiguration Module (CCM)

3.7.2 Memory Map Table 3-3. Chip Configuration Module Memory Map

Address Bits 31–16 Bits 15–0
0x00c1_0000 Chip configuration register (CCR) 0x00c1_0004 Reset configuration re gister (RCON) Chip identification register (CIR) S 0x00c1_0008 Chip test register (CTR)
0x00c1_000c
1. S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and resul t in a cycle termination transfer error.
2. Writing to reserved addr esses has no effect; reading returns 0s.
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3. Accessing an unimplemented addres s has no effect and causes a cycle ter m ination t ransfer error.

3.7.3 Register Descriptions

The following subsection describes the CCM registers.
3.7.3.1 Chip Configuration Register
Address: 0x00c1_0000 and 0x00c1_0001
Read: Write:
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Reset: Note 1 0 Note 2 Note 2 0 Note 1 Note 1 Note 1
Read: 0 Write:
Access
Reserved
Reserved
Unimplemented
Bit 15 14 13 12 11 10 9 Bit 8
0
LOAD
Bit 7654321Bit 0
SZEN PSTEN SHINT BME BMD BMT1 BMT0
SHEN EMINT
(3)
(2)
(2)
0 MODE2 MODE1 MODE0
(1)
S
S
—
Reset:0Note 3Note 201000
= Writes have no effect and the access terminates without a transfer error exception.
Notes:
1. Determined during reset configuration
2. 0 for all configurati ons except em ulation mode, 1 for emul ation mode
3. 0 for all configurati ons except em ulation and mast er modes, 1 for emula tion and master modes
Figure 3-2. Chip Configuration Register (CCR)
Technical Data MMC2107 – Rev. 2.0
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LOAD — Pad Driver Load Bit
The LOAD bit selects full or default drive strength for selected pad output drivers. For maximum capacitive load, set the LOAD bit to select full drive strength. For reduced power consumption, clear the LOAD bit to select default drive strength.
1 = Full drive strength 0 = Default drive strength
Table 3-2 shows the read/write accessibility of this write-once bit.
SHEN — Show Cycle Enable Bit
The SHEN bit enables the external memory interface to drive the external bus during internal transfer operations.
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1 = Show cycles enabled 0 = Show cycles disabled
Chip Configuration Module (CCM)
Memory Map and Registers
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In emulation mod e, the SHE N bit is rea d-only. In al l other mo des, it is a read/write bit.
EMINT — Emulate Internal Address Space Bit
The EMINT bit enables chip select 1 (CS1) to decode the internal memory address space.
1 = CS1 decodes internal memory address space. 0 = CS1 decodes external memory address space.
The EMINT bit is read-always but can be written only in emulation mode.
MODE[2:0] — Chip Configuration Mode Field
This read-only field reflects the chip confi guration mode, as shown in
Table 3-4.
Table 3-4. Chip Configuration Mode Selection
MODE[2:0] Chip Configuration Mode
111 Master mode
110 Single-chip mode 10X FAST mode 0XX Emulation mode
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA Chip Configuration Module (CCM) 95
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SZEN — TSIZ[1:0] Enable Bits
This read/write bit ena bles the TSIZ[1:0] f u nction o f the e xterna l pins.
1 = TSIZ[1:0] function enabled 0 = TSIZ[1:0] function disabled
PSTEN — PSTAT[3:0] Signal Enable Bits
This read/write bit enables the PSTAT[3:0] function of the external pins.
1 = PSTAT[3:0] function enabled 0 = PSTAT[3:0] function disabled
SHINT — Show Interrupt Bit
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The SHINT bit allows visibility to any active interrupt request to the processor. If the SHINT bit is set, the RSTOUT fast and normal interrupt signals.
1 = Internal requests reflected on RSTOUT pin 0 = Normal RSTOUT pin function
The SHINT bit is read/write always.
pin is the OR of the
NOTE: The FRCRSTOUT function in the reset controller has a higher priority
than the SHINT function.
BME — Bus Monitor External Enable Bit
The BME bit enables the bus monitor to operate during external bus cycles.
1 = Bus monitor enabled on external bus cycles 0 = Bus monitor disabled on external bus cycles
Table 3-2 shows the read/write accessibility of this write-once bit.
BMD — Bus Monitor Debug Mode Bit
The BMD bit controls how the bus monitor responds during debug mode.
1 = Bus monitor enabled in debug mode 0 = Bus monitor disabled in debug mode
This bit is read/write always.
Technical Data MMC2107 – Rev. 2.0
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Memory Map and Registers
BMT[1:0] — Bus Monitor Timing Field
The BMT field selects the timeout time for the bus monito r as shown in Table 3-5.
Table 3-5. Bus Monitor Timeout Values
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3.7.3.2 Reset Configuration Register
The reset configuration register (RCON) is a read-only register; writing to RCON has no effect. A t reset, RCON determ ines the default operation of certain chip functions. All default functions defined by the RCON values may be overr idden du ri ng re set config uratio n onl y if the exte rnal RCON
Address: 0x00c1_0004 and 0x00c1_0005
cale Semiconductor,
Read: 0 0 000000 Write:
Reset:00000000
BMT[1:0]
00 64 01 32 10 16 11 8
Timeout Period
(in System Clocks)
Table 3-2 shows the read/write accessibility of these write-once bits.
pin is asserted.
Bit 15 14 13 12 11 10 9 Bit 8
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Read:
Write:
Reset:11001000
Bit 7654321Bit 0
1
RPLLSEL1RPLLREF0RLOAD
= Writes have no effect and the access terminates without a transfer error exception.
0
1
BOOTPS0BOOTSEL
0
Figure 3-3. Reset Conf igu ra tio n Regi ste r (RCO N)
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA Chip Configuration Module (CCM) 97
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RPLLSEL — PLL Mode Select Bit
When the PLL is enabled, the read-only RPLLSEL bit reflects the default PLL mode.
1 = Normal PLL mode 0 = 1:1 PLL mode
The default PLL mode can be overridden during reset configuration. If the defau lt mod e is o verr idden, the PLL SEL b it in t he cl ock mod ule SYNSR reflects the PLL mode.
RPLLREF — PLL Reference Bit
When the PLL is enabled in normal PLL mode, the read-only RPLLREF bit reflects the default PLL reference.
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1 = Crystal oscillator is PLL reference. 0 = External clock is PLL reference.
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The default PLL reference can be overridden during reset configuration. If the defau lt mode is overridden, the P LLREF bit in the clock module SYNSR reflects the PLL reference.
RLOAD — Pad Driver Load Bit
The read-only RLOAD bit reflects the pad driver strength configuration.
1 = Full drive strength 0 = Default drive strength
The default function of the pad driver strength can be overridden during reset configuration. If the default mode is overridden, the LOAD bit in CCR reflects the pad driver strength configuration.
BOOTPS — Boot Port Size Bit
If the boot device is configured to b e external, the read -only BOOTPS bit reflects the default selection for the boot port size.
1 = Boot device uses 32-bit port. 0 = Boot device uses 16-bit port.
The default function of the boot port size can be overridden during reset configuration. If the default mode is overridden, the PS bit in CSCR0 reflects the boot device port size configuration.
BOOTSEL — Boot Select Bit
This read-only bit reflects the default selection for the boot device.
1 = Boot from external boot device 0 = Boot from internal boot device
Technical Data MMC2107 – Rev. 2.0
98 Chip Configuration Module (CCM) MOTOROLA
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3.7.3.3 Chip Identification Register
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Memory Map and Registers
The default fu nction of the b oot select can b e overridde n during r eset configuration. If the default mode is overridden, the CSEN bit in CSCR0 bit reflects the boot device configuration.
MODE — Chip Configuration Mode Bit
The read-only MODE bi t reflects the de fault chi p configur ation mo de.
1 = Master mode 0 = Single-chip mode
The default mode can be overridde n during reset con figurat ion. If the default mode is overridden, the MODE0 bit in CCR reflects the mode configuration.
The chip identification register (CIR) is a read-only register; writing to CIR has no effect.
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Address: 0x00c1_0006 and 0x00c1_0007
Bit 15 14 13 12 11 10 9 Bit 8 Read: Write:
Reset:00010111
Read: Write:
Reset:00000000
0
PIN7
Bit 7654321Bit 0
0
PRN7
0
PIN6
0
PRN6
= Writes have no effect and the access terminates without a transfer error exception.
0
PIN5
0
PRN5
1
PIN4
0
PRN4
0
PIN3
0
PRN3
1
PIN2
0
PRN2
1
PIN1
0
PRN1
1
PIN0
0
PRN0
Figure 3-4. Chip Identification Register (CIR)
PIN[7:0] — Part Identification Number Field
This read-only field contains a unique identification number for the part.
PRN[7:0] — Part Revision Number Field
This read-o nly field conta ins the full-laye r mask revision nu mber. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order.
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA Chip Configuration Module (CCM) 99
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Chip Co nfiguration Module (CCM)
3.7.3.4 Chip Test Register
The chip test register (CTR) is reserved for factory testing.
NOTE: To safeguard against unintentional ly acti vating test logic, w rite $000 0 to
the lock-out test features. Setting any bit in CTR may lead to unpredictable results.
Address: 0x00c1_0008 and 0x00c1_0009
Bit 15 14 13 12 11 10 9 Bit 8 Read: 0 0 000000 Write:
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Reset:00000000
Bit 7654321Bit 0

3.8 Functional Descr iption

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Read: 0 0 000000 Write:
Reset:00000000
= Writes have no effect and the access terminates without a transfer error exception.
Figure 3-5. Chip Test Register (CTR)
Six functions are defined within the chip configuration module:
1. Reset configuration
2. Chip mode selection
3. Boot devi ce selection
4. Output pad strength configuration
5. Clock mode selection
6. Module configuration
These functions are described here.
Technical Data MMC2107 – Rev. 2.0
100 Chip Configuration Module (CCM) MOTOROLA
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