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Freescale MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4 Service Manual

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KL25 Sub-Family Reference Manual
Supports: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4,
MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4,
MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4,
MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4
Document Number: KL25P80M48SF0RM
Rev. 3, September 2012
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................33
1.1.1 Purpose.........................................................................................................................................................33
1.1.2 Audience......................................................................................................................................................33
1.2 Conventions..................................................................................................................................................................33
1.2.1 Numbering systems......................................................................................................................................33
1.2.2 Typographic notation...................................................................................................................................34
1.2.3 Special terms................................................................................................................................................34
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................35
2.2 Kinetis L Series.............................................................................................................................................................35
2.3 KL25 Sub-Family Introduction.....................................................................................................................................38
2.4 Module functional categories........................................................................................................................................39
2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................39
2.4.2 System Modules...........................................................................................................................................40
2.4.3 Memories and Memory Interfaces...............................................................................................................41
2.4.4 Clocks...........................................................................................................................................................41
2.4.5 Security and Integrity modules....................................................................................................................42
2.4.6 Analog modules...........................................................................................................................................42
2.4.7 Timer modules.............................................................................................................................................42
2.4.8 Communication interfaces...........................................................................................................................43
2.4.9 Human-machine interfaces..........................................................................................................................44
2.5 Orderable part numbers.................................................................................................................................................44
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................45
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3.2 Module to Module Interconnects..................................................................................................................................45
3.2.1 Module to Module Interconnects.................................................................................................................45
3.2.2 Analog reference options.............................................................................................................................48
3.3 Core Modules................................................................................................................................................................48
3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................48
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................51
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................55
3.4 System Modules............................................................................................................................................................56
3.4.1 SIM Configuration.......................................................................................................................................56
3.4.2 System Mode Controller (SMC) Configuration...........................................................................................57
3.4.3 PMC Configuration......................................................................................................................................57
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................58
3.4.5 MCM Configuration....................................................................................................................................60
3.4.6 Crossbar-Light Switch Configuration..........................................................................................................61
3.4.7 Peripheral Bridge Configuration..................................................................................................................62
3.4.8 DMA request multiplexer configuration......................................................................................................63
3.4.9 DMA Controller Configuration...................................................................................................................66
3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................67
3.5 Clock Modules..............................................................................................................................................................70
3.5.1 MCG Configuration.....................................................................................................................................70
3.5.2 OSC Configuration......................................................................................................................................71
3.6 Memories and Memory Interfaces................................................................................................................................72
3.6.1 Flash Memory Configuration.......................................................................................................................72
3.6.2 Flash Memory Controller Configuration.....................................................................................................74
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3.6.3 SRAM Configuration...................................................................................................................................75
3.7 Analog...........................................................................................................................................................................77
3.7.1 16-bit SAR ADC Configuration..................................................................................................................77
3.7.2 CMP Configuration......................................................................................................................................81
3.7.3 12-bit DAC Configuration...........................................................................................................................83
3.8 Timers...........................................................................................................................................................................84
3.8.1 Timer/PWM Module Configuration............................................................................................................84
3.8.2 PIT Configuration........................................................................................................................................87
3.8.3 Low-power timer configuration...................................................................................................................88
3.8.4 RTC configuration.......................................................................................................................................90
3.9 Communication interfaces............................................................................................................................................91
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................91
3.9.2 SPI configuration.........................................................................................................................................96
3.9.3 I2C Configuration........................................................................................................................................97
3.9.4 UART Configuration...................................................................................................................................98
3.10 Human-machine interfaces (HMI)................................................................................................................................99
3.10.1 GPIO Configuration.....................................................................................................................................99
3.10.2 TSI Configuration........................................................................................................................................101
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................105
4.2 System memory map.....................................................................................................................................................105
4.3 Flash Memory Map.......................................................................................................................................................106
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................106
4.4 SRAM memory map.....................................................................................................................................................107
4.5 Bit Manipulation Engine...............................................................................................................................................107
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................108
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................108
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................109
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4.6.3 Modules Restricted Access in User Mode...................................................................................................112
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................112
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................115
5.2 Programming model......................................................................................................................................................115
5.3 High-Level device clocking diagram............................................................................................................................115
5.4 Clock definitions...........................................................................................................................................................116
5.4.1 Device clock summary.................................................................................................................................117
5.5 Internal clocking requirements.....................................................................................................................................119
5.5.1 Clock divider values after reset....................................................................................................................119
5.5.2 VLPR mode clocking...................................................................................................................................120
5.6 Clock Gating.................................................................................................................................................................121
5.7 Module clocks...............................................................................................................................................................121
5.7.1 PMC 1-kHz LPO clock................................................................................................................................122
5.7.2 COP clocking...............................................................................................................................................122
5.7.3 RTC clocking...............................................................................................................................................123
5.7.4 LPTMR clocking..........................................................................................................................................123
5.7.5 TPM clocking...............................................................................................................................................124
5.7.6 USB FS OTG Controller clocking...............................................................................................................124
5.7.7 UART clocking............................................................................................................................................125
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................127
6.2 Reset..............................................................................................................................................................................127
6.2.1 Power-on reset (POR)..................................................................................................................................128
6.2.2 System reset sources....................................................................................................................................128
6.2.3 MCU Resets.................................................................................................................................................131
6.2.4 Reset Pin .....................................................................................................................................................133
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6.2.5 Debug resets.................................................................................................................................................133
6.3 Boot...............................................................................................................................................................................134
6.3.1 Boot sources.................................................................................................................................................134
6.3.2 FOPT boot options.......................................................................................................................................134
6.3.3 Boot sequence..............................................................................................................................................135
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................137
7.2 Clocking Modes............................................................................................................................................................137
7.2.1 Partial Stop...................................................................................................................................................137
7.2.2 DMA Wakeup..............................................................................................................................................138
7.2.3 Compute Operation......................................................................................................................................139
7.2.4 Peripheral Doze............................................................................................................................................140
7.2.5 Clock Gating................................................................................................................................................141
7.3 Power modes.................................................................................................................................................................141
7.4 Entering and exiting power modes...............................................................................................................................143
7.5 Module Operation in Low Power Modes......................................................................................................................143
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................149
8.2 Flash Security...............................................................................................................................................................149
8.3 Security Interactions with other Modules.....................................................................................................................149
8.3.1 Security Interactions with Debug.................................................................................................................150
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................151
9.2 Debug Port Pin Descriptions.........................................................................................................................................151
9.3 SWD status and control registers..................................................................................................................................152
9.3.1 MDM-AP Control Register..........................................................................................................................153
9.3.2 MDM-AP Status Register............................................................................................................................154
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9.4 Debug Resets................................................................................................................................................................156
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................157
9.6 Debug in Low Power Modes........................................................................................................................................157
9.7 Debug & Security.........................................................................................................................................................157
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................159
10.2 Signal Multiplexing Integration....................................................................................................................................159
10.2.1 Port control and interrupt module features..................................................................................................160
10.2.2 Clock gating.................................................................................................................................................161
10.2.3 Signal multiplexing constraints....................................................................................................................161
10.3 Pinout............................................................................................................................................................................161
10.3.1 KL25 Signal Multiplexing and Pin Assignments........................................................................................161
10.3.2 KL25 Pinouts...............................................................................................................................................164
10.4 Module Signal Description Tables................................................................................................................................168
10.4.1 Core Modules...............................................................................................................................................168
10.4.2 System Modules...........................................................................................................................................169
10.4.3 Clock Modules.............................................................................................................................................169
10.4.4 Memories and Memory Interfaces...............................................................................................................169
10.4.5 Analog..........................................................................................................................................................169
10.4.6 Timer Modules.............................................................................................................................................170
10.4.7 Communication Interfaces...........................................................................................................................171
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................173
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................175
11.2 Overview.......................................................................................................................................................................175
11.2.1 Features........................................................................................................................................................175
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11.2.2 Modes of operation......................................................................................................................................176
11.3 External signal description............................................................................................................................................176
11.4 Detailed signal description............................................................................................................................................177
11.5 Memory map and register definition.............................................................................................................................177
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................183
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................185
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................186
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................186
11.6 Functional description...................................................................................................................................................187
11.6.1 Pin control....................................................................................................................................................187
11.6.2 Global pin control........................................................................................................................................188
11.6.3 External interrupts........................................................................................................................................188
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................191
12.1.1 Features........................................................................................................................................................191
12.2 Memory map and register definition.............................................................................................................................191
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................193
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................194
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................195
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................197
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................199
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................200
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................202
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................204
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................206
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................207
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................209
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................210
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12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................211
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................213
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................213
12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................214
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................214
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................215
12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................216
12.3 Functional description...................................................................................................................................................216
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................217
13.2 Modes of operation.......................................................................................................................................................217
13.3 Memory map and register descriptions.........................................................................................................................219
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................219
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................221
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................222
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................223
13.4 Functional description...................................................................................................................................................224
13.4.1 Power mode transitions................................................................................................................................224
13.4.2 Power mode entry/exit sequencing..............................................................................................................227
13.4.3 Run modes....................................................................................................................................................229
13.4.4 Wait modes..................................................................................................................................................231
13.4.5 Stop modes...................................................................................................................................................232
13.4.6 Debug in low power modes.........................................................................................................................235
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................237
14.2 Features.........................................................................................................................................................................237
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14.3 Low-voltage detect (LVD) system................................................................................................................................237
14.3.1 LVD reset operation.....................................................................................................................................238
14.3.2 LVD interrupt operation...............................................................................................................................238
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................238
14.4 I/O retention..................................................................................................................................................................239
14.5 Memory map and register descriptions.........................................................................................................................239
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................240
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................241
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................242
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................245
15.1.1 Features........................................................................................................................................................245
15.1.2 Modes of operation......................................................................................................................................246
15.1.3 Block diagram..............................................................................................................................................247
15.2 LLWU signal descriptions............................................................................................................................................248
15.3 Memory map/register definition...................................................................................................................................248
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................249
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................250
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................251
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................252
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................253
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................255
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................257
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................258
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................260
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................261
15.4 Functional description...................................................................................................................................................262
15.4.1 LLS mode.....................................................................................................................................................263
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15.4.2 VLLS modes................................................................................................................................................263
15.4.3 Initialization.................................................................................................................................................263
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................265
16.2 Reset memory map and register descriptions...............................................................................................................265
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................265
16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................267
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................268
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................269
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................271
17.1.1 Overview......................................................................................................................................................272
17.1.2 Features........................................................................................................................................................272
17.1.3 Modes of Operation.....................................................................................................................................273
17.2 External Signal Description..........................................................................................................................................273
17.3 Memory Map and Register Definition..........................................................................................................................274
17.4 Functional Description..................................................................................................................................................274
17.4.1 BME Decorated Stores.................................................................................................................................274
17.4.2 BME Decorated Loads.................................................................................................................................280
17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................287
17.5 Application Information................................................................................................................................................288
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................291
18.1.1 Features........................................................................................................................................................291
18.2 Memory map/register descriptions...............................................................................................................................291
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................292
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................293
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18.2.3 Platform Control Register (MCM_PLACR)................................................................................................293
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................296
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................299
19.1.1 Overview......................................................................................................................................................299
19.1.2 Features........................................................................................................................................................302
19.1.3 Modes of Operation.....................................................................................................................................303
19.2 External Signal Description..........................................................................................................................................303
19.3 Memory Map and Register Definition..........................................................................................................................304
19.3.1 MTB_RAM Memory Map...........................................................................................................................304
19.3.2 MTB_DWT Memory Map...........................................................................................................................316
19.3.3 System ROM Memory Map.........................................................................................................................326
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................331
20.1.1 Features........................................................................................................................................................331
20.2 Memory Map / Register Definition...............................................................................................................................331
20.3 Functional Description..................................................................................................................................................332
20.3.1 General operation.........................................................................................................................................332
20.3.2 Arbitration....................................................................................................................................................333
20.4 Initialization/application information...........................................................................................................................334
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................335
21.1.1 Features........................................................................................................................................................335
21.1.2 General operation.........................................................................................................................................335
21.2 Functional description...................................................................................................................................................336
21.2.1 Access support.............................................................................................................................................336
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Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................337
22.1.1 Overview......................................................................................................................................................337
22.1.2 Features........................................................................................................................................................338
22.1.3 Modes of operation......................................................................................................................................338
22.2 External signal description............................................................................................................................................339
22.3 Memory map/register definition...................................................................................................................................339
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................339
22.4 Functional description...................................................................................................................................................340
22.4.1 DMA channels with periodic triggering capability......................................................................................341
22.4.2 DMA channels with no triggering capability...............................................................................................343
22.4.3 Always-enabled DMA sources....................................................................................................................343
22.5 Initialization/application information...........................................................................................................................344
22.5.1 Reset.............................................................................................................................................................344
22.5.2 Enabling and configuring sources................................................................................................................344
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................349
23.1.1 Overview......................................................................................................................................................349
23.1.2 Features........................................................................................................................................................350
23.2 DMA Transfer Overview..............................................................................................................................................351
23.3 Memory Map and Registers..........................................................................................................................................352
23.3.1 Source Address Register (DMA_SARn).....................................................................................................353
23.3.2 Destination Address Register (DMA_DARn).............................................................................................354
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................355
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................357
23.4 Functional Description..................................................................................................................................................361
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................361
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23.4.2 Channel Initialization and Startup................................................................................................................361
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................363
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................364
23.4.5 Termination..................................................................................................................................................365
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................367
24.1.1 Features........................................................................................................................................................367
24.1.2 Modes of Operation.....................................................................................................................................370
24.2 External Signal Description..........................................................................................................................................371
24.3 Memory Map/Register Definition.................................................................................................................................371
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................372
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................373
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................374
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................374
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................376
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................377
24.3.7 MCG Status Register (MCG_S)..................................................................................................................378
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................380
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................381
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................381
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................382
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................382
24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................383
24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................383
24.4 Functional Description..................................................................................................................................................384
24.4.1 MCG mode state diagram............................................................................................................................384
24.4.2 Low Power Bit Usage..................................................................................................................................388
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24.4.3 MCG Internal Reference Clocks..................................................................................................................388
24.4.4 External Reference Clock............................................................................................................................389
24.4.5 MCG Fixed frequency clock .......................................................................................................................389
24.4.6 MCG PLL clock ..........................................................................................................................................390
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................390
24.5 Initialization / Application information........................................................................................................................391
24.5.1 MCG module initialization sequence...........................................................................................................391
24.5.2 Using a 32.768 kHz reference......................................................................................................................393
24.5.3 MCG mode switching..................................................................................................................................394
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................405
25.2 Features and Modes......................................................................................................................................................405
25.3 Block Diagram..............................................................................................................................................................406
25.4 OSC Signal Descriptions..............................................................................................................................................406
25.5 External Crystal / Resonator Connections....................................................................................................................407
25.6 External Clock Connections.........................................................................................................................................408
25.7 Memory Map/Register Definitions...............................................................................................................................409
25.7.1 OSC Memory Map/Register Definition.......................................................................................................409
25.8 Functional Description..................................................................................................................................................410
25.8.1 OSC Module States......................................................................................................................................410
25.8.2 OSC Module Modes.....................................................................................................................................412
25.8.3 Counter.........................................................................................................................................................413
25.8.4 Reference Clock Pin Requirements.............................................................................................................413
25.9 Reset..............................................................................................................................................................................414
25.10 Low Power Modes Operation.......................................................................................................................................414
25.11 Interrupts.......................................................................................................................................................................414
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Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................415
26.1.1 Overview......................................................................................................................................................415
26.1.2 Features........................................................................................................................................................415
26.2 Modes of operation.......................................................................................................................................................416
26.3 External signal description............................................................................................................................................416
26.4 Memory map and register descriptions.........................................................................................................................416
26.5 Functional description...................................................................................................................................................416
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................419
27.1.1 Features........................................................................................................................................................420
27.1.2 Block Diagram.............................................................................................................................................420
27.1.3 Glossary.......................................................................................................................................................421
27.2 External Signal Description..........................................................................................................................................422
27.3 Memory Map and Registers..........................................................................................................................................422
27.3.1 Flash Configuration Field Description.........................................................................................................422
27.3.2 Program Flash IFR Map...............................................................................................................................423
27.3.3 Register Descriptions...................................................................................................................................424
27.4 Functional Description..................................................................................................................................................432
27.4.1 Flash Protection............................................................................................................................................433
27.4.2 Interrupts......................................................................................................................................................433
27.4.3 Flash Operation in Low-Power Modes........................................................................................................434
27.4.4 Functional Modes of Operation...................................................................................................................434
27.4.5 Flash Reads and Ignored Writes..................................................................................................................434
27.4.6 Read While Write (RWW)...........................................................................................................................435
27.4.7 Flash Program and Erase..............................................................................................................................435
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27.4.8 Flash Command Operations.........................................................................................................................435
27.4.9 Margin Read Commands.............................................................................................................................440
27.4.10 Flash Command Description........................................................................................................................441
27.4.11 Security........................................................................................................................................................454
27.4.12 Reset Sequence............................................................................................................................................456
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................457
28.1.1 Features........................................................................................................................................................457
28.1.2 Block diagram..............................................................................................................................................458
28.2 ADC Signal Descriptions..............................................................................................................................................459
28.2.1 Analog Power (VDDA)...............................................................................................................................460
28.2.2 Analog Ground (VSSA)...............................................................................................................................460
28.2.3 Voltage Reference Select.............................................................................................................................460
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................461
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................461
28.3 Register definition.........................................................................................................................................................461
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................462
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................465
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................467
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................468
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................469
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................470
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................472
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................474
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................474
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................475
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................475
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................476
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28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................476
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................477
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................477
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................478
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................478
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................479
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................479
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................480
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................480
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................481
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................481
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................482
28.4 Functional description...................................................................................................................................................482
28.4.1 Clock select and divide control....................................................................................................................483
28.4.2 Voltage reference selection..........................................................................................................................483
28.4.3 Hardware trigger and channel selects..........................................................................................................484
28.4.4 Conversion control.......................................................................................................................................485
28.4.5 Automatic compare function........................................................................................................................493
28.4.6 Calibration function.....................................................................................................................................494
28.4.7 User-defined offset function........................................................................................................................495
28.4.8 Temperature sensor......................................................................................................................................497
28.4.9 MCU wait mode operation...........................................................................................................................497
28.4.10 MCU Normal Stop mode operation.............................................................................................................498
28.4.11 MCU Low-Power Stop mode operation......................................................................................................499
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28.5 Initialization information..............................................................................................................................................499
28.5.1 ADC module initialization example............................................................................................................499
28.6 Application information................................................................................................................................................501
28.6.1 External pins and routing.............................................................................................................................501
28.6.2 Sources of error............................................................................................................................................503
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................509
29.2 CMP features................................................................................................................................................................509
29.3 6-bit DAC key features.................................................................................................................................................510
29.4 ANMUX key features...................................................................................................................................................511
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................511
29.6 CMP block diagram......................................................................................................................................................512
29.7 Memory map/register definitions..................................................................................................................................514
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................514
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................515
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................517
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................517
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................518
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................519
29.8 Functional description...................................................................................................................................................520
29.8.1 CMP functional modes.................................................................................................................................520
29.8.2 Power modes................................................................................................................................................529
29.8.3 Startup and operation...................................................................................................................................530
29.8.4 Low-pass filter.............................................................................................................................................531
29.9 CMP interrupts..............................................................................................................................................................533
29.10 DMA support................................................................................................................................................................533
29.11 CMP Asyncrhonous DMA support...............................................................................................................................534
29.12 Digital-to-analog converter...........................................................................................................................................534
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29.13 DAC functional description..........................................................................................................................................535
29.13.1 Voltage reference source select....................................................................................................................535
29.14 DAC resets....................................................................................................................................................................535
29.15 DAC clocks...................................................................................................................................................................535
29.16 DAC interrupts..............................................................................................................................................................536
29.17 CMP Trigger Mode.......................................................................................................................................................536
Chapter 30
12-bit Digital-to-Analog Converter (DAC)
30.1 Introduction...................................................................................................................................................................537
30.2 Features.........................................................................................................................................................................537
30.3 Block diagram...............................................................................................................................................................537
30.4 Memory map/register definition...................................................................................................................................539
30.4.1 DAC Data Low Register (DACx_DATnL).................................................................................................539
30.4.2 DAC Data High Register (DACx_DATnH)................................................................................................540
30.4.3 DAC Status Register (DACx_SR)...............................................................................................................540
30.4.4 DAC Control Register (DACx_C0).............................................................................................................541
30.4.5 DAC Control Register 1 (DACx_C1)..........................................................................................................542
30.4.6 DAC Control Register 2 (DACx_C2)..........................................................................................................542
30.5 Functional description...................................................................................................................................................543
30.5.1 DAC data buffer operation...........................................................................................................................543
30.5.2 DMA operation............................................................................................................................................544
30.5.3 Resets...........................................................................................................................................................544
30.5.4 Low-Power mode operation.........................................................................................................................544
Chapter 31
Timer/PWM Module (TPM)
31.1 Introduction...................................................................................................................................................................547
31.1.1 TPM Philosophy..........................................................................................................................................547
31.1.2 Features........................................................................................................................................................547
31.1.3 Modes of Operation.....................................................................................................................................548
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31.1.4 Block Diagram.............................................................................................................................................548
31.2 TPM Signal Descriptions..............................................................................................................................................549
31.2.1 TPM_EXTCLK — TPM External Clock....................................................................................................549
31.2.2 TPM_CHn — TPM Channel (n) I/O Pin.....................................................................................................550
31.3 Memory Map and Register Definition..........................................................................................................................550
31.3.1 Status and Control (TPMx_SC)...................................................................................................................552
31.3.2 Counter (TPMx_CNT).................................................................................................................................553
31.3.3 Modulo (TPMx_MOD)................................................................................................................................554
31.3.4 Channel (n) Status and Control (TPMx_CnSC)...........................................................................................555
31.3.5 Channel (n) Value (TPMx_CnV).................................................................................................................557
31.3.6 Capture and Compare Status (TPMx_STATUS).........................................................................................557
31.3.7 Configuration (TPMx_CONF).....................................................................................................................559
31.4 Functional Description..................................................................................................................................................561
31.4.1 Clock Domains.............................................................................................................................................561
31.4.2 Prescaler.......................................................................................................................................................562
31.4.3 Counter.........................................................................................................................................................562
31.4.4 Input Capture Mode.....................................................................................................................................564
31.4.5 Output Compare Mode.................................................................................................................................565
31.4.6 Edge-Aligned PWM (EPWM) Mode...........................................................................................................566
31.4.7 Center-Aligned PWM (CPWM) Mode........................................................................................................568
31.4.8 Registers Updated from Write Buffers........................................................................................................570
31.4.9 DMA............................................................................................................................................................570
31.4.10 Reset Overview............................................................................................................................................571
31.4.11 TPM Interrupts.............................................................................................................................................571
Chapter 32
Periodic Interrupt Timer (PIT)
32.1 Introduction...................................................................................................................................................................573
32.1.1 Block diagram..............................................................................................................................................573
32.1.2 Features........................................................................................................................................................574
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32.2 Signal description..........................................................................................................................................................574
32.3 Memory map/register description.................................................................................................................................575
32.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................575
32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)...............................................................................577
32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)...............................................................................577
32.3.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................578
32.3.5 Current Timer Value Register (PIT_CVALn).............................................................................................578
32.3.6 Timer Control Register (PIT_TCTRLn)......................................................................................................579
32.3.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................580
32.4 Functional description...................................................................................................................................................580
32.4.1 General operation.........................................................................................................................................580
32.4.2 Interrupts......................................................................................................................................................582
32.4.3 Chained timers.............................................................................................................................................582
32.5 Initialization and application information.....................................................................................................................582
32.6 Example configuration for chained timers....................................................................................................................583
32.7 Example configuration for the lifetime timer...............................................................................................................584
Chapter 33
Low-Power Timer (LPTMR)
33.1 Introduction...................................................................................................................................................................587
33.1.1 Features........................................................................................................................................................587
33.1.2 Modes of operation......................................................................................................................................587
33.2 LPTMR signal descriptions..........................................................................................................................................588
33.2.1 Detailed signal descriptions.........................................................................................................................588
33.3 Memory map and register definition.............................................................................................................................588
33.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................589
33.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................590
33.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................592
33.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................592
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33.4 Functional description...................................................................................................................................................593
33.4.1 LPTMR power and reset..............................................................................................................................593
33.4.2 LPTMR clocking..........................................................................................................................................593
33.4.3 LPTMR prescaler/glitch filter......................................................................................................................593
33.4.4 LPTMR compare..........................................................................................................................................595
33.4.5 LPTMR counter...........................................................................................................................................595
33.4.6 LPTMR hardware trigger.............................................................................................................................596
33.4.7 LPTMR interrupt..........................................................................................................................................596
Chapter 34
Real Time Clock (RTC)
34.1 Introduction...................................................................................................................................................................597
34.1.1 Features........................................................................................................................................................597
34.1.2 Modes of operation......................................................................................................................................597
34.1.3 RTC Signal Descriptions.............................................................................................................................597
34.2 Register definition.........................................................................................................................................................598
34.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................599
34.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................599
34.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................600
34.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................600
34.2.5 RTC Control Register (RTC_CR)................................................................................................................601
34.2.6 RTC Status Register (RTC_SR)..................................................................................................................603
34.2.7 RTC Lock Register (RTC_LR)....................................................................................................................604
34.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................605
34.3 Functional description...................................................................................................................................................606
34.3.1 Power, clocking, and reset...........................................................................................................................606
34.3.2 Time counter................................................................................................................................................607
34.3.3 Compensation...............................................................................................................................................607
34.3.4 Time alarm...................................................................................................................................................608
34.3.5 Update mode................................................................................................................................................608
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34.3.6 Register lock................................................................................................................................................609
34.3.7 Interrupt........................................................................................................................................................609
Chapter 35
Universal Serial Bus OTG Controller (USBOTG)
35.1 Introduction...................................................................................................................................................................611
35.1.1 USB..............................................................................................................................................................611
35.1.2 USB On-The-Go..........................................................................................................................................612
35.1.3 USB-FS Features..........................................................................................................................................613
35.2 Functional description...................................................................................................................................................613
35.2.1 Data Structures.............................................................................................................................................613
35.3 Programmers interface..................................................................................................................................................614
35.3.1 Buffer Descriptor Table...............................................................................................................................614
35.3.2 RX vs. TX as a USB target device or USB host..........................................................................................615
35.3.3 Addressing BDT entries...............................................................................................................................616
35.3.4 Buffer Descriptors (BDs).............................................................................................................................616
35.3.5 USB transaction...........................................................................................................................................619
35.4 Memory map/Register definitions................................................................................................................................621
35.4.1 Peripheral ID register (USBx_PERID)........................................................................................................623
35.4.2 Peripheral ID Complement register (USBx_IDCOMP)...............................................................................624
35.4.3 Peripheral Revision register (USBx_REV)..................................................................................................624
35.4.4 Peripheral Additional Info register (USBx_ADDINFO).............................................................................625
35.4.5 OTG Interrupt Status register (USBx_OTGISTAT)....................................................................................625
35.4.6 OTG Interrupt Control Register (USBx_OTGICR).....................................................................................626
35.4.7 OTG Status register (USBx_OTGSTAT)....................................................................................................627
35.4.8 OTG Control register (USBx_OTGCTL)....................................................................................................628
35.4.9 Interrupt Status register (USBx_ISTAT).....................................................................................................629
35.4.10 Interrupt Enable register (USBx_INTEN)...................................................................................................630
35.4.11 Error Interrupt Status register (USBx_ERRSTAT).....................................................................................631
35.4.12 Error Interrupt Enable register (USBx_ERREN).........................................................................................632
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35.4.13 Status register (USBx_STAT)......................................................................................................................633
35.4.14 Control register (USBx_CTL)......................................................................................................................634
35.4.15 Address register (USBx_ADDR).................................................................................................................635
35.4.16 BDT Page Register 1 (USBx_BDTPAGE1)................................................................................................636
35.4.17 Frame Number Register Low (USBx_FRMNUML)...................................................................................636
35.4.18 Frame Number Register High (USBx_FRMNUMH)..................................................................................637
35.4.19 Token register (USBx_TOKEN)..................................................................................................................637
35.4.20 SOF Threshold Register (USBx_SOFTHLD)..............................................................................................638
35.4.21 BDT Page Register 2 (USBx_BDTPAGE2)................................................................................................639
35.4.22 BDT Page Register 3 (USBx_BDTPAGE3)................................................................................................639
35.4.23 Endpoint Control register (USBx_ENDPTn)...............................................................................................639
35.4.24 USB Control register (USBx_USBCTRL)..................................................................................................640
35.4.25 USB OTG Observe register (USBx_OBSERVE)........................................................................................641
35.4.26 USB OTG Control register (USBx_CONTROL)........................................................................................642
35.4.27 USB Transceiver Control Register 0 (USBx_USBTRC0)...........................................................................642
35.4.28 Frame Adjust Register (USBx_USBFRMADJUST)...................................................................................643
35.5 OTG and Host mode operation.....................................................................................................................................644
35.6 Host Mode Operation Examples...................................................................................................................................644
35.7 On-The-Go operation....................................................................................................................................................647
35.7.1 OTG dual role A device operation...............................................................................................................648
35.7.2 OTG dual role B device operation...............................................................................................................649
Chapter 36
USB Voltage Regulator
36.1 Introduction...................................................................................................................................................................651
36.1.1 Overview......................................................................................................................................................651
36.1.2 Features........................................................................................................................................................652
36.1.3 Modes of Operation.....................................................................................................................................653
36.2 USB Voltage Regulator Module Signal Descriptions..................................................................................................653
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Chapter 37
Serial Peripheral Interface (SPI)
37.1 Introduction...................................................................................................................................................................655
37.1.1 Features........................................................................................................................................................655
37.1.2 Modes of Operation.....................................................................................................................................656
37.1.3 Block Diagrams............................................................................................................................................657
37.2 External Signal Description..........................................................................................................................................659
37.2.1 SPSCK — SPI Serial Clock.........................................................................................................................659
37.2.2 MOSI — Master Data Out, Slave Data In...................................................................................................660
37.2.3 MISO — Master Data In, Slave Data Out...................................................................................................660
37.2.4 SS — Slave Select........................................................................................................................................660
37.3 Memory Map and Register Descriptions......................................................................................................................661
37.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................661
37.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................663
37.3.3 SPI baud rate register (SPIx_BR).................................................................................................................664
37.3.4 SPI status register (SPIx_S).........................................................................................................................665
37.3.5 SPI data register (SPIx_D)...........................................................................................................................667
37.3.6 SPI match register (SPIx_M).......................................................................................................................668
37.4 Functional Description..................................................................................................................................................668
37.4.1 General.........................................................................................................................................................668
37.4.2 Master Mode................................................................................................................................................669
37.4.3 Slave Mode..................................................................................................................................................670
37.4.4 SPI Transmission by DMA..........................................................................................................................671
37.4.5 SPI Clock Formats.......................................................................................................................................673
37.4.6 SPI Baud Rate Generation...........................................................................................................................676
37.4.7 Special Features...........................................................................................................................................677
37.4.8 Error Conditions...........................................................................................................................................678
37.4.9 Low Power Mode Options...........................................................................................................................679
37.4.10 Reset.............................................................................................................................................................681
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37.4.11 Interrupts......................................................................................................................................................681
37.5 Initialization/Application Information..........................................................................................................................683
37.5.1 Initialization Sequence.................................................................................................................................683
37.5.2 Pseudo-Code Example.................................................................................................................................684
Chapter 38
Inter-Integrated Circuit (I2C)
38.1 Introduction...................................................................................................................................................................687
38.1.1 Features........................................................................................................................................................687
38.1.2 Modes of operation......................................................................................................................................688
38.1.3 Block diagram..............................................................................................................................................688
38.2 I2C signal descriptions..................................................................................................................................................689
38.3 Memory map and register descriptions.........................................................................................................................689
38.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................690
38.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................691
38.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................692
38.3.4 I2C Status register (I2Cx_S)........................................................................................................................694
38.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................695
38.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................696
38.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................697
38.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................698
38.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................699
38.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................701
38.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................701
38.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................701
38.4 Functional description...................................................................................................................................................702
38.4.1 I2C protocol.................................................................................................................................................702
38.4.2 10-bit address...............................................................................................................................................707
38.4.3 Address matching.........................................................................................................................................709
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38.4.4 System management bus specification........................................................................................................709
38.4.5 Resets...........................................................................................................................................................712
38.4.6 Interrupts......................................................................................................................................................712
38.4.7 Programmable input glitch filter..................................................................................................................714
38.4.8 Address matching wakeup...........................................................................................................................715
38.4.9 DMA support...............................................................................................................................................715
38.5 Initialization/application information...........................................................................................................................716
Chapter 39
Universal Asynchronous Receiver/Transmitter (UART0)
39.1 Introduction...................................................................................................................................................................721
39.1.1 Features........................................................................................................................................................721
39.1.2 Modes of operation......................................................................................................................................722
39.1.3 Block diagram..............................................................................................................................................722
39.2 Register definition.........................................................................................................................................................724
39.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................725
39.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................726
39.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................726
39.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................728
39.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................729
39.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................731
39.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................733
39.2.8 UART Data Register (UARTx_D)...............................................................................................................734
39.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................735
39.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................736
39.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................736
39.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................737
39.3 Functional description...................................................................................................................................................738
39.3.1 Baud rate generation....................................................................................................................................738
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39.3.2 Transmitter functional description...............................................................................................................738
39.3.3 Receiver functional description...................................................................................................................740
39.3.4 Additional UART functions.........................................................................................................................743
39.3.5 Interrupts and status flags............................................................................................................................745
Chapter 40
Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
40.1 Introduction...................................................................................................................................................................747
40.1.1 Features........................................................................................................................................................747
40.1.2 Modes of operation......................................................................................................................................747
40.1.3 Block diagram..............................................................................................................................................748
40.2 Register definition.........................................................................................................................................................750
40.2.1 UART Baud Rate Register: High (UARTx_BDH)......................................................................................751
40.2.2 UART Baud Rate Register: Low (UARTx_BDL).......................................................................................751
40.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................752
40.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................753
40.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................755
40.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................756
40.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................758
40.2.8 UART Data Register (UARTx_D)...............................................................................................................760
40.2.9 UART Control Register 4 (UARTx_C4).....................................................................................................760
40.3 Functional description...................................................................................................................................................761
40.3.1 Baud rate generation....................................................................................................................................761
40.3.2 Transmitter functional description...............................................................................................................762
40.3.3 Receiver functional description...................................................................................................................764
40.3.4 Interrupts and status flags............................................................................................................................767
40.3.5 DMA Operation...........................................................................................................................................768
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