Freescale MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4 Service Manual

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Freescale Semiconductor, Inc.

Document Number: KL25P80M48SF0

Data Sheet: Technical Data Rev 5 08/2014

Kinetis KL25 Sub-Family

48 MHz Cortex-M0+ Based Microcontroller with USB

Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K2x family. General purpose MCU with USB 2.0, featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution.

This product offers:

• Run power consumption down to 47 μA/MHz in very low power run mode

• Static power consumption down to 2 μA with full state retention and 4 μs wakeup

• Ultra-efficient Cortex-M0+ processor running up to 48 MHz with industry leading throughput

• Memory option is up to 128 KB flash and 16 KB RAM

• Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller

Performance

• 48 MHz ARM® Cortex®-M0+ core

Memories and memory interfaces

• Up to 128 KB program flash memory

• Up to 16 KB SRAM

System peripherals

• Nine low-power modes to provide power optimization based on application requirements

• COP Software watchdog

• 4-channel DMA controller, supporting up to 63 request sources

• Low-leakage wakeup unit

• SWD debug interface and Micro Trace Buffer

• Bit Manipulation Engine

Clocks

• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator

• Multi-purpose clock source

• 1 kHz LPO clock

Operating Characteristics

• Voltage range: 1.71 to 3.6 V

Human-machine interface

• Low-power hardware touch sensor interface (TSI)

• Up to 66 general-purpose input/output (GPIO)

Communication interfaces

• USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator

• Two 8-bit SPI modules

• One low power UART module

• Two UART modules

• Two I2C module

Analog Modules

• 16-bit SAR ADC

• 12-bit DAC

• Analog comparator (CMP) containing a 6-bit DAC and programmable reference input

Timers

• Six channel Timer/PWM (TPM)

• Two 2-channel Timer/PWM modules

• Periodic interrupt timers

• 16-bit low-power timer (LPTMR)

• Real time clock

MKL25ZxxVFM4

MKL25ZxxVFT4 MKL25ZxxVLH4 MKL25ZxxVLK4

32-pin QFN (FM)

5 x 5 x 1 Pitch 0.5 mm

64-pin LQFP (LH)

10 x 10 x 1.4 Pitch 0.5

48-pin QFN (FT)

7 x 7 x 1 Pitch 0.5 mm

80-pin LQFP (LK)

12 x 12 x 1.4 Pitch 0.5

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• Flash write voltage range: 1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

Security and integrity modules

• 80-bit unique identification number per chip

Ordering Information

Part Number Memory Maximum number of I\O's

Flash (KB) SRAM (KB)

MKL25Z32VFM4 32 4 23 MKL25Z64VFM4 64 8 23 MKL25Z128VFM4 128 16 23 MKL25Z32VFT4 32 4 36 MKL25Z64VFT4 64 8 36 MKL25Z128VFT4 128 16 36 MKL25Z32VLH4 32 4 50 MKL25Z64VLH4 64 8 50 MKL25Z128VLH4 128 16 50 MKL25Z32VLK4 32 4 66 MKL25Z64VLK4 64 8 66 MKL25Z128VLK4 128 16 66

1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search.

Related Resources

Type Description Resource

Selector Guide The Freescale Solution Advisor is a web-based tool that features

Solution Advisor

interactive application wizards and a dynamic product selector.

Product Brief The Product Brief contains concise overview/summary information to

KL2 Family Product Brief

enable quick evaluation of a device for design suitability.

Reference Manual

The Reference Manual contains a comprehensive description of the structure and function (operation) of a device.

Data Sheet The Data Sheet includes electrical characteristics and signal

KL25P80M48SF0RM

KL25P80M48SF0

connections.

Chip Errata The chip mask set Errata provides additional or corrective

KINETIS_L_xN97F

information for a particular device mask set.

Package drawing

Package dimensions are provided in package drawings. QFN 32-pin: 98ASA00473D

QFN 48-pin: 98ASA00466D LQFP 64-pin: 98ASS23234W LQFP 80-pin: 98ASS23174W

1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.

2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x” replaced by the revision of the device you are using.

Figure 1 shows the functional modules in the chip.

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

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Kinetis KL25 Family

ARM

Cortex™-M0+

Core

Debug

interfaces

Interrupt

controller

MTB

Security

and Integrity

Internal

watchdog

Analog

16-bit ADC

Analog

comparator

6-bit DAC

12-bit DAC

System

Internal

watchdog

DMA

BME

Timers

1x6ch+2x2ch

Low

power timer

Periodic interrupt

timers

RTC

Memories and

Memory Interfaces

Program

flash

RAM

Communication

Interfaces

I C

Low power

UART

SPI

UART

Clocks

Phase-

locked loop

Frequency-

locked loop

Low/high frequency oscillator

Internal

reference

clocks

Human-Machine

Interface (HMI)

GPIOs

with

interrupt

TSI

LEGEND

Figure 1. Functional block diagram

Kinetis KL25 Sub-Family, Rev5 08/2014.

USB LS/FS

Migration difference from KL15 family

Freescale Semiconductor, Inc.

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Table of Contents

1 Ratings....................................................................................5

1.1 Thermal handling ratings.................................................5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................7

2.2.1 Voltage and current operating requirements....... 7

2.2.2 LVD and POR operating requirements................7

2.2.3 Voltage and current operating behaviors.............8

2.2.4 Power mode transition operating behaviors........ 9

2.2.5 Power consumption operating behaviors............ 10

2.2.6 EMC radiated emissions operating behaviors.....16

2.2.7 Designing with radiated emissions in mind..........17

2.2.8 Capacitance attributes.........................................17

2.3 Switching specifications...................................................17

2.3.1 Device clock specifications..................................17

2.3.2 General switching specifications......................... 18

2.4 Thermal specifications.....................................................18

2.4.1 Thermal operating requirements......................... 18

2.4.2 Thermal attributes................................................19

3 Peripheral operating requirements and behaviors.................. 19

3.1 Core modules.................................................................. 19

3.1.1 SWD electricals .................................................. 19

3.2 System modules..............................................................21

3.3 Clock modules.................................................................21

3.3.1 MCG specifications..............................................21

3.3.2 Oscillator electrical specifications........................23

3.4 Memories and memory interfaces................................... 25

3.4.1 Flash electrical specifications..............................25

3.5 Security and integrity modules........................................ 27

3.6 Analog............................................................................. 27

3.6.1 ADC electrical specifications............................... 27

3.6.2 CMP and 6-bit DAC electrical specifications....... 32

3.6.3 12-bit DAC electrical characteristics....................33

3.7 Timers..............................................................................36

3.8 Communication interfaces...............................................36

3.8.1 USB electrical specifications............................... 36

3.8.2 USB VREG electrical specifications.................... 37

3.8.3 SPI switching specifications................................ 37

3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 42

3.8.5 UART...................................................................43

3.9 Human-machine interfaces (HMI)....................................43

3.9.1 TSI electrical specifications................................. 43

4 Dimensions............................................................................. 44

4.1 Obtaining package dimensions....................................... 44

5 Pinout......................................................................................44

5.1 KL25 Signal Multiplexing and Pin Assignments...............44

5.2 KL25 pinouts....................................................................47

6 Ordering parts......................................................................... 51

6.1 Determining valid orderable parts....................................51

7 Part identification.....................................................................51

7.1 Description.......................................................................52

7.2 Format............................................................................. 52

7.3 Fields...............................................................................52

7.4 Example...........................................................................52

8 Terminology and guidelines.................................................... 53

8.1 Definition: Operating requirement....................................53

8.2 Definition: Operating behavior.........................................53

8.3 Definition: Attribute.......................................................... 54

8.4 Definition: Rating............................................................. 54

8.5 Result of exceeding a rating............................................54

8.6 Relationship between ratings and operating

requirements....................................................................55

8.7 Guidelines for ratings and operating requirements..........55

8.8 Definition: Typical value...................................................56

8.9 Typical value conditions.................................................. 57

9 Revision history.......................................................................57

Freescale Semiconductor, Inc.

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Ratings

1 Ratings

1.1 Thermal handling ratings

Table 1. Thermal handling ratings

Symbol Description Min. Max. Unit Notes

STG

SDR

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

Storage temperature –55 150 °C 1 Solder temperature, lead-free — 260 °C 2

1.2 Moisture handling ratings

Table 2. Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD handling ratings

Table 3. ESD handling ratings

Symbol Description Min. Max. Unit Notes

HBM

CDM

LAT

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

Electrostatic discharge voltage, human body model –2000 +2000 V 1 Electrostatic discharge voltage, charged-device

model Latch-up current at ambient temperature of 105 °C –100 +100 mA 3

–500 +500 V 2

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Freescale Semiconductor, Inc.

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80%

20%

50%

Input Signal

Fall Time

High

Low

Rise Time

Midpoint1

The midpoint is VIL + (VIH - VIL) / 2

General

1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings

Symbol Description Min. Max. Unit

DDA

USB_DP

USB_DM

REGIN

Digital supply voltage –0.3 3.8 V Digital supply current — 120 mA IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to

all port pins) Analog supply voltage VDD – 0.3 VDD + 0.3 V USB_DP input voltage –0.3 3.63 V USB_DM input voltage –0.3 3.63 V USB regulator input –0.3 6.0 V

–25 25 mA

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure.

All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics.

Freescale Semiconductor, Inc.

Figure 2. Input signal measurement reference

• CL=30 pF loads

• Slew rate disabled

• Normal drive strength

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2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements

Symbol Description Min. Max. Unit Notes

DDA

VDD – V

VSS – V

Supply voltage 1.71 3.6 V Analog supply voltage 1.71 3.6 V —

DDAVDD

SSAVSS

-to-V

Input high voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

differential voltage –0.1 0.1 V —

DDA

differential voltage –0.1 0.1 V —

SSA

0.7 × V

0.75 × V

— —

V V

General

—

HYS

ICIO

ICcont

Input low voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

Input hysteresis 0.06 × V IO pin negative DC injection current—single pin

• VIN < VSS–0.3V

Contiguous pin DC injection current —regional limit,

— —

0.35 × V

0.3 × V

V V

— V —

–3 — mA

—

— includes sum of negative injection currents of 16 contiguous pins

–25 — mA

V 2

ODPU

RAM

• Negative current injection

Open drain pullup voltage level V VDD voltage required to retain RAM 1.2 — V —

1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If V greater than V

(= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If

IO_MIN

this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (V

IO_MIN

- VIN)/|I

ICIO

2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 6. VDD supply LVD and POR operating requirements

Symbol Description Min. Typ. Max. Unit Notes

POR

Kinetis KL25 Sub-Family, Rev5 08/2014.

Falling VDD POR detect voltage 0.8 1.1 1.5 V —

Table continues on the next page...

Freescale Semiconductor, Inc.

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General

Table 6. VDD supply LVD and POR operating requirements (continued)

Symbol Description Min. Typ. Max. Unit Notes

LVW1H

LVW2H

LVW3H

LVW4H

LVW1L

LVW2L

LVW3L

LVW4L

LVDH

HYSH

LVDL

HYSL

LPO

Falling low-voltage detect threshold — high

2.48 2.56 2.64 V —

range (LVDV = 01) Low-voltage warning thresholds — high range

• Level 1 falling (LVWV = 00)

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

Low-voltage inhibit reset/recover hysteresis —

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

— ±60 — mV —

high range Falling low-voltage detect threshold — low

1.54 1.60 1.66 V —

range (LVDV=00) Low-voltage warning thresholds — low range

• Level 1 falling (LVWV = 00)

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

Low-voltage inhibit reset/recover hysteresis —

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

— ±40 — mV —

low range Bandgap voltage reference 0.97 1.00 1.03 V —

Internal low power oscillator period — factory

900 1000 1100 μs —

trimmed

V V V V

1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors

Symbol Description Min. Max. Unit Notes

OHT

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Output high voltage — Normal drive pad (except RESET)

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA

Output high voltage — High drive pad (except

VDD – 0.5 VDD – 0.5

— —

V V

RESET)

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA

VDD – 0.5 VDD – 0.5

— —

V V

Output high current total for all ports — 100 mA —

Table continues on the next page...

Kinetis KL25 Sub-Family, Rev5 08/2014.

1, 2

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General

Table 7. Voltage and current operating behaviors (continued)

Symbol Description Min. Max. Unit Notes

OLT

I R R

I I

Output low voltage — Normal drive pad

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA

Output low voltage — High drive pad

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA

Output low current total for all ports — 100 mA — Input leakage current (per pin) for full temperature

range Input leakage current (per pin) at 25 °C — 0.025 μA 3 Input leakage current (total all pins) for full

temperature range Hi-Z (off-state) leakage current (per pin) — 1 μA — Internal pullup resistors 20 50 kΩ 4 Internal pulldown resistors 20 50 kΩ 5

— —

— 1 μA 3

— 65 μA 3

0.5

V V

1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output.

3. Measured at VDD = 3.6 V

4. Measured at VDD supply voltage = VDD min and Vinput = V

5. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

All specifications except t table assume this clock configuration:

• CPU and system clocks = 48 MHz

• Bus and flash clock = 24 MHz

• FEI clock mode

POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 8. Power mode transition operating behaviors

and VLLSx→RUN recovery times in the following

POR

Symbol Description Min. Typ. Max. Unit

POR

Kinetis KL25 Sub-Family, Rev5 08/2014.

After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first

Table continues on the next page...

— — 300 μs 1

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Page 10

General

Table 8. Power mode transition operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit

instruction across the operating temperature range of the chip.

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS3 → RUN

• LLS → RUN

• VLPS → RUN

• STOP → RUN

—

115

4.6

4.4

μs

1. Normal boot (FTFA_FOPT[LPBOOT]=11).

2.2.5 Power consumption operating behaviors

The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).

Table 9. Power consumption operating behaviors

Symbol Description Temp. Typ. Max Unit Note

DDA

DD_RUNCO_ CM

DD_RUNCO

DD_RUN

Analog supply current — — See note mA 1 Run mode current in compute operation

- 48 MHz core / 24 MHz flash/ bus disabled, LPTMR running using 4 MHz internal reference clock, CoreMark® benchmark code executing from flash, at 3.0 V

Run mode current in compute operation

- 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash, at 3.0 V

Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at

3.0 V

— 6.4 — mA 2

— 3.9 4.8 mA 3

— 5 5.9 mA 3

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Table continues on the next page...

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Table 9. Power consumption operating behaviors (continued)

Symbol Description Temp. Typ. Max Unit Note

DD_RUN

DD_WAIT

DD_PSTOP2

DD_VLPRCO _CM

DD_VLPRCO

DD_VLPR

DD_VLPW

DD_STOP

DD_VLPS

Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at

at 25 °C 6.2 6.5 mA 3, 4

at 125 °C 6.8 7.1 mA

3.0 V Wait mode current - core disabled / 48

— 3.1 3.8 mA 3 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V

Wait mode current - core disabled / 24

— 2.4 3.2 mA 3 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V

Stop mode current with partial stop 2

— 1.6 2 mA 3 clocking option - core and system disabled / 10.5 MHz bus, at 3.0 V

Very-low-power run mode current in

— 777 — µA 5 compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, LPTMR running with 4 MHz internal reference clock, CoreMark benchmark code executing from flash, at 3.0 V

Very low power run mode current in

— 171 420 µA 6 compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash, at 3.0 V

Very low power run mode current - 4

— 204 449 µA 6 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V

Very low power run mode current - 4

— 262 509 µA 4, 6 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V

Very low power wait mode current -

— 123 366 µA 6 core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V

Stop mode current at 3.0 V at 25 °C 319 343 µA —

at 50 °C 333 365 µA at 70 °C 353 400 µA at 85 °C 380 450 µA

at 105 °C 444 572 µA

Very-low-power stop mode current at

3.0 V

at 25 °C 3.75 8.46 µA — at 50 °C 6.66 13.41 µA at 70 °C 12.9 25.71 µA

General

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General

Table 9. Power consumption operating behaviors (continued)

Symbol Description Temp. Typ. Max Unit Note

at 85 °C 22.7 44.06 µA

at 105 °C 48.4 90.1 µA

DD_LLS

DD_VLLS3

DD_VLLS1

DD_VLLS0

Low leakage stop mode current at 3.0 V

Very low-leakage stop mode 3 current at 3.0 V

Very low-leakage stop mode 1 current at 3.0 V

Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3.0 V

Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3.0 V

at 25 °C 1.68 2.09 µA — at 50 °C 3.05 4.04 µA at 70 °C 5.71 7.75 µA at 85 °C 10 13.54 µA

at 105 °C 22.4 30.41 µA

at 25 °C 1.22 1.6 µA — at 50 °C 2.25 2.31 µA at 70 °C 4.21 5.44 µA at 85 °C 7.37 9.44 µA

at 105 °C 16.6 21.76 µA

at 25 °C 0.58 0.94 µA — at 50 °C 1.26 1.31 µA at 70 °C 2.53 3.33 µA at 85 °C 4.74 6.1 µA

at 105 °C 11.4 15.27 µA

at 25 °C 0.31 0.65 µA — at 50 °C 0.99 1.43 µA at 70 °C 2.25 3.01 µA at 85 °C 4.46 5.83 µA

at 105 °C 11.13 14.99 µA

at 25 °C 0.12 0.47 µA 7 at 50 °C 0.8 1.24 µA at 70 °C 2.06 2.81 µA at 85 °C 4.27 5.62 µA

at 105 °C 10.93 14.78 µA

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current.

2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for time.

3. MCG configured for FEI mode.

4. Incremental current consumption from peripheral activity is not included.

5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced.

6. MCG configured for BLPI mode.

7. No brownout.

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Table 10. Low power mode peripheral adders — typical value

Symbol Description Temperature (°C) Unit

-40 25 50 70 85 105

IREFSTEN4MHz

IREFSTEN32KHz

EREFSTEN4MHz

EREFSTEN32KHz

CMP

RTC

UART

TPM

4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled.

32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled.

External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled.

External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled.

VLLS1 440 490 540 560 570 580 nA VLLS3 440 490 540 560 570 580

LLS 490 490 540 560 570 680

VLPS 510 560 560 560 610 680

STOP 510 560 560 560 610 680

CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption.

RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption.

UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption.

MCGIRCLK

(4 MHz internal

reference

clock)

OSCERCLK

(4 MHz

external

crystal)

TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and

MCGIRCLK

(4 MHz internal

reference

clock)

OSCERCLK

(4 MHz

external

crystal)

I/O switching currents.

56 56 56 56 56 56 µA

52 52 52 52 52 52 µA

206 228 237 245 251 258 µA

22 22 22 22 22 22 µA

432 357 388 475 532 810 nA

66 66 66 66 66 66 µA

214 237 246 254 260 268

86 86 86 86 86 86 µA

235 256 265 274 280 287

General

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General

Table 10. Low power mode peripheral adders — typical value (continued)

Symbol Description Temperature (°C) Unit

-40 25 50 70 85 105

ADC

Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode.

ADC peripheral adder combining the measured values at VDD and V placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions.

DDA

45 45 45 45 45 45 µA

366 366 366 366 366 366 µA

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FBE for run mode, and BLPE for VLPR mode

• USB regulator disabled

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 15

All Off

Temperature = 25, V = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE

All Peripheral CLK Gates

All On

CLK Ratio Flash-Core Core Freq (MHz)

Current Consumption on V

DD(A)

Run Mode Current Vs Core Frequency

8.00E-03

7.00E-03

6.00E-03

5.00E-03

4.00E-03

3.00E-03

2.00E-03

1.00E-03

000.00E+00

'1-1

1 2

12 24

'1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2

General

Figure 3. Run mode supply current vs. core frequency

Kinetis KL25 Sub-Family, Rev5 08/2014.

Freescale Semiconductor, Inc.

Page 16

VLPR Mode Current Vs Core Frequency

Temperature = 25, V = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE

All Peripheral CLK Gates

'1-1'1-2'1-2'1-

All Off

All On

CLK Ratio Flash-Core Core Freq (MHz)

Current Consumption on VDD (A)

400.00E-06

350.00E-06

300.00E-06

250.00E-06

200.00E-06

150.00E-06

100.00E-06

50.00E-06

000.00E+00

1 2

General

Figure 4. VLPR mode current vs. core frequency

2.2.6

EMC radiated emissions operating behaviors

Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP

package

Symbol Description Frequency

band

(MHz)

V V V V

RE_IEC

RE1

RE2

RE3

RE4

Radiated emissions voltage, band 1 0.15–50 13 dBμV 1, 2 Radiated emissions voltage, band 2 50–150 15 dBμV Radiated emissions voltage, band 3 150–500 12 dBμV Radiated emissions voltage, band 4 500–1000 7 dBμV IEC level 0.15–1000 M — 2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and

Freescale Semiconductor, Inc.

Typ. Unit Notes

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General

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range.

2. VDD = 3.3 V, TA = 25 °C, f

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method

= 8 MHz (crystal), f

OSC

= 48 MHz, f

SYS

= 48 MHz

BUS

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 12. Capacitance attributes

Symbol Description Min. Max. Unit

Input capacitance — 7 pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 13. Device clock specifications

Symbol Description Min. Max. Unit

Normal run mode

SYS

BUS

FLASH

SYS_USB

LPTMR

SYS

BUS

FLASH

LPTMR

System and core clock — 48 MHz Bus clock — 24 MHz Flash clock — 24 MHz System and core clock when Full Speed USB in operation 20 — MHz LPTMR clock — 24 MHz

VLPR and VLPS modes System and core clock — 4 MHz Bus clock — 1 MHz Flash clock — 1 MHz LPTMR clock

Table continues on the next page...

— 24 MHz

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Page 18

General

Table 13. Device clock specifications (continued)

Symbol Description Min. Max. Unit

ERCLK

LPTMR_ERCLK

osc_hi_2

TPM

UART0

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR.

2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

External reference clock — 16 MHz LPTMR external reference clock — 16 MHz Oscillator crystal or resonator frequency — high frequency

mode (high range) (MCG_C2[RANGE]=1x) TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz

— 16 MHz

2.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and UART signals.

Table 14. General switching specifications

Description Min. Max. Unit Notes

GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path

External RESET and NMI pin interrupt pulse width — Asynchronous path

GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3

1. The greater synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

3. 75 pF load

1.5 — Bus clock cycles

100 — ns 2

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 15. Thermal operating requirements

Symbol Description Min. Max. Unit

Freescale Semiconductor, Inc.

Die junction temperature –40 125 °C Ambient temperature –40 105 °C

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2.4.2 Thermal attributes

Table 16. Thermal attributes

Peripheral operating requirements and behaviors

Board type Symbol Description 80

Single-layer (1S) R

Four-layer (2s2p) R

Single-layer (1S) R

Four-layer (2s2p) R

— R

— Ψ

Thermal resistance, junction

θJA

to ambient (natural convection)

Thermal resistance, junction

θJA

to ambient (natural convection)

Thermal resistance, junction

θJMA

to ambient (200 ft./min. air speed)

Thermal resistance, junction

θJMA

to ambient (200 ft./min. air speed)

Thermal resistance, junction

θJB

to board Thermal resistance, junction

θJC

to case Thermal characterization

parameter, junction to package top outside center (natural convection)

48 QFN 32 QFN Unit Notes

LQFP64LQFP

70 71 84 92 °C/W 1

53 52 28 33 °C/W

— 59 69 75 °C/W

— 46 22 27 °C/W

34 34 10 12 °C/W 2

15 20 2.0 1.8 °C/W 3

0.6 5 5.0 8 °C/W 4

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air).

2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board.

3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate.

4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

Kinetis KL25 Sub-Family, Rev5 08/2014.

Freescale Semiconductor, Inc.

Page 20

J3 J3

J4 J4

SWD_CLK (input)

Peripheral operating requirements and behaviors

3.1.1 SWD electricals

Table 17. SWD full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 1.71 3.6 V

J1 SWD_CLK frequency of operation

• Serial wire debug

J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width

• Serial wire debug

J4 SWD_CLK rise and fall times — 3 ns

J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns

—

MHz

Freescale Semiconductor, Inc.

Figure 5. Serial wire clock input timing

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 21

J11

J12

J11

J10

Input data valid

Output data valid

SWD_CLK

SWD_DIO

Peripheral operating requirements and behaviors

Figure 6. Serial wire data timing

3.2

System modules

There are no specifications necessary for the device's system modules.

3.3

Clock modules

3.3.1 MCG specifications

Table 18. MCG specifications

Symbol Description Min. Typ. Max. Unit Notes

ints_ft

ints_t

fdco_res_t

Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C

Internal reference frequency (slow clock) — user trimmed

Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using C3[SCTRIM] and C4[SCFTRIM]

Table continues on the next page...

— 32.768 — kHz

31.25 — 39.0625 kHz

— ± 0.3 ± 0.6 %f

dco

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Page 22

Peripheral operating requirements and behaviors

Table 18. MCG specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

Δf

dco_t

Δf

dco_t

intf_ft

Δf

intf_ft

intf_t

loc_low

loc_high

fll_ref

dco

dco_t_DMX3

cyc_fll

fll_acquire

vco

pll_ref

cyc_pll

Total deviation of trimmed average DCO output

— +0.5/-0.7 ± 3 %f

frequency over voltage and temperature Total deviation of trimmed average DCO output

— ± 0.4 ± 1.5 %f frequency over fixed voltage and temperature range of 0–70 °C

Internal reference frequency (fast clock) —

— 4 — MHz factory trimmed at nominal VDD and 25 °C

Frequency deviation of internal reference clock

— +1/-2 ± 3 %f (fast clock) over temperature and voltage — factory trimmed at nominal VDD and 25 °C

Internal reference frequency (fast clock) —

3 — 5 MHz

user trimmed at nominal VDD and 25 °C Loss of external clock minimum frequency —

RANGE = 00 Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(3/5) x

ints_t

(16/5) x

ints_t

— — kHz

FLL FLL reference frequency range 31.25 — 39.0625 kHz DCO output

frequency range

DCO output frequency

FLL period jitter

• f

= 48 MHz

VCO

Low range (DRS = 00)

640 × f

fll_ref

Mid range (DRS = 01)

1280 × f

fll_ref

Low range (DRS = 00)

732 × f

fll_ref

Mid range (DRS = 01)

1464 × f

fll_ref

20 20.97 25 MHz 3, 4

40 41.94 48 MHz

— 23.99 — MHz 5, 6

— 47.97 — MHz

— 180 — ps 7

FLL target frequency acquisition time — — 1 ms 8

PLL VCO operating frequency 48.0 — 100 MHz PLL operating current

pll

• PLL at 96 MHz (f

osc_hi_1

= 8 MHz, f

pll_ref

— 1060 — µA

2 MHz, VDIV multiplier = 48)

PLL operating current

pll

• PLL at 48 MHz (f

osc_hi_1

= 8 MHz, f

pll_ref

— 600 — µA

2 MHz, VDIV multiplier = 24) PLL reference frequency range 2.0 — 4.0 MHz PLL period jitter (RMS)

• f

= 48 MHz

vco

• f

= 100 MHz

vco

— —

120

— —

dco

intf_ft

ps ps

1, 2

Freescale Semiconductor, Inc.

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 18. MCG specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

acc_pll

PLL accumulated jitter over 1µs (RMS)

• f

= 48 MHz

vco

• f

= 100 MHz

vco

— —

1350

600

— —

ps ps

pll_lock

Lock entry frequency tolerance ± 1.49 — ± 2.98 %

lock

Lock exit frequency tolerance ± 4.47 — ± 5.97 %

unl

Lock detector detection time — — 150 × 10

-6

s 11

+ 1075(1/

)

pll_ref

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode).

2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, f

ints_ft

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.

4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δf

) over voltage and temperature must be considered.

dco_t

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification is based on standard deviation (RMS) of period or frequency.

8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

9. Excludes any oscillator currents that are also consuming power while PLL is in operation.

10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise

characteristics of each PCB and results will vary.

11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

Symbol Description Min. Typ. Max. Unit Notes

DDOSC

Kinetis KL25 Sub-Family, Rev5 08/2014.

Supply voltage 1.71 — 3.6 V

Supply current — low-power mode (HGO=0)

• 32 kHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

— — — — —

500 200 300 950

1.2

Table continues on the next page...

— — — — —

nA μA μA μA

Freescale Semiconductor, Inc.

Page 24

Peripheral operating requirements and behaviors

Table 19. Oscillator DC electrical specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

• 24 MHz

• 32 MHz

— 1.5 — mA

DDOSC

C C R

Supply current — high gain mode (HGO=1)

• 32 kHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

EXTAL load capacitance — — — 2, 3

XTAL load capacitance — — — 2, 3

Feedback resistor — low-frequency, low-power

— — — — — —

25 400 500

2.5 3 4

— — — — — —

μA μA

μA mA mA mA

— — — MΩ 2, 4

mode (HGO=0) Feedback resistor — low-frequency, high-gain

— 10 — MΩ

mode (HGO=1) Feedback resistor — high-frequency, low-

— — — MΩ

power mode (HGO=0) Feedback resistor — high-frequency, high-gain

— 1 — MΩ

mode (HGO=1) Series resistor — low-frequency, low-power

— — — kΩ

mode (HGO=0) Series resistor — low-frequency, high-gain

— 200 — kΩ

mode (HGO=1) Series resistor — high-frequency, low-power

— — — kΩ

mode (HGO=0) Series resistor — high-frequency, high-gain

mode (HGO=1)

Peak-to-peak amplitude of oscillation (oscillator

—

kΩ

— 0.6 — V mode) — low-frequency, low-power mode (HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

— V

— V mode) — low-frequency, high-gain mode (HGO=1)

Peak-to-peak amplitude of oscillation (oscillator

— 0.6 — V mode) — high-frequency, low-power mode (HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

— V

— V mode) — high-frequency, high-gain mode (HGO=1)

1. VDD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

Freescale Semiconductor, Inc.

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Peripheral operating requirements and behaviors

3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used.

4. When low power mode is selected, RF is integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.

3.3.2.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

Symbol Description Min. Typ. Max. Unit Notes

osc_lo

osc_hi_1

osc_hi_2

ec_extal

dc_extal

cst

Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)

Oscillator crystal or resonator frequency — high-frequency mode (low range) (MCG_C2[RANGE]=01)

Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x)

Input clock frequency (external clock mode) — — 48 MHz 1, 2 Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode (HGO=0)

Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1)

32 — 40 kHz

3 — 8 MHz

8 — 32 MHz

— 750 — ms 3, 4

— 250 — ms

— 0.6 — ms

— 1 — ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

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Peripheral operating requirements and behaviors

3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.

Table 21. NVM program/erase timing specifications

Symbol Description Min. Typ. Max. Unit Notes

hvpgm4

hversscr

hversall

1. Maximum time based on expectations at cycling end-of-life.

Longword Program high-voltage time — 7.5 18 μs — Sector Erase high-voltage time — 13 113 ms 1 Erase All high-voltage time — 52 452 ms 1

3.4.1.2 Flash timing specifications — commands

Table 22. Flash command timing specifications

Symbol Description Min. Typ. Max. Unit Notes

rd1sec1k

pgmchk

rdrsrc

pgm4

ersscr

rd1all

rdonce

pgmonce

ersall

vfykey

Read 1s Section execution time (flash sector) — — 60 μs 1 Program Check execution time — — 45 μs 1 Read Resource execution time — — 30 μs 1 Program Longword execution time — 65 145 μs — Erase Flash Sector execution time — 14 114 ms 2 Read 1s All Blocks execution time — — 1.8 ms — Read Once execution time — — 25 μs 1 Program Once execution time — 65 — μs — Erase All Blocks execution time — 88 650 ms 2 Verify Backdoor Access Key execution time — — 30 μs 1

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.4.1.3 Flash high voltage current behaviors

Table 23. Flash high voltage current behaviors

Symbol Description Min. Typ. Max. Unit

DD_PGM

DD_ERS

Freescale Semiconductor, Inc.

Average current adder during high voltage flash programming operation

Average current adder during high voltage flash erase operation

— 2.5 6.0 mA

— 1.5 4.0 mA

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Peripheral operating requirements and behaviors

3.4.1.4 Reliability specifications

Table 24. NVM reliability specifications

Symbol Description Min. Typ.

Program Flash

nvmretp10k

nvmretp1k

nvmcycp

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.

Data retention after up to 10 K cycles 5 50 — years — Data retention after up to 1 K cycles 20 100 — years — Cycling endurance 10 K 50 K — cycles 2

Max. Unit Notes

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6

Analog

3.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the differential pins ADCx_DP0, ADCx_DM0.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications.

3.6.1.1

Symbol Description Conditions Min. Typ.

DDA

ΔV

DDA

ΔV

SSA

REFH

REFL

16-bit ADC operating conditions

Table 25. 16-bit ADC operating conditions

Supply voltage Absolute 1.71 — 3.6 V — Supply voltage Delta to VDD (VDD – V Ground voltage Delta to VSS (V ADC reference

voltage high ADC reference

voltage low

) -100 0 +100 mV 2

DDA

– V

) -100 0 +100 mV 2

SSA

1.13 V

SSA

DDA

SSA

Max. Unit Notes

DDA

SSA

V 3

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Page 28

Peripheral operating requirements and behaviors

Table 25. 16-bit ADC operating conditions (continued)

Symbol Description Conditions Min. Typ.

ADIN

Input voltage • 16-bit differential mode

• All other modes

Input capacitance

• 16-bit mode

• 8-bit / 10-bit / 12-bit modes

VREFL

— —

—

Max. Unit Notes

31/32 *

V —

VREFH

VREFH 8 4

pF —

ADIN

Input series

— 2 5 kΩ —

resistance

ADCK

Analog source

resistance (external)

ADC conversion

13-bit / 12-bit modes f

< 4 MHz

ADCK

—

kΩ

≤ 13-bit mode 1.0 — 18.0 MHz 5

clock frequency

ADCK

ADC conversion

16-bit mode 2.0 — 12.0 MHz 5

clock frequency

rate

ADC conversion rate

≤ 13-bit modes No ADC hardware averaging

20.000

—

818.330

Ksps

Continuous conversions enabled, subsequent conversion time

rate

ADC conversion rate

16-bit mode No ADC hardware averaging

37.037

—

461.467

Ksps

Continuous conversions enabled, subsequent conversion time

1. Typical values assume V

= 3.0 V, Temp = 25 °C, f

DDA

= 1.0 MHz, unless otherwise stated. Typical values are for

ADCK

reference only, and are not tested in production.

2. DC potential difference.

3. For packages without dedicated VREFH and VREFL pins, V V

SSA

is internally tied to V

REFH

DDA

, and V

is internally tied to

REFL

4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns.

5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 29

RAS

VAS

CAS

ZAS

VADIN

ZADIN

RADIN

CADIN

Pad leakage due to input protection

INPUT PIN

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

ADC SAR

ENGINE

Peripheral operating requirements and behaviors

Figure 7. ADC input impedance equivalency diagram

3.6.1.2

16-bit ADC electrical characteristics

Table 26. 16-bit ADC characteristics (V

Symbol Description Conditions

DDA_ADC

ADACK

TUE Total unadjusted

Supply current 0.215 — 1.7 mA 3 ADC

asynchronous clock source

Sample Time See Reference Manual chapter for sample times

error

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

• 12-bit modes

• <12-bit modes

= V

REFH

Min. Typ.

1.2

2.4

3.0

4.4

— —

DDA

2.4

4.0

5.2

6.2

±4

±1.4

, V

REFL

= V

SSA

)

Max. Unit Notes

3.9

6.1

7.3

9.5

±6.8

MHz MHz MHz MHz

LSB

t 1/f

±2.1

ADACK

DNL Differential non-

• 12-bit modes

linearity

• <12-bit modes

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—

Table continues on the next page...

±0.7

±0.2

–1.1 to

LSB

+1.9

–0.3 to 0.5

Freescale Semiconductor, Inc.

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Peripheral operating requirements and behaviors

Table 26. 16-bit ADC characteristics (V

Symbol Description Conditions

INL Integral non-

• 12-bit modes

linearity

• <12-bit modes

Full-scale error • 12-bit modes

• <12-bit modes

ENOB Effective number

Quantization error

of bits

• 16-bit modes

• ≤13-bit modes

16-bit differential mode

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

• Avg = 4

SINAD

Signal-to-noise plus distortion

THD Total harmonic

distortion

See ENOB

16-bit differential mode

• Avg = 32

16-bit single-ended mode

• Avg = 32

= V

REFH

Min. Typ.

—

— — — —

12.8

11.9

12.2

11.4

—

DDA

, V

±1.0

REFL

= V

) (continued)

SSA

Max. Unit Notes

–2.7 to

LSB

+1.9

±0.5

–0.7 to

+0.5

–4

–1.4

–1 to 0

—

14.5

13.8

13.9

13.1

–5.4 –1.8

—

±0.5

— —

LSB

bits bits

6.02 × ENOB + 1.76 dB

-94

-85

—

ADIN

DDA

SFDR Spurious free

dynamic range

Input leakage error

Temp sensor slope

TEMP25

Temp sensor voltage

Freescale Semiconductor, Inc.

16-bit differential mode

—

• Avg = 32 78

—

16-bit single-ended mode

• Avg = 32

IIn × R

mV IIn =

leakage

current

(refer to

the MCU's

voltage

and

current

operating

ratings)

Across the full temperature

1.55 1.62 1.69 mV/°C 8

range of the device 25 °C 706 716 726 mV 8

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 31

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

ENOB

ADC Clock Frequency (MHz)

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

12.30

12.00 1 2 3 4 5 6 7 8 9 10 1211

Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

ENOB

ADC Clock Frequency (MHz)

14.00

13.75

13.25

13.00

12.75

12.50

12.00

11.75

11.50

11.25

11.00 1 2 3 4 5 6 7 8 9 10 1211

Averaging of 4 samples Averaging of 32 samples

13.50

12.25

Peripheral operating requirements and behaviors

1. All accuracy numbers assume the ADC is calibrated with V

2. Typical values assume V

= 3.0 V, Temp = 25 °C, f

DDA

ADCK

= V

REFH

DDA

= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed.

4. 1 LSB = (V

REFH

- V

REFL

)/2

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Kinetis KL25 Sub-Family, Rev5 08/2014.

Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

Freescale Semiconductor, Inc.

Page 32

Peripheral operating requirements and behaviors

3.6.2 CMP and 6-bit DAC electrical specifications

Table 27. Comparator and 6-bit DAC electrical specifications

Symbol Description Min. Typ. Max. Unit

DDHS

DDLS

AIN

AIO

Supply voltage 1.71 — 3.6 V Supply current, high-speed mode (EN = 1, PMODE =

— — 200 μA

1) Supply current, low-speed mode (EN = 1, PMODE =

— — 20 μA

0) Analog input voltage V

— V Analog input offset voltage — — 20 mV Analog comparator hysteresis

• CR0[HYSTCTR] = 00

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

— — — —

5 10 20 30

— — — —

mV mV mV mV

CMPOh

CMPOl

DHS

Output high VDD – 0.5 — — V Output low — — 0.5 V Propagation delay, high-speed mode (EN = 1,

20 50 200 ns

PMODE = 1)

DLS

Propagation delay, low-speed mode (EN = 1, PMODE

80 250 600 ns

= 0)

— — 40 μs

DAC6b

Analog comparator initialization delay 6-bit DAC current adder (enabled) — 7 — μA

INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB

DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB

1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.

3. 1 LSB = V

reference

/64

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 33

CMP Hysteresis vs Vinn

HYSTCTR Setting

000.00E+00

0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1

Vinn (V)

30.00E-03

20.00E-03

10.00E-03

40.00E-03

50.00E-03

60.00E-03

70.00E-03

80.00E-03

90.00E-03

CMP Hysteresis (V)

180.00E-03

CMP Hysteresis vs Vinn

0 1 2

HYSTCTR Setting

60.00E-03

0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1

CMP Hysteresis (V)

Vinn (V)

-20.00E-03

000.00E+00

20.00E-03

40.00E-03

80.00E-03

100.00E-03

120.00E-03

140.00E-03

160.00E-03

Peripheral operating requirements and behaviors

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.6.3

Kinetis KL25 Sub-Family, Rev5 08/2014.

12-bit DAC electrical characteristics

Freescale Semiconductor, Inc.

Page 34

Peripheral operating requirements and behaviors

3.6.3.1 12-bit DAC operating requirements

Table 28. 12-bit DAC operating requirements

Symbol Desciption Min. Max. Unit Notes

DDA

DACR

Supply voltage 1.71 3.6 V Reference voltage 1.13 3.6 V 1 Output load capacitance — 100 pF 2

Output load current — 1 mA

1. The DAC reference can be selected to be V

DDA

or V

REFH

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

3.6.3.2 12-bit DAC operating behaviors

Table 29. 12-bit DAC operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

DDA_DACL

DDA_DACH

DACLP

DACHP

CCDACLP

dacoutl

dacouth

INL Integral non-linearity error — high speed

DNL Differential non-linearity error — V

OFFSET

PSRR Power supply rejection ratio, V

T T

Rop Output resistance (load = 3 kΩ) — — 250 Ω

SR Slew rate -80h→ F7Fh→ 80h

Supply current — low-power mode — — 250 μA

Supply current — high-speed mode — — 900 μA

Full-scale settling time (0x080 to 0xF7F) —

— 100 200 μs 1

low-power mode Full-scale settling time (0x080 to 0xF7F) —

— 15 30 μs 1

high-power mode Code-to-code settling time (0xBF8 to

— 0.7 1 μs 1 0xC08) — low-power mode and high-speed mode

DAC output voltage range low — high-

— — 100 mV speed mode, no load, DAC set to 0x000

DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF

DACR

−100

— V

DACR

— — ±8 LSB 2 mode

DACR

> 2

— — ±1 LSB 3 V

DACR

— — ±1 LSB 4 VREF_OUT

Offset error — ±0.4 ±0.8 %FSR 5 Gain error — ±0.1 ±0.6 %FSR 5

≥ 2.4 V 60 — 90 dB

DDA

Temperature coefficient offset voltage — 3.7 — μV/C 6

Temperature coefficient gain error — 0.000421 — %FSR/C

1.2

1.7

—

V/μs

Table continues on the next page...

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 35

Digital Code

DAC12 INL (LSB)

500 1000 1500 2000 2500 3000 3500 4000

-2

-4

-6

-8

Peripheral operating requirements and behaviors

Table 29. 12-bit DAC operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

• High power (SPHP)

• Low power (SPLP)

0.05 0.12 —

BW 3dB bandwidth

• High power (SPHP)

• Low power (SPLP)

550

1. Settling within ±1 LSB

2. The INL is measured for 0 + 100 mV to V

3. The DNL is measured for 0 + 100 mV to V

4. The DNL is measured for 0 + 100 mV to V

5. Calculated by a best fit curve from VSS + 100 mV to V

6. V

= 3.0 V, reference select set for V

DDA

−100 mV

DACR

−100 mV

DACR

−100 mV with V

DACR

(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC

DDA

DACR

− 100 mV

set to 0x800, temperature range is across the full range of the device

DDA

— —

> 2.4 V

— —

kHz

Figure 12. Typical INL error vs. digital code

Kinetis KL25 Sub-Family, Rev5 08/2014.

Freescale Semiconductor, Inc.

Page 36

Temperature °C

DAC12 Mid Level Code Voltage

105 125

1.499

-40

1.4985

1.498

1.4975

1.497

1.4965

1.496

Peripheral operating requirements and behaviors

3.7

Timers

Figure 13. Offset at half scale vs. temperature

See General switching specifications.

3.8

Communication interfaces

3.8.1 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org.

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 37

Peripheral operating requirements and behaviors

NOTE

The MCGPLLCLK meets the USB jitter specifications for certification with the use of an external clock/crystal for both Device and Host modes.

The MCGFLLCLK does not meet the USB jitter specifications for certification.

3.8.2 USB VREG electrical specifications

Table 30. USB VREG electrical specifications

650

—

Max. Unit Notes

—

Symbol Description Min. Typ.

VREGIN Input supply voltage 2.7 — 5.5 V

DDon

DDstby

DDoff

Quiescent current — Run mode, load current equal zero, input supply (VREGIN) > 3.6 V

Quiescent current — Standby mode, load current equal zero

Quiescent current — Shutdown mode

• VREGIN = 5.0 V and temperature=25 °C

• Across operating voltage and temperature

— 125 186 μA

— 1.1 10 μA

— —

nA μA

LOADrun

LOADstby

Reg33out

OUT

ESR External output capacitor equivalent series

LIM

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I

Maximum load current — Run mode — — 120 mA Maximum load current — Standby mode — — 1 mA Regulator output voltage — Input supply

(VREGIN) > 3.6 V

• Run mode

• Standby mode

Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode

External output capacitor 1.76 2.2 8.16 μF

resistance Short circuit current — 290 — mA

2.1

2.1 — 3.6 V 2

1 — 100 mΩ

3.3

2.8

3.6

V V

Load

Kinetis KL25 Sub-Family, Rev5 08/2014.

Freescale Semiconductor, Inc.

Page 38

Peripheral operating requirements and behaviors

3.8.3 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.

Table 31. SPI master mode timing on slew rate disabled pads

Num. Symbol Description Min. Max. Unit Note

1 f 2 t

SPSCK

3 t 4 t 5 t

WSPSCK

6 t 7 t 8 t 9 t

10 t

11 t

Lead

Lag

Frequency of operation f

SPSCK period 2 x t

periph

/2048 f

periph

/2 Hz 1

periph

2048 x

periph

Enable lead time 1/2 — t Enable lag time 1/2 — t Clock (SPSCK) high or low time t

– 30 1024 x

periph

Data setup time (inputs) 16 — ns — Data hold time (inputs) 0 — ns —

Data valid (after SPSCK edge) — 10 ns —

Data hold time (outputs) 0 — ns — Rise time input — t

Fall time input

– 25 ns —

periph

Rise time output — 25 ns — Fall time output

ns 2

SPSCK

ns —

— —

1. For SPI0, f

2. t

periph

= 1/f

is the bus clock (f

periph

). For SPI1 f

BUS

is the system clock (f

periph

SYS

Table 32. SPI master mode timing on slew rate enabled pads

Num. Symbol Description Min. Max. Unit Note

1 f 2 t

3 t 4 t 5 t

6 t

SPSCK

Lead

Lag

WSPSCK

Freescale Semiconductor, Inc.

Frequency of operation f

SPSCK period 2 x t

periph

/2048 f

periph

/2 Hz 1

periph

2048 x

periph

Enable lead time 1/2 — t Enable lag time 1/2 — t Clock (SPSCK) high or low time t

– 30 1024 x

periph

Data setup time (inputs) 96 — ns —

Table continues on the next page...

Kinetis KL25 Sub-Family, Rev5 08/2014.

ns 2

SPSCK

ns —

— —

Page 39

(OUTPUT)

6 7

MSB IN2

LSB IN

MSB OUT2

LSB OUT

(CPOL=0)

SPSCK

(CPOL=1)

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

BIT 6 . . . 1

Peripheral operating requirements and behaviors

Table 32. SPI master mode timing on slew rate enabled pads (continued)

Num. Symbol Description Min. Max. Unit Note

7 t 8 t 9 t

10 t

11 t

Data hold time (inputs) 0 — ns —

Data valid (after SPSCK edge) — 52 ns —

Data hold time (outputs) 0 — ns — Rise time input — t

Fall time input

– 25 ns —

periph

Rise time output — 36 ns — Fall time output

1. For SPI0, f

2. t

periph

= 1/f

is the bus clock (f

periph

). For SPI1 f

BUS

is the system clock (f

periph

SYS

Figure 14. SPI master mode timing (CPHA = 0)

Kinetis KL25 Sub-Family, Rev5 08/2014.

Freescale Semiconductor, Inc.

Page 40

6 7

MSB IN2

BIT 6 . . . 1

MASTER MSB OUT2

MASTER LSB OUT

10 11

PORT DATA

10 11 4

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

(OUTPUT)

(CPOL=0)

SPSCK

(CPOL=1)

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

LSB IN

BIT 6 . . . 1

Peripheral operating requirements and behaviors

Figure 15. SPI master mode timing (CPHA = 1)

Table 33. SPI slave mode timing on slew rate disabled pads

Num. Symbol Description Min. Max. Unit Note

1 f 2 t 3 t 4 t 5 t 6 t

SPSCK

Lead

Lag

WSPSCK

7 t 8 t 9 t

dis

10 t 11 t

12 t

13 t

1. For SPI0, f

2. t

periph

= 1/f

periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

Frequency of operation 0 f

SPSCK period 4 x t

periph

/4 Hz 1

periph

— ns 2 Enable lead time 1 — t Enable lag time 1 — t Clock (SPSCK) high or low time t

– 30 — ns —

periph

Data setup time (inputs) 2 — ns — Data hold time (inputs) 7 — ns —

Slave access time — t

Slave MISO disable time — t Data valid (after SPSCK edge) — 22 ns —

periph

Data hold time (outputs) 0 — ns — Rise time input — t

Fall time input

– 25 ns —

periph

Rise time output — 25 ns — Fall time output

is the bus clock (f

). For SPI1 f

BUS

is the system clock (f

periph

SYS

periph

— —

ns 3 ns 4

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 41

6 7

MSB IN

BIT 6 . . . 1

SLAVE MSB

SLAVE LSB OUT

NOTE: Not defined

SEE NOTE

see note

(INPUT)

(CPOL=0)

SPSCK

(CPOL=1)

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

LSB IN

BIT 6 . . . 1

Peripheral operating requirements and behaviors

Table 34. SPI slave mode timing on slew rate enabled pads

Num. Symbol Description Min. Max. Unit Note

1 f 2 t

SPSCK

3 t 4 t 5 t

WSPSCK

6 t 7 t 8 t

9 t 10 t 11 t 12 t

13 t

Lead

Lag

Frequency of operation 0 f

SPSCK period 4 x t

periph

/4 Hz 1

periph

— ns 2 Enable lead time 1 — t Enable lag time 1 — t Clock (SPSCK) high or low time t

– 30 — ns —

periph

Data setup time (inputs) 2 — ns — Data hold time (inputs) 7 — ns —

Slave access time — t

Slave MISO disable time — t

dis

Data valid (after SPSCK edge) — 122 ns —

periph

Data hold time (outputs) 0 — ns — Rise time input — t

Fall time input

– 25 ns —

periph

Rise time output — 36 ns — Fall time output

periph

ns 3 ns 4

— —

1. For SPI0, f

2. t

periph

= 1/f

is the bus clock (f

periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

Figure 16. SPI slave mode timing (CPHA = 0)

Kinetis KL25 Sub-Family, Rev5 08/2014.

). For SPI1 f

BUS

is the system clock (f

periph

SYS

Freescale Semiconductor, Inc.

Page 42

6 7

MSB IN

BIT 6 . . . 1

MSB OUT SLAVE LSB OUT

12 13

SLAVE

see note

(INPUT)

(CPOL=0)

SPSCK

(CPOL=1)

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

NOTE: Not defined

LSB IN

BIT 6 . . . 1

Peripheral operating requirements and behaviors

Figure 17. SPI slave mode timing (CPHA = 1)

3.8.4 Inter-Integrated Circuit Interface (I2C) timing

Table 35. I2C timing

Characteristic Symbol Standard Mode Fast Mode Unit

Minimum Maximum Minimum Maximum

0.9

kHz

µs

— ns 300 ns 300 ns

SCL Clock Frequency f

Hold time (repeated) START condition.

SCL

tHD; STA 4 — 0.6 — µs

0 100 0 400

After this period, the first clock pulse is

generated.

LOW period of the SCL clock t

HIGH period of the SCL clock t

Set-up time for a repeated START

LOW

HIGH

tSU; STA 4.7 — 0.6 — µs

4.7 — 1.3 — µs 4 — 0.6 — µs

condition

Data hold time for I2C bus devices tHD; DAT 0

Data set-up time tSU; DAT 250

Rise time of SDA and SCL signals t

Fall time of SDA and SCL signals t

— 1000 20 +0.1C — 300 20 +0.1C

3.45 — 1003,

Set-up time for STOP condition tSU; STO 4 — 0.6 — µs

Bus free time between STOP and

START condition

Pulse width of spikes that must be

BUF

4.7 — 1.3 — µs

N/A N/A 0 50 ns

suppressed by the input filter

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 43



SDA

HD; STA

HD; DAT

LOW

SU; DAT

HIGH

SU; STA

HD; STA

SU; STO

BUF

SCL

Peripheral operating requirements and behaviors

2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines.

3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. Input signal Slew = 10 ns and Output Load = 50 pF

5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t

SU; DAT

≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t + t

= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is

SU; DAT

released.

7. Cb = total capacitance of the one bus line in pF.

rmax

Figure 18. Timing definition for fast and standard mode devices on the I2C bus

3.8.5

UART

See General switching specifications.

3.9

Human-machine interfaces (HMI)

3.9.1 TSI electrical specifications

Table 36. TSI electrical specifications

Symbol Description Min. Typ. Max. Unit

TSI_RUNF Fixed power consumption in run mode — 100 — µA TSI_RUNV Variable power consumption in run mode

(depends on oscillator's current selection)

TSI_EN Power consumption in enable mode — 100 — µA

TSI_DIS Power consumption in disable mode — 1.2 — µA

TSI_TEN TSI analog enable time — 66 — µs

TSI_CREF TSI reference capacitor — 1.0 — pF

TSI_DVOLT Voltage variation of VP & VM around nominal

values

Kinetis KL25 Sub-Family, Rev5 08/2014.

1.0 — 128 µA

0.19 — 1.03 V

Freescale Semiconductor, Inc.

Page 44

Dimensions

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package Then use this document number

32-pin QFN 98ASA00473D 48-pin QFN 98ASA00466D 64-pin LQFP 98ASS23234W 80-pin LQFP 98ASS23174W

5 Pinout

5.1 KL25 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.

LQFP64LQFP48QFN32QFN

1 1 — 1 PTE0 DISABLED PTE0 UART1_TX RTC_

2 2 — — PTE1 DISABLED PTE1 SPI1_MOSI UART1_RX SPI1_MISO I2C1_SCL 3 — — — PTE2 DISABLED PTE2 SPI1_SCK 4 — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI 5 — — — PTE4 DISABLED PTE4 SPI1_PCS0 6 — — — PTE5 DISABLED PTE5 7 3 1 — VDD VDD VDD 8 4 2 2 VSS VSS VSS 9 5 3 3 USB0_DP USB0_DP USB0_DP

10 6 4 4 USB0_DM USB0_DM USB0_DM

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

CMP0_OUT I2C1_SDA

CLKOUT

Freescale Semiconductor, Inc.

Kinetis KL25 Sub-Family, Rev5 08/2014.

Page 45

Pinout

LQFP64LQFP48QFN32QFN

11 7 5 5 VOUT33 VOUT33 VOUT33 12 8 6 6 VREGIN VREGIN VREGIN 13 9 7 — PTE20 ADC0_DP0/

14 10 8 — PTE21 ADC0_DM0/

15 11 — — PTE22 ADC0_DP3/

16 12 — — PTE23 ADC0_DM3/

17 13 9 7 VDDA VDDA VDDA 18 14 10 — VREFH VREFH VREFH 19 15 11 — VREFL VREFL VREFL 20 16 12 8 VSSA VSSA VSSA 21 17 13 — PTE29 CMP0_IN5/

22 18 14 9 PTE30 DAC0_OUT/

23 19 — — PTE31 DISABLED PTE31 TPM0_CH4 24 20 15 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 25 21 16 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 26 22 17 10 PTA0 SWD_CLK TSI0_CH1 PTA0 TPM0_CH5 SWD_CLK 27 23 18 11 PTA1 DISABLED TSI0_CH2 PTA1 UART0_RX TPM2_CH0 28 24 19 12 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH1 29 25 20 13 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 30 26 21 14 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH1 NMI_b 31 27 — — PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2 32 28 — — PTA12 DISABLED PTA12 TPM1_CH0 33 29 — — PTA13 DISABLED PTA13 TPM1_CH1 34 — — — PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX 35 — — — PTA15 DISABLED PTA15 SPI0_SCK UART0_RX 36 — — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO 37 — — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI 38 30 22 15 VDD VDD VDD 39 31 23 16 VSS VSS VSS 40 32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RX TPM_

41 33 25 18 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_

42 34 26 19 PTA20 RESET_b PTA20 RESET_b 43 35 27 20 PTB0/

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

LLWU_P5

ADC0_DP0/

ADC0_SE0

ADC0_SE4a

ADC0_SE3

ADC0_SE7a

ADC0_SE4b

ADC0_SE23/ CMP0_IN4

ADC0_SE8/ TSI0_CH0

ADC0_SE0 ADC0_DM0/

ADC0_SE4a ADC0_DP3/

ADC0_SE3 ADC0_DM3/

ADC0_SE7a

CMP0_IN5/ ADC0_SE4b

DAC0_OUT/ ADC0_SE23/ CMP0_IN4

ADC0_SE8/ TSI0_CH0

PTE20 TPM1_CH0 UART0_TX

PTE21 TPM1_CH1 UART0_RX

PTE22 TPM2_CH0 UART2_TX

PTE23 TPM2_CH1 UART2_RX

PTE29 TPM0_CH2 TPM_

CLKIN0

PTE30 TPM0_CH3 TPM_

CLKIN1

CLKIN0

CLKIN1

PTB0/ LLWU_P5

I2C0_SCL TPM1_CH0

LPTMR0_ ALT1

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Pinout

LQFP64LQFP48QFN32QFN

44 36 28 21 PTB1 ADC0_SE9/

45 37 29 — PTB2 ADC0_SE12/

46 38 30 — PTB3 ADC0_SE13/

47 — — — PTB8 DISABLED PTB8 EXTRG_IN 48 — — — PTB9 DISABLED PTB9 49 — — — PTB10 DISABLED PTB10 SPI1_PCS0 50 — — — PTB11 DISABLED PTB11 SPI1_SCK 51 39 31 — PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_MOSI UART0_RX TPM_

52 40 32 — PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_MISO UART0_TX TPM_

53 41 — — PTB18 TSI0_CH11 TSI0_CH11 PTB18 TPM2_CH0 54 42 — — PTB19 TSI0_CH12 TSI0_CH12 PTB19 TPM2_CH1 55 43 33 — PTC0 ADC0_SE14/

56 44 34 22 PTC1/

57 45 35 23 PTC2 ADC0_SE11/

58 46 36 24 PTC3/

59 47 — — VSS VSS VSS 60 48 — — VDD VDD VDD 61 49 37 25 PTC4/

62 50 38 26 PTC5/

63 51 39 27 PTC6/

64 52 40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO SPI0_MOSI 65 53 — — PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4 66 54 — — PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5 67 55 — — PTC10 DISABLED PTC10 I2C1_SCL 68 56 — — PTC11 DISABLED PTC11 I2C1_SDA 69 — — — PTC12 DISABLED PTC12 TPM_

70 — — — PTC13 DISABLED PTC13 TPM_

71 — — — PTC16 DISABLED PTC16 72 — — — PTC17 DISABLED PTC17

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

TSI0_CH6

TSI0_CH7

TSI0_CH8

TSI0_CH13

ADC0_SE15/ LLWU_P6/ RTC_CLKIN

LLWU_P7

LLWU_P8

LLWU_P9

LLWU_P10

TSI0_CH14

TSI0_CH15

DISABLED PTC3/

DISABLED PTC4/

DISABLED PTC5/

CMP0_IN0 CMP0_IN0 PTC6/

ADC0_SE9/ TSI0_CH6

ADC0_SE12/ TSI0_CH7

ADC0_SE13/ TSI0_CH8

ADC0_SE14/ TSI0_CH13

ADC0_SE15/ TSI0_CH14

ADC0_SE11/ TSI0_CH15

PTB1 I2C0_SDA TPM1_CH1

PTB2 I2C0_SCL TPM2_CH0

PTB3 I2C0_SDA TPM2_CH1

SPI1_MISO

CLKIN0

SPI1_MOSI

CLKIN1

PTC0 EXTRG_IN CMP0_OUT

PTC1/ LLWU_P6/ RTC_CLKIN

PTC2 I2C1_SDA TPM0_CH1

LLWU_P7

LLWU_P8

LLWU_P9

LLWU_P10

I2C1_SCL TPM0_CH0

UART1_RX TPM0_CH2 CLKOUT

SPI0_PCS0 UART1_TX TPM0_CH3

SPI0_SCK LPTMR0_

ALT2

SPI0_MOSI EXTRG_IN SPI0_MISO

CLKIN0

CLKIN1

CMP0_OUT

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Pinout

LQFP64LQFP48QFN32QFN

73 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 74 58 42 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 75 59 43 — PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO 76 60 44 — PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI 77 61 45 29 PTD4/

78 62 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 79 63 47 31 PTD6/

80 64 48 32 PTD7 DISABLED PTD7 SPI1_MISO UART0_TX SPI1_MOSI

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

LLWU_P14

LLWU_P15

DISABLED PTD4/

LLWU_P14

ADC0_SE7b ADC0_SE7b PTD6/

LLWU_P15

SPI1_PCS0 UART2_RX TPM0_CH4

SPI1_MOSI UART0_RX SPI1_MISO

5.2 KL25 pinouts

The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL25 Signal Multiplexing and Pin

Assignments.

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VSSA

VREFL

VREFH

VDDA

PTE23

PTE22

PTE21

PTE20

VREGIN

VOUT33

USB0_DM

USB0_DP

VSS

VDD

PTE5

PTE4

PTE3

PTE2

PTE1

PTE0

PTD7

PTD6/LLWU_P15

PTD5

PTD4/LLWU_P14

PTD3

PTD2

PTD1

PTD0

PTC17

PTC16

PTC13

PTC12

PTC11

PTC10

PTC9

PTC8

PTC7

PTC6/LLWU_P10

PTC5/LLWU_P9

PTC4/LLWU_P8

VDD

VSS

PTC3/LLWU_P7

PTC2

PTC1/LLWU_P6/RTC_CLKIN

PTC0

PTB19

PTB18

PTB17

PTB16

PTB11

PTB10

PTB9

PTB8

PTB3

PTB2

PTB1

PTB0/LLWU_P5

PTA20

PTA19

PTA18

VSS

VDD

PTA17

PTA16

PTA15

PTA14

PTA13

PTA12

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

PTE25

PTE24

PTE31

PTE30

PTE29

Pinout

Figure 19. KL25 80-pin LQFP pinout diagram

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PTE24

PTE31

PTE30

PTE29

VSSA

VREFL

VREFH

VDDA

PTE23

PTE22

PTE21

PTE20

VREGIN

VOUT33

USB0_DM

USB0_DP

VSS

VDD

PTE1

PTE0

PTD7

PTD6/LLWU_P15

PTD5

PTD4/LLWU_P14

PTD3

PTD2

PTD1

PTD0

PTC11

PTC10

PTC9

PTC8

PTC7

PTC6/LLWU_P10

PTC5/LLWU_P9

PTC4/LLWU_P8

VDD

VSS

PTC3/LLWU_P7

PTC2

PTC1/LLWU_P6/RTC_CLKIN

PTC0

PTB19

PTB18

PTB17

PTB16

PTB3

PTB2

PTB1

PTB0/LLWU_P5

PTA20

PTA19

PTA18

VSS

VDD

PTA13

PTA12

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

PTE25

Pinout

Figure 20. KL25 64-pin LQFP pinout diagram

Kinetis KL25 Sub-Family, Rev5 08/2014.

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Page 50

VSSA

VREFL

VREFH

VDDA

PTE21

PTE20

VREGIN

VOUT33

USB0_DM

USB0_DP

VSS

VDD

PTD7

PTD6/LLWU_P15

PTD5

PTD4/LLWU_P14

PTD3

PTD2

PTD1

PTD0

PTC7

PTC6/LLWU_P10

PTC5/LLWU_P9

PTC4/LLWU_P8

PTC3/LLWU_P7

PTC2

PTC1/LLWU_P6/RTC_CLKIN

PTC0

PTB17

PTB16

PTB3

PTB2

PTB1

PTB0/LLWU_P5

PTA20

PTA19

PTA3

PTA2

PTA1

PTA0

PTE25

PTE24

PTE30

PTE29

PTA18

VSS

VDD

PTA4

Pinout

Figure 21. KL25 48-pin QFN pinout diagram

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PTD7

PTD6/LLWU_P15

PTD5

PTD4/LLWU_P14

PTC7

PTC6/LLWU_P10

PTC5/LLWU_P9

PTC4/LLWU_P8

PTA2

PTA1

PTA0

PTE30

VSS

VDD

PTA4

PTA3

PTB0/LLWU_P5

PTA20

PTA19

PTA18

PTC3/LLWU_P7

PTC2

PTC1/LLWU_P6/RTC_CLKIN

PTB1

VSSA

VDDA

VREGIN

VOUT33

USB0_DM

USB0_DP

VSS

PTE0

Ordering parts

Figure 22. KL25 32-pin QFN pinout diagram

Ordering parts

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PKL25 and MKL25

Part identification

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Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q KL## A FFF R T PP CC N

7.3

Fields

This table lists the possible values for each field in the part number (not all combinations are valid):

Table 37. Part number fields descriptions

Field Description Values

Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification KL## Kinetis family • KL25 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 32 = 32 KB

• 64 = 64 KB

• 128 = 128 KB R Silicon revision • (Blank) = Main

• A = Revision after main T Temperature range (°C) • V = –40 to 105 PP Package identifier • FM = 32 QFN (5 mm x 5 mm)

• FT = 48 QFN (7 mm x 7 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• LK = 80 LQFP (12 mm x 12 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel

• (Blank) = Trays

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Terminology and guidelines

7.4 Example

This is an example part number: MKL25Z64VLK4

8 Terminology and guidelines

8.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

8.1.1 Example

This is an example of an operating requirement:

Symbol Description Min. Max. Unit

1.0 V core supply voltage

0.9 1.1 V

8.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

8.2.1

This is an example of an operating behavior:

Example

Symbol Description Min. Max. Unit

Kinetis KL25 Sub-Family, Rev5 08/2014.

Digital I/O weak pullup/ pulldown current

10 130 µA

Freescale Semiconductor, Inc.

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Terminology and guidelines

8.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

8.3.1 Example

This is an example of an attribute:

Symbol Description Min. Max. Unit

CIN_D Input capacitance:

digital pins

— 7 pF

8.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

8.4.1

This is an example of an operating rating:

Example

Symbol Description Min. Max. Unit

1.0 V core supply voltage

–0.3 1.2 V

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Measured characteristic

Operating rating

Failures in time (ppm)

The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

–∞

- No permanent failure

- Correct operation

Normal operating range

Fatal range

Expected permanent failure

Fatal range

Expected permanent failure

∞

Operating rating (max.)

Operating requirement (max.)

Operating requirement (min.)

Operating rating (min.)

Operating (power on)

Degraded operating range

–∞

No permanent failure

Handling range

Fatal range

Expected permanent failure

Fatal range

Expected permanent failure

∞

Handling rating (max.)

Handling rating (min.)

Handling (power off)

- No permanent failure

- Possible decreased life

- Possible incorrect operation

- No permanent failure

- Possible decreased life

- Possible incorrect operation

Terminology and guidelines

8.5 Result of exceeding a rating

8.6 Relationship between ratings and operating requirements

8.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

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Terminology and guidelines

8.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions

Typical values are provided as design guidelines and are neither tested nor guaranteed.

8.8.1 Example 1

This is an example of an operating behavior that includes a typical value:

Symbol Description Min. Typ. Max. Unit

Digital I/O weak pullup/pulldown current

10 70 130 µA

8.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions:

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0.90

0.95

1.00

1.05

1.10

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

150 °C

105 °C

25 °C

–40 °C

VDD(V)

(μA)

DD_STOP

Revision history

8.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified):

Table 38. Typical value conditions

Symbol Description Value Unit

Ambient temperature 25 °C

3.3 V supply voltage 3.3 V

9 Revision history

The following table provides a revision history for this document.

Table 39. Revision history

Rev. No. Date Substantial Changes

2 9/2012 Completed all the TBDs, initial public release. 3 9/2012 Updated Signal Multiplexing and Pin Assignments table to add UART2

signals.

4 3/2014 • Updated the front page and restructured the chapters

Table continues on the next page...

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Revision history

Rev. No. Date Substantial Changes

Table 39. Revision history (continued)

• Added a note to the I

• Updated Voltage and current operating ratings

• Updated Voltage and current operating requirements

• Updated the Voltage and current operating behaviors

• Updated Power mode transition operating behaviors

• Updated Capacitance attributes

• Updated footnote in the Device clock specifications

• Updated t

in the Flash timing specifications — commands

ersall

• Updated VADIN in the 16-bit ADC operating conditions

• Updated Temp sensor slope and voltage and added a note to them in the 16-bit ADC electrical characteristics

• Removed TA in the 12-bit DAC operating requirements

• Added Inter-Integrated Circuit Interface (I2C) timing

08/2014 • Updated related source and added block diagram in the front

page

• Updated Power consumption operating behaviors

• Updated the note in USB electrical specifications

in the ESD handling ratings

LAT

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How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein.

Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions.

Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.

Document Number KL25P80M48SF0

Revision 5 08/2014

Freescale MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Ratings

1.1 Thermal handling ratings

1.2 Moisture handling ratings

1.3 ESD handling ratings

General

2.1 AC electrical characteristics

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

2.2.2 LVD and POR operating requirements

2.2.3 Voltage and current operating behaviors

2.2.4 Power mode transition operating behaviors

2.2.5 Power consumption operating behaviors

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

EMC radiated emissions operating behaviors

2.2.7 Designing with radiated emissions in mind

2.2.8 Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

2.3.2 General switching specifications

2.4 Thermal specifications

2.4.1 Thermal operating requirements

2.4.2 Thermal attributes

Peripheral operating requirements and behaviors

3.1 Core modules

System modules

Clock modules

3.3.1 MCG specifications

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

3.3.2.2 Oscillator frequency specifications

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

3.4.1.2 Flash timing specifications — commands

3.4.1.3 Flash high voltage current behaviors

3.5 Security and integrity modules

Analog

3.6.1 ADC electrical specifications

16-bit ADC operating conditions

16-bit ADC electrical characteristics

3.6.2 CMP and 6-bit DAC electrical specifications

12-bit DAC electrical characteristics

3.6.3.2 12-bit DAC operating behaviors

Timers

Communication interfaces

3.8.1 USB electrical specifications

3.8.2 USB VREG electrical specifications

3.8.4 Inter-Integrated Circuit Interface (I2C) timing

UART

Human-machine interfaces (HMI)

3.9.1 TSI electrical specifications

Dimensions

4.1 Obtaining package dimensions

5 Pinout

5.1 KL25 Signal Multiplexing and Pin Assignments

5.2 KL25 pinouts

Ordering parts

6.1 Determining valid orderable parts

Part identification

7.1 Description

7.2 Format

Fields

Terminology and guidelines

8.1 Definition: Operating requirement

8.2 Definition: Operating behavior

8.3 Definition: Attribute

8.4 Definition: Rating

8.6 Relationship between ratings and operating requirements

8.7 Guidelines for ratings and operating requirements

8.8 Definition: Typical value

Revision history

8.9 Typical value conditions