Freescale MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4 Service Manual
...
Freescale Semiconductor, Inc.
Document Number: KL25P80M48SF0
Data Sheet: Technical Data Rev 5 08/2014
Kinetis KL25 Sub-Family
48 MHz Cortex-M0+ Based Microcontroller with USB
Designed with efficiency in mind. Compatible with all other
Kinetis L families as well as Kinetis K2x family. General purpose
MCU with USB 2.0, featuring market leading ultra low-power to
provide developers an appropriate entry-level 32-bit solution.
This product offers:
• Run power consumption down to 47 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48 MHz
with industry leading throughput
• Memory option is up to 128 KB flash and 16 KB RAM
• Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
Performance
• 48 MHz ARM® Cortex®-M0+ core
Memories and memory interfaces
• Up to 128 KB program flash memory
• Up to 16 KB SRAM
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• 4-channel DMA controller, supporting up to 63 request
sources
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
Clocks
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source
• 1 kHz LPO clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• Up to 66 general-purpose input/output (GPIO)
Communication interfaces
• USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator
• Two 8-bit SPI modules
• One low power UART module
• Two UART modules
• Two I2C module
Analog Modules
• 16-bit SAR ADC
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Timers
• Six channel Timer/PWM (TPM)
• Two 2-channel Timer/PWM modules
• Periodic interrupt timers
• 16-bit low-power timer (LPTMR)
• Real time clock
MKL25ZxxVFM4
MKL25ZxxVFT4
MKL25ZxxVLH4
MKL25ZxxVLK4
32-pin QFN (FM)
5 x 5 x 1 Pitch 0.5 mm
64-pin LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
48-pin QFN (FT)
7 x 7 x 1 Pitch 0.5 mm
80-pin LQFP (LK)
12 x 12 x 1.4 Pitch 0.5
mm
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Security and integrity modules
• 80-bit unique identification number per chip
Ordering Information
1
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MKL25Z32VFM4 32 4 23
MKL25Z64VFM4 64 8 23
MKL25Z128VFM4 128 16 23
MKL25Z32VFT4 32 4 36
MKL25Z64VFT4 64 8 36
MKL25Z128VFT4 128 16 36
MKL25Z32VLH4 32 4 50
MKL25Z64VLH4 64 8 50
MKL25Z128VLH4 128 16 50
MKL25Z32VLK4 32 4 66
MKL25Z64VLK4 64 8 66
MKL25Z128VLK4 128 16 66
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type Description Resource
Selector Guide The Freescale Solution Advisor is a web-based tool that features
Solution Advisor
interactive application wizards and a dynamic product selector.
Product Brief The Product Brief contains concise overview/summary information to
KL2 Family Product Brief
1
enable quick evaluation of a device for design suitability.
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal
KL25P80M48SF0RM
KL25P80M48SF0
1
1
connections.
Chip Errata The chip mask set Errata provides additional or corrective
KINETIS_L_xN97F
2
information for a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings. QFN 32-pin: 98ASA00473D
QFN 48-pin: 98ASA00466D
LQFP 64-pin: 98ASS23234W
LQFP 80-pin: 98ASS23174W
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x”
replaced by the revision of the device you are using.
Figure 1 shows the functional modules in the chip.
1
1
1
1
2
Freescale Semiconductor, Inc.
Kinetis KL25 Sub-Family, Rev5 08/2014.
Kinetis KL25 Family
®
ARM
Cortex™-M0+
Core
Debug
interfaces
Interrupt
controller
MTB
Security
and Integrity
Internal
watchdog
Analog
16-bit ADC
x1
Analog
comparator
x1
6-bit DAC
12-bit DAC
System
Internal
watchdog
DMA
BME
Timers
Timers
1x6ch+2x2ch
Low
power timer
x1
Periodic
interrupt
timers
RTC
Memories and
Memory Interfaces
Program
flash
RAM
Communication
Interfaces
2
I C
x2
Low power
UART
x1
SPI
x2
UART
x2
Clocks
Phase-
locked loop
Frequency-
locked loop
Low/high
frequency
oscillator
Internal
reference
clocks
Human-Machine
Interface (HMI)
GPIOs
with
interrupt
TSI
LEGEND
Figure 1. Functional block diagram
Kinetis KL25 Sub-Family, Rev5 08/2014.
USB LS/FS
x1
Migration difference from KL15 family
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings.................................................5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications.....................................................18
2.4.1 Thermal operating requirements......................... 18
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 19
3.1 Core modules.................................................................. 19
3.1.1 SWD electricals .................................................. 19
3.2 System modules..............................................................21
3.3 Clock modules.................................................................21
3.3.1 MCG specifications..............................................21
3.3.2 Oscillator electrical specifications........................23
3.4 Memories and memory interfaces................................... 25
3.4.1 Flash electrical specifications..............................25
3.5 Security and integrity modules........................................ 27
3.6 Analog............................................................................. 27
3.6.1 ADC electrical specifications............................... 27
3.6.2 CMP and 6-bit DAC electrical specifications....... 32
3.6.3 12-bit DAC electrical characteristics....................33
3.7 Timers..............................................................................36
3.8 Communication interfaces...............................................36
3.8.1 USB electrical specifications............................... 36
3.8.2 USB VREG electrical specifications.................... 37
3.8.3 SPI switching specifications................................ 37
3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 42
3.8.5 UART...................................................................43
3.9 Human-machine interfaces (HMI)....................................43
3.9.1 TSI electrical specifications................................. 43
4 Dimensions............................................................................. 44
4.1 Obtaining package dimensions....................................... 44
5 Pinout......................................................................................44
5.1 KL25 Signal Multiplexing and Pin Assignments...............44
5.2 KL25 pinouts....................................................................47
6 Ordering parts......................................................................... 51
6.1 Determining valid orderable parts....................................51
7 Part identification.....................................................................51
7.1 Description.......................................................................52
7.2 Format............................................................................. 52
7.3 Fields...............................................................................52
7.4 Example...........................................................................52
8 Terminology and guidelines.................................................... 53
8.1 Definition: Operating requirement....................................53
8.2 Definition: Operating behavior.........................................53
8.3 Definition: Attribute.......................................................... 54
8.4 Definition: Rating............................................................. 54
8.5 Result of exceeding a rating............................................54
8.6 Relationship between ratings and operating
requirements....................................................................55
8.7 Guidelines for ratings and operating requirements..........55
8.8 Definition: Typical value...................................................56
8.9 Typical value conditions.................................................. 57
9 Revision history.......................................................................57
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Freescale Semiconductor, Inc.
Kinetis KL25 Sub-Family, Rev5 08/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
T
STG
T
SDR
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Storage temperature –55 150 °C 1
Solder temperature, lead-free — 260 °C 2
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol Description Min. Max. Unit Notes
V
HBM
V
CDM
I
LAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Electrostatic discharge voltage, human body model –2000 +2000 V 1
Electrostatic discharge voltage, charged-device
model
Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
–500 +500 V 2
Kinetis KL25 Sub-Family, Rev5 08/2014.
5
Freescale Semiconductor, Inc.
80%
20%
50%
V
IL
Input Signal
V
IH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
V
I
DD
V
I
V
DDA
V
USB_DP
V
USB_DM
V
REGIN
DD
IO
D
Digital supply voltage –0.3 3.8 V
Digital supply current — 120 mA
IO pin input voltage –0.3 VDD + 0.3 V
Instantaneous maximum current single pin limit (applies to
all port pins)
Analog supply voltage VDD – 0.3 VDD + 0.3 V
USB_DP input voltage –0.3 3.63 V
USB_DM input voltage –0.3 3.63 V
USB regulator input –0.3 6.0 V
–25 25 mA
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
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Freescale Semiconductor, Inc.
Figure 2. Input signal measurement reference
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
Kinetis KL25 Sub-Family, Rev5 08/2014.
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
V
DD
V
DDA
VDD – V
VSS – V
V
IH
Supply voltage 1.71 3.6 V
Analog supply voltage 1.71 3.6 V —
DDAVDD
SSAVSS
-to-V
-to-V
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
differential voltage –0.1 0.1 V —
DDA
differential voltage –0.1 0.1 V —
SSA
0.7 × V
0.75 × V
DD
DD
—
—
V
V
General
—
V
V
HYS
I
ICIO
I
ICcont
Input low voltage
IL
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
Input hysteresis 0.06 × V
IO pin negative DC injection current—single pin
• VIN < VSS–0.3V
Contiguous pin DC injection current —regional limit,
—
—
DD
0.35 × V
0.3 × V
DD
DD
V
V
— V —
–3 — mA
—
1
—
includes sum of negative injection currents of 16
contiguous pins
–25 — mA
DD
V
DD
V 2
V
V
ODPU
RAM
• Negative current injection
Open drain pullup voltage level V
VDD voltage required to retain RAM 1.2 — V —
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If V
greater than V
(= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
IO_MIN
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (V
IO_MIN
- VIN)/|I
ICIO
|.
2. Open drain outputs must be pulled to VDD.
IN
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
V
POR
Kinetis KL25 Sub-Family, Rev5 08/2014.
Falling VDD POR detect voltage 0.8 1.1 1.5 V —
Table continues on the next page...
Freescale Semiconductor, Inc.
7
General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
V
V
LVW1H
V
LVW2H
V
LVW3H
V
LVW4H
V
V
V
LVW1L
V
LVW2L
V
LVW3L
V
LVW4L
V
V
t
LVDH
HYSH
LVDL
HYSL
LPO
Falling low-voltage detect threshold — high
2.48 2.56 2.64 V —
range (LVDV = 01)
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
Low-voltage inhibit reset/recover hysteresis —
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
— ±60 — mV —
high range
Falling low-voltage detect threshold — low
1.54 1.60 1.66 V —
range (LVDV=00)
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
Low-voltage inhibit reset/recover hysteresis —
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
— ±40 — mV —
low range
Bandgap voltage reference 0.97 1.00 1.03 V —
BG
Internal low power oscillator period — factory
900 1000 1100 μs —
trimmed
V
V
V
V
V
V
V
V
1
1
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
V
OH
V
OH
I
OHT
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Freescale Semiconductor, Inc.
Output high voltage — Normal drive pad (except
RESET)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
Output high voltage — High drive pad (except
VDD – 0.5
VDD – 0.5
—
—
V
V
RESET)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high current total for all ports — 100 mA —
Table continues on the next page...
Kinetis KL25 Sub-Family, Rev5 08/2014.
1, 2
1, 2
General
Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
V
V
I
OLT
I
R
R
I
I
I
OL
OL
IN
IN
IN
OZ
PU
PD
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
Output low current total for all ports — 100 mA —
Input leakage current (per pin) for full temperature
range
Input leakage current (per pin) at 25 °C — 0.025 μA 3
Input leakage current (total all pins) for full
temperature range
Hi-Z (off-state) leakage current (per pin) — 1 μA —
Internal pullup resistors 20 50 kΩ 4
Internal pulldown resistors 20 50 kΩ 5
—
—
—
—
— 1 μA 3
— 65 μA 3
0.5
0.5
0.5
0.5
V
V
V
V
1
1
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = V
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
SS
2.2.4 Power mode transition operating behaviors
All specifications except t
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
and VLLSx→RUN recovery times in the following
POR
Symbol Description Min. Typ. Max. Unit
t
POR
Kinetis KL25 Sub-Family, Rev5 08/2014.
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
Table continues on the next page...
— — 300 μs 1
Freescale Semiconductor, Inc.
9
General
Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
—
95
93
42
4
4
4
115
115
53
4.6
4.4
4.4
μs
μs
μs
μs
μs
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol Description Temp. Typ. Max Unit Note
I
DDA
I
DD_RUNCO_ CM
I
DD_RUNCO
I
DD_RUN
Analog supply current — — See note mA 1
Run mode current in compute operation
- 48 MHz core / 24 MHz flash/ bus
disabled, LPTMR running using 4 MHz
internal reference clock, CoreMark®
benchmark code executing from flash,
at 3.0 V
Run mode current in compute operation
- 48 MHz core / 24 MHz flash / bus
clock disabled, code of while(1) loop
executing from flash, at 3.0 V
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
disabled, code executing from flash, at
3.0 V
— 6.4 — mA 2
— 3.9 4.8 mA 3
— 5 5.9 mA 3
10
Freescale Semiconductor, Inc.
Table continues on the next page...
Kinetis KL25 Sub-Family, Rev5 08/2014.
Table 9. Power consumption operating behaviors (continued)
Symbol Description Temp. Typ. Max Unit Note
I
DD_RUN
I
DD_WAIT
I
DD_WAIT
I
DD_PSTOP2
I
DD_VLPRCO _CM
I
DD_VLPRCO
I
DD_VLPR
I
DD_VLPR
I
DD_VLPW
I
DD_STOP
I
DD_VLPS
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
enabled, code executing from flash, at
at 25 °C 6.2 6.5 mA 3, 4
at 125 °C 6.8 7.1 mA
3.0 V
Wait mode current - core disabled / 48
— 3.1 3.8 mA 3
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
Wait mode current - core disabled / 24
— 2.4 3.2 mA 3
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled • at 3.0 V
Stop mode current with partial stop 2
— 1.6 2 mA 3
clocking option - core and system
disabled / 10.5 MHz bus, at 3.0 V
Very-low-power run mode current in
— 777 — µA 5
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, LPTMR
running with 4 MHz internal reference
clock, CoreMark benchmark code
executing from flash, at 3.0 V
Very low power run mode current in
— 171 420 µA 6
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, code
executing from flash, at 3.0 V
Very low power run mode current - 4
— 204 449 µA 6
MHz core / 0.8 MHz bus and flash, all
peripheral clocks disabled, code
executing from flash, at 3.0 V
Very low power run mode current - 4
— 262 509 µA 4, 6
MHz core / 0.8 MHz bus and flash, all
peripheral clocks enabled, code
executing from flash, at 3.0 V
Very low power wait mode current -
— 123 366 µA 6
core disabled / 4 MHz system / 0.8
MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled,
at 3.0 V
Stop mode current at 3.0 V at 25 °C 319 343 µA —
at 50 °C 333 365 µA
at 70 °C 353 400 µA
at 85 °C 380 450 µA
at 105 °C 444 572 µA
Very-low-power stop mode current at
3.0 V
at 25 °C 3.75 8.46 µA —
at 50 °C 6.66 13.41 µA
at 70 °C 12.9 25.71 µA
General
Kinetis KL25 Sub-Family, Rev5 08/2014.
Table continues on the next page...
11
Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol Description Temp. Typ. Max Unit Note
at 85 °C 22.7 44.06 µA
at 105 °C 48.4 90.1 µA
I
DD_LLS
I
DD_VLLS3
I
DD_VLLS1
I
DD_VLLS0
I
DD_VLLS0
Low leakage stop mode current at 3.0
V
Very low-leakage stop mode 3 current
at 3.0 V
Very low-leakage stop mode 1 current
at 3.0 V
Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0
V
Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0
V
at 25 °C 1.68 2.09 µA —
at 50 °C 3.05 4.04 µA
at 70 °C 5.71 7.75 µA
at 85 °C 10 13.54 µA
at 105 °C 22.4 30.41 µA
at 25 °C 1.22 1.6 µA —
at 50 °C 2.25 2.31 µA
at 70 °C 4.21 5.44 µA
at 85 °C 7.37 9.44 µA
at 105 °C 16.6 21.76 µA
at 25 °C 0.58 0.94 µA —
at 50 °C 1.26 1.31 µA
at 70 °C 2.53 3.33 µA
at 85 °C 4.74 6.1 µA
at 105 °C 11.4 15.27 µA
at 25 °C 0.31 0.65 µA —
at 50 °C 0.99 1.43 µA
at 70 °C 2.25 3.01 µA
at 85 °C 4.46 5.83 µA
at 105 °C 11.13 14.99 µA
at 25 °C 0.12 0.47 µA 7
at 50 °C 0.8 1.24 µA
at 70 °C 2.06 2.81 µA
at 85 °C 4.27 5.62 µA
at 105 °C 10.93 14.78 µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for
time.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout.
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Kinetis KL25 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 10. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
I
IREFSTEN4MHz
I
IREFSTEN32KHz
I
EREFSTEN4MHz
I
EREFSTEN32KHz
I
CMP
I
RTC
I
UART
I
TPM
4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured
by entering all modes with
the crystal enabled.
VLLS1 440 490 540 560 570 580 nA
VLLS3 440 490 540 560 570 580
LLS 490 490 540 560 570 680
VLPS 510 560 560 560 610 680
STOP 510 560 560 560 610 680
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
UART peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source waiting for RX data at
115200 baud rate. Includes
selected clock source power
consumption.
MCGIRCLK
(4 MHz
internal
reference
clock)
OSCERCLK
(4 MHz
external
crystal)
TPM peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source configured for output
compare generating 100 Hz
clock signal. No load is
placed on the I/O generating
the clock signal. Includes
selected clock source and
MCGIRCLK
(4 MHz
internal
reference
clock)
OSCERCLK
(4 MHz
external
crystal)
I/O switching currents.
56 56 56 56 56 56 µA
52 52 52 52 52 52 µA
206 228 237 245 251 258 µA
22 22 22 22 22 22 µA
432 357 388 475 532 810 nA
66 66 66 66 66 66 µA
214 237 246 254 260 268
86 86 86 86 86 86 µA
235 256 265 274 280 287
General
Kinetis KL25 Sub-Family, Rev5 08/2014.
Table continues on the next page...
13
Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
I
I
ADC
BG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
ADC peripheral adder combining the
measured values at VDD and V
placing the device in STOP or VLPS mode.
ADC is configured for low power mode using
the internal clock and continuous
conversions.
DDA
by
45 45 45 45 45 45 µA
366 366 366 366 366 366 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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Freescale Semiconductor, Inc.
Kinetis KL25 Sub-Family, Rev5 08/2014.
All Off
Temperature = 25, V = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
DD
All Peripheral CLK Gates
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on V
DD(A)
Run Mode Current Vs Core Frequency
8.00E-03
7.00E-03
6.00E-03
5.00E-03
4.00E-03
3.00E-03
2.00E-03
1.00E-03
000.00E+00
'1-1
1 2
3
4
6
12 24
48
'1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2
General
Figure 3. Run mode supply current vs. core frequency
Kinetis KL25 Sub-Family, Rev5 08/2014.
15
Freescale Semiconductor, Inc.
VLPR Mode Current Vs Core Frequency
Temperature = 25, V = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
DD
All Peripheral CLK Gates
'1-1'1-2'1-2'1-
4
All Off
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD (A)
400.00E-06
350.00E-06
300.00E-06
250.00E-06
200.00E-06
150.00E-06
100.00E-06
50.00E-06
000.00E+00
1 2
4
General
Figure 4. VLPR mode current vs. core frequency
2.2.6
EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP
package
Symbol Description Frequency
band
(MHz)
V
V
V
V
V
RE_IEC
RE1
RE2
RE3
RE4
Radiated emissions voltage, band 1 0.15–50 13 dBμV 1, 2
Radiated emissions voltage, band 2 50–150 15 dBμV
Radiated emissions voltage, band 3 150–500 12 dBμV
Radiated emissions voltage, band 4 500–1000 7 dBμV
IEC level 0.15–1000 M — 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
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Freescale Semiconductor, Inc.
Typ. Unit Notes
Kinetis KL25 Sub-Family, Rev5 08/2014.
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, f
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
= 8 MHz (crystal), f
OSC
= 48 MHz, f
SYS
= 48 MHz
BUS
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol Description Min. Max. Unit
C
IN
Input capacitance — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
f
SYS
f
BUS
f
FLASH
f
SYS_USB
f
LPTMR
f
SYS
f
BUS
f
FLASH
f
LPTMR
System and core clock — 48 MHz
Bus clock — 24 MHz
Flash clock — 24 MHz
System and core clock when Full Speed USB in operation 20 — MHz
LPTMR clock — 24 MHz
VLPR and VLPS modes
System and core clock — 4 MHz
Bus clock — 1 MHz
Flash clock — 1 MHz
LPTMR clock
2
Table continues on the next page...
1
— 24 MHz
Kinetis KL25 Sub-Family, Rev5 08/2014.
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Freescale Semiconductor, Inc.
General
Table 13. Device clock specifications (continued)
Symbol Description Min. Max. Unit
f
ERCLK
f
LPTMR_ERCLK
f
osc_hi_2
f
TPM
f
UART0
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
External reference clock — 16 MHz
LPTMR external reference clock — 16 MHz
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
TPM asynchronous clock — 8 MHz
UART0 asynchronous clock — 8 MHz
— 16 MHz
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
External RESET and NMI pin interrupt pulse width —
Asynchronous path
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
1.5 — Bus clock
cycles
100 — ns 2
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
1
Symbol Description Min. Max. Unit
T
J
T
A
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Freescale Semiconductor, Inc.
Die junction temperature –40 125 °C
Ambient temperature –40 105 °C
Kinetis KL25 Sub-Family, Rev5 08/2014.
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