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Freescale MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4 Service Manual

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Page 1
KL25 Sub-Family Reference Manual
Supports: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4,
MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4,
MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4,
MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4
Document Number: KL25P80M48SF0RM
Rev. 3, September 2012
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................33
1.1.1 Purpose.........................................................................................................................................................33
1.1.2 Audience......................................................................................................................................................33
1.2 Conventions..................................................................................................................................................................33
1.2.1 Numbering systems......................................................................................................................................33
1.2.2 Typographic notation...................................................................................................................................34
1.2.3 Special terms................................................................................................................................................34
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................35
2.2 Kinetis L Series.............................................................................................................................................................35
2.3 KL25 Sub-Family Introduction.....................................................................................................................................38
2.4 Module functional categories........................................................................................................................................39
2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................39
2.4.2 System Modules...........................................................................................................................................40
2.4.3 Memories and Memory Interfaces...............................................................................................................41
2.4.4 Clocks...........................................................................................................................................................41
2.4.5 Security and Integrity modules....................................................................................................................42
2.4.6 Analog modules...........................................................................................................................................42
2.4.7 Timer modules.............................................................................................................................................42
2.4.8 Communication interfaces...........................................................................................................................43
2.4.9 Human-machine interfaces..........................................................................................................................44
2.5 Orderable part numbers.................................................................................................................................................44
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................45
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3.2 Module to Module Interconnects..................................................................................................................................45
3.2.1 Module to Module Interconnects.................................................................................................................45
3.2.2 Analog reference options.............................................................................................................................48
3.3 Core Modules................................................................................................................................................................48
3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................48
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................51
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................55
3.4 System Modules............................................................................................................................................................56
3.4.1 SIM Configuration.......................................................................................................................................56
3.4.2 System Mode Controller (SMC) Configuration...........................................................................................57
3.4.3 PMC Configuration......................................................................................................................................57
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................58
3.4.5 MCM Configuration....................................................................................................................................60
3.4.6 Crossbar-Light Switch Configuration..........................................................................................................61
3.4.7 Peripheral Bridge Configuration..................................................................................................................62
3.4.8 DMA request multiplexer configuration......................................................................................................63
3.4.9 DMA Controller Configuration...................................................................................................................66
3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................67
3.5 Clock Modules..............................................................................................................................................................70
3.5.1 MCG Configuration.....................................................................................................................................70
3.5.2 OSC Configuration......................................................................................................................................71
3.6 Memories and Memory Interfaces................................................................................................................................72
3.6.1 Flash Memory Configuration.......................................................................................................................72
3.6.2 Flash Memory Controller Configuration.....................................................................................................74
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3.6.3 SRAM Configuration...................................................................................................................................75
3.7 Analog...........................................................................................................................................................................77
3.7.1 16-bit SAR ADC Configuration..................................................................................................................77
3.7.2 CMP Configuration......................................................................................................................................81
3.7.3 12-bit DAC Configuration...........................................................................................................................83
3.8 Timers...........................................................................................................................................................................84
3.8.1 Timer/PWM Module Configuration............................................................................................................84
3.8.2 PIT Configuration........................................................................................................................................87
3.8.3 Low-power timer configuration...................................................................................................................88
3.8.4 RTC configuration.......................................................................................................................................90
3.9 Communication interfaces............................................................................................................................................91
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................91
3.9.2 SPI configuration.........................................................................................................................................96
3.9.3 I2C Configuration........................................................................................................................................97
3.9.4 UART Configuration...................................................................................................................................98
3.10 Human-machine interfaces (HMI)................................................................................................................................99
3.10.1 GPIO Configuration.....................................................................................................................................99
3.10.2 TSI Configuration........................................................................................................................................101
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................105
4.2 System memory map.....................................................................................................................................................105
4.3 Flash Memory Map.......................................................................................................................................................106
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................106
4.4 SRAM memory map.....................................................................................................................................................107
4.5 Bit Manipulation Engine...............................................................................................................................................107
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................108
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................108
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................109
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4.6.3 Modules Restricted Access in User Mode...................................................................................................112
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................112
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................115
5.2 Programming model......................................................................................................................................................115
5.3 High-Level device clocking diagram............................................................................................................................115
5.4 Clock definitions...........................................................................................................................................................116
5.4.1 Device clock summary.................................................................................................................................117
5.5 Internal clocking requirements.....................................................................................................................................119
5.5.1 Clock divider values after reset....................................................................................................................119
5.5.2 VLPR mode clocking...................................................................................................................................120
5.6 Clock Gating.................................................................................................................................................................121
5.7 Module clocks...............................................................................................................................................................121
5.7.1 PMC 1-kHz LPO clock................................................................................................................................122
5.7.2 COP clocking...............................................................................................................................................122
5.7.3 RTC clocking...............................................................................................................................................123
5.7.4 LPTMR clocking..........................................................................................................................................123
5.7.5 TPM clocking...............................................................................................................................................124
5.7.6 USB FS OTG Controller clocking...............................................................................................................124
5.7.7 UART clocking............................................................................................................................................125
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................127
6.2 Reset..............................................................................................................................................................................127
6.2.1 Power-on reset (POR)..................................................................................................................................128
6.2.2 System reset sources....................................................................................................................................128
6.2.3 MCU Resets.................................................................................................................................................131
6.2.4 Reset Pin .....................................................................................................................................................133
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6.2.5 Debug resets.................................................................................................................................................133
6.3 Boot...............................................................................................................................................................................134
6.3.1 Boot sources.................................................................................................................................................134
6.3.2 FOPT boot options.......................................................................................................................................134
6.3.3 Boot sequence..............................................................................................................................................135
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................137
7.2 Clocking Modes............................................................................................................................................................137
7.2.1 Partial Stop...................................................................................................................................................137
7.2.2 DMA Wakeup..............................................................................................................................................138
7.2.3 Compute Operation......................................................................................................................................139
7.2.4 Peripheral Doze............................................................................................................................................140
7.2.5 Clock Gating................................................................................................................................................141
7.3 Power modes.................................................................................................................................................................141
7.4 Entering and exiting power modes...............................................................................................................................143
7.5 Module Operation in Low Power Modes......................................................................................................................143
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................149
8.2 Flash Security...............................................................................................................................................................149
8.3 Security Interactions with other Modules.....................................................................................................................149
8.3.1 Security Interactions with Debug.................................................................................................................150
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................151
9.2 Debug Port Pin Descriptions.........................................................................................................................................151
9.3 SWD status and control registers..................................................................................................................................152
9.3.1 MDM-AP Control Register..........................................................................................................................153
9.3.2 MDM-AP Status Register............................................................................................................................154
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9.4 Debug Resets................................................................................................................................................................156
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................157
9.6 Debug in Low Power Modes........................................................................................................................................157
9.7 Debug & Security.........................................................................................................................................................157
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................159
10.2 Signal Multiplexing Integration....................................................................................................................................159
10.2.1 Port control and interrupt module features..................................................................................................160
10.2.2 Clock gating.................................................................................................................................................161
10.2.3 Signal multiplexing constraints....................................................................................................................161
10.3 Pinout............................................................................................................................................................................161
10.3.1 KL25 Signal Multiplexing and Pin Assignments........................................................................................161
10.3.2 KL25 Pinouts...............................................................................................................................................164
10.4 Module Signal Description Tables................................................................................................................................168
10.4.1 Core Modules...............................................................................................................................................168
10.4.2 System Modules...........................................................................................................................................169
10.4.3 Clock Modules.............................................................................................................................................169
10.4.4 Memories and Memory Interfaces...............................................................................................................169
10.4.5 Analog..........................................................................................................................................................169
10.4.6 Timer Modules.............................................................................................................................................170
10.4.7 Communication Interfaces...........................................................................................................................171
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................173
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................175
11.2 Overview.......................................................................................................................................................................175
11.2.1 Features........................................................................................................................................................175
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11.2.2 Modes of operation......................................................................................................................................176
11.3 External signal description............................................................................................................................................176
11.4 Detailed signal description............................................................................................................................................177
11.5 Memory map and register definition.............................................................................................................................177
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................183
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................185
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................186
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................186
11.6 Functional description...................................................................................................................................................187
11.6.1 Pin control....................................................................................................................................................187
11.6.2 Global pin control........................................................................................................................................188
11.6.3 External interrupts........................................................................................................................................188
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................191
12.1.1 Features........................................................................................................................................................191
12.2 Memory map and register definition.............................................................................................................................191
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................193
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................194
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................195
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................197
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................199
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................200
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................202
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................204
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................206
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................207
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................209
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................210
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12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................211
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................213
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................213
12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................214
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................214
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................215
12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................216
12.3 Functional description...................................................................................................................................................216
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................217
13.2 Modes of operation.......................................................................................................................................................217
13.3 Memory map and register descriptions.........................................................................................................................219
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................219
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................221
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................222
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................223
13.4 Functional description...................................................................................................................................................224
13.4.1 Power mode transitions................................................................................................................................224
13.4.2 Power mode entry/exit sequencing..............................................................................................................227
13.4.3 Run modes....................................................................................................................................................229
13.4.4 Wait modes..................................................................................................................................................231
13.4.5 Stop modes...................................................................................................................................................232
13.4.6 Debug in low power modes.........................................................................................................................235
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................237
14.2 Features.........................................................................................................................................................................237
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14.3 Low-voltage detect (LVD) system................................................................................................................................237
14.3.1 LVD reset operation.....................................................................................................................................238
14.3.2 LVD interrupt operation...............................................................................................................................238
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................238
14.4 I/O retention..................................................................................................................................................................239
14.5 Memory map and register descriptions.........................................................................................................................239
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................240
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................241
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................242
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................245
15.1.1 Features........................................................................................................................................................245
15.1.2 Modes of operation......................................................................................................................................246
15.1.3 Block diagram..............................................................................................................................................247
15.2 LLWU signal descriptions............................................................................................................................................248
15.3 Memory map/register definition...................................................................................................................................248
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................249
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................250
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................251
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................252
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................253
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................255
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................257
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................258
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................260
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................261
15.4 Functional description...................................................................................................................................................262
15.4.1 LLS mode.....................................................................................................................................................263
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15.4.2 VLLS modes................................................................................................................................................263
15.4.3 Initialization.................................................................................................................................................263
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................265
16.2 Reset memory map and register descriptions...............................................................................................................265
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................265
16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................267
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................268
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................269
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................271
17.1.1 Overview......................................................................................................................................................272
17.1.2 Features........................................................................................................................................................272
17.1.3 Modes of Operation.....................................................................................................................................273
17.2 External Signal Description..........................................................................................................................................273
17.3 Memory Map and Register Definition..........................................................................................................................274
17.4 Functional Description..................................................................................................................................................274
17.4.1 BME Decorated Stores.................................................................................................................................274
17.4.2 BME Decorated Loads.................................................................................................................................280
17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................287
17.5 Application Information................................................................................................................................................288
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................291
18.1.1 Features........................................................................................................................................................291
18.2 Memory map/register descriptions...............................................................................................................................291
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................292
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................293
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18.2.3 Platform Control Register (MCM_PLACR)................................................................................................293
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................296
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................299
19.1.1 Overview......................................................................................................................................................299
19.1.2 Features........................................................................................................................................................302
19.1.3 Modes of Operation.....................................................................................................................................303
19.2 External Signal Description..........................................................................................................................................303
19.3 Memory Map and Register Definition..........................................................................................................................304
19.3.1 MTB_RAM Memory Map...........................................................................................................................304
19.3.2 MTB_DWT Memory Map...........................................................................................................................316
19.3.3 System ROM Memory Map.........................................................................................................................326
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................331
20.1.1 Features........................................................................................................................................................331
20.2 Memory Map / Register Definition...............................................................................................................................331
20.3 Functional Description..................................................................................................................................................332
20.3.1 General operation.........................................................................................................................................332
20.3.2 Arbitration....................................................................................................................................................333
20.4 Initialization/application information...........................................................................................................................334
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................335
21.1.1 Features........................................................................................................................................................335
21.1.2 General operation.........................................................................................................................................335
21.2 Functional description...................................................................................................................................................336
21.2.1 Access support.............................................................................................................................................336
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Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................337
22.1.1 Overview......................................................................................................................................................337
22.1.2 Features........................................................................................................................................................338
22.1.3 Modes of operation......................................................................................................................................338
22.2 External signal description............................................................................................................................................339
22.3 Memory map/register definition...................................................................................................................................339
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................339
22.4 Functional description...................................................................................................................................................340
22.4.1 DMA channels with periodic triggering capability......................................................................................341
22.4.2 DMA channels with no triggering capability...............................................................................................343
22.4.3 Always-enabled DMA sources....................................................................................................................343
22.5 Initialization/application information...........................................................................................................................344
22.5.1 Reset.............................................................................................................................................................344
22.5.2 Enabling and configuring sources................................................................................................................344
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................349
23.1.1 Overview......................................................................................................................................................349
23.1.2 Features........................................................................................................................................................350
23.2 DMA Transfer Overview..............................................................................................................................................351
23.3 Memory Map and Registers..........................................................................................................................................352
23.3.1 Source Address Register (DMA_SARn).....................................................................................................353
23.3.2 Destination Address Register (DMA_DARn).............................................................................................354
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................355
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................357
23.4 Functional Description..................................................................................................................................................361
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................361
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23.4.2 Channel Initialization and Startup................................................................................................................361
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................363
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................364
23.4.5 Termination..................................................................................................................................................365
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................367
24.1.1 Features........................................................................................................................................................367
24.1.2 Modes of Operation.....................................................................................................................................370
24.2 External Signal Description..........................................................................................................................................371
24.3 Memory Map/Register Definition.................................................................................................................................371
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................372
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................373
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................374
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................374
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................376
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................377
24.3.7 MCG Status Register (MCG_S)..................................................................................................................378
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................380
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................381
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................381
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................382
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................382
24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................383
24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................383
24.4 Functional Description..................................................................................................................................................384
24.4.1 MCG mode state diagram............................................................................................................................384
24.4.2 Low Power Bit Usage..................................................................................................................................388
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24.4.3 MCG Internal Reference Clocks..................................................................................................................388
24.4.4 External Reference Clock............................................................................................................................389
24.4.5 MCG Fixed frequency clock .......................................................................................................................389
24.4.6 MCG PLL clock ..........................................................................................................................................390
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................390
24.5 Initialization / Application information........................................................................................................................391
24.5.1 MCG module initialization sequence...........................................................................................................391
24.5.2 Using a 32.768 kHz reference......................................................................................................................393
24.5.3 MCG mode switching..................................................................................................................................394
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................405
25.2 Features and Modes......................................................................................................................................................405
25.3 Block Diagram..............................................................................................................................................................406
25.4 OSC Signal Descriptions..............................................................................................................................................406
25.5 External Crystal / Resonator Connections....................................................................................................................407
25.6 External Clock Connections.........................................................................................................................................408
25.7 Memory Map/Register Definitions...............................................................................................................................409
25.7.1 OSC Memory Map/Register Definition.......................................................................................................409
25.8 Functional Description..................................................................................................................................................410
25.8.1 OSC Module States......................................................................................................................................410
25.8.2 OSC Module Modes.....................................................................................................................................412
25.8.3 Counter.........................................................................................................................................................413
25.8.4 Reference Clock Pin Requirements.............................................................................................................413
25.9 Reset..............................................................................................................................................................................414
25.10 Low Power Modes Operation.......................................................................................................................................414
25.11 Interrupts.......................................................................................................................................................................414
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Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................415
26.1.1 Overview......................................................................................................................................................415
26.1.2 Features........................................................................................................................................................415
26.2 Modes of operation.......................................................................................................................................................416
26.3 External signal description............................................................................................................................................416
26.4 Memory map and register descriptions.........................................................................................................................416
26.5 Functional description...................................................................................................................................................416
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................419
27.1.1 Features........................................................................................................................................................420
27.1.2 Block Diagram.............................................................................................................................................420
27.1.3 Glossary.......................................................................................................................................................421
27.2 External Signal Description..........................................................................................................................................422
27.3 Memory Map and Registers..........................................................................................................................................422
27.3.1 Flash Configuration Field Description.........................................................................................................422
27.3.2 Program Flash IFR Map...............................................................................................................................423
27.3.3 Register Descriptions...................................................................................................................................424
27.4 Functional Description..................................................................................................................................................432
27.4.1 Flash Protection............................................................................................................................................433
27.4.2 Interrupts......................................................................................................................................................433
27.4.3 Flash Operation in Low-Power Modes........................................................................................................434
27.4.4 Functional Modes of Operation...................................................................................................................434
27.4.5 Flash Reads and Ignored Writes..................................................................................................................434
27.4.6 Read While Write (RWW)...........................................................................................................................435
27.4.7 Flash Program and Erase..............................................................................................................................435
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27.4.8 Flash Command Operations.........................................................................................................................435
27.4.9 Margin Read Commands.............................................................................................................................440
27.4.10 Flash Command Description........................................................................................................................441
27.4.11 Security........................................................................................................................................................454
27.4.12 Reset Sequence............................................................................................................................................456
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................457
28.1.1 Features........................................................................................................................................................457
28.1.2 Block diagram..............................................................................................................................................458
28.2 ADC Signal Descriptions..............................................................................................................................................459
28.2.1 Analog Power (VDDA)...............................................................................................................................460
28.2.2 Analog Ground (VSSA)...............................................................................................................................460
28.2.3 Voltage Reference Select.............................................................................................................................460
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................461
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................461
28.3 Register definition.........................................................................................................................................................461
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................462
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................465
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................467
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................468
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................469
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................470
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................472
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................474
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................474
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................475
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................475
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................476
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28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................476
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................477
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................477
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................478
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................478
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................479
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................479
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................480
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................480
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................481
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................481
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................482
28.4 Functional description...................................................................................................................................................482
28.4.1 Clock select and divide control....................................................................................................................483
28.4.2 Voltage reference selection..........................................................................................................................483
28.4.3 Hardware trigger and channel selects..........................................................................................................484
28.4.4 Conversion control.......................................................................................................................................485
28.4.5 Automatic compare function........................................................................................................................493
28.4.6 Calibration function.....................................................................................................................................494
28.4.7 User-defined offset function........................................................................................................................495
28.4.8 Temperature sensor......................................................................................................................................497
28.4.9 MCU wait mode operation...........................................................................................................................497
28.4.10 MCU Normal Stop mode operation.............................................................................................................498
28.4.11 MCU Low-Power Stop mode operation......................................................................................................499
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28.5 Initialization information..............................................................................................................................................499
28.5.1 ADC module initialization example............................................................................................................499
28.6 Application information................................................................................................................................................501
28.6.1 External pins and routing.............................................................................................................................501
28.6.2 Sources of error............................................................................................................................................503
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................509
29.2 CMP features................................................................................................................................................................509
29.3 6-bit DAC key features.................................................................................................................................................510
29.4 ANMUX key features...................................................................................................................................................511
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................511
29.6 CMP block diagram......................................................................................................................................................512
29.7 Memory map/register definitions..................................................................................................................................514
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................514
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................515
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................517
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................517
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................518
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................519
29.8 Functional description...................................................................................................................................................520
29.8.1 CMP functional modes.................................................................................................................................520
29.8.2 Power modes................................................................................................................................................529
29.8.3 Startup and operation...................................................................................................................................530
29.8.4 Low-pass filter.............................................................................................................................................531
29.9 CMP interrupts..............................................................................................................................................................533
29.10 DMA support................................................................................................................................................................533
29.11 CMP Asyncrhonous DMA support...............................................................................................................................534
29.12 Digital-to-analog converter...........................................................................................................................................534
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29.13 DAC functional description..........................................................................................................................................535
29.13.1 Voltage reference source select....................................................................................................................535
29.14 DAC resets....................................................................................................................................................................535
29.15 DAC clocks...................................................................................................................................................................535
29.16 DAC interrupts..............................................................................................................................................................536
29.17 CMP Trigger Mode.......................................................................................................................................................536
Chapter 30
12-bit Digital-to-Analog Converter (DAC)
30.1 Introduction...................................................................................................................................................................537
30.2 Features.........................................................................................................................................................................537
30.3 Block diagram...............................................................................................................................................................537
30.4 Memory map/register definition...................................................................................................................................539
30.4.1 DAC Data Low Register (DACx_DATnL).................................................................................................539
30.4.2 DAC Data High Register (DACx_DATnH)................................................................................................540
30.4.3 DAC Status Register (DACx_SR)...............................................................................................................540
30.4.4 DAC Control Register (DACx_C0).............................................................................................................541
30.4.5 DAC Control Register 1 (DACx_C1)..........................................................................................................542
30.4.6 DAC Control Register 2 (DACx_C2)..........................................................................................................542
30.5 Functional description...................................................................................................................................................543
30.5.1 DAC data buffer operation...........................................................................................................................543
30.5.2 DMA operation............................................................................................................................................544
30.5.3 Resets...........................................................................................................................................................544
30.5.4 Low-Power mode operation.........................................................................................................................544
Chapter 31
Timer/PWM Module (TPM)
31.1 Introduction...................................................................................................................................................................547
31.1.1 TPM Philosophy..........................................................................................................................................547
31.1.2 Features........................................................................................................................................................547
31.1.3 Modes of Operation.....................................................................................................................................548
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31.1.4 Block Diagram.............................................................................................................................................548
31.2 TPM Signal Descriptions..............................................................................................................................................549
31.2.1 TPM_EXTCLK — TPM External Clock....................................................................................................549
31.2.2 TPM_CHn — TPM Channel (n) I/O Pin.....................................................................................................550
31.3 Memory Map and Register Definition..........................................................................................................................550
31.3.1 Status and Control (TPMx_SC)...................................................................................................................552
31.3.2 Counter (TPMx_CNT).................................................................................................................................553
31.3.3 Modulo (TPMx_MOD)................................................................................................................................554
31.3.4 Channel (n) Status and Control (TPMx_CnSC)...........................................................................................555
31.3.5 Channel (n) Value (TPMx_CnV).................................................................................................................557
31.3.6 Capture and Compare Status (TPMx_STATUS).........................................................................................557
31.3.7 Configuration (TPMx_CONF).....................................................................................................................559
31.4 Functional Description..................................................................................................................................................561
31.4.1 Clock Domains.............................................................................................................................................561
31.4.2 Prescaler.......................................................................................................................................................562
31.4.3 Counter.........................................................................................................................................................562
31.4.4 Input Capture Mode.....................................................................................................................................564
31.4.5 Output Compare Mode.................................................................................................................................565
31.4.6 Edge-Aligned PWM (EPWM) Mode...........................................................................................................566
31.4.7 Center-Aligned PWM (CPWM) Mode........................................................................................................568
31.4.8 Registers Updated from Write Buffers........................................................................................................570
31.4.9 DMA............................................................................................................................................................570
31.4.10 Reset Overview............................................................................................................................................571
31.4.11 TPM Interrupts.............................................................................................................................................571
Chapter 32
Periodic Interrupt Timer (PIT)
32.1 Introduction...................................................................................................................................................................573
32.1.1 Block diagram..............................................................................................................................................573
32.1.2 Features........................................................................................................................................................574
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32.2 Signal description..........................................................................................................................................................574
32.3 Memory map/register description.................................................................................................................................575
32.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................575
32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)...............................................................................577
32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)...............................................................................577
32.3.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................578
32.3.5 Current Timer Value Register (PIT_CVALn).............................................................................................578
32.3.6 Timer Control Register (PIT_TCTRLn)......................................................................................................579
32.3.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................580
32.4 Functional description...................................................................................................................................................580
32.4.1 General operation.........................................................................................................................................580
32.4.2 Interrupts......................................................................................................................................................582
32.4.3 Chained timers.............................................................................................................................................582
32.5 Initialization and application information.....................................................................................................................582
32.6 Example configuration for chained timers....................................................................................................................583
32.7 Example configuration for the lifetime timer...............................................................................................................584
Chapter 33
Low-Power Timer (LPTMR)
33.1 Introduction...................................................................................................................................................................587
33.1.1 Features........................................................................................................................................................587
33.1.2 Modes of operation......................................................................................................................................587
33.2 LPTMR signal descriptions..........................................................................................................................................588
33.2.1 Detailed signal descriptions.........................................................................................................................588
33.3 Memory map and register definition.............................................................................................................................588
33.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................589
33.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................590
33.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................592
33.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................592
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33.4 Functional description...................................................................................................................................................593
33.4.1 LPTMR power and reset..............................................................................................................................593
33.4.2 LPTMR clocking..........................................................................................................................................593
33.4.3 LPTMR prescaler/glitch filter......................................................................................................................593
33.4.4 LPTMR compare..........................................................................................................................................595
33.4.5 LPTMR counter...........................................................................................................................................595
33.4.6 LPTMR hardware trigger.............................................................................................................................596
33.4.7 LPTMR interrupt..........................................................................................................................................596
Chapter 34
Real Time Clock (RTC)
34.1 Introduction...................................................................................................................................................................597
34.1.1 Features........................................................................................................................................................597
34.1.2 Modes of operation......................................................................................................................................597
34.1.3 RTC Signal Descriptions.............................................................................................................................597
34.2 Register definition.........................................................................................................................................................598
34.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................599
34.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................599
34.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................600
34.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................600
34.2.5 RTC Control Register (RTC_CR)................................................................................................................601
34.2.6 RTC Status Register (RTC_SR)..................................................................................................................603
34.2.7 RTC Lock Register (RTC_LR)....................................................................................................................604
34.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................605
34.3 Functional description...................................................................................................................................................606
34.3.1 Power, clocking, and reset...........................................................................................................................606
34.3.2 Time counter................................................................................................................................................607
34.3.3 Compensation...............................................................................................................................................607
34.3.4 Time alarm...................................................................................................................................................608
34.3.5 Update mode................................................................................................................................................608
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34.3.6 Register lock................................................................................................................................................609
34.3.7 Interrupt........................................................................................................................................................609
Chapter 35
Universal Serial Bus OTG Controller (USBOTG)
35.1 Introduction...................................................................................................................................................................611
35.1.1 USB..............................................................................................................................................................611
35.1.2 USB On-The-Go..........................................................................................................................................612
35.1.3 USB-FS Features..........................................................................................................................................613
35.2 Functional description...................................................................................................................................................613
35.2.1 Data Structures.............................................................................................................................................613
35.3 Programmers interface..................................................................................................................................................614
35.3.1 Buffer Descriptor Table...............................................................................................................................614
35.3.2 RX vs. TX as a USB target device or USB host..........................................................................................615
35.3.3 Addressing BDT entries...............................................................................................................................616
35.3.4 Buffer Descriptors (BDs).............................................................................................................................616
35.3.5 USB transaction...........................................................................................................................................619
35.4 Memory map/Register definitions................................................................................................................................621
35.4.1 Peripheral ID register (USBx_PERID)........................................................................................................623
35.4.2 Peripheral ID Complement register (USBx_IDCOMP)...............................................................................624
35.4.3 Peripheral Revision register (USBx_REV)..................................................................................................624
35.4.4 Peripheral Additional Info register (USBx_ADDINFO).............................................................................625
35.4.5 OTG Interrupt Status register (USBx_OTGISTAT)....................................................................................625
35.4.6 OTG Interrupt Control Register (USBx_OTGICR).....................................................................................626
35.4.7 OTG Status register (USBx_OTGSTAT)....................................................................................................627
35.4.8 OTG Control register (USBx_OTGCTL)....................................................................................................628
35.4.9 Interrupt Status register (USBx_ISTAT).....................................................................................................629
35.4.10 Interrupt Enable register (USBx_INTEN)...................................................................................................630
35.4.11 Error Interrupt Status register (USBx_ERRSTAT).....................................................................................631
35.4.12 Error Interrupt Enable register (USBx_ERREN).........................................................................................632
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35.4.13 Status register (USBx_STAT)......................................................................................................................633
35.4.14 Control register (USBx_CTL)......................................................................................................................634
35.4.15 Address register (USBx_ADDR).................................................................................................................635
35.4.16 BDT Page Register 1 (USBx_BDTPAGE1)................................................................................................636
35.4.17 Frame Number Register Low (USBx_FRMNUML)...................................................................................636
35.4.18 Frame Number Register High (USBx_FRMNUMH)..................................................................................637
35.4.19 Token register (USBx_TOKEN)..................................................................................................................637
35.4.20 SOF Threshold Register (USBx_SOFTHLD)..............................................................................................638
35.4.21 BDT Page Register 2 (USBx_BDTPAGE2)................................................................................................639
35.4.22 BDT Page Register 3 (USBx_BDTPAGE3)................................................................................................639
35.4.23 Endpoint Control register (USBx_ENDPTn)...............................................................................................639
35.4.24 USB Control register (USBx_USBCTRL)..................................................................................................640
35.4.25 USB OTG Observe register (USBx_OBSERVE)........................................................................................641
35.4.26 USB OTG Control register (USBx_CONTROL)........................................................................................642
35.4.27 USB Transceiver Control Register 0 (USBx_USBTRC0)...........................................................................642
35.4.28 Frame Adjust Register (USBx_USBFRMADJUST)...................................................................................643
35.5 OTG and Host mode operation.....................................................................................................................................644
35.6 Host Mode Operation Examples...................................................................................................................................644
35.7 On-The-Go operation....................................................................................................................................................647
35.7.1 OTG dual role A device operation...............................................................................................................648
35.7.2 OTG dual role B device operation...............................................................................................................649
Chapter 36
USB Voltage Regulator
36.1 Introduction...................................................................................................................................................................651
36.1.1 Overview......................................................................................................................................................651
36.1.2 Features........................................................................................................................................................652
36.1.3 Modes of Operation.....................................................................................................................................653
36.2 USB Voltage Regulator Module Signal Descriptions..................................................................................................653
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Chapter 37
Serial Peripheral Interface (SPI)
37.1 Introduction...................................................................................................................................................................655
37.1.1 Features........................................................................................................................................................655
37.1.2 Modes of Operation.....................................................................................................................................656
37.1.3 Block Diagrams............................................................................................................................................657
37.2 External Signal Description..........................................................................................................................................659
37.2.1 SPSCK — SPI Serial Clock.........................................................................................................................659
37.2.2 MOSI — Master Data Out, Slave Data In...................................................................................................660
37.2.3 MISO — Master Data In, Slave Data Out...................................................................................................660
37.2.4 SS — Slave Select........................................................................................................................................660
37.3 Memory Map and Register Descriptions......................................................................................................................661
37.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................661
37.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................663
37.3.3 SPI baud rate register (SPIx_BR).................................................................................................................664
37.3.4 SPI status register (SPIx_S).........................................................................................................................665
37.3.5 SPI data register (SPIx_D)...........................................................................................................................667
37.3.6 SPI match register (SPIx_M).......................................................................................................................668
37.4 Functional Description..................................................................................................................................................668
37.4.1 General.........................................................................................................................................................668
37.4.2 Master Mode................................................................................................................................................669
37.4.3 Slave Mode..................................................................................................................................................670
37.4.4 SPI Transmission by DMA..........................................................................................................................671
37.4.5 SPI Clock Formats.......................................................................................................................................673
37.4.6 SPI Baud Rate Generation...........................................................................................................................676
37.4.7 Special Features...........................................................................................................................................677
37.4.8 Error Conditions...........................................................................................................................................678
37.4.9 Low Power Mode Options...........................................................................................................................679
37.4.10 Reset.............................................................................................................................................................681
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37.4.11 Interrupts......................................................................................................................................................681
37.5 Initialization/Application Information..........................................................................................................................683
37.5.1 Initialization Sequence.................................................................................................................................683
37.5.2 Pseudo-Code Example.................................................................................................................................684
Chapter 38
Inter-Integrated Circuit (I2C)
38.1 Introduction...................................................................................................................................................................687
38.1.1 Features........................................................................................................................................................687
38.1.2 Modes of operation......................................................................................................................................688
38.1.3 Block diagram..............................................................................................................................................688
38.2 I2C signal descriptions..................................................................................................................................................689
38.3 Memory map and register descriptions.........................................................................................................................689
38.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................690
38.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................691
38.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................692
38.3.4 I2C Status register (I2Cx_S)........................................................................................................................694
38.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................695
38.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................696
38.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................697
38.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................698
38.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................699
38.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................701
38.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................701
38.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................701
38.4 Functional description...................................................................................................................................................702
38.4.1 I2C protocol.................................................................................................................................................702
38.4.2 10-bit address...............................................................................................................................................707
38.4.3 Address matching.........................................................................................................................................709
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38.4.4 System management bus specification........................................................................................................709
38.4.5 Resets...........................................................................................................................................................712
38.4.6 Interrupts......................................................................................................................................................712
38.4.7 Programmable input glitch filter..................................................................................................................714
38.4.8 Address matching wakeup...........................................................................................................................715
38.4.9 DMA support...............................................................................................................................................715
38.5 Initialization/application information...........................................................................................................................716
Chapter 39
Universal Asynchronous Receiver/Transmitter (UART0)
39.1 Introduction...................................................................................................................................................................721
39.1.1 Features........................................................................................................................................................721
39.1.2 Modes of operation......................................................................................................................................722
39.1.3 Block diagram..............................................................................................................................................722
39.2 Register definition.........................................................................................................................................................724
39.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................725
39.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................726
39.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................726
39.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................728
39.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................729
39.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................731
39.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................733
39.2.8 UART Data Register (UARTx_D)...............................................................................................................734
39.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................735
39.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................736
39.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................736
39.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................737
39.3 Functional description...................................................................................................................................................738
39.3.1 Baud rate generation....................................................................................................................................738
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39.3.2 Transmitter functional description...............................................................................................................738
39.3.3 Receiver functional description...................................................................................................................740
39.3.4 Additional UART functions.........................................................................................................................743
39.3.5 Interrupts and status flags............................................................................................................................745
Chapter 40
Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
40.1 Introduction...................................................................................................................................................................747
40.1.1 Features........................................................................................................................................................747
40.1.2 Modes of operation......................................................................................................................................747
40.1.3 Block diagram..............................................................................................................................................748
40.2 Register definition.........................................................................................................................................................750
40.2.1 UART Baud Rate Register: High (UARTx_BDH)......................................................................................751
40.2.2 UART Baud Rate Register: Low (UARTx_BDL).......................................................................................751
40.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................752
40.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................753
40.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................755
40.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................756
40.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................758
40.2.8 UART Data Register (UARTx_D)...............................................................................................................760
40.2.9 UART Control Register 4 (UARTx_C4).....................................................................................................760
40.3 Functional description...................................................................................................................................................761
40.3.1 Baud rate generation....................................................................................................................................761
40.3.2 Transmitter functional description...............................................................................................................762
40.3.3 Receiver functional description...................................................................................................................764
40.3.4 Interrupts and status flags............................................................................................................................767
40.3.5 DMA Operation...........................................................................................................................................768
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40.3.6 Additional UART functions.........................................................................................................................769
Chapter 41
General-Purpose Input/Output (GPIO)
41.1 Introduction...................................................................................................................................................................771
41.1.1 Features........................................................................................................................................................771
41.1.2 Modes of operation......................................................................................................................................771
41.1.3 GPIO signal descriptions.............................................................................................................................772
41.2 Memory map and register definition.............................................................................................................................773
41.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................775
41.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................776
41.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................776
41.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................777
41.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................777
41.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................778
41.3 FGPIO memory map and register definition................................................................................................................778
41.3.1 Port Data Output Register (FGPIOx_PDOR)..............................................................................................780
41.3.2 Port Set Output Register (FGPIOx_PSOR).................................................................................................781
41.3.3 Port Clear Output Register (FGPIOx_PCOR).............................................................................................781
41.3.4 Port Toggle Output Register (FGPIOx_PTOR)...........................................................................................782
41.3.5 Port Data Input Register (FGPIOx_PDIR)...................................................................................................782
41.3.6 Port Data Direction Register (FGPIOx_PDDR)..........................................................................................783
41.4 Functional description...................................................................................................................................................783
41.4.1 General-purpose input..................................................................................................................................783
41.4.2 General-purpose output................................................................................................................................783
41.4.3 IOPORT.......................................................................................................................................................784
Chapter 42
Touch Sensing Input (TSI)
42.1 Introduction...................................................................................................................................................................785
42.1.1 Features........................................................................................................................................................785
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42.1.2 Modes of operation......................................................................................................................................785
42.1.3 Block diagram..............................................................................................................................................786
42.2 External signal description............................................................................................................................................787
42.2.1 TSI[15:0]......................................................................................................................................................787
42.3 Register definition.........................................................................................................................................................787
42.3.1 TSI General Control and Status Register (TSIx_GENCS)..........................................................................787
42.3.2 TSI DATA Register (TSIx_DATA).............................................................................................................792
42.3.3 TSI Threshold Register (TSIx_TSHD)........................................................................................................793
42.4 Functional description...................................................................................................................................................793
42.4.1 Capacitance measurement............................................................................................................................794
42.4.2 TSI measurement result...............................................................................................................................797
42.4.3 Enable TSI module.......................................................................................................................................797
42.4.4 Software and hardware trigger.....................................................................................................................797
42.4.5 Scan times....................................................................................................................................................798
42.4.6 Clock setting................................................................................................................................................798
42.4.7 Reference voltage.........................................................................................................................................798
42.4.8 Current source..............................................................................................................................................799
42.4.9 End of scan...................................................................................................................................................799
42.4.10 Out-of-range interrupt..................................................................................................................................799
42.4.11 Wake up MCU from low power modes.......................................................................................................800
42.4.12 DMA function support.................................................................................................................................800
42.4.13 Noise detection mode...................................................................................................................................800
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Chapter 1 About This Document
1.1

Overview

1.1.1 Purpose

This document describes the features, architecture, and programming model of the Freescale KL25 microcontroller.

1.1.2 Audience

This document is primarily for system architects and software application developers who are using or considering using the KL25 microcontroller in a system.
1.2

Conventions

1.2.1 Numbering systems

The following suffixes identify different numbering systems:
This suffix Identifies a
b Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x.
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Conventions

1.2.2 Typographic notation

The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
code
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
Scaling Mode (SCM) field in the Status Register (SR).
• A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.2.3 Special terms

The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the module or chip behavior is unpredictable.
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Chapter 2 Introduction

2.1 Overview

This chapter provides an overview of the Kinetis L series of ARM® Cortex™-M0+ MCUs and KL25 product family. It also presents high-level descriptions of the modules available on the devices covered by this document.

2.2 Kinetis L Series

The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal ARM Cortex-M0+ MCUs in the industry. The portfolio includes 5 MCU families that offer a broad range of memory, peripheral and package options. Kinetis L Series families share common peripherals and pin-counts allowing developers to migrate easily within an MCU family or between MCU families to take advantage of more memory or feature integration. This scalability allows developers to standardize on the Kinetis L Series for their end product platforms, maximising hardware and software reuse and reducing time­to-market.
Features common to all Kinetis L series families include:
• 48 MHz ARM Cortex-M0+ core
• High-speed 12/16-bit analog-to-digital converters
• 12-bit digital-to-analog converters for all series except for KLx4/KLx2 family
• High-speed analog comparators
• Low-power touch sensing with wake-up on touch from reduced power states for all series except for KLx4 family
• Powerful timers for a broad range of applications including motor control
• Low power focused serial communication interfaces such as low power UART, SPI, I2C etc.
• Single power supply: 1.71V - 3.6V with multiple low-power modes support single operation temperature: -40 ~ 105 °C (exclude CSP package)
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Page 36
KL2x Family
KL1x Family
KL0x Family
KL3x Family
Family
Program
Flash
Packages Key Features
Low power Mixed signal USB Segment LCD
KL4x Family
8-32KB
32-256KB
32-256KB
64-256KB
128-256KB
16-48pin
32-80pin
32-121pin
64-121pin
64-121pin
Kinetis L Series
Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and human­machine interface peripherals. Each MCU family is supported by a market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners. The KL0x family is the entry-point to the Kinetis L series and is pin compatible with the 8-bit S08PT family. The KL1x/2x/3x/4x families are compatible with each other and their equivalent ARM Cortex-M4 Kinetis K series families - K10/20/30/40.
All Kinetis L series families include a powerful array of analog, communication and timing and control peripherals with the level of feature integration increasing with flash memory size and the pin count. Features within the Kinetis L series families include:
Figure 2-1. Kinetis L series families of MCU portfolio
• Core and Architecture:
• ARM Cortex-M0+ Core running up to 48 MHz with zero wait state execution from memories
• Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to external events allowing bit banging and software protocol emulation
• Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction and ISR entry, and reducing power consumption
• Excellent code density vs. 8-bit and 16-bit MCUs - reduces flash size, system cost and power consumption
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Chapter 2 Introduction
• Optimized access to program memory: Accesses on alternate cycles reduces power consumption
• 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex­M3/M4: Reuse existing compilers and debug tools
• Simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging of 8/16/32-bit data in memory
• Linear 4 GB address space removes the need for paging/banking, reducing software complexity
• ARM third-party ecosystem support: Software and tools to help minimize development time/cost
• Micro Trace Buffer: Lightweight trace solution allows fast bug identification and correction
• BME: Bit manipulation engine reduces code size and cycles for bit oriented operations to peripheral registers eliminating traditional methods where the core would need to perform read-modify-write operations.
• Up to 4-channel DMA for peripheral and memory servicing with minimal CPU intervention (feature not available on KL02 family)
• Ultra low-power:
• Extreme dynamic efficiency: 32-bit ARM Cortex-M0+ core combined with Freescale 90 nm thin film storage flash technology delivers 50% energy savings per Coremark versus the closest 8/16-bit competitive solution
• Multiple flexible low-power modes, including new operation clocking option which reduces dynamic power by shutting off bus and system clocks for lowest power core processing. Peripherals with an alternate asynchronous clock source can continue operation.
• UART, SPI, I2C, ADC, DAC, TPM, LPT, and DMA support low-power mode operation without waking up the core
• Memory:
• Scalable memory footprints from 8 KB flash / 1 KB SRAM to 256 KB flash / 32 KB SRAM
• Embedded 64 B cache memory for optimizing bus bandwidth and flash execution performance (32 B cache on KL02 family)
• Mixed-signal analog:
• Fast, high precision 16-, or 12-bit ADC with optional differential pairs, 12-bit DAC, high speed comparators. Powerful signal conditioning, conversion and analysis capability with reduced system cost (12-bit DAC not available on KL02 family)
• Human Machine Interface (HMI):
• Optional capacitive Touch Sensing Interface with full low-power support and minimal current adder when enabled
• Segment LCD controller
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Page 38

KL25 Sub-Family Introduction

• Connectivity and Communications:
• Up to three UARTs, all UARTs support DMA transfers, and can trigger when data on bus is detected, UART0 supports 4x to 32x over sampling ratio. Asynchronous transmit and receive operation for operating in STOP/VLPS modes.
• Up to two SPIs
• Up to two I2Cs
• Full-speed USB OTG controller with on-chip transceiver
• 5 V to 3.3 V USB on-chip regulator
• One I2S
• Reliability, Safety and Security:
• Internal watchdog with independent clock source
• Timing and Control:
• Powerful timer modules which support general purpose, PWM, and motor control functions
• Periodic Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and timer modules
• System:
• GPIO with pin interrupt functionality
• Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully functional flash and analog peripherals
• Ambient operating temperature ranges from -40 °C to 105 °C
2.3 KL25 Sub-Family Introduction
The device is highly-integrated, market leading ultra low power 32-bit microcontroller based on the enhanced Cortex-M0+ (CM0+) core platform. The family derivatives feature:
• Core platform clock up to 48 MHz, bus clock up to 24 MHz
• Memory option is up to 128 KB Flash and 16 KB RAM
• Wide operating voltage ranges from 1.71V to 3.6V with full functional Flash program/erase/read operations
• Multiple package options from 32-pin to 80-pin
• Ambient operating temperature ranges from –40 °C to 105 °C
The family acts as an ultra low power, cost effective microcontroller to provide developers an appropriate entry-level 32-bit solution. The family is next generation MCU solution for low cost, low power, high performance devices applications. It’s valuable for cost-sensitive, portable applications requiring long battery life-time.
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Chapter 2 Introduction

2.4 Module functional categories

The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail.
Table 2-1. Module functional categories
Module category Description
ARM Cortex-M0+ core • 32-bit MCU core from ARM’s Cortex-M class, 1.77 CoreMark®/MHz from
single-cycle access memories, 48 MHz CPU frequency
System • System integration module
• Power management and mode controllers
• Multiple power modes available based on run, wait, stop, and power­down modes
• Miscellaneous control module
• Low-leakage wakeup unit
• Peripheral bridge
• Direct memory access (DMA) controller with multiplexer to increase available DMA requests
• COP watchdog
Memories • Internal memories include:
• Up to 128 KB flash memory
• up to 16 KB SRAM
Clocks • Multiple clock generation options available from internally- and externally-
generated clocks
• MCG module with FLL and PLL for systems and CPU clock sources
• Low power 1 kHz RC oscillator for RTC and COP watchdog
• System oscillator to provide clock source for the MCU
Security • COP watchdog timer (COP) Analog • 16-bit analog-to-digital converters with DMA supported and four muxed
differential pairs
• Comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)
• 12-bit DAC with DMA support and two 16-bit data buffer
Timers • One 6-channel TPM
• Two 2-channel TPMs
• 2-channel periodic interrupt timer
• Real time clock
• Low-power timer
• System tick timer
Communications • Two 8-bit serial peripheral interface
• USB OTG controller with built-in FS/LS transceiver
• USB voltage regulator
• Two inter-integrated circuit (I2C) modules
• One low power UART module and two UART modules
Human-Machine Interfaces (HMI) • General purpose input/output controller
• Capacitive touch sense input interface enabled in hardware
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Module functional categories
2.4.1 ARM® Cortex™-M0+ Core Modules
The following core modules are available on this device.
Table 2-2. Core modules
Module Description
ARM® Cortex™-M0+ The ARM® Cortex™-M0+ is the newest member of the Cortex M Series of
processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M0+ processor is based on the ARMv6 Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.
NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing.
Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port.
Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. One
debug interface is supported:
• Serial Wire Debug (SWD)

2.4.2 System Modules

The following system modules are available on this device.
Table 2-3. System modules
Module Description
System integration module (SIM) The SIM includes integration logic and several module configuration settings. System mode controller The SMC provides control and protection on entry and exit to each power mode,
control for the Power management controller (PMC), and reset entry and exit for the complete MCU.
Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Miscellaneous control module (MCM) The MCM includes integration logic and details.
Table continues on the next page...
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Chapter 2 Introduction
Table 2-3. System modules (continued)
Module Description
Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access
different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave.
Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS
and VLLS) through various internal peripheral and external pin sources.
Peripheral bridge The peripheral bridge converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 4 for the DMA
controller.
Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control
descriptors for data movement via dual-address transfers for 8-, 16- and 32-bit data values.
Computer operating properly watchdog (WDOG)
The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 kHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency.

2.4.3 Memories and Memory Interfaces

The following memories and memory interfaces are available on this device.
Table 2-4. Memories and memory interfaces
Module Description
Flash memory Program flash memory — up to 128 KB of the non-volatile flash memory that can
execute program code
Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Up to 16 KB internal system RAM.

2.4.4 Clocks

The following clock modules are available on this device.
Table 2-5. Clock modules
Module Description
Multipurpose Clock Generator (MCG) MCG module containing a frequency-locked-loop (FLL) and phase-locked-loop
(PLL) controlled by internal or external reference oscillator.
System oscillator The system oscillator, in conjunction with an external crystal or resonator,
generates a reference clock for the MCU.
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Module functional categories

2.4.5 Security and Integrity modules

The following security and integrity modules are available on this device:
Table 2-6. Security and integrity modules
Module Description
Watchdog Timer (WDOG) Watchdog Timer keeps a watch on the system functioning and resets it in case of
its failure.

2.4.6 Analog modules

The following analog modules are available on this device:
Table 2-7. Analog modules
Module Description
Analog-to-digital converters (ADC) 16-bit successive-approximation ADC module. Analog comparators One comparator that compares two analog input voltages across the full range of
the supply voltage and can trigger an ADC acquisition, TPM update, or CPU
interrupt.
6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for
comparator.
12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin
or set as one of the inputs to the analog comparator or ADC.

2.4.7 Timer modules

The following timer modules are available on this device:
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Page 43
Table 2-8. Timer modules
Module Description
Timer/PWM module (TPM) • Selectable TPM clock mode
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running counter or modulo counter with counting be up or up­down
• Six configurable channels for input capture, output compare, or edge-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel
• Support the generation of an interrupt and/or DMA request when the counter overflows
• Support selectable trigger input to optionally reset or cause the counter to start incrementing.
• Support the generation of hardware triggers when the counter overflows and per channel
Periodic interrupt timers (PIT) • One general purpose interrupt timer
• Interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
• DMA support
Low power timer (LPTMR) • 16-bit time counter or pulse counter with compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
Real-time counter (RTC) • 16-bit up-counter
• 16-bit modulo match limit
• Software controllable periodic interrupt on match
• Software selectable clock sources for input to prescaler with programmable 16-bit prescaler
• XOSC 32.678 kHz nominal
• LPO (~1 kHz)
• External RTC_CLKIN
Chapter 2 Introduction

2.4.8 Communication interfaces

The following communication interfaces are available on this device:
Table 2-9. Communication modules
Module Description
USB OTG (low-/full-speed) USB 2.0 compliant module with support for host, device, and On-The-Go modes.
Includes an on-chip transceiver for full and low speeds.
USB voltage regulator Up to 5 V regulator input typically provided by USB VBUS power with 3.3 V
regulated output that powers on-chip USB subsystem, capable of sourcing 120 mA
to external board components.
Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System
Management Bus (SMBus) Specification, version 2.
Universal asynchronous receiver/ transmitters (UART)
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One low power UART module that retains functional in stop modes. Two UART
modules.
Page 44

Orderable part numbers

2.4.9 Human-machine interfaces

The following human-machine interfaces (HMI) are available on this device:
Table 2-10. HMI modules
Module Description
General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt and
DMA request generation.
Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications.
Operation is available in low-power modes via interrupts.
2.5 Orderable part numbers
The following table summarizes the part numbers of the devices covered by this document.
Table 2-11. Orderable part numbers summary
Freescale part number CPU
frequency
MKL25Z32VFM4 48 MHz 32 QFN 32 KB 4 KB -40 to 105 °C MKL25Z64VFM4 48 MHz 32 QFN 64 KB 8 KB -40 to 105 °C
MKL25Z128VFM4 48 MHz 32 QFN 128 KB 16 KB -40 to 105 °C
MKL25Z32VFT4 48 MHz 48 QFN 32 KB 4 KB -40 to 105 °C MKL25Z64VFT4 48 MHz 48 QFN 64 KB 8 KB -40 to 105 °C
MKL25Z128VFT4 48 MHz 48 QFN 128 KB 16 KB -40 to 105 °C
MKL25Z32VLH4 48 MHz 64 LQFP 32 KB 4 KB -40 to 105 °C MKL25Z64VLH4 48 MHz 64 LQFP 64 KB 8 KB -40 to 105 °C
MKL25Z128VLH4 48 MHz 64 LQFP 128 KB 16 KB -40 to 105 °C
MKL25Z32VLK4 48 MHz 80 LQFP 32 KB 4 KB -40 to 105 °C MKL25Z64VLK4 48 MHz 80 LQFP 64 KB 8 KB -40 to 105 °C
MKL25Z128VLK4 48 MHz 80 LQFP 128 KB 16 KB -40 to 105 °C
Pin count Package Total flash
memory
RAM Temperature range
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Chapter 3 Chip Configuration

3.1 Introduction

This chapter provides details on the individual modules of the microcontroller. It includes:
• Module block diagrams showing immediate connections within the device
• Specific module-to-module interactions not necessarily discussed in the individual module chapters
• Links for more information
3.2

Module to Module Interconnects

3.2.1 Module to Module Interconnects

The below table captures the Module to module interconnections for this device.
Table 3-1. Module to Module Interconnects
Peripheral Signal — to Peripheral Use Case Control Comment
TPM1 CH0F, CH1F to ADC (Trigger) ADC Triggering
(A AND B)
Table continues on the next page...
SOPT7_ADCAL
TTRGEN = 0
Ch0 is A, and
Ch1 is B,
selecting this
ADC trigger is
for supporting A
and B triggering.
In Stop and
VLPS modes,
the second
trigger must be
set to >10us after the first
trigger
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Module to Module Interconnects
Table 3-1. Module to Module Interconnects (continued)
Peripheral Signal — to Peripheral Use Case Control Comment
LPTMR Hardware trigger to ADC (Trigger) ADC Triggering
(A or B)
TPMx TOF to ADC (Trigger) ADC Triggering
(A or B)
PIT CHx TIF0, TIF1 to ADC (Trigger) ADC Triggering
(A or B)
RTC ALARM or
SECONDS
EXTRG_IN EXTRG_IN to ADC (Trigger) ADC Triggering
CMP0 CMP0_OUT to ADC (Trigger) ADC Triggering
CMP0 CMP0_OUT to LPTMR_ALT0 Count CMP
CMP0 CMP0_OUT to TPM1 CH0 Input capture SOPT4_TPM1C
CMP0 CMP0_OUT to TPM2 CH0 Input capture SOPT4_TPM2C
CMP0 CMP0_OUT to UART0_RX IR interface SOPT5_UART0
CMP0 CMP0_OUT to UART1_RX IR Interface SOPT5_UART1
LPTMR Hardware trigger to CMPx Low power
to ADC (Trigger) ADC Triggering
(A or B)
(A or B)
(Aor B)
events
triggering of the
comparator
SOPT7_ADC0T
RGSEL (4 bit
field), ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field),
SOPT7_ADC0P
RETRGSEL to
select A or B
SOPT7_ADC0T
RGSEL (4 bit
field), ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field) ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field) ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field) ADC0PRETRG SEL to select A
or B
LPTMR_CSR[T
PS]
H0SRC
H0SRC
RXSRC
SRC
CMP_CR1[TRIG
M]
—
—
—
—
—
—
—
—
—
—
—
—
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-1. Module to Module Interconnects (continued)
Peripheral Signal — to Peripheral Use Case Control Comment
LPTMR Hardware trigger to TPMx TPM Trigger
input
TPMx TOF to TPMx TPM Trigger
input
TPM1 Timebase to TPMx TPM Global
timebase input
PIT CHx TIF0, TIF1 to TPMx TPM Trigger
input
RTC ALARM or
SECONDS
EXTRG_IN EXTRG_IN to TPMx TPM Trigger
CMP0 CMP0_OUT to TPMx TPM Trigger
LPTMR Hardware trigger to TSI TSI triggering TSI selects HW
UART0 UART0_TX to Modulated by
UART0 UART0_TX to Modulated by
UART1 UART1_TX to Modulated by
UART1 UART1_TX to Modulated by
PIT TIF0 to DAC Advance DAC
PIT TIF0 to DMA CH0 DMA HW
PIT TIF1 to DMA CH1 DMA HW
to TPMx TPM Trigger
input
input
input
UART
TPM1 CH0
TPM2 CH0
TPM1 CH0
TPM2 CH0
modulation
UART
modulation
UART
modulation
UART
modulation
FIFO
Trigger
Trigger
TPMx_CONF[T
RGSEL] (4 bit
field) TPMx_CONF[T
RGSEL] (4 bit
field)
TPMx_CONF[G
TBEEN]
TPMx_CONF[T
RGSEL] (4 bit
field)
TPMx_CONF[T
RGSEL] (4 bit
field) TPMx_CONF[T
RGSEL] (4 bit
field) TPMx_CONF[T
RGSEL] (4 bit
field)
trigger
SOPT5_UART0
TXSRC
SOPT5_UART0
TXSRC
SOPT5_UART1
TXSRC
SOPT5_UART1
TXSRC
DAC HWTRG
Select
DMA MUX
register option
DMA MUX
register option
—
—
—
If PIT is
triggering the
TPM, the TPM
clock must be
faster than Bus
clock.
—
—
—
—
—
—
—
—
—
—
—
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Page 48

Core Modules

3.2.2 Analog reference options

Several analog blocks have selectable reference voltages as shown in the below table. These options allow analog peripherals to share or have separate analog references. Care should be taken when selecting analog references to avoid cross talk noise.
Table 3-2. Analog reference options
Module Reference option Comment/ Reference selection
16-bit SAR ADC 1 - VREFH
2 - VDDA
3 - Reserved
12-bit DAC 1 - VREFH
2 - VDDA
CMP with 6-bit DAC Vin1 - VREFH
Vin2 - VDD
1
1
Selected by ADCx_SC2[REFSEL] bits
Selected by DACx_C0[DACRFS] bit
Selected by CMPx_DACCR[VRSEL] bit
1. Use this option for the best ADC operation.
3.3
Core Modules

3.3.1 ARM Cortex-M0+ Core Configuration

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com.
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ARM Cortex-M0+
Core
Debug Interrupts
Crossbar
switch
Chapter 3 Chip Configuration
Figure 3-1. Core configuration
Table 3-3. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M0+ core,
r0p0
System memory map System memory map
Clocking Clock distribution
Power management Power management
System/instruction/data
bus module
Debug Serial Wire Debug
Interrupts Nested Vectored
Crossbar switch Crossbar switch
(SWD)
Interrupt Controller
(NVIC)
Miscellaneous Control
Module (MCM)
ARM Cortex-M0+ Technical Reference Manual, r0p0
Debug
NVIC
MCM
3.3.1.1 ARM Cortex M0+ Core
The ARM Cortex M0+ parameter settings are as follows:
Table 3-4. Table 3. ARM Cortex-M0+ parameter settings
Parameter Verilog Name Value Description
Arch Clock Gating ACG 1 = Present Implements architectural clock
gating
DAP Slave Port Support AHBSLV 1 Support any AHB debug
access port (like the CM4
DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM
Table continues on the next page...
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
DAP)
table
Page 50
Core Modules
Table 3-4. Table 3. ARM Cortex-M0+ parameter settings (continued)
Parameter Verilog Name Value Description
Endianess BE 0 Little endian control for data
transfers
Breakpoints BKPT 2 Implements 2 breakpoints
Debug Support DBG 1 = Present
Halt Event Support HALTEV 1 = Present
I/O Port IOP 1 = Present Implements single-cycle ld/st
accesses to special addr
space
IRQ Mask Enable IRQDIS 0x00000000 Assume (for now) all 32 IRQs
are used (set if IRQ is
disabled)
Debug Port Protocol JTAGnSW 0 = SWD SWD protocol, not JTAG
Core Memory Protection MPU 0 = Absent No MPU
Number of IRQs NUMIRQ 32 Assume full NVIC request
vector
Reset all regs RAR 0 = Standard Do not force all registers to be
async reset
Multiplier SMUL 0 = Fast Mul Implements single-cycle
multiplier
Multi-drop Support SWMD 0 = Absent Do not include serial wire
support for multi-drop
System Tick Timer SYST 1 = Present Implements system tick timer
(for CM4 compatibility) DAP Target ID TARGETID 0 User/Privileged USER 1 = Present Implements processor
operating modes
Vector Table Offset Register VTOR 1 = Present Implements relocation of
exception vector table
WIC Support WIC 1 = Present Implements WIC interface
WIC Requests WICLINES 34 Exact number of wakeup
IRQs is 34
Watchpoints WPT 2 Implements 2 watchpoints
For details on the ARM Cortex-M0+ processor core see the ARM website: arm.com.
3.3.1.2 Buses, Interconnects, and Interfaces
The ARM Cortex-M0+ core has two bus interfaces:
• single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash and RAM.
• single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores.
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Page 51
Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+
core
Interrupts
Module
Module
Module
PPB
Chapter 3 Chip Configuration
3.3.1.3 System Tick Timer
The CLKSOURCE bit in SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero.
3.3.1.4 Debug Facilities
This device supports standard ARM 2-pin SWD debug port.
3.3.1.5 Core Privilege Levels
The Core on this device is implemented with both Privileged and Unprivileged levels. The ARM documentation uses different terms than this document to distinguish between privilege levels.
If you see this term... it also means this term...
Privileged Supervisor Unprivileged or user User

3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com.
Figure 3-2. NVIC configuration
Table 3-5. Reference links to related information
Topic Related module Reference
Full description Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+ Technical Reference Manual
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Table continues on the next page...
Page 52
Core Modules
Table 3-5. Reference links to related information (continued)
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
3.3.2.1 Interrupt priority levels
This device supports 4 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 2 bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W
IRQ3
0 0 0 0 0 0
IRQ2
0 0 0 0 0 0
IRQ1
0 0 0 0 0 0
IRQ0
0 0 0 0 0 0
3.3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request.
3.3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
Table 3-7. Interrupt vector assignments
Address Vector IRQ
ARM Core System Handler Vectors
1
NVIC
IPR
register
number
Source module Source description
2
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-7. Interrupt vector assignments (continued)
Address Vector IRQ
0x0000_0000 0 — — ARM core Initial Stack Pointer 0x0000_0004 1 — — ARM core Initial Program Counter 0x0000_0008 2 — — ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 — — ARM core Hard Fault 0x0000_0010 4 — — — — 0x0000_0014 5 — — — — 0x0000_0018 6 — — — — 0x0000_001C 7 — — — — 0x0000_0020 8 — — — — 0x0000_0024 9 — — — — 0x0000_0028 10 — — — — 0x0000_002C 11 — — ARM core Supervisor call (SVCall) 0x0000_0030 12 — — — — 0x0000_0034 13 — — — — 0x0000_0038 14 — — ARM core Pendable request for system service
0x0000_003C 15 — — ARM core System tick timer (SysTick)
Non-Core Vectors
0x0000_0040 16 0 0 DMA DMA channel 0 transfer complete and error 0x0000_0044 17 1 0 DMA DMA channel 1 transfer complete and error 0x0000_0048 18 2 0 DMA DMA channel 2 transfer complete and error 0x0000_004C 19 3 0 DMA DMA channel 3 transfer complete and error 0x0000_0050 20 4 1 — — 0x0000_0054 21 5 1 FTFA Command complete and read collision 0x0000_0058 22 6 1 PMC Low-voltage detect, low-voltage warning 0x0000_005C 23 7 1 LLWU Low Leakage Wakeup 0x0000_0060 24 8 2 I2C0 0x0000_0064 25 9 2 I2C1 0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources 0x0000_006C 27 11 2 SPI1 Single interrupt vector for all sources 0x0000_0070 28 12 3 UART0 Status and error 0x0000_0074 29 13 3 UART1 Status and error 0x0000_0078 30 14 3 UART2 Status and error 0x0000_007C 31 15 3 ADC0 0x0000_0080 32 16 4 CMP0 0x0000_0084 33 17 4 TPM0 0x0000_0088 34 18 4 TPM1 0x0000_008C 35 19 4 TPM2
1
NVIC
IPR
register
number
Source module Source description
2
(PendableSrvReq)
Table continues on the next page...
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Page 54
Core Modules
Table 3-7. Interrupt vector assignments (continued)
Address Vector IRQ
0x0000_0090 36 20 5 RTC Alarm interrupt 0x0000_0094 37 21 5 RTC Seconds interrupt 0x0000_0098 38 22 5 PIT Single interrupt vector for all channels 0x0000_009C 39 23 5 — — 0x0000_00A0 40 24 6 USB OTG 0x0000_00A4 41 25 6 DAC0 0x0000_00A8 42 26 6 TSI0 0x0000_00AC 43 27 6 MCG 0x0000_00B0 44 28 7 LPTMR0 0x0000_00B4 45 29 7 — 0x0000_00B8 46 30 7 Port control module Pin detect (Port A) 0x0000_00BC 47 31 7 Port control module Pin detect ( Port D )
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
1
NVIC
IPR
register
number
Source module Source description
2
3.3.2.3.1 Determining the bitfield and register location for configuring a particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the SPI0 row from Interrupt priority levels.
Table 3-8. Interrupt vector assignments
Address Vector IRQ
0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.
1
NVIC IPR
register
number
Source module Source description
2
• The NVIC registers you would use to configure the interrupt are:
• NVICIPR2
• To determine the particular IRQ's bitfield location within these particular registers:
• NVICIPR2 bitfield starting location = 8 * (IRQ mod 4) + 6 = 22
Since the NVICIPR bitfields are 2-bit wide (4 priority levels), the NVICIPR2 bitfield range is 22-23
Therefore, the following bitfield locations are used to configure the SPI0 interrupts:
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Page 55
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Chapter 3 Chip Configuration
• NVICIPR2[23:22]
3.3.3 Asynchronous wake-up interrupt controller (AWIC)
configuration
This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com.
Figure 3-3. Asynchronous wake-up interrupt controller configuration
Table 3-9. Reference links to related information
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Nested vectored
interrupt controller
(NVIC)
Wake-up requests AWIC wake-up sources
NVIC
3.3.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-10. AWIC stop wake-up sources
Wake-up source Description
Available system resets RESET pin when LPO is its clock source Low-voltage detect Mode Controller Low-voltage warning Mode Controller Pin interrupts Port control module - Any enabled pin interrupt is capable of waking the system ADC The ADC is functional when using internal clock source
Table continues on the next page...
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Register access
Peripheral
bridge
System integration
module (SIM)

System Modules

Table 3-10. AWIC stop wake-up sources (continued)
Wake-up source Description
CMP0 Interrupt in normal or trigger mode I2Cx Address match wakeup UART0 Any interrupt provided clock remains enabled UART1 and UART2 Active edge on RXD RTC Alarm or seconds interrupt TSI Any interrupt NMI NMI pin TPMx Any interrupt provided clock remains enabled LPTMR Any interrupt provided clock remains enabled SPI Slave mode interrupt
3.4
System Modules

3.4.1 SIM Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-4. SIM configuration
Table 3-11. Reference links to related information
Topic Related module Reference
Full description SIM SIM
System memory map System memory map
Clocking Clock distribution
Power management Power management
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Power Management
Controller (PMC)
Register access
Peripheral
bridge
System Mode
Controller (SMC)
Resets
Chapter 3 Chip Configuration

3.4.2 System Mode Controller (SMC) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-5. System Mode Controller configuration
Table 3-12. Reference links to related information
Topic Related module Reference
Full description System Mode
Controller (SMC)
System memory map System memory map
Power management Power management
Power management
controller (PMC)
Low-Leakage Wakeup
Unit (LLWU)
Reset Control Module
(RCM)
SMC
PMC
LLWU
Reset
3.4.2.1 VLLS2 not supported
VLLS2 power mode is not supported on this device.

3.4.3 PMC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Register access
Power Management
Controller (PMC)
Module signals
Peripheral
bridge
Module signals
System Mode
Controller (SMC)
Low-Leakage
Wakeup Unit
System Modules
Figure 3-6. PMC configuration
Table 3-13. Reference links to related information
Topic Related module Reference
Full description PMC PMC
System memory map System memory map
Power management Power management
Full description System Mode
Controller (SMC)
Low-Leakage Wakeup
Unit (LLWU)
Reset Control Module
(RCM)
System Mode Controller
LLWU
Reset

3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Page 59
Low-Leakage Wake-up
Unit (LLWU)
Power Management
Controller (PMC)
Peripheral
bridge 0
Register access
Wake-up
requests
Module
Module
Chapter 3 Chip Configuration
Figure 3-7. Low-Leakage Wake-up Unit configuration
Table 3-14. Reference links to related information
Topic Related module Reference
Full description LLWU LLWU
System memory map System memory map
Clocking Clock distribution
Power management Power management chapter
Power Management
Controller (PMC)
System Mode
Controller (SMC)
Wake-up requests LLWU wake-up sources
Power Management Controller (PMC)
System Mode Controller
3.4.4.1 LLWU interrupt
3.4.4.2 Wake-up Sources
The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IF­M7IF are connections to the internal peripheral interrupt flags.
Do not mask the LLWU interrupt when in LLS mode. Masking the interrupt prevents the device from exiting stop mode when a wakeup is detected.
In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted.
NOTE
NOTE
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Miscellaneous
Control Module
(MCM)
Transfers
ARM Cortex-M0+
core
Flash Memory
Controller
Transfers
System Modules
Table 3-15. Wakeup Sources
LLWU pin Module source or pin name
LLWU_P5 PTB0 LLWU_P6 PTC1 LLWU_P7 PTC3 LLWU_P8 PTC4
LLWU_P9 PTC5 LLWU_P10 PTC6 LLWU_P14 PTD4 LLWU_P15 PTD6
LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF TSI0 LLWU_M5IF RTC Alarm LLWU_M6IF Reserved LLWU_M7IF RTC Seconds

3.4.5 MCM Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-8. MCM configuration
Table 3-16. Reference links to related information
Topic Related module Reference
Full description Miscellaneous control
module (MCM)
System memory map System memory map
Clocking Clock distribution
Power management Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
MCM
Table continues on the next page...
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Crossbar Switch
Slave Modules
Master Modules
M2
M0
S0
S2
ARM core
unified bus
DMA
Flash
controller
S1
SRAML
BME
Peripheral
bridge 0
GPIO
controller
SRAMU
Peripherals
USB
M3
Chapter 3 Chip Configuration
Table 3-16. Reference links to related information (continued)
Topic Related module Reference
Transfer Flash memory
Flash memory controller
controller

3.4.6 Crossbar-Light Switch Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-9. Crossbar-Light switch integration
Table 3-17. Reference links to related information
Topic Related module Reference
Full description Crossbar switch Crossbar Switch
System memory map System memory map
Clocking Clock Distribution Crossbar switch master ARM Cortex-M0+ core ARM Cortex-M0+ core Crossbar switch master DMA controller DMA controller Crossbar switch master USB FS/LS USB FS/LS
Crossbar switch slave Flash memory
controller
Crossbar switch slave SRAM controller SRAM configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
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Flash memory controller
Page 62
System Modules
Table 3-17. Reference links to related information (continued)
Topic Related module Reference
Crossbar switch slave Peripheral bridge Peripheral bridge
2-ported peripheral GPIO controller GPIO controleer
3.4.6.1 Crossbar-Light Switch Master Assignments
The masters connected to the crossbar switch are assigned as follows:
Master module Master port number
ARM core unified bus 0 DMA 2 USB OTG 3
3.4.6.2 Crossbar Switch Slave Assignments
This device contains 3 slaves connected to the crossbar switch. The slave assignment is as follows:
Slave module Slave port number
Flash memory controller 0 SRAM controller 1 Peripheral bridge 0 2

3.4.7 Peripheral Bridge Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Peripherals
Transfers
AIPS-Lite
peripheral bridge
Transfers
Crossbar switch
Figure 3-10. Peripheral bridge configuration
Table 3-18. Reference links to related information
Topic Related module Reference
Full description Peripheral bridge
(AIPS-Lite)
System memory map System memory map
Clocking Clock Distribution
Crossbar switch Crossbar switch Crossbar switch
Peripheral bridge (AIPS-Lite)
3.4.7.1 Number of peripheral bridges
Chapter 3 Chip Configuration
This device contains one peripheral bridge.
3.4.7.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module.

3.4.8 DMA request multiplexer configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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DMA Request
Multiplexer
DMA controller
Requests
Module
Module
Module
Peripheral
bridge 0
Register access
Channel
request
System Modules
Figure 3-11. DMA request multiplexer configuration
Table 3-19. Reference links to related information
Topic Related module Reference
Full description DMA request
multiplexer
System memory map System memory map
Clocking Clock distribution
Power management Power management
Channel request DMA controller DMA Controller
Requests DMA request sources
DMA Mux
3.4.8.1 DMA MUX Request Sources
This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is no hard correlation between any of the DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table.
Table 3-20. DMA request sources - MUX 0
Source
number
0 — Channel disabled 1 Reserved Not used 2 UART0 Receive Yes 3 UART0 Transmit Yes 4 UART1 Receive 5 UART1 Transmit 6 UART2 Receive 7 UART2 Transmit
Source module Source description Async DMA
1
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KL25 Sub-Family Reference Manual, Rev. 3, September 2012
capable
Page 65
Chapter 3 Chip Configuration
Table 3-20. DMA request sources - MUX 0 (continued)
Source
number
8 Reserved —
9 Reserved — 10 Reserved — 11 Reserved — 12 Reserved — 13 Reserved — 14 Reserved — 15 Reserved — 16 SPI0 Receive 17 SPI0 Transmit 18 SPI1 Receive 19 SPI1 Transmit 20 Reserved — 21 Reserved — 22 I2C0 — 23 I2C1 — 24 TPM0 Channel 0 Yes 25 TPM0 Channel 1 Yes 26 TPM0 Channel 2 Yes 27 TPM0 Channel 3 Yes 28 TPM0 Channel 4 Yes 29 TPM0 Channel 5 Yes 30 Reserved — 31 Reserved — 32 TPM1 Channel 0 Yes 33 TPM1 Channel 1 Yes 34 TPM2 Channel 0 Yes 35 TPM2 Channel 1 Yes 36 Reserved — 37 Reserved — 38 Reserved — 39 Reserved — 40 ADC0 — Yes 41 Reserved — 42 CMP0 — Yes 43 Reserved — 44 Reserved — 45 DAC0 — 46 Reserved —
Source module Source description Async DMA
capable
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System Modules
Table 3-20. DMA request sources - MUX 0 (continued)
Source
number
47 Reserved — 48 Reserved — 49 Port control module Port A Yes 50 Reserved — 51 Reserved — 52 Port control module Port D Yes 53 Reserved — 54 TPM0 Overflow Yes 55 TPM1 Overflow Yes 56 TPM2 Overflow Yes 57 TSI — Yes 58 Reserved — 59 Reserved — 60 DMA MUX Always enabled 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled
Source module Source description Async DMA
capable
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
3.4.8.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first two DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments .

3.4.9 DMA Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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DMA Controller
Crossbar switch
Requests
Peripheral
bridge 0
Register access
Transfers
DMA Multiplexer
WDOG
Mode Controller
Peripheral
bridge 0
Register access
Chapter 3 Chip Configuration
Figure 3-12. DMA Controller configuration
Table 3-21. Reference links to related information
Topic Related module Reference
Full description DMA controller DMA controller
System memory map System memory map
Clocking Clock distribution
Power management Power management
Crossbar switch Crossbar switch Crossbar switch
Requests DMA request sources

3.4.10 Computer Operating Properly (COP) Watchdog Configuration

This section summarizes how the module has been configured in the chip.
Figure 3-13. COP watchdog configuration
Table 3-22. Reference links to related information
Topic Related module Reference
Clocking Clock distribution
Power management Power management
Table continues on the next page...
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System Modules
Table 3-22. Reference links to related information (continued)
Topic Related module Reference
Programming model System Integration
Module (SIM)
SIM
3.4.10.1 COP clocks
The two clock inputs for the COP are the 1 kHz clock and the bus clock.
3.4.10.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an application, it can be disabled by clearing COPCTRL[COPT] in the SIM.
The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not affect the data in the SRVCOP register. As soon as the write sequence is complete, the COP timeout period is restarted. If the program fails to perform this restart during the timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to the SRVCOP register, the microcontroller immediately resets.
The SIM's COPCTRL[COPCLKS] field selects the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1 kHz clock source. With each clock source, there are three associated timeouts controlled by COPCTRL[COPT]. The following table summarizes the control functions of the COPCLKS and COPT bits. The COP watchdog defaults to operation from the 1 kHz clock source and the longest timeout for that clock source (210 cycles).
Table 3-23. COP configuration options
Control Bits Clock Source COP Window Opens
COPCTRL[COPCLKS] COPCTRL[COPT]
N/A 00 N/A N/A COP is disabled
0 01 1 kHz N/A 25 cycles (32 ms)
(COPCTRL[COPW]=1)
COP Overflow Count
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Chapter 3 Chip Configuration
Table 3-23. COP configuration options (continued)
Control Bits Clock Source COP Window Opens
COPCTRL[COPCLKS] COPCTRL[COPT]
0 10 1 kHz N/A 28 cycles (256 ms) 0 11 1 kHz N/A 210 cycles (1024 ms) 1 01 Bus 6,144 cycles 213 cycles 1 10 Bus 49,152 cycles 216 cycles 1 11 Bus 196,608 cycles 218 cycles
(COPCTRL[COPW]=1)
COP Overflow Count
After the bus clock source is selected, windowed COP operation is available by setting COPCTRL[COPW] in the SIM. In this mode, writes to the SRVCOP register to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the chip. When the 1 kHz clock source is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SIM's COPCTRL register and after any system reset. Subsequent writes to the SIM's COPCTRL register have no effect on COP operation. Even if an application uses the reset default settings of the COPT, COPCLKS, and COPW bits, the user should write to the write-once COPCTRL register during reset initialization to lock in the settings. This approach prevents accidental changes if the application program becomes lost.
The write to the SRVCOP register that services (clears) the COP counter should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails.
If the bus clock source is selected, the COP counter does not increment while the microcontroller is in debug mode or while the system is in stop (including VLPS or LLS) mode. The COP counter resumes when the microcontroller exits debug mode or stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either debug mode or stop (including VLPS or LLS) mode. The counter begins from zero upon exit from debug mode or stop mode.
Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is re-initialized and enabled as for any reset.
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Register access
Peripheral
bridge
Multipurpose Clock
Generator (MCG)
System
oscillator
System integration
module (SIM)

Clock Modules

3.4.10.3 Clock Gating
This family of devices includes clock gating control for each peripheral, that is, the clock to each peripheral can explicitly be gated on or off, using clock-gate control bits in the SIM module.
3.5
Clock Modules

3.5.1 MCG Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-14. MCG configuration
Table 3-24. Reference links to related information
Topic Related module Reference
Full description MCG MCG
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.5.1.1 MCG FLL modes
On L-series devices the MCGFLLCLK frequency is limited to 48 MHz max. The DCO is limited to the two lowest range settings (MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01).
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Signal multiplexing
Register access
Peripheral
bridge
System oscillator
MCG
Module signals
RTC
Chapter 3 Chip Configuration

3.5.2 OSC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-15. OSC configuration
Table 3-25. Reference links to related information
Topic Related module Reference
Full description OSC OSC
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
Full description MCG MCG
3.5.2.1 OSC modes of operation with MCG and RTC
The most common method of controlling the OSC block is through MCG clock source selection MCG_C1[CLKS] and the MCG_C2 register bits to configure the oscillator frequency range, gain-mode, and for crystal or external clock operation. The OSC_CR also provides control for enabling the OSC and configuring internal load capacitors for the EXTAL and XTAL pins. See the OSC and MCG chapters for more details.
The RTC_CR[OSCE] bit has overriding control over the MCG and OSC_CR enable functions. When RTC_CR[OSCE] is set, the OSC is configured for low frequency, low power and the RTC_CR[SCxP] bits override the OSC_CR[SCxP] bits to control the internal capacitance configuration. See the RTC chapter for more details.
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Register access
Flash memory
Transfers
Flash memory
controller
Peripheral bus
controller 0

Memories and Memory Interfaces

3.6
Memories and Memory Interfaces

3.6.1 Flash Memory Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-16. Flash memory configuration
Table 3-26. Reference links to related information
Topic Related module Reference
Full description Flash memory Flash memory
System memory map System memory map
Clocking Clock Distribution
Transfers Flash memory
controller
Register access Peripheral bridge Peripheral bridge
Flash memory controller
3.6.1.1 Flash Memory Sizes
The devices covered in this document contain 1 program flash block consisting of 1 KB sectors.
The amounts of flash memory for the devices covered in this document are:
Table 3-27. KL25 flash memory size
Device Program flash (KB) Block 0 (P-Flash) address range
MKL25Z32VFM4 32 0x0000_0000 – 0x0000_7FFF MKL25Z64VFM4 64 0x0000_0000 – 0x0000_FFFF
Table continues on the next page...
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Table 3-27. KL25 flash memory size (continued)
Program flash
Flash configuration field
Program flash base address
Flash memory base address
Registers
Device Program flash (KB) Block 0 (P-Flash) address range
MKL25Z128VFM4 128 0x0000_0000 – 0x0001_FFFF
MKL25Z32VFT4 32 0x0000_0000 – 0x0000_7FFF MKL25Z64VFT4 64 0x0000_0000 – 0x0000_FFFF
MKL25Z128VFT4 128 0x0000_0000 – 0x0001_FFFF
MKL25Z32VLH4 32 0x0000_0000 – 0x0000_7FFF MKL25Z64VLH4 64 0x0000_0000 – 0x0000_FFFF
MKL25Z128VLH4 128 0x0000_0000 – 0x0001_FFFF
MKL25Z32VLK4 32 0x0000_0000 – 0x0000_7FFF MKL25Z64VLK4 64 0x0000_0000 – 0x0000_FFFF
MKL25Z128VLK4 128 0x0000_0000 – 0x0001_FFFF
3.6.1.2 Flash Memory Map
Chapter 3 Chip Configuration
The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map.
Figure 3-17. Flash memory map
The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash
Memory Sizes for details of supported ranges.
Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response.
3.6.1.3 Flash Security
How flash security is implemented on this device is described in Chip Security.
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Memories and Memory Interfaces
3.6.1.4 Flash Modes
The flash memory chapter defines two modes of operation - NVM normal and NVM special modes. On this device, The flash memory only operates in NVM normal mode. All references to NVM special mode should be ignored.
3.6.1.5 Erase All Flash Contents
In addition to software, the entire flash memory may be erased external to the flash memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP STATUS[0] is cleared when the mass erase completes.
3.6.1.6 FTFA_FOPT Register
The flash memory's FTFA_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition.

3.6.2 Flash Memory Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
See MCM_PLACR register description for details on the reset configuration of the FMC.
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Flash memory
controller
Transfers
Transfers
Flash memory
Crossbar switch
MCM
SRAM upper
Transfers
Cortex-M0+
core
switch
SRAM lower
crossbar
SRAM
controller
Chapter 3 Chip Configuration
Figure 3-18. Flash memory controller configuration
Table 3-28. Reference links to related information
Topic Related module Reference
Full description Flash memory
controller
System memory map System memory map
Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch
Register access MCM MCM
Flash memory controller

3.6.3 SRAM Configuration

This section summarizes how the module has been configured in the chip.
Figure 3-19. SRAM configuration
Table 3-29. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map System memory map
Clocking Clock Distribution
ARM Cortex-M0+ core ARM Cortex-M0+ core
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Memories and Memory Interfaces
3.6.3.1 SRAM Sizes
This device contains SRAM which could be accessed by bus masters through the cross­bar switch. The amount of SRAM for the devices covered in this document is shown in the following table.
Table 3-30. KL25 SRAM memory size
Device SRAM (KB)
MKL25Z32VFM4 4 MKL25Z64VFM4 8
MKL25Z128VFM4 16
MKL25Z32VFT4 4 MKL25Z64VFT4 8
MKL25Z128VFT4 16
MKL25Z32VLH4 4 MKL25Z64VLH4 8
MKL25Z128VLH4 16
MKL25Z32VLK4 4 MKL25Z64VLK4 8
MKL25Z128VLK4 16
3.6.3.2 SRAM Ranges
The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated to SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]
This is illustrated in the following figure.
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SRAM_U
0x2000_0000
SRAM size *(1/4)
SRAM_L
0x1FFF_FFFF
SRAM size * (3/4)
0x2000_0000 – SRAM_size/4
0x2000_0000 + SRAM_size(3/4) - 1
Chapter 3 Chip Configuration
For example, for a device containing 16 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_2FFF
3.6.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0 no SRAM is retained.
3.7

Analog

3.7.1 16-bit SAR ADC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-20. SRAM blocks memory map
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Module signals
Register access
16-bit SAR ADC
Peripheral bus
controller 0
Other peripherals
Analog
Figure 3-21. 16-bit SAR ADC configuration
Table 3-31. Reference links to related information
Topic Related module Reference
Full description 16-bit SAR ADC 16-bit SAR ADC
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.1.1 ADC Instantiation Information
This device contains one 16 -bit successive approximation ADC with up to 16-channel. The ADC supports both software and hardware triggers. The hardware trigger sources are
listed in the Module-to-Module section. The number of ADC channels present on the device is determined by the pinout of the
specific device package and is shown in the following table.
Table 3-32. Number of KL25 ADC channels
Device Number of ADC channels
MKL25Z32VFM4 7 MKL25Z64VFM4 7
MKL25Z128VFM4 7
MKL25Z32VFT4 13 MKL25Z64VFT4 13
MKL25Z128VFT4 13
MKL25Z32VLH4 14 MKL25Z64VLH4 14
MKL25Z128VLH4 14
MKL25Z32VLK4 14
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Chapter 3 Chip Configuration
Table 3-32. Number of KL25 ADC channels (continued)
Device Number of ADC channels
MKL25Z64VLK4 14
MKL25Z128VLK4 14
3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA req) on conversion completion.
3.7.1.3 ADC0 Connections/Channel Assignment
NOTE
As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode.
3.7.1.3.1 ADC0 Channel Assignment
ADC Channel
(SC1n[ADCH])
00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0/ADC0_SE0 00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1/ADC0_SE1 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2/ADC0_SE2 00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3/ADC0_SE3
1
00100
1
00101
1
00110
1
00111
1
00100
1
00101
1
00110
1
00111 01000 AD8 Reserved ADC0_SE8 01001 AD9 Reserved ADC0_SE9 01010 AD10 Reserved Reserved
Channel Input signal
(SC1n[DIFF]= 1)
AD4a Reserved ADC0_DM0/ADC0_SE4a AD5a Reserved ADC0_DM1/ADC0_SE5a AD6a Reserved ADC0_DM2/ADC0_SE6a AD7a Reserved ADC0_DM3/ADC0_SE7a AD4b Reserved ADC0_SE4b AD5b Reserved ADC0_SE5b AD6b Reserved ADC0_SE6b AD7b Reserved ADC0_SE7b
Input signal
(SC1n[DIFF]= 0)
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Analog
ADC Channel
(SC1n[ADCH])
01011 AD11 Reserved ADC0_SE11 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved Reserved 10001 AD17 Reserved Reserved 10010 AD18 Reserved Reserved 10011 AD19 Reserved Reserved 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC0 Output/
11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled
Channel Input signal
(SC1n[DIFF]= 1)
2
Input signal
(SC1n[DIFF]= 0)
ADC0_SE23
Bandgap (S.E)
2
1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details.
2. This is the PMC bandgap 1V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.
3.7.1.4 ADC Analog Supply and Reference Connections
This device includes dedicated VDDA and VSSA pins. This device contains separate VREFH and VREFL pins on 48-pin and higher devices.
These pins are internally connected to VDDA and VSSA respectively, on 32-pin devices.
3.7.1.5 ADC Reference Options
The ADC supports the following references:
• VREFH/VREFL - connected as the primary reference option
• VDDA - connected as the V
reference option
ALT
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Module signals
Register access
CMP
Peripheral
bridge 0
Other peripherals
Chapter 3 Chip Configuration

3.7.2 CMP Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-22. CMP configuration
Table 3-33. Reference links to related information
Topic Related module Reference
Full description Comparator (CMP) Comparator
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.2.1 CMP Instantiation Information
The device includes one high speed comparator and two 8-input multiplexors for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. Two of the channels are connected to internal sources, leaving resources to support up to 6 input pins. See the channel assignment table for a summary of CMP input connections for this device.
The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, which provides a selectable voltage reference for applications where voltage reference is needed for internal connection to the CMP.
The CMP can be optionally on in all modes except VLLS0. The CMP has several module to module interconnects in order to facilitate ADC
triggering, TPM triggering and UART IR interfaces. For complete details on the CMP module interconnects please refer to the Module-to-Module section.
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Analog
The CMP does not support window compare function and CMP_CR1[WE] must always be written to 0. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0).
Due to the pin number limitation, the CMP pass through mode is not supported by this device, so the CMPx_MUXCR[PSTM] must be left as 0.
3.7.2.2 CMP input connections
The following table shows the fixed internal connections to the CMP.
Table 3-34. CMP input connections
CMP Inputs CMP0
IN0 CMP0_IN0 IN1 CMP0_IN1 IN2 CMP0_IN2 IN3 CMP0_IN3 IN4 12-bit DAC0 reference/ CMP0_IN4 IN5 CMP0_IN5 IN6 Bandgap IN7 6-bit DAC0 reference
1
1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.
3.7.2.3 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows:
• VREFH - V
input. When using VREFH, any ADC conversion using this same
in1
reference at the same time is negatively impacted.
• VDD - V
in2
input
3.7.2.4 CMP trigger mode
The CMP and 6-bit DAC sub-block supports trigger mode operation when the CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output. In this device, control for this two staged sequencing
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Signal multiplexing
Module signals
Register access
12-bit DAC
Peripheral bus
controller 0
Other peripherals
Chapter 3 Chip Configuration
is provided from the LPTMR. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period.
The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the Analog comparator initialization delay as defined in the device datasheet.

3.7.3 12-bit DAC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-23. 12-bit DAC configuration
Table 3-35. Reference links to related information
Topic Related module Reference
Full description 12-bit DAC 12-bit DAC
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.3.1 12-bit DAC Instantiation Information
This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a two word FIFO for DMA support.
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Timers

3.7.3.2 12-bit DAC Output
The output of the DAC can be placed on an external pin or selected as an input to the analog comparator or ADC.
3.7.3.3 12-bit DAC Analog Supply and Reference Connections
This device includes dedicated VDDA and VSSA pins. This device contains separate VREFH and VREFL pins on 48-pin and higher devices.
These pins are internally connected to VDDA and VSSA respectively, on 32-pin devices.
3.7.3.4 12-bit DAC Reference
For this device VREFH and VDDA are selectable as the DAC reference. VREFH is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options.
Be aware that if the DAC and ADC use the same reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching.
3.8
Timers

3.8.1 Timer/PWM Module Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Signal multiplexing
Module signals
Register access
TPM
Peripheral bus
controller 0
Other peripherals
Chapter 3 Chip Configuration
Figure 3-24. TPM configuration
Table 3-36. Reference links to related information
Topic Related module Reference
Full description Timer/PWM Module Timer/PWM Module
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.8.1.1 TPM Instantiation Information
This device contains three Low Power TPM modules (TPM). All TPM modules in the device only are configured as basic TPM function, and no quadrature decoder function and all can be functional in Stop/VLPS mode. The clock source is either external or internal in Stop/VLPS mode.
The following table shows how these modules are configured.
Table 3-37. TPM configuration
TPM instance Number of channels Features/usage
TPM0 6 Basic TPM,functional in Stop/VLPS mode TPM1 2 Basic TPM,functional in Stop/VLPS mode TPM2 2 Basic TPM,functional in Stop/VLPS mode
There are several connections to and from the TPMs in order to facilitate customer use cases. For complete details on the TPM module interconnects please refer to the Module-
to-Module section.
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Timers
3.8.1.2 Clock Options
The TPM blocks are clocked from a single TPM clock that can be selected from OSCERCLK, MCGIRCLK, MCGPLLCLK/2, or MCGFLLCLK. The selected source is controlled by SIM_SOPT2[TPMSRC] and SIM_SOPT2[PLLFLLSEL]control registers.
Each TPM also supports an external clock mode (TPM_SC[CMOD]=1x) in which the counter increments after a synchronized (to the selected TPM clock source) rising edge detect of an external clock input. The available external clock (either TPM_CLKIN0 or TPM_CLKIN1) is selected by SIM_SOPT4[TPMxCLKSEL] control register. To guarantee valid operation the selected external clock must be less than half the frequency of the selected TPM clock source.
3.8.1.3 Trigger Options
Each TPM has a selectable trigger input source controlled by the TPMx_CONF[TRGSEL] field to use for starting the counter and/or reloading the counter. The options available are shown in the following table.
Table 3-38. TPM trigger options
TPMx_CONF[TRGSEL] Selected source
0000 External trigger pin input (EXTRG_IN) 0001 CMP0 output 0010 Reserved 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 0110 Reserved 0111 Reserved 1000 TPM0 overflow 1001 TPM1 overflow 1010 TPM2 overflow 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved
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Register access
Peripheral
bridge
Periodic interrupt
timer
Chapter 3 Chip Configuration
3.8.1.4 Global Timebase
Each TPM has a global timebase feature controlled by the TPMx_CONF[GTBEEN] bit. TPM1 is configured as the global time when this option is enabled.
3.8.1.5 TPM Interrupts
The TPM has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an TPM interrupt occurs, read the TPM status registers to determine the exact interrupt source.

3.8.2 PIT Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-25. PIT configuration
Table 3-39. Reference links to related information
Topic Related module Reference
Full description PIT PIT
System memory map System memory map
Clocking Clock Distribution
Power management Power management
3.8.2.1 PIT/DMA Periodic Trigger Assignments
The PIT generates periodic trigger events to the DMA channel mux as shown in the table below.
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Register access
Peripheral
bridge
Module signals
Low-power timer
Timers
Table 3-40. PIT channel assignments for periodic DMA triggering
PIT Channel DMA Channel Number
PIT Channel 0 DMA Channel 0 PIT Channel 1 DMA Channel 1
3.8.2.2 PIT/ADC Triggers
PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module. For more details, refer to SIM chapter.
3.8.2.3 PIT/TPM Triggers
PIT triggers are selected as TPMx trigger sources using the TPMx_CONF[TRGSEL] bits in the TPM module. For more details, refer to TPM chapter.
3.8.2.4 PIT/DAC Triggers
PIT Channel 0 is configured as the DAC hardware trigger source. For more details, refer to DAC chapter.

3.8.3 Low-power timer configuration

Figure 3-26. LPT configuration
Topic Related module Reference
Full description Low-power timer Low-power timer
Table 3-41. Reference links to related information
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-41. Reference links to related information (continued)
Topic Related module Reference
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.8.3.1 LPTMR Instantiation Information
The low-power timer (LPTMR) allows operation during all power modes. The LPTMR can operate as a real-time interrupt or pulse accumulator. It includes a 15-bit prescaler (real-time interrupt mode) or glitch filter (pulse accumulator mode).
The LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO, OSCERCLK, or an external 32.768 kHz crystal. In VLLS0 mode, the clocking option is limited to an external pin with the OSC configured for bypass (external clock) operation.
An interrupt is generated (and the counter may reset) when the counter equals the value in the 16-bit compare register.
3.8.3.2 LPTMR pulse counter input options
The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield.
LPTMR_CSR[TPS] Pulse counter input number Chip input
00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 LPTMR_ALT3 pin
3.8.3.3 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield.
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Register access
Peripheral
bridge
Module signals
Real-time clock
Timers
NOTE
The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes.
LPTMR0_PSR[PCS] Prescaler/glitch filter clock
number
00 0 MCGIRCLK — internal reference clock
01 1 LPO — 1 kHz clock (not available in
10 2 ERCLK32K (not available in VLLS0
11 3 OSCERCLK — external reference clock
Chip clock
(not available in LLS and VLLS modes)
VLLS0 mode)
mode when using 32 kHz oscillator)
(not available in VLLS0 mode)
See Clock Distribution for more details on these clocks.

3.8.4 RTC configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-27. RTC configuration
Table 3-42. Reference links to related information
Topic Related module Reference
Full description RTC RTC
System memory map System memory map
Clocking Clock Distribution
Power management Power management
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Chapter 3 Chip Configuration
3.8.4.1 RTC Instantiation Information
RTC prescaler is clocked by ERCLK32K. RTC is reset on POR Only. RTC_CR[OSCE] can override the configuration of the System OSC, configuring the
OSC for 32kHz crystal operation in all power modes (except VLLS0) and through any System Reset. When OSCE is enabled, the RTC also overrides the capacitor configurations.
3.8.4.2 RTC_CLKOUT options
RTC_CLKOUT pin can be driven either with the RTC 1 Hz output or with the OSCERCLK on-chip clock source. Control for this option is through SIM_SOPT2[RTCCLKOUTSEL] bit.
When RTCCLKOUTSEL=0, the RTC 1 Hz clock is output is selected on the RTC_CLKOUT pin. When RTCCLKOUTSEL=1, OSCERCLK clock is output on the RTC_CLKOUT pin.
3.9

Communication interfaces

3.9.1 Universal Serial Bus (USB) FS Subsystem

The USB FS subsystem includes these components:
• Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification.
• USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for host mode functionality.
• A 3.3 V regulator.
• VBUS detect signal: To detect a valid VBUS in device mode, use a GPIO signal that can wake the chip in all power modes.
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USB controller
FS/LS
transceiver
USB voltage
regulator
D+ D-
VREGIN VOUT33
Communication interfaces
Figure 3-28. USB Subsystem Overview
3.9.1.1 USB Wakeup
When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action.
Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function.
3.9.1.2 USB Power Distribution
This chip includes an internal 5 V to 3.3 V USB regulator that powers the USB transceiver or the MCU (depending on the application).
3.9.1.2.1 AA/AAA cells power supply
The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the USB regulator is enabled to power the USB transceiver.
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Chapter 3 Chip Configuration
2 AA Cells
TYPE A
D+
VBUS
D-
VDD
VOUT33
Cstab
VREGIN
USB0_DP
USB0_DM
To PMC and Pads
USB
Regulator
USB
XCVR
Figure 3-29. USB regulator AA cell usecase
Chip
USB
Controller
3.9.1.2.2 Li-Ion battery power supply
The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. To charge the battery, the MCU can configure the battery charger.
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Communication interfaces
VDD
To PMC and Pads
VOUT33
C
stab
TYPE A
VBUS
D+
D-
VSS
Charger
Li-Ion
Si2301
VREGIN
USB0_DP
USB0_DM
USB
Regulator
USB
XCVR
Chip
USB
Controller
Figure 3-30. USB regulator Li-ion usecase
3.9.1.2.3 USB bus power supply
The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor.
VDD
To PMC and Pads
Cstab
TYPE A
VBUS
D+
D-
VOUT33
VREGIN
USB0_DP
USB0_DM
USB
Regulator
XCVR
USB
Chip
USB
Controller
Figure 3-31. USB regulator bus supply
3.9.1.3 USB power management
The regulator should be put into STANDBY mode whenever the chip is in Stop mode.
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Module signals
Register access
USB controller
Peripheral
bridge 0
Crossbar switch
Transfers
Chapter 3 Chip Configuration
3.9.1.4 USB controller configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-32. USB controller configuration
Table 3-43. Reference links to related information
Topic Related module Reference
Full description USB controller USB controller
System memory map System memory map
Clocking Clock Distribution
Transfers Crossbar switch Crossbar switch
Signal Multiplexing Port control Signal Multiplexing
NOTE
When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating.
3.9.1.5 USB Voltage Regulator Configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Module signals
USB Voltage
Regulator
USB OTG
Signal multiplexing
Register access
SPI
Peripheral
bridge
Module signals
Communication interfaces
Figure 3-33. USB Voltage Regulator configuration
Table 3-44. Reference links to related information
Topic Related module Reference
Full description USB Voltage Regulator USB Voltage Regulator
System memory map System memory map
Clocking Clock Distribution
USB controller USB controller
Signal Multiplexing Port control Signal Multiplexing
NOTE
When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating.

3.9.2 SPI configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-34. SPI configuration
Table 3-45. Reference links to related information
Topic Related module Reference
Full description SPI SPI
System memory map System memory map
Clocking Clock Distribution
Table continues on the next page...
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Module signals
2
I C
Chapter 3 Chip Configuration
Table 3-45. Reference links to related information (continued)
Topic Related module Reference
Signal Multiplexing Port control Signal Multiplexing
3.9.2.1 SPI Instantiation Information
This device contains two SPI module that supports 8-bit data length. SPI0 is clocked on the bus clock. SPI1 is clocked from the system clock. SPI1 is
therefore disabled in "Partial Stop Mode". The SPI supports DMA request and can operate in VLPS mode. When the SPI is
operating in VLPS mode, it will operate as a slave. SPI can wakeup MCU from VLPS mode upon reception of SPI data in slave mode.

3.9.3 I2C Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-35. I2C configuration
Table 3-46. Reference links to related information
Topic Related module Reference
Full description I2C I2C
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
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Peripheral
bridge
Module signals
UART
Communication interfaces
3.9.3.1 IIC Instantiation Information
This device has two IIC module. When the package pins associated with IIC have their mux select configured for IIC
operation, the pins (SCL and SDA) are driven in a pseudo open drain configuration. The digital glitch filter implemented in the IICx module, controlled by the
I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts.

3.9.4 UART Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-36. UART configuration
Table 3-47. Reference links to related information
Topic Related module Reference
Full description UART1 and UART2 UART Full description UART0 UART
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
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Module signals
GPIO controller
ARM Cortex -M0+
Core
Register access
Chapter 3 Chip Configuration
3.9.4.1 UART0 overview
The UART0 module supports basic UART with DMA interface function, x4 to x32 oversampling of baud-rate.
This module supports LIN slave operation. The module can remain functional in VLPS mode provided the clock it is using remains
enabled. ISO7816 protocol is intended to be handled in software for this product. To support smart
card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like ISO7816 communication via the SIM_SOPT5[UART0ODE] bit.
3.9.4.2 UART1 and UART2 Overview
This device contains two basic universal asynchronous receiver/transmitter (UART) modules with DMA function support. Generally, these modules are used in RS-232, RS-485, and other communications. This module supports LIN Slave operation.
3.10

Human-machine interfaces (HMI)

3.10.1 GPIO Configuration

Figure 3-37. GPIO configuration
Table 3-48. Reference links to related information
Topic Related module Reference
Full description GPIO GPIO
System memory map System memory map
Clocking Clock Distribution
Table continues on the next page...
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Human-machine interfaces (HMI)
Table 3-48. Reference links to related information (continued)
Topic Related module Reference
Power management Power management
Crossbar switch Crossbar switch Crossbar switch
Signal Multiplexing Port control Signal Multiplexing
3.10.1.1 GPIO Instantiation Information
The device includes four pins, PTB0, PTB1, PTD6, and PTD7, with high current drive capability. These pins can be used to drive LED or power MOSFET directly. The high drive capability applies to all functions which are multiplexed on these pins (UART, TPM, SPI...etc)
3.10.1.1.1 Pull Devices and Directions
The pull devices are enabled out of POR only on RESET_B, NMI_b and respective SWD signals. Other pins can be enabled by writing to PORTx_PCRn[PE] field.
All the pins are hard wired to be pullup except for SWD_CLK. The state will be reflected in the PORTx_PCRn[PS] field.
3.10.1.2 Port Control and Interrupt Summary
The following table provides more information regarding the Port Control and Interrupt configurations .
Table 3-49. Ports Summary
Feature Port A Port B Port C Port D Port E
Pull Select control No No No No No
Pull Select at reset PTA0=Pull down,
Others=Pull up
Pull Enable control Yes Yes Yes Yes Yes
Pull Enable at reset PTA0/PTA3/PTA4/
RESET_b=Enabled ; Others=Disabled
Slew Rate Enable
control
No No No No No
Pull up Pull up Pull up Pull up
Disabled Disabled Disabled Disabled
Table continues on the next page...
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