Freescale MCF5329 User Manual
Freescale Semiconductor
MAPBGA–256
17mm x 17mm
MAPBGA–196
15mm x 15mm
Data Sheet: Technical Data
MCF532x ColdFire®
Microprocessor Data Sheet
Features
• Version 3 ColdFire variable-length RISC processor core
• System debug support
• JTAG support for system level board testing
• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,
accessible by core and non-core bus masters (e.g., DMA,
FEC, LCD controller, and USB host and OTG)
• Power management
• Liquid Crystal Display Controller (LCDC)
• Embedded Voice-over-IP (VoIP) system solution
• SDR/DDR SDRAM Controller
• Universal Serial Bus (USB) Host Controller
• Universal Serial Bus (USB) On-the-Go (OTG) controller
• Synchronous Serial Interface (SSI)
• Fast Ethernet Controller (FEC)
• Cryptography Hardware Accelerators
• FlexCAN Module
• Three Universal Asynchronous Receiver Transmitters
(UARTs)
2
•I
C Module
• Queued Serial Peripheral Interface (QSPI)
• Pulse Width Modulation (PWM) module
• Real Time Clock
• Four 32-bit DMA Timers
• Software Watchdog Timer
• Four Periodic Interrupt Timers (PITs)
• Phase Locked Loop (PLL)
• Interrupt Controllers (x2)
• DMA Controller
• FlexBus (External Interface)
• Chip Configuration Module (CCM)
• Reset Controller
• General Purpose I/O interface
Document Number: MCF5329DS
Rev. 4, 04/2008
MCF5329
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Supply Voltage Sequencing and Separation Cautions . .5
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6
4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . 18
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .19
5.6 External Interface Timing Characteristics . . . . . . . . . . .20
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .23
5.7.2 DDR SDRAM AC Timing Characteristics . . . . . 25
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 28
5.9 Reset and Configuration Override Timing . . . . . . . . . . 29
5.10 LCD Controller Timing Specifications . . . . . . . . . . . . . 30
5.11 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.12 ULPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . 33
5.13 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 33
2
5.14 I
C Input/Output Timing Specifications . . . . . . . . . . . . 35
5.15 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37
5.15.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 37
5.15.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . 37
5.15.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 38
5.15.4 MII Serial Management Channel Timing . . . . . 38
5.16 32-Bit Timer Module Timing Specifications . . . . . . . . . 39
5.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 39
5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
5.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
6 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.1 Package Dimensions—256 MAPBGA . . . . . . . . . . . . . 46
7.2 Package Dimensions—196 MAPBGA . . . . . . . . . . . . . 47
8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor2
MCF532x Family Comparison
FlexBus
D[31:0]
A[23:0]
R/W
CS[5:0]
TA
TS
XBS
M2
M1 M0
M5
PWMs, EPORT,
JTAG
TAP
TRST
TCLK
TMS
TDI
TDO
Cache
(1024x32)x4
DMA
UARTs
FlexCAN
I2C
QSPI
DMA Timers
Watchdog, PITs
PADI — Pin Muxing
EXTAL
XTAL
CLKOUT
16 KByte
Chip
External
Selects
(To/From PADI)
CANTX
CANRX
FEC
FEC
DMA Timer
SDRAMC
UART
I
2
C
SDRAMC
QSPI
JTAG_EN
RTC
USB Host
M4
LCDC
S4
S7
S1
Reset
PORTS
SDRAMC
SSI
LCDC
USB OTG
RESET
SRAM
(4096x32)x2
32 KByte
PLL
S6
SDRAMC
M6
USB Host
USB OTG
ULPI Interface
INTC0
INTC1
RCON
LCDC
SSI
V3 ColdFire CPU
DIV EMAC
BDM
(To/From PADI)
RNGA
SKHA
MDHA
Cryptography
Modules
Interface
RSTOUT
EXTAL32K
XTAL32K
(To/From SRAM backdoor)
(To/From XBS backdoor)
DREQ
n
DACKn
(To/From PADI)
USB Host
USB OTG
BE/BWE[3:0]
PWM
XCVR XCVR
(To/From PADI)
1 MCF532x Family Comparison
The following table compares the various device derivatives available within the MCF532x family.
Freescale Semiconductor 3
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock up to 240 MHz
Peripheral and External Bus Clock
(Core clock ÷ 3)
Performance (Dhrystone/2.1 MIPS) up to 211
Unified Cache 16 Kbytes
Static RAM (SRAM) 32 Kbytes
Figure 1. MCF5329 Block Diagram
Table 1. MCF532x Family Configurations
Module MCF5327 MCF5328 MCF53281 MCF5329
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
••••
up to 80 MHz
Ordering Information
LCD Controller • • • •
SDR/DDR SDRAM Controller • • • •
USB 2.0 Host • • • •
USB 2.0 On-the-Go • • • •
UTMI+ Low Pin Interface (ULPI) — • • •
Synchronous Serial Interface (SSI) • • • •
Fast Ethernet Controller (FEC) — • • •
Cryptography Hardware Accelerators — — — •
Embedded Voice-over-IP System Solution — — • —
FlexCAN 2.0B communication module — — • •
UARTs 3333
2
C ••••
I
QSPI • • • •
PWM Module • • • •
Real Time Clock • • • •
32-bit DMA Timers 4444
Table 1. MCF53 2 x Family Configurations (continued)
Module MCF5327 MCF5328 MCF53281 MCF5329
Watchdog Timer (WDT) • • • •
Periodic Interrupt Timers (PIT) 4444
Edge Port Module (EPORT) • • • •
Interrupt Controllers (INTC) 2222
16-channel Direct Memory Access (DMA) • • • •
FlexBus External Interface • • • •
General Purpose I/O Module (GPIO) • • • •
®
JTAG - IEEE
Package 196
1149.1 Test Access Port • • • •
MAPBGA
256
MAPBGA
256
MAPBGA
2 Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
MCF5327CVM240 MCF5327 RISC Microprocessor 196 MAPBGA 240 MHz –40
MCF5328CVM240 MCF5328 RISC Microprocessor 256 MAPBGA 240 MHz –40
MCF53281CVM240 MCF53281 RISC Microprocessor 256 MAPBGA 240 MHz –40
MCF5329CVM240 MCF5329 RISC Microprocessor 256 MAPBGA 240 MHz –40
Description Package Speed Temperature
256
MAPBGA
° to +85° C
° to +85° C
° to +85° C
° to +85° C
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor4
Hardware Design Considerations
Board IV
DD
10 Ω
0.1 µF
PLL V
DD
Pin
10 µF
GND
Board EV
DD
0 Ω
0.1 µF
USB V
DD
Pin
10 µF
GND
3 Hardware Design Considerations
3.1 PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in
Figure 2 should be connected between the board V
close to the dedicated PLLV
pin as possible.
DD
and the PLLVDD pins. The resistor and capacitors should be placed as
DD
Figure 2. System PLL V
Power Filter
DD
3.2 USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EV
close to the dedicated USBV
or IV
DD
pin as possible.
DD
and each of the USBVDD pins. The resistor and capacitors should be placed as
DD
Figure 3. USB V
Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3 Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or
3.3V) and EV
are specified relative to IVDD.
DD
3.3.1 Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
the EV
must powered up. IV
Freescale Semiconductor 5
/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD
DD
should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is
DD
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Pin Assignments and Reset States
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.
3.3.2 Power Down Sequence
If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IV
not lag EV
, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the
DD
and PLLVDD power down before EVDD or SDVDD must power down. IVDD should
DD
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV
2. Drop EV
/PLLVDD to 0 V.
DD
/SDVDD supplies.
DD
4 Pin Assignments and Reset States
4.1 Signal Multiplexing
The following table lists all the MCF532x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the
MCF532x signals, consult the MCF5329 Reference Manual (MCF5329RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.
Table 3. MCF5327/8/9 Signal Information and Muxing
Signal Name GPIO Alternate 1 Alternate 2
Reset
RESET
RSTOUT — — — O
EXTAL32K — — — I
XTAL32K — — — O
FB_CLK — — — O
2
EXTAL — — — I
2
XTAL
— — — I
Clock
— — — O
1
Dir.
Voltage
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
SDVDD
MCF5327
196
MAPBGA
Domain
J11 N15 N15
P14 P14 P14
L14 P16 P16
K14 N16 N16
M11 P13 P13
N11 R13 R13
L1 T2 T2
MCF5328
256
MAPBGA
MCF53281
MCF5329
256
MAPBGA
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor6
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Mode Selection
2
RCON
— — — I
DRAMSEL — — — I
FlexBus
A[23:22] — FB_CS
[5:4] — O
A[21:16] — — — O
A[15:14] — SD_BA[1:0]
A[13:11] — SD_A[13:11]
3
3
—O
—O
A10 — — — O
A[9:0] — SD_A[9:0]
D[31:16] — SD_D[31:16]
D[15:1] — FB_D[31:17]
2
D0
BE/BWE
OE
TA
R/W
[3:0] PBE[3:0] SD_DQM[3:0]
2
— FB_D[16]
PBUSCTL3 — — O
PBUSCTL2 — — I
PBUSCTL1 — — O
3
4
4
4
3
—O
— I/O
— I/O
— I/O
— O
TS PBUSCTL0 DACK0 —O
1
Dir.
Volta ge
EVDD
EVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
MCF5327
MAPBGA
Domain
196
MCF5328
256
MAPBGA
MCF53281
MCF5329
MAPBGA
M7 M8 M8
G11 H12 H12
B11,C11 C13, D13 C13, D13
B12, A12,
D11, C12,
B13, A13
E13, A14,
B14, C14,
A15, B15
E13, A14,
B14, C14,
A15, B15
A14, B14 D14, B16 D14, B16
C13, C14,
D12
C15, C16,
D15
C15, C16,
D13 D16 D16
D14,
E11–14,
F11–F14,
E14–E16,
F13–F16,
G16– G14
E14–E16,
F13–F16,
G16– G14
G14
H3–H1,
J4–J1, K1,
L4, M2, M3,
N1, N2, P1,
P2, N3
F4–F1,
G5–G2, L5,
N4, P4, M5,
N5, P5, L6
M1–M4,
N1–N4, T3,
P4, R4, T4,
N5, P5, R5,
T5
J3–J1,
K4–K1, L2,
R6, N7, P7,
R7, T7, P8,
M1–M4,
N1–N4, T3,
P4, R4, T4,
N5, P5, R5,
J3–J1,
K4–K1, L2,
R6, N7, P7,
R7, T7, P8,
R8
M6 T8 T8
H4, P3, G1, M4L4, P6, L3, N6L4, P6, L3,
P6 R9 R9
G13 G13 G13
N6 N8 N8
D2 H4 H4
256
D15
T5
R8
N6
Chip Selects
FB_CS
[5:4] PCS[5:4] — — O
[3:1] PCS[3:1] O
FB_CS
FB_CS0
———O
SDVDD
SDVDD
SDVDD
— B13, A13 B13, A13
A11, D10,
C10
A12, B12,
C12
A12, B12,
B10 D12 D12
C12
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor 7
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
SDRAM Controller
SD_A10 — — — O
SD_CKE — — — O
SD_CLK — — — O
SD_CLK
SD_CS1
SD_CS0
———O
———O
———O
SD_DQS3 — — — O
SD_DQS2 — — — O
SD_SCAS
SD_SRAS
———O
———O
SD_SDR_DQS — — — O
SD_WE
———O
External Interrupts Port
IRQ7
IRQ6
2
2
PIRQ7
PIRQ6
2
2
— — I
USBHOST_
— I
VBUS_EN
IRQ5
2
PIRQ5
2
USBHOST_
— I
VBUS_OC
IRQ4
IRQ3
IRQ2
IRQ1
2
2
2
2
PIRQ4
PIRQ3
PIRQ2
PIRQ1
2
2
2
2
SSI_MCLK — I
— — I
USB_CLKIN — I
DREQ1
2
SSI_CLKIN I
1
Dir.
Volta ge
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
5
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
MCF5327
MAPBGA
Domain
196
MCF5328
256
MAPBGA
L2 P2 P2
E1 H2 H2
K3 R1 R1
K2 R2 R2
— J4 J4
E2 H1 H1
H5 L1 L1
K6 T6 T6
L3 P3 P3
M1 R3 R3
K4 P1 P1
D1 H3 H3
J13 J13 J13
— J14 J14
— J15 J15
L13 J16 J16
M14 K14 K14
M13 K15 K15
N13 K16 K16
MCF53281
MCF5329
256
MAPBGA
FEC
FEC_MDC PFECI2C3 I2C_SCL
FEC_MDIO PFECI2C2 I2C_SDA
2
2
— O
— I/O
FEC_TXCLK PFECH7 — — I
FEC_TXEN PFECH6 — — O
FEC_TXD0 PFECH5 ULPI_DATA0 — O
FEC_COL PFECH4 ULPI_CLK — I
FEC_RXCLK PFECH3 ULPI_NXT — I
FEC_RXDV PFECH2 ULPI_STP — I
FEC_RXD0 PFECH1 ULPI_DATA4 — I
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
— C1 C1
— C2 C2
— A2 A2
— B2 B2
— E4 E4
— A8 A8
— C8 C8
— D8 D8
— C6 C6
Freescale Semiconductor8
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
FEC_CRS PFECH0 ULPI_DIR — I
FEC_TXD[3:1] PFECL[7:5] ULPI_DATA[3:1] — O
FEC_TXER PFECL4 — — O
FEC_RXD[3:1] PFECL[3:1] ULPI_DATA[7:5] — I
FEC_RXER PFECL0 — — I
LCD Controller
LCD_D17 PLCDDH1 CANTX — O
LCD_D16 PLCDDH0 CANRX — O
LCD_D17 PLCDDH1 — — O
LCD_D16 PLCDDH0 — — O
LCD_D15 PLCDDM7 — — O
LCD_D14 PLCDDM6 — — O
LCD_D13 PLCDDM5 — — O
LCD_D12 PLCDDM4 — — O
LCD_D[11:8] PLCDDM[3:0] — — O
LCD_D7 PLCDDL7 — — O
LCD_D6 PLCDDL6 — — O
LCD_D5 PLCDDL5 — — O
LCD_D4 PLCDDL4 — — O
LCD_D[3:0] PLCDDL[3:0] — — O
LCD_ACD/
PLCDCTLH0 — — O
LCD_OE
LCD_CLS PLCDCTLL7 — — O
LCD_CONTRAST PLCDCTLL6 — — O
LCD_FLM/
PLCDCTLL5 — — O
LCD_VSYNC
LCD_LP/
PLCDCTLL4 — — O
LCD_HSYNC
LCD_LSCLK PLCDCTLL3 — — O
LCD_PS PLCDCTLL2 — — O
LCD_REV PLCDCTLL1 — — O
LCD_SPL_SPR PLCDCTLL0 — — O
1
Dir.
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
MCF5327
196
MAPBGA
Volta ge
Domain
— B8 B8
— D3–D1 D3–D1
— B1 B1
— E7, A6, B6 E7, A6, B6
— D4 D4
— — C9
— — D9
A6 C9 —
B6 D9 —
C6 A7 A7
D6 B7 B7
A5 C7 C7
B5 D7 D7
C5, D5, A4, B4D6, E6, A5, B5D6, E6, A5,
MCF5328
256
MAPBGA
MCF53281
MCF5329
256
MAPBGA
B5
EVDD
EVDD
EVDD
EVDD
EVDD
C4 C5 C5
B3 D5 D5
A3 A4 A4
A2 A3 A3
D4, C3, D3, B2B4, C4, B3, C3B4, C4, B3,
C3
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
D7 B9 B9
C7 A9 A9
B7 D10 D10
A7 C10 C10
A8 B10 B10
B8 A10 A10
C8 A11 A11
D8 B11 B11
B9 C11 C11
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor 9
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
1
USB Host & USB On-the-Go
USBOTG_M — — — I/O
USBOTG_P — — — I/O
USBHOST_M — — — I/O
USBHOST_P — — — I/O
FlexCAN (MCF53281 & MCF5329 only)
CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:
I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX.
PWM
PWM7 PPWM7 — — I/O
PWM5 PPWM5 — — I/O
PWM3 PPWM3 DT3OUT DT3IN I/O
PWM1 PPWM1 DT2OUT DT2IN I/O
MCF5327
Dir.
Volta ge
Domain
USB
VDD
USB
VDD
USB
VDD
USB
VDD
EVDD
EVDD
EVDD
EVDD
196
MAPBGA
G12 L15 L15
H13 L16 L16
K13 M15 M15
J12 M16 M16
— H13 H13
— H14 H14
H14 H15 H15
J14 H16 H16
MCF5328
256
MAPBGA
MCF53281
MCF5329
256
MAPBGA
SSI
SSI_MCLK PSSI4 — — I/O
SSI_BCLK PSSI3 U2CTS PWM7 I/O
SSI_FS PSSI2 U2RTS PWM5 I/O
SSI_RXD
SSI_TXD
SSI_RXD
SSI_TXD
2
2
2
2
PSSI1 U2RXD CANRX I
PSSI0 U2TXD CANTX O
PSSI1 U2RXD — I
PSSI0 U2TXD — O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
— G4 G4
— F4 F4
— G3 G3
— — G2
— — G1
— G2 —
— G1 —
I2C
I2C_SCL
I2C_SDA
I2C_SCL
I2C_SDA
2
2
2
2
PFECI2C1 CANTX U2TXD I/O
PFECI2C0 CANRX U2RXD I/O
PFECI2C1 — U2TXD I/O
PFECI2C0 — U2RXD I/O
EVDD
EVDD
EVDD
EVDD
— — F3
— — F2
E3 F3 —
E4 F2 —
DMA
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor10
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Volta ge
Domain
MCF5327
MAPBGA
Signal Name GPIO Alternate 1 Alternate 2
1
Dir.
QSPI
QSPI_CS2 PQSPI5 U2RTS — O
QSPI_CS1 PQSPI4 PWM7 USBOTG_
EVDD
EVDD
O
PU_EN
QSPI_CS0 PQSPI3 PWM5 — O
QSPI_CLK PQSPI2 I2C_SCL
2
— O
QSPI_DIN PQSPI1 U2CTS — I
QSPI_DOUT PQSPI0 I2C_SDA — O
EVDD
EVDD
EVDD
EVDD
UARTs
U1CTS PUARTL7 SSI_BCLK — I
U1RTS PUARTL6 SSI_FS — O
U1TXD PUARTL5 SSI_TXD
U1RXD PUARTL4 SSI_RXD
2
2
— O
— I
U0CTS PUARTL3 — — I
U0RTS PUARTL2 — — O
U0TXD PUARTL1 — — O
U0RXD PUARTL0 — — I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.
MCF53281
MCF5329
256
MAPBGA
196
MCF5328
256
MAPBGA
P10 T12 T12
L11 T13 T13
— P11 P11
N10 R12 R12
L10 N12 N12
M10 P12 P12
C9 D11 D11
D9 E10 E10
A9 E11 E11
A10 E12 E12
P13 R15 R15
N12 T15 T15
P12 T14 T14
P11 R14 R14
DMA Timers
DT3IN PTIMER3 DT3OUT U2RXD I
DT2IN PTIMER2 DT2OUT U2TXD I
DT1IN PTIMER1 DT1OUT DACK1 I
DT0IN PTIMER0 DT0OUT DREQ0
2
BDM/JTAG
JTAG_EN
DSCLK — TRST
PSTCLK — TCLK
7
— — — I
BKPT — TMS
DSI — TDI
2
2
2
2
— I
— O
— I
— I
DSO — TDO — O
DDATA[3:0] — — — O
EVDD
EVDD
EVDD
EVDD
I
6
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
C1 F1 F1
B1 E1 E1
A1 E2 E2
C2 E3 E3
L12 M13 M13
N14 P15 P15
L7 T9 T9
M12 R16 R16
K12 N14 N14
N9 N11 N11
N7, P7, L8, M8N9, P9, N10,
P10
N9, P9, N10,
P10
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor 11
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
MAPBGA
R10, T10,
R11, T11
Signal Name GPIO Alternate 1 Alternate 2
PST[3:0] — — — O
1
Dir.
EVDD
MCF5327
196
MAPBGA
Volta ge
Domain
N8, P8, L9, M9R10, T10,
MCF5328
256
MAPBGA
R11, T11
Test
7
TEST
PLL_TEST
— — — I
8
— — — I
EVDD
EVDD
E10 A16 A16
— N13 N13
Power Supplies
EVDD — — — — — E6, E7,
F5–F7, H9,
J8, J9, K8,
K9, K11
E8, F5–F8,
G5, G6, H5,
H6, J11,
K11, K12,
L9–L11, M9,
E8, F5–F8,
G5, G6, H5,
H6, J11,
K11, K12,
L9–L11, M9,
M10
IVDD — — — — — E5, K5, K10,
J10
E5, G12, M5,
M11, M12
E5, G12, M5,
M11, M12
PLL_VDD — — — — — H10 J12 J12
SD_VDD — — — — — E8, E9,
F8–F10,
J5–J7, K7
E9, F9–F11,
G11, H11,
J5, J6, K5,
K6, L5–L8,
M6, M7
E9, F9–F11,
G11, H11,
J5, J6, K5,
K6, L5–L8,
M6, M7
USB_VDD — — — — — G10 L14 L14
256
M10
VSS — — — — — G6–G9,
H6–H8, P9
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
PLL_VSS — — — — — H11 K13 K13
USB_VSS — — — — — H12 M14 M14
1
Refers to pin’s primary function.
2
Pull-up enabled internally on this signal for this mode.
3
The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor
when accessing SDRAM memory space and are included here for completeness.
4
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating
the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
5
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
6
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.
7
Pull-down enabled internally on this signal for this mode.
8
Must be left floating for proper operation of the PLL.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor12
Pin Assignments and Reset States
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor 13
Pin Assignments and Reset States
NOTE
4.2 Pinout—256 MAPBGA
Figure 4 shows a pinout of the MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 devices.
NOTE
The pin at location N13 (PLL_TEST) must be left floating or improper operation of the
PLL module occurs.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
FEC_
B
TXER
FEC_
C
MDC
FEC_
D
TXD1
EDT2IN DT1IN DT0IN
FDT3IN
SSI_
G
TXD
SD_
H
CS0
J
D13 D14
K
SD_
L
DQS3
FEC_
NC
TXCLK
FEC_
TXEN
FEC_
MDIO
FEC_
TXD2
I2C_
SDA
SSI_
RXD
SD_CKE
D9 D10 D11 D12 SD_VDD SD_VDD VSS VSS VSS VSS EVDD EVDD
D8
LCD_D4LCD_D5LCD_D9FEC_
RXD2
LCD_D1LCD_D3LCD_D8FEC_
RXD1
LCD_D0LCD_D2LCD_D7FEC_
RXD0
FEC_
TXD3
I2C_
SCL
SSI_FS
SD_WE
D15 SD_CS1
BE/
BWE1
FEC_
RXER
FEC_
TXD0
SSI_
BCLK
SSI_
MCLK
BWE3
LCD_D6LCD_
IVDD
EVDD EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD NC A6 A5 A4 A3 F
EVDD EVDD VSS VSS VSS VSS SD_VDD IVDD
TS
EVDD EVDD VSS VSS VSS VSS SD_VDD
SD_VDD SD_VDD VSS VSS VSS VSS EVDD
BE/
SD_VDD SD_VDD SD_VDD SD_VDD EVDD EVDD EVDD VSS
LCD_
D11
D10
LCD_
D15
LCD_
D14
LCD_
D13
LCD_
D12
FEC_
RXD3
FEC_
COL
FEC_
CRS
FEC_
RXCLK
FEC_
RXDV
EVDD SD_VDD
LCD_
CLS
LCD_
ACD/OE
LCD_
D17
LCD_
D16
LCD_
LSCLK
LCD_LP/
HSYNC
LCD_FLM/
VSYNC
LCD_CON
TRAST
U1RTS
LCD_
PS
LCD_
REV
LCD_
SPL_SPR
U1CTS
U1TXD U1RXD A21 A9 A8 A7 E
FB_CS3
FB_CS2
FB_CS1
FB_CS0
DRAM
SEL
PLL_
VDD
FB_CS4
FB_CS5
A23 A18 A13 A12 C
A22 A15 A11 A10 D
TA
PWM7 PWM5 PWM3 PWM1 H
IRQ7
PLL_
VSS
USB_
VSS
A20 A17 TEST A
A19 A16 A14 B
A0 A1 A2 G
IRQ6 IRQ5 IRQ4
IRQ3
USBOTG
_VDD
IRQ2 IRQ1
USB
OTG_M
OTG_P
USB
J
K
L
JTAG_
D31 D30 D29 D28 IVDD SD_VDD SD_VDD
M
D27 D26 D25 D24 D19
N
SD_DR
P
R SD_CLK
T NC FB_CLK D23 D20 D16
SD_A10 SD_CAS
_DQS
SD_CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SD_RAS
D22 D18
D21 D17 D7 D4 D1
BE/
BWE0
BE/
BWE2
SD_
DQS2
RCON
D6
D5 D2 DDATA2 DDATA0
D3 D0
EVDD EVDD IVDD IVDD
R/W
DDATA3 DDATA1
OE
TCLK/
PSTCLK
PST3
PST2 PST0
TDO/
DSO
QSPI_
CS0
PST1
QSPI_
DIN
QSPI_
DOUT
QSPI_
CLK
QSPI_
CS2
EN
PLL_
TEST
EXTAL
32K
XTAL
32K
QSPI_
CS1
USBHOST
_VSS
TDI/DSI RESET
RSTOUT
U0RXD
U0TXD
Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA)
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor14
USB
HOST_M
TRST/
DSCLK
U0CTS
U0RTS
USB
HOST_P
XTAL N
EXTAL P
TMS/
BKPT
NC T
M
R
Electrical Characteristics
4.3 Pinout—196 MAPBGA
The pinout for the MCF5327CVM240 package is shown below.
12 3 4 56 7 8 9 101112 1314
A
DT1IN
B
D2TIN
C
DT3IN DT0IN
D
SD_WE
E
SD_CKE SD_CS0
F
D12 D13 D14 D15 EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD A4 A3 A2 A1
G
BE/
BWE1
H
D29 D30 D31
J
D25 D26 D27 D28 SD_VDD SD_VDD SD_VDD EVDD EVDD IVDD RESET
K
D24 SD_CLK SD_CLK
L
FB_CLK SD_A10 SD_CAS
LCD_D4LCD_D5LCD_D9LCD_
LCD_D0LCD_D6LCD_D8LCD_
LCD_D2LCD_D7LCD_
TS
D8 D9 D10 D11 VSS VSS VSS VSS
LCD_D1LCD_D3LCD_
I2C_SCL I2C_SDA IVDD EVDD EVDD SD_VDD SD_VDD TEST A8 A7 A6 A5
BE/
BWE3
SD_DR_
DQS
D23 D7 D1
SD_
DQS3
IVDD
D13
D12
D11
D10
LCD_
LCD_FLM/
D17
VSYNC
LCD_
LCD_CON
D16
LCD_
D15
LCD_
D14
VSS VSS VSS EVDD
SD_
DQS2
TRAST
ACD/OE
SD_VDD EVDD EVDD IVDD EVDD TDI/DSI
TCLK/
PSTCLK
LCD_
CLS
LCD_
LCD_LP/
HSYNC
LCD_
LSCLK
LCD_
LCD_
REV
DDATA1 PST1
U1TXD U1RXD FB_CS3
LCD_
SPL_SPR
U1CTS
PS
U1RTS
A20 A16 A15
FB_CS0
FB_CS1 A22 A18 A13 A12
FB_CS2 A19 A11 A10 A9
USB
OTG_VDD
PLL_
VDD
QSPI_
DIN
A23 A21 A17 A14
DRAM
SEL
PLL_
VSS
QSPI_
CS1
USB
OTG_ M
USBHOST
_VSS
USB
HOST_P
JTAG_
EN
USB
OTG_ P
IRQ7
USB
HOST_M
IRQ4 EXTAL
TA A0
PWM3
PWM1
XTAL
A
B
C
D
E
F
G
H
J
K
L
M
SD_RAS
N
D20 D19 D16 D6 D3 R/W DDATA3 PST3
P
D18 D17
D22 D21
BE/
BWE2
12 3 4 56 7 8 9 101112 1314
BE/
BWE0
D5 D2 OE DDATA2 PST2 VSS
D4 D0 RCON DDATA0 PST0
TDO/
DSO
QSPI_
DOUT
QSPI_
CLK
QSPI_
CS2
EXTAL
32K
XTAL
32K
U0RXD U0TXD U0CTS
TMS/
BKPT
U0RTS IRQ1
IRQ2 IRQ3
TRST/
DSCLK
RSTOUT
Figure 5. MCF5327CVM240 Pinout Top View (196 MAPBGA)
5 Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit.
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications of MCF5329.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications
will be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4
M
N
P
Freescale Semiconductor 15
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