Freescale MCF5329 User Manual

Freescale Semiconductor

MAPBGA–256
17mm x 17mm

MAPBGA–196
15mm x 15mm

Data Sheet: Technical Data

MCF532x ColdFire®
Microprocessor Data Sheet

Features

• Version 3 ColdFire variable-length RISC processor core

• System debug support

• JTAG support for system level board testing

• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,

accessible by core and non-core bus masters (e.g., DMA,
FEC, LCD controller, and USB host and OTG)

• Power management

• Liquid Crystal Display Controller (LCDC)

• Embedded Voice-over-IP (VoIP) system solution

• SDR/DDR SDRAM Controller

• Universal Serial Bus (USB) Host Controller

• Universal Serial Bus (USB) On-the-Go (OTG) controller

• Synchronous Serial Interface (SSI)

• Fast Ethernet Controller (FEC)

• Cryptography Hardware Accelerators

• FlexCAN Module

• Three Universal Asynchronous Receiver Transmitters
(UARTs)

2

•I

C Module

• Queued Serial Peripheral Interface (QSPI)

• Pulse Width Modulation (PWM) module

• Real Time Clock

• Four 32-bit DMA Timers

• Software Watchdog Timer

• Four Periodic Interrupt Timers (PITs)

• Phase Locked Loop (PLL)

• Interrupt Controllers (x2)

• DMA Controller

• FlexBus (External Interface)

• Chip Configuration Module (CCM)

• Reset Controller

• General Purpose I/O interface

Document Number: MCF5329DS

Rev. 4, 04/2008

MCF5329

© Freescale Semiconductor, Inc., 2008. All rights reserved.

Table of Contents

1MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3 Supply Voltage Sequencing and Separation Cautions . .5

3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5

3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6

4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6

4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .14

4.3 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15

5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17

5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . 18

5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .19

5.6 External Interface Timing Characteristics . . . . . . . . . . .20

5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .23

5.7.2 DDR SDRAM AC Timing Characteristics . . . . . 25

5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 28

5.9 Reset and Configuration Override Timing . . . . . . . . . . 29

5.10 LCD Controller Timing Specifications . . . . . . . . . . . . . 30

5.11 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.12 ULPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . 33

5.13 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 33

2

5.14 I

C Input/Output Timing Specifications . . . . . . . . . . . . 35

5.15 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37

5.15.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 37

5.15.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . 37

5.15.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 38

5.15.4 MII Serial Management Channel Timing . . . . . 38

5.16 32-Bit Timer Module Timing Specifications . . . . . . . . . 39

5.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 39

5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40

5.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42

6 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.1 Package Dimensions—256 MAPBGA . . . . . . . . . . . . . 46

7.2 Package Dimensions—196 MAPBGA . . . . . . . . . . . . . 47

8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor2

MCF532x Family Comparison

FlexBus

D[31:0]
A[23:0]

R/W

CS[5:0]
TA

TS

XBS

M2

M1 M0

M5

PWMs, EPORT,

JTAG
TAP

TRST
TCLK
TMS

TDI

TDO

Cache

(1024x32)x4

DMA

UARTs

FlexCAN

I2C

QSPI

DMA Timers

Watchdog, PITs

PADI — Pin Muxing

EXTAL

XTAL

CLKOUT

16 KByte

Chip

External

Selects

(To/From PADI)

CANTX

CANRX

FEC

FEC

DMA Timer

SDRAMC

UART

I

2

C

SDRAMC
QSPI

JTAG_EN

RTC

USB Host

M4

LCDC

S4

S7

S1

Reset

PORTS

SDRAMC

SSI

LCDC

USB OTG

RESET

SRAM

(4096x32)x2

32 KByte

PLL

S6

SDRAMC

M6

USB Host

USB OTG

ULPI Interface

INTC0

INTC1

RCON

LCDC

SSI

V3 ColdFire CPU

DIV EMAC

BDM

(To/From PADI)

RNGA

SKHA

MDHA

Cryptography

Modules

Interface

RSTOUT

EXTAL32K

XTAL32K

(To/From SRAM backdoor)

(To/From XBS backdoor)

DREQ

n

DACKn

(To/From PADI)

USB Host

USB OTG

BE/BWE[3:0]

PWM

XCVR XCVR

(To/From PADI)

1 MCF532x Family Comparison

The following table compares the various device derivatives available within the MCF532x family.

Freescale Semiconductor 3

ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)

Core (System) Clock up to 240 MHz

Peripheral and External Bus Clock
(Core clock ÷ 3)

Performance (Dhrystone/2.1 MIPS) up to 211

Unified Cache 16 Kbytes

Static RAM (SRAM) 32 Kbytes

Figure 1. MCF5329 Block Diagram

Table 1. MCF532x Family Configurations

Module MCF5327 MCF5328 MCF53281 MCF5329

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

••••

up to 80 MHz

Ordering Information

LCD Controller • • • •

SDR/DDR SDRAM Controller • • • •

USB 2.0 Host • • • •

USB 2.0 On-the-Go • • • •

UTMI+ Low Pin Interface (ULPI) — • • •

Synchronous Serial Interface (SSI) • • • •

Fast Ethernet Controller (FEC) — • • •

Cryptography Hardware Accelerators — — — •

Embedded Voice-over-IP System Solution — — • —

FlexCAN 2.0B communication module — — • •

UARTs 3333

2

C ••••

I

QSPI • • • •

PWM Module • • • •

Real Time Clock • • • •

32-bit DMA Timers 4444

Table 1. MCF53 2 x Family Configurations (continued)

Module MCF5327 MCF5328 MCF53281 MCF5329

Watchdog Timer (WDT) • • • •

Periodic Interrupt Timers (PIT) 4444

Edge Port Module (EPORT) • • • •

Interrupt Controllers (INTC) 2222

16-channel Direct Memory Access (DMA) • • • •

FlexBus External Interface • • • •

General Purpose I/O Module (GPIO) • • • •

®

JTAG - IEEE

Package 196

1149.1 Test Access Port • • • •

MAPBGA

256

MAPBGA

256

MAPBGA

2 Ordering Information

Table 2. Orderable Part Numbers

Freescale Part

Number

MCF5327CVM240 MCF5327 RISC Microprocessor 196 MAPBGA 240 MHz –40

MCF5328CVM240 MCF5328 RISC Microprocessor 256 MAPBGA 240 MHz –40

MCF53281CVM240 MCF53281 RISC Microprocessor 256 MAPBGA 240 MHz –40

MCF5329CVM240 MCF5329 RISC Microprocessor 256 MAPBGA 240 MHz –40

Description Package Speed Temperature

256

MAPBGA

° to +85° C

° to +85° C

° to +85° C

° to +85° C

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor4

Hardware Design Considerations

Board IV

DD

10 Ω

0.1 µF

PLL V

DD

Pin

10 µF

GND

Board EV

DD

0 Ω

0.1 µF

USB V

DD

Pin

10 µF

GND

3 Hardware Design Considerations

3.1 PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in

Figure 2 should be connected between the board V

close to the dedicated PLLV

pin as possible.

DD

and the PLLVDD pins. The resistor and capacitors should be placed as

DD

Figure 2. System PLL V

Power Filter

DD

3.2 USB Power Filtering

To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EV
close to the dedicated USBV

or IV

DD

pin as possible.

DD

and each of the USBVDD pins. The resistor and capacitors should be placed as

DD

Figure 3. USB V

Power Filter

DD

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.

3.3 Supply Voltage Sequencing and Separation Cautions

The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or

3.3V) and EV

are specified relative to IVDD.

DD

3.3.1 Power Up Sequence

If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
the EV
must powered up. IV

Freescale Semiconductor 5

/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD

DD

should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is

DD

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Pin Assignments and Reset States

high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.

3.3.2 Power Down Sequence

If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IV
not lag EV

, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the

DD

and PLLVDD power down before EVDD or SDVDD must power down. IVDD should

DD

ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV

2. Drop EV

/PLLVDD to 0 V.

DD

/SDVDD supplies.

DD

4 Pin Assignments and Reset States

4.1 Signal Multiplexing

The following table lists all the MCF532x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the
MCF532x signals, consult the MCF5329 Reference Manual (MCF5329RM).

NOTE

In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.

Table 3. MCF5327/8/9 Signal Information and Muxing

Signal Name GPIO Alternate 1 Alternate 2

Reset

RESET

RSTOUT — — — O

EXTAL32K — — — I

XTAL32K — — — O

FB_CLK — — — O

2

EXTAL — — — I

2

XTAL

— — — I

Clock

— — — O

1

Dir.

Voltage

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

SDVDD

MCF5327

196

MAPBGA

Domain

J11 N15 N15

P14 P14 P14

L14 P16 P16

K14 N16 N16

M11 P13 P13

N11 R13 R13

L1 T2 T2

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor6

Pin Assignments and Reset States

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Mode Selection

2

RCON

— — — I

DRAMSEL — — — I

FlexBus

A[23:22] — FB_CS

[5:4] — O

A[21:16] — — — O

A[15:14] — SD_BA[1:0]

A[13:11] — SD_A[13:11]

3

3

—O

—O

A10 — — — O

A[9:0] — SD_A[9:0]

D[31:16] — SD_D[31:16]

D[15:1] — FB_D[31:17]

2

D0

BE/BWE

OE

TA

R/W

[3:0] PBE[3:0] SD_DQM[3:0]

2

— FB_D[16]

PBUSCTL3 — — O

PBUSCTL2 — — I

PBUSCTL1 — — O

3

4

4

4

3

—O

— I/O

— I/O

— I/O

— O

TS PBUSCTL0 DACK0 —O

1

Dir.

Volta ge

EVDD

EVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

MCF5327

MAPBGA

Domain

196

MCF5328

256

MAPBGA

MCF53281

MCF5329

MAPBGA

M7 M8 M8

G11 H12 H12

B11,C11 C13, D13 C13, D13

B12, A12,
D11, C12,

B13, A13

E13, A14,
B14, C14,

A15, B15

E13, A14,
B14, C14,

A15, B15

A14, B14 D14, B16 D14, B16

C13, C14,

D12

C15, C16,

D15

C15, C16,

D13 D16 D16

D14,

E11–14,

F11–F14,

E14–E16,
F13–F16,

G16– G14

E14–E16,
F13–F16,

G16– G14

G14

H3–H1,

J4–J1, K1,
L4, M2, M3,
N1, N2, P1,

P2, N3

F4–F1,
G5–G2, L5,
N4, P4, M5,

N5, P5, L6

M1–M4,
N1–N4, T3,
P4, R4, T4,
N5, P5, R5,

T5

J3–J1,

K4–K1, L2,
R6, N7, P7,
R7, T7, P8,

M1–M4,
N1–N4, T3,
P4, R4, T4,
N5, P5, R5,

J3–J1,

K4–K1, L2,
R6, N7, P7,
R7, T7, P8,

R8

M6 T8 T8

H4, P3, G1, M4L4, P6, L3, N6L4, P6, L3,

P6 R9 R9

G13 G13 G13

N6 N8 N8

D2 H4 H4

256

D15

T5

R8

N6

Chip Selects

FB_CS

[5:4] PCS[5:4] — — O

[3:1] PCS[3:1] O

FB_CS

FB_CS0

———O

SDVDD

SDVDD

SDVDD

— B13, A13 B13, A13

A11, D10,

C10

A12, B12,

C12

A12, B12,

B10 D12 D12

C12

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 7

Pin Assignments and Reset States

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

SDRAM Controller

SD_A10 — — — O

SD_CKE — — — O

SD_CLK — — — O

SD_CLK

SD_CS1

SD_CS0

———O

———O

———O

SD_DQS3 — — — O

SD_DQS2 — — — O

SD_SCAS

SD_SRAS

———O

———O

SD_SDR_DQS — — — O

SD_WE

———O

External Interrupts Port

IRQ7

IRQ6

2

2

PIRQ7

PIRQ6

2

2

— — I

USBHOST_

— I

VBUS_EN

IRQ5

2

PIRQ5

2

USBHOST_

— I

VBUS_OC

IRQ4

IRQ3

IRQ2

IRQ1

2

2

2

2

PIRQ4

PIRQ3

PIRQ2

PIRQ1

2

2

2

2

SSI_MCLK — I

— — I

USB_CLKIN — I

DREQ1

2

SSI_CLKIN I

1

Dir.

Volta ge

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

SDVDD

5

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

MCF5327

MAPBGA

Domain

196

MCF5328

256

MAPBGA

L2 P2 P2

E1 H2 H2

K3 R1 R1

K2 R2 R2

— J4 J4

E2 H1 H1

H5 L1 L1

K6 T6 T6

L3 P3 P3

M1 R3 R3

K4 P1 P1

D1 H3 H3

J13 J13 J13

— J14 J14

— J15 J15

L13 J16 J16

M14 K14 K14

M13 K15 K15

N13 K16 K16

MCF53281

MCF5329

256

MAPBGA

FEC

FEC_MDC PFECI2C3 I2C_SCL

FEC_MDIO PFECI2C2 I2C_SDA

2

2

— O

— I/O

FEC_TXCLK PFECH7 — — I

FEC_TXEN PFECH6 — — O

FEC_TXD0 PFECH5 ULPI_DATA0 — O

FEC_COL PFECH4 ULPI_CLK — I

FEC_RXCLK PFECH3 ULPI_NXT — I

FEC_RXDV PFECH2 ULPI_STP — I

FEC_RXD0 PFECH1 ULPI_DATA4 — I

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

— C1 C1

— C2 C2

— A2 A2

— B2 B2

— E4 E4

— A8 A8

— C8 C8

— D8 D8

— C6 C6

Freescale Semiconductor8

Pin Assignments and Reset States

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

FEC_CRS PFECH0 ULPI_DIR — I

FEC_TXD[3:1] PFECL[7:5] ULPI_DATA[3:1] — O

FEC_TXER PFECL4 — — O

FEC_RXD[3:1] PFECL[3:1] ULPI_DATA[7:5] — I

FEC_RXER PFECL0 — — I

LCD Controller

LCD_D17 PLCDDH1 CANTX — O

LCD_D16 PLCDDH0 CANRX — O

LCD_D17 PLCDDH1 — — O

LCD_D16 PLCDDH0 — — O

LCD_D15 PLCDDM7 — — O

LCD_D14 PLCDDM6 — — O

LCD_D13 PLCDDM5 — — O

LCD_D12 PLCDDM4 — — O

LCD_D[11:8] PLCDDM[3:0] — — O

LCD_D7 PLCDDL7 — — O

LCD_D6 PLCDDL6 — — O

LCD_D5 PLCDDL5 — — O

LCD_D4 PLCDDL4 — — O

LCD_D[3:0] PLCDDL[3:0] — — O

LCD_ACD/

PLCDCTLH0 — — O

LCD_OE

LCD_CLS PLCDCTLL7 — — O

LCD_CONTRAST PLCDCTLL6 — — O

LCD_FLM/

PLCDCTLL5 — — O

LCD_VSYNC

LCD_LP/

PLCDCTLL4 — — O

LCD_HSYNC

LCD_LSCLK PLCDCTLL3 — — O

LCD_PS PLCDCTLL2 — — O

LCD_REV PLCDCTLL1 — — O

LCD_SPL_SPR PLCDCTLL0 — — O

1

Dir.

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

MCF5327

196

MAPBGA

Volta ge

Domain

— B8 B8

— D3–D1 D3–D1

— B1 B1

— E7, A6, B6 E7, A6, B6

— D4 D4

— — C9

— — D9

A6 C9 —

B6 D9 —

C6 A7 A7

D6 B7 B7

A5 C7 C7

B5 D7 D7

C5, D5, A4, B4D6, E6, A5, B5D6, E6, A5,

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

B5

EVDD

EVDD

EVDD

EVDD

EVDD

C4 C5 C5

B3 D5 D5

A3 A4 A4

A2 A3 A3

D4, C3, D3, B2B4, C4, B3, C3B4, C4, B3,

C3

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

D7 B9 B9

C7 A9 A9

B7 D10 D10

A7 C10 C10

A8 B10 B10

B8 A10 A10

C8 A11 A11

D8 B11 B11

B9 C11 C11

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 9

Pin Assignments and Reset States

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

1

USB Host & USB On-the-Go

USBOTG_M — — — I/O

USBOTG_P — — — I/O

USBHOST_M — — — I/O

USBHOST_P — — — I/O

FlexCAN (MCF53281 & MCF5329 only)

CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:

I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX.

PWM

PWM7 PPWM7 — — I/O

PWM5 PPWM5 — — I/O

PWM3 PPWM3 DT3OUT DT3IN I/O

PWM1 PPWM1 DT2OUT DT2IN I/O

MCF5327

Dir.

Volta ge

Domain

USB
VDD

USB
VDD

USB
VDD

USB
VDD

EVDD

EVDD

EVDD

EVDD

196

MAPBGA

G12 L15 L15

H13 L16 L16

K13 M15 M15

J12 M16 M16

— H13 H13

— H14 H14

H14 H15 H15

J14 H16 H16

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

SSI

SSI_MCLK PSSI4 — — I/O

SSI_BCLK PSSI3 U2CTS PWM7 I/O

SSI_FS PSSI2 U2RTS PWM5 I/O

SSI_RXD

SSI_TXD

SSI_RXD

SSI_TXD

2

2

2

2

PSSI1 U2RXD CANRX I

PSSI0 U2TXD CANTX O

PSSI1 U2RXD — I

PSSI0 U2TXD — O

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

— G4 G4

— F4 F4

— G3 G3

— — G2

— — G1

— G2 —

— G1 —

I2C

I2C_SCL

I2C_SDA

I2C_SCL

I2C_SDA

2

2

2

2

PFECI2C1 CANTX U2TXD I/O

PFECI2C0 CANRX U2RXD I/O

PFECI2C1 — U2TXD I/O

PFECI2C0 — U2RXD I/O

EVDD

EVDD

EVDD

EVDD

— — F3

— — F2

E3 F3 —

E4 F2 —

DMA

DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:

TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor10

Pin Assignments and Reset States

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Volta ge

Domain

MCF5327

MAPBGA

Signal Name GPIO Alternate 1 Alternate 2

1

Dir.

QSPI

QSPI_CS2 PQSPI5 U2RTS — O

QSPI_CS1 PQSPI4 PWM7 USBOTG_

EVDD

EVDD

O

PU_EN

QSPI_CS0 PQSPI3 PWM5 — O

QSPI_CLK PQSPI2 I2C_SCL

2

— O

QSPI_DIN PQSPI1 U2CTS — I

QSPI_DOUT PQSPI0 I2C_SDA — O

EVDD

EVDD

EVDD

EVDD

UARTs

U1CTS PUARTL7 SSI_BCLK — I

U1RTS PUARTL6 SSI_FS — O

U1TXD PUARTL5 SSI_TXD

U1RXD PUARTL4 SSI_RXD

2

2

— O

— I

U0CTS PUARTL3 — — I

U0RTS PUARTL2 — — O

U0TXD PUARTL1 — — O

U0RXD PUARTL0 — — I

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.

MCF53281

MCF5329

256

MAPBGA

196

MCF5328

256

MAPBGA

P10 T12 T12

L11 T13 T13

— P11 P11

N10 R12 R12

L10 N12 N12

M10 P12 P12

C9 D11 D11

D9 E10 E10

A9 E11 E11

A10 E12 E12

P13 R15 R15

N12 T15 T15

P12 T14 T14

P11 R14 R14

DMA Timers

DT3IN PTIMER3 DT3OUT U2RXD I

DT2IN PTIMER2 DT2OUT U2TXD I

DT1IN PTIMER1 DT1OUT DACK1 I

DT0IN PTIMER0 DT0OUT DREQ0

2

BDM/JTAG

JTAG_EN

DSCLK — TRST

PSTCLK — TCLK

7

— — — I

BKPT — TMS

DSI — TDI

2

2

2

2

— I

— O

— I

— I

DSO — TDO — O

DDATA[3:0] — — — O

EVDD

EVDD

EVDD

EVDD

I

6

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

C1 F1 F1

B1 E1 E1

A1 E2 E2

C2 E3 E3

L12 M13 M13

N14 P15 P15

L7 T9 T9

M12 R16 R16

K12 N14 N14

N9 N11 N11

N7, P7, L8, M8N9, P9, N10,

P10

N9, P9, N10,

P10

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 11

Pin Assignments and Reset States

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF53281

MCF5329

MAPBGA

R10, T10,

R11, T11

Signal Name GPIO Alternate 1 Alternate 2

PST[3:0] — — — O

1

Dir.

EVDD

MCF5327

196

MAPBGA

Volta ge

Domain

N8, P8, L9, M9R10, T10,

MCF5328

256

MAPBGA

R11, T11

Test

7

TEST

PLL_TEST

— — — I

8

— — — I

EVDD

EVDD

E10 A16 A16

— N13 N13

Power Supplies

EVDD — — — — — E6, E7,

F5–F7, H9,

J8, J9, K8,

K9, K11

E8, F5–F8,

G5, G6, H5,

H6, J11,

K11, K12,

L9–L11, M9,

E8, F5–F8,

G5, G6, H5,

H6, J11,

K11, K12,

L9–L11, M9,

M10

IVDD — — — — — E5, K5, K10,

J10

E5, G12, M5,

M11, M12

E5, G12, M5,

M11, M12

PLL_VDD — — — — — H10 J12 J12

SD_VDD — — — — — E8, E9,

F8–F10,

J5–J7, K7

E9, F9–F11,

G11, H11,
J5, J6, K5,

K6, L5–L8,

M6, M7

E9, F9–F11,

G11, H11,
J5, J6, K5,

K6, L5–L8,

M6, M7

USB_VDD — — — — — G10 L14 L14

256

M10

VSS — — — — — G6–G9,

H6–H8, P9

G7–G10,
H7–H10,

J7–10,
K7–K10,
L12, L13

G7–G10,

H7–H10,

J7–10,
K7–K10,
L12, L13

PLL_VSS — — — — — H11 K13 K13

USB_VSS — — — — — H12 M14 M14

1

Refers to pin’s primary function.

2

Pull-up enabled internally on this signal for this mode.

3

The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor
when accessing SDRAM memory space and are included here for completeness.

4

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating
the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

5

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.

6

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.

7

Pull-down enabled internally on this signal for this mode.

8

Must be left floating for proper operation of the PLL.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor12

Pin Assignments and Reset States

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 13

Pin Assignments and Reset States

NOTE

4.2 Pinout—256 MAPBGA

Figure 4 shows a pinout of the MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 devices.

NOTE

The pin at location N13 (PLL_TEST) must be left floating or improper operation of the
PLL module occurs.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A

FEC_

B

TXER

FEC_

C

MDC

FEC_

D

TXD1

EDT2IN DT1IN DT0IN

FDT3IN

SSI_

G

TXD

SD_

H

CS0

J

D13 D14

K

SD_

L

DQS3

FEC_

NC

TXCLK

FEC_

TXEN

FEC_

MDIO

FEC_

TXD2

I2C_

SDA

SSI_

RXD

SD_CKE

D9 D10 D11 D12 SD_VDD SD_VDD VSS VSS VSS VSS EVDD EVDD

D8

LCD_D4LCD_D5LCD_D9FEC_

RXD2

LCD_D1LCD_D3LCD_D8FEC_

RXD1

LCD_D0LCD_D2LCD_D7FEC_

RXD0

FEC_

TXD3

I2C_

SCL

SSI_FS

SD_WE

D15 SD_CS1

BE/

BWE1

FEC_

RXER

FEC_

TXD0

SSI_

BCLK

SSI_

MCLK

BWE3

LCD_D6LCD_

IVDD

EVDD EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD NC A6 A5 A4 A3 F

EVDD EVDD VSS VSS VSS VSS SD_VDD IVDD

TS

EVDD EVDD VSS VSS VSS VSS SD_VDD

SD_VDD SD_VDD VSS VSS VSS VSS EVDD

BE/

SD_VDD SD_VDD SD_VDD SD_VDD EVDD EVDD EVDD VSS

LCD_

D11

D10

LCD_

D15

LCD_

D14

LCD_

D13

LCD_

D12

FEC_

RXD3

FEC_

COL

FEC_

CRS

FEC_

RXCLK

FEC_

RXDV

EVDD SD_VDD

LCD_

CLS

LCD_

ACD/OE

LCD_

D17

LCD_

D16

LCD_

LSCLK

LCD_LP/

HSYNC

LCD_FLM/

VSYNC

LCD_CON

TRAST

U1RTS

LCD_

PS

LCD_

REV

LCD_

SPL_SPR

U1CTS

U1TXD U1RXD A21 A9 A8 A7 E

FB_CS3

FB_CS2

FB_CS1

FB_CS0

DRAM

SEL

PLL_

VDD

FB_CS4

FB_CS5

A23 A18 A13 A12 C

A22 A15 A11 A10 D

TA

PWM7 PWM5 PWM3 PWM1 H

IRQ7

PLL_

VSS

USB_

VSS

A20 A17 TEST A

A19 A16 A14 B

A0 A1 A2 G

IRQ6 IRQ5 IRQ4

IRQ3

USBOTG

_VDD

IRQ2 IRQ1

USB

OTG_M

OTG_P

USB

J

K

L

JTAG_

D31 D30 D29 D28 IVDD SD_VDD SD_VDD

M

D27 D26 D25 D24 D19

N

SD_DR

P

R SD_CLK

T NC FB_CLK D23 D20 D16

SD_A10 SD_CAS

_DQS

SD_CLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SD_RAS

D22 D18

D21 D17 D7 D4 D1

BE/

BWE0

BE/

BWE2

SD_

DQS2

RCON

D6

D5 D2 DDATA2 DDATA0

D3 D0

EVDD EVDD IVDD IVDD

R/W

DDATA3 DDATA1

OE

TCLK/

PSTCLK

PST3

PST2 PST0

TDO/

DSO

QSPI_

CS0

PST1

QSPI_

DIN

QSPI_

DOUT

QSPI_

CLK

QSPI_

CS2

EN

PLL_

TEST

EXTAL

32K

XTAL

32K

QSPI_

CS1

USBHOST

_VSS

TDI/DSI RESET

RSTOUT

U0RXD

U0TXD

Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA)

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor14

USB

HOST_M

TRST/

DSCLK

U0CTS

U0RTS

USB

HOST_P

XTAL N

EXTAL P

TMS/

BKPT

NC T

M

R

Electrical Characteristics

4.3 Pinout—196 MAPBGA

The pinout for the MCF5327CVM240 package is shown below.

12 3 4 56 7 8 9 101112 1314

A

DT1IN

B

D2TIN

C

DT3IN DT0IN

D

SD_WE

E

SD_CKE SD_CS0

F

D12 D13 D14 D15 EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD A4 A3 A2 A1

G

BE/

BWE1

H

D29 D30 D31

J

D25 D26 D27 D28 SD_VDD SD_VDD SD_VDD EVDD EVDD IVDD RESET

K

D24 SD_CLK SD_CLK

L

FB_CLK SD_A10 SD_CAS

LCD_D4LCD_D5LCD_D9LCD_

LCD_D0LCD_D6LCD_D8LCD_

LCD_D2LCD_D7LCD_

TS

D8 D9 D10 D11 VSS VSS VSS VSS

LCD_D1LCD_D3LCD_

I2C_SCL I2C_SDA IVDD EVDD EVDD SD_VDD SD_VDD TEST A8 A7 A6 A5

BE/

BWE3

SD_DR_

DQS

D23 D7 D1

SD_

DQS3

IVDD

D13

D12

D11

D10

LCD_

LCD_FLM/

D17

VSYNC

LCD_

LCD_CON

D16

LCD_

D15

LCD_

D14

VSS VSS VSS EVDD

SD_

DQS2

TRAST

ACD/OE

SD_VDD EVDD EVDD IVDD EVDD TDI/DSI

TCLK/

PSTCLK

LCD_

CLS

LCD_

LCD_LP/

HSYNC

LCD_

LSCLK

LCD_

LCD_

REV

DDATA1 PST1

U1TXD U1RXD FB_CS3

LCD_

SPL_SPR

U1CTS

PS

U1RTS

A20 A16 A15

FB_CS0

FB_CS1 A22 A18 A13 A12

FB_CS2 A19 A11 A10 A9

USB

OTG_VDD

PLL_

VDD

QSPI_

DIN

A23 A21 A17 A14

DRAM

SEL

PLL_

VSS

QSPI_

CS1

USB

OTG_ M

USBHOST

_VSS

USB

HOST_P

JTAG_

EN

USB

OTG_ P

IRQ7

USB

HOST_M

IRQ4 EXTAL

TA A0

PWM3

PWM1

XTAL

A

B

C

D

E

F

G

H

J

K

L

M

SD_RAS

N

D20 D19 D16 D6 D3 R/W DDATA3 PST3

P

D18 D17

D22 D21

BE/

BWE2

12 3 4 56 7 8 9 101112 1314

BE/

BWE0

D5 D2 OE DDATA2 PST2 VSS

D4 D0 RCON DDATA0 PST0

TDO/

DSO

QSPI_
DOUT

QSPI_

CLK

QSPI_

CS2

EXTAL

32K

XTAL

32K

U0RXD U0TXD U0CTS

TMS/

BKPT

U0RTS IRQ1

IRQ2 IRQ3

TRST/

DSCLK

RSTOUT

Figure 5. MCF5327CVM240 Pinout Top View (196 MAPBGA)

5 Electrical Characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit.
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications of MCF5329.

The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications
will be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

M

N

P

Freescale Semiconductor 15

Electrical Characteristics

The parameters specified in this MCU document supersede any values found in the module
specifications.

5.1 Maximum Ratings

Table 4. Absolute Maximum Ratings

Rating Symbol Value Unit

NOTE

1, 2

Core Supply Voltage IV

CMOS Pad Supply Voltage EV

DDR/Memory Pad Supply Voltage SDV

PLL Supply Voltage PLLV

Digital Input Voltage

Instantaneous Maximum Current
Single pin limit (applies to all pins)

3

3, 4, 5

Operating Temperature Range (Packaged) T

DD

DD

DD

DD

V

IN

I

D

A

(TL - TH)

Storage Temperature Range T

1

Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”

stg

– 0.5 to +2.0 V

– 0.3 to +4.0 V

– 0.3 to +4.0 V

– 0.3 to +2.0 V

– 0.3 to +3.6 V

25 mA

– 40 to +85 °C

– 55 to +150 °C

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.

2

This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (V

SS

EVDD).

3

Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
and then use the larger of the two values.

4

All functional non-supply pins are internally clamped to VSS and EVDD.

5

Power supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions. If positive injection current (V

, the injection current may flow out of EV

I

DD

and could result in external power supply going

DD

> EVDD) is greater than

in

out of regulation. Ensure external EVDD load shunts current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power
supply must maintain regulation within operating EV

range during instantaneous and

DD

operating maximum current conditions.

or

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor16

5.2 Thermal Characteristics

TJTAPDΘ

JMA

×()+=

P

D

K

T

J

273° C+()

---------------------------------

=

KPDTA273° C×()Q

JMAPD

2

×+×=

Table 5. Thermal Characteristics

Characteristic Symbol 256MBGA 196MBGA Unit

Junction to ambient, natural convection Four layer board

Junction to ambient (@200 ft/min) Four layer board

Junction to board — θ

Junction to case — θ

Junction to top of package — Ψ

Maximum operating junction temperature — T

1

θ

and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.

JMA

Freescale recommends the use of θ
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the Ψ

jt

EIA/JESD Standard 51-2.

2

Per JEDEC JESD51-6 with the board horizontal.

3

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.

4

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).

5

Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written in conformance with Psi-JT.

and power dissipation specifications in the system design to prevent

JmA

parameter, the device power dissipation, and the method described in

(2s2p)

(2s2p)

θ

θ

JMA

JMA

JB

JC

jt

j

Electrical Characteristics

1,2

37

34

27

16

4

1,2

3

4

1,5

42

38

32

19

5

105 105

1,5

1,2

1,2

°C / W

°C / W

3

°C / W

4

°C / W

°C / W

o

C

The average chip-junction temperature (TJ) in °C can be obtained from:

Eqn. 1

Where:

T

A

Q

JMA

P

D

P

INT

P

I/O

For most applications P

= Ambient Temperature, °C
= Package Thermal Resistance, Junction-to-Ambient, °C/W
=P

INT

+ P

I/O

=IDD × IVDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined

< P

I/O

and can be ignored. An approximate relationship between PD and TJ (if P

INT

is neglected) is:

I/O

Eqn. 2

Solving equations 1 and 2 for K gives:

Eqn. 3

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 17

Electrical Characteristics

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known T
for any value of T

. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively

A

.

A

5.3 ESD Protection

Table 6. ESD Protection Characteristics1,

Characteristics Symbol Value Units

ESD Target for Human Body Model HBM 2000 V

1

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive
Grade Integrated Circuits.

2

A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.

2

5.4 DC Electrical Specifications

Table 7. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Core Supply Voltage IV

DD

PLL Supply Voltage PLLV

CMOS Pad Supply Voltage EV

SDRAM and FlexBus Supply Voltage

SDV
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)

USB Supply Voltage USBV

CMOS Input High Voltage EV

CMOS Input Low Voltage EV

CMOS Output High Voltage

= –5.0 mA

I

OH

CMOS Output Low Voltage

I

= 5.0 mA

OL

SDRAM and FlexBus Input High Voltage

EV

EV

SDV
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)

SDRAM and FlexBus Input Low Voltage

SDV
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)

DD

IH

IL

OH

OL

DD

DD

IH

IL

1.4 1.6 V

1.4 1.6 V

3.0 3.6 V

1.70

2.25

3.0

DD

3.0 3.6 V

2EV

VSS – 0.3 0.8 V

EV

0.4 — V

DD –

—0.4V

1.35

1.7
2

SDVDD+ 0.3
SDV
SDV

VSS – 0.3

– 0.3

V

SS

VSS – 0.3

1.95

2.75

3.6

+0.3 V

DD

+ 0.3

DD

+ 0.3

DD

0.45

0.8

0.8

V

V

V

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor18

Electrical Characteristics

Table 7. DC Electrical Specifications (continued)

Characteristic Symbol Min Max Unit

SDRAM and FlexBus Output High Voltage

Mobile DDR/Bus Input High Voltage (nominal 1.8V)

SDV

OH

SDVDD–0.35
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)

= –5.0 mA for all modes

I

OH

SDRAM and FlexBus Output Low Voltage

SDV

OL

Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)

= 5.0 mA for all modes

I

OL

Input Leakage Current

I

in

Vin = VDD or VSS, Input-only pins

Weak Internal Pull-Up Device Current, tested at V

Input Capacitance

2

Max.

IL

I

APU

C

in

1

All input-only pins
All input/output (three-state) pins

1

Refer to the signals section for pins having weak internal pull-up devices.

2

This parameter is characterized before qualification rather than 100% tested.

5.5 Oscillator and PLL Electrical Characteristics

Table 8. PLL Electrical Characteristics

V

—

2.1

2.4

—
—

V
—
—
—

0.3

0.3

0.5

−1.0 1.0 μA

−10 −130 μA

pF
—
—

7
7

Num Characteristic Symbol

PLL Reference Frequency Range

1

2

3 Crystal Start-up Time

4

5

7 PLL Lock Time

8 Duty Cycle of reference

9 XTAL Current I

10 Total on-chip stray capacitance on XTAL C

11 Total on-chip stray capacitance on EXTAL C

Crystal reference
External reference

Core frequency
CLKOUT Frequency

EXTAL Input High Voltage

Crystal Mode

2

3, 4

5

All other modes (External, Limp)

EXTAL Input Low Voltage

Crystal Mode

5

All other modes (External, Limp)

3, 6

3

f

ref_crystal

f

ref_ext

f

sys

f

sys/3

t

cst

V

IHEXT

V

IHEXT

V

ILEXT

V

ILEXT

t

lpll

t

dc

XTAL

S_XTAL

S_EXTAL

Min.

Val ue

12
12

488 x 10
163 x 10

−6

−6

Max.

Val ue

1

25

1

40

240

80

Unit

MHz
MHz

MHz
MHz

—10ms

V

E

XTAL

VDD

+ 0.4

/2 + 0.4

—
—

E

V

VDD

XTAL

—
—

– 0.4

/2 – 0.4

V
V

V
V

— 50000 CLKIN

40 60 %

13mA

1.5 pF

1.5 pF

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 19

Electrical Characteristics

Table 8. PLL Electrical Characteristics (continued)

Num Characteristic Symbol

Crystal capacitive load C

12

Discrete load capacitance for XTAL C

L

L_XTAL

Min.

Val ue

13

Discrete load capacitance for EXTAL C

L_EXTAL

14

vco

3, 4, 7, 8, 9

= (f

ref *

Measured at f

3, 10, 11

SYS

PFD)/4 f

Max

C

jitter

—
—

C

mod

vco

0.8 2.2 %f

350 540 MHz

CLKOUT Period Jitte r,

17

Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter

Frequency Modulation Range Limit

18

(f

Max must not be exceeded)

sys

19 VCO Frequency. f

1

The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock

Max.

Val ue

See crystal

spec

2*CL –

C

S_XTAL

C

PCB_XTAL

2*CL–-

C

S_EXTAL

C

PCB_EXTAL

10

TBD

–

–

7

7

% f
% f

frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.

2

All internal registers retain data at 0 Hz.

3

This parameter is guaranteed by characterization before qualification rather than 100% tested.

4

Proper PC board layout procedures must be followed to achieve specifications.

5

This parameter is guaranteed by design rather than 100% tested.

6

This specification is the PLL lock time only and does not include oscillator start-up time.

7

C

PCB_EXTAL

8

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

and C

PCB_XTAL

are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.

9

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.

10

Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.

11

Modulation range determined by hardware design.

Unit

pF

pF

sys/3

sys/3

sys/3

sys

.

5.6 External Interface Timing Characteristics

Table 9 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings listed in Table 9
are shown in Figure 7 and Figure 8.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor20

Electrical Characteristics

Invalid Invalid

FB_CLK (80MHz)

TSETUP

THOLD

Input Setup And Hold

1.5V

t

rise

Vh = V

IH

Vl = V

IL

1.5V1.5V Val id

t

fall

Vh = V

IH

Vl = V

IL

Input Rise Time

Input Fall Time

* The timings are also valid for inputs sampled on the negative clock edge.

Inputs

FB_CLK

B4

B5

Figure 6. General Input Timing Requirements

5.6.1 FlexBus

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS
Chip-select, FB_CS0
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.

5.6.1.1 FlexBus AC Timing Characteristics

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.

Num Characteristic Symbol Min Max Unit

— Frequency of Operation f

FB1 Clock Period (FB_CLK) t

FB2

FB3

[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.

can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or

Table 9. FlexBus AC Timing Specifications

Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS

[5:0], R/W, TS, BE/BWE[3:0] and OE)

Address, Data, and Control Output Hold (A[23:0], D[31:0],

[5:0], R/W, TS, BE/BWE[3:0], and OE)

FB_CS

1

1, 2

sys/3

FBCK (tcyc)

t

FBCHDCV

t

FBCHDCI

—80Mhz

12.5 — ns

—7.0ns

1—ns

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 21

Electrical Characteristics

FB_CLK

FB_R/W

S0 S1 S2 S3

FB_TS

FB_A[23:0]

FB_D[31:X]

FB_CSn, FB_OE,

FB_BE/BWE

n

FB_TA

DATA

ADDR[31:X]

ADDR[23:0]

FB3

FB1

FB2 FB5

FB4

FB7

FB6

Num Characteristic Symbol Min Max Unit

Table 9. FlexBus AC Timing Specifications (continued)

FB4 Data Input Setup t

FB5 Data Input Hold t

FB6 Transfer Acknowledge (TA

FB7 Transfer Acknowledge (TA

1

Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC

) Input Setup t

) Input Hold t

DVF BCH

DIFBCH

CVFBCH

CIFBCH

3.5 — ns

0—ns

4—ns

0—ns

Timing Characteristics” for SD_CS[3:0] timing.

2

The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.

NOTE

The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.

The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.

Figure 7. FlexBus Read Timing

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor22

5.7 SDRAM Bus

FB_CLK

FB_R/W

FB_TS

FB_OE

S0 S2 S3

DATA

S1

ADDR[31:X]

FB_A[23:0]

FB_D[31:X]

ADDR[23:0]

FB_CSn, FB_BE/BWEn

FB_TA

FB3

FB1

FB2

FB7

FB6

Electrical Characteristics

Figure 8. FlexBus Write Timing

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.

5.7.1 SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.

Table 10. SDR Timing Specifications

Symbol Characteristic Symbol Min Max Unit

• Frequency of Operation

SD1 Clock Period

2

SD3 Pulse Width High

SD4 Pulse Width Low

SD5

SD6

SD7 SD_SDR_DQS Output Valid

SD8

Address, SD_CKE, SD_CAS
SD_CS[1:0] - Output Valid

Address, SD_CKE, SD_CAS
SD_CS[1:0] - Output Hold

SD_DQS[3:0] input setup relative to SD_CLK

1

3

4

, SD_RAS, SD_WE, SD_BA,

, SD_RAS, SD_WE, SD_BA,

5

6

• TBD 80 MHz

t

SDCK

t

SDCKH

t

SDCKH

t

SDCHACV

t

SDCHACI

t

DQSOV

t

DQVSDCH

12.5 TBD ns

0.45 0.55 SD_CLK

0.45 0.55 SD_CLK

—

0.5 × SD_CLK
+1.0

2.0 — ns

— Self timed ns

0.25 ×

SD_CLK

0.40 × SD_CLK ns

ns

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 23

Electrical Characteristics

SD_CLK

SDDM

D[31:0]

A[23:0]

SD_BA[1:0]

CMD

ROW

SD1

SD4

COL

SD5

WD1 WD2 WD3 WD4

SD12

SD11

SD_CSn

SD_RAS

SD_WE

SD_CAS

SD2

SD3

Table 10. SDR Timing Specifications (continued)

Symbol Characteristic Symbol Min Max Unit

SD9 SD_DQS[3:2] input hold relative to SD_CLK

SD10

Data (D[31:0]) Input Setup relative to SD_CLK (reference

8

only)

SD11 Data Input Hold relative to SD_CLK (reference only) t

SD12

Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid

SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold t

1

The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329
Reference Manual for more information on setting the SDRAM clock rate.

2

SD_CLK is one SDRAM clock in (ns).

3

Pulse width high plus pulse width low cannot exceed min and max clock period.

4

Pulse width high plus pulse width low cannot exceed min and max clock period.

5

SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.

6

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.

7

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.

8

Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.

7

t

DQISDCH

t

DVSDCH

DISDCH

t

SDCHDMV

SDCHDMI

Does not apply. 0.5×SD_CLK fixed width.

0.25 ×

SD_CLK

—ns

1.0 — ns

—

0.75 × SD_CLK
+ 0.5

1.5 — ns

ns

Figure 9. SDR Write Timing

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor24

Electrical Characteristics

SD_CLK

SD_CSn,

SDDM

D[31:0]

A[23:0],

SD_RAS

,

SD_BA[1:0]

CMD

ROW

SD1

SD4

COL

WD1 WD2 WD3 WD4

SD9

3/4 MCLK

SD_SDR_DQS

SD_DQS[3:2]

Delayed

SD10

SD7

Board Delay

SD8

Board Delay

SD6

tDQS

Reference

SD_CLK

from

Memories

(Measured at Output Pin)

(Measured at Input Pin)

SD5

NOTE: Data driven from memories relative

to delayed memory clock.

SD_WE

SD_CAS,

SD2

SD3

Figure 10. SDR Read Timing

5.7.2 DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.

Table 11. DDR Timing Specifications

Num Characteristic Symbol Min Max Unit

• Frequency of Operation t

DD1 Clock Period

DD2 Pulse Width High

DD3 Pulse Width Low

Address, SD_CKE, SD_CAS

DD4

SD_CS

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

DD5

SD_CS[1:0] - Output Hold

[1:0] - Output Valid

DD6 Write Command to first DQS Latching Transition t

Data and Data Mask Output Setup (DQ-->DQS) Relative

DD7

to DQS (DDR Write Mode)

Freescale Semiconductor 25

1

2

3

, SD_RAS, SD_WE,

3

4, 5

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

DDCK

t

DDSK

t

DDCKH

t

DDCKL

t

SDCHACV

t

SDCHACI

CMDVDQ

t

DQDMV

TBD 80 Mhz

12.5 TBD ns

0.45 0.55 SD_CLK

0.45 0.55 SD_CLK

—

2.0 — ns

— 1.25 SD_CLK

1.5 — ns

0.5 × SD_CLK
+1.0

ns

Electrical Characteristics

Table 11. DDR Timing Specifications (continued)

Num Characteristic Symbol Min Max Unit

Data and Data Mask Output Hold (DQS-->DQ) Relative to

DD8

DQS (DDR Write Mode)

DD9 Input Data Skew Relative to DQS (Input Setup)

DD10

Input Data Hold Relative to DQS

6

7

8

DD11 DQS falling edge from SDCLK rising (output hold time) t

DD12 DQS input read preamble width t

DD13 DQS input read postamble width t

DD14 DQS output write preamble width t

DD15 DQS output write postamble width t

1

SD_CLK is one SDRAM clock in (ns).

2

Pulse width high plus pulse width low cannot exceed min and max clock period.

3

Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,

t

DQDMI

t

DVD Q

t

DIDQ

DQLSDCH

DQRPRE

DQRPST

DQWPRE

DQWPST

1.0 — ns

—1ns

0.25 × SD_CLK

—ns

+0.5ns

0.5 — ns

0.9 1.1 SD_CLK

0.4 0.6 SD_CLK

0.25 SD_CLK

0.4 0.6 SD_CLK

and voltage variations.

4

This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

5

The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.

6

This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].

7

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).

8

Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor26

Electrical Characteristics

SD_CLK

SD_CS

n,SD_WE,

DM3/DM2

D[31:24]/D[23:16]

A[13:0]

SD_RAS

, SD_CAS

CMD

ROW

DD1

DD5

DD4

COL

WD1 WD2 WD3 WD4

DD7

SD_DQS3/SD_DQS2

DD8

DD8

DD7

SD_CLK

DD3

DD2

DD6

Figure 11. DDR Write Timing

Freescale Semiconductor 27

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

SD_CLK

SD_CS

n,SD_WE,

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

A[13:0]

SD_RAS

, SD_CAS

CMD

ROW

DD1

DD5

DD4

WD1 WD2 WD3 WD4

SD_DQS3/SD_DQS2

DD9

SD_CLK

DD3

DD2

D[31:24]/D[23:16]

WD1 WD2 WD3 WD4

DD10

CL=2

CL=2.5

COL

DQS Read

Preamble

DQS Read
Postamble

DQS Read

Preamble

DQS Read
Postamble

CL = 2.5 CL = 2

Figure 12. DDR Read Timing

5.8 General Purpose I/O Timing

Num Characteristic Symbol Min Max Unit

G1 FB_CLK High to GPIO Output Valid t

G2 FB_CLK High to GPIO Output Invalid t

G3 GPIO Input Valid to FB_CLK High t

G4 FB_CLK High to GPIO Input Invalid t

1

GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Table 12. GPIO Timing1

CHPOV

CHPOI

PVCH

CHPI

—10ns

1.5 — ns

9—ns

1.5 — ns

Freescale Semiconductor28

Electrical Characteristics

G1

FB_CLK

GPIO Outputs

G2

G3 G4

GPIO Inputs

R1

R2

FB_CLK

RESET

RSTOUT

R3

R4

R8

R7R6R5

Configuration Overrides*:

R4

(RCON, Override pins])

Figure 13. GPIO Timing

5.9 Reset and Configuration Override Timing

Table 13. Reset and Configuration Override Timing

Num Characteristic Symbol Min Max Unit

R1 RESET

R2 FB_CLK High to RESET

R3 RESET

R4 FB_CLK High to RSTOUT Valid t

R5 RSTOUT

R6 Configuration Override Setup Time to RSTOUT

R7 Configuration Override Hold Time after RSTOUT invalid t

R8 RSTOUT

1

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to

Input valid to FB_CLK High t

Input invalid t

Input valid Time

1

valid to Config. Overrides valid t

invalid t

invalid to Configuration Override High Impedance t

RVCH

CHRI

t

RIVT

CHROV

ROVCV

COS

COH

ROICZ

9—ns

1.5 — ns

5—t

—10ns

0—ns

20 — t

0—ns

—1t

the system. Thus, RESET must be held a minimum of 100 ns.

CYC

CYC

CYC

Freescale Semiconductor 29

Refer to the CCM chapter of the MCF5329 Reference Manual for more information.

Figure 14. RESET and Configuration Override Timing

NOTE

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

T1

T2

T3

LCD_LSCLK

LCD_LD[17:0]

Line 1 Line Y

T1

T4

T3

(1,1)

(1,2)

(1,X)

T5 T7

T6

XMAX

LCD_VSYNC

LCD_HSYNC

LCD_OE

LCD_LD[17:0]

LCD_LSCLK

LCD_HSYNC

LCD_OE

LCD_LD[15:0]

T2

Display regionNon-display region

Line Y

5.10 LCD Controller Timing Specifications

This sections lists the timing specifications for the LCD Controller.

Table 14. LCD_LSCLK Timing

Num Parameter Minimum Maximum Unit

T1 LCD_LSCLK Period 25 2000 ns

T2 Pixel data setup time 11 — ns

T3 Pixel data up time 11 — ns

Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with

bus width is set and LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus
width settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK
and LCD_LD signals can also be programmed.

Figure 15. LCD_LSCLK to LCD_LD[17:0] timing diagram

Figure 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor30

Electrical Characteristics

D1

D2

D320

LCD_LSCLK

LCD_LD

LCD_SPL_SPR

LCD_HSYNC

LCD_CLS

LCD_PS

LCD_REV

XMAX

T2

D320

T1

T3

T5

T4

T7

T6

T2

T4

T7

Table 15. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Number Description Minimum Value Unit

T1 End of LCD_OE to beginning of LCD_VSYNC T5+T6+T7-1 (VWAIT1·T2)+T5+T6+T7-1 Ts

T2 LCD_HSYNC period — XMAX+T5+T6+T7 Ts

T3 LCD_VSYNC pulse width T2 VWIDTH·T2 Ts

T4 End of LCD_VSYNC to beginning of LCD_OE 1 (VWAIT2·T2)+1 Ts

T5 LCD_HSYNC pulse width 1 HWIDTH+1 Ts

T6 End of LCD_HSYNC to beginning to LCD_OE 3 HWAIT2+3 Ts

T7 End of LCD_OE to beginning of LCD_HSYNC 1 HWAIT1+1 Ts

Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC and LCD_OE can be programmed as active high or active

low. In Figure 16, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the
LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 16, LCD_LSCLK is always active.

Note: XMAX is defined in number of pixels in one line.

Freescale Semiconductor 31

Figure 17. Sharp TFT Panel Timing

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

T1

T2

T4

T3

XMAX

LCD_VSYNC

LCD_LSCLK

LCD_HSYNC

LCD_LD[15:0]

T2

T1

Ts

Table 16. Sharp TFT Panel Timing

Num Description Minimum Value Unit

T1 LCD_SPL/LCD_SPR pulse width — 1 Ts

T2 End of LCD_LD of line to beginning of LCD_HSYNC 1 HWAIT1+1 Ts

T3 End of LCD_HSYNC to beginning of LCD_LD of line 4 HWAIT2 + 4 Ts

T4 LCD_CLS rise delay from end of LCD_LD of line 3 CLS_RISE_DELAY+1 Ts

T5 LCD_CLS pulse width 1 CLS_HI_WIDTH+1 Ts

T6 LCD_PS rise delay from LCD_CLS negation 0 PS_RISE_DELAY Ts

T7 LCD_REV toggle delay from last LCD_LD of line 1 REV_TOGGLE_DELAY+1 Ts

Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line.
Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.
Note: LCD_REV toggles in every LCD_HSYN period.

Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK

Figure 18. Non-TFT Mode Panel Timing

Table 17. Non-TFT Mode Panel Timing

Num Description Minimum Value Unit

T1 LCD_HSYNC to LCD_VSYNC delay 2 HWAIT2 + 2 Tpix

T2 LCD_HSYNC pulse width 1 HWIDTH + 1 Tpix

T3 LCD_VSYNC to LCD_LSCLK — 0 ≤ T3 ≤ Ts —

T4 LCD_LSCLK to LCD_HSYNC 1 HWAIT1 + 1 Tpix

can be programmed as active high or active low. In Figure 18, all three signals are active high. When it is in CSTN
mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width
= 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor32

Electrical Characteristics

TSC

THC

TSD

TDC

TDD

ULPI_CLK

ULPI_STP

ULPI_DATA

ULPI_DIR/ULPI_NXT

ULPI_DATA

THD

(Output)

(Input)

(Input-8bit)

(Output-8bit)

5.11 USB On-The-Go

The MCF5329 device is compliant with industry standard USB 2.0 specification.

5.12 ULPI Timing Specification

Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only.
All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a
50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge.

The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.

5.13 SSI Timing Specifications

This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.

Freescale Semiconductor 33

Figure 19. ULPI Timing Diagram

Table 18. ULPI Interface Timing

Parameter Symbol Min Max Units

Setup time (control in, 8-bit data in) TSC, TSD — 3.0 ns

Hold time (control in, 8-bit data in) THC, THD −1.5 — ns

Output delay (control out, 8-bit data out) TDC, TDD — 6.0 ns

t

MCLK

t

BCLK

1

8 × t

8 × t

SYS

SYS

—ns

MCLK

—ns

BCLK

Table 19. SSI Timing – Master Modes

Num Description Symbol Min Max Units

S1 SSI_MCLK cycle time

S2 SSI_MCLK pulse width high / low 45% 55% t

S3 SSI_BCLK cycle time

S4 SSI_BCLK pulse width 45% 55% t

S5 SSI_BCLK to SSI_FS output valid — 15 ns

2

3

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

Num Description Symbol Min Max Units

S6 SSI_BCLK to SSI_FS output invalid -2 — ns

S7 SSI_BCLK to SSI_TXD valid — 15 ns

S8 SSI_BCLK to SSI_TXD invalid / high impedence -4 — ns

S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 15 — ns

S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns

1

All timings specified with a capactive load of 25pF.

2

SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).

3

SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x f

Table 19. SSI Timing – Master Modes1 (continued)

.

SYS

Table 20. SSI Timing – Slave Modes

1

Num Description Symbol Min Max Units

S11 SSI_BCLK cycle time t

BCLK

8 × t

—ns

SYS

S12 SSI_BCLK pulse width high/low 45% 55% t

S13 SSI_FS input setup before SSI_BCLK 10 — ns

S14 SSI_FS input hold after SSI_BCLK 3 — ns

S15 SSI_BCLK to SSI_TXD/SSI_FS output valid — 15 ns

S16 SSI_BCLK to SSI_TXD/SSI_FS output invalid/high

-2 — ns

impedence

S17 SSI_RXD setup before SSI_BCLK 10 — ns

S18 SSI_RXD hold after SSI_BCLK 3 — ns

1

All timings specified with a capactive load of 25pF.

BCLK

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor34

Figure 20. SSI Timing – Master Modes

SSI_MCLK

(Output)

SSI_BCLK

(Output)

SSI_FS

(Output)

SSI_TXD

SSI_RXD

S1 S2 S2

S3

S4 S4

S5

S6

S7

S8

S8

S9 S10

S7

SSI_FS

(Input)

S9

S10

SSI_BCLK

(Input)

SSI_FS

(Input)

SSI_TXD

SSI_RXD

S11

S12

S12

S14

S15

S16

S16

S17 S18

S15

S13

SSI_FS
(Output)

S15

S16

Electrical Characteristics

5.14 I2C Input/Output Timing Specifications

Table 21 lists specifications for the I2C input timing parameters shown in Figure 22.

Freescale Semiconductor 35

Figure 21. SSI Timing – Slave Modes

Table 21. I

Num Characteristic Min Max Units

I1 Start condition hold time 2 — t

I2 Clock low period 8 — t

I3 I2C_SCL/I2C_SDA rise time (VIL= 0.5 V to VIH=2.4 V) — 1 ms

I4 Data hold time 0 — ns

2

C Input Timing Specifications between SCL and SDA

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

cyc

cyc

Electrical Characteristics

I2

I6

I1

I4

I7

I8

I9

I5

I3

I2C_SCL

I2C_SDA

Table 21. I2C Input Timing Specifications between SCL and SDA (continued)

Num Characteristic Min Max Units

I5 I2C_SCL/I2C_SDA fall time (VIH= 2.4 V to VIL=0.5 V) — 1 ms

I6 Clock high time 4 — t

I7 Data setup time 0 — ns

I8 Start condition setup time (for repeated start condition only) 2 — t

I9 Stop condition setup time 2 — t

Table 22 lists specifications for the I2C output timing parameters shown in Figure 22.

Num Characteristic Min Max Units

1

I1

I2 1Clock low period 10 — t

2

I3

1

I4

3

I5

1

I6

I7 1Data setup time 2 — t

I8 1Start condition setup time (for repeated start condition only) 20 — t

I9 1Stop condition setup time 10 — t

1

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Ta b le 2 2 . The I
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Ta b le 2 2 are minimum values.

2

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.

3

Specified at a nominal 50-pF load.

Table 22. I2C Output Timing Specifications between SCL and SDA

Start condition hold time 6 — t

I2C_SCL/I2C_SDA rise time (V

Data hold time 7 — t

I2C_SCL/I2C_SDA fall time (V

Clock high time 10 — t

= 0.5 V to VIH=2.4 V) — — µs

IL

= 2.4 V to VIL= 0.5 V) — 3 ns

IH

cyc

cyc

cyc

2

C interface is

cyc

cyc

cyc

cyc

cyc

cyc

cyc

Figure 22 shows timing for the values in Table 22 and Table 21.

2

Figure 22. I

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

C Input/Output Timings

Freescale Semiconductor36

Electrical Characteristics

M1 M2

FEC_RXCLK (input)

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

M3

M4

5.15 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.

5.15.1 MII Receive Signal Timing

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_RXCLK frequency.

Table 23 lists MII receive channel timings.

Table 23. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup 5 — ns

M2 FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold 5 — ns

M3 FEC_RXCLK pulse width high 35% 65% FEC_RXCLK period

M4 FEC_RXCLK pulse width low 35% 65% FEC_RXCLK period

Figure 23 shows MII receive signal timings listed in Table 23.

5.15.2 MII Transmit Signal Timing

Table 24 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_TXCLK frequency.

Num Characteristic Min Max Unit

M5 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid 5 — ns

M6 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid — 25 ns

M7 FEC_TXCLK pulse width high 35% 65% FEC_TXCLK period

M8 FEC_TXCLK pulse width low 35% 65% FEC_TXCLK period

Figure 24 shows MII transmit signal timings listed in Table 24.

Freescale Semiconductor 37

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Figure 23. MII Receive Signal Timing Diagram

Table 24. MII Transmit Signal Timing

Electrical Characteristics

M6

FEC_TXCLK (input)

FEC_TXD[3:0] (outputs)

FEC_TXEN
FEC_TXER

M5

M7

M8

FEC_CRS

M9

FEC_COL

Figure 24. MII Transmit Signal Timing Diagram

5.15.3 MII Async Inputs Signal Timing

Table 25 lists MII asynchronous inputs signal timing.

Table 25. MII Async Inputs Signal Timing

Num Characteristic Min Max Unit

M9 FEC_CRS, FEC_COL minimum pulse width 1.5 — FEC_TXCLK period

5.15.4 MII Serial Management Channel Timing

Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5

MHz.

Num Characteristic Min Max Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum

M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) — 25 ns

M12 FEC_MDIO (input) to FEC_MDC rising edge setup 10 — ns

M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns

M14 FEC_MDC pulse width high 40% 60% FEC_MDC period

M15 FEC_MDC pulse width low 40% 60% FEC_MDC period

propagation delay)

Figure 25. MII Async Inputs Timing Diagram

Table 26. MII Serial Management Channel Timing

0— ns

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor38

Figure 26. MII Serial Management Channel Timing Diagram

M11

FEC_MDC (output)

FEC_MDIO (output)

M12 M13

FEC_MDIO (input)

M10

M14

M15

Electrical Characteristics

5.16 32-Bit Timer Module Timing Specifications

Table 27 lists timer module AC timings.

5.17 QSPI Electrical Specifications

Table 28 lists QSPI timings.

Name Characteristic Min Max Unit

QS1 QSPI_CS[3:0] to QSPI_CLK 1 510 t

QS2 QSPI_CLK high to QSPI_DOUT valid. — 10 ns

QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) 2 — ns

QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 — ns

QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 — ns

Table 27. Timer Module AC Timing Specifications

Name Characteristic Min Max Unit

T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — t

T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — t

CYC

CYC

Table 28. QSPI Modules AC Timing Specifications

CYC

Freescale Semiconductor 39

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

QSPI_CS[3:0]

QSPI_CLK

QSPI_DOUT

QS5

QS1

QSPI_DIN

QS3

QS4

QS2

Figure 27. QSPI Timing

5.18 JTAG and Boundary Scan Timing

Table 29. JTAG and Boundary Scan Timing

Num Characteristics

J1 TCLK Frequency of Operation f

J2 TCLK Cycle Period t

J3 TCLK Clock Pulse Width t

J4 TCLK Rise and Fall Times t

J5 Boundary Scan Input Data Setup Time to TCLK Rise t

J6 Boundary Scan Input Data Hold Time after TCLK Rise t

J7 TCLK Low to Boundary Scan Output Data Valid t

J8 TCLK Low to Boundary Scan Output High Z t

J9 TMS, TDI Input Data Setup Time to TCLK Rise t

J10 TMS, TDI Input Data Hold Time after TCLK Rise t

J11 TCLK Low to TDO Data Valid t

J12 TCLK Low to TDO High Z t

J13 TRST

J14 TRST

1

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Assert Time t

Setup Time (Negation) to TCLK High t

1

Symbol Min Max Unit

JCYC

JCYC

JCW

JCRF

BSDST

BSDHT

BSDV

BSDZ

TAPBST

TAPBHT

TDODV

TDODZ

TRSTAT

TRSTST

DC 1/4 f

4— t

sys/3

CYC

26 — ns

03 ns

4— ns

26 — ns

033 ns

033 ns

4— ns

10 — ns

026 ns

08 ns

100 — ns

10 — ns

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor40

Figure 28. Test Clock Input Timing

TCLK

V

IL

V

IH

J4

J4

(input)

J2

J3 J3

Input Data Valid

Output Data Valid

Output Data Valid

TCLK

Data Inputs

Data Outputs

Data Outputs

Data Outputs

V

IL

V

IH

J7

J8

J7

J6J5

Input Data Valid

Output Data Valid

Output Data Valid

TCLK

TDI

TDO

TDO

TDO

TMS

V

IL

V

IH

J9 J10

J11

J12

J11

TCLK

TRST

J13

J14

Electrical Characteristics

Figure 29. Boundary Scan (JTAG) Timing

Figure 30. Test Access Port Timing

Freescale Semiconductor 41

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Figure 31. TRST

Timing

Current Consumption

PSTCLK

PSTDDATA[7:0]

D0

D1

D2

Past

Current

DSCLK

DSI

DSO

Next

Current

D5

D3

D4

5.19 Debug AC Timing Specifications

Table 30 lists specifications for the debug AC timing parameters shown in Figure 32.

Table 30. Debug AC Timing Specification

Num Characteristic Min Max Units

D0 PSTCLK cycle time 2 2 t

D1 PSTCLK rising to PSTDDATA valid — 3.0 ns

D2 PSTCLK rising to PSTDDATA invalid 1.5 — ns

DSI-to-DSCLK setup 1 — PSTCLK

D3

1

D4

1

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized

DSCLK input relative to the rising edge of PSTCLK.

DSCLK-to-DSO hold 4 — PSTCLK

D5 DSCLK cycle time 5 — PSTCLK

D6 BKPT assertion time 1 — PSTCLK

SYS

Figure 32. Real-Time Trace AC Timing

= 1/f

SYS

6 Current Consumption

All current consumption data is lab data measured on a single device using an evaluation board. Table 31 shows the typical
power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.

Figure 33. BDM Serial Port AC Timing

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor42

Current Consumption

0

50

100

150

200

250

300

350

400

450

58 64 72 80 80(peak)

fsys/3 (MHz)

Power Consumption (mW)

Stop 0 - Flash

Stop 1 - Flash

Stop 2 - Flash

Stop 3 - Flash

Wait/Doze - Flash

Run - Flash

Table 31. Current Consumption in Low-Power Modes

Mode Voltage

3.3 V 3.9 3.92 4.0 4.0 4.0

Stop Mode 3 (Stop 11)

Stop Mode 2 (Stop 10)

Stop Mode 1(Stop 01)

Stop Mode 0 (Stop 00)

Wait/Doze

Run

1

All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room
temperature with pins configured for high drive strength.

2

Refer to the Power Management chapter in the MCF532x Reference Manual for more information on low-power
modes.

3

All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low
power mode. All code executed from flash.

4

All peripheral clocks on before entering low power mode. All code is executed from flash.

5

See the description of the low-power control register (LCPR) in the MCF532x Reference Manual for more
information on stop modes 0–3.

5

1.5 V 1.04 1.04 1.04 1.04 1.08

3.3 V 4.69 4.72 4.8 4.8 4.8

4

1.5 V 2.69 2.69 2.70 2.70 2.75

3.3 V 4.72 4.73 4.81 4.81 4.81

4

1.5 V 15.28 16.44 17.85 19.91 20.42

3.3 V 21.65 21.68 24.33 26.13 26.16

4

1.5 V 15.47 16.63 18.06 20.12 20.67

3.3 V 22.49 22.52 25.21 27.03 39.8

1.5 V 26.79 28.85 30.81 34.47 97.4

3.3 V 33.61 33.61 42.3 50.5 62.6

1.5 V 56.3 60.7 65.4 73.4 132.3

58 MHz

(Typ)

3

64 MHz

(Typ)

3

72 MHz

(Typ)

3

1,2

80 MHz

(Typ)

3

80 MHz

(Peak)

4

Units

mA

Figure 34. Current Consumption in Low-Power Modes

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 43

Current Consumption

Estimated Power Consumption vs. Core Frequency

0

50

100

150

200

250

300

0 40 80 120 160 200 240

Core Frequency (MHz)

)

Table 32. Typical Active Current Consumption Specifications

Frequency Voltage

f

sys/3

1.333 MHz

2.666 MHz

58 MHz

64 MHz

72 MHz

80 MHz

1

All values are measured with a 3.30 V EVDD, 3.30 V SDVDD and 1.5 V IVDD power
supplies. Tests performed at room temperature with pins configured for high drive
strength.

2

CPU polling a status register. All peripheral clocks except UART0, FlexBus,
INTC0, reset controller, PLL, and edge port disabled.

3

Peak current measured while running a while(1) loop with all modules active.

3.3V 7.73 7.74

1.5V 2.87 3.56

3.3V 8.57 8.60

1.5V 4.37 5.52

3.3V 40.10 49.3

1.5V 65.90 91.70

3.3V 44.40 54.0

1.5V 69.50 97.0

3.3V 53.6 63.7

1.5V 74.6 104.7

3.3V 63.0 73.7

1.5V 79.6 112.9

Typical

2

Active

(Flash)

Peak

3

1

Unit

mA

Figure 35 shows the estimated maximum power consumption.

Power Consumption (mW

Figure 35. Estimated Maximum Power Consumption

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor44

Package Information

X

Y

D

E

Laser mark for pin A1
identification in
this area

0.20

Metalized mark for
pin A1 identification
in this area

M

M

3

A

B
C
D

E

F
G
H

J

K

L
M
N

P
R

T

123456710111213141516

e15X

e15X

b256X

M

0.25 YZ

M

0.10XZ

S

Detail K

View M-M

Rotated 90° Clockwise

S

A

Z

Z

A2

A1

4

0.15

Z0.30

256X

5

K

Notes:

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.

3. Dimension b is measured at the
maximum solder ball diameter, parallel
to datum plane Z.

4. Datum Z (seating plane) is defined by
the spherical crowns of the solder
balls.

5. Parallelism measurement shall exclude
any effect of mark on top surface of
package.

Dim Min Max

Millimeters

A 1.25 1.60

A1

0.27 0.47

A2

1.16 REF

b

0.40 0.60

D

17.00 BSC

E

17.00 BSC

e 1.00 BSC
S

0.50 BSC

Top View

Bottom View

7 Package Information

This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF532x devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication of this
document. The most up-to-date mechanical drawings can be found at the product summary
page located at http://www.freescale.com/coldfire.

7.1 Package Dimensions—256 MAPBGA

Figure 36 shows MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 package dimensions.

Figure 36. 256 MAPBGA Package Outline

Freescale Semiconductor 45

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Package Information

X

0.20

Laser mark for pin 1
identification in
this area

e

13X

D

E

M

S

A1

A2

A

0.15 Z

0.30 Z

Z

Rotated 90 Clockwise

Detail K

°

5

View M-M

e13X

S

M

X0.30 YZ

0.10 Z

3

b

196X

Metalized mark for
pin 1 identification
in this area

14 13 12 11 5 4 3 2

B

C

D

E

F

G

H

J

K

L

4

NOTES:

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.

3. Dimension B is measured at the
maximum solder ball diameter,
parallel to datum plane Z.

4. Datum Z (seating plane) is defined
by the spherical crowns of the solder
balls.

5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.

DIM Min Max

Millimeters

A 1.32 1.75
A1 0.27 0.47
A2 1.18 REF

b 0.35 0.65
D 15.00 BSC
E 15.00 BSC

e 1.00 BSC
S 0.50 BSC

Y

K

M

N

P

A

1610 9

Top View

Bottom View

7.2 Package Dimensions—196 MAPBGA

Figure 37 shows the MCF5327CVM240 package dimensions.

Figure 37. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor46

8 Revision History

Table 33. MCF5329DS Document Revision History

Rev. No. Substantive Changes Date of Release

0 • Initial release. 11/2005

Revision History

0.1 • Added not to Section 7, “Package Information.”

• Added top view and bottom view where appropriate in mechanical
drawings and pinout figures.

• Figure 6: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”

1 • Corrected MCF5327 196MAPBGA ball map locations in Ta b l e 5 for

the following signals: RCON, D1, D0, OE, R/W, SD_DQS2, PSTCLK,
DDATA[3:0], PST[3:0], EVDD, IVDD, and SD_VDD. Figure 5 was
correct.

• Updated thermal characteristic values in Ta b le 5 .

• Updated DC electricals values in Ta b le 7 .

• Updated Section 3.3, “Supply Voltage Sequencing and Separation

Cautions” and subsections.

• Updated and added Oscillator/PLL characteristics in Ta b le 8 .

• Ta b le 9 : Swapped min/max for FB1; Removed FB8 & FB9.

• Updated SDRAM write timing diagram, Figure 9.

• Ta b le 1 1 : Added values for frequency of operation and DD1.

• Reworded first paragraph in Section 5.12, “ULPI Timing

Specification.”

• Updated Figure 19.

• Replaced figure & table Section 5.13, “SSI Timing Specifications,”
with slave & master mode versions.

• Removed second sentence from Section 5.15.2, “MII Transmit Signal

Timing,” regarding no minimum frequency requirement for TXCLK.

• Removed third and fourth paragraphs from Section 5.15.2, “MII

Transmit Signal Timing,” as this feature is not supported on this

device.

• Updated figure & table Section 5.19, “Debug AC Timing

Specifications.”

• Renamed & moved previous version’s Section 5.5 “Power
Consumption” to Section 6, “Current Consumption.” Added additional
real-world data to this section as well.

2 • Added MCF53281 device information throughout: features list, family

configuration table, ordering information table, signals description
table, and relevant package diagram titles

• Remove Footnote 1 from Tab l e 1 1.

• Changed document type from Advance Information to Technical Data.

3/2006

7/2007

8/2007

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 47

Revision History

Rev. No. Substantive Changes Date of Release

Table 33. MCF5329DS Document Revision History (continued)

3 • Corrected MCF53281 in features list table. This device contains CAN,

but does not feature the cryptography accelerators.

• In pin-multiplexing table, moved MCF53281 label from the MCF5328
column to the MCF5329 column, because this device contains CAN
output signals.

4 • Corrected pinouts in Ta bl e 5 for 196 MAPBGA device:

Changed D[15:1] entry from “F4–F1, G4–G2...” to “F4–F1, G5–G2...”
Changed DSO/TDO entry from “P9” to “N9”

• Corrected D0 spec in Ta b le 3 0 from 1.5 x t

to 2 x t

sys

for min and

sys

max balues.

• Updated FlexBus read and write timing diagrams in Figure 7 and

Figure 8.

• Removed footnote 2 from the IRQ[7:1] alternate functions USBHOST
VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and
SSI_CLKIN signals in Ta bl e 5 .

• Updated pinouts for 196 MAPBGA device, MCF5327CVM240 in both

Figure 5 and Ta b le 2 .

The following locations are affected: G10–12, H12–14, J11–14,
K12–13, L12–13, M12–14, N13.
The following signals are affected: USBOTG_VDD, USBHOST_VSS,
USBOTG_M, USBOTG_P, USBHOST_M, USBHOST_P, DRAMSEL,
PWM3, PWM1, IRQ
TMS/BKPT

.

[7,4,3,2,1], RESET, TDI/DSI, JTAG_EN,

10/2007

4/2008

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor48

THIS PAGE INTENTIONALLY BLANK

Revision History

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor 49

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Document Number: MCF5329DS

Rev. 4
04/2008