Freescale MCF5307PB DATA SHEET

Freescale Semiconductor, Inc.

Advance Information

MCF5307PB/D
Rev. 1, 1/2002

MCF5307 Integrated Microprocessor Product Brief

This document provides an overview of the MCF5307 ColdFire processor. It includes general
descriptions of the modules and features incorporated in the MCF5307.

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1.1 Features

The MCF5307 integrated microprocessor combines a V3 ColdFire processor core with the
following components, as shown in Figure 1:

• 8-Kbyte unified cache

• 4-Kbyte on-chip SRAM

• Integer/fractional multiply-accumulate (MAC) unit

• Divide unit

• System debug interface

• DRAM controller for synchronous and asynchronous DRAM

• Four-channel DMA controller

• Two general-purpose timers

•Two UARTs

2

C™

interface

•I

• Parallel I/O interface

• System integration module (SIM)

Designed for embedded control applications, the MCF5307 delivers 75 Dhrystone 2.1 MIPS
at 90 MHz while minimizing system costs.

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Features

V3 COLDFIRE PROCESSOR COMPLEX

JTAG

Instruction Unit

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Branch Logic

General­Purpose

Registers

A0–A7

31

0

D0–D7

31

0

Debug

Module

PSTCLK

BCLKO

(sent off-chip

and to on-chip

peripherals)

CLKIN

RSTI

DRAM Controller Chip-Select Module External

DRAM Control

Addr/Cntrl Mask

DACR0/1

DRAM Controller

PLL

X n

PLL

DCR

Outputs

DMR0/1

PCLK

RSTO

Local Memory Bus

SYSTEM INTEGRATION MODULE (SIM)

System Control PLL Control

SWIVR

RSR

SWSR SYPCR

888

CSARs CSCRs CSMRs

CS[7:0]

8

SRAM Controller

RAMBAR

4-Kbyte

SRAM

Cache Controller

CACR

ACR0
ACR1

Base Address

MBAR

Control Signals

8-Kbyte

Cache

Bus Interface

32-Bit Data Bus

CCR

Local

Memory

Bus Master Park

MPARK

32-Bit Address Bus

Instruction Fetch

IAG

Pipeline (IFP)

IC1
IC2
IED

Eight-Instruction
FIFO Buffer

Operand Execution
Pipeline (OEP)

DSOC

DIV

31

0

Interrupt Controller

10 ICRs

MAC

AGEX

4-Entry
Store
Buffer

Parallel Port

PLL

IRQPAR

4

[1,3,5,7]

IRQ

IPR

IMR

AVR

DMA

Four

Channels

Software
Watchdog

2

C Module

I

Two UARTs

Tw o

General-

Purpose

Timers

Figure 1. MCF5307 Block Diagram

2

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Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and
on-chip memories, are integrated using advanced process technologies.

The MCF5307 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and
ColdFire customers in which development tools and customer code can be leveraged. In fact, customers
moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K
assembly code to the ColdFire architecture.

Based on the concept of variable-length RISC technology, the ColdFire family combines the architectural
simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In defining
the ColdFire architecture for embedded processing applications, a 68K-code compatible core combines
performance advantages of a RISC architecture with the optimum code density of a streamlined,
variable-length M68000 instruction set.

By using a variable-length instruction set architecture, embedded system designers using ColdFire RISC
processors enjoy significant advantages over conventional fixed-length RISC architectures. The denser
binary code for ColdFire processors consumes less memory than many fixed-length instruction set RISC
processors available. This improved code density means more efficient system memory use for a given
application and allows use of slower, less costly memory to help achieve a target performance level.

The MCF5307 is the first standard product to implement the Version 3 ColdFire microprocessor core. To
reach higher levels of frequency and performance, numerous enhancements were made to the V2
architecture. Most notable are a deeper instruction pipeline, branch acceleration, and a unified cache, which
together provide 75 (Dhrystone 2.1) MIPS at 90 MHz. Increasing the internal speed of the core also allows
higher performance while providing the system designer with an easy-to-use lower speed system interface.
The processor complex frequency is an integer multiple, 2 to 4 times, of the external bus frequency. The core
clock can be stopped to support a low-power mode.

Serial communication channels are provided by an I
UARTs. Four channels of DMA allow for fast data transfer using a programmable burst mode independent
of processor execution. The two 16-bit general-purpose multimode timers provide separate input and output
signals. For system protection, the processor includes a programmable 16-bit software watchdog timer. In
addition, common system functions such as chip selects, interrupt control, bus arbitration, and an
IEEE 1149.1 JTAG module are included. A sophisticated debug interface supports background-debug mode
plus real-time trace and debug with expanded flexibility of on-chip breakpoint registers. This interface is
present in all ColdFire standard products and allows common emulator support across the entire family of
microprocessors.

MCF5307 Features

2

C interface module and two programmable full-duplex

1.2 MCF5307 Features

The following list summarizes MCF5307 features:

• ColdFire processor core

— Variable-length RISC, clock-multiplied Version 3 microprocessor core

— Fully code compatible with Version 2 processors

— Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and

two-stage operand execution pipeline (OEP)

— Eight-instruction FIFO buffer provides decoupling between the pipelines

— Branch prediction mechanisms for accelerating program execution

— 32-bit internal address bus supporting 4 Gbytes of linear address space

MOTOROLA

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MCF5307 Features

— 32-bit data bus

— 16 user-accessible, 32-bit-wide, general-purpose registers

— Supervisor/user modes for system protection

— Vector base register to relocate exception-vector table

— Optimized for high-level language constructs

• Multiply and accumulate unit (MAC)

— High-speed, complex arithmetic processing for DSP applications

— Tightly coupled to the OEP

— Three-stage execute pipeline with one clock issue rate for 16 x 16 operations

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— 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate

— Signed or unsigned integer support, plus signed fractional operands

• Hardware integer divide unit

— Unsigned and signed integer divide support

— Tightly coupled to the OEP

— 32/16 and 32/32 operation support producing quotient and/or remainder results

• 8-Kbyte unified cache

— Four-way set-associative organization

— Operates at higher processor core frequency

— Provides pipelined, single-cycle access to critical code and data

— Supports write-through and copyback modes

— Four-entry, 32-bit store buffer to improve performance of operand writes

• 4-Kbyte SRAM

— Programmable location anywhere within 4-Gbyte linear address space

— Higher core-frequency operation

— Pipelined, single-cycle access to critical code or data

• DMA controller

— Four fully programmable channels: two support external requests

— Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability

— Source/destination address pointers that can increment or remain constant

— 24-bit transfer counter per channel

4

— Operand packing and unpacking supported

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— Two-bus-clock internal access

— Automatic DMA transfers from on-chip UARTs using internal interrupts

• DRAM controller

— Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast page mode

support

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— Up to 512 Mbytes of DRAM

— Programmable timer provides CAS-before-RAS refresh for asynchronous DRAMs

— Support for two separate memory blocks

•Two UARTs

— Full-duplex operation

— Programmable clock

— Modem control signals available (CTS

— Processor-interrupt capability

• Dual 16-bit general-purpose multiple-mode timers

, RTS)

MCF5307 Features

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— 8-bit prescaler

— Timer input and output pins

— Processor-interrupt capability

— Up to 22-nS resolution at 45 MHz

2

C module

•I

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

2

— Fully compatible with industry-standard I

— Master or slave modes support multiple masters

— Automatic interrupt generation with programmable level

• System interface module (SIM)

— Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM, FLASH, and

memory-mapped I/O devices

— Eight fully programmable chip selects, each with a base address register

— Programmable wait states and port sizes per chip select

— User-programmable processor clock/input clock frequency ratio

— Programmable interrupt controller

— Low interrupt latency

— Four external interrupt request inputs

— Programmable autovector generator

— Software watchdog timer

• 16-bit general-purpose I/O interface

C bus

• IEEE 1149.1 test (JTAG) module

• System debug support

— Real-time trace for determining dynamic execution path while in emulator mode

— Background debug mode (BDM) for debug features while halted

— Real-time debug support, including 6 user-visible hardware breakpoint registers supporting a

variety of breakpoint configurations

— Supports comprehensive emulator functions through trace and breakpoint logic

MOTOROLA

MCF5307 Integrated Microprocessor Product Brief 5

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