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MCF5307 ColdFire

Integrated Microprocessor

User’s Manual

MCF5307UM/D

Rev. 2.0, 08/2000

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ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductors

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us: USA/EUROPE/Locations Not Listed:

or 1–800–441–2447

JAPAN:

Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan.

81–3–3440–3569

ASIA/PACIFIC:

Hong Kong. 852–26668334

Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.,

Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140

Technical Information Center:

HOME PAGE:

Document Comments World Wide Web Addresses

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: FAX (512) 895-2638, Attn: RISC Applications Engineering

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: http://www.motorola.com/PowerPC

http://www.motorola.com/NetComm http://www.motorola.com/ColdFire

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Overview

Part I: MCF5307

Processor

Core

ColdFire Core

Hardware Multiply/Accumulate (MAC) Unit

Local Memory

Debug Support

Part II: System Integration Module (

SIM)

SIM Overview

Phase-Locked Loop (PLL)

C Module

Interrupt Controller

Chip-Select Module

Synchronous/Asynchronous DRAM Controller Module

Part III: Peripheral Module

DMA Controller Module

Timer Module

UART Modules

Parallel Port (General-Purpose I/O)

Part IV: Hardware Interface

Mechanical Data

Signal Descriptions

Part I

2 3 4 5

Part II

6 7 8

9 10 11

Part III

12 13 14

Part IV

16 17

Bus Operation

IEEE 1149.1 Test Access Port (JTAG)

Electrical Specifications

Appendix: Memory Map

Glossary of Terms and Abbreviations

Index

18 19

GLO

IND

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Part I

2 3 4 5

Part II

6 7 8

Overview Part I: MCF5307

Processor

Core ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support Part II: System Integration Module (

SIM) SIM Overview Phase-Locked Loop (PLL)

C Module

9 10 11

Part III

12 13 14

Part IV

Interrupt Controller Chip-Select Module Synchronous/Asynchronous DRAM Controller Module Part III: Peripheral Module DMA Controller Module Timer Module UART Modules

Parallel Port (General-Purpose I/O)

Part IV: Hardware Interface

16 17 18 19

GLO

IND

Mechanical Data Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Electrical Specifications

Appendix B: Memory Map Glossary of Terms and Abbreviations Index

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CONTENTS

Paragraph Number

Title

Page

Number

About This Book

Chapter 1

Overview

1.1 Features............................................................................................................... 1-1

1.2 MCF5307 Features.............................................................................................. 1-4

1.2.1 Process............................................................................................................ 1-6

1.3 ColdFire Module Description............................................................................. 1-7

1.3.1 ColdFire Core ................................................................................................. 1-7

1.3.1.1 Instruction Fetch Pipeline (IFP).................................................................. 1-7

1.3.1.2 Operand Execution Pipeline (OEP)............................................................ 1-7

1.3.1.3 MAC Module.............................................................................................. 1-7

1.3.1.4 Integer Divide Module................................................................................ 1-7

1.3.1.5 8-Kbyte Unified Cache............................................................................... 1-8

1.3.1.6 Internal 4-Kbyte SRAM ............................................................................. 1-8

1.3.2 DRAM Controller........................................................................................... 1-8

1.3.3 DMA Controller.............................................................................................. 1-8

1.3.4 UART Modules............................................................................................... 1-8

1.3.5 Timer Module................................................................................................. 1-9

1.3.6 I2C Module..................................................................................................... 1-9

1.3.7 System Interface ........................................................................................... 1-10

1.3.7.1 External Bus Interface .............................................................................. 1-10

1.3.7.2 Chip Selects .............................................................................................. 1-10

1.3.7.3 16-Bit Parallel Port Interface.................................................................... 1-10

1.3.7.4 Interrupt Controller................................................................................... 1-10

1.3.7.5 JTAG......................................................................................................... 1-11

1.3.8 System Debug Interface................................................................................ 1-11

1.3.9 PLL Module.................................................................................................. 1-11

1.4 Programming Model, Addressing Modes, and Instruction Set......................... 1-12

1.4.1 Programming Model..................................................................................... 1-13

1.4.2 User Registers............................................................................................... 1-14

1.4.3 Supervisor Registers..................................................................................... 1-14

1.4.4 Instruction Set............................................................................................... 1-15

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CONTENTS

Paragraph Number

Title

Page

Number

Part I

MCF5407 Processor Core

Chapter 2

ColdFire Core

2.1 Features and Enhancements.............................................................................. 2-21

2.1.1 Clock-Multiplied Microprocessor Core........................................................ 2-22

2.1.2 Enhanced Pipelines....................................................................................... 2-22

2.1.2.1 Instruction Fetch Pipeline (IFP)................................................................ 2-23

2.1.2.1.1 Branch Acceleration ............................................................................. 2-23

2.1.2.2 Operand Execution Pipeline (OEP).......................................................... 2-24

2.1.2.2.1 Illegal Opcode Handling....................................................................... 2-24

2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit...................................... 2-24

2.1.2.2.3 Hardware Divide Unit .......................................................................... 2-25

2.1.3 Debug Module Enhancements...................................................................... 2-25

2.2 Programming Model......................................................................................... 2-26

2.2.1 User Programming Model ............................................................................ 2-27

2.2.1.1 Data Registers (D0–D7) ........................................................................... 2-27

2.2.1.2 Address Registers (A0–A6)...................................................................... 2-27

2.2.1.3 Stack Pointer (A7, SP).............................................................................. 2-28

2.2.1.4 Program Counter (PC).............................................................................. 2-28

2.2.1.5 Condition Code Register (CCR)............................................................... 2-28

2.2.2 Supervisor Programming Model................................................................... 2-29

2.2.2.1 Status Register (SR).................................................................................. 2-29

2.2.2.2 Vector Base Register (VBR) .................................................................... 2-30

2.2.2.3 Cache Control Register (CACR) .............................................................. 2-30

2.2.2.4 Access Control Registers (ACR0–ACR1)................................................ 2-31

2.2.2.5 RAM Base Address Register (RAMBAR)............................................... 2-31

2.2.2.6 Module Base Address Register (MBAR) ................................................. 2-31

2.3 Integer Data Formats......................................................................................... 2-31

2.4 Organization of Data in Registers..................................................................... 2-31

2.4.1 Organization of Integer Data Formats in Registers...................................... 2-31

2.4.2 Organization of Integer Data Formats in Memory ....................................... 2-32

2.5 Addressing Mode Summary ............................................................................. 2-33

2.6 Instruction Set Summary................................................................................... 2-34

2.6.1 Instruction Set Summary .............................................................................. 2-37

2.7 Instruction Timing ............................................................................................ 2-40

2.7.1 MOVE Instruction Execution Times............................................................ 2-41

2.7.2 Execution Timings—One-Operand Instructions.......................................... 2-43

2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-43

2.7.4 Miscellaneous Instruction Execution Times................................................. 2-45

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CONTENTS

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2.7.5 Branch Instruction Execution Times ............................................................ 2-46

2.8 Exception Processing Overview....................................................................... 2-47

2.8.1 Exception Stack Frame Definition................................................................ 2-49

2.8.2 Processor Exceptions.................................................................................... 2-50

Title

Page

Number

Chapter 3

Hardware Multiply/Accumulate (MAC) Unit

3.1 Overview............................................................................................................. 3-1

3.1.1 MAC Programming Model............................................................................. 3-2

3.1.2 General Operation........................................................................................... 3-3

3.1.3 MAC Instruction Set Summary ...................................................................... 3-4

3.1.4 Data Representation........................................................................................ 3-4

3.2 MAC Instruction Execution Timings.................................................................. 3-5

Chapter 4

Local Memory

4.1 Interactions between Local Memory Modules ................................................... 4-1

4.2 SRAM Overview ................................................................................................ 4-1

4.3 SRAM Operation................................................................................................ 4-2

4.4 SRAM Programming Model............................................................................... 4-3

4.4.1 SRAM Base Address Register (RAMBAR)................................................... 4-3

4.5 SRAM Initialization............................................................................................ 4-4

4.5.1 SRAM Initialization Code.............................................................................. 4-5

4.6 Power Management ............................................................................................ 4-6

4.7 Cache Overview.................................................................................................. 4-6

4.8 Cache Organization............................................................................................. 4-7

4.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8

4.8.2 The Cache at Start-Up..................................................................................... 4-9

4.9 Cache Operation................................................................................................ 4-11

4.9.1 Caching Modes............................................................................................. 4-13

4.9.1.1 Cacheable Accesses.................................................................................. 4-13

4.9.1.2 Write-Through Mode ............................................................................... 4-14

4.9.1.3 Copyback Mode ....................................................................................... 4-14

4.9.2 Cache-Inhibited Accesses............................................................................. 4-14

4.9.3 Cache Protocol.............................................................................................. 4-15

4.9.3.1 Read Miss ................................................................................................. 4-15

4.9.3.2 Write Miss ............................................................................................... 4-16

4.9.3.3 Read Hit.................................................................................................... 4-16

4.9.3.4 Write Hit .................................................................................................. 4-16

4.9.4 Cache Coherency ......................................................................................... 4-17

Contents

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CONTENTS

Paragraph Number

4.9.5 Memory Accesses for Cache Maintenance................................................... 4-17

4.9.5.1 Cache Filling............................................................................................. 4-17

4.9.5.2 Cache Pushes ............................................................................................ 4-18

4.9.5.2.1 Push and Store Buffers ......................................................................... 4-18

4.9.5.2.2 Push and Store Buffer Bus Operation................................................... 4-18

4.9.6 Cache Locking.............................................................................................. 4-19

4.10 Cache Registers................................................................................................. 4-21

4.10.1 Cache Control Register (CACR) .................................................................. 4-21

4.10.2 Access Control Registers (ACR0–ACR1).................................................... 4-22

4.11 Cache Management........................................................................................... 4-24

4.12 Cache Operation Summary............................................................................... 4-25

4.12.1 Cache State Transitions ................................................................................ 4-25

4.13 Cache Initialization Code.................................................................................. 4-29

Title

Page

Number

Chapter 5

Debug Support

5.1 Overview............................................................................................................. 5-1

5.2 Signal Description............................................................................................... 5-2

5.3 Real-Time Trace Support.................................................................................... 5-3

5.3.1 Begin Execution of Taken Branch (PST = 0x5)............................................. 5-4

5.4 Programming Model........................................................................................... 5-5

5.4.1 Address Attribute Trigger Register (AATR).................................................. 5-7

5.4.2 Address Breakpoint Registers (ABLR, ABHR)............................................ 5-8

5.4.3 BDM Address Attribute Register (BAAR)..................................................... 5-9

5.4.4 Configuration/Status Register (CSR)............................................................ 5-10

5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-12

5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-13

5.4.7 Trigger Definition Register (TDR)............................................................... 5-14

5.5 Background Debug Mode (BDM).................................................................... 5-16

5.5.1 CPU Halt....................................................................................................... 5-16

5.5.2 BDM Serial Interface.................................................................................... 5-17

5.5.2.1 Receive Packet Format ............................................................................. 5-19

5.5.2.2 Transmit Packet Format............................................................................ 5-19

5.5.3 BDM Command Set...................................................................................... 5-19

5.5.3.1 ColdFire BDM Command Format............................................................ 5-20

5.5.3.1.1 Extension Words as Required............................................................... 5-21

5.5.3.2 Command Sequence Diagrams................................................................. 5-21

5.5.3.3 Command Set Descriptions ...................................................................... 5-23

5.5.3.3.1 Read A/D Register (

5.5.3.3.2 Write A/D Register (

5.5.3.3.3 Read Memory Location (

RAREG/RDREG

WAREG/WDREG

READ

) ..................................................... 5-24

)................................................... 5-25

)............................................................ 5-26

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CONTENTS

Paragraph Number

5.5.3.3.4 Write Memory Location (

5.5.3.3.5 Dump Memory Block (

5.5.3.3.6 Fill Memory Block (

5.5.3.3.7 Resume Execution (

5.5.3.3.8 No Operation (

5.5.3.3.9 Synchronize PC to the PST/DDATA Lines (

5.5.3.3.10 Read Control Register (

5.5.3.3.11 Write Control Register (

5.5.3.3.12 Read Debug Module Register (

5.5.3.3.13 Write Debug Module Register (

5.6 Real-Time Debug Support................................................................................ 5-39

5.6.1 Theory of Operation...................................................................................... 5-40

5.6.1.1 Emulator Mode......................................................................................... 5-41

5.6.2 Concurrent BDM and Processor Operation.................................................. 5-41

5.7 Motorola-Recommended BDM Pinout............................................................. 5-42

5.8 Processor Status, DDATA Definition............................................................... 5-42

5.8.1 User Instruction Set ...................................................................................... 5-43

5.8.2 Supervisor Instruction Set............................................................................. 5-46

NOP

Title

WRITE

) ......................................................... 5-27

DUMP

).............................................................. 5-29

FILL

)..................................................................... 5-31

)........................................................................ 5-33

) .............................................................................. 5-34

SYNC_PC

RCREG

)............................................................ 5-36

WCREG

) .......................................................... 5-37

RDMREG

WDMREG

) ............................................. 5-38

) ........................................... 5-39

) ....................... 5-35

Page

Number

Part II

System Integration Module (SIM)

Chapter 6

SIM Overview

6.1 Features............................................................................................................... 6-1

6.2 Programming Model........................................................................................... 6-3

6.2.1 SIM Register Memory Map............................................................................ 6-3

6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4

6.2.3 Reset Status Register (RSR)........................................................................... 6-5

6.2.4 Software Watchdog Timer.............................................................................. 6-6

6.2.5 System Protection Control Register (SYPCR) ............................................... 6-8

6.2.6 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9

6.2.7 Software Watchdog Service Register (SWSR)............................................... 6-9

6.2.8 PLL Clock Control for CPU STOP Instruction............................................ 6-10

6.2.9 Pin Assignment Register (PAR)................................................................... 6-10

6.2.10 Bus Arbitration Control................................................................................ 6-11

6.2.10.1 Default Bus Master Park Register (MPARK) .......................................... 6-11

6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12

6.2.10.1.2 Arbitration between Internal and External Masters

for Accessing Internal Resources ......................................................... 6-14

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CONTENTS

Paragraph Number

Title

Page

Number

Chapter 7

Phase-Locked Loop (PLL)

7.1 Overview............................................................................................................. 7-1

7.1.1 PLL:PCLK Ratios........................................................................................... 7-2

7.2 PLL Operation .................................................................................................... 7-2

7.2.1 Reset/Initialization.......................................................................................... 7-2

7.2.2 Normal Mode.................................................................................................. 7-2

7.2.3 Reduced-Power Mode..................................................................................... 7-2

7.2.4 PLL Control Register (PLLCR)...................................................................... 7-3

7.3 PLL Port List ...................................................................................................... 7-3

7.4 Timing Relationships.......................................................................................... 7-4

7.4.1 PCLK, PSTCLK, and BCLKO....................................................................... 7-4

7.4.2 RSTI

7.5 PLL Power Supply Filter Circuit........................................................................ 7-6

8.1 Overview............................................................................................................. 8-1

8.2 Interface Features................................................................................................ 8-1

8.3 I

8.4 I

8.4.1 Arbitration Procedure ..................................................................................... 8-4

8.4.2 Clock Synchronization.................................................................................... 8-5

8.4.3 Handshaking ................................................................................................... 8-5

8.4.4 Clock Stretching ............................................................................................. 8-5

8.5 Programming Model........................................................................................... 8-6

8.5.1 I

8.5.2 I

8.5.3 I

8.5.4 I

8.5.5 I

8.6 I

8.6.1 Initialization Sequence.................................................................................. 8-10

8.6.2 Generation of START................................................................................... 8-10

8.6.3 Post-Transfer Software Response................................................................. 8-11

8.6.4 Generation of STOP...................................................................................... 8-12

8.6.5 Generation of Repeated START................................................................... 8-12

8.6.6 Slave Mode................................................................................................... 8-13

8.6.7 Arbitration Lost............................................................................................. 8-13

Timing................................................................................................... 7-5

Chapter 8

C Module

C System Configuration................................................................................... 8-3

C Protocol ........................................................................................................ 8-3

C Address Register (IADR)......................................................................... 8-6

C Frequency Divider Register (IFDR)......................................................... 8-7

C Control Register (I2CR)........................................................................... 8-8

C Status Register (I2SR).............................................................................. 8-9

C Data I/O Register (I2DR)....................................................................... 8-10

C Programming Examples............................................................................. 8-10

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CONTENTS

Paragraph Number

Title

Page

Number

Chapter 9

Interrupt Controller

9.1 Overview............................................................................................................. 9-1

9.2 Interrupt Controller Registers............................................................................. 9-2

9.2.1 Interrupt Control Registers (ICR0–ICR9) ...................................................... 9-3

9.2.2 Autovector Register (AVR)............................................................................ 9-5

9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)................................... 9-6

9.2.4 Interrupt Port Assignment Register (IRQPAR).............................................. 9-7

Chapter 10

10.1 Overview........................................................................................................... 10-1

10.2 Chip-Select Module Signals ............................................................................. 10-1

10.3 Chip-Select Operation....................................................................................... 10-2

10.3.1 General Chip-Select Operation..................................................................... 10-3

10.3.1.1 8-, 16-, and 32-Bit Port Sizing.................................................................. 10-4

10.3.1.2 Global Chip-Select Operation................................................................... 10-4

10.4 Chip-Select Registers........................................................................................ 10-5

10.4.1 Chip-Select Module Registers...................................................................... 10-6

10.4.1.1 Chip-Select Address Registers (CSAR0–CSAR7)................................... 10-6

10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)...................................... 10-6

10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7) .................................... 10-8

10.4.1.4 Code Example........................................................................................... 10-9

Chip-Select Module

Chapter 11

Synchronous/Asynchronous DRAM Controller Module

11.1 Overview........................................................................................................... 11-1

11.1.1 Definitions .................................................................................................... 11-2

11.1.2 Block Diagram and Major Components....................................................... 11-2

11.2 DRAM Controller Operation............................................................................ 11-3

11.2.1 DRAM Controller Registers......................................................................... 11-3

11.3 Asynchronous Operation .................................................................................. 11-4

11.3.1 DRAM Controller Signals in Asynchronous Mode...................................... 11-4

11.3.2 Asynchronous Register Set........................................................................... 11-4

11.3.2.1 DRAM Control Register (DCR) in Asynchronous Mode ........................ 11-4

11.3.2.2 DRAM Address and Control Registers (DACR0/DACR1) ..................... 11-5

11.3.2.3 DRAM Controller Mask Registers (DMR0/DMR1) ................................ 11-7

11.3.3 General Asynchronous Operation Guidelines .............................................. 11-8

11.3.3.1 Non-Page-Mode Operation..................................................................... 11-11

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11.3.3.2 Burst Page-Mode Operation ................................................................... 11-12

11.3.3.3 Continuous Page Mode........................................................................... 11-13

11.3.3.4 Extended Data Out (EDO) Operation..................................................... 11-15

11.3.3.5 Refresh Operation................................................................................... 11-16

11.4 Synchronous Operation................................................................................... 11-16

11.4.1 DRAM Controller Signals in Synchronous Mode...................................... 11-17

11.4.2 Using Edge Select (EDGESEL) ................................................................. 11-18

11.4.3 Synchronous Register Set........................................................................... 11-19

11.4.3.1 DRAM Control Register (DCR) in Synchronous Mode.......................... 11-19

11.4.3.2 DRAM Address and Control Registers (DACR0/DACR1)

in Synchronous Mode .........................................................................11-20

11.4.3.3 DRAM Controller Mask Registers (DMR0/DMR1) .............................. 11-22

11.4.4 General Synchronous Operation Guidelines............................................... 11-23

11.4.4.1 Address Multiplexing ............................................................................. 11-23

11.4.4.2 Interfacing Example................................................................................ 11-27

11.4.4.3 Burst Page Mode..................................................................................... 11-27

11.4.4.4 Continuous Page Mode........................................................................... 11-29

11.4.4.5 Auto-Refresh Operation.......................................................................... 11-31

11.4.4.6 Self-Refresh Operation ........................................................................... 11-32

11.4.5 Initialization Sequence................................................................................ 11-33

11.4.5.1 Mode Register Settings........................................................................... 11-33

11.5 SDRAM Example........................................................................................... 11-34

11.5.1 SDRAM Interface Configuration................................................................ 11-35

11.5.2 DCR Initialization....................................................................................... 11-35

11.5.3 DACR Initialization.................................................................................... 11-35

11.5.4 DMR Initialization...................................................................................... 11-37

11.5.5 Mode Register Initialization ....................................................................... 11-38

11.5.6 Initialization Code....................................................................................... 11-39

Title

Page

Number

Part III

Peripheral Module

Chapter 12

DMA Controller Module

12.1 Overview........................................................................................................... 12-1

12.1.1 DMA Module Features................................................................................. 12-2

12.2 DMA Signal Description .................................................................................. 12-2

12.3 DMA Transfer Overview.................................................................................. 12-3

12.4 DMA Controller Module Programming Model................................................ 12-4

12.4.1 Source Address Registers (SAR0–SAR3).................................................... 12-6

12.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 12-7

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12.4.3 Byte Count Registers (BCR0–BCR3)........................................................... 12-7

12.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 12-8

12.4.5 DMA Status Registers (DSR0–DSR3)....................................................... 12-10

12.4.6 DMA Interrupt Vector Registers (DIVR0–DIVR3)................................... 12-11

12.5 DMA Controller Module Functional Description........................................... 12-11

12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)........................... 12-12

12.5.2 Data Transfer Modes .................................................................................. 12-12

12.5.2.1 Dual-Address Transfers.......................................................................... 12-12

12.5.2.2 Single-Address Transfers........................................................................ 12-13

12.5.3 Channel Initialization and Startup .............................................................. 12-13

12.5.3.1 Channel Prioritization............................................................................. 12-13

12.5.3.2 Programming the DMA Controller Module ........................................... 12-13

12.5.4 Data Transfer .............................................................................................. 12-14

12.5.4.1 External Request and Acknowledge Operation...................................... 12-14

12.5.4.2 Auto-Alignment...................................................................................... 12-17

12.5.4.3 Bandwidth Control.................................................................................. 12-18

12.5.5 Termination................................................................................................. 12-18

Title

Page

Number

Chapter 13

Timer Module

13.1 Overview........................................................................................................... 13-1

13.1.1 Key Features................................................................................................. 13-2

13.2 General-Purpose Timer Units........................................................................... 13-2

13.3 General-Purpose Timer Programming Model .................................................. 13-2

13.3.1 Timer Mode Registers (TMR0/TMR1) ........................................................ 13-3

13.3.2 Timer Reference Registers (TRR0/TRR1)................................................... 13-4

13.3.3 Timer Capture Registers (TCR0/TCR1)....................................................... 13-4

13.3.4 Timer Counters (TCN0/TCN1) .................................................................... 13-5

13.3.5 Timer Event Registers (TER0/TER1)........................................................... 13-5

13.4 Code Example................................................................................................... 13-6

13.5 Calculating Time-Out Values........................................................................... 13-7

Chapter 14

UART Modules

14.1 Overview........................................................................................................... 14-1

14.2 Serial Module Overview................................................................................... 14-2

14.3 Register Descriptions........................................................................................ 14-2

14.3.1 UART Mode Registers 1 (UMR1n).............................................................. 14-4

14.3.2 UART Mode Register 2 (UMR2n)............................................................... 14-6

14.3.3 UART Status Registers (USRn) ................................................................... 14-7

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14.3.4 UART Clock-Select Registers (UCSRn)...................................................... 14-8

14.3.5 UART Command Registers (UCRn)............................................................ 14-9

14.3.6 UART Receiver Buffers (URBn) ............................................................... 14-11

14.3.7 UART Transmitter Buffers (UTBn)........................................................... 14-11

14.3.8 UART Input Port Change Registers (UIPCRn).......................................... 14-12

14.3.9 UART Auxiliary Control Register (UACRn)............................................. 14-12

14.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 14-13

14.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)............................ 14-14

14.3.12 UART Interrupt Vector Register (UIVRn)................................................. 14-15

14.3.13 UART Input Port Register (UIPn).............................................................. 14-15

14.3.14 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 14-15

14.4 UART Module Signal Definitions.................................................................. 14-16

14.5 Operation......................................................................................................... 14-18

14.5.1 Transmitter/Receiver Clock Source............................................................ 14-18

14.5.1.1 Programmable Divider............................................................................ 14-18

14.5.1.2 Calculating Baud Rates........................................................................... 14-19

14.5.1.2.1 BCLKO Baud Rates ........................................................................... 14-19

14.5.1.2.2 External Clock .................................................................................... 14-19

14.5.2 Transmitter and Receiver Operating Modes............................................... 14-19

14.5.2.1 Transmitting ........................................................................................... 14-21

14.5.2.2 Receiver .................................................................................................. 14-22

14.5.2.3 FIFO Stack ............................................................................................. 14-24

14.5.3 Looping Modes........................................................................................... 14-25

14.5.3.1 Automatic Echo Mode............................................................................ 14-25

14.5.3.2 Local Loop-Back Mode.......................................................................... 14-25

14.5.3.3 Remote Loop-Back Mode....................................................................... 14-26

14.5.4 Multidrop Mode.......................................................................................... 14-26

14.5.5 Bus Operation............................................................................................. 14-28

14.5.5.1 Read Cycles ............................................................................................ 14-28

14.5.5.2 Write Cycles ........................................................................................... 14-28

14.5.5.3 Interrupt Acknowledge Cycles ............................................................... 14-28

14.5.6 Programming .............................................................................................. 14-28

14.5.6.1 UART Module Initialization Sequence .................................................. 14-29

Title

Page

Number

Chapter 15

Parallel Port (General-Purpose I/O)

15.1 Parallel Port Operation...................................................................................... 15-1

15.1.1 Pin Assignment Register (PAR)................................................................... 15-1

15.1.2 Port A Data Direction Register (PADDR).................................................... 15-2

15.1.3 Port A Data Register (PADAT).................................................................... 15-2

15.1.4 Code Example............................................................................................... 15-3

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Part IV

Hardware Interface

Chapter 16

Mechanical Data

16.1 Package............................................................................................................. 16-1

16.2 Pinout................................................................................................................ 16-1

16.3 Mechanical Diagram......................................................................................... 16-8

16.4 Case Drawing.................................................................................................... 16-9

Chapter 17

Signal Descriptions

17.1 Overview........................................................................................................... 17-1

17.2 MCF5307 Bus Signals...................................................................................... 17-7

17.2.1 Address Bus.................................................................................................. 17-7

17.2.1.1 Address Bus (A[23:0]).............................................................................. 17-7

17.2.1.2 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7

17.2.2 Data Bus (D[31:0]) ....................................................................................... 17-8

17.2.3 Read/Write (R/W

17.2.4 Size (SIZ[1:0]).............................................................................................. 17-8

17.2.5 Transfer Start (TS

17.2.6 Address Strobe (AS)..................................................................................... 17-9

17.2.7 Transfer Acknowledge (T

17.2.8 Transfer In Progress (TIP

17.2.9 Transfer Type (TT[1:0]/PP[1:0])................................................................ 17-10

17.2.10 Transfer Modifier (TM[2:0]/PP[4:2])......................................................... 17-10

17.3 Interrupt Control Signals................................................................................. 17-12

17.3.1 Interrupt Request (IRQ1

17.4 Bus Arbitration Signals................................................................................... 17-12

17.4.1 Bus Request (BR

17.4.2 Bus Grant (BG

17.4.3 Bus Driven (BD)......................................................................................... 17-13

17.5 Clock and Reset Signals.................................................................................. 17-13

17.5.1 Reset In (RSTI

17.5.2 Clock Input (CLKIN).................................................................................. 17-13

17.5.3 Bus Clock Output (BCLKO) ...................................................................... 17-13

17.5.4 Reset Out (RSTO)....................................................................................... 17-13

17.5.5 Data/Configuration Pins (D[7:0])............................................................... 17-13

17.5.5.1 D[7:5Boot Chip-Select (CS0

17.5.5.2 D7—Auto Acknowledge Configuration (AA_CONFIG) ...................... 17-14

)......................................................................................... 17-8

)........................................................................................ 17-9

A)......................................................................... 17-9

/PP7)................................................................... 17-10

/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7)....... 17-12

) ....................................................................................... 17-12

).......................................................................................... 17-12

)........................................................................................... 17-13

) Configuration ......................................... 17-14

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17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0])........................... 17-14

17.5.6 D4—Address Configuration (ADDR_CONFIG)....................................... 17-14

17.5.7 D[3:2]—Frequency Control PLL (FREQ[1:0]..........................................) 17-15

17.5.8 D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])....................... 17-15

17.6 Chip-Select Module Signals ........................................................................... 17-15

17.6.1 Chip-Select (CS[7:0])................................................................................. 17-16

17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16

17.6.3 Output Enable (OE).................................................................................... 17-16

17.7 DRAM Controller Signals .............................................................................. 17-16

17.7.1 Row Address Strobes (RAS[1:0])............................................................... 17-16

17.7.2 Column Address Strobes (CAS[3:0])......................................................... 17-16

17.7.3 DRAM Write (DRAMW)........................................................................... 17-17

17.7.4 Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17

17.7.5 Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17

17.7.6 Synchronous DRAM Clock Enable (SCKE).............................................. 17-17

17.7.7 Synchronous Edge Select (EDGESEL)...................................................... 17-17

17.8 DMA Controller Module Signals.................................................................... 17-17

17.8.1 DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-18

17.9 Serial Module Signals..................................................................................... 17-18

17.9.1 Transmitter Serial Data Output (TxD)........................................................ 17-18

17.9.2 Receiver Serial Data Input (RxD)............................................................... 17-18

17.9.3 Clear to Send (CTS).................................................................................... 17-18

17.9.4 Request to Send (RTS) ............................................................................... 17-18

17.10 Timer Module Signals..................................................................................... 17-18

17.10.1 Timer Inputs (TIN[1:0]).............................................................................. 17-19

17.10.2 Timer Outputs (TOUT1, TOUT0).............................................................. 17-19

17.11 Parallel I/O Port (PP[15:0]) ............................................................................ 17-19

17.12 I2C Module Signals ........................................................................................ 17-19

17.12.1 I2C Serial Clock (SCL)............................................................................... 17-19

17.12.2 I2C Serial Data (SDA)................................................................................ 17-19

17.13 Debug and Test Signals .................................................................................. 17-20

17.13.1 Test Mode (MTMOD[3:0]) ........................................................................ 17-20

17.13.2 High Impedance (HIZ

17.13.3 Processor Clock Output (PSTCLK)............................................................ 17-20

17.13.4 Debug Data (DDATA[3:0])........................................................................ 17-20

17.13.5 Processor Status (PST[3:0])........................................................................ 17-20

17.14 Debug Module/JTAG Signals......................................................................... 17-21

17.14.1 Test Reset/Development Serial Clock (TRST

17.14.2 Test Mode Select/Breakpoint (TMS/BKPT

17.14.3 Test Data Input/Development Serial Input (TDI/DSI)............................... 17-22

17.14.4 Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22

17.14.5 Test Clock (TCK) ....................................................................................... 17-23

Title

)................................................................................ 17-20

/DSCLK) ............................ 17-21

) .............................................. 17-22

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Chapter 18

Bus Operation

18.1 Features............................................................................................................. 18-1

18.2 Bus and Control Signals ................................................................................... 18-1

18.3 Bus Characteristics............................................................................................ 18-2

18.4 Data Transfer Operation ................................................................................... 18-3

18.4.1 Bus Cycle Execution..................................................................................... 18-4

18.4.2 Data Transfer Cycle States ........................................................................... 18-5

18.4.3 Read Cycle.................................................................................................... 18-7

18.4.4 Write Cycle................................................................................................... 18-8

18.4.5 Fast-Termination Cycles............................................................................... 18-9

18.4.6 Back-to-Back Bus Cycles........................................................................... 18-10

18.4.7 Burst Cycles................................................................................................ 18-11

18.4.7.1 Line Transfers......................................................................................... 18-12

18.4.7.2 Line Read Bus Cycles............................................................................. 18-12

18.4.7.3 Line Write Bus Cycles............................................................................ 18-14

18.4.7.4 Transfers Using Mixed Port Sizes .......................................................... 18-15

18.5 Misaligned Operands...................................................................................... 18-16

18.6 Bus Errors ....................................................................................................... 18-17

18.7 Interrupt Exceptions........................................................................................ 18-17

18.7.1 Level 7 Interrupts........................................................................................ 18-18

18.7.2 Interrupt-Acknowledge Cycle..................................................................... 18-19

18.8 Bus Arbitration................................................................................................ 18-20

18.8.1 Bus Arbitration Signals............................................................................... 18-21

18.9 General Operation of External Master Transfers............................................ 18-21

18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire Mode)......................... 18-25

18.9.2 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29

18.10 Reset Operation............................................................................................... 18-33

18.10.1 Master Reset ............................................................................................... 18-34

18.10.2 Software Watchdog Reset........................................................................... 18-35

Chapter 19

IEEE 1149.1 Test Access Port (JTAG)

19.1 Overview........................................................................................................... 19-1

19.2 JTAG Signal Descriptions ............................................................................... 19-2

19.3 TAP Controller.................................................................................................. 19-3

19.4 JTAG Register Descriptions............................................................................. 19-4

19.4.1 JTAG Instruction Shift Register.................................................................. 19-5

19.4.2 IDCODE Register......................................................................................... 19-6

19.4.3 JTAG Boundary-Scan Register .................................................................... 19-7

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19.4.4 JTAG Bypass Register................................................................................ 19-10

19.5 Restrictions ..................................................................................................... 19-10

19.6 Disabling IEEE Standard 1149.1 Operation................................................... 19-11

19.7 Obtaining the IEEE Standard 1149.1.............................................................. 19-12

Title

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Chapter 20

Electrical Specifications

20.1 General Parameters........................................................................................... 20-1

20.2 Clock Timing Specifications............................................................................. 20-2

20.3 Input/Output AC Timing Specifications........................................................... 20-3

20.4 Reset Timing Specifications........................................................................... 20-12

20.5 Debug AC Timing Specifications................................................................... 20-12

20.6 Timer Module AC Timing Specifications ...................................................... 20-14

20.7 I

20.8 UART Module AC Timing Specifications..................................................... 20-16

20.9 Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-18

20.10 DMA Timing Specifications........................................................................... 20-19

20.11 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-20

C Input/Output Timing Specifications......................................................... 20-15

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ILLUSTRATIONS

Figure Number

1-1 MCF5307 Block Diagram.............................................................................................1-2

1-2 UART Module Block Diagram..................................................................................... 1-9

1-3 PLL Module................................................................................................................1-12

1-4 ColdFire MCF5307 Programming Model ..................................................................1-13

2-1 ColdFire Enhanced Pipeline .......................................................................................2-23

2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25

2-3 ColdFire Programming Model....................................................................................2-27

2-5 Status Register (SR)....................................................................................................2-30

2-6 Vector Base Register (VBR)....................................................................................... 2-30

2-7 Organization of Integer Data Formats in Data Registers............................................ 2-32

2-8 Organization of Integer Data Formats in Address Registers...................................... 2-32

2-9 Memory Operand Addressing..................................................................................... 2-33

2-10 Exception Stack Frame Form......................................................................................2-49

3-1 ColdFire MAC Multiplication and Accumulation........................................................3-2

3-2 MAC Programming Model...........................................................................................3-2

4-1 SRAM Base Address Register (RAMBAR).................................................................4-3

4-2 Unified Cache Organization .........................................................................................4-7

4-3 Cache Organization and Line Format...........................................................................4-8

4-4 Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern....................... 4-10

4-5 Caching Operation...................................................................................................... 4-11

4-6 Write-Miss in Copyback Mode................................................................................... 4-16

4-7 Cache Locking............................................................................................................ 4-20

4-8 Cache Control Register (CACR) ................................................................................4-21

4-9 Access Control Register Format (ACRn)................................................................... 4-23

4-10 A

4-11 Cache Line State Diagram—Copyback Mode............................................................ 4-26

4-12 Cache Line State Diagram—Write-Through Mode.................................................... 4-26

5-1 Processor/Debug Module Interface...............................................................................5-1

5-2 PSTCLK Timing...........................................................................................................5-3

5-3 Example JMP Instruction Output on PST/DDATA......................................................5-5

5-4 Debug Programming Model .........................................................................................5-6

5-5 Address Attribute Trigger Register (AATR)................................................................5-7

5-6 Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9

5-7 BDM Address Attribute Register (BAAR)................................................................... 5-9

5-8 Configuration/Status Register (CSR).......................................................................... 5-10

5-9 Data Breakpoint/Mask Registers (DBR and DBMR).................................................5-12

Format ..................................................................................................................4-24

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Figure Number

Title

Page

Number

5-10 Program Counter Breakpoint Register (PBR).............................................................5-14

5-11 Program Counter Breakpoint Mask Register (PBMR)...............................................5-14

5-12 Trigger Definition Register (TDR).............................................................................5-15

5-13 BDM Serial Interface Timing.....................................................................................5-18

5-14 Receive BDM Packet..................................................................................................5-19

5-15 Transmit BDM Packet ................................................................................................ 5-19

5-16 BDM Command Format............................................................................................. 5-21

5-17 Command Sequence Diagram.....................................................................................5-22

5-19 5-18 5-21 5-20 5-23 5-22 5-24 5-25 5-26 5-27 5-28 5-29 5-31 5-30 5-33 5-32 5-35 5-34 5-37 5-36 5-39 5-38 5-41 5-40 5-43 5-42

RAREG/RDREG RAREG/RDREG WAREG/WDREG WAREG/WDREG READ

Command Sequence..........................................................................................5-26

READ

Command/Result Formats................................................................................. 5-26

WRITE WRITE DUMP

Command/Result Formats................................................................................ 5-29

DUMP

Command Sequence ......................................................................................... 5-30

FILL

Command Format................................................................................................5-31

FILL

Command Sequence............................................................................................ 5-32

Command Sequence..............................................................................................5-33

GO Command Format.................................................................................................. 5-33

NOP Command Sequence............................................................................................ 5-34

NOP Command Format................................................................................................5-34

SYNC_PC Command Sequence....................................................................................5-35

SYNC_PC Command Format........................................................................................5-35

RCREG Command Sequence........................................................................................5-36

RCREG Command/Result Formats............................................................................... 5-36

WCREG Command Sequence.......................................................................................5-37

WCREG Command/Result Formats..............................................................................5-37

RDMREG Command Sequence.....................................................................................5-38

RDMREG bdm Command/Result Formats.................................................................... 5-38

WDMREG Command Sequence....................................................................................5-39

WDMREG BDM Command Format.............................................................................. 5-39

Command Sequence............................................................................ 5-24

Command Format ............................................................................... 5-24

Command Sequence..........................................................................5-25

Command Format.............................................................................. 5-25

Command Format............................................................................................ 5-27

Command Sequence ........................................................................................5-28

5-44 Recommended BDM Connector................................................................................. 5-42

6-1 SIM Block Diagram......................................................................................................6-1

6-2 Module Base Address Register (MBAR) .....................................................................6-4

6-3 Reset Status Register (RSR) ......................................................................................... 6-5

6-4 MCF5307 Embedded System Recovery from Unterminated Access........................... 6-7

6-5 System Protection Control Register (SYPCR) .............................................................6-8

6-6 Software Watchdog Interrupt Vector Register (SWIVR).............................................6-9

6-7 Software Watchdog Service Register (SWSR)............................................................. 6-9

6-8 Pin Assignment Register (PAR) ................................................................................. 6-10

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6-9 Default Bus Master Register (MPARK).....................................................................6-11

6-10 Round Robin Arbitration (PARK = 00)...................................................................... 6-12

6-11 Park on Master Core Priority (PARK = 01) ............................................................... 6-13

6-12 Park on DMA Module Priority (PARK = 10)............................................................. 6-13

6-13 Park on Current Master Priority (PARK = 01)...........................................................6-14

7-1 PLL Module Block Diagram ........................................................................................7-1

7-2 PLL Control Register (PLLCR).................................................................................... 7-3

7-3 CLKIN, PCLK, PSTCLK, and BCLKO Timing..........................................................7-5

7-4 Reset and Initialization Timing..................................................................................... 7-6

7-5 PLL Power Supply Filter Circuit..................................................................................7-6

8-1 I 8-2 I

8-3 Repeated START..........................................................................................................8-4

8-4 Synchronized Clock SCL.............................................................................................. 8-5

8-5 I 8-6 I 8-7 I 8-8 I 8-9 I 8-10 Flow-Chart of Typical I

9-1 Interrupt Controller Block Diagram..............................................................................9-1

9-2 Interrupt Control Registers (ICR0–ICR9) ....................................................................9-3

9-3 Autovector Register (AVR)..........................................................................................9-5

9-4 Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR).........................9-7

9-5 Interrupt Port Assignment Register (IRQPAR)............................................................9-7

10-1 Connections for External Memory Port Sizes ............................................................10-4

10-2 Chip Select Address Registers (CSAR0–CSAR7) .....................................................10-6

10-3 Chip Select Mask Registers (CSMRn) .......................................................................10-7

10-4 Chip-Select Control Registers (CSCR0–CSCR7) ......................................................10-8

11-1 Asynchronous/Synchronous DRAM Controller Block Diagram ...............................11-2

11-2 DRAM Control Register (DCR) (Asynchronous Mode)............................................11-5

11-3 DRAM Address and Control Registers (DACR0/DACR1)........................................11-6

11-4 DRAM Controller Mask Registers (DMR0 and DMR1)............................................ 11-7

11-5 Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4) .......................... 11-11

11-6 Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5) .......................... 11-12

11-7 Burst Page-Mode Read Operation (4-3-3-3).............................................................11-13

11-8 Burst Page-Mode Write Operation (4-3-3-3)............................................................ 11-13

11-9 Continuous Page-Mode Operation............................................................................ 11-14

11-10 Write Hit in Continuous Page Mode......................................................................... 11-15

11-11 EDO Read Operation (3-2-2-2) ................................................................................11-15

11-12 DRAM Access Delayed by Refresh .........................................................................11-16

11-13 MCF5307 SDRAM Interface.................................................................................... 11-18

11-14 Using EDGESEL to Change Signal Timing.............................................................11-19

C Module Block Diagram..........................................................................................8-2

C Standard Communication Protocol ........................................................................8-3

C Address Register (IADR).......................................................................................8-6

C Frequency Divider Register (IFDR)....................................................................... 8-7

C Control Register (I2CR).........................................................................................8-8

CR Status Register (I2SR) ......................................................................................... 8-9

C Data I/O Register (I2DR)..................................................................................... 8-10

C Interrupt Routine ............................................................. 8-14

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11-15 DRAM Control Register (DCR) (Synchronous Mode)............................................ 11-19

11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20

11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22

11-18 Burst Read SDRAM Access.....................................................................................11-28

11-19 Burst Write SDRAM Access.................................................................................... 11-29

11-20 Synchronous, Continuous Page-Mode Access—Consecutive Reads.......................11-30

11-21 Synchronous, Continuous Page-Mode Access—Read after Write........................... 11-31

11-22 Auto-Refresh Operation............................................................................................ 11-32

11-23 Self-Refresh Operation ............................................................................................. 11-32

11-24 Mode Register Set (mrs) Command .........................................................................11-34

11-25 Initialization Values for DCR...................................................................................11-35

11-26 SDRAM Configuration.............................................................................................11-36

11-27 DACR Register Configuration.................................................................................. 11-36

11-28 DMR0 Register.........................................................................................................11-37

11-29 Mode Register Mapping to MCF5307 A[31:0]........................................................ 11-38

12-1 DMA Signal Diagram.................................................................................................12-1

12-2 Dual-Address Transfer................................................................................................ 12-3

12-3 Single-Address Transfers............................................................................................ 12-4

12-4 Source Address Registers (SARn)..............................................................................12-6

12-5 Destination Address Registers (DARn)......................................................................12-7

12-6 Byte Count Registers (BCRn)—BCR24BIT = 1........................................................12-7

12-7 BCRn—BCR24BIT = 0..............................................................................................12-8

12-8 DMA Control Registers (DCRn)............................................................................... 12-8

12-9 DMA Status Registers (DSRn)................................................................................12-10

12-10 DMA Interrupt Vector Registers (DIVRn)...............................................................12-11

12-11 DREQ Timing Constraints, Dual-Address DMA Transfer.......................................12-15

12-12 Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer...................12-16

12-13 Single-Address DMA Transfer.................................................................................12-17

13-1 Timer Block Diagram................................................................................................. 13-1

13-2 Timer Mode Registers (TMR0/TMR1) ......................................................................13-3

13-3 Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4

13-4 Timer Capture Register (TCR0/TCR1) ......................................................................13-5

13-5 Timer Counters (TCN0/TCN1)...................................................................................13-5

13-6 Timer Event Registers (TER0/TER1)......................................................................... 13-5

14-1 Simplified Block Diagram..........................................................................................14-1

14-2 UART Mode Registers 1 (UMR1n)............................................................................ 14-5

14-3 UART Mode Register 2 (UMR2n)............................................................................. 14-6

14-4 UART Status Register (USRn)...................................................................................14-7

14-5 UART Clock-Select Register (UCSRn)......................................................................14-8

14-6 UART Command Register (UCRn)............................................................................ 14-9

14-7 UART Receiver Buffer (URB0)...............................................................................14-11

14-8 UART Transmitter Buffer (UTB0)...........................................................................14-12

14-9 UART Input Port Change Register (UIPCRn)..........................................................14-12

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Figure Number

14-10 UART Auxiliary Control Register (UACRn)...........................................................14-13

14-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-13

14-12 UART Divider Upper Register (UDUn)................................................................... 14-14

14-13 UART Divider Lower Register (UDLn)................................................................... 14-14

14-14 UART Interrupt Vector Register (UIVRn)...............................................................14-15

14-15 UART Input Port Register (UIPn)............................................................................14-15

14-17 UART Block Diagram Showing External and Internal Interface Signals................ 14-16

14-16 UART Output Port Command Register (UOP1/UOP0)...........................................14-16

14-18 UART/RS-232 Interface...........................................................................................14-17

14-19 Clocking Source Diagram......................................................................................... 14-18

14-20 Transmitter and Receiver Functional Diagram......................................................... 14-20

14-21 Transmitter Timing Diagram....................................................................................14-22

14-22 Receiver Timing........................................................................................................14-23

14-23 Automatic Echo ........................................................................................................14-25

14-24 Local Loop-Back ......................................................................................................14-26

14-25 Remote Loop-Back...................................................................................................14-26

14-26 Multidrop Mode Timing Diagram............................................................................ 14-27

14-27 UART Mode Programming Flowchart.....................................................................14-30

15-1 Parallel Port Pin Assignment Register (PAR) ............................................................15-1

15-2 Port A Data Direction Register (PADDR).................................................................. 15-2

15-3 Port A Data Register (PADAT)..................................................................................15-3

16-1 Mechanical Diagram...................................................................................................16-9

16-2 MCF5307 Case Drawing (General View) ................................................................ 16-10

16-3 Case Drawing (Details)............................................................................................. 16-11

17-1 MCF5307 Block Diagram with Signal Interfaces ......................................................17-2

18-1 Signal Relationship to BCLKO for Non-DRAM Access........................................... 18-2

18-2 Connections for External Memory Port Sizes ............................................................18-4

18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4

18-4 Data Transfer State Transition Diagram.....................................................................18-6

18-5 Read Cycle Flowchart................................................................................................. 18-7

18-6 Basic Read Bus Cycle.................................................................................................18-8

18-7 Write Cycle Flowchart................................................................................................18-9

18-8 Basic Write Bus Cycle................................................................................................18-9

18-9 Read Cycle with Fast Termination ...........................................................................18-10

18-10 Write Cycle with Fast Termination...........................................................................18-10

18-11 Back-to-Back Bus Cycles......................................................................................... 18-11

18-12 Line Read Burst (2-1-1-1), External Termination ....................................................18-12

18-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13

18-14 Line Read Burst (3-2-2-2), External Termination ....................................................18-13

18-15 Line Read Burst-Inhibited, Fast, External Termination............................................18-14

18-16 Line Write Burst (2-1-1-1), Internal/External Termination......................................18-14

18-17 Line Write Burst (3-2-2-2) with One Wait State, Internal Termination...................18-15

18-18 Line Write Burst-Inhibited, Internal Termination .................................................... 18-15

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ILLUSTRATIONS

Figure Number

18-19 Longword Read from an 8-Bit Port, External Termination......................................18-16

18-20 Longword Read from an 8-Bit Port, Internal Termination.......................................18-16

18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17

18-22 Example of a Misaligned Word Transfer (32-Bit Port)............................................18-17

18-23 Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20

18-24 Basic No-Wait-State External Master Access ..........................................................18-22

18-25 External Master Burst Line Access to 32-Bit Port....................................................18-24

18-26 MCF5307 Two-Wire Mode Bus Arbitration Interface.............................................18-25

18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26

18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27

18-29 MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................18-28

18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30

18-31 Three-Wire Bus Arbitration......................................................................................18-31

18-32 Three-Wire Bus Arbitration Protocol State Diagram ...............................................18-32

18-33 Master Reset Timing................................................................................................. 18-34

18-34 Software Watchdog Reset Timing............................................................................18-36

19-1 JTAG Test Logic Block Diagram...............................................................................19-2

19-2 JTAG TAP Controller State Machine......................................................................... 19-4

19-4 Disabling JTAG in JTAG Mode...............................................................................19-11

19-5 Disabling JTAG in Debug Mode..............................................................................19-11

20-1 Clock Timing.............................................................................................................. 20-3

20-2 PSTCLK Timing.........................................................................................................20-3

20-3 AC Timings—Normal Read and Write Bus Cycles................................................... 20-5

20-4 SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO.............................. 20-6

20-5 SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO............................. 20-7

20-6 SDRAM Read Cycle with EDGESEL Tied High.......................................................20-8

20-7 SDRAM Write Cycle with EDGESEL Tied High...................................................... 20-9

20-8 SDRAM Read Cycle with EDGESEL Tied Low..................................................... 20-10

20-9 SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-11

20-10 AC Output Timing—High Impedance......................................................................20-11

20-11 Reset Timing.............................................................................................................20-12

20-12 Real-Time Trace AC Timing....................................................................................20-13

20-13 BDM Serial Port AC Timing....................................................................................20-13

20-14 Timer Module AC Timing........................................................................................20-14

20-15 I

20-16 UART0/1 Module AC Timing—UART Mode.........................................................20-17

20-17 General-Purpose I/O Timing.....................................................................................20-18

20-18 DMA Timing ............................................................................................................20-19

20-19 IEEE 1149.1 (JTAG) AC Timing.............................................................................20-21

C Input/Output Timings.........................................................................................20-16

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TABLES

Table Number

1-1 User-Level Registers................................................................................................... 1-14

1-2 Supervisor-Level Registers.........................................................................................1-14

2-1 CCR Field Descriptions .............................................................................................2-28

2-2 MOVEC Register Map ...............................................................................................2-29

2-3 Status Field Descriptions ............................................................................................ 2-30

2-4 Integer Data Formats...................................................................................................2-31

2-5 ColdFire Effective Addressing Modes........................................................................2-34

2-6 Notational Conventions ..............................................................................................2-34

2-7 User-Mode Instruction Set Summary ......................................................................... 2-37

2-8 Supervisor-Mode Instruction Set Summary................................................................2-40

2-9 Misaligned Operand References.................................................................................2-41

2-10 Move Byte and Word Execution Times......................................................................2-42

2-11 Move Long Execution Times......................................................................................2-42

2-12 MAC Move Execution Times.....................................................................................2-43

2-13 One-Operand Instruction Execution Times................................................................ 2-43

2-14 Two-Operand Instruction Execution Times................................................................2-44

2-15 Miscellaneous Instruction Execution Times...............................................................2-45

2-16 General Branch Instruction Execution Times............................................................. 2-46

2-17 Bcc Instruction Execution Times................................................................................ 2-47

2-18 Exception Vector Assignments................................................................................... 2-48

2-19 Format Field Encoding ...............................................................................................2-49

2-20 Fault Status Encodings................................................................................................ 2-50

2-21 MCF5307 Exceptions ................................................................................................. 2-50

3-1 MAC Instruction Summary...........................................................................................3-4

3-2 Two-Operand MAC Instruction Execution Times .......................................................3-5

3-3 MAC Move Instruction Execution Times.....................................................................3-6

4-1 RAMBAR Field Description ........................................................................................ 4-3

4-2 Examples of Typical RAMBAR Settings.....................................................................4-6

4-3 Valid and Modified Bit Settings................................................................................... 4-8

4-4 CACR Field Descriptions........................................................................................... 4-21

4-5 ACRn Field Descriptions............................................................................................4-23

4-6 Cache Line State Transitions...................................................................................... 4-27

4-7 Cache Line State Transitions (Current State Invalid).................................................4-28

4-8 Cache Line State Transitions (Current State Valid) ................................................... 4-28

4-9 Cache Line State Transitions (Current State Modified) ............................................. 4-29

5-1 Debug Module Signals.................................................................................................. 5-2

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TABLES

Table Number

5-2 Processor Status Encoding............................................................................................5-4

5-3 BDM/Breakpoint Registers........................................................................................... 5-7

5-4 AATR Field Descriptions............................................................................................. 5-8

5-5 ABLR Field Description...............................................................................................5-9

5-6 ABHR Field Description...............................................................................................5-9

5-7 BAAR Field Descriptions...........................................................................................5-10

5-8 CSR Field Descriptions .............................................................................................. 5-11

5-9 DBR Field Descriptions..............................................................................................5-13

5-10 DBMR Field Descriptions .......................................................................................... 5-13

5-11 Access Size and Operand Data Location....................................................................5-13

5-12 PBR Field Descriptions .............................................................................................. 5-14

5-13 PBMR Field Descriptions...........................................................................................5-14

5-14 TDR Field Descriptions..............................................................................................5-15

5-15 Receive BDM Packet Field Description.....................................................................5-19

5-16 Transmit BDM Packet Field Description ...................................................................5-19

5-17 BDM Command Summary......................................................................................... 5-20

5-18 BDM Field Descriptions.............................................................................................5-21

5-19 Control Register Map.................................................................................................. 5-36

5-20 Definition of DRc Encoding—Read...........................................................................5-38

5-21 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................... 5-40

5-22 PST/DDATA Specification for User-Mode Instructions............................................ 5-43

5-23 PST/DDATA Specification for Supervisor-Mode Instructions..................................5-46

6-1 SIM Registers ..............................................................................................................6-3

6-2 MBAR Field Descriptions ............................................................................................ 6-5

6-3 RSR Field Descriptions ................................................................................................ 6-6

6-4 SYPCR Field Descriptions ...........................................................................................6-8

6-5 PLLIPL Settings ......................................................................................................... 6-10

6-6 MPARK Field Descriptions........................................................................................6-11

7-1 PLLCR Field Descriptions............................................................................................ 7-3

7-2 PLL Module Input SIgnals............................................................................................7-3

7-3 PLL Module Output Signals.........................................................................................7-4

8-1 I 8-2 I

8-3 IFDR Field Descriptions...............................................................................................8-7

8-4 I 8-5 I

9-1 Interrupt Controller Registers....................................................................................... 9-2

9-2 Interrupt Control Registers ...........................................................................................9-2

9-3 ICRn Field Descriptions ...............................................................................................9-3

9-4 Interrupt Priority Scheme.............................................................................................. 9-4

9-5 AVR Field Descriptions................................................................................................ 9-6

9-6 Autovector Register Bit Assignments........................................................................... 9-6

9-7 IPR and IMR Field Descriptions...................................................................................9-7

C Interface Memory Map........................................................................................... 8-6

C Address Register Field Descriptions......................................................................8-6

CR Field Descriptions................................................................................................8-8

SR Field Descriptions ................................................................................................ 8-9

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TABLES

Table Number

9-8 IRQPAR Field Descriptions .........................................................................................9-8

10-1 Chip-Select Module Signals .......................................................................................10-1

10-2 Byte Enables/Byte Write Enable Signal Settings ....................................................... 10-2

10-3 Accesses by Matches in CSCRs and DACRs.............................................................10-3

10-4 D7/AA, Automatic Acknowledge of Boot CS0.......................................................... 10-4

10-5 D[6:5]/PS[1:0], Port Size of Boot CS0.......................................................................10-4

10-6 Chip-Select Registers.................................................................................................. 10-5

10-7 CSARn Field Description........................................................................................... 10-6

10-8 CSMRn Field Descriptions.........................................................................................10-7

10-9 CSCRn Field Descriptions..........................................................................................10-8

11-1 DRAM Controller Registers....................................................................................... 11-3

11-2 SDRAM Signal Summary ......................................................................................... 11-4

11-3 DCR Field Descriptions (Asynchronous Mode)......................................................... 11-5

11-4 DACR0/DACR1 Field Description ............................................................................ 11-6

11-5 DMR0/DMR1 Field Descriptions............................................................................... 11-7

11-6 Generic Address Multiplexing Scheme...................................................................... 11-8

11-7 DRAM Addressing for Byte-Wide Memories..........................................................11-10

11-8 DRAM Addressing for 16-Bit Wide Memories........................................................11-10

11-9 DRAM Addressing for 32-Bit Wide Memories........................................................11-11

11-10 SDRAM Commands.................................................................................................11-17

11-11 Synchronous DRAM Signal Connections ................................................................11-17

11-12 DCR Field Descriptions (Synchronous Mode).........................................................11-19

11-13 DACR0/DACR1 Field Descriptions (Synchronous Mode)......................................11-21

11-14 DMR0/DMR1 Field Descriptions............................................................................. 11-23

11-15 MCF5307 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 11-24

11-16 MCF5307 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 11-24

11-17 MCF5307 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................. 11-24

11-18 MCF5307 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................. 11-24

11-19 MCF5307 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 11-25

11-20 MCF5307 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 11-25

11-21 MCF5307 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)................ 11-25

11-22 MCF5307 to SDRAM Interface (16-Bit Port, 10-Column Address Lines).............. 11-25

11-23 MCF5307 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 11-25

11-24 MCF5307 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 11-26

11-25 MCF5307to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ..............11-26

11-26 MCF5307 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26

11-27 MCF5307 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26

11-28 MCF5307 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 11-26

11-29 MCF5307 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 11-27

11-30 MCF5307 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 11-27

11-31 SDRAM Hardware Connections...............................................................................11-27

11-32 SDRAM Example Specifications .............................................................................11-34

11-33 SDRAM Hardware Connections...............................................................................11-35

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TABLES

Table Number

11-34 DCR Initialization Values......................................................................................... 11-35

11-35 DACR Initialization Values......................................................................................11-36

11-36 DMR0 Initialization Values......................................................................................11-37

11-37 Mode Register Initialization .....................................................................................11-38

12-1 DMA Signals ..............................................................................................................12-2

12-2 Memory Map for DMA Controller Module Registers................................................ 12-5

12-3 DCRn Field Descriptions............................................................................................12-8

12-4 DSRn Field Descriptions .......................................................................................... 12-10

13-1 General-Purpose Timer Module Memory Map .......................................................... 13-3

13-2 TMRn Field Descriptions ...........................................................................................13-4

13-3 TERn Field Descriptions.............................................................................................13-6

13-5 Calculated Time-out Values (90-MHz Processor Clock)........................................... 13-7

14-1 UART Module Programming Model.......................................................................... 14-3

14-2 UMR1n Field Descriptions.........................................................................................14-5

14-3 UMR2n Field Descriptions.........................................................................................14-6

14-4 USRn Field Descriptions ............................................................................................ 14-7

14-5 UCSRn Field Descriptions.......................................................................................... 14-9

14-6 UCRn Field Descriptions............................................................................................14-9

14-7 UIPCRn Field Descriptions ...................................................................................... 14-12

14-8 UACRn Field Descriptions.......................................................................................14-13

14-9 UISRn/UIMRn Field Descriptions ...........................................................................14-14

14-10 UIVRn Field Descriptions ........................................................................................ 14-15

14-11 UIPn Field Descriptions............................................................................................ 14-15

14-12 UOP1/UOP0 Field Descriptions...............................................................................14-16

14-13 UART Module Signals .............................................................................................14-17

14-14 UART Module Initialization Sequence ....................................................................14-29

15-1 Parallel Port Pin Descriptions.....................................................................................15-2

15-2 PADDR Field Description..........................................................................................15-2

15-3 Relationship between PADAT Register and Parallel Port Pin (PP)........................... 15-3

16-1 Pins 1–52 (Left, Top-to-Bottom)................................................................................16-1

16-2 Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3

16-3 Pins 105–156 (Right, Bottom-to-Top)........................................................................16-4

16-4 Pins 157–208 (Top, Right-to-Left)............................................................................. 16-6

16-5 Dimensions ...............................................................................................................16-11

17-1 MCF5307 Signal Index............................................................................................... 17-3

17-2 Data Pin Configuration............................................................................................... 17-6

17-3 Bus Cycle Size Encoding............................................................................................ 17-7

17-4 Bus Cycle Transfer Type Encoding............................................................................17-9

17-5 TM[2:0] Encodings for TT = 00 (Normal Access).....................................................17-9

17-6 TM0 Encoding for DMA as Master (TT = 01)...........................................................17-9

17-7 TM[2:1] Encoding for DMA as Master (TT = 01)................................................... 17-10

17-8 TM[2:0] Encodings for TT = 10 (Emulator Access)................................................ 17-10

17-9 TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-10

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TABLES

Table Number

17-10 Data Pin Configuration............................................................................................. 17-12

17-11 D7 Selection of CS0 Automatic Acknowledge ........................................................17-13

17-12 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-13

17-13 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-13

17-14 CLKIN Frequency ....................................................................................................17-13

17-15 BCLKO/PSTCLK Divide Ratios..............................................................................17-14

17-16 Processor Status Signal Encodings...........................................................................17-19

18-1 ColdFire Bus Signal Summary ................................................................................... 18-1

18-2 Bus Cycle Size Encoding............................................................................................ 18-3

18-3 Accesses by Matches in CSCRs and DACRs.............................................................18-5

18-4 Bus Cycle States .........................................................................................................18-6

18-5 Allowable Line Access Patterns ............................................................................... 18-12

18-6 MCF5307 Arbitration Protocol States...................................................................... 18-20

18-7 ColdFire Bus Arbitration Signal Summary...............................................................18-21

18-8 Cycles for Basic No-Wait-State External Master Access......................................... 18-23

18-9 Cycles for External Master Burst Line Access to 32-Bit Port..................................18-24

18-10 MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions....................18-28

18-11 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32

18-12 Data Pin Configuration............................................................................................. 18-35

19-1 JTAG Pin Descriptions............................................................................................... 19-3

19-2 JTAG Instructions.......................................................................................................19-5

19-3 IDCODE Bit Assignments..........................................................................................19-6

19-4 Boundary-Scan Bit Definitions................................................................................... 19-7

20-1 Absolute Maximum Ratings....................................................................................... 20-1

20-2 Operating Temperatures..............................................................................................20-1

20-3 DC Electrical Specifications.......................................................................................20-2

20-4 Clock Timing Specification........................................................................................20-2

20-5 Input AC Timing Specification................................................................................... 20-3

20-6 Output AC Timing Specification................................................................................20-4

20-7 Reset Timing Specification....................................................................................... 20-12

20-8 Debug AC Timing Specification ..............................................................................20-12

20-9 Timer Module AC Timing Specification..................................................................20-14

20-10 I 20-11 I

20-12 UART Module AC Timing Specifications............................................................... 20-16

20-13 General-Purpose I/O Port AC Timing Specifications............................................... 20-18

20-14 DMA AC Timing Specifications.............................................................................. 20-19

20-15 IEEE 1149.1 (JTAG) AC Timing Specifications .....................................................20-20

A-1 SIM Registers............................................................................................................... A-1

A-2 Interrupt Controller Registers...................................................................................... A-1

A-3 Chip-Select Registers................................................................................................... A-2

A-4 DRAM Controller Registers........................................................................................ A-3

A-5 General-Purpose Timer Registers................................................................................A-4

C Input Timing Specifications between SCL and SDA......................................... 20-15

C Output Timing Specifications between SCL and SDA......................................20-15

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TABLES

Table Number

A-6 UART0 Control Registers............................................................................................ A-4

A-7 UART1 Control Registers............................................................................................ A-6

A-8 Parallel Port Memory Map........................................................................................... A-7

A-9 I

A-10 DMA Controller Registers...........................................................................................A-8

C Interface Memory Map.......................................................................................... A-8

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About This Book

The primary objective of this user’s manual is to deﬁne the functionality of the MCF5307 processors for use by software and hardware developers.

The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation.

T o locate an y published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldﬁre.

Audience

This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MCF5307. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire architecture.

Organization

Following is a summary and a brief description of the major sections of this manual:

• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in the MCF5307, focussing in particular on new features.

• Part I is intended for system designers who need to understand the operation of the MCF5307 ColdFire core.

— Chapter 2, “ColdFire Core,” provides an ov erview of the microprocessor core of

the MCF5307. The chapter begins with a description of enhancements from the V2 ColdFire core, and then fully describes the V3 programming model as it is implemented on the MCF5307. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings.

— Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the

MCF5307 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).

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Organization

— Chapter 4, “Local Memory.” This chapter describes the MCF5307

implementation of the ColdFire V3 local memory speciﬁcation. It consists of the two following major sections.

– Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM

(SRAM) implementation. It covers general operations, conﬁguration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.

– Section 4.7, “Cache Overview,” describes the MCF5307 cache

implementation, including organization, conﬁguration, and coherency. It describes cache operations and how the cache interacts with other memory structures.

— Chapter 5, “Deb ug Support,” describes the Re vision C enhanced hardware debug

support in the MCF5307. This revision of the ColdFire debug architecture encompasses earlier revisions.

• Part II, “System Integration Module (SIM),” describes the system integration module, which provides overall control of the bus and serves as the interface between the ColdFire core processor complex and internal peripheral devices. It includes a general description of the SIM and individual chapters that describe components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt controller for peripherals, conﬁguration and operation of chip selects, and the SDRAM controller.

— Chapter 6, “SIM Overview,” describes the SIM programming model, bus

arbitration, and system-protection functions for the MCF5307.

— Chapter 7, “Phase-Locked Loop (PLL),” describes conﬁguration and operation

of the PLL module. It describes in detail the registers and signals that support the PLL implementation.

— Chapter 8, “I

protocol, clock synchronization, and the registers in the I

C Module,” describes the MCF5307 I2C module, including I2C

C programing model.

It also provides extensive programming examples.

— Chapter 9, “Interrupt Controller,” describes operation of the interrupt controller

portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme.

— Chapter 10, “Chip-Select Module,” describes the MCF5307 chip-select

implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers.

— Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”

describes conﬁguration and operation of the synchronous/asynchronous DRAM controller component of the SIM. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations.

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• Part III, “Peripheral Module,” describes the operation and conﬁguration of the MCF5307 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II.

— Chapter 12, “DMA Controller Module,” provides an overview of the DMA

controller module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations.

— Chapter 13, “Timer Module,” describes conﬁguration and operation of the two

general-purpose timer modules, timer 0 and timer 1. It includes programming examples.

— Chapter 14, “UART Modules,” describes the use of the universal

asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5307 and includes programming examples.

— Chapter 15, “Parallel Port (General-Purpose I/O),” describes the operation and

programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port.

• Part IV, “Hardware Interface,” provides a pinout and both electrical and functional descriptions of the MCF5307 signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams.

Organization

— Chapter 16, “Mechanical Data,” provides a functional pin listing and package

diagram for the MCF5307.

— Chapter 17, “Signal Descriptions,” provides an alphabetical listing of MCF5307

signals. This chapter describes the MCF5307 signals. In particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset.

— Chapter 18, “Bus Operation,” describes data transfers, error conditions, bus

arbitration, and reset operations. It describes transfers initiated by the MCF5307 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Note that Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,” describes DRAM cycles.

— Chapter 19, “IEEE 1149.1 Test Access Port (JTAG),” describes conﬁguration

and operation of the MCF5307 JT A G test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality.

— Chapter 20, “Electrical Speciﬁcations,” describes AC and DC electrical

speciﬁcations and thermal characteristics for the MCF5307. Because additional speeds may have become available since the publication of this book, consult Motorola’s ColdFire web page, http://www.motorola.com/coldﬁre, to conﬁrm that this is the latest information.

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Conventions

This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics In code and tables, instruction mnemonics are shown in lowercase.

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Acronyms and Abbreviations

italics Italics indicate variable command parameters.

Book titles in text are set in italics.

0x0 Preﬁx to denote hexadecimal number 0b0 Preﬁx to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Speciﬁc bits,

ﬁelds, or ranges appear in brackets. For example, RAMBAR[BA]

identiﬁes the base address ﬁeld in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don’t care.

n Used to express an undeﬁned numerical value ¬ NOT logical operator

& AND logical operator | OR logical operator

Acronyms and Abbreviations

Table i lists acronyms and abbreviations used in this document.

Table i. Acronyms and Abbreviated Terms

Term Meaning

ADC Analog-to-digital conversion ALU Arithmetic logic unit AVEC Autovector BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EA Effective address EDO Extended data output (DRAM) FIFO First-in, ﬁrst-out

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Acronyms and Abbreviations

Table i. Acronyms and Abbreviated Terms (Continued)

Term Meaning

GPIO General-purpose I/O

C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, ﬁrst-out LRU Least recently used LSB Least-signiﬁcant byte lsb Least-signiﬁcant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-signiﬁcant byte msb Most-signiﬁcant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad ﬂat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter

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Terminology and Notational Conventions

Table ii shows notational conventions used throughout this document.

Table ii Notational Conventions

Instruction Operand Syntax

Opcode Wildcard

cc Logical condition (example: NE for not equal)

An Any address register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any data register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Rc Any control register (example VBR is the vector base register)

Rm MAC registers (ACC, MAC, MASK)

Rn Any address or data register

Rw Destination register w (used for MAC instructions only)

Ry,Rx Any source and destination registers, respectively

Xi index register i (can be an address or data register: Ai, Di)

ACC MAC accumulator register CCR Condition code register (lower byte of SR)

MACSR MAC status register

MASK MAC mask register

PC Program counter SR Status register

Port Name

PSTDDATA Processor status/debug data port

Miscellaneous Operands

#<data> Immediate data following the 16-bit operation word of the instruction

Í Effective address

<ea>y,<ea>x Source and destination effective addresses, respectively

<label> Assembly language program label

<list> List of registers for MOVEM instruction (example: D3–D0) <shift> Shift operation: shift left (<<), shift right (>>) <size> Operand data size: byte (B), word (W), longword (L)

bc Both instruction and data caches dc Data cache

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Terminology and Notational Conventions

Table ii Notational Conventions (Continued)

Instruction Operand Syntax

ic Instruction cache

# <vector> Identiﬁes the 4-bit vector number for trap instructions

identiﬁes an indirect data address referencing memory

<xxx> identiﬁes an absolute address referencing memory

dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)

SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)

Operations

+ Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator

x Arithmetic multiplication

/ Arithmetic division ~ Invert; operand is logically complemented & Logical AND

| Logical OR

^ Logical exclusive OR

<< Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→ Source operand is moved to destination operand

←→ Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

If <condition>

then

else

{} Optional operation () Identiﬁes an indirect address

Address Calculated effective address (pointer)

Bit Bit selection (example: Bit 3 of D0)

lsb Least signiﬁcant bit (example: lsb of D0)

LSB Least signiﬁcant byte

LSW Least signiﬁcant word

msb Most signiﬁcant bit MSB Most signiﬁcant byte MSW Most signiﬁcant word

Test the condition. If true, the operations after ‘then’ are performed. If the condition is f alse and the optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.

Subﬁelds and Qualiﬁers

Displacement value, n-bits wide (example: d16 is a 16-bit displacement)

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Table ii Notational Conventions (Continued)

Instruction Operand Syntax

C Carry N Negative V Overﬂow X Extend Z Zero

Terminology and Notational Conventions

Condition Code Register Bit Names

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Terminology and Notational Conventions

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Chapter 1 Overview

This chapter is an overview of the MCF5307 ColdFire processor. It includes general descriptions of the modules and features incorporated in the MCF5307.

1.1 Features

The MCF5307 integrated microprocessor combines a V3 ColdFire processor core with the following components, as shown in Figure 1-1:

• 8-Kbyte uniﬁed cache

• 4-Kbyte on-chip SRAM

• Integer/fractional multiply-accumulate (MAC) unit

• Divide unit

• System debug interface

• DRAM controller for synchronous and asynchronous DRAM

• Four-channel DMA controller

• Two general-purpose timers

•Two UARTs

2C™

•I

• Parallel I/O interface

• System integration module (SIM)

Designed for embedded control applications, the MCF5307 delivers 75 Dhrystone 2.1 MIPS at 90 MHz while minimizing system costs.

interface

Chapter 1. Overview 1-1

Features

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JTAG

V3 COLDFIRE PROCESSOR COMPLEX

Instruction Unit

Branch Logic

CCR

GeneralPurpose Registers

A0–A7

D0–D7

DIV

Debug

Module

Local

BCLKO

(sent off-chip

and to on-chip

peripherals)

CLKIN

RSTI

PLL

X n

PSTCLK

PCLK RSTO

SRAM Controller

RAMBAR

4-Kbyte

SRAM

Cache Controller

CACR

ACR0 ACR1

8-Kbyte

Cache

Memory

Local Memory Bus

Instruction Fetch

IAG

Pipeline (IFP)

IC1 IC2 IED

Eight-Instruction FIFO Buffer

Operand Execution Pipeline (OEP)

DSOC

AGEX

4-Entry Store Buffer

MAC

SYSTEM INTEGRATION MODULE (SIM)

System Control PLL Control

SWIVR

DMR0/1

RSR

SWSR SYPCR

888

CSARs CSCRs CSMRs

PLL

DRAM Controller Chip-Select Module External

DRAM Control

DCR

Addr/Cntrl Mask

DACR0/1

DRAM Controller

Outputs

CS[7:0]

Base Address

MBAR

Bus Master Park

MPARK

Bus Interface

32-Bit Address Bus

32-Bit Data Bus

Control Signals

Figure 1-1. MCF5307 Block Diagram

1-2 MCF5307 User’s Manual

Parallel Port

PLL

Interrupt Controller

10 ICRs

IRQ

IRQPAR

IPR IMR AVR

[1,3,5,7]

DMA Four

Channels

Software Watchdog

C Module

Two UARTs

Two GeneralPurpose

Timers

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Features

Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated using advanced process technologies.

The MCF5307 extends the legacy of Motorola’ s 68K family by pro viding a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged. In fact, customers moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K assembly code to the ColdFire architecture.

Based on the concept of variable-length RISC technology, the ColdFire family combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In deﬁning the ColdFire architecture for embedded processing applications, a 68K-code compatible core combines performance advantages of a RISC architecture with the optimum code density of a streamlined, variable-length M68000 instruction set.

By using a variable-length instruction set architecture, embedded system designers using ColdFire RISC processors enjoy signiﬁcant advantages over conventional ﬁxed-length RISC architectures. The denser binary code for ColdFire processors consumes less memory than many ﬁxed-length instruction set RISC processors available. This improved code density means more efﬁcient system memory use for a giv en application and allows use of slower, less costly memory to help achieve a target performance level.

The MCF5307 is the ﬁrst standard product to implement the Version 3 ColdFire microprocessor core. To reach higher levels of frequency and performance, numerous enhancements were made to the V2 architecture. Most notable are a deeper instruction pipeline, branch acceleration, and a uniﬁed cache, which together provide 75 (Dhrystone

2.1) MIPS at 90 MHz. Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The processor complex frequency is an integer multiple, 2 to 4 times, of the external bus frequency. The core clock can be stopped to support a low-power mode.

Serial communication channels are provided by an I

C interface module and two programmable full-duplex UAR Ts. F our channels of DMA allow for fast data transfer using a programmable burst mode independent of processor execution. The two 16-bit general-purpose multimode timers provide separate input and output signals. For system protection, the processor includes a programmable 16-bit software watchdog timer. In addition, common system functions such as chip selects, interrupt control, bus arbitration, and an IEEE 1149.1 JTAG module are included. A sophisticated debug interface supports background-debug mode plus real-time trace and debug with expanded ﬂexibility of on-chip breakpoint registers. This interface is present in all ColdFire standard products and allows common emulator support across the entire family of microprocessors.

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MCF5307 Features

1.2 MCF5307 Features

The following list summarizes MCF5307 features:

• ColdFire processor core — Variable-length RISC, clock-multiplied Version 3 microprocessor core — Fully code compatible with Version 2 processors — T wo independent decoupled pipelines: four-stage instruction fetch pipeline (IFP)

and two-stage operand execution pipeline (OEP) — Eight-instruction FIFO buffer provides decoupling between the pipelines — Branch prediction mechanisms for accelerating program execution — 32-bit internal address bus supporting 4 Gbytes of linear address space — 32-bit data bus — 16 user-accessible, 32-bit-wide, general-purpose registers — Supervisor/user modes for system protection — Vector base register to relocate exception-vector table — Optimized for high-level language constructs

• Multiply and accumulate unit (MAC) — High-speed, complex arithmetic processing for DSP applications — Tightly coupled to the OEP — Three-stage execute pipeline with one clock issue rate for 16 x 16 operations — 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate — Signed or unsigned integer support, plus signed fractional operands

• Hardware integer divide unit — Unsigned and signed integer divide support — Tightly coupled to the OEP — 32/16 and 32/32 operation support producing quotient and/or remainder results

• 8-Kbyte uniﬁed cache — Four-way set-associative organization — Operates at higher processor core frequency — Provides pipelined, single-cycle access to critical code and data — Supports write-through and copyback modes — Four-entry, 32-bit store buffer to improve performance of operand writes

• 4-Kbyte SRAM — Programmable location anywhere within 4-Gbyte linear address space — Higher core-frequency operation — Pipelined, single-cycle access to critical code or data

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MCF5307 Features

• DMA controller — Four fully programmable channels: two support external requests — Dual-address and single-address transfer support with 8-, 16-, and 32-bit data

capability — Source/destination address pointers that can increment or remain constant — 24-bit transfer counter per channel — Operand packing and unpacking supported — Auto-alignment transfers supported for efﬁcient block movement — Bursting and cycle steal support — Two-bus-clock internal access — Automatic DMA transfers from on-chip UARTs using internal interrupts

• DRAM controller — Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast

page mode support — Up to 512 Mbytes of DRAM — Programmable timer provides CAS-before-RAS refresh for asynchronous

DRAMs — Support for two separate memory blocks

•Two UARTs — Full-duplex operation — Programmable clock — Modem control signals available (CTS

, RTS)

— Processor-interrupt capability

• Dual 16-bit general-purpose multiple-mode timers — 8-bit prescaler — Timer input and output pins — Processor-interrupt capability — Up to 22-nS resolution at 45 MHz

C module

•I — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and

keypads

— Fully compatible with industry-standard I

C bus — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level

• System interface module (SIM) — Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM,

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MCF5307 Features

FLASH, and memory-mapped I/O devices — Eight fully programmable chip selects, each with a base address register — Programmable wait states and port sizes per chip select — User-programmable processor clock/input clock frequency ratio — Programmable interrupt controller — Low interrupt latency — Four external interrupt request inputs — Programmable autovector generator — Software watchdog timer

• 16-bit general-purpose I/O interface

• IEEE 1149.1 test (JTAG) module

• System debug support — Real-time trace for determining dynamic execution path while in emulator mode — Background debug mode (BDM) for debug features while halted — Real-time debug support, including 6 user-visible hardware breakpoint re gisters

supporting a variety of breakpoint conﬁgurations

— Supports comprehensive emulator functions through trace and breakpoint logic

• On-chip PLL — Supports processor clock/bus clock ratios of 66/33, 66/22, 66/16.5, 90/45, 90/30,

and 90/22.5

— Supports low-power mode

• Product offerings — 75 Dhrystone 2.1 MIPS at 90 MHz — Implemented in 0.35 µ, triple-layer-metal process technology with 3.3-V

operation (5.0-V compliant I/O pads) — 208-pin plastic QFP package — 0°–70° C operating temperature

1.2.1 Process

The MCF5307 is manufactured in a 0.35-µ CMOS process with triple-layer-metal routing technology. This process combines the high performance and low power needed for embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0.5 V to GND - 0.5 V, with guaranteed TTL-level speciﬁcations.

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ColdFire Module Description

1.3 ColdFire Module Description

The following sections provide overviews of the various modules incorporated in the MCF5307.

1.3.1 ColdFire Core

The Version 4 ColdFire core consists of two independent and decoupled pipelines to maximize performance—the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP).

1.3.1.1 Instruction Fetch Pipeline (IFP)

The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the operand execution pipeline (OEP). Because the fetch and execution pipelines are decoupled by a eight-instruction FIFO buffer, the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the time stalled waiting for instructions. To maximize the performance of branch instructions, the Version 3 IFP implements a branch prediction mechanism. Backward branches are predicted to be taken. The prediction for forward branches is controlled by a bit in the Condition Code Register (CCR). These predictions allow the IFP to redirect the fetch stream do wn the path predicted to be taken well in advance of the actual instruction execution. The result is signiﬁcantly improved performance.

1.3.1.2 Operand Execution Pipeline (OEP)

The prefetched instruction stream is gated from the FIFO buffer into the two-stage OEP. The OEP consists of a traditional two-stage RISC compute engine with a register ﬁle access feeding an arithmetic/logic unit (ALU). The OEP decodes the instruction, fetches the required operands and then executes the required function.

1.3.1.3 MAC Module

The MAC unit provides signal processing capabilities for the MCF5307 in a variety of applications including digital audio and servo control. Integrated as an ex ecution unit in the processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers, plus signed, ﬁxed-point fractional input operands.

1.3.1.4 Integer Divide Module

Integrated into the OEP, the divide module performs operations using signed and unsigned integers. The module supports word and longword divides producing quotients and/or remainders.

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ColdFire Module Description

1.3.1.5 8-Kbyte Uniﬁed Cache

The MCF5307 architecture includes an 8-Kbyte uniﬁed cache. This four-way, set-associative cache provides pipelined, single-cycle access on cached instructions and operands.

As with all ColdFire caches, the cache controller implements a non-lockup, streaming design. The use of processor-local memories decouples performance from external memory speeds and increases available bandwidth for external devices or the on-chip 4-channel DMA.

The cache implements line-ﬁll buffers to optimize 16-byte line b urst accesses. Additionally , the cache supports copyback, write-through, or cache-inhibited modes. A 4-entry, 32-bit buffer is used for cache line push operations and can be conﬁgured for deferred write buffering in write-through or cache-inhibited modes.

1.3.1.6 Internal 4-Kbyte SRAM

The 4-Kbyte on-chip SRAM module provides pipelined, single-cycle access to memory regions mapped to these devices. The memory can be mapped to any 0-modulo-32K location in the 4-Gbyte address space. The SRAM module is useful for storing time-critical functions, the system stack, or heavily-referenced data operands.

1.3.2 DRAM Controller

The MCF5307 DRAM controller provides a direct interface for up to two blocks of DRAM. The controller supports 8-, 16-, or 32-bit memory widths and can easily interface to PC-100 DIMMs. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in normal mode or in page mode and supports SDRAMs and EDO DRAMs.

1.3.3 DMA Controller

The MCF5307 provides four fully programmable DMA channels for quick data transfer. Dual- and single-address modes support bursting and cycle steal. Data transfers are 32 bits long with packing and unpacking supported along with an auto-alignment option for efﬁcient block transfers. Automatic block transfers from on-chip serial UARTs are also supported through the DMA channels.

1.3.4 UART Modules

The MCF5307 contains two UARTs, which function independently. Either UART can be clocked by the system bus clock, eliminating the need for an external crystal. Each UART module interfaces directly to the CPU, as shown in Figure 1-2.

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System Integration

Module (SIM)

Interrupt

Controller

Figure 1-2. UART Module Block Diagram

Internal Channel

Control Logic

Interrupt Control

Logic

UART

Communications

Programmable

Generation

Serial

Channel

Clock

ColdFire Module Description

CTS RTS RxD TxD

BCLKO or External clock (TIN)

Each UART module consists of the following major functional areas:

• Serial communication channel

• 16-bit divider for clock generation

• Internal channel control logic

• Interrupt control logic

Each UART contains an programmable clock-rate generator. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. The UARTs include 4-byte and 2-byte FIFO buffers. The UART modules also provide several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send (RTS

) and clear-to-send (CTS) lines.

BCLKO provides the time base through a programmable prescaler. The UART time scale can also be sourced from a timer input. Full-duplex, auto-echo loopback, local loopback, and remote loopback modes allow testing of UART connections. The programmable UARTs can interrupt the CPU on various normal or error-condition events.

1.3.5 Timer Module

The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of three modes. One mode captures the timer value with an external event. Another mode triggers an e xternal signal or interrupts the CPU when the timer reaches a set value, while a third mode counts external events.

The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system bus cycle or an external clock input pin (TIN). The programmable timer-output pin generates either an active-low pulse or toggles the output.

1.3.6 I

The I between devices. The I

C Module

C interface is a two-wire, bidirectional serial bus used for quick data exchanges

C minimizes the interconnection between devices in the end system

and is best suited for applications that need occasional bursts of rapid communication over

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ColdFire Module Description

short distances among several devices. The I

C can operate in master, slave, or

multiple-master modes.

1.3.7 System Interface

The MCF5307 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM, ROM, and peripheral de vices through the use of fully programmable chip selects and write enables. Support for burst ROMs is also included. Through the on-chip PLL, users can input a slower clock (16.6 to 45 MHz) that is internally multiplied to create the faster processor clock (33.3 to 90 MHz).

1.3.7.1 External Bus Interface

The bus interface controller transfers information between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. The external bus interface provides up to 32 bits of address bus space, a 32-bit data bus, and all associated control signals. This interface implements an extended synchronous protocol that supports bursting operations.

Simple two-wire request/acknowledge bus arbitration between the MCF5307 processor and another bus master, such as an external DMA device, is glueless with arbitration logic internal to the MCF5307 processor. Multiple-master arbitration is also a v ailable with some simple external arbitration logic.

1.3.7.2 Chip Selects

Eight fully programmable chip select outputs support the use of external memory and peripheral circuits with user-deﬁned wait-state insertion. These signals interface to 8-, 16-, or 32-bit ports. The base address, access permissions, and internal bus transfer terminations are programmable with conﬁguration registers for each chip select. CS0 global chip select functionality of boot ROM upon reset for initializing the MCF5307.

1.3.7.3 16-Bit Parallel Port Interface

A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin basis.

also provides

1.3.7.4 Interrupt Controller

The interrupt controller provides user-programmable control of ten internal peripheral interrupts and implements four external ﬁxed interrupt-request pins. Each internal interrupt can be programmed to any one of seven interrupt le v els and four priority lev els within each of these levels. Additionally, the external interrupt request pins can be mapped to levels 1, 3, 5, and 7 or levels 2, 4, 6, and 7. Autovector capability is available for both internal and external interrupts.

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ColdFire Module Description

1.3.7.5 JTAG

To help with system diagnostics and manufacturing testing, the MCF5307 processor includes dedicated user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability , often referred to as the Joint Test Action Group, or JTAG. F or more information, refer to the IEEE 1149.1a standard.

1.3.8 System Debug Interface

The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug unit in the MCF5307 is a compatible upgrade to the MCF52xx debug module with added ﬂexibility in the breakpoint registers and a new command to view the program counter (PC).

The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the dedicated deb ug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be conﬁgured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level deﬁnitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.

The MCF5307’s new interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.

T o support program trace, the Version 3 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses deﬁning processor activity at the CPU’s clock rate.

1.3.9 PLL Module

The MCF5307 PLL module is shown in Figure 1-3.

Chapter 1. Overview

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Programming Model, Addressing Modes, and Instruction Set

CLKIN

FREQ[1:0]

DIVIDE[1:0]

RSTI

PLL

CLKIN X 4 by 2

Figure 1-3. PLL Module

Divide

Divide by 2,

3, or 4

RSTO PCLK PSTCLK BCLKO

The PLL module’s three modes of operation are described as follows.

• Reset mode—When RSTI asserts RST

O from the MCF5307. The core:bus frequency ratio and other MCF5307

is asserted, the PLL enters reset mode. At reset, the PLL

conﬁguration information are sampled during reset.

• Normal mode—In normal mode, the input frequency programmed at reset is clock-multiplied to provide the processor clock (PCLK).

• Reduced-power mode—In reduced-power mode, the PCLK is disabled by e xecuting a sequence that includes programming a control bit in the system conﬁguration register (SCR) and then executing the STOP instruction. Register contents are retained in reduced-power mode, so the system can be reenabled quickly when an unmasked interrupt or reset is detected.

1.4 Programming Model, Addressing Modes, and Instruction Set

The ColdFire programming model has two privilege le v els—supervisor and user. The S bit in the status register (SR) indicates the privilege level. The processor identiﬁes a logical address that differentiates between supervisor and user modes by accessing either the supervisor or user address space.

• User mode—When the processor is in user mode (SR[S] = 0), only a subset of registers can be accessed, and privileged instructions cannot be e xecuted. Typically , most application processing occurs in user mode. User mode is usually entered by executing a return from exception instruction (RTE, assuming the value of SR[S] saved on the stack is 0) or a MOVE, SR instruction (assuming SR[S] is 0).

• Supervisor mode—This mode protects system resources from uncontrolled access by users. In supervisor mode, complete access is provided to all registers and the entire ColdFire instruction set. Typically, system programmers use the supervisor programming model to implement operating system functions and provide I/O

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Programming Model, Addressing Modes, and Instruction Set

control. The supervisor programming model provides access to the same registers as the user model, plus additional registers for conﬁguring on-chip system resources, as described in Section 1.4.3, “Supervisor Registers.”

Exceptions (including interrupts) are handled in supervisor mode.

1.4.1 Programming Model

Figure 1-4 shows the MCF5307 programming model.

User Registers

Supervisor

Registers

31 0

31 19

Must be zeros VBR Vector base register

D0 Data registers D1 D2 D3 D4 D5 D6 D7

A0 Address registers A1 A2 A3 A4 A5 A6 A7 Stack pointer PC Program counter CCR Condition code register

MACSR MAC status register ACC MAC accumulator MASK MAC mask register

(CCR) SR Status register

CACR Cache control register ACR0 Access control register 0 ACR1 Access control register 1 RAMBAR RAM base address register MBAR Module base address register

Figure 1-4. ColdFire MCF5307 Programming Model

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Programming Model, Addressing Modes, and Instruction Set

1.4.2 User Registers

The user programming model is shown in Figure 1-4 and summarized in Table 1-1.

Table 1-1. User-Level Registers

Data registers (D0–D7)

Address registers (A0–A7)

Program counter (PC)

Condition code register (CCR)

MAC status register (MACSR)

Accumulator (ACC)

Mask register (MASK)

These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as index registers.

These 32-bit registers serve as software stack pointers, index registers, or base address registers. The base address registers can be used for word and longword operations. A7 functions as a hardware stack pointer during stacking for subroutine calls and e xception handling.

Contains the address of the instruction currently being executed by the MCF5307 processor

The CCR is the lower byte of the SR. It contains indicator ﬂags that reﬂect the result of a pre vious operation and are used for conditional instruction execution.

Deﬁnes the operating conﬁguration of the MAC unit and contains indicator ﬂags from the results of MAC instructions.

General-purpose register used to accumulate the results of MAC operations

General-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.

1.4.3 Supervisor Registers

Table 1-2 summarizes the MCF5307 supervisor-level registers.

Table 1-2. Supervisor-Level Registers

Status register (SR) The upper byte of the SR provides interrupt information in addition to a variety of mode indicators

Vector base register (VBR)

Cache conﬁguration register (CACR)

Access control registers (ACR0/1)

RAM base address register (RAMBAR)

Module base address register (MBAR)

signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as shown in Figure 1-4.

Deﬁnes the upper 12 bits of the base address of the exception vector table used during exception processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1 Mbyte address.

Deﬁnes the operating modes of the Version 4 cache memories. Control ﬁelds conﬁguring the instruction, data, and branch cache are provided by this register, along with the default attributes for the 4-Gbyte address space.

Deﬁne address ranges and attributes associated with various memory regions within the 4-Gbyte address space. Each ACR deﬁnes the location of a given memory region and assigns attributes such as write-protection and cache mode (copyback, write-through, cacheability). Additionally, CACR ﬁelds assign default attributes to the instruction and data memory spaces.

Provide the logical base address for the 4-Kbyte SRAM module and deﬁne attributes and access types allowed for the SRAM.

Deﬁnes the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals.

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Programming Model, Addressing Modes, and Instruction Set

1.4.4 Instruction Set

The ColdFire instruction set supports high-level languages and is optimized for those instructions most commonly generated by compilers in embedded applications. Table 2-8 provides an alphabetized listing of the ColdFire instruction set opcodes, supported operation sizes, and assembler syntax. For two-operand instructions, the ﬁrst operand is generally the source operand and the second is the destination.

Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports most of the common 68K opcodes. A majority of the instructions are binary compatible or optimized 68K opcodes. This feature, when coupled with the code conversion tools from third-party developers, generally minimizes software porting issues for customers with 68K applications.

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Programming Model, Addressing Modes, and Instruction Set

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Intended Audience

Part I

MCF5307 Processor Core

Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5307. It also describes the operation of the MCF5307

Contents

• Chapter 2, “ColdFire Core,” provides an ov erview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the V2 ColdFire core, and then fully describes the V3 programming model as it is implemented on the MCF5307. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings.

• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit, ” describes the MCF5307 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).

• Chapter 4, “Local Memory.” This chapter describes the MCF5307 implementation of the ColdFire V3 local memory speciﬁcation. It consists of the two following major sections.

— Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM

(SRAM) implementation. It covers general operations, conﬁguration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.

— Section 4.7, “Cache Overview,” describes the MCF5307 cache implementation,

including organization, conﬁguration, and coherency. It describes cache operations and how the cache interacts with other memory structures.

• Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug support in the MCF5307. This revision of the ColdFire debug architecture encompasses earlier revisions.

Part I. MCF5307 Processor Core I-xvii

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2.1 Features and Enhancements

The MCF5307 is the ﬁrst standard product to contain a Version 3 ColdFire microprocessor core. To reach higher levels of frequency and performance, numerous enhancements were made to the V2 architecture. Most notable are a deeper instruction pipeline, branch acceleration, and a uniﬁed cache, which together provide 75 (Dhrystone 2.1) MIPS at 90 MHz.

The MCF5307 core design emphasizes performance, and backward compatibility represents the next step on the ColdFire performance roadmap.

The following list summarizes MCF5307 features:

• Variable-length RISC, clock-multiplied Version 3 microprocessor core

• Two independent, decoupled pipelines—four-stage instruction fetch pipeline (IFP) and two-stage operand execution pipeline (OEP)

• Eight-instruction FIFO buffer provides decoupling between the pipelines

• Branch prediction mechanisms for accelerating program execution

• 32-bit internal address bus supporting 4 Gbytes of linear address space

• 32-bit data bus

• 16 user-accessible, 32-bit-wide, general-purpose registers

• Supervisor/user modes for system protection

• Vector base register to relocate exception-vector table

• Optimized for high-level language constructs

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Features and Enhancements

2.1.1 Clock-Multiplied Microprocessor Core

The MCF5307 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface.

The frequency of the processor complex can be 2x, 3x, or 4x the external bus speed. The processor, cache, integrated SRAM, and misalignment module operate at the higher

speed clock (PCLK); other system integrated modules operate at the speed of the bus clock (BCLKO). When combined with the enhanced pipeline structure of the Version 3 ColdFire core, the processor and its local memories provide a high level of performance for today’s demanding embedded applications.

PCLK can be disabled to minimize dissipation when a low-power mode is entered. This is described in Section 7.2.3, “Reduced-Power Mode.”

2.1.2 Enhanced Pipelines

The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes the speciﬁed function. The two independent, decoupled pipeline structures maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1 and are summarized as follows:

• Four-stage IFP (plus optional instruction buffer stage) — Instruction address generation (IAG) calculates the next prefetch address. — Instruction fetch cycle 1 (IC1) initiates prefetch on the processor’s local

instruction bus.

— Instruction fetch cycle 2 (IC2) completes prefetch on the processor’ s instruction

local bus.

— Instruction early decode (IED) generates time-critical decode signals needed for

the OEP.

— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of

fetch latency.

• Two-stage OEP — Decode, select/operand fetch (DSOC) decodes the instruction and selects the

required components for the effective address calculation, or the operand fetch cycle.

— Address generation/execute (AGEX) Calculates the oeprand address, or

performs the execution of the instruction.

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IAG

Instruction

Address

Generation

Features and Enhancements

Address [31:0]

Data[31:0]

Instruction Fetch Pipeline

Operand Execution Pipeline

IC1

IC2

IED

DSOC

AGEX

Instruction

Fetch Cycle 1

Instruction

Fetch Cycle 2

Instruction

Early Decode

FIFO

Instruction Buffer

Decode & Select,

Operand Fetch

Address

Generation,

Execute

Figure 2-1. ColdFire Enhanced Pipeline

2.1.2.1 Instruction Fetch Pipeline (IFP)

Because the fetch and execution pipelines are decoupled by an eight-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls.

2.1.2.1.1 Branch Acceleration

Because the IFP and the OEP are decoupled by the instruction buffer, the increased depth of the IFP is generally hidden from the OEP’s instruction execution. The one exception is change-of-ﬂow instructions such as unconditional branches or jumps, subroutine calls, and taken conditional branches. To minimize the effects of the increased depth of the IFP, the prefetched instruction stream is monitored for change-of-ﬂow opcodes. When certain types of change-of-ﬂow instructions are detected, the target instruction address is calculated, and fetching immediately begins in the target stream.

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Features and Enhancements

For example, if an unconditional BRA instruction is detected, the IED calculates the target of the BRA instruction, and the IAG immediately begins fetching at the target address. Because of the decoupled nature of the two pipelines, the target instruction is available to the OEP immediately after the BRA instruction, giving it a single-cycle execution time.

The acceleration logic uses a static prediction algorithm when processing conditional branch (Bcc) instructions. The default scheme is forward Bcc instructions are predicted as not-taken, while backward Bcc instructions are predicted as taken. A user-mode control bit, CCR[7], allows users to dynamically alter the prediction algorithm for forward Bcc instructions. See Section 2.2.1.5, “Condition Code Register (CCR).

2.1.2.2 Operand Execution Pipeline (OEP)

The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register ﬁle feeding an arithmetic/logic unit. For simple register-to-register instructions, the ﬁrst stage of the OEP performs the instruction decode and fetching of the required register operands (OC), while the actual instruction execution is performed in the second stage (EX).

For memory-to-register instructions, the instruction is effectively staged through the OEP twice in the following way:

• The instruction is decoded and the components of the operand address are selected (DS).

• The operand address is generated using the “execute engine” (AG).

• The memory operand is fetched while any register operand is simultaneously fetched (OC).

• The instruction is executed (EX).

For register-to-memory operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. For read-modify-write instructions, the pipeline effectiv ely combines a memory-to-register operation with a store operation.

2.1.2.2.1 Illegal Opcode Handling

To aid in conversion from M68000 code, every 16-bit operation word is decoded to ensure that each instruction is valid. If the processor attempts execution of an illegal or unsupported instruction, an illegal instruction exception (vector 4) is taken.

2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit

The MAC is an optional unit in Version 3 that provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family. The MAC features a three-stage execution pipeline, optimized for 16 x 16 multiplies. It is tightly coupled to the OEP, which can issue a 16 x 16 multiply with a 32-bit accumulation plus fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued.

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Features and Enhancements

Figure 2-2 shows basic functionality of the MAC. A full set of instructions are pro vided for signed and unsigned integers plus signed, ﬁxed-point fractional input operands.

Operand Y Oper and X

Shift 0,1,-1

+/-

Accumulator

Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram

The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit.”

• Signed and unsigned integer multiplies

• Multiply-accumulate operations with signed and unsigned fractional operands

• Miscellaneous register operations

2.1.2.2.3 Hardware Divide Unit

The hardware divide unit performs the following integer division operations:

• 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder

• 32-bit operand/32-bit operand producing a 32-bit quotient

• 32-bit operand/32-bit operand producing a 32-bit remainder

2.1.3 Debug Module Enhancements

The ColdFire processor core debug interface supports system integration in conjunction with low-cost development tools. Real-time trace and debug information can be accessed through a standard interface, which allows the processor and system to be debugged at full speed without costly in-circuit emulators. The MCF5307 debug unit is a compatible upgrade to the MCF52xx debug module with enhancements that include:

• A new command to obtain the value of the program counter (PC)

• Allowing ORing of terms in creating breakpoints

• Increased ﬂexibility of the breakpoint registers

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Programming Model

On-chip breakpoint resources include the following:

• Conﬁguration/status register (CSR)

• Background debug mode (BDM) address attributes register (BAAR)

• Bus attributes and mask register (AATR)

• Breakpoint registers. These can be used to deﬁne triggers combining address, data, and PC conditions in single- or dual-level deﬁnitions. They include the following:

— PC breakpoint register (PBR) — PC breakpoint mask register (PBMR) — Data operand address breakpoint registers (ABHR/ABLR) — Data breakpoint register (DBR)

• Data breakpoint mask register (DBMR)

• Trigger deﬁnition register (TDR) can be programmed to generate a processor halt or initiate a debug interrupt exception.

These registers can be accessed through the dedicated debug serial communication channel, or from the processor’s supervisor programming model, using the WDEBUG instruction.

The enhancements of the Revision B debug speciﬁcation are fully backward-compatible with the A revision. For more information, see Chapter 5, “Debug Support.”

2.2 Programming Model

The MCF5307 programming model consists of three instruction and register groups—user, MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are restricted to user and MAC instructions and programming models. Supervisor-mode system software can reference all user-mode and MAC instructions and registers and additional supervisor instructions and control registers. The user or supervisor programming model is selected based on SR[S]. The following sections describe the registers in the user, MAC, and supervisor programming models.

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Programming Model

User Registers

Supervisor

Registers

31 0

31 19

Must be zeros VBR Vector base register

D0 Data registers D1 D2 D3 D4 D5 D6 D7

A0 Address registers A1 A2 A3 A4 A5 A6 A7 Stack pointer PC Program counter CCR Condition code register

MACSR MAC status register ACC MAC accumulator MASK MAC mask register

(CCR) SR Status register

CACR Cache control register ACR0 Access control register 0 ACR1 Access control register 1 RAMBAR RAM base address register MBAR Module base address register

Figure 2-3. ColdFire Programming Model

2.2.1 User Programming Model

As Figure 2-3 shows, the user programming model consists of the following registers:

• 16 general-purpose 32-bit registers, D0–D7 and A0–A7

• 32-bit program counter

• 8-bit condition code register

2.2.1.1 Data Registers (D0–D7)

Registers D0–D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit) operations. They may also be used as index registers.

2.2.1.2 Address Registers (A0–A6)

The address registers (A0–A6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations.

Chapter 2. ColdFire Core 2-27

Programming Model

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2.2.1.3 Stack Pointer (A7, SP)

The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. The initial value of A7 is loaded from the reset exception vector, address 0x0000. The same register is used for user and supervisor modes, and may be used for word and longword operations.

A subroutine call saves the program counter (PC) on the stack and the return restores the PC from the stack. The PC and the status register (SR) are saved on the stack during exception and interrupt processing. The return from exception instruction restores SR and PC values from the stack.

2.2.1.4 Program Counter (PC)

The PC holds the address of the executing instruction. For sequential instructions, the processor automatically increments PC. When program ﬂow changes, the PC is updated with the target instruction. For some instructions, the PC speciﬁes the base address for PC-relative operand addressing modes.

2.2.1.5 Condition Code Register (CCR)

The CCR, Figure 2-4, occupies SR[7–0], as shown in Figure 2-3. CCR[4–0] are indicator ﬂags based on results generated by arithmetic operations.

Table 2-1 describes the CCR ﬁeldsMAC Programming ModelFigure 2-3 shows the registers in the MAC portion of the user programming model. These registers are described as follows:Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.

76543210

Field P — X N Z V C

Reset 0 00 Undeﬁned

R/W R/W R R/W R/W R/W R/W R/W

Table 2-1. CCR Field Descriptions

Bits Name Description

7 P Branch prediction bit. Alters the static prediction algorithm used by the branch acceleration logic in the

6–5 — Reserved, should be cleared.

4 X Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not

3 N Negative condition code bit. Set if the msb of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared.

IFP on forward conditional branches. 0 Predicted as not-taken. 1 Predicted as taken.

affected or set to a speciﬁed result. Also used as an input operand for multiple-precision arithmetic.

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Table 2-1. CCR Field Descriptions (Continued)

Bits Name Description

1 V Overﬂow condition code bit. Set if an arithmetic overﬂow occurs, implying that the result cannot be

0 C Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a

represented in the operand size; otherwise cleared.

borrow occurs in a subtraction; otherwise cleared.

Programming Model

• Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.

• MAC status register (MACSR)—This 8-bit register deﬁnes conﬁguration of the MAC unit and contains indicator ﬂags af fected by MAC instructions. Unless noted otherwise, MACSR indicator ﬂag settings are based on the ﬁnal result, that is, the result of the ﬁnal operation involving the product and accumulator.

2.2.2 Supervisor Programming Model

The MCF5307 supervisor programming model is shown in Figure 2-3. Typically, system programmers use the supervisor programming model to implement operating system functions and provide memory and I/O control. The supervisor programming model provides access to the user registers and additional supervisor registers, which include the upper byte of the status register (SR), the vector base register (VBR), and registers for conﬁguring attributes of the address space connected to the Version 3 processor core. Most supervisor-mode registers are accessed by using the MOVEC instruction with the control register deﬁnitions in Table 2-2.

Table 2-2. MOVEC Register Map

Rc[11–0] Register Deﬁnition

0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x801 Vector base register (VBR) 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR)

2.2.2.1 Status Register (SR)

The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software can read or write the entire SR; user software can read or write only SR[7–0], described in Section 2.2.1.5, “Condition Code Register (CCR).” The control bits indicate processor states—trace mode (T), supervisor or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.

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Programming Model

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field T — S M — I P — X N Z V C

Reset 00100 111 0 00 —————

R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W R/W R/W

System byte Condition code register (CCR)

Figure 2-5. Status Register (SR)

Table 2-3 describes SR ﬁelds.

Table 2-3. Status Field Descriptions

Bits Name Description

15 T Trace enable. When T is set, the processor performs a trace exception after every instruction. 13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode

12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution

10–8 I Interrupt priority mask. Deﬁnes the current interrupt priority. Interrupt requests are inhibited for all

7–0 CCR Condition code register. See Table 2-1.

0 User mode 1 Supervisor mode

of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.

priority levels less than or equal to the current priority, except the edge-sensitive level-7 request, which cannot be masked.

2.2.2.2 Vector Base Register (VBR)

The VBR holds the base address of the exception vector table in memory . The displacement of an exception vector is added to the value in this register to access the vector table. VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte boundary.

313029282726252423222120191817161514131211109876543210

Field Exception vector table base address —

Reset 0000_0000_0000_0000_0000_0000_0000_0000

R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from

Rc[11–0] 0x801

the debug module only. The upper 12 bits are returned, the low-order 20 bits are undeﬁned.

Figure 2-6. Vector Base Register (VBR)

2.2.2.3 Cache Control Register (CACR)

The CACR controls operation of both the instruction and data cache memory. It includes bits for enabling, freezing, and inv alidating cache contents. It also includes bits for deﬁning the default cache mode and write-protect ﬁelds. See Section 4.10.1, “Cache Control Register (CACR).”

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Integer Data Formats

2.2.2.4 Access Control Registers (ACR0–ACR1)

The access control registers (ACR0–ACR1) deﬁne attributes for two user-deﬁned memory regions. Attributes include deﬁnition of cache mode, write protect and buf fer write enables. See Section 4.10.2, “Access Control Registers (ACR0–ACR1).”

2.2.2.5 RAM Base Address Register (RAMBAR)

The RAMBAR register determines the base address location of the internal SRAM module and indicates the types of references mapped to it. The RAMBAR includes a base address, write-protect bit, address space mask bits, and an enable. The RAM base address must be aligned on a 0-modulo-32-Kbyte boundary. See Section 4.4.1, “SRAM Base Address Register (RAMBAR).”

2.2.2.6 Module Base Address Register (MBAR)

The module base address register (MBAR) deﬁnes the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. See Section 6.2.2, “Module Base Address Register (MBAR).”

2.3 Integer Data Formats

Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly deﬁned by the instruction operation.

Table 2-4. Integer Data Formats

Operand Data Format Size

Bit 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits

2.4 Organization of Data in Registers

The following sections describe data organization within the data, address, and control registers.

2.4.1 Organization of Integer Data Formats in Registers

Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. Longword operands occupy the entire 32 bits of integer data registers. A data re gister that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining

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Organization of Data in Registers

high-order portion does not change. The least signiﬁcant bit (lsb) of all integer sizes is zero, the most-signiﬁcant bit (msb) of a longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7.

31 30 1 0

msb lsb Bit (0 ≤ bit number ≤ 31)

31 7 0

Not used msb Low order byte lsb Byte (8 bits)

31 15 0

Not used msb Lower order word lsb Word (16 bits)

31 0

msb Longword lsb Longword (32 bits)

Figure 2-7. Organization of Integer Data Formats in Data Registers

The instruction set encodings do not allow the use of address registers for byte-sized operands. When an address register is a source operand, either the low-order word or the entire longword operand is used, depending on the operation size. Word-length source operands are sign-extended to 32 bits and then used in the operation with anaddress register destination. When an address register is a destination, the entire register is affected, regardless of the operation size. Figure 2-8 shows integer formats for address registers.

31 16 15 0

Sign-Extended 16-Bit Address Operand

31 0

Full 32-Bit Address Operand

Figure 2-8. Organization of Integer Data Formats in Address Registers

The size of control registers varies according to function. Some have undeﬁned bits reserved for future deﬁnition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility.

All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode.

2.4.2 Organization of Integer Data Formats in Memory

All ColdFire processors use a big-endian addressing scheme. The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a longword data item corresponds to the address of the high-order word. The lower order word is located at address N + 2. The address N of a word data item corresponds to the address of the high-order byte. The lower order byte is located at address N + 1. This

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Addressing Mode Summary

organization is shown in Figure 2-9.

31 23 15 7 0

Longword 0x0000_0000

Word 0x0000_0000 Word 0x0000_0002

Byte 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003

Longword 0x0000_0004

Word 0x0000_0004 Word 0x0000_0006

Byte 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007

. . .

Longword 0xFFFF_FFFC

Word 0xFFFF_FFFC Word 0xFFFF_FFFE

Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF

Figure 2-9. Memory Operand Addressing

2.5 Addressing Mode Summary

Addressing modes are categorized by how they are used. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable (writable) data operands. Control addressing modes refer to memory operands without an associated size.

These categories sometimes combine to form more restrictive categories. Two combined classiﬁcations are alterable memory (both alterable and memory) and data alterable (both alterable and data). Twelve of the most commonly used effective addressing modes from the M68000 Family are available on ColdFire microprocessors. Table 2-5 summarizes these modes and their categories;

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Instruction Set Summary

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Table 2-5. ColdFire Effective Addressing Modes

— —

X X X X

X X

2.6 Instruction Set Summary

The ColdFire instruction set is a simpliﬁed version of the M68000 instruction set. The removed instructions include BCD, bit ﬁeld, logical rotate, decrement and branch, and integer multiply with a 64-bit result. Nine new MAC instructions have been added.

Table 2-6 lists notational conventions used throughout this manual.

Table 2-6. Notational Conventions

Instruction Operand Syntax

Opcode Wildcard

cc Logical condition (example: NE for not equal)

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Instruction Set Summary

Table 2-6. Notational Conventions (Continued)

Instruction Operand Syntax

An Any address register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any data register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Rc Any control register (example VBR is the vector base register)

Rm MAC registers (ACC, MAC, MASK)

Rn Any address or data register Rw Destination register w (used for MAC instructions only)

Ry,Rx Any source and destination registers, respectively

Xi index register i (can be an address or data register: Ai, Di)

ACC MAC accumulator register

CCR Condition code register (lower byte of SR)

MACSR MAC status register

MASK MAC mask register

PC Program counter SR Status register

Port Name

DDATA Debug data port

PST Processor status port

Miscellaneous Operands

#<data> Immediate data following the 16-bit operation word of the instruction

Í Effective address

<ea>y,<ea>x Source and destination effective addresses, respectively

<label> Assembly language program label

<list> List of registers for MOVEM instruction (example: D3–D0) <shift> Shift operation: shift left (<<), shift right (>>) <size> Operand data size: byte (B), word (W), longword (L)

uc Uniﬁed cache

# <vector> Identiﬁes the 4-bit vector number for trap instructions

identiﬁes an indirect data address referencing memory

<xxx> identiﬁes an absolute address referencing memory

dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)

SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)

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Instruction Set Summary

Table 2-6. Notational Conventions (Continued)

Instruction Operand Syntax

Operations

+ Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator

x Arithmetic multiplication

/ Arithmetic division ~ Invert; operand is logically complemented & Logical AND

| Logical OR

^ Logical exclusive OR

<< Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→ Source operand is moved to destination operand

←→ Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

If <condition>

then

else

{} Optional operation () Identiﬁes an indirect address

Address Calculated effective address (pointer)

Bit Bit selection (example: Bit 3 of D0)

lsb Least signiﬁcant bit (example: lsb of D0)

LSB Least signiﬁcant byte

LSW Least signiﬁcant word

msb Most signiﬁcant bit MSB Most signiﬁcant byte MSW Most signiﬁcant word

Test the condition. If the condition is true, the operations in the then clause are performed. If the condition is false and the optional else clause is present, the operations in the else claue are performed. If the condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.

Subﬁelds and Qualiﬁers

Displacement value, n-bits wide (example: d16 is a 16-bit displacement)

Condition Code Register Bit Names

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Table 2-6. Notational Conventions (Continued)

Instruction Operand Syntax

P Branch prediction C Carry N Negative V Overﬂow X Extend Z Zero

2.6.1 Instruction Set Summary

Table 2-7 lists implemented user-mode instructions by opcode.

Instruction Set Summary

Table 2-7. User-Mode Instruction Set Summary

Instruction Operand Syntax Operand Size Operation

ADD Dy,<ea>x

<ea>y,Dx ADDA <ea>y,Ax .L Source + destination → destination ADDI #<data>,Dx .L Immediate data + destination → destination ADDQ #<data>,<ea>x .L Immediate data + destination → destination ADDX Dy,Dx .L Source + destination + X → destination AND Dy,<ea>x

<ea>y,Dx ANDI #<data>,Dx .L Immediate data & destination → destination ASL Dy,Dx

#<data>,Dx ASR Dy,Dx

#<data>,Dx Bcc <label> .B,.W If condition true, then PC + 2 + dn → PC BCHG Dy,<ea>x

#<data>,<ea-1>x BCLR Dy,<ea>x

#<data>,<ea-1>x BRA <label> .B,.W PC + 2 + d BSET Dy,<ea>x

#<data>,<ea-1>x BSR <label> .B,.W SP – 4 → SP; next sequential PC→ (SP); PC + 2 + dn → PC BTST Dy,<ea>x

#<data>,<ea-1>x CLR <ea>y,Dx .B,.W,.L 0 → destination CMP <ea>y,Ax .L Destination – source CMPA <ea>y,Dx .L Destination – source

.L .L

.B,.L .B,.L

Source + destination → destination

Source & destination → destination

X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #<data>) ← 0

MSB → (Dx >> Dy) → X/C MSB → (Dx >> #<data>) → X/C

~(<bit number> of destination) → Z, Bit of destination

~(<bit number> of destination) → Z; 0 → bit of destination

→ PC

~(<bit number> of destination) → Z; 1→ bit of destination

~(<bit number> of destination) → Z

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Instruction Set Summary

Table 2-7. User-Mode Instruction Set Summary (Continued)

Instruction Operand Syntax Operand Size Operation

CMPI <ea>y,Dx .L Destination – immediate data DIVS <ea-1>y,Dx

DIVU <ea-1>y,Dx

EOR Dy,<ea>x .L Source ^ destination → destination EORI #<data>,Dx .L Immediate data ^ destination → destination EXT #<data>,Dx .B →.W

EXTB Dx .B →.L Sign-extended destination → destination HALT JMP <ea-3>y Unsized Address of <ea> → PC JSR <ea-3>y Unsized SP – 4 → SP; next sequential PC → (SP); <ea> → PC LEA <ea-3>y,Ax .L <ea> → Ax LINK Ax,#<d16> .W SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP LSL Dy,Dx

LSR Dy,Dx

MAC Ry,RxSF .L + (.W × .W) → .L

MACL Ry,RxSF,<ea-1>y,Rw .L + (.W × .W) → .L, .L

MOVE <ea>y,<ea>x .B,.W,.L <ea>y → <ea>x MOVE from

MAC

MOVE to MAC

MOVE from CCR

MOVE to CCR

MOVEA <ea>y,Ax .W,.L → .L Source → destination

<ea>y,Dx

Dy,<ea>x

None Unsized Enter halted state

#<data>,Dx

MASK,Rx

ACC,Rx

MACSR,Rx

MACSR,CCR .L MACSR → CCR

Ry,ACC

Ry,MACSR

Ry,MASK

#<data>,ACC

#<data>,MACSR

#<data>,MASK

CCR,Dx .W CCR → Dx

Dy,CCR

#<data>,CCR

.W .L

.W →.L

.L .L

.L + (.L × .L) → .L

.L + (.L × .L) → .L, .L

.L Rm → Rx

.L Ry → Rm

.L #<data> → Rm

.B Dy → CCR

Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient} Dx /<ea>y → Dx {32-bit quotient} Signed operation

Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient} Dx /<ea>y → Dx {32-bit quotient} Unsigned operation

Sign-extended destination → destination

X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #<data>) ← 0

0 → (Dx >> Dy) → X/C 0 → (Dx >> #<data>) → X/C

ACC + (Ry × Rx){<< 1 | >> 1} → ACC ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea>y{&MASK}) → Rw

ACC + (Ry × Rx){<< 1 | >> 1} → ACC ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) → Rw

#<data> → CCR

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Instruction Set Summary

Table 2-7. User-Mode Instruction Set Summary (Continued)

Instruction Operand Syntax Operand Size Operation

MOVEM #<list>,<ea-2>x

<ea-2>y,#<list> MOVEQ #<data>,Dx .B → .L Sign-extended immediate data → destination MSAC Ry,RxSF .L - (.W × .W) → .L

MSACL Ry,RxSF,<ea-1>y,Rw .L - (.W × .W) → .L, .L

MULS <ea>y,Dx .W X .W → .L

MULU <ea>y,Dx .W X .W → .L

NEG Dx .L 0 – destination → destination NEGX Dx .L 0 – destination – X → destination NOP none Unsized Synchronize pipelines; PC + 2 → PC NOT Dx .L ~ Destination → destination OR <ea>y,Dx

Dy,<ea>x ORI #<data>,Dx .L Immediate data | destination → destination PEA <ea-3>y .L SP – 4 → SP; Address of <ea> → (SP) PULSE none Unsized Set PST= 0x4 REMS <ea-1>,Dx .L Dx/<ea>y → Dw {32-bit remainder}

REMU <ea-1>,Dx .L Dx/<ea>y → Dw {32-bit remainder}

RTS none Unsized (SP) → PC; SP + 4 → SP Scc Dx .B If condition true, then 1s  destination;

SUB <ea>y,Dx

Dy,<ea>x SUBA <ea>y,Ax .L Destination – source → destination SUBI #<data>,Dx .L Destination – immediate data → destination SUBQ #<data>,<ea>x .L Destination – immediate data → destination SUBX Dy,Dx .L Destination – source – X → destination SWAP Dx .W MSW of Dx ←→ LSW of Dx TRAP #<vector> Unsized SP – 4 → SP;PC → (SP);

TRAPF None

#<data>

.L .L

.L - (.L × .L) → .L

.L - (.L × .L) → .L, .L

.L X .L → .L

.L Source | destination → destination

.L .L

Unsized .W .L

Listed registers → destination Source → listed registers

ACC – (Ry × Rx){<< 1 | >> 1} → ACC

ACC – (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) → Rw

Source × destination → destination Signed operation

Source × destination → destination Unsigned operation

Signed operation

Unsigned operation

Else 0s → destination Destination – source → destination

SP – 2 → SP;SR → (SP); SP – 2 → SP; format → (SP); Vector address → PC

PC + 2 → PC PC + 4 → PC PC + 6 → PC

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Instruction Timing

Table 2-7. User-Mode Instruction Set Summary (Continued)

Instruction Operand Syntax Operand Size Operation

TST <ea>y .B,.W,.L Set condition codes UNLK Ax Unsized Ax →SP; (SP) → Ax; SP + 4 → SP WDDATA <ea>y .B,.W,.L <ea>y →DDATA port

By default the HALT instruction is a supervisor-mode instruction; however, it can be conﬁgured to allow user-mode

execution by setting CSR[UHE].

Table 2-8 describes supervisor-mode instructions.

Table 2-8. Supervisor-Mode Instruction Set Summary

Instruction Operand Syntax Operand Size Operation

CPUSHL (An) Unsized Invalidate instruction cache line

Push and invalidate data cache line Push data cache line and invalidate (I,D)-cache lines

HALT MOVE from SR SR, Dx .W SR → Dx MOVE to SR Dy,SR

MOVEC Ry,Rc .L Ry → Rc

RTE None Unsized (SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatﬁeld  SP STOP #<data> .W Immediate data → SR; enter stopped state WDEBUG <ea-2>y .L <ea-2>y → debug module

The HALT instruction can be conﬁgured to allow user-mode execution by setting CSR[UHE].

none Unsized Enter halted state

.W Source → SR

#<data>,SR

Rc Register Deﬁnition

0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x006 Access control register 2 (ACR2) 0x007 Access control register 3 (ACR3) 0x801 Vector base register (VBR) 0xC04 RAM base address register 0 (RAMBAR0) 0xC05 RAM base address register 1 (RAMBAR1)

2.7 Instruction Timing

The timing data presented in this section assumes the following:

• The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP spends no time waiting for the IFP to supply opwords and/or extension words.

• The OEP experiences no sequence-related pipeline stalls. For the MCF5307, the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all store operations (except MOVEM),

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Instruction Timing

certain hardware resources within the processor are marked as “busy” for two clock cycles after the ﬁnal DSOC cycle of the store instruction. If a subsequent store instruction is encountered within this two-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive store operations is two cycles.

• The OEP can complete all memory accesses without memory causing any stall conditions. Thus, timing details in this section assume an inﬁnite zero-wait state memory attached to the core.

• All operand data accesses are assumed to be aligned on the same byte boundary as the operand size:

— 16-bit operands aligned on 0-modulo-2 addresses — 32-bit operands aligned on 0-modulo-4 addresses Operands that do not meet these guidelines are misaligned. T able 2-9 shows how the

core decomposes a misaligned operand reference into a series of aligned accesses.

Table 2-9. Misaligned Operand References

A[1:0] Size Bus Operations Additional C(R/W)

x1 Word Byte, Byte 2(1/0) if read

x1 Long Byte, Word, Byte 3(2/0) if read

10 Long Word, Word 2(1/0) if read

Each timing entry is presented as C(r/w), described as follows: C is the number of processor clock cycles, including all applicable operand f etches and writes, as

well as all internal core cycles required to complete the instruction execution. r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation

performing a read-modify write function is denoted as (1/1).

1(0/1) if write

2(0/2) if write

1(0/1) if write

2.7.1 MOVE Instruction Execution Times

The execution times for the MOVE.{B,W,L} instructions are shown in the next tables. Table 2-12 shows the timing for the other generic move operations.

NOTE:

For all tables in this chapter, the execution time of any instruction using the PC-relative effective addressing modes is equivalent to the time using comparable An-relative mode.

ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)} ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}

The nomenclature “(xxx).wl” refers to both forms of absolute addressing, (xxx).w and (xxx).l.

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Instruction Timing

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Table 2-10 lists execution times for MOVE.{B,W} instructions.

Table 2-10. Move Byte and Word Execution Times

Source

Destination

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1)

(Ay)+ 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1)

-(Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1)

(d16,Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — —

(d8,Ay,Xi*SF) 5(1/0) 5(1/1) 5(1/1) 5(1/1) — — —

(xxx).w 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

(xxx).l 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

(d16,PC) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — —

(d8,PC,Xi*SF) 5(1/0) 5(1/1) 5(1/1) 5(1/1) — — —

#<xxx> 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

Table 2-11 lists timings for MOVE.L.

Table 2-11. Move Long Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

(Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

-(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

(xxx).w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(xxx).l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

#<xxx> 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

Table 2-12 gives execution times for MOVE.L instructions accessing program-visible registers of the MAC unit, along with other MOVE.L timings. Execution times for moving contents of the ACC or MACSR into a destination location represent the best-case scenario when the store instruction is executed and there are no load or MAC or MSAC instruction

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in the MAC execution pipeline.

Table 2-12. MAC Move Execution Times

Instruction Timing

Opcode Í

Effective Address

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

move.l <ea>,ACC 1(0/0) — — — — — — 1(0/0) move.l <ea>,MACSR 2(0/0) — — — — — — 2(0/0) move.l <ea>,MASK 1(0/0) — — — — — — 1(0/0) move.l ACC,Rx 3(0/0) — — — — — — — move.l MACSR,CCR 3(0/0) — — — — — — — move.l MACSR,Rx 3(0/0) — — — — — — — move.l MASK,Rx 3(0/0) — — — — — — —

2.7.2 Execution Timings—One-Operand Instructions

Table 2-13 shows standard timings for single-operand instructions.

Table 2-13. One-Operand Instruction Execution Times

Effective Address

Opcode Í

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #xxx

clr.b Í 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

clr.w Í 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

clr.l Í 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

ext.w Dx 1(0/0) — — — — — — —

ext.l Dx 1(0/0) — — — — — — — extb.l Dx 1(0/0) — — — — — — — neg.l Dx 1(0/0) — — — — — — —

negx.l Dx 1(0/0) — — — — — — —

not.l Dx 1(0/0) — — — — — — —

scc Dx 1(0/0) — — — — — — —

swap Dx 1(0/0) — — — — — — —

tst.b Í 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) tst.w Í 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0)

tst.l Í 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

2.7.3 Execution Timings—Two-Operand Instructions

Table 2-14 shows standard timings for two-operand instructions.

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Table 2-14. Two-Operand Instruction Execution Times

Opcode Í

Effective Address

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

add.l <ea>,Rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) add.l Dy,<ea> — 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

addi.l #imm,Dx 1(0/0) — — — — — — —

addq.l #imm,<ea> 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — addx.l Dy,Dx 1(0/0) — — — — — — —

and.l <ea>,Rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) and.l Dy,<ea> — 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

andi.l #imm,Dx 1(0/0) — — — — — — —

asl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

asr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

bchg Dy,<ea> 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) 6(1/1) 5(1/1) — bchg #imm,<ea> 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) — — —

bclr Dy,<ea> 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) 6(1/1) 5(1/1) —

bclr #imm,<ea> 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) — — — bset Dy,<ea> 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) 6(1/1) 5(1/1) — bset #imm,<ea> 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) — — —

btst Dy,<ea> 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) —

btst #imm,<ea> 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) — — —

cmp.l <ea>,Rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) cmpi.l #imm,Dx 1(0/0) — — — — — — — divs.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

divu.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

divs.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — —

divu.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — —

eor.l Dy,<ea> 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

eori.l #imm,Dx 1(0/0) — — — — — — —

lea <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) — lsl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0) lsr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

mac.w Ry,Rx 1(0/0) — — — — — — —

mac.l Ry,Rx 3(0/0) — — — — — — —

msac.w Ry,Rx 1(0/0) — — — — — — —

msac.l Ry,Rx 3(0/0) — — — — — — — mac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

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Instruction Timing

Table 2-14. Two-Operand Instruction Execution Times (Continued)

Opcode Í

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

mac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — —

moveq #imm,Dx — — — — — — — 1(0/0)

msac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

msac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — — muls.w <ea>,Dx 3(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 3(0/0) mulu.w <ea>,Dx 3(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 3(0/0)

muls.l <ea>,Dx 5(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) — — — mulu.l <ea>,Dx 5(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) — — —

or.l <ea>,Rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0)

or.l Dy,<ea> — 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

or.l #imm,Dx 1(0/0) — — — — — — —

rems.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — — remu.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — —

sub.l <ea>,Rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) sub.l Dy,<ea> — 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

subi.l #imm,Dx 1(0/0) — — — — — — — subq.l #imm,<ea> 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — subx.l Dy,Dx 1(0/0) — — — — — — —

Effective Address

2.7.4 Miscellaneous Instruction Execution Times

Table 2-15 lists timings for miscellaneous instructions.

Table 2-15. Miscellaneous Instruction Execution Times

Opcode Í

cpushl (Ax) — 11(0/1) — — — — — —

link.w Ay,#imm 2(0/1) — — — — — — — move.w CCR,Dx 1(0/0) — — — — — — — move.w <ea>,CCR 1(0/0) — — — — — — 1(0/0) move.w SR,Dx 1(0/0) — — — — — — — move.w <ea>,SR 9(0/0) — — — — — — 9(0/0)

movec Ry,Rc 11(0/1) — — — — — — —

movem.l

movem.l &list,<ea> — 2+n(0/n) — — 2+n(0/n) — — —

<ea>,&list — 2+n(n/0) — — 2+n(n/0) — — —

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

Effective Address

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Table 2-15. Miscellaneous Instruction Execution Times (Continued)

Opcode Í

nop 3(0/0) — — — — — — — pea Í — 2(0/1) — — 2(0/1)

pulse 1(0/0) — — — — — — —

stop #imm — — — — — — — 3(0/0) trap #imm — — — — — — — 18(1/2)

trapf 1(0/0) — — — — — — —

trapf.w 1(0/0) — — — — — — —

trapf.l 1(0/0) — — — — — — —

unlk Ax 3(1/0) — — — — — — — wddata.l Í — 7(1/0) 7(1/0) 7(1/0) 7(1/0) 8(1/0) 7(1/0) — wdebug.l Í — 10(2/0) — — 10(2/0) — — —

If a MOVE.W #imm,SR instruction is executed and #imm[13] = 1, the execution time is 1(0/0).

n is the number of registers moved by the MOVEM opcode.

PEA execution times are the same for (d16,PC).

PEA execution times are the same for (d8,PC,Xi*SF).

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

Effective Address

3(0/1)

2(0/1) —

2.7.5 Branch Instruction Execution Times

Table 2-16 shows general branch instruction timing.

Table 2-16. General Branch Instruction Execution Times

Opcode Í

bra ————1(0/1) bsr — — — — 1(0/1)

jmp Í — 5(0/0) — — 5(0/0)

jsr Í — 5(0/1) — — 5(0/1) 6(0/1) 1(0/1)

rte — — 14(2/0) — — — — —

rts — — 8(1/0) — — — — —

Assumes branch acceleration. Depending on the pipeline status, execution times may vary from 1 to 3 cycles.

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

Effective Address

1 1 1

——— ———

6(0/0) 1(0/0)

1 1

— —

For the conditional branch opcodes (bcc), a static algorithm is used to determine the prediction state of the branch. This algorithm is:

if bcc is a forward branch && CCR[7] == 0

2-46 MCF5307 User’s Manual

then the bcc is predicted as not-taken

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Exception Processing Overview

if bcc is a forward branch && CCR[7] == 1

then the bcc is predicted as taken else if bcc is a backward branch

then the bcc is predicted as taken

Table 2-17 shows timing for Bcc instructions.

Table 2-17. Bcc Instruction Execution Times

Opcode

bcc 1(0/0) 1(0/0) 5(0/0)

Predicted

Correctly as Taken

Predicted

Correctly as Not

Taken

Predicted

Incorrectly

2.8 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 Family processors include the following:

• A simpliﬁed exception vector table

• Reduced relocation capabilities using the vector base register

• A single exception stack frame format

• Use of a single, self-aligning system stack pointer

ColdFire processors use an instruction restart exception model but require more software support to recover from certain access errors. See Table 2-18 for details.

Exception processing can be deﬁned as the time from the detection of the fault condition until the fetch of the ﬁrst handler instruction has been initiated. It is comprised of the following four major steps:

1. The processor makes an internal copy of the SR and then enters supervisor mode by setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an interrupt exception also forces SR[M] to be cleared and the interrupt priority mask to be set to the level of the current interrupt request.

2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a peripheral device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address.

3. The processor saves the current context by creating an exception stack frame on the system stack. ColdFire processors support a single stack pointer in the A7 address register; therefore, there is no notion of separate supervisor and user stack pointers. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a simpliﬁed

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Exception Processing Overview

ﬁxed-length stack frame for all exceptions. The exception type determines whether the program counter in the exception stack frame deﬁnes the address of the faulting instruction (fault) or of the next instruction to be executed (next).

4. The processor acquires the address of the ﬁrst instruction of the exception handler. The exception vector table is aligned on a 1-Mbyte boundary. This instruction address is obtained by fetching a value from the table at the address deﬁned in the vector base register. The index into the exception table is calculated as 4 x vector_number. When the index value is generated, the vector table contents determine the address of the ﬁrst instruction of the desired handler. After the fetch of the ﬁrst opcode of the handler is initiated, exception processing terminates and normal instruction processing continues in the handler.

ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address boundary; see Table 2-18. The table contains 256 exception vectors where the ﬁrst 64 are deﬁned by Motorola; the remaining 192 are user-deﬁned interrupt vectors.

Table 2-18. Exception Vector Assignments

Vector Numbers Vector Offset (Hex) Stacked Program Counter

0 000 — Initial stack pointer 1 004 — Initial program counter 2 008 Fault Access error 3 00C Fault Address error 4 010 Fault Illegal instruction 5 014 Fault Divide by zero

6–7 018–01C — Reserved

8 020 Fault Privilege violation

9 024 Next Trace 10 028 Fault Unimplemented line-a opcode 11 02C Fault Unimplemented line-f opcode 12 030 Next Debug interrupt 13 034 — Reserved 14 038 Fault Format error 15 03C Next Uninitialized interrupt

16–23 040–05C — Reserved

24 060 Next Spurious interrupt

25–31 064–07C Next Level 1–7 autovectored interrupts 32–47 080–0BC Next Trap #0–15 instructions 48–60 0C0–0F0 — Reserved

61 0F4 Fault Unsupported instruction

Assignment

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Exception Processing Overview

Table 2-18. Exception Vector Assignments (Continued)

Vector Numbers Vector Offset (Hex) Stacked Program Counter

62–63 0F8–0FC — Reserved

64–255 100–3FC Next User-deﬁned interrupts

The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC of the instruction that immediately follows the instruction that caused the fault.

Assignment

ColdFire processors inhibit sampling for interrupts during the ﬁrst instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register.

2.8.1 Exception Stack Frame Deﬁnition

The exception stack frame is shown in Figure 2-10. The ﬁrst longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword contains the 32-bit program counter address.

31 28 27 26 25 18 17 16 15 0

A7→ Format FS[3–2] Vector[7–0] FS[1–0] Status Register

+ 0x04 Program Counter [31–0]

Figure 2-10. Exception Stack Frame Form

The 16-bit format/vector word contains three unique ﬁelds:

• Format ﬁeld—This 4-bit ﬁeld at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. See Table 2-19. This ﬁeld records any longword misalignment of the stack pointer that may have existed when the exception occurred.

Table 2-19. Format Field Encoding

Original A7 at Time of

Exception, Bits 1–0

00 Original A[7–8] 0100 01 Original A[7–9] 0101 10 Original A[7–10] 0110 11 Original A[7–11] 0111

A7 at First Instruction of

Handler

Format Field Bits

31–28

• Fault status ﬁeld—The 4-bit ﬁeld, FS[3–0], at the top of the system stack is deﬁned for access and address errors along with interrupted debug service routines. See Table 2-20.

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Exception Processing Overview

Table 2-20. Fault Status Encodings

FS[3–0] Deﬁnition

0000 Not an access or address error

0001-001x Reserved

0100 Error on instruction fetch

0101–011x Reserved

1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read

1101–111x Reserved

• Vector number—This 8-bit ﬁeld, vector[7–0], deﬁnes the exception type. It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-18.

2.8.2 Processor Exceptions

Table 2-21 describes MCF5307 exceptions.

Table 2-21. MCF5307 Exceptions

Exception Description

Access Error Access errors are reported only in conjunction with an attempted store to write-protected memory.

Address Error

Illegal Instruction

Divide by Zero

Privilege Violation

Thus, access errors associated with instruction fetch or operand read accesses are not possible. Caused by an attempted execution transf erring control to an odd instruction address (that is, if bit 0 of

the target address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of 8 on an indexed effectiv e addressing mode , or attempted ex ecution of an instruction with a full-f ormat indexed addressing mode.

On Version 2 ColdFire implementations, only some illegal opcodes were decoded and generated an illegal instruction exception. The Version 3 processor decodes the full 16-bit opcode and generates this exception if execution of an unsupported instruction is attempted. Additionally, attempting to execute an illegal line A or line F opcode generates unique exception types: vectors 10 and 11, respectively. ColdFire processors do not provide illegal instruction detection on extension words of any instruction, including MOVEC. Attempting to execute an instruction with an illegal extension word causes undeﬁned results.

Attempted division by zero causes an exception (vector 5, offset = 0x014) e xcept when the PC points to the faulting instruction (DIVU, DIVS, REMU, REMS).

Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire Programmer’s Reference Manual lists supervisor- and user-mode instructions.

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Exception Processing Overview

Table 2-21. MCF5307 Exceptions (Continued)

Exception Description

Trace Exception

Debug Interrupt

RTE and Format Error Exceptions

TRAP Executing TRAP always forces an exception and is useful for implementing system calls. The trap

Interrupt Exception

ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this deﬁnition is the STOP instruction. If the processor is in trace mode, the instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reﬂects the just-loaded value. If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets the trace bit in the SR, hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reﬂects the just-loaded value. Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other e xception types. As an example, consider a TRAP instruction executing in trace mode. The processor initiates the TRAP exception and passes control to the corresponding handler. If the system requires that a trace exception be processed, the TRAP exception handler must check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception.

Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the processor internally calculates the vector number (12). Additionally, the M bit and the interrupt priority mask ﬁelds of the SR are unaffected by the interrupt. See Section 2.2.2.1, “Status Register (SR).”

When an RTE instruction executes, the processor ﬁrst examines the 4-bit format ﬁeld to validate the frame type. For a ColdFire processor, any attempted execution of an RTE where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original exception frame and the stacked PC points to R TE.The selection of the format value provides limited debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero; so, attempting an RTE using this old format generates a format error on a ColdFire processor. If the format ﬁeld deﬁnes a valid type, the processor does the following: 1 Reloads the SR operand. 2 Fetches the second longword operand. 3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the ﬁrst

longword fetch.

4 Transfers control to the instruction address deﬁned by the second longword operand in the stack

frame.

instruction may be used to change from user to supervisor mode. Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized

and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. Autovectoring may optionally be conﬁgured through the system interface module (SIM). See Section 9.2.2, “Autovector Register (AVR).”

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Table 2-21. MCF5307 Exceptions (Continued)

Exception Description

Reset Exception

Unsupported Instruction Exception

Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception priority; it provides for system initialization and recovery from catastrophic failure. When assertion of RSTI

is recognized, current processing is aborted and cannot be recovered. The reset exception places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T]. This exception also clears SR[M] and sets the processor’s interrupt priority mask in the SR to the highest level (lev el 7). Next, the VBR is initializ ed to 0x0000_0000. Conﬁguration registers controlling the operation of all processor-local memories (cache and RAM modules on the MCF5307) are invalidated, disabling the memories. Note: Other implementation-speciﬁc supervisor registers are also affected. Refer to each of the modules in this manual for details on these registers. After RSTI process. During this time, certain events are sampled, including the assertion of the debug breakpoint signal. If the processor is not halted, it initiates the reset exception by performing two longword read bus cycles. The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC. After the initial instruction is fetched from memory, program execution begins at the address in the PC . If an access error or address error occurs before the ﬁrst instruction executes, the processor enters the fault-on-fault halted state.

If the MCF5307 attempts to execute a valid instruction but the required optional hardware module is not present in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is then passed to an exception handler that can then process the opcode as required by the system.

is negated, the processor waits 80 cycles before beginning the actual reset exception

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state.

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Chapter 3 Hardware Multiply/Accumulate (MAC) Unit

This chapter describes the MCF5307 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).

3.1 Overview

The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family.

The MAC unit provides signal processing capabilities for the MCF5307 in a variety of applications including digital audio and servo control. Integrated as an ex ecution unit in the processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, ﬁxed-point fractional input operands.

The MAC unit provides functionality in three related areas:

• Signed and unsigned integer multiplies

• Multiply-accumulate operations supporting signed, unsigned, and signed fractional operands

• Miscellaneous register operations

Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this functionality is contained in a MAC module, as shown in Figure 3-1.

The MAC unit is tightly coupled to the OEP and features a three-stage execution pipeline. To minimize silicon costs, the ColdFire MAC is optimized for 16 x 16 multiply instructions. The OEP can issue a 16 x 16 multiply with a 32-bit accumulation and fetch a 32-bit operand in the same cycle. A 32 x 32 multiply with a 32-bit accumulation takes three cycles before the next instruction can be issued. Figure 3-1 shows the basic functionality of the ColdFire MAC. A full set of instructions is provided for signed and unsigned integers plus signed, ﬁxed-point, fractional input operands.

Chapter 3. Hardware Multiply/Accumulate (MAC) Unit 3-1

Overview

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Operand Y Operand X

Shift 0,1,-1

+/-

Accumulator

Figure 3-1. ColdFire MAC Multiplication and Accumulation

The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints. F or example, small digital ﬁlters can tolerate some variance in the execution time of the algorithm; larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements exceeding the scope of any processor architecture and requiring a fully developed DSP implementation.

The M68000 architecture was not designed for high-speed signal processing, and a large DSP engine would be excessive in an embedded environment. In striking a middle ground between speed, size, and functionality , the ColdFire MAC unit is optimized for a small set of operations that involve multiplication and cumulative additions. Speciﬁcally, the multiplier array is optimized for single-cycle, 16 x 16 multiplies producing a 32-bit result, with a possible accumulation cycle following. This is common in a large portion of signal processing applications. In addition, the ColdFire core architecture has been modiﬁed to allow for an operand fetch in parallel with a multiply, increasing overall performance for certain DSP operations.

3.1.1 MAC Programming Model

Figure 3-2 shows the registers in the MAC portion of the user programming model.

31 0

MACSR MAC status register ACC MAC accumulator MASK MAC mask register

Figure 3-2. MAC Programming Model

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These registers are described as follows:

• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.

• MAC status register (MACSR)—This 8-bit register deﬁnes conﬁguration of the MAC unit and contains indicator ﬂags af fected by MAC instructions. Unless noted otherwise, the setting of MACSR indicator ﬂags is based on the ﬁnal result, that is, the result of the ﬁnal operation involving the product and accumulator.

Overview

3.1.2 General Operation

The MAC unit supports the ColdFire integer multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of this number to or from the value contained in the accumulator. The product may be optionally shifted left or right one bit before the addition or subtraction takes place. Hardware support for saturation arithmetic may be enabled to minimize software overhead when dealing with potential ov erﬂo w conditions using signed or unsigned operands.

These MAC operations treat the operands as one of the following formats:

• Signed integers

• Unsigned integers

• Signed, ﬁxed-point, fractional numbers

To maintain compactness, the MAC module is optimized for 16-bit multiplications. Two 16-bit operands produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit result. For longword integer operations, only the least signiﬁcant 32 bits of the product are calculated. For fractional operations, the entire 63-bit product is calculated and then either truncated or rounded to a 32-bit result using the round-to-nearest (even) method.

Because the multiplier array is implemented in a 3-stage pipeline, MAC instructions can have an effective issue rate of one clock for word operations, three for longword integer operations, and four for 32-bit fractional operations. Arithmetic operations use register-based input operands, and summed values are stored internally in the accumulator. Thus, an additional MOVE instruction is necessary to store data in a general-purpose register. MAC instructions can choose the upper or lower word of a register as the input, which helps ﬁltering operations in which one data register is loaded with input data and another is loaded with coefﬁcient data. Two 16-bit MAC operations can be performed without fetching additional operands between instructions by alternating the word choice

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Overview

during the calculations. The need to move large amounts of data quickly can limit throughput in DSP engines.

However, data can be moved efﬁciently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for ﬁlling registers quickly with input data, ﬁlter coefﬁcients, and output data. Loading an operand from memory into a register during a MAC operation makes some DSP operations, especially ﬁltering and convolution, more manageable.

The MACSR has a 4-bit operational mode ﬁeld and three condition ﬂags. The operational mode bits control the overﬂow/saturation mode, whether operands are signed or unsigned, whether operands are treated as integers or fractions, and how rounding is performed. Negative, zero and overﬂow ﬂags are also provided.

The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask register (MASK), and MACSR, are described in Section 3.1.1, “MAC Programming Model.”

3.1.3 MAC Instruction Set Summary

The MAC unit supports the integer multiply operations deﬁned by the baseline ColdFire architecture, as well as the new multiply-accumulate instructions. Table 3-1 summarizes the MAC unit instruction set.

Table 3-1. MAC Instruction Summary

Instruction Mnemonic Description

Multiply Signed MULS <ea>y,Dx Multiplies two signed operands yielding a signed result Multiply Unsigned MULU <ea>y,Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate MAC Ry,RxSF

Multiply Accumulate with Load

Load Accumulator MOV.L {Ry,#imm},ACC Loads the accumulator with a 32-bit operand Store Accumulator MOV.L ACC,Rx Writes the contents of the accumulator to a register Load MACSR MOV.L {Ry,#imm},MACSR Writes a value to the MACSR Store MACSR MOV.L MACSR,Rx Write the contents of MACSR to a register Store MACSR to CCR MOV.L MACSR,CCR Write the contents of MACSR to the processor’s CCR register Load MASK MOV.L {Ry,#imm},MASK Writes a value to MASK Store MASK MOV.L MASK,Rx Writes the contents of MASK to a register

MSAC Ry,RxSF MAC Ry,RxSF,Rw

MSAC Ry,RxSF,Rw

Multiplies two operands, then adds or subtracts the product to/from the accumulator

Multiplies two operands, then adds or subtracts the product to/from the accumulator while loading a register with the memory operand

3.1.4 Data Representation

The MAC unit supports three basic operand types:

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MAC Instruction Execution Timings

• Two’s complement signed integer: In this format, an N-bit operand represents a number within the range -2

(N-1)

< operand < 2

(N-1)

- 1. The binary point is to the right

of the least signiﬁcant bit.

• Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 <

operand < 2N - 1. The binary point is to the right of the

least signiﬁcant bit.

• T wo’ s complement, signed fractional: In an N-bit number , the ﬁrst bit is the sign bit. The remaining bits signify the ﬁrst N-1 bits after the binary point. Given an N-bit number, a

N-1aN-2aN-3

... a2a1a0, its value is given by the following formula:

N2–

i0=

This format can represent numbers in the range -1 <

i1N–+()

∑

ai⋅

operand < 1 - 2

(N-1)

For words and longwords, the greatest negati ve number that can be represented is -1, whose internal representation is 0x8000 and 0x0x8000_0000, respectively. The

most positive word is 0x7FFF or (1 - 2 0x7FFF_FFFF or (1 - 2

-31

-15

); the most positive longword is

3.2 MAC Instruction Ex ecution Timings

Table 3-2 shows standard timings for two-operand MAC instructions.

Table 3-2. Two-Operand MAC Instruction Execution Times

Opcode Í

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

mac.w Ry,Rx 1(0/0) — — — — — — —

mac.l Ry,Rx 3(0/0) — — — — — — —

msac.w Ry,Rx 1(0/0) — — — — — — —

msac.l Ry,Rx 3(0/0) — — — — — — — mac.w Ry,Rx,ea,Rw — 1(1/0) 1(1/0) 1(1/0) 1(1/0) — — —

mac.l Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

msac.w Ry,Rx,ea,Rw — 1(1/0) 1(1/0) 1(1/0) 1(1/0) — — —

msac.l Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — — muls.w <ea>,Dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) mulu.w <ea>,Dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0)

muls.l <ea>,Dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — — mulu.l <ea>,Dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — —

Effective Address

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MAC Instruction Execution Timings

Table 3-3 shows standard timings for MAC move instructions.

Table 3-3. MAC Move Instruction Execution Times

Opcode Í

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>

move.l <ea>,ACC 1(0/0) — — — — — — 1(0/0) move.l <ea>,MACSR 6(0/0) — — — — — — 6(0/0) move.l <ea>,MASK 5(0/0) — — — — — — 5(0/0) move.l ACC,Rx 1(0/0) — — — — — — — move.l MACSR,CCR 1(0/0) — — — — — — — move.l MACSR,Rx 1(0/0) — — — — — — — move.l MASK,Rx 1(0/0) — — — — — — —

Effective Address

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Chapter 4 Local Memory

This chapter describes the MCF5307 implementation of the ColdFire Version 3 local memory speciﬁcation. It consists of two major sections.

• Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, conﬁguration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.

• Section 4.7, “Cache Overview,” describes the MCF5307 cache implementation, including organization, conﬁguration, and coherency. It describes cache operations and how the cache interfaces with other memory structures.

4.1 Interactions between Local Memory Modules

Depending on conﬁguration information, instruction fetches and data read accesses may be sent simultaneously to the RAM and cache controllers. This approach is required because both controllers are memory-mapped devices and the hit/miss determination is made concurrently with the read data access. Power dissipation can be minimized by conﬁguring the RAMBARs to mask unused address spaces whenever possible.

If the access address is mapped into the region deﬁned by the RAM (and this region is not masked), the RAM provides the data back to the processor , and the cache data is discarded. Accesses from the RAM module are never cached. The complete deﬁnition of the processor’s local bus priority scheme for read references is as follows:

) RAM supplies data to the processor

For data write references, the memory mapping into the local memories is resolved before the appropriate destination memory is accessed. Accordingly, only the targeted local memory is accessed for data write transfers.

if (RAM “hits” else if (cache “hits”)

cache supplies data to the processor

else system memory reference to access data

4.2 SRAM Overview

The 4-Kbyte on-chip SRAM module is connected to the internal bus and provides pipelined, single-cycle access to memory mapped to the module. Memory can be mapped to any

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SRAM Operation

0-modulo-32K location in the 4-Gbyte address space and conﬁgured to respond to either instruction or data accesses.Time-critical functions can be mapped into instruction the system stack. Other heavily-referenced data can be mapped into memory.

The following summarizes features of the MCF5307 SRAM implementation:

• 4-Kbyte SRAM, organized as 1024 x 32 bits

• Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle.

• Physical location on the processor’s high-speed local bus

• Memory location programmable on any 0-modulo-32K address boundary

• Byte, word, and longword address capabilities

• The RAM base address register (RAMBAR) deﬁnes the logical base address, attributes, and access types for the SRAM module.

4.3 SRAM Operation

The SRAM module provides a general-purpose memory block that the ColdFire processor can access with single-cycle throughput. The location of the memory block can be speciﬁed to any word-aligned address in the 4-Gbyte address space by RAMBAR[BA], described in Section 4.4.1, “SRAM Base Address Register (RAMBAR).” The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module connects physically to the processor’s high-speed local bus, it can service processor-initiated accesses or memory-referencing debug module commands.

Instruction fetches and data reads can be sent to both the cache and SRAM blocks simultaneously . If the reference is mapped into a region deﬁned by the SRAM, the SRAM provides data to the processor and any cache data is discarded. Data accessed from the SRAM module are not cached.

Note also that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system conﬁguration allows concurrent core and DMA execution, where the core can reference code or data from the internal SRAM or cache while performing a DMA transfer.

4-2 MCF5307 User’s Manual

Freescale MCF5307 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

About This Book

Audience

Organization

Suggested Reading

General Information

ColdFire Documentation

Conventions

Acronyms and Abbreviations

Terminology and Notational Conventions

1.1 Features

1.2 MCF5307 Features

1.2.1 Process

1.3 ColdFire Module Description

1.3.1 ColdFire Core

1.3.1.1 Instruction Fetch Pipeline (IFP)

1.3.1.2 Operand Execution Pipeline (OEP)

1.3.1.3 MAC Module

1.3.1.4 Integer Divide Module

1.3.1.6 Internal 4-Kbyte SRAM

1.3.2 DRAM Controller

1.3.3 DMA Controller

1.3.4 UART Modules

1.3.5 Timer Module

1.3.7 System Interface

1.3.7.1 External Bus Interface

1.3.7.2 Chip Selects

1.3.7.3 16-Bit Parallel Port Interface

1.3.7.4 Interrupt Controller

1.3.7.5 JTAG

1.3.8 System Debug Interface

1.3.9 PLL Module

1.4 Programming Model, Addressing Modes, and Instruction Set

1.4.1 Programming Model

1.4.2 User Registers

1.4.3 Supervisor Registers

1.4.4 Instruction Set

2.1 Features and Enhancements

2.1.1 Clock-Multiplied Microprocessor Core

2.1.2 Enhanced Pipelines

2.1.2.1 Instruction Fetch Pipeline (IFP)

2.1.2.1.1 Branch Acceleration

2.1.2.2 Operand Execution Pipeline (OEP)

2.1.2.2.1 Illegal Opcode Handling

2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit

2.1.2.2.3 Hardware Divide Unit

2.1.3 Debug Module Enhancements

2.2 Programming Model

2.2.1 User Programming Model

2.2.1.1 Data Registers (D0–D7)

2.2.1.2 Address Registers (A0–A6)

2.2.1.3 Stack Pointer (A7, SP)

2.2.1.4 Program Counter (PC)

2.2.1.5 Condition Code Register (CCR)

2.2.2 Supervisor Programming Model

2.2.2.1 Status Register (SR)

2.2.2.2 Vector Base Register (VBR)

2.2.2.3 Cache Control Register (CACR)

2.2.2.4 Access Control Registers (ACR0–ACR1)

2.2.2.5 RAM Base Address Register (RAMBAR)

2.2.2.6 Module Base Address Register (MBAR)

2.3 Integer Data Formats

2.4 Organization of Data in Registers

2.4.1 Organization of Integer Data Formats in Registers

2.4.2 Organization of Integer Data Formats in Memory

2.5 Addressing Mode Summary

2.6 Instruction Set Summary

2.6.1 Instruction Set Summary

2.7 Instruction Timing

2.7.1 MOVE Instruction Execution Times

2.7.2 Execution Timings—One-Operand Instructions

2.7.3 Execution Timings—Two-Operand Instructions

2.7.4 Miscellaneous Instruction Execution Times

2.7.5 Branch Instruction Execution Times

2.8 Exception Processing Overview

2.8.2 Processor Exceptions

3.1 Overview