Freescale MCF5307 DATA SHEET

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MCF5307 ColdFire

Integrated Microprocessor

User’s Manual

MCF5307UM/D

Rev. 2.0, 08/2000

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ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductors

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us: USA/EUROPE/Locations Not Listed:

or 1–800–441–2447

JAPAN:

Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan.

81–3–3440–3569

ASIA/PACIFIC:

Hong Kong. 852–26668334

Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.,

Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140

Technical Information Center:

HOME PAGE:

Document Comments World Wide Web Addresses

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: FAX (512) 895-2638, Attn: RISC Applications Engineering

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: http://www.motorola.com/PowerPC

http://www.motorola.com/NetComm http://www.motorola.com/ColdFire

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Overview

Part I: MCF5307

Processor

Core

ColdFire Core

Hardware Multiply/Accumulate (MAC) Unit

Local Memory

Debug Support

Part II: System Integration Module (

SIM)

SIM Overview

Phase-Locked Loop (PLL)

C Module

Interrupt Controller

Chip-Select Module

Synchronous/Asynchronous DRAM Controller Module

Part III: Peripheral Module

DMA Controller Module

Timer Module

UART Modules

Parallel Port (General-Purpose I/O)

Part IV: Hardware Interface

Mechanical Data

Signal Descriptions

Part I

2 3 4 5

Part II

6 7 8

9 10 11

Part III

12 13 14

Part IV

16 17

Bus Operation

IEEE 1149.1 Test Access Port (JTAG)

Electrical Specifications

Appendix: Memory Map

Glossary of Terms and Abbreviations

Index

18 19

GLO

IND

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Part I

2 3 4 5

Part II

6 7 8

Overview Part I: MCF5307

Processor

Core ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support Part II: System Integration Module (

SIM) SIM Overview Phase-Locked Loop (PLL)

C Module

9 10 11

Part III

12 13 14

Part IV

Interrupt Controller Chip-Select Module Synchronous/Asynchronous DRAM Controller Module Part III: Peripheral Module DMA Controller Module Timer Module UART Modules

Parallel Port (General-Purpose I/O)

Part IV: Hardware Interface

16 17 18 19

GLO

IND

Mechanical Data Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Electrical Specifications

Appendix B: Memory Map Glossary of Terms and Abbreviations Index

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CONTENTS

Paragraph Number

Title

Page

Number

About This Book

Chapter 1

Overview

1.1 Features............................................................................................................... 1-1

1.2 MCF5307 Features.............................................................................................. 1-4

1.2.1 Process............................................................................................................ 1-6

1.3 ColdFire Module Description............................................................................. 1-7

1.3.1 ColdFire Core ................................................................................................. 1-7

1.3.1.1 Instruction Fetch Pipeline (IFP).................................................................. 1-7

1.3.1.2 Operand Execution Pipeline (OEP)............................................................ 1-7

1.3.1.3 MAC Module.............................................................................................. 1-7

1.3.1.4 Integer Divide Module................................................................................ 1-7

1.3.1.5 8-Kbyte Unified Cache............................................................................... 1-8

1.3.1.6 Internal 4-Kbyte SRAM ............................................................................. 1-8

1.3.2 DRAM Controller........................................................................................... 1-8

1.3.3 DMA Controller.............................................................................................. 1-8

1.3.4 UART Modules............................................................................................... 1-8

1.3.5 Timer Module................................................................................................. 1-9

1.3.6 I2C Module..................................................................................................... 1-9

1.3.7 System Interface ........................................................................................... 1-10

1.3.7.1 External Bus Interface .............................................................................. 1-10

1.3.7.2 Chip Selects .............................................................................................. 1-10

1.3.7.3 16-Bit Parallel Port Interface.................................................................... 1-10

1.3.7.4 Interrupt Controller................................................................................... 1-10

1.3.7.5 JTAG......................................................................................................... 1-11

1.3.8 System Debug Interface................................................................................ 1-11

1.3.9 PLL Module.................................................................................................. 1-11

1.4 Programming Model, Addressing Modes, and Instruction Set......................... 1-12

1.4.1 Programming Model..................................................................................... 1-13

1.4.2 User Registers............................................................................................... 1-14

1.4.3 Supervisor Registers..................................................................................... 1-14

1.4.4 Instruction Set............................................................................................... 1-15

Contents

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CONTENTS

Paragraph Number

Title

Page

Number

Part I

MCF5407 Processor Core

Chapter 2

ColdFire Core

2.1 Features and Enhancements.............................................................................. 2-21

2.1.1 Clock-Multiplied Microprocessor Core........................................................ 2-22

2.1.2 Enhanced Pipelines....................................................................................... 2-22

2.1.2.1 Instruction Fetch Pipeline (IFP)................................................................ 2-23

2.1.2.1.1 Branch Acceleration ............................................................................. 2-23

2.1.2.2 Operand Execution Pipeline (OEP).......................................................... 2-24

2.1.2.2.1 Illegal Opcode Handling....................................................................... 2-24

2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit...................................... 2-24

2.1.2.2.3 Hardware Divide Unit .......................................................................... 2-25

2.1.3 Debug Module Enhancements...................................................................... 2-25

2.2 Programming Model......................................................................................... 2-26

2.2.1 User Programming Model ............................................................................ 2-27

2.2.1.1 Data Registers (D0–D7) ........................................................................... 2-27

2.2.1.2 Address Registers (A0–A6)...................................................................... 2-27

2.2.1.3 Stack Pointer (A7, SP).............................................................................. 2-28

2.2.1.4 Program Counter (PC).............................................................................. 2-28

2.2.1.5 Condition Code Register (CCR)............................................................... 2-28

2.2.2 Supervisor Programming Model................................................................... 2-29

2.2.2.1 Status Register (SR).................................................................................. 2-29

2.2.2.2 Vector Base Register (VBR) .................................................................... 2-30

2.2.2.3 Cache Control Register (CACR) .............................................................. 2-30

2.2.2.4 Access Control Registers (ACR0–ACR1)................................................ 2-31

2.2.2.5 RAM Base Address Register (RAMBAR)............................................... 2-31

2.2.2.6 Module Base Address Register (MBAR) ................................................. 2-31

2.3 Integer Data Formats......................................................................................... 2-31

2.4 Organization of Data in Registers..................................................................... 2-31

2.4.1 Organization of Integer Data Formats in Registers...................................... 2-31

2.4.2 Organization of Integer Data Formats in Memory ....................................... 2-32

2.5 Addressing Mode Summary ............................................................................. 2-33

2.6 Instruction Set Summary................................................................................... 2-34

2.6.1 Instruction Set Summary .............................................................................. 2-37

2.7 Instruction Timing ............................................................................................ 2-40

2.7.1 MOVE Instruction Execution Times............................................................ 2-41

2.7.2 Execution Timings—One-Operand Instructions.......................................... 2-43

2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-43

2.7.4 Miscellaneous Instruction Execution Times................................................. 2-45

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2.7.5 Branch Instruction Execution Times ............................................................ 2-46

2.8 Exception Processing Overview....................................................................... 2-47

2.8.1 Exception Stack Frame Definition................................................................ 2-49

2.8.2 Processor Exceptions.................................................................................... 2-50

Title

Page

Number

Chapter 3

Hardware Multiply/Accumulate (MAC) Unit

3.1 Overview............................................................................................................. 3-1

3.1.1 MAC Programming Model............................................................................. 3-2

3.1.2 General Operation........................................................................................... 3-3

3.1.3 MAC Instruction Set Summary ...................................................................... 3-4

3.1.4 Data Representation........................................................................................ 3-4

3.2 MAC Instruction Execution Timings.................................................................. 3-5

Chapter 4

Local Memory

4.1 Interactions between Local Memory Modules ................................................... 4-1

4.2 SRAM Overview ................................................................................................ 4-1

4.3 SRAM Operation................................................................................................ 4-2

4.4 SRAM Programming Model............................................................................... 4-3

4.4.1 SRAM Base Address Register (RAMBAR)................................................... 4-3

4.5 SRAM Initialization............................................................................................ 4-4

4.5.1 SRAM Initialization Code.............................................................................. 4-5

4.6 Power Management ............................................................................................ 4-6

4.7 Cache Overview.................................................................................................. 4-6

4.8 Cache Organization............................................................................................. 4-7

4.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8

4.8.2 The Cache at Start-Up..................................................................................... 4-9

4.9 Cache Operation................................................................................................ 4-11

4.9.1 Caching Modes............................................................................................. 4-13

4.9.1.1 Cacheable Accesses.................................................................................. 4-13

4.9.1.2 Write-Through Mode ............................................................................... 4-14

4.9.1.3 Copyback Mode ....................................................................................... 4-14

4.9.2 Cache-Inhibited Accesses............................................................................. 4-14

4.9.3 Cache Protocol.............................................................................................. 4-15

4.9.3.1 Read Miss ................................................................................................. 4-15

4.9.3.2 Write Miss ............................................................................................... 4-16

4.9.3.3 Read Hit.................................................................................................... 4-16

4.9.3.4 Write Hit .................................................................................................. 4-16

4.9.4 Cache Coherency ......................................................................................... 4-17

Contents

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CONTENTS

Paragraph Number

4.9.5 Memory Accesses for Cache Maintenance................................................... 4-17

4.9.5.1 Cache Filling............................................................................................. 4-17

4.9.5.2 Cache Pushes ............................................................................................ 4-18

4.9.5.2.1 Push and Store Buffers ......................................................................... 4-18

4.9.5.2.2 Push and Store Buffer Bus Operation................................................... 4-18

4.9.6 Cache Locking.............................................................................................. 4-19

4.10 Cache Registers................................................................................................. 4-21

4.10.1 Cache Control Register (CACR) .................................................................. 4-21

4.10.2 Access Control Registers (ACR0–ACR1).................................................... 4-22

4.11 Cache Management........................................................................................... 4-24

4.12 Cache Operation Summary............................................................................... 4-25

4.12.1 Cache State Transitions ................................................................................ 4-25

4.13 Cache Initialization Code.................................................................................. 4-29

Title

Page

Number

Chapter 5

Debug Support

5.1 Overview............................................................................................................. 5-1

5.2 Signal Description............................................................................................... 5-2

5.3 Real-Time Trace Support.................................................................................... 5-3

5.3.1 Begin Execution of Taken Branch (PST = 0x5)............................................. 5-4

5.4 Programming Model........................................................................................... 5-5

5.4.1 Address Attribute Trigger Register (AATR).................................................. 5-7

5.4.2 Address Breakpoint Registers (ABLR, ABHR)............................................ 5-8

5.4.3 BDM Address Attribute Register (BAAR)..................................................... 5-9

5.4.4 Configuration/Status Register (CSR)............................................................ 5-10

5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-12

5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-13

5.4.7 Trigger Definition Register (TDR)............................................................... 5-14

5.5 Background Debug Mode (BDM).................................................................... 5-16

5.5.1 CPU Halt....................................................................................................... 5-16

5.5.2 BDM Serial Interface.................................................................................... 5-17

5.5.2.1 Receive Packet Format ............................................................................. 5-19

5.5.2.2 Transmit Packet Format............................................................................ 5-19

5.5.3 BDM Command Set...................................................................................... 5-19

5.5.3.1 ColdFire BDM Command Format............................................................ 5-20

5.5.3.1.1 Extension Words as Required............................................................... 5-21

5.5.3.2 Command Sequence Diagrams................................................................. 5-21

5.5.3.3 Command Set Descriptions ...................................................................... 5-23

5.5.3.3.1 Read A/D Register (

5.5.3.3.2 Write A/D Register (

5.5.3.3.3 Read Memory Location (

RAREG/RDREG

WAREG/WDREG

READ

) ..................................................... 5-24

)................................................... 5-25

)............................................................ 5-26

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CONTENTS

Paragraph Number

5.5.3.3.4 Write Memory Location (

5.5.3.3.5 Dump Memory Block (

5.5.3.3.6 Fill Memory Block (

5.5.3.3.7 Resume Execution (

5.5.3.3.8 No Operation (

5.5.3.3.9 Synchronize PC to the PST/DDATA Lines (

5.5.3.3.10 Read Control Register (

5.5.3.3.11 Write Control Register (

5.5.3.3.12 Read Debug Module Register (

5.5.3.3.13 Write Debug Module Register (

5.6 Real-Time Debug Support................................................................................ 5-39

5.6.1 Theory of Operation...................................................................................... 5-40

5.6.1.1 Emulator Mode......................................................................................... 5-41

5.6.2 Concurrent BDM and Processor Operation.................................................. 5-41

5.7 Motorola-Recommended BDM Pinout............................................................. 5-42

5.8 Processor Status, DDATA Definition............................................................... 5-42

5.8.1 User Instruction Set ...................................................................................... 5-43

5.8.2 Supervisor Instruction Set............................................................................. 5-46

NOP

Title

WRITE

) ......................................................... 5-27

DUMP

).............................................................. 5-29

FILL

)..................................................................... 5-31

)........................................................................ 5-33

) .............................................................................. 5-34

SYNC_PC

RCREG

)............................................................ 5-36

WCREG

) .......................................................... 5-37

RDMREG

WDMREG

) ............................................. 5-38

) ........................................... 5-39

) ....................... 5-35

Page

Number

Part II

System Integration Module (SIM)

Chapter 6

SIM Overview

6.1 Features............................................................................................................... 6-1

6.2 Programming Model........................................................................................... 6-3

6.2.1 SIM Register Memory Map............................................................................ 6-3

6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4

6.2.3 Reset Status Register (RSR)........................................................................... 6-5

6.2.4 Software Watchdog Timer.............................................................................. 6-6

6.2.5 System Protection Control Register (SYPCR) ............................................... 6-8

6.2.6 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9

6.2.7 Software Watchdog Service Register (SWSR)............................................... 6-9

6.2.8 PLL Clock Control for CPU STOP Instruction............................................ 6-10

6.2.9 Pin Assignment Register (PAR)................................................................... 6-10

6.2.10 Bus Arbitration Control................................................................................ 6-11

6.2.10.1 Default Bus Master Park Register (MPARK) .......................................... 6-11

6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12

6.2.10.1.2 Arbitration between Internal and External Masters

for Accessing Internal Resources ......................................................... 6-14

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CONTENTS

Paragraph Number

Title

Page

Number

Chapter 7

Phase-Locked Loop (PLL)

7.1 Overview............................................................................................................. 7-1

7.1.1 PLL:PCLK Ratios........................................................................................... 7-2

7.2 PLL Operation .................................................................................................... 7-2

7.2.1 Reset/Initialization.......................................................................................... 7-2

7.2.2 Normal Mode.................................................................................................. 7-2

7.2.3 Reduced-Power Mode..................................................................................... 7-2

7.2.4 PLL Control Register (PLLCR)...................................................................... 7-3

7.3 PLL Port List ...................................................................................................... 7-3

7.4 Timing Relationships.......................................................................................... 7-4

7.4.1 PCLK, PSTCLK, and BCLKO....................................................................... 7-4

7.4.2 RSTI

7.5 PLL Power Supply Filter Circuit........................................................................ 7-6

8.1 Overview............................................................................................................. 8-1

8.2 Interface Features................................................................................................ 8-1

8.3 I

8.4 I

8.4.1 Arbitration Procedure ..................................................................................... 8-4

8.4.2 Clock Synchronization.................................................................................... 8-5

8.4.3 Handshaking ................................................................................................... 8-5

8.4.4 Clock Stretching ............................................................................................. 8-5

8.5 Programming Model........................................................................................... 8-6

8.5.1 I

8.5.2 I

8.5.3 I

8.5.4 I

8.5.5 I

8.6 I

8.6.1 Initialization Sequence.................................................................................. 8-10

8.6.2 Generation of START................................................................................... 8-10

8.6.3 Post-Transfer Software Response................................................................. 8-11

8.6.4 Generation of STOP...................................................................................... 8-12

8.6.5 Generation of Repeated START................................................................... 8-12

8.6.6 Slave Mode................................................................................................... 8-13

8.6.7 Arbitration Lost............................................................................................. 8-13

Timing................................................................................................... 7-5

Chapter 8

C Module

C System Configuration................................................................................... 8-3

C Protocol ........................................................................................................ 8-3

C Address Register (IADR)......................................................................... 8-6

C Frequency Divider Register (IFDR)......................................................... 8-7

C Control Register (I2CR)........................................................................... 8-8

C Status Register (I2SR).............................................................................. 8-9

C Data I/O Register (I2DR)....................................................................... 8-10

C Programming Examples............................................................................. 8-10

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CONTENTS

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Title

Page

Number

Chapter 9

Interrupt Controller

9.1 Overview............................................................................................................. 9-1

9.2 Interrupt Controller Registers............................................................................. 9-2

9.2.1 Interrupt Control Registers (ICR0–ICR9) ...................................................... 9-3

9.2.2 Autovector Register (AVR)............................................................................ 9-5

9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)................................... 9-6

9.2.4 Interrupt Port Assignment Register (IRQPAR).............................................. 9-7

Chapter 10

10.1 Overview........................................................................................................... 10-1

10.2 Chip-Select Module Signals ............................................................................. 10-1

10.3 Chip-Select Operation....................................................................................... 10-2

10.3.1 General Chip-Select Operation..................................................................... 10-3

10.3.1.1 8-, 16-, and 32-Bit Port Sizing.................................................................. 10-4

10.3.1.2 Global Chip-Select Operation................................................................... 10-4

10.4 Chip-Select Registers........................................................................................ 10-5

10.4.1 Chip-Select Module Registers...................................................................... 10-6

10.4.1.1 Chip-Select Address Registers (CSAR0–CSAR7)................................... 10-6

10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)...................................... 10-6

10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7) .................................... 10-8

10.4.1.4 Code Example........................................................................................... 10-9

Chip-Select Module

Chapter 11

Synchronous/Asynchronous DRAM Controller Module

11.1 Overview........................................................................................................... 11-1

11.1.1 Definitions .................................................................................................... 11-2

11.1.2 Block Diagram and Major Components....................................................... 11-2

11.2 DRAM Controller Operation............................................................................ 11-3

11.2.1 DRAM Controller Registers......................................................................... 11-3

11.3 Asynchronous Operation .................................................................................. 11-4

11.3.1 DRAM Controller Signals in Asynchronous Mode...................................... 11-4

11.3.2 Asynchronous Register Set........................................................................... 11-4

11.3.2.1 DRAM Control Register (DCR) in Asynchronous Mode ........................ 11-4

11.3.2.2 DRAM Address and Control Registers (DACR0/DACR1) ..................... 11-5

11.3.2.3 DRAM Controller Mask Registers (DMR0/DMR1) ................................ 11-7

11.3.3 General Asynchronous Operation Guidelines .............................................. 11-8

11.3.3.1 Non-Page-Mode Operation..................................................................... 11-11

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11.3.3.2 Burst Page-Mode Operation ................................................................... 11-12

11.3.3.3 Continuous Page Mode........................................................................... 11-13

11.3.3.4 Extended Data Out (EDO) Operation..................................................... 11-15

11.3.3.5 Refresh Operation................................................................................... 11-16

11.4 Synchronous Operation................................................................................... 11-16

11.4.1 DRAM Controller Signals in Synchronous Mode...................................... 11-17

11.4.2 Using Edge Select (EDGESEL) ................................................................. 11-18

11.4.3 Synchronous Register Set........................................................................... 11-19

11.4.3.1 DRAM Control Register (DCR) in Synchronous Mode.......................... 11-19

11.4.3.2 DRAM Address and Control Registers (DACR0/DACR1)

in Synchronous Mode .........................................................................11-20

11.4.3.3 DRAM Controller Mask Registers (DMR0/DMR1) .............................. 11-22

11.4.4 General Synchronous Operation Guidelines............................................... 11-23

11.4.4.1 Address Multiplexing ............................................................................. 11-23

11.4.4.2 Interfacing Example................................................................................ 11-27

11.4.4.3 Burst Page Mode..................................................................................... 11-27

11.4.4.4 Continuous Page Mode........................................................................... 11-29

11.4.4.5 Auto-Refresh Operation.......................................................................... 11-31

11.4.4.6 Self-Refresh Operation ........................................................................... 11-32

11.4.5 Initialization Sequence................................................................................ 11-33

11.4.5.1 Mode Register Settings........................................................................... 11-33

11.5 SDRAM Example........................................................................................... 11-34

11.5.1 SDRAM Interface Configuration................................................................ 11-35

11.5.2 DCR Initialization....................................................................................... 11-35

11.5.3 DACR Initialization.................................................................................... 11-35

11.5.4 DMR Initialization...................................................................................... 11-37

11.5.5 Mode Register Initialization ....................................................................... 11-38

11.5.6 Initialization Code....................................................................................... 11-39

Title

Page

Number

Part III

Peripheral Module

Chapter 12

DMA Controller Module

12.1 Overview........................................................................................................... 12-1

12.1.1 DMA Module Features................................................................................. 12-2

12.2 DMA Signal Description .................................................................................. 12-2

12.3 DMA Transfer Overview.................................................................................. 12-3

12.4 DMA Controller Module Programming Model................................................ 12-4

12.4.1 Source Address Registers (SAR0–SAR3).................................................... 12-6

12.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 12-7

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12.4.3 Byte Count Registers (BCR0–BCR3)........................................................... 12-7

12.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 12-8

12.4.5 DMA Status Registers (DSR0–DSR3)....................................................... 12-10

12.4.6 DMA Interrupt Vector Registers (DIVR0–DIVR3)................................... 12-11

12.5 DMA Controller Module Functional Description........................................... 12-11

12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)........................... 12-12

12.5.2 Data Transfer Modes .................................................................................. 12-12

12.5.2.1 Dual-Address Transfers.......................................................................... 12-12

12.5.2.2 Single-Address Transfers........................................................................ 12-13

12.5.3 Channel Initialization and Startup .............................................................. 12-13

12.5.3.1 Channel Prioritization............................................................................. 12-13

12.5.3.2 Programming the DMA Controller Module ........................................... 12-13

12.5.4 Data Transfer .............................................................................................. 12-14

12.5.4.1 External Request and Acknowledge Operation...................................... 12-14

12.5.4.2 Auto-Alignment...................................................................................... 12-17

12.5.4.3 Bandwidth Control.................................................................................. 12-18

12.5.5 Termination................................................................................................. 12-18

Title

Page

Number

Chapter 13

Timer Module

13.1 Overview........................................................................................................... 13-1

13.1.1 Key Features................................................................................................. 13-2

13.2 General-Purpose Timer Units........................................................................... 13-2

13.3 General-Purpose Timer Programming Model .................................................. 13-2

13.3.1 Timer Mode Registers (TMR0/TMR1) ........................................................ 13-3

13.3.2 Timer Reference Registers (TRR0/TRR1)................................................... 13-4

13.3.3 Timer Capture Registers (TCR0/TCR1)....................................................... 13-4

13.3.4 Timer Counters (TCN0/TCN1) .................................................................... 13-5

13.3.5 Timer Event Registers (TER0/TER1)........................................................... 13-5

13.4 Code Example................................................................................................... 13-6

13.5 Calculating Time-Out Values........................................................................... 13-7

Chapter 14

UART Modules

14.1 Overview........................................................................................................... 14-1

14.2 Serial Module Overview................................................................................... 14-2

14.3 Register Descriptions........................................................................................ 14-2

14.3.1 UART Mode Registers 1 (UMR1n).............................................................. 14-4

14.3.2 UART Mode Register 2 (UMR2n)............................................................... 14-6

14.3.3 UART Status Registers (USRn) ................................................................... 14-7

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14.3.4 UART Clock-Select Registers (UCSRn)...................................................... 14-8

14.3.5 UART Command Registers (UCRn)............................................................ 14-9

14.3.6 UART Receiver Buffers (URBn) ............................................................... 14-11

14.3.7 UART Transmitter Buffers (UTBn)........................................................... 14-11

14.3.8 UART Input Port Change Registers (UIPCRn).......................................... 14-12

14.3.9 UART Auxiliary Control Register (UACRn)............................................. 14-12

14.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 14-13

14.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)............................ 14-14

14.3.12 UART Interrupt Vector Register (UIVRn)................................................. 14-15

14.3.13 UART Input Port Register (UIPn).............................................................. 14-15

14.3.14 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 14-15

14.4 UART Module Signal Definitions.................................................................. 14-16

14.5 Operation......................................................................................................... 14-18

14.5.1 Transmitter/Receiver Clock Source............................................................ 14-18

14.5.1.1 Programmable Divider............................................................................ 14-18

14.5.1.2 Calculating Baud Rates........................................................................... 14-19

14.5.1.2.1 BCLKO Baud Rates ........................................................................... 14-19

14.5.1.2.2 External Clock .................................................................................... 14-19

14.5.2 Transmitter and Receiver Operating Modes............................................... 14-19

14.5.2.1 Transmitting ........................................................................................... 14-21

14.5.2.2 Receiver .................................................................................................. 14-22

14.5.2.3 FIFO Stack ............................................................................................. 14-24

14.5.3 Looping Modes........................................................................................... 14-25

14.5.3.1 Automatic Echo Mode............................................................................ 14-25

14.5.3.2 Local Loop-Back Mode.......................................................................... 14-25

14.5.3.3 Remote Loop-Back Mode....................................................................... 14-26

14.5.4 Multidrop Mode.......................................................................................... 14-26

14.5.5 Bus Operation............................................................................................. 14-28

14.5.5.1 Read Cycles ............................................................................................ 14-28

14.5.5.2 Write Cycles ........................................................................................... 14-28

14.5.5.3 Interrupt Acknowledge Cycles ............................................................... 14-28

14.5.6 Programming .............................................................................................. 14-28

14.5.6.1 UART Module Initialization Sequence .................................................. 14-29

Title

Page

Number

Chapter 15

Parallel Port (General-Purpose I/O)

15.1 Parallel Port Operation...................................................................................... 15-1

15.1.1 Pin Assignment Register (PAR)................................................................... 15-1

15.1.2 Port A Data Direction Register (PADDR).................................................... 15-2

15.1.3 Port A Data Register (PADAT).................................................................... 15-2

15.1.4 Code Example............................................................................................... 15-3

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Part IV

Hardware Interface

Chapter 16

Mechanical Data

16.1 Package............................................................................................................. 16-1

16.2 Pinout................................................................................................................ 16-1

16.3 Mechanical Diagram......................................................................................... 16-8

16.4 Case Drawing.................................................................................................... 16-9

Chapter 17

Signal Descriptions

17.1 Overview........................................................................................................... 17-1

17.2 MCF5307 Bus Signals...................................................................................... 17-7

17.2.1 Address Bus.................................................................................................. 17-7

17.2.1.1 Address Bus (A[23:0]).............................................................................. 17-7

17.2.1.2 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7

17.2.2 Data Bus (D[31:0]) ....................................................................................... 17-8

17.2.3 Read/Write (R/W

17.2.4 Size (SIZ[1:0]).............................................................................................. 17-8

17.2.5 Transfer Start (TS

17.2.6 Address Strobe (AS)..................................................................................... 17-9

17.2.7 Transfer Acknowledge (T

17.2.8 Transfer In Progress (TIP

17.2.9 Transfer Type (TT[1:0]/PP[1:0])................................................................ 17-10

17.2.10 Transfer Modifier (TM[2:0]/PP[4:2])......................................................... 17-10

17.3 Interrupt Control Signals................................................................................. 17-12

17.3.1 Interrupt Request (IRQ1

17.4 Bus Arbitration Signals................................................................................... 17-12

17.4.1 Bus Request (BR

17.4.2 Bus Grant (BG

17.4.3 Bus Driven (BD)......................................................................................... 17-13

17.5 Clock and Reset Signals.................................................................................. 17-13

17.5.1 Reset In (RSTI

17.5.2 Clock Input (CLKIN).................................................................................. 17-13

17.5.3 Bus Clock Output (BCLKO) ...................................................................... 17-13

17.5.4 Reset Out (RSTO)....................................................................................... 17-13

17.5.5 Data/Configuration Pins (D[7:0])............................................................... 17-13

17.5.5.1 D[7:5Boot Chip-Select (CS0

17.5.5.2 D7—Auto Acknowledge Configuration (AA_CONFIG) ...................... 17-14

)......................................................................................... 17-8

)........................................................................................ 17-9

A)......................................................................... 17-9

/PP7)................................................................... 17-10

/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7)....... 17-12

) ....................................................................................... 17-12

).......................................................................................... 17-12

)........................................................................................... 17-13

) Configuration ......................................... 17-14

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17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0])........................... 17-14

17.5.6 D4—Address Configuration (ADDR_CONFIG)....................................... 17-14

17.5.7 D[3:2]—Frequency Control PLL (FREQ[1:0]..........................................) 17-15

17.5.8 D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])....................... 17-15

17.6 Chip-Select Module Signals ........................................................................... 17-15

17.6.1 Chip-Select (CS[7:0])................................................................................. 17-16

17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16

17.6.3 Output Enable (OE).................................................................................... 17-16

17.7 DRAM Controller Signals .............................................................................. 17-16

17.7.1 Row Address Strobes (RAS[1:0])............................................................... 17-16

17.7.2 Column Address Strobes (CAS[3:0])......................................................... 17-16

17.7.3 DRAM Write (DRAMW)........................................................................... 17-17

17.7.4 Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17

17.7.5 Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17

17.7.6 Synchronous DRAM Clock Enable (SCKE).............................................. 17-17

17.7.7 Synchronous Edge Select (EDGESEL)...................................................... 17-17

17.8 DMA Controller Module Signals.................................................................... 17-17

17.8.1 DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-18

17.9 Serial Module Signals..................................................................................... 17-18

17.9.1 Transmitter Serial Data Output (TxD)........................................................ 17-18

17.9.2 Receiver Serial Data Input (RxD)............................................................... 17-18

17.9.3 Clear to Send (CTS).................................................................................... 17-18

17.9.4 Request to Send (RTS) ............................................................................... 17-18

17.10 Timer Module Signals..................................................................................... 17-18

17.10.1 Timer Inputs (TIN[1:0]).............................................................................. 17-19

17.10.2 Timer Outputs (TOUT1, TOUT0).............................................................. 17-19

17.11 Parallel I/O Port (PP[15:0]) ............................................................................ 17-19

17.12 I2C Module Signals ........................................................................................ 17-19

17.12.1 I2C Serial Clock (SCL)............................................................................... 17-19

17.12.2 I2C Serial Data (SDA)................................................................................ 17-19

17.13 Debug and Test Signals .................................................................................. 17-20

17.13.1 Test Mode (MTMOD[3:0]) ........................................................................ 17-20

17.13.2 High Impedance (HIZ

17.13.3 Processor Clock Output (PSTCLK)............................................................ 17-20

17.13.4 Debug Data (DDATA[3:0])........................................................................ 17-20

17.13.5 Processor Status (PST[3:0])........................................................................ 17-20

17.14 Debug Module/JTAG Signals......................................................................... 17-21

17.14.1 Test Reset/Development Serial Clock (TRST

17.14.2 Test Mode Select/Breakpoint (TMS/BKPT

17.14.3 Test Data Input/Development Serial Input (TDI/DSI)............................... 17-22

17.14.4 Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22

17.14.5 Test Clock (TCK) ....................................................................................... 17-23

Title

)................................................................................ 17-20

/DSCLK) ............................ 17-21

) .............................................. 17-22

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Chapter 18

Bus Operation

18.1 Features............................................................................................................. 18-1

18.2 Bus and Control Signals ................................................................................... 18-1

18.3 Bus Characteristics............................................................................................ 18-2

18.4 Data Transfer Operation ................................................................................... 18-3

18.4.1 Bus Cycle Execution..................................................................................... 18-4

18.4.2 Data Transfer Cycle States ........................................................................... 18-5

18.4.3 Read Cycle.................................................................................................... 18-7

18.4.4 Write Cycle................................................................................................... 18-8

18.4.5 Fast-Termination Cycles............................................................................... 18-9

18.4.6 Back-to-Back Bus Cycles........................................................................... 18-10

18.4.7 Burst Cycles................................................................................................ 18-11

18.4.7.1 Line Transfers......................................................................................... 18-12

18.4.7.2 Line Read Bus Cycles............................................................................. 18-12

18.4.7.3 Line Write Bus Cycles............................................................................ 18-14

18.4.7.4 Transfers Using Mixed Port Sizes .......................................................... 18-15

18.5 Misaligned Operands...................................................................................... 18-16

18.6 Bus Errors ....................................................................................................... 18-17

18.7 Interrupt Exceptions........................................................................................ 18-17

18.7.1 Level 7 Interrupts........................................................................................ 18-18

18.7.2 Interrupt-Acknowledge Cycle..................................................................... 18-19

18.8 Bus Arbitration................................................................................................ 18-20

18.8.1 Bus Arbitration Signals............................................................................... 18-21

18.9 General Operation of External Master Transfers............................................ 18-21

18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire Mode)......................... 18-25

18.9.2 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29

18.10 Reset Operation............................................................................................... 18-33

18.10.1 Master Reset ............................................................................................... 18-34

18.10.2 Software Watchdog Reset........................................................................... 18-35

Chapter 19

IEEE 1149.1 Test Access Port (JTAG)

19.1 Overview........................................................................................................... 19-1

19.2 JTAG Signal Descriptions ............................................................................... 19-2

19.3 TAP Controller.................................................................................................. 19-3

19.4 JTAG Register Descriptions............................................................................. 19-4

19.4.1 JTAG Instruction Shift Register.................................................................. 19-5

19.4.2 IDCODE Register......................................................................................... 19-6

19.4.3 JTAG Boundary-Scan Register .................................................................... 19-7

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19.4.4 JTAG Bypass Register................................................................................ 19-10

19.5 Restrictions ..................................................................................................... 19-10

19.6 Disabling IEEE Standard 1149.1 Operation................................................... 19-11

19.7 Obtaining the IEEE Standard 1149.1.............................................................. 19-12

Title

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Chapter 20

Electrical Specifications

20.1 General Parameters........................................................................................... 20-1

20.2 Clock Timing Specifications............................................................................. 20-2

20.3 Input/Output AC Timing Specifications........................................................... 20-3

20.4 Reset Timing Specifications........................................................................... 20-12

20.5 Debug AC Timing Specifications................................................................... 20-12

20.6 Timer Module AC Timing Specifications ...................................................... 20-14

20.7 I

20.8 UART Module AC Timing Specifications..................................................... 20-16

20.9 Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-18

20.10 DMA Timing Specifications........................................................................... 20-19

20.11 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-20

C Input/Output Timing Specifications......................................................... 20-15

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ILLUSTRATIONS

Figure Number

1-1 MCF5307 Block Diagram.............................................................................................1-2

1-2 UART Module Block Diagram..................................................................................... 1-9

1-3 PLL Module................................................................................................................1-12

1-4 ColdFire MCF5307 Programming Model ..................................................................1-13

2-1 ColdFire Enhanced Pipeline .......................................................................................2-23

2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25

2-3 ColdFire Programming Model....................................................................................2-27

2-5 Status Register (SR)....................................................................................................2-30

2-6 Vector Base Register (VBR)....................................................................................... 2-30

2-7 Organization of Integer Data Formats in Data Registers............................................ 2-32

2-8 Organization of Integer Data Formats in Address Registers...................................... 2-32

2-9 Memory Operand Addressing..................................................................................... 2-33

2-10 Exception Stack Frame Form......................................................................................2-49

3-1 ColdFire MAC Multiplication and Accumulation........................................................3-2

3-2 MAC Programming Model...........................................................................................3-2

4-1 SRAM Base Address Register (RAMBAR).................................................................4-3

4-2 Unified Cache Organization .........................................................................................4-7

4-3 Cache Organization and Line Format...........................................................................4-8

4-4 Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern....................... 4-10

4-5 Caching Operation...................................................................................................... 4-11

4-6 Write-Miss in Copyback Mode................................................................................... 4-16

4-7 Cache Locking............................................................................................................ 4-20

4-8 Cache Control Register (CACR) ................................................................................4-21

4-9 Access Control Register Format (ACRn)................................................................... 4-23

4-10 A

4-11 Cache Line State Diagram—Copyback Mode............................................................ 4-26

4-12 Cache Line State Diagram—Write-Through Mode.................................................... 4-26

5-1 Processor/Debug Module Interface...............................................................................5-1

5-2 PSTCLK Timing...........................................................................................................5-3

5-3 Example JMP Instruction Output on PST/DDATA......................................................5-5

5-4 Debug Programming Model .........................................................................................5-6

5-5 Address Attribute Trigger Register (AATR)................................................................5-7

5-6 Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9

5-7 BDM Address Attribute Register (BAAR)................................................................... 5-9

5-8 Configuration/Status Register (CSR).......................................................................... 5-10

5-9 Data Breakpoint/Mask Registers (DBR and DBMR).................................................5-12

Format ..................................................................................................................4-24

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Figure Number

Title

Page

Number

5-10 Program Counter Breakpoint Register (PBR).............................................................5-14

5-11 Program Counter Breakpoint Mask Register (PBMR)...............................................5-14

5-12 Trigger Definition Register (TDR).............................................................................5-15

5-13 BDM Serial Interface Timing.....................................................................................5-18

5-14 Receive BDM Packet..................................................................................................5-19

5-15 Transmit BDM Packet ................................................................................................ 5-19

5-16 BDM Command Format............................................................................................. 5-21

5-17 Command Sequence Diagram.....................................................................................5-22

5-19 5-18 5-21 5-20 5-23 5-22 5-24 5-25 5-26 5-27 5-28 5-29 5-31 5-30 5-33 5-32 5-35 5-34 5-37 5-36 5-39 5-38 5-41 5-40 5-43 5-42

RAREG/RDREG RAREG/RDREG WAREG/WDREG WAREG/WDREG READ

Command Sequence..........................................................................................5-26

READ

Command/Result Formats................................................................................. 5-26

WRITE WRITE DUMP

Command/Result Formats................................................................................ 5-29

DUMP

Command Sequence ......................................................................................... 5-30

FILL

Command Format................................................................................................5-31

FILL

Command Sequence............................................................................................ 5-32

Command Sequence..............................................................................................5-33

GO Command Format.................................................................................................. 5-33

NOP Command Sequence............................................................................................ 5-34

NOP Command Format................................................................................................5-34

SYNC_PC Command Sequence....................................................................................5-35

SYNC_PC Command Format........................................................................................5-35

RCREG Command Sequence........................................................................................5-36

RCREG Command/Result Formats............................................................................... 5-36

WCREG Command Sequence.......................................................................................5-37

WCREG Command/Result Formats..............................................................................5-37

RDMREG Command Sequence.....................................................................................5-38

RDMREG bdm Command/Result Formats.................................................................... 5-38

WDMREG Command Sequence....................................................................................5-39

WDMREG BDM Command Format.............................................................................. 5-39

Command Sequence............................................................................ 5-24

Command Format ............................................................................... 5-24

Command Sequence..........................................................................5-25

Command Format.............................................................................. 5-25

Command Format............................................................................................ 5-27

Command Sequence ........................................................................................5-28

5-44 Recommended BDM Connector................................................................................. 5-42

6-1 SIM Block Diagram......................................................................................................6-1

6-2 Module Base Address Register (MBAR) .....................................................................6-4

6-3 Reset Status Register (RSR) ......................................................................................... 6-5

6-4 MCF5307 Embedded System Recovery from Unterminated Access........................... 6-7

6-5 System Protection Control Register (SYPCR) .............................................................6-8

6-6 Software Watchdog Interrupt Vector Register (SWIVR).............................................6-9

6-7 Software Watchdog Service Register (SWSR)............................................................. 6-9

6-8 Pin Assignment Register (PAR) ................................................................................. 6-10

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6-9 Default Bus Master Register (MPARK).....................................................................6-11

6-10 Round Robin Arbitration (PARK = 00)...................................................................... 6-12

6-11 Park on Master Core Priority (PARK = 01) ............................................................... 6-13

6-12 Park on DMA Module Priority (PARK = 10)............................................................. 6-13

6-13 Park on Current Master Priority (PARK = 01)...........................................................6-14

7-1 PLL Module Block Diagram ........................................................................................7-1

7-2 PLL Control Register (PLLCR).................................................................................... 7-3

7-3 CLKIN, PCLK, PSTCLK, and BCLKO Timing..........................................................7-5

7-4 Reset and Initialization Timing..................................................................................... 7-6

7-5 PLL Power Supply Filter Circuit..................................................................................7-6

8-1 I 8-2 I

8-3 Repeated START..........................................................................................................8-4

8-4 Synchronized Clock SCL.............................................................................................. 8-5

8-5 I 8-6 I 8-7 I 8-8 I 8-9 I 8-10 Flow-Chart of Typical I

9-1 Interrupt Controller Block Diagram..............................................................................9-1

9-2 Interrupt Control Registers (ICR0–ICR9) ....................................................................9-3

9-3 Autovector Register (AVR)..........................................................................................9-5

9-4 Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR).........................9-7

9-5 Interrupt Port Assignment Register (IRQPAR)............................................................9-7

10-1 Connections for External Memory Port Sizes ............................................................10-4

10-2 Chip Select Address Registers (CSAR0–CSAR7) .....................................................10-6

10-3 Chip Select Mask Registers (CSMRn) .......................................................................10-7

10-4 Chip-Select Control Registers (CSCR0–CSCR7) ......................................................10-8

11-1 Asynchronous/Synchronous DRAM Controller Block Diagram ...............................11-2

11-2 DRAM Control Register (DCR) (Asynchronous Mode)............................................11-5

11-3 DRAM Address and Control Registers (DACR0/DACR1)........................................11-6

11-4 DRAM Controller Mask Registers (DMR0 and DMR1)............................................ 11-7

11-5 Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4) .......................... 11-11

11-6 Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5) .......................... 11-12

11-7 Burst Page-Mode Read Operation (4-3-3-3).............................................................11-13

11-8 Burst Page-Mode Write Operation (4-3-3-3)............................................................ 11-13

11-9 Continuous Page-Mode Operation............................................................................ 11-14

11-10 Write Hit in Continuous Page Mode......................................................................... 11-15

11-11 EDO Read Operation (3-2-2-2) ................................................................................11-15

11-12 DRAM Access Delayed by Refresh .........................................................................11-16

11-13 MCF5307 SDRAM Interface.................................................................................... 11-18

11-14 Using EDGESEL to Change Signal Timing.............................................................11-19

C Module Block Diagram..........................................................................................8-2

C Standard Communication Protocol ........................................................................8-3

C Address Register (IADR).......................................................................................8-6

C Frequency Divider Register (IFDR)....................................................................... 8-7

C Control Register (I2CR).........................................................................................8-8

CR Status Register (I2SR) ......................................................................................... 8-9

C Data I/O Register (I2DR)..................................................................................... 8-10

C Interrupt Routine ............................................................. 8-14

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11-15 DRAM Control Register (DCR) (Synchronous Mode)............................................ 11-19

11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20

11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22

11-18 Burst Read SDRAM Access.....................................................................................11-28

11-19 Burst Write SDRAM Access.................................................................................... 11-29

11-20 Synchronous, Continuous Page-Mode Access—Consecutive Reads.......................11-30

11-21 Synchronous, Continuous Page-Mode Access—Read after Write........................... 11-31

11-22 Auto-Refresh Operation............................................................................................ 11-32

11-23 Self-Refresh Operation ............................................................................................. 11-32

11-24 Mode Register Set (mrs) Command .........................................................................11-34

11-25 Initialization Values for DCR...................................................................................11-35

11-26 SDRAM Configuration.............................................................................................11-36

11-27 DACR Register Configuration.................................................................................. 11-36

11-28 DMR0 Register.........................................................................................................11-37

11-29 Mode Register Mapping to MCF5307 A[31:0]........................................................ 11-38

12-1 DMA Signal Diagram.................................................................................................12-1

12-2 Dual-Address Transfer................................................................................................ 12-3

12-3 Single-Address Transfers............................................................................................ 12-4

12-4 Source Address Registers (SARn)..............................................................................12-6

12-5 Destination Address Registers (DARn)......................................................................12-7

12-6 Byte Count Registers (BCRn)—BCR24BIT = 1........................................................12-7

12-7 BCRn—BCR24BIT = 0..............................................................................................12-8

12-8 DMA Control Registers (DCRn)............................................................................... 12-8

12-9 DMA Status Registers (DSRn)................................................................................12-10

12-10 DMA Interrupt Vector Registers (DIVRn)...............................................................12-11

12-11 DREQ Timing Constraints, Dual-Address DMA Transfer.......................................12-15

12-12 Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer...................12-16

12-13 Single-Address DMA Transfer.................................................................................12-17

13-1 Timer Block Diagram................................................................................................. 13-1

13-2 Timer Mode Registers (TMR0/TMR1) ......................................................................13-3

13-3 Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4

13-4 Timer Capture Register (TCR0/TCR1) ......................................................................13-5

13-5 Timer Counters (TCN0/TCN1)...................................................................................13-5

13-6 Timer Event Registers (TER0/TER1)......................................................................... 13-5

14-1 Simplified Block Diagram..........................................................................................14-1

14-2 UART Mode Registers 1 (UMR1n)............................................................................ 14-5

14-3 UART Mode Register 2 (UMR2n)............................................................................. 14-6

14-4 UART Status Register (USRn)...................................................................................14-7

14-5 UART Clock-Select Register (UCSRn)......................................................................14-8

14-6 UART Command Register (UCRn)............................................................................ 14-9

14-7 UART Receiver Buffer (URB0)...............................................................................14-11

14-8 UART Transmitter Buffer (UTB0)...........................................................................14-12

14-9 UART Input Port Change Register (UIPCRn)..........................................................14-12

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Figure Number

14-10 UART Auxiliary Control Register (UACRn)...........................................................14-13

14-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-13

14-12 UART Divider Upper Register (UDUn)................................................................... 14-14

14-13 UART Divider Lower Register (UDLn)................................................................... 14-14

14-14 UART Interrupt Vector Register (UIVRn)...............................................................14-15

14-15 UART Input Port Register (UIPn)............................................................................14-15

14-17 UART Block Diagram Showing External and Internal Interface Signals................ 14-16

14-16 UART Output Port Command Register (UOP1/UOP0)...........................................14-16

14-18 UART/RS-232 Interface...........................................................................................14-17

14-19 Clocking Source Diagram......................................................................................... 14-18

14-20 Transmitter and Receiver Functional Diagram......................................................... 14-20

14-21 Transmitter Timing Diagram....................................................................................14-22

14-22 Receiver Timing........................................................................................................14-23

14-23 Automatic Echo ........................................................................................................14-25

14-24 Local Loop-Back ......................................................................................................14-26

14-25 Remote Loop-Back...................................................................................................14-26

14-26 Multidrop Mode Timing Diagram............................................................................ 14-27

14-27 UART Mode Programming Flowchart.....................................................................14-30

15-1 Parallel Port Pin Assignment Register (PAR) ............................................................15-1

15-2 Port A Data Direction Register (PADDR).................................................................. 15-2

15-3 Port A Data Register (PADAT)..................................................................................15-3

16-1 Mechanical Diagram...................................................................................................16-9

16-2 MCF5307 Case Drawing (General View) ................................................................ 16-10

16-3 Case Drawing (Details)............................................................................................. 16-11

17-1 MCF5307 Block Diagram with Signal Interfaces ......................................................17-2

18-1 Signal Relationship to BCLKO for Non-DRAM Access........................................... 18-2

18-2 Connections for External Memory Port Sizes ............................................................18-4

18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4

18-4 Data Transfer State Transition Diagram.....................................................................18-6

18-5 Read Cycle Flowchart................................................................................................. 18-7

18-6 Basic Read Bus Cycle.................................................................................................18-8

18-7 Write Cycle Flowchart................................................................................................18-9

18-8 Basic Write Bus Cycle................................................................................................18-9

18-9 Read Cycle with Fast Termination ...........................................................................18-10

18-10 Write Cycle with Fast Termination...........................................................................18-10

18-11 Back-to-Back Bus Cycles......................................................................................... 18-11

18-12 Line Read Burst (2-1-1-1), External Termination ....................................................18-12

18-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13

18-14 Line Read Burst (3-2-2-2), External Termination ....................................................18-13

18-15 Line Read Burst-Inhibited, Fast, External Termination............................................18-14

18-16 Line Write Burst (2-1-1-1), Internal/External Termination......................................18-14

18-17 Line Write Burst (3-2-2-2) with One Wait State, Internal Termination...................18-15

18-18 Line Write Burst-Inhibited, Internal Termination .................................................... 18-15

Title

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ILLUSTRATIONS

Figure Number

18-19 Longword Read from an 8-Bit Port, External Termination......................................18-16

18-20 Longword Read from an 8-Bit Port, Internal Termination.......................................18-16

18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17

18-22 Example of a Misaligned Word Transfer (32-Bit Port)............................................18-17

18-23 Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20

18-24 Basic No-Wait-State External Master Access ..........................................................18-22

18-25 External Master Burst Line Access to 32-Bit Port....................................................18-24

18-26 MCF5307 Two-Wire Mode Bus Arbitration Interface.............................................18-25

18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26

18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27

18-29 MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................18-28

18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30

18-31 Three-Wire Bus Arbitration......................................................................................18-31

18-32 Three-Wire Bus Arbitration Protocol State Diagram ...............................................18-32

18-33 Master Reset Timing................................................................................................. 18-34

18-34 Software Watchdog Reset Timing............................................................................18-36

19-1 JTAG Test Logic Block Diagram...............................................................................19-2

19-2 JTAG TAP Controller State Machine......................................................................... 19-4

19-4 Disabling JTAG in JTAG Mode...............................................................................19-11

19-5 Disabling JTAG in Debug Mode..............................................................................19-11

20-1 Clock Timing.............................................................................................................. 20-3

20-2 PSTCLK Timing.........................................................................................................20-3

20-3 AC Timings—Normal Read and Write Bus Cycles................................................... 20-5

20-4 SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO.............................. 20-6

20-5 SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO............................. 20-7

20-6 SDRAM Read Cycle with EDGESEL Tied High.......................................................20-8

20-7 SDRAM Write Cycle with EDGESEL Tied High...................................................... 20-9

20-8 SDRAM Read Cycle with EDGESEL Tied Low..................................................... 20-10

20-9 SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-11

20-10 AC Output Timing—High Impedance......................................................................20-11

20-11 Reset Timing.............................................................................................................20-12

20-12 Real-Time Trace AC Timing....................................................................................20-13

20-13 BDM Serial Port AC Timing....................................................................................20-13

20-14 Timer Module AC Timing........................................................................................20-14

20-15 I

20-16 UART0/1 Module AC Timing—UART Mode.........................................................20-17

20-17 General-Purpose I/O Timing.....................................................................................20-18

20-18 DMA Timing ............................................................................................................20-19

20-19 IEEE 1149.1 (JTAG) AC Timing.............................................................................20-21

C Input/Output Timings.........................................................................................20-16

Title

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xxiv MCF5307 User’s Manual

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TABLES

Table Number

1-1 User-Level Registers................................................................................................... 1-14

1-2 Supervisor-Level Registers.........................................................................................1-14

2-1 CCR Field Descriptions .............................................................................................2-28

2-2 MOVEC Register Map ...............................................................................................2-29

2-3 Status Field Descriptions ............................................................................................ 2-30

2-4 Integer Data Formats...................................................................................................2-31

2-5 ColdFire Effective Addressing Modes........................................................................2-34

2-6 Notational Conventions ..............................................................................................2-34

2-7 User-Mode Instruction Set Summary ......................................................................... 2-37

2-8 Supervisor-Mode Instruction Set Summary................................................................2-40

2-9 Misaligned Operand References.................................................................................2-41

2-10 Move Byte and Word Execution Times......................................................................2-42

2-11 Move Long Execution Times......................................................................................2-42

2-12 MAC Move Execution Times.....................................................................................2-43

2-13 One-Operand Instruction Execution Times................................................................ 2-43

2-14 Two-Operand Instruction Execution Times................................................................2-44

2-15 Miscellaneous Instruction Execution Times...............................................................2-45

2-16 General Branch Instruction Execution Times............................................................. 2-46

2-17 Bcc Instruction Execution Times................................................................................ 2-47

2-18 Exception Vector Assignments................................................................................... 2-48

2-19 Format Field Encoding ...............................................................................................2-49

2-20 Fault Status Encodings................................................................................................ 2-50

2-21 MCF5307 Exceptions ................................................................................................. 2-50

3-1 MAC Instruction Summary...........................................................................................3-4

3-2 Two-Operand MAC Instruction Execution Times .......................................................3-5

3-3 MAC Move Instruction Execution Times.....................................................................3-6

4-1 RAMBAR Field Description ........................................................................................ 4-3

4-2 Examples of Typical RAMBAR Settings.....................................................................4-6

4-3 Valid and Modified Bit Settings................................................................................... 4-8

4-4 CACR Field Descriptions........................................................................................... 4-21

4-5 ACRn Field Descriptions............................................................................................4-23

4-6 Cache Line State Transitions...................................................................................... 4-27

4-7 Cache Line State Transitions (Current State Invalid).................................................4-28

4-8 Cache Line State Transitions (Current State Valid) ................................................... 4-28

4-9 Cache Line State Transitions (Current State Modified) ............................................. 4-29

5-1 Debug Module Signals.................................................................................................. 5-2

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TABLES

Table Number

5-2 Processor Status Encoding............................................................................................5-4

5-3 BDM/Breakpoint Registers........................................................................................... 5-7

5-4 AATR Field Descriptions............................................................................................. 5-8

5-5 ABLR Field Description...............................................................................................5-9

5-6 ABHR Field Description...............................................................................................5-9

5-7 BAAR Field Descriptions...........................................................................................5-10

5-8 CSR Field Descriptions .............................................................................................. 5-11

5-9 DBR Field Descriptions..............................................................................................5-13

5-10 DBMR Field Descriptions .......................................................................................... 5-13

5-11 Access Size and Operand Data Location....................................................................5-13

5-12 PBR Field Descriptions .............................................................................................. 5-14

5-13 PBMR Field Descriptions...........................................................................................5-14

5-14 TDR Field Descriptions..............................................................................................5-15

5-15 Receive BDM Packet Field Description.....................................................................5-19

5-16 Transmit BDM Packet Field Description ...................................................................5-19

5-17 BDM Command Summary......................................................................................... 5-20

5-18 BDM Field Descriptions.............................................................................................5-21

5-19 Control Register Map.................................................................................................. 5-36

5-20 Definition of DRc Encoding—Read...........................................................................5-38

5-21 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................... 5-40

5-22 PST/DDATA Specification for User-Mode Instructions............................................ 5-43

5-23 PST/DDATA Specification for Supervisor-Mode Instructions..................................5-46

6-1 SIM Registers ..............................................................................................................6-3

6-2 MBAR Field Descriptions ............................................................................................ 6-5

6-3 RSR Field Descriptions ................................................................................................ 6-6

6-4 SYPCR Field Descriptions ...........................................................................................6-8

6-5 PLLIPL Settings ......................................................................................................... 6-10

6-6 MPARK Field Descriptions........................................................................................6-11

7-1 PLLCR Field Descriptions............................................................................................ 7-3

7-2 PLL Module Input SIgnals............................................................................................7-3

7-3 PLL Module Output Signals.........................................................................................7-4

8-1 I 8-2 I

8-3 IFDR Field Descriptions...............................................................................................8-7

8-4 I 8-5 I

9-1 Interrupt Controller Registers....................................................................................... 9-2

9-2 Interrupt Control Registers ...........................................................................................9-2

9-3 ICRn Field Descriptions ...............................................................................................9-3

9-4 Interrupt Priority Scheme.............................................................................................. 9-4

9-5 AVR Field Descriptions................................................................................................ 9-6

9-6 Autovector Register Bit Assignments........................................................................... 9-6

9-7 IPR and IMR Field Descriptions...................................................................................9-7

C Interface Memory Map........................................................................................... 8-6

C Address Register Field Descriptions......................................................................8-6

CR Field Descriptions................................................................................................8-8

SR Field Descriptions ................................................................................................ 8-9

Title

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xxvi MCF5307 User’s Manual

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TABLES

Table Number

9-8 IRQPAR Field Descriptions .........................................................................................9-8

10-1 Chip-Select Module Signals .......................................................................................10-1

10-2 Byte Enables/Byte Write Enable Signal Settings ....................................................... 10-2

10-3 Accesses by Matches in CSCRs and DACRs.............................................................10-3

10-4 D7/AA, Automatic Acknowledge of Boot CS0.......................................................... 10-4

10-5 D[6:5]/PS[1:0], Port Size of Boot CS0.......................................................................10-4

10-6 Chip-Select Registers.................................................................................................. 10-5

10-7 CSARn Field Description........................................................................................... 10-6

10-8 CSMRn Field Descriptions.........................................................................................10-7

10-9 CSCRn Field Descriptions..........................................................................................10-8

11-1 DRAM Controller Registers....................................................................................... 11-3

11-2 SDRAM Signal Summary ......................................................................................... 11-4

11-3 DCR Field Descriptions (Asynchronous Mode)......................................................... 11-5

11-4 DACR0/DACR1 Field Description ............................................................................ 11-6

11-5 DMR0/DMR1 Field Descriptions............................................................................... 11-7

11-6 Generic Address Multiplexing Scheme...................................................................... 11-8

11-7 DRAM Addressing for Byte-Wide Memories..........................................................11-10

11-8 DRAM Addressing for 16-Bit Wide Memories........................................................11-10

11-9 DRAM Addressing for 32-Bit Wide Memories........................................................11-11

11-10 SDRAM Commands.................................................................................................11-17

11-11 Synchronous DRAM Signal Connections ................................................................11-17

11-12 DCR Field Descriptions (Synchronous Mode).........................................................11-19

11-13 DACR0/DACR1 Field Descriptions (Synchronous Mode)......................................11-21

11-14 DMR0/DMR1 Field Descriptions............................................................................. 11-23

11-15 MCF5307 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 11-24

11-16 MCF5307 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 11-24

11-17 MCF5307 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................. 11-24

11-18 MCF5307 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................. 11-24

11-19 MCF5307 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 11-25

11-20 MCF5307 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 11-25

11-21 MCF5307 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)................ 11-25

11-22 MCF5307 to SDRAM Interface (16-Bit Port, 10-Column Address Lines).............. 11-25

11-23 MCF5307 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 11-25

11-24 MCF5307 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 11-26

11-25 MCF5307to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ..............11-26

11-26 MCF5307 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26

11-27 MCF5307 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26

11-28 MCF5307 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 11-26

11-29 MCF5307 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 11-27

11-30 MCF5307 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 11-27

11-31 SDRAM Hardware Connections...............................................................................11-27

11-32 SDRAM Example Specifications .............................................................................11-34

11-33 SDRAM Hardware Connections...............................................................................11-35

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TABLES

Table Number

11-34 DCR Initialization Values......................................................................................... 11-35

11-35 DACR Initialization Values......................................................................................11-36

11-36 DMR0 Initialization Values......................................................................................11-37

11-37 Mode Register Initialization .....................................................................................11-38

12-1 DMA Signals ..............................................................................................................12-2

12-2 Memory Map for DMA Controller Module Registers................................................ 12-5

12-3 DCRn Field Descriptions............................................................................................12-8

12-4 DSRn Field Descriptions .......................................................................................... 12-10

13-1 General-Purpose Timer Module Memory Map .......................................................... 13-3

13-2 TMRn Field Descriptions ...........................................................................................13-4

13-3 TERn Field Descriptions.............................................................................................13-6

13-5 Calculated Time-out Values (90-MHz Processor Clock)........................................... 13-7

14-1 UART Module Programming Model.......................................................................... 14-3

14-2 UMR1n Field Descriptions.........................................................................................14-5

14-3 UMR2n Field Descriptions.........................................................................................14-6

14-4 USRn Field Descriptions ............................................................................................ 14-7

14-5 UCSRn Field Descriptions.......................................................................................... 14-9

14-6 UCRn Field Descriptions............................................................................................14-9

14-7 UIPCRn Field Descriptions ...................................................................................... 14-12

14-8 UACRn Field Descriptions.......................................................................................14-13

14-9 UISRn/UIMRn Field Descriptions ...........................................................................14-14

14-10 UIVRn Field Descriptions ........................................................................................ 14-15

14-11 UIPn Field Descriptions............................................................................................ 14-15

14-12 UOP1/UOP0 Field Descriptions...............................................................................14-16

14-13 UART Module Signals .............................................................................................14-17

14-14 UART Module Initialization Sequence ....................................................................14-29

15-1 Parallel Port Pin Descriptions.....................................................................................15-2

15-2 PADDR Field Description..........................................................................................15-2

15-3 Relationship between PADAT Register and Parallel Port Pin (PP)........................... 15-3

16-1 Pins 1–52 (Left, Top-to-Bottom)................................................................................16-1

16-2 Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3

16-3 Pins 105–156 (Right, Bottom-to-Top)........................................................................16-4

16-4 Pins 157–208 (Top, Right-to-Left)............................................................................. 16-6

16-5 Dimensions ...............................................................................................................16-11

17-1 MCF5307 Signal Index............................................................................................... 17-3

17-2 Data Pin Configuration............................................................................................... 17-6

17-3 Bus Cycle Size Encoding............................................................................................ 17-7

17-4 Bus Cycle Transfer Type Encoding............................................................................17-9

17-5 TM[2:0] Encodings for TT = 00 (Normal Access).....................................................17-9

17-6 TM0 Encoding for DMA as Master (TT = 01)...........................................................17-9

17-7 TM[2:1] Encoding for DMA as Master (TT = 01)................................................... 17-10

17-8 TM[2:0] Encodings for TT = 10 (Emulator Access)................................................ 17-10

17-9 TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-10

Title

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xxviii MCF5307 User’s Manual

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TABLES

Table Number

17-10 Data Pin Configuration............................................................................................. 17-12

17-11 D7 Selection of CS0 Automatic Acknowledge ........................................................17-13

17-12 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-13

17-13 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-13

17-14 CLKIN Frequency ....................................................................................................17-13

17-15 BCLKO/PSTCLK Divide Ratios..............................................................................17-14

17-16 Processor Status Signal Encodings...........................................................................17-19

18-1 ColdFire Bus Signal Summary ................................................................................... 18-1

18-2 Bus Cycle Size Encoding............................................................................................ 18-3

18-3 Accesses by Matches in CSCRs and DACRs.............................................................18-5

18-4 Bus Cycle States .........................................................................................................18-6

18-5 Allowable Line Access Patterns ............................................................................... 18-12

18-6 MCF5307 Arbitration Protocol States...................................................................... 18-20

18-7 ColdFire Bus Arbitration Signal Summary...............................................................18-21

18-8 Cycles for Basic No-Wait-State External Master Access......................................... 18-23

18-9 Cycles for External Master Burst Line Access to 32-Bit Port..................................18-24

18-10 MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions....................18-28

18-11 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32

18-12 Data Pin Configuration............................................................................................. 18-35

19-1 JTAG Pin Descriptions............................................................................................... 19-3

19-2 JTAG Instructions.......................................................................................................19-5

19-3 IDCODE Bit Assignments..........................................................................................19-6

19-4 Boundary-Scan Bit Definitions................................................................................... 19-7

20-1 Absolute Maximum Ratings....................................................................................... 20-1

20-2 Operating Temperatures..............................................................................................20-1

20-3 DC Electrical Specifications.......................................................................................20-2

20-4 Clock Timing Specification........................................................................................20-2

20-5 Input AC Timing Specification................................................................................... 20-3

20-6 Output AC Timing Specification................................................................................20-4

20-7 Reset Timing Specification....................................................................................... 20-12

20-8 Debug AC Timing Specification ..............................................................................20-12

20-9 Timer Module AC Timing Specification..................................................................20-14

20-10 I 20-11 I

20-12 UART Module AC Timing Specifications............................................................... 20-16

20-13 General-Purpose I/O Port AC Timing Specifications............................................... 20-18

20-14 DMA AC Timing Specifications.............................................................................. 20-19

20-15 IEEE 1149.1 (JTAG) AC Timing Specifications .....................................................20-20

A-1 SIM Registers............................................................................................................... A-1

A-2 Interrupt Controller Registers...................................................................................... A-1

A-3 Chip-Select Registers................................................................................................... A-2

A-4 DRAM Controller Registers........................................................................................ A-3

A-5 General-Purpose Timer Registers................................................................................A-4

C Input Timing Specifications between SCL and SDA......................................... 20-15

C Output Timing Specifications between SCL and SDA......................................20-15

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TABLES

Table Number

A-6 UART0 Control Registers............................................................................................ A-4

A-7 UART1 Control Registers............................................................................................ A-6

A-8 Parallel Port Memory Map........................................................................................... A-7

A-9 I

A-10 DMA Controller Registers...........................................................................................A-8

C Interface Memory Map.......................................................................................... A-8

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