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MCF5272
DATA SHEET
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Freescale MCF5272 DATA SHEET

MCF5272 ColdFire® Integrated Microprocessor
ColdFire Microcontrollers
MCF5272UM Rev. 3 03/2007
®
freescale.com
Overview
1
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
System Integration Module (SIM)
Interrupt Controller
Chip-Select Module
SDRAM Controller
DMA Controller Module
Ethernet Module
Universal Serial Bus (USB)
Physical Layer Interface Controller (PLIC)
2
3
4
5
6
7
8
9
10
11
12
13
Queued Serial Peripheral Interface (QSPI) Module
Timer Module
UART Modules
General-Purpose I/O Module
Pulse-Width Modulation (PWM) Module
Signal Descriptions
Bus Operation
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
Appendix A: List of Memory Maps
Appendix B: Buffering and Impedence Matching
14
15
16
17
18
19
20
21
22
23
A
B
Index
IND
1
Overview
2
3
4
5
6
7
8
9
10
11
12
13
ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC)
14
15
16
17
18
19
20
21
22
23
A
B
Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module Pulse-Width Modulation (PWM) Module Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Appendix B: Buffering and Impedence Matching
IND
Index
List of Figures
Figure Page Number Title Number
1-1 MCF5272 Block Diagram........................................................................................................1-2
2-1 ColdFire Pipeline.....................................................................................................................2-2
2-2 ColdFire Multiply-Accumulate Functionality Diagram..............................................................2-3
2-3 ColdFire Programming Model .................................................................................................2-5
2-4 Condition Code Register (CCR)..............................................................................................2-6
2-5 Status Register (SR) ...............................................................................................................2-8
2-6 Vector Base Register (VBR) ...................................................................................................2-8
2-7 Organization of Integer Data Formats in Data Registers...................................................... 2-10
2-8 Organization of Integer Data Formats in Address Registers.................................................2-10
2-9 Memory Operand Addressing ............................................................................................... 2-11
2-10 Exception Stack Frame Form................................................................................................2-27
3-1 ColdFire MAC Multiplication and Accumulation ...................................................................... 3-1
3-2 MAC Programming Model.......................................................................................................3-2
4-1 SRAM Base Address Register (RAMBAR) .............................................................................4-3
4-2 ROM Base Address Register (ROMBAR).............................................................................. 4-5
4-3 Instruction Cache Block Diagram............................................................................................ 4-8
4-4 Cache Control Register (CACR) ...........................................................................................4-12
4-5 Access Control Register Format (ACRn) .............................................................................. 4-14
5-1 Processor/Debug Module Interface.........................................................................................5-1
5-2 PSTCLK Timing ......................................................................................................................5-2
5-3 Example JMP Instruction Output on PST/DDATA .................................................................. 5-5
5-4 Debug Programming Model .................................................................................................... 5-6
5-5 Address Attribute Trigger Register (AATR)............................................................................. 5-7
5-6 Address Breakpoint Registers (ABLR, ABHR)........................................................................ 5-9
5-7 Configuration/Status Register (CSR) .................................................................................... 5-10
5-8 Data Breakpoint/Mask Registers (DBR and DBMR).............................................................5-12
5-9 Program Counter Breakpoint Register (PBR) .......................................................................5-13
5-10 Program Counter Breakpoint Mask Register (PBMR)...........................................................5-13
5-11 Trigger Definition Register (TDR)..........................................................................................5-14
5-12 BDM Serial Interface Timing .................................................................................................5-17
5-13 Receive BDM Packet ............................................................................................................ 5-18
5-14 Transmit BDM Packet ........................................................................................................... 5-18
5-15 BDM Command Format ........................................................................................................5-20
5-16 Command Sequence Diagram..............................................................................................5-21
5-17 5-18 5-19 5-20 5-21 5-22
RAREG/RDREG Command Format ..........................................................................................5-22
RAREG/RDREG Command Sequence......................................................................................5-22
WAREG/WDREG Command Format .........................................................................................5-23
WAREG/WDREG Command Sequence ....................................................................................5-23
READ Command/Result Formats ...........................................................................................5-24
READ Command Sequence ...................................................................................................5-24
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor v
List of Figures (Continued)
Figure Page Number Title Number
5-23 WRITE Command Format.......................................................................................................5-25
5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40
5-41 Recommended BDM Connector ...........................................................................................5-41
6-1 SIM Block Diagram .................................................................................................................6-1
6-2 Module Base Address Register (MBAR).................................................................................6-4
6-3 System Configuration Register (SCR) ....................................................................................6-5
6-4 System Protection Register (SPR).......................................................................................... 6-6
6-5 Power Management Register (PMR) ...................................................................................... 6-7
6-6 Activate Low-Power Register (ALPR) ................................................................................... 6-10
6-7 Device Identification Register (DIR)......................................................................................6-11
6-8 Watchdog Reset Reference Register (WRRR).....................................................................6-12
6-9 Watchdog Interrupt Reference Register (WIRR)...................................................................6-12
6-10 Watchdog Counter Register (WCR)......................................................................................6-13
6-11 Watchdog Event Register (WER)..........................................................................................6-13
7-1 Interrupt Controller Block Diagram.......................................................................................... 7-2
7-2 Interrupt Control Register 1 (ICR1) ......................................................................................... 7-4
7-3 Interrupt Control Register 2 (ICR2) ......................................................................................... 7-5
7-4 Interrupt Control Register 3 (ICR3) ......................................................................................... 7-5
7-5 Interrupt Control Register 4(ICR4) ..........................................................................................7-5
7-6 Interrupt Source Register (ISR)............................................................................................... 7-6
7-7 Programmable Interrupt Transition Register (PITR) ...............................................................7-7
7-8 Programmable Interrupt Wakeup Register (PIWR)................................................................. 7-8
7-9 Programmable Interrupt Vector Register (PIVR).....................................................................7-9
8-1 Chip Select Base Registers (CSBRn).....................................................................................8-3
8-2 Chip Select Option Registers (CSORn) .................................................................................8-5
9-1 SDRAM Controller Signals...................................................................................................... 9-2
9-2 54-Pin TSOP SDRAM Pin Definition....................................................................................... 9-3
9-3 SDRAM Configuration Register (SDCR).................................................................................9-6
WRITE Command Sequence..................................................................................................5-26
DUMP Command/Result Formats..........................................................................................5-27
DUMP Command Sequence...................................................................................................5-27
FILL Command Format .........................................................................................................5-28
FILL Command Sequence......................................................................................................5-29
GO Command Format............................................................................................................5-29
GO Command Sequence.......................................................................................................5-29
NOP Command Format..........................................................................................................5-30
NOP Command Sequence .....................................................................................................5-30
RCREG Command/Result Formats......................................................................................... 5-30
RCREG Command Sequence................................................................................................. 5-31
WCREG Command/Result Formats ........................................................................................5-31
WCREG Command Sequence ................................................................................................5-31
RDMREG BDM Command/Result Formats..............................................................................5-32
RDMREG Command Sequence...............................................................................................5-32
WDMREG BDM Command Format..........................................................................................5-33
WDMREG Command Sequence..............................................................................................5-33
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
vi Freescale Semiconductor
List of Figures (Continued)
Figure Page Number Title Number
9-4 SDRAM Timing Register (SDTR)............................................................................................9-8
9-5 Example Setup Time Violation on SDRAM Data Input during Write.....................................9-12
9-6 Timing Refinement with Inverted SDCLK..............................................................................9-13
9-7 Timing Refinement with True CAS Latency and Inverted SDCLK ........................................ 9-13
9-8 Timing Refinement with Effective CAS Latency....................................................................9-14
9-9 SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1........................................... 9-16
9-10 SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1..............................................9-17
9-11 SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 ...........................................9-18
9-12 SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 ..............................................9-19
9-13 SDRAM Refresh Cycle..........................................................................................................9-20
9-14 Enter SDRAM Self-Refresh Mode.........................................................................................9-21
9-15 Exit SDRAM Self-Refresh Mode ...........................................................................................9-22
10-1 DMA Mode Register (DMR) ..................................................................................................10-2
10-2 DMA Interrupt Register (DIR)................................................................................................10-4
10-3 DMA Source Address Register (DSAR)................................................................................10-5
10-4 DMA Destination Address Register (DDAR).........................................................................10-6
10-5 DMA Byte Count Register (DBCR) .......................................................................................10-6
11-1 Ethernet Block Diagram ........................................................................................................11-2
11-2 Fast Ethernet Module Block Diagram ...................................................................................11-2
11-3 Ethernet Frame Format.........................................................................................................11-4
11-4 Ethernet Address Recognition Flowchart.............................................................................. 11-7
11-5 Ethernet Control Register (ECR).........................................................................................11-11
11-6 Interrupt Event Register (EIR).............................................................................................11-12
11-7 Interrupt Mask Register (EIMR) .........................................................................................11-13
11-8 Interrupt Vector Status Register (IVSR)..............................................................................11-14
11-9 Receive Descriptor Active Register (RDAR).......................................................................11-15
11-10 Transmit Descriptor Active Register (TDAR) ......................................................................11-16
11-11 MII Management Frame Register (MMFR) ......................................................................... 11-17
11-12 MII Speed Control Register (MSCR)..................................................................................11-18
11-13 FIFO Receive Bound Register (FRBR)..............................................................................11-19
11-14 FIFO Receive Start Register (FRSR)................................................................................. 11-20
11-15 Transmit FIFO Watermark (TFWR)....................................................................................11-21
11-16 FIFO Transmit Start Register (TFSR) ................................................................................. 11-22
11-17 Receive Control Register (RCR)......................................................................................... 11-23
11-18 Maximum Frame Length Register (MFLR)..........................................................................11-24
11-19 Transmit Control Register (TCR) ........................................................................................11-25
11-20 RAM Perfect Match Address Low (MALR).......................................................................... 11-26
11-21 RAM Perfect Match Address High (MAUR) ........................................................................11-27
11-22 Hash Table High (HTUR)...................................................................................................11-28
11-23 Hash Table Low (HTLR) ....................................................................................................11-29
11-24 Pointer-to-Receive Descriptor Ring (ERDSR).....................................................................11-30
11-25 Pointer-to-Transmit Descriptor Ring (ETDSR)....................................................................11-31
11-26 Receive Buffer Size (EMRBR) ............................................................................................11-32
11-27 Receive Buffer Descriptor (RxBD) ......................................................................................11-35
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor vii
List of Figures (Continued)
Figure Page Number Title Number
11-28 Transmit Buffer Descriptor (TxBD)..................................................................................... 11-37
12-1 The USB “Tiered Star” Topology...........................................................................................12-2
12-2 USB Module Block Diagram..................................................................................................12-3
12-3 USB Frame Number Register (FNR) ....................................................................................12-9
12-4 USB Frame Number Match Register (FNMR).......................................................................12-9
12-5 USB Real-Time Frame Monitor Register (RFMR)...............................................................12-10
12-6 USB Real-Time Frame Monitor Match Register (RFMMR).................................................12-11
12-7 USB Function Address Register (FAR)............................................................................... 12-11
12-8 USB Alternate Settings Register (ASR) .............................................................................. 12-12
12-9 USB Device Request Data 1 Register (DRR1) ...................................................................12-13
12-10 USB Device Request Data 2 Register (DRR2) ...................................................................12-13
12-11 USB Specification Number Register (SPECR) ...................................................................12-14
12-12 USB Endpoint 0 Status Register (EP0SR)..........................................................................12-14
12-13 USB Endpoint 0 IN Configuration Register (IEP0CFG) ......................................................12-15
12-14 USB Endpoint 0 OUT Configuration Register ..................................................................... 12-16
12-15 USB Endpoint 1–7 Configuration Register..........................................................................12-16
12-16 USB Endpoint 0 Control Register (EP0CTL).......................................................................12-17
12-17 USB Endpoint 1-7 Control Register (EPnCTL) ...................................................................12-20
12-18 USB Endpoint 0 Interrupt Mask (EP0IMR)
and General/Endpoint 0 Interrupt Registers (EP0ISR) .......................................................12-22
12-19 USB Endpoints 1–7 Interrupt Status Registers (EPnISR)...................................................12-25
12-20 USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR) ...................................................... 12-26
12-21 USB Endpoint 0-7 Data Registers (EPnDR) ....................................................................... 12-27
12-22 USB Endpoint 0-7 Data Present Registers (EPnDPR) ....................................................... 12-28
12-23 Example USB Configuration Descriptor Structure .............................................................. 12-29
12-24 Recommended USB Line Interface.....................................................................................12-36
12-25 USB Protection Circuit ........................................................................................................12-37
13-1 PLIC System Diagram...........................................................................................................13-2
13-2 GCI/IDL Receive Data Flow..................................................................................................13-3
13-3 GCI/IDL B-Channel Receive Data Register Demultiplexing..................................................13-4
13-4 GCI/IDL Transmit Data Flow.................................................................................................13-4
13-5 GCI/IDL B Data Transmit Register Multiplexing....................................................................13-5
13-6 B-Channel Unencoded and HDLC Encoded Data................................................................13-6
13-7 D-Channel HDLC Encoded and Unencoded Data................................................................13-7
13-8 D-Channel Contention ..........................................................................................................13-8
13-9 GCI/IDL Loopback Mode ......................................................................................................13-9
13-10 Periodic Frame Interrupt .....................................................................................................13-10
13-11 PLIC Internal Timing Signal Routing...................................................................................13-12
13-12 PLIC Clock Generator.........................................................................................................13-12
13-13 B1 Receive Data Registers P0B1RR–P3B1RR..................................................................13-15
13-14 B2 Receive Data Registers P0B2RR – P3B2RR................................................................13-16
13-15 D Receive Data Registers P0DRR–P3DRR .......................................................................13-16
13-16 B1 Transmit Data Registers P0B1TR–P3B1TR.................................................................. 13-17
13-17 B2 Transmit Data Registers P0B2TR–P3B2TR.................................................................. 13-17
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
viii Freescale Semiconductor
List of Figures (Continued)
Figure Page Number Title Number
13-18 D Transmit Data Registers P0DTR–P3DTR .......................................................................13-18
13-19 Port Configuration Registers (P0CR–P3CR) ......................................................................13-18
13-20 Loopback Control Register (PLCR).....................................................................................13-20
13-21 Interrupt Configuration Registers (P0ICR–P3ICR)..............................................................13-20
13-22 Periodic Status Registers (P0PSR–P3PSR)....................................................................... 13-22
13-23 Aperiodic Status Register (PASR) ......................................................................................13-23
13-24 GCI Monitor Channel Receive Registers (P0GMR–P3GMR) .............................................13-24
13-25 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT).............................................13-25
13-26 GCI Monitor Channel Transmit Abort Register (PGMTA) ...................................................13-26
13-27 GCI Monitor Channel Transmit Status Register (PGMTS)..................................................13-27
13-28 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) ...................................................13-28
13-29 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ................................................... 13-29
13-30 GCI C/I Channel Transmit Status Register (PGCITSR)...................................................... 13-30
13-31 D-Channel Status Register (PDCSR) .................................................................................13-31
13-32 D-Channel Request Registers (PDRQR)............................................................................13-32
13-33 Sync Delay Registers (P0SDR–P3SDR) ............................................................................13-33
13-34 Clock Select Register (PCSR) ............................................................................................13-34
13-35 Port 1 Configuration Register (P1CR)................................................................................. 13-36
13-36 Port 1 Interrupt Configuration Register (P1ICR) .................................................................13-37
13-37 ISDN SOHO PABX Example ..............................................................................................13-38
13-38 Standard IDL2 10-Bit Mode ................................................................................................13-39
13-39 ISDN SOHO PABX Example ..............................................................................................13-40
13-40 Standard IDL2 10-Bit Mode ................................................................................................13-41
13-41 Two-Line Remote Access ...................................................................................................13-41
13-42 Standard IDL2 8-Bit Mode ..................................................................................................13-42
14-1 QSPI Block Diagram .............................................................................................................14-2
14-2 QSPI RAM Model..................................................................................................................14-5
14-3 QSPI Mode Register (QMR) .................................................................................................14-9
14-4 QSPI Clocking and Data Transfer Example........................................................................14-10
14-5 SPI Modes Timing...............................................................................................................14-11
14-6 QSPI Delay Register (QDLYR) ........................................................................................... 14-11
14-7 QSPI Wrap Register (QWR) ...............................................................................................14-12
14-8 QSPI Interrupt Register (QIR).............................................................................................14-13
14-9 QSPI Address Register.......................................................................................................14-14
14-10 QSPI Data Register ............................................................................................................14-14
14-11 Command RAM Registers (QCR0–QCR15).......................................................................14-15
15-1 Timer Block Diagram.............................................................................................................15-2
15-2 Timer Mode Registers (TMR0–TMR3)..................................................................................15-3
15-3 Timer Reference Registers (TRR0–TRR3)...........................................................................15-4
15-4 Timer Capture Registers (TCAP0–TCAP3) ..........................................................................15-4
15-5 Timer Counter (TCN0–TCN3)...............................................................................................15-4
15-6 Timer Event Registers (TER0–TER3)................................................................................... 15-5
16-1 Simplified Block Diagram ...................................................................................................... 16-1
16-2 UART Mode Registers 1 (UMR1n)........................................................................................16-4
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor ix
List of Figures (Continued)
Figure Page Number Title Number
16-3 UART Mode Register 2 (UMR2n) .........................................................................................16-6
16-4 UART Status Registers (USRn)............................................................................................16-7
16-5 UART Clock-Select Registers (UCSRn) ...............................................................................16-8
16-6 UART Command Registers (UCRn) .....................................................................................16-9
16-7 UART Receiver Buffer (URBn)............................................................................................16-10
16-8 UART Transmitter Buffers (UTBn) ......................................................................................16-11
16-9 UART Input Port Change Registers (UIPCRn) ................................................................... 16-11
16-10 UART Auxiliary Control Registers (UACRn) .......................................................................16-12
16-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn).....................................................16-13
16-12 UART Divider Upper Registers (UDUn)..............................................................................16-14
16-13 UART Divider Lower Registers (UDLn)...............................................................................16-14
16-14 UART Autobaud Upper Registers (UABUn)........................................................................16-14
16-15 UART Autobaud Lower Registers (UABLn) ........................................................................ 16-14
16-16 UART Transmitter FIFO Registers (UTFn) .........................................................................16-15
16-17 UART Receiver FIFO Registers (URFn).............................................................................16-16
16-18 UART Fractional Precision Divider Control Registers (UFPDn)..........................................16-17
16-19 UART Input Port Registers (UIPn) ......................................................................................16-17
16-20 UART Output Port Command Registers (UOP1/UOP0) .....................................................16-18
16-21 UART Block Diagram Showing External and Internal Interface Signals............................. 16-18
16-22 UART/RS-232 Interface ......................................................................................................16-19
16-23 Clocking Source Diagram ...................................................................................................16-20
16-24 Transmitter and Receiver Functional Diagram....................................................................16-22
16-25 Transmitter Timing ..............................................................................................................16-23
16-26 Receiver Timing .................................................................................................................. 16-24
16-27 Automatic Echo...................................................................................................................16-27
16-28 Local Loop-Back .................................................................................................................16-27
16-29 Remote Loop-Back .............................................................................................................16-28
16-30 Multidrop Mode Timing Diagram.........................................................................................16-29
16-31 UART Mode Programming Flowchart (Sheet 1 of 5) .......................................................... 16-30
17-1 Port A Control Register (PACNT)..........................................................................................17-3
17-2 Port B Control Register (PBCNT)..........................................................................................17-5
17-3 Port D Control Register (PDCNT) .........................................................................................17-8
17-4 Port A Data Direction Register (PADDR)............................................................................17-10
17-5 Port B Data Direction Register (PBDDR)............................................................................17-10
17-6 Port C Data Direction Register (PCDDR)............................................................................17-11
17-7 Port x Data Register (PADAT, PBDAT, and PCDAT) .........................................................17-11
18-1 PWM Block Diagram (3 Identical Modules)...........................................................................18-1
18-2 PWM Control Registers (PWCRn) ........................................................................................18-3
18-3 PWM Width Register (PWWDn)............................................................................................18-4
18-4 PWM Waveform Examples (PWCRn[EN] = 1)......................................................................18-4
19-1 MCF5272 Block Diagram with Signal Interfaces...................................................................19-2
20-1 Internal Operand Representation..........................................................................................20-5
20-2 MCF5272 Interface to Various Port Sizes............................................................................. 20-5
20-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination................................................20-8
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
x Freescale Semiconductor
List of Figures (Continued)
Figure Page Number Title Number
20-4 Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination................................................. 20-9
20-5 Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination................20-9
20-6 Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination.............. 20-10
20-7 Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................20-10
20-8 Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................ 20-11
20-9 Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State ................20-11
20-10 Longword Read; EBI=11; 32-Bit Port; Internal Termination................................................20-12
20-11 Word Write; EBI=11; 16/32-Bit Port; Internal Termination ..................................................20-13
20-12 Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination.................................20-14
20-13 Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination................ 20-14
20-14 Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination...................................20-15
20-15 Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination.................. 20-15
20-16 Longword Read with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination .........................................................................20-16
20-17 Longword Write with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination .........................................................................20-17
20-18 Example of a Misaligned Longword Transfer......................................................................20-18
20-19 Example of a Misaligned Word Transfer.............................................................................20-18
20-20 Longword Write Access To 32-Bit Port Terminated with TEA Timing................................. 20-20
20-21 Master Reset Timing........................................................................................................... 20-22
20-22 Normal Reset Timing ..........................................................................................................20-23
20-23 Software Watchdog Timer Reset Timing ............................................................................20-24
20-24 Soft Reset Timing ...............................................................................................................20-25
21-1 Test Access Port Block Diagram...........................................................................................21-2
21-2 TAP Controller State Machine...............................................................................................21-3
21-3 Output Cell (O.Cell) (BC–1) ..................................................................................................21-4
21-4 Input Cell (I.Cell). Observe only (BC–4)................................................................................ 21-5
21-5 Output Control Cell (En.Cell) (BC–4) .................................................................................... 21-5
21-6 Bidirectional Cell (IO.Cell) (BC–6).........................................................................................21-6
21-7 General Arrangement for Bidirectional Pins..........................................................................21-6
21-8 Bypass Register....................................................................................................................21-8
22-1 MCF5272 Pinout (196 MAPBGA) .........................................................................................22-1
22-2 196 MAPBGA Package Dimensions (Case No. 1128A-01)..................................................22-2
23-1 Clock Input Timing Diagram..................................................................................................23-5
23-2 General Input Timing Requirements.....................................................................................23-7
23-3 Read/Write SRAM Bus Timing..............................................................................................23-9
23-4 SRAM Bus Cycle Terminated by TA...................................................................................23-10
23-5 SRAM Bus Cycle Terminated by TEA.................................................................................23-11
23-6 Reset and Mode Select/HIZ Configuration Timing.............................................................. 23-12
23-7 Real-Time Trace AC Timing................................................................................................23-13
23-8 BDM Serial Port AC Timing.................................................................................................23-13
23-9 SDRAM Signal Timing ........................................................................................................23-15
23-10 SDRAM Self-Refresh Cycle Timing ....................................................................................23-16
23-11 MII Receive Signal Timing Diagram....................................................................................23-17
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xi
List of Figures (Continued)
Figure Page Number Title Number
23-12 MII Transmit Signal Timing Diagram................................................................................... 23-18
23-13 MII Async Inputs Timing Diagram ....................................................................................... 23-19
23-14 MII Serial Management Channel Timing Diagram .............................................................. 23-20
23-15 Timer Timing .......................................................................................................................23-21
23-16 UART Timing.......................................................................................................................23-22
23-17 IDL Master Timing...............................................................................................................23-23
23-18 IDL Slave Timing.................................................................................................................23-25
23-19 GCI Slave Mode Timing......................................................................................................23-26
23-20 GCI Master Mode Timing....................................................................................................23-27
23-21 General-Purpose I/O Port Timing........................................................................................23-28
23-22 USB Interface Timing..........................................................................................................23-29
23-23 IEEE 1149.1 (JTAG) Timing................................................................................................23-30
23-24 QSPI Timing........................................................................................................................23-31
23-25 PWM Timing........................................................................................................................23-32
B-1 Buffering and Termination.......................................................................................................B-2
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xii Freescale Semiconductor
Table of Contents
Paragraph Page Number Title Number
Chapter 1
Overview
1.1 MCF5272 Key Features ................................................................................................................. 1-1
1.2 MCF5272 Architecture .................................................................................................................. 1-4
1.2.1 Version 2 ColdFire Core ..................................................................................................... 1-4
1.2.2 System Integration Module (SIM) ...................................................................................... 1-5
1.2.2.1 External Bus Interface .......................................................................................... 1-5
1.2.2.2 Chip Select and Wait State Generation ................................................................. 1-5
1.2.2.3 System Configuration and Protection ...................................................................1-5
1.2.2.4 Power Management .............................................................................................. 1-6
1.2.2.5 Parallel Input/Output Ports ................................................................................... 1-6
1.2.2.6 Interrupt Inputs ..................................................................................................... 1-6
1.2.3 UART Module .................................................................................................................... 1-6
1.2.4 Timer Module .....................................................................................................................1-7
1.2.5 Test Access Port ................................................................................................................. 1-7
1.3 System Design .............................................................................................................................. 1-7
1.3.1 System Bus Configuration ..................................................................................................1-7
1.4 MCF5272-Specific Features .......................................................................................................... 1-7
1.4.1 Physical Layer Interface Controller (PLIC) ....................................................................... 1-7
1.4.2 Pulse-Width Modulation (PWM) Unit ............................................................................... 1-8
1.4.3 Queued Serial Peripheral Interface (QSPI) ........................................................................ 1-8
1.4.4 Universal Serial Bus (USB) Module .................................................................................. 1-8
Chapter 2
ColdFire Core
2.1 Features and Enhancements ........................................................................................................... 2-1
2.1.1 Decoupled Pipelines ........................................................................................................... 2-1
2.1.1.1 Instruction Fetch Pipeline (IFP) ............................................................................ 2-2
2.1.1.2 Operand Execution Pipeline (OEP) ...................................................................... 2-2
2.1.1.2.1 Illegal Opcode Handling.............................................................................. 2-3
2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit.............................................. 2-3
2.1.1.2.3 Hardware Divide Unit.................................................................................. 2-4
2.1.2 Debug Module Enhancements ............................................................................................ 2-4
2.2 Programming Model ...................................................................................................................... 2-4
2.2.1 User Programming Model .................................................................................................. 2-4
2.2.1.1 Data Registers (D0–D7) ....................................................................................... 2-5
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2.2.1.2 Address Registers (A0–A6) .................................................................................. 2-5
2.2.1.3 Stack Pointer (A7, SP) .......................................................................................... 2-5
2.2.1.4 Program Counter (PC) .......................................................................................... 2-6
2.2.1.5 Condition Code Register (CCR) ...........................................................................2-6
2.2.1.6 MAC Programming Model ................................................................................... 2-7
2.2.2 Supervisor Programming Model ........................................................................................ 2-7
2.2.2.1 Status Register (SR) ..............................................................................................2-8
2.2.2.2 Vector Base Register (VBR) ................................................................................. 2-8
2.2.2.3 Cache Control Register (CACR) .......................................................................... 2-9
2.2.2.4 Access Control Registers (ACR0–ACR1) ............................................................ 2-9
2.2.2.5 ROM Base Address Register (ROMBAR) ........................................................... 2-9
2.2.2.6 RAM Base Address Register (RAMBAR) ........................................................... 2-9
2.2.2.7 Module Base Address Register (MBAR) ............................................................. 2-9
2.3 Integer Data Formats ..................................................................................................................... 2-9
2.4 Organization of Data in Registers ................................................................................................2-10
2.4.1 Organization of Integer Data Formats in Registers .......................................................... 2-10
2.4.2 Organization of Integer Data Formats in Memory ........................................................... 2-11
2.5 Addressing Mode Summary ........................................................................................................ 2-12
2.6 Instruction Set Summary ............................................................................................................. 2-13
2.6.1 Instruction Set Summary .................................................................................................. 2-15
2.7 Instruction Timing ........................................................................................................................2-19
2.7.1 MOVE Instruction Execution Times ................................................................................2-20
2.7.2 Execution Timings—One-Operand Instructions .............................................................. 2-22
2.7.3 Execution Timings—Two-Operand Instructions ..............................................................2-22
2.7.4 Miscellaneous Instruction Execution Times .....................................................................2-24
2.7.5 Branch Instruction Execution Times ................................................................................ 2-25
2.8 Exception Processing Overview .................................................................................................. 2-25
2.8.1 Exception Stack Frame Definition ................................................................................... 2-27
2.8.2 Processor Exceptions ........................................................................................................ 2-28
Chapter 3
Hardware Multiply/Accumulate (MAC) Unit
3.1 Overview ........................................................................................................................................ 3-1
3.1.1 MAC Programming Model ................................................................................................. 3-2
3.1.2 General Operation .............................................................................................................. 3-3
3.1.3 MAC Instruction Set Summary .......................................................................................... 3-4
3.1.4 Data Representation ............................................................................................................ 3-4
3.2 MAC Instruction Execution Timings ............................................................................................. 3-4
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Chapter 4
Local Memory
4.1 Interactions between Local Memory Modules .............................................................................. 4-1
4.2 Local Memory Registers ................................................................................................................ 4-2
4.3 SRAM Overview ........................................................................................................................... 4-2
4.3.1 SRAM Operation ................................................................................................................4-2
4.3.2 SRAM Programming Model .............................................................................................. 4-2
4.3.2.1 SRAM Base Address Register (RAMBAR) ......................................................... 4-3
4.3.2.2 SRAM Initialization ............................................................................................. 4-4
4.3.2.3 Programming RAMBAR for Power Management ............................................... 4-4
4.4 ROM Overview .............................................................................................................................. 4-5
4.4.1 ROM Operation .................................................................................................................. 4-5
4.4.2 ROM Programming Model ................................................................................................. 4-5
4.4.2.1 ROM Base Address Register (ROMBAR) ........................................................... 4-5
4.4.2.2 Programming ROMBAR for Power Management ............................................... 4-6
4.5 Instruction Cache Overview .......................................................................................................... 4-7
4.5.1 Instruction Cache Physical Organization ........................................................................... 4-7
4.5.2 Instruction Cache Operation ...............................................................................................4-8
4.5.2.1 Interaction with Other Modules ............................................................................ 4-8
4.5.2.2 Cache Coherency and Invalidation ....................................................................... 4-8
4.5.2.3 Caching Modes ..................................................................................................... 4-9
4.5.2.3.1 Cacheable Accesses ..................................................................................... 4-9
4.5.2.3.2 Cache-Inhibited Accesses............................................................................ 4-9
4.5.2.4 Reset ...................................................................................................................4-10
4.5.2.5 Cache Miss Fetch Algorithm/Line Fills ............................................................. 4-10
4.5.3 Instruction Cache Programming Model ........................................................................... 4-12
4.5.3.1 Cache Control Register (CACR) ........................................................................ 4-12
4.5.3.2 Access Control Registers (ACR0 and ACR1) .................................................... 4-14
Chapter 5
Debug Support
5.1 Overview ........................................................................................................................................ 5-1
5.2 Signal Description .......................................................................................................................... 5-2
5.3 Real-Time Trace Support ...............................................................................................................5-3
5.3.1 Begin Execution of Taken Branch (PST = 0x5) ................................................................. 5-4
5.4 Programming Model ...................................................................................................................... 5-5
5.4.1 Revision A Shared Debug Resources .................................................................................5-7
5.4.2 Address Attribute Trigger Register (AATR) ...................................................................... 5-7
5.4.3 Address Breakpoint Registers (ABLR, ABHR) ................................................................. 5-9
5.4.4 Configuration/Status Register (CSR) ............................................................................... 5-10
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5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR) ............................................................ 5-12
5.4.6 Program Counter Breakpoint/Mask Registers
(PBR, PBMR) ............................................................................................................................ 5-13
5.4.7 Trigger Definition Register (TDR) ................................................................................... 5-14
5.5 Background Debug Mode (BDM) ............................................................................................... 5-15
5.5.1 CPU Halt .......................................................................................................................... 5-16
5.5.2 BDM Serial Interface ....................................................................................................... 5-17
5.5.2.1 Receive Packet Format ....................................................................................... 5-18
5.5.2.2 Transmit Packet Format ......................................................................................5-18
5.5.3 BDM Command Set ......................................................................................................... 5-19
5.5.3.1 ColdFire BDM Command Format ...................................................................... 5-20
5.5.3.1.1 Extension Words as Required.................................................................... 5-20
5.5.3.2 Command Sequence Diagrams ........................................................................... 5-21
5.5.3.3 Command Set Descriptions ................................................................................ 5-22
5.5.3.3.1 Read A/D Register (RAREG/RDREG)...........................................................5-22
5.5.3.3.2 Write A/D Register (WAREG/WDREG)........................................................ 5-23
5.5.3.3.3 Read Memory Location (READ)................................................................. 5-24
5.5.3.3.4 Write Memory Location (WRITE)............................................................... 5-25
5.5.3.3.5 Dump Memory Block (DUMP) ................................................................... 5-27
5.5.3.3.6 Fill Memory Block (FILL) .......................................................................... 5-28
5.5.3.3.7 Resume Execution (GO) ............................................................................. 5-29
5.5.3.3.8 No Operation (NOP).................................................................................... 5-30
5.5.3.3.9 Read Control Register (RCREG).................................................................. 5-30
5.5.3.3.10 Write Control Register (WCREG)..............................................................5-31
5.5.3.3.11 Read Debug Module Register (RDMREG).................................................5-32
5.5.3.3.12 Write Debug Module Register (WDMREG)............................................... 5-33
5.6 Real-Time Debug Support ........................................................................................................... 5-33
5.6.1 Theory of Operation .......................................................................................................... 5-34
5.6.1.1 Emulator Mode ................................................................................................... 5-35
5.6.2 Concurrent BDM and Processor Operation ...................................................................... 5-35
5.7 Processor Status, DDATA Definition ........................................................................................... 5-36
5.7.1 User Instruction Set .......................................................................................................... 5-36
5.7.2 Supervisor Instruction Set ................................................................................................5-40
5.8 Freescale-Recommended BDM Pinout ....................................................................................... 5-41
Chapter 6
System Integration Module (SIM)
6.1 Features .......................................................................................................................................... 6-1
6.2 Programming Model ...................................................................................................................... 6-2
6.2.1 SIM Register Memory Map ................................................................................................ 6-2
6.2.2 Module Base Address Register (MBAR) ........................................................................... 6-3
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6.2.3 System Configuration Register (SCR) ............................................................................... 6-5
6.2.4 System Protection Register (SPR) ...................................................................................... 6-6
6.2.5 Power Management Register (PMR) .................................................................................. 6-7
6.2.6 Activate Low-Power Register (ALPR) ............................................................................ 6-10
6.2.7 Device Identification Register (DIR) ............................................................................... 6-11
6.2.8 Software Watchdog Timer ................................................................................................ 6-11
6.2.8.1 Watchdog Reset Reference Register (WRRR) ................................................... 6-12
6.2.8.2 Watchdog Interrupt Reference Register (WIRR) ................................................6-12
6.2.8.3 Watchdog Counter Register (WCR) ................................................................... 6-13
6.2.8.4 Watchdog Event Register (WER) .......................................................................6-13
Chapter 7
Interrupt Controller
7.1 Overview ........................................................................................................................................ 7-1
7.2 Interrupt Controller Registers ........................................................................................................ 7-2
7.2.1 Interrupt Controller Registers .............................................................................................7-3
7.2.2 Interrupt Control Registers (ICR1–ICR4) .......................................................................... 7-4
7.2.2.1 Interrupt Control Register 1 (ICR1) ..................................................................... 7-4
7.2.2.2 Interrupt Control Register 2 (ICR2) ..................................................................... 7-5
7.2.2.3 Interrupt Control Register 3 (ICR3) ..................................................................... 7-5
7.2.2.4 Interrupt Control Register 4 (ICR4) ..................................................................... 7-5
7.2.3 Interrupt Source Register (ISR) ..........................................................................................7-6
7.2.4 Programmable Interrupt Transition Register (PITR) .......................................................... 7-7
7.2.5 Programmable Interrupt Wakeup Register (PIWR) ............................................................7-8
7.2.6 Programmable Interrupt Vector Register (PIVR) ............................................................... 7-9
Chapter 8
Chip Select Module
8.1 Overview ........................................................................................................................................ 8-1
8.1.1 Features ............................................................................................................................... 8-1
8.1.2 Chip Select Usage ............................................................................................................... 8-1
8.1.3 Boot CS0 Operation ........................................................................................................... 8-2
8.2 Chip Select Registers ..................................................................................................................... 8-2
8.2.1 Chip Select Base Registers (CSBR0–CSBR7) ................................................................... 8-3
8.2.2 Chip Select Option Registers (CSOR0–CSOR7) ............................................................... 8-5
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Chapter 9
SDRAM Controller
9.1 Overview ........................................................................................................................................ 9-1
9.2 SDRAM Controller Signals ........................................................................................................... 9-1
9.3 Interface to SDRAM Devices ........................................................................................................ 9-4
9.4 SDRAM Banks, Page Hits, and Page Misses ................................................................................ 9-6
9.5 SDRAM Registers ......................................................................................................................... 9-6
9.5.1 SDRAM Configuration Register (SDCR) .......................................................................... 9-6
9.5.2 SDRAM Timing Register (SDTR) ..................................................................................... 9-8
9.6 Auto Initialization .......................................................................................................................... 9-9
9.7 Power-Down and Self-Refresh ...................................................................................................... 9-9
9.8 Performance ................................................................................................................................. 9-10
9.9 Solving Timing Issues with SDCR[INV] .................................................................................... 9-12
9.10 SDRAM Interface ...................................................................................................................... 9-14
9.10.1 SDRAM Read Accesses ................................................................................................. 9-15
9.10.2 SDRAM Write Accesses ................................................................................................9-18
9.10.3 SDRAM Refresh Timing ................................................................................................9-20
Chapter 10
DMA Controller
10.1 DMA Data Transfer Types ......................................................................................................... 10-1
10.2 DMA Address Modes ................................................................................................................ 10-2
10.3 DMA Controller Registers ......................................................................................................... 10-2
10.3.1 DMA Mode Register (DMR) ......................................................................................... 10-2
10.3.2 DMA Interrupt Register (DIR) .......................................................................................10-4
10.3.3 DMA Source Address Register (DSAR) ........................................................................ 10-5
10.3.4 DMA Destination Address Register (DDAR) ................................................................ 10-6
10.3.5 DMA Byte Count Register (DBCR) ............................................................................... 10-6
Chapter 11
Ethernet Module
11.1 Overview .................................................................................................................................... 11-1
11.1.1 Features ........................................................................................................................... 11-1
11.2 Module Operation ...................................................................................................................... 11-1
11.3 Transceiver Connection ............................................................................................................. 11-3
11.4 FEC Frame Transmission ........................................................................................................... 11-4
11.4.1 FEC Frame Reception .................................................................................................... 11-5
11.4.2 CAM Interface ................................................................................................................11-6
11.4.3 Ethernet Address Recognition ........................................................................................ 11-6
11.4.4 Hash Table Algorithm ..................................................................................................... 11-8
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11.4.5 Interpacket Gap Time ..................................................................................................... 11-8
11.4.6 Collision Handling ..........................................................................................................11-8
11.4.7 Internal and External Loopback ..................................................................................... 11-8
11.4.8 Ethernet Error-Handling Procedure ................................................................................ 11-9
11.4.8.1 Transmission Errors .......................................................................................... 11-9
11.4.8.2 Reception Errors ............................................................................................... 11-9
11.5 Programming Model ................................................................................................................ 11-10
11.5.1 Ethernet Control Register (ECR) ...................................................................................11-11
11.5.2 Interrupt Event Register (EIR) ..................................................................................... 11-12
11.5.3 Interrupt Mask Register (EIMR) .................................................................................. 11-13
11.5.4 Interrupt Vector Status Register (IVSR) ....................................................................... 11-14
11.5.5 Receive Descriptor Active Register (RDAR) ............................................................... 11-15
11.5.6 Transmit Descriptor Active Register (TDAR) ............................................................. 11-16
11.5.7 MII Management Frame Register (MMFR) ................................................................. 11-17
11.5.8 MII Speed Control Register (MSCR) ........................................................................... 11-18
11.5.9 FIFO Receive Bound Register (FRBR) ........................................................................ 11-19
11.5.10 FIFO Receive Start Register (FRSR) ......................................................................... 11-20
11.5.11 Transmit FIFO Watermark (TFWR) ........................................................................... 11-21
11.5.12 FIFO Transmit Start Register (TFSR) ........................................................................ 11-22
11.5.13 Receive Control Register (RCR) ................................................................................ 11-23
11.5.14 Maximum Frame Length Register (MFLR) ............................................................... 11-24
11.5.15 Transmit Control Register (TCR) ............................................................................... 11-25
11.5.16 RAM Perfect Match Address Low (MALR) .............................................................. 11-26
11.5.16.1 RAM Perfect Match Address High (MAUR) ............................................... 11-27
11.5.17 Hash Table High (HTUR) ........................................................................................... 11-28
11.5.18 Hash Table Low (HTLR) ............................................................................................ 11-29
11.5.19 Pointer-to-Receive Descriptor Ring (ERDSR) ........................................................... 11-30
11.5.20 Pointer-to-Transmit Descriptor Ring (ETDSR) .......................................................... 11-31
11.5.21 Receive Buffer Size Register (EMRBR) .................................................................... 11-32
11.5.22 Initialization Sequence ............................................................................................... 11-33
11.5.22.1 Hardware Initialization ................................................................................. 11-33
11.5.23 User Initialization (Prior to Asserting ETHER_EN) .................................................. 11-33
11.5.24 FEC Initialization ....................................................................................................... 11-34
11.5.24.1 User Initialization (after setting ETHER_EN) .............................................. 11-34
11.6 Buffer Descriptors .................................................................................................................... 11-34
11.6.1 FEC Buffer Descriptor Tables ...................................................................................... 11-35
11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD) .................................................. 11-35
11.6.1.2 Ethernet Transmit Buffer Descriptor .............................................................. 11-37
11.7 Differences between MCF5272 FEC and MPC860T FEC ...................................................... 11-39
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Chapter 12
Universal Serial Bus (USB)
12.1 Introduction ................................................................................................................................ 12-1
12.2 Module Operation ...................................................................................................................... 12-2
12.2.1 USB Module Architecture .............................................................................................. 12-2
12.2.1.1 USB Transceiver Interface ................................................................................12-3
12.2.1.2 Clock Generator ................................................................................................ 12-4
12.2.1.3 USB Control Logic ........................................................................................... 12-4
12.2.1.4 Endpoint Controllers ......................................................................................... 12-5
12.2.1.5 USB Request Processor .................................................................................... 12-5
12.3 Register Description and Programming Model ......................................................................... 12-7
12.3.1 USB Memory Map ......................................................................................................... 12-7
12.3.2 Register Descriptions ......................................................................................................12-9
12.3.2.1 USB Frame Number Register (FNR) ............................................................... 12-9
12.3.2.2 USB Frame Number Match Register (FNMR) ................................................. 12-9
12.3.2.3 USB Real-Time Frame Monitor Register (RFMR) ........................................ 12-10
12.3.2.4 USB Real-Time Frame Monitor Match Register (RFMMR) ......................... 12-11
12.3.2.5 USB Function Address Register (FAR) .......................................................... 12-11
12.3.2.6 USB Alternate Settings Register (ASR) ......................................................... 12-12
12.3.2.7 USB Device Request Data 1 and 2 Registers (DRR1/ 2) ............................... 12-13
12.3.2.8 USB Specification Number Register (SPECR) .............................................. 12-14
12.3.2.9 USB Endpoint 0 Status Register (EP0SR) ...................................................... 12-14
12.3.2.10 USB Endpoint 0 IN Configuration Register (IEP0CFG) ............................. 12-15
12.3.2.11 USB Endpoint 0 OUT Configuration Register (OEP0CFG) ........................12-16
12.3.2.12 USB Endpoint 1–7 Configuration Register (EPnCFG) ................................ 12-16
12.3.2.13 USB Endpoint 0 Control Register (EP0CTL) .............................................. 12-17
12.3.2.14 USB Endpoint 1–7 Control Register (EPnCTL) .......................................... 12-20
12.3.2.15 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0 Interrupt
Registers (EP0ISR) .......................................................................................................... 12-22
12.3.2.16 USB Endpoints 1–7 Status / Interrupt Registers (EPnISR) .......................... 12-25
12.3.2.17 USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR) ............................. 12-26
12.3.2.18 USB Endpoint 0–7 Data Registers (EPnDR) ................................................ 12-27
12.3.2.19 USB Endpoint 0–7 Data Present Registers (EPnDPR) ................................. 12-28
12.3.3 Configuration RAM ...................................................................................................... 12-28
12.3.3.1 Configuration RAM Content .......................................................................... 12-28
12.3.3.2 USB Device Configuration Example .............................................................. 12-29
12.3.4 USB Module Access Times .......................................................................................... 12-30
12.3.4.1 Registers ......................................................................................................... 12-30
12.3.4.2 Endpoint FIFOs .............................................................................................. 12-30
12.3.4.3 Configuration RAM ........................................................................................ 12-30
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12.4 Software Architecture and Application Notes ......................................................................... 12-31
12.4.1 USB Module Initialization ........................................................................................... 12-31
12.4.2 USB Configuration and Interface Changes .................................................................. 12-31
12.4.3 FIFO Configuration ...................................................................................................... 12-32
12.4.4 Data Flow ..................................................................................................................... 12-32
12.4.4.1 Control, Bulk, and Interrupt Endpoints .......................................................... 12-33
12.4.4.1.1 IN Endpoints .......................................................................................... 12-33
12.4.4.1.2 OUT Endpoints ...................................................................................... 12-33
12.4.4.2 Isochronous Endpoints .................................................................................... 12-33
12.4.4.2.1 IN Endpoints .......................................................................................... 12-34
12.4.4.2.2 OUT Endpoints ...................................................................................... 12-34
12.4.5 Class- and Vendor-Specific Request Operation ............................................................ 12-34
12.4.6 remote wakeup and resume Operation ......................................................................... 12-35
12.4.7 Endpoint Halt Feature ................................................................................................... 12-35
12.5 Line Interface ........................................................................................................................... 12-36
12.5.1 Attachment Detection ................................................................................................... 12-36
12.5.2 PCB Layout Recommendations ................................................................................... 12-36
12.5.3 Recommended USB Protection Circuit ........................................................................12-37
Chapter 13
Physical Layer Interface Controller (PLIC)
13.1 Introduction ................................................................................................................................ 13-1
13.2 GCI/IDL Block .......................................................................................................................... 13-3
13.2.1 GCI/IDL B- and D-Channel Receive Data Registers .....................................................13-3
13.2.2 GCI/IDL B- and D-Channel Transmit Data Registers ................................................... 13-4
13.2.3 GCI/IDL B- and D-Channel Bit Alignment ................................................................... 13-5
13.2.3.1 B-Channel Unencoded Data ............................................................................. 13-5
13.2.3.2 B-Channel HDLC Encoded Data ...................................................................... 13-6
13.2.3.3 D-Channel HDLC Encoded Data ..................................................................... 13-6
13.2.3.4 D-Channel Unencoded Data ............................................................................. 13-7
13.2.3.5 GCI/IDL D-Channel Contention ..................................................................... 13-8
13.2.4 GCI/IDL Looping Modes ............................................................................................... 13-8
13.2.4.1 Automatic Echo Mode ...................................................................................... 13-9
13.2.4.2 Local Loopback Mode ...................................................................................... 13-9
13.2.4.3 Remote Loopback Mode ................................................................................... 13-9
13.2.5 GCI/IDL Interrupts ......................................................................................................... 13-9
13.2.5.1 GCI/IDL Periodic Frame Interrupt ................................................................... 13-9
13.2.5.2 GCI Aperiodic Status Interrupt ...................................................................... 13-10
13.2.5.3 Interrupt Control ............................................................................................. 13-11
13.3 PLIC Timing Generator ........................................................................................................... 13-11
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13.3.1 Clock Synthesis ............................................................................................................ 13-11
13.3.2 Super Frame Sync Generation ......................................................................................13-13
13.3.3 Frame Sync Synthesis ................................................................................................... 13-13
13.4 PLIC Register Memory Map ................................................................................................... 13-13
13.5 PLIC Registers ......................................................................................................................... 13-15
13.5.1 B1 Data Receive Registers (P0B1RR–P3B1RR) ......................................................... 13-15
13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR) ......................................................... 13-16
13.5.3 D Data Receive Registers (P0DRR–P3DRR) .............................................................. 13-16
13.5.4 B1 Data Transmit Registers (P0B1TR–P3B1TR) ......................................................... 13-17
13.5.5 B2 Data Transmit Registers (P0B2TR–P3B2TR) ........................................................13-17
13.5.6 D Data Transmit Registers (P0DTR–P3DTR) ............................................................. 13-18
13.5.7 Port Configuration Registers (P0CR–P3CR) ............................................................... 13-18
13.5.8 Loopback Control Register (PLCR) .............................................................................13-20
13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR) ..................................................... 13-20
13.5.10 Periodic Status Registers (P0PSR–P3PSR) ................................................................13-22
13.5.11 Aperiodic Status Register (PASR) ..............................................................................13-23
13.5.12 GCI Monitor Channel Receive Registers (P0GMR–P3GMR) ...................................13-24
13.5.13 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT) .................................. 13-25
13.5.14 GCI Monitor Channel Transmit Abort Register (PGMTA) ....................................... 13-26
13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS) ....................................... 13-27
13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) ..........................................13-28
13.5.17 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ......................................... 13-29
13.5.18 GCI C/I Channel Transmit Status Register (PGCITSR) ............................................ 13-30
13.5.19 D-Channel Status Register (PDCSR) ......................................................................... 13-31
13.5.20 D-Channel Request Register (PDRQR) ..................................................................... 13-32
13.5.21 Sync Delay Registers (P0SDR–P3SDR) .................................................................... 13-33
13.5.22 Clock Select Register (PCSR) .................................................................................... 13-34
13.6 Application Examples .............................................................................................................. 13-35
13.6.1 Introduction .................................................................................................................. 13-35
13.6.2 PLIC Initialization ........................................................................................................ 13-35
13.6.2.1 Port Configuration Example ........................................................................... 13-35
13.6.2.2 Interrupt Configuration Example .................................................................... 13-37
13.6.3 Example 1: ISDN SOHO PBX with Ports 0, 1, 2, and 3 .............................................. 13-38
13.6.4 Example 2: ISDN SOHO PBX with Ports 1, 2, and 3 .................................................. 13-40
13.6.5 Example 3: Two-Line Remote Access with Ports 0 and 1 ........................................... 13-41
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Chapter 14
Queued Serial Peripheral Interface (QSPI) Module
14.1 Overview .................................................................................................................................... 14-1
14.2 Features ...................................................................................................................................... 14-1
14.3 Module Description ................................................................................................................... 14-1
14.3.1 Interface and Pins ........................................................................................................... 14-3
14.3.2 Internal Bus Interface ..................................................................................................... 14-3
14.4 Operation ................................................................................................................................... 14-3
14.4.1 QSPI RAM ..................................................................................................................... 14-4
14.4.1.1 Receive RAM ................................................................................................... 14-5
14.4.1.2 Transmit RAM ..................................................................................................14-6
14.4.1.3 Command RAM ............................................................................................... 14-6
14.4.2 Baud Rate Selection ....................................................................................................... 14-6
14.4.3 Transfer Delays ...............................................................................................................14-7
14.4.4 Transfer Length ..............................................................................................................14-8
14.4.5 Data Transfer .................................................................................................................. 14-8
14.5 Programming Model .................................................................................................................. 14-9
14.5.1 QSPI Mode Register (QMR) .......................................................................................... 14-9
14.5.2 QSPI Delay Register (QDLYR) ................................................................................... 14-11
14.5.3 QSPI Wrap Register (QWR) ........................................................................................ 14-12
14.5.4 QSPI Interrupt Register (QIR) ...................................................................................... 14-13
14.5.5 QSPI Address Register (QAR) ..................................................................................... 14-14
14.5.6 QSPI Data Register (QDR) .......................................................................................... 14-14
14.5.7 Command RAM Registers (QCR0–QCR15) ............................................................... 14-15
14.5.8 Programming Example ................................................................................................. 14-16
Chapter 15
Timer Module
15.1 Overview .................................................................................................................................... 15-1
15.2 Timer Operation .........................................................................................................................15-1
15.3 General-Purpose Timer Registers .............................................................................................. 15-3
15.3.1 Timer Mode Registers (TMR0–TMR3) ..........................................................................15-3
15.3.2 Timer Reference Registers (TRR0–TRR3) .................................................................... 15-4
15.3.3 Timer Capture Registers (TCAP0–TCAP3) ...................................................................15-4
15.3.4 Timer Counters (TCN0–TCN3) .....................................................................................15-4
15.3.5 Timer Event Registers (TER0–TER3) ...........................................................................15-5
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Chapter 16
UART Modules
16.1 Overview .................................................................................................................................... 16-1
16.2 Serial Module Overview ............................................................................................................ 16-2
16.3 Register Descriptions ................................................................................................................. 16-2
16.3.1 UART Mode Registers 1 (UMR1n) ............................................................................... 16-4
16.3.2 UART Mode Register 2 (UMR2n) ................................................................................. 16-6
16.3.3 UART Status Registers (USRn) ..................................................................................... 16-7
16.3.4 UART Clock-Select Registers (UCSRn) ........................................................................16-8
16.3.5 UART Command Registers (UCRn) .............................................................................. 16-9
16.3.6 UART Receiver Buffers (URBn) ................................................................................. 16-10
16.3.7 UART Transmitter Buffers (UTBn) ............................................................................. 16-11
16.3.8 UART Input Port Change Registers (UIPCRn) ............................................................ 16-11
16.3.9 UART Auxiliary Control Registers (UACRn) ............................................................. 16-12
16.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) ..........................................16-12
16.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn) ............................................ 16-14
16.3.12 UART Autobaud Registers (UABUn/UABLn) .......................................................... 16-14
16.3.13 UART Transmitter FIFO Registers (UTFn) ............................................................... 16-15
16.3.14 UART Receiver FIFO Registers (URFn) ................................................................... 16-16
16.3.15 UART Fractional Precision Divider Control Registers (UFPDn) .............................. 16-17
16.3.16 UART Input Port Registers (UIPn) ............................................................................ 16-17
16.3.17 UART Output Port Command Registers (UOP1n/UOP0n) ....................................... 16-18
16.4 UART Module Signal Definitions ........................................................................................... 16-18
16.5 Operation ................................................................................................................................. 16-19
16.5.1 Transmitter/Receiver Clock Source .............................................................................. 16-19
16.5.1.1 Programmable Divider .................................................................................... 16-20
16.5.1.2 Calculating Baud Rates ................................................................................... 16-20
16.5.1.2.1 CLKIN Baud Rates................................................................................ 16-20
16.5.1.2.2 External Clock........................................................................................ 16-21
16.5.1.2.3 Autobaud Detection ............................................................................... 16-21
16.5.2 Transmitter and Receiver Operating Modes .................................................................16-22
16.5.2.1 Transmitting ................................................................................................... 16-22
16.5.2.2 Receiver .......................................................................................................... 16-24
16.5.2.3 Transmitter FIFO ............................................................................................ 16-25
16.5.2.4 Receiver FIFO ............................................................................................... 16-25
16.5.3 Looping Modes ............................................................................................................. 16-26
16.5.3.1 Automatic Echo Mode .................................................................................... 16-27
16.5.3.2 Local Loop-Back Mode .................................................................................. 16-27
16.5.3.3 Remote Loop-Back Mode ............................................................................... 16-27
16.5.4 Multidrop Mode ............................................................................................................ 16-28
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16.5.5 Bus Operation ............................................................................................................... 16-29
16.5.5.1 Read Cycles .................................................................................................... 16-29
16.5.5.2 Write Cycles ...................................................................................................16-29
16.5.5.3 Interrupt Acknowledge Cycles ....................................................................... 16-29
16.5.6 Programming ................................................................................................................ 16-30
16.5.6.1 UART Module Initialization Sequence .......................................................... 16-30
Chapter 17
General Purpose I/O Module
17.1 Overview .................................................................................................................................... 17-1
17.2 Port Control Registers ................................................................................................................ 17-2
17.2.1 Port A Control Register (PACNT) ..................................................................................17-3
17.2.2 Port B Control Register (PBCNT) .................................................................................. 17-5
17.2.3 Port C Control Register .................................................................................................. 17-8
17.2.4 Port D Control Register (PDCNT) ................................................................................. 17-8
17.3 Data Direction Registers .......................................................................................................... 17-10
17.3.1 Port A Data Direction Register (PADDR) .................................................................... 17-10
17.3.2 Port B Data Direction Register (PBDDR) .................................................................... 17-10
17.3.3 Port C Data Direction Register (PCDDR) .................................................................... 17-11
17.4 Port Data Registers .................................................................................................................. 17-11
17.4.1 Port Data Register (PxDAT) ......................................................................................... 17-11
Chapter 18
Pulse-Width Modulation (PWM) Module
18.1 Overview .................................................................................................................................... 18-1
18.2 PWM Operation ......................................................................................................................... 18-2
18.3 PWM Programming Model ....................................................................................................... 18-2
18.3.1 PWM Control Register (PWCRn) .................................................................................. 18-3
18.3.2 PWM Width Register (PWWDn) ................................................................................... 18-4
Chapter 19
Signal Descriptions
19.1 MCF5272 Block Diagram with Signal Interfaces ..................................................................... 19-1
19.2 Signal List .................................................................................................................................. 19-3
19.3 Address Bus (A[22:0]/SDA[13:0]) .......................................................................................... 19-19
19.4 Data Bus (D[31:0]) .................................................................................................................. 19-19
19.4.1 Dynamic Data Bus Sizing ............................................................................................ 19-19
19.5 Chip Selects (CS7/SDCS, CS[6:0]) ......................................................................................... 19-19
19.6 Bus Control Signals ................................................................................................................. 19-20
19.6.1 Output Enable/Read (OE/RD) ......................................................................................19-20
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19.6.2 Byte Strobes (BS[3:0]) ................................................................................................. 19-20
19.6.3 Read/Write (R/W) .........................................................................................................19-21
19.6.4 Transfer Acknowledge (TA/PB5) ................................................................................. 19-22
19.6.5 Hi-Z .............................................................................................................................. 19-22
19.6.6 Bypass ........................................................................................................................... 19-22
19.6.7 SDRAM Row Address Strobe (RAS0) ........................................................................ 19-22
19.6.8 SDRAM Column Address Strobe (CAS0) ................................................................... 19-22
19.6.9 SDRAM Clock (SDCLK) ............................................................................................. 19-22
19.6.10 SDRAM Write Enable (SDWE) ................................................................................. 19-22
19.6.11 SDRAM Clock Enable (SDCLKE) ............................................................................ 19-22
19.6.12 SDRAM Bank Selects (SDBA[1:0]) .......................................................................... 19-23
19.6.13 SDRAM Row Address 10 (A10)/A10 Precharge (A10_PRECHG) .......................... 19-23
19.7 CPU Clock and Reset Signals ..................................................................................................19-23
19.7.1 RSTI ............................................................................................................................. 19-23
19.7.2 DRESETEN .................................................................................................................. 19-23
19.7.3 CPU External Clock (CLKIN) ..................................................................................... 19-23
19.7.4 Reset Output (RSTO) ................................................................................................... 19-23
19.8 Interrupt Request Inputs (INT[6:1]) ......................................................................................... 19-23
19.9 General-Purpose I/O (GPIO) Ports .......................................................................................... 19-24
19.10 UART0 Module Signals and PB[4:0] .................................................................................... 19-24
19.10.1 Transmit Serial Data Output (URT0_TxD/PB0) ........................................................ 19-24
19.10.2 Receive Serial Data Input (URT0_RxD/PB1) ............................................................ 19-25
19.10.3 Clear-to-Send (URT0_CTS/PB2) ............................................................................... 19-25
19.10.4 Request to Send (URT0_RTS/PB3) ............................................................................ 19-25
19.10.5 Clock (URT0_CLK/PB4) ........................................................................................... 19-25
19.11 USB Module Signals and PA[6:0] ......................................................................................... 19-25
19.11.1 USB Transmit Serial Data Output (USB_TP/PA0) .................................................... 19-25
19.11.2 USB Receive Serial Data Input (USB_RP/PA1) ........................................................ 19-25
19.11.3 USB Receive Data Negative (USB_RN/PA2) ............................................................19-25
19.11.4 USB Transmit Data Negative (USB_TN/PA3) ........................................................... 19-26
19.11.5 USB Suspend Driver (USB_SUSP/PA4) .................................................................... 19-26
19.11.6 USB Transmitter Output Enable (USB_TxEN/PA5) ..................................................19-26
19.11.7 USB Rx Data Output (USB_RxD/PA6) ..................................................................... 19-26
19.11.8 USB_D+ and USB_D- ................................................................................................19-26
19.11.9 USB_CLK ..................................................................................................................19-26
19.11.10 INT1/USB Wake-on-Ring (USB_WOR) ................................................................. 19-26
19.12 Timer Module Signals ............................................................................................................19-27
19.12.1 Timer Input 0 (TIN0) .................................................................................................. 19-27
19.12.2 Timer Output (TOUT0)/PB7 ...................................................................................... 19-27
19.12.3 Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2) .................................... 19-27
19.12.4 Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1) .............................. 19-27
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19.13 Ethernet Module Signals ........................................................................................................ 19-27
19.13.1 Transmit Clock (E_TxCLK) ....................................................................................... 19-27
19.13.2 Transmit Data (E_TxD0) ............................................................................................19-28
19.13.3 Collision (E_COL) ..................................................................................................... 19-28
19.13.4 Receive Data Valid (E_RxDV) ................................................................................... 19-28
19.13.5 Receive Clock (E_RxCLK) ........................................................................................ 19-28
19.13.6 Receive Data (E_RxD0) ............................................................................................. 19-28
19.13.7 Transmit Enable (E_TxEN) ........................................................................................19-28
19.13.8 Transmit Data (E_TxD[3:1]/PB[10:8]) ...................................................................... 19-28
19.13.9 Receive Data (E_RxD[3:1]/PB[13:11]) ......................................................................19-28
19.13.10 Receive Error (E_RxER/PB14) ................................................................................ 19-29
19.13.11 Management Data Clock (E_MDC/PB15) ............................................................... 19-29
19.13.12 Management Data (E_MDIO) .................................................................................. 19-29
19.13.13 Transmit Error (E_TxER) .........................................................................................19-29
19.13.14 Carrier Receive Sense (E_CRS) ............................................................................... 19-29
19.14 PWM Module Signals (PWM_OUT0–PWM_OUT2]) ......................................................... 19-29
19.15 Queued Serial Peripheral Interface (QSPI) Signals ............................................................... 19-29
19.15.1 QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL) .................................... 19-30
19.15.2 QSPI Synchronous Serial Data Input (QSPI_Din) ..................................................... 19-30
19.15.3 QSPI Serial Clock (QSPI_CLK/BUSW1) .................................................................. 19-30
19.15.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0) ................................... 19-30
19.15.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................................ 19-30
19.15.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............................. 19-30
19.15.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3) ............................ 19-30
19.16 Physical Layer Interface Controller TDM Ports and UART 1 .............................................. 19-31
19.16.1 GCI/IDL TDM Port 0. ................................................................................................ 19-31
19.16.1.1 Frame Sync (FSR0/FSC0/PA8) .................................................................... 19-31
19.16.1.2 D-Channel Grant (DGNT0/PA9) .................................................................. 19-31
19.16.1.3 Data Clock (DCL0/URT1_CLK) .................................................................. 19-31
19.16.1.4 Serial Data Input (DIN0/URT1_RxD) ..........................................................19-31
19.16.1.5 UART1 CTS (URT1_CTS/QSPI_CS2) ........................................................ 19-32
19.16.1.6 UART1 RTS (URT1_RTS
19.16.1.7 Serial Data Output (DOUT0/URT1_TxD) ................................................... 19-32
19.16.1.8 D-Channel Request(DREQ0/PA10) .............................................................19-32
19.16.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11) ........................................................ 19-32
19.16.2 GCI/IDL TDM Port 1 ................................................................................................. 19-32
19.16.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT) ............................................... 19-32
19.16.2.2 GCI/IDL Data Out (DOUT1) ....................................................................... 19-33
19.16.2.3 GCI/IDL Data In (DIN1) .............................................................................. 19-33
19.16.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ............................................... 19-33
19.16.2.5 D-Channel Request (DREQ1/PA14) ............................................................19-33
/INT5) ................................................................. 19-32
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19.16.2.6 D-Channel Grant (DGNT1_INT6/PA15_INT6) ...........................................19-33
19.16.3 GCI/IDL TDM Ports 2 and 3 ...................................................................................... 19-34
19.16.3.1 GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) .........................................19-34
19.16.3.2 GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13) .........................................19-34
19.16.3.3 QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7 (PA7/DOUT3/QSPI_CS3) ... 19-34
19.16.3.4 INT4 and Port 3 GCI/IDL Data In (INT4/DIN3) ......................................... 19-35
19.17 JTAG Test Access Port and BDM Debug Port ...................................................................... 19-35
19.17.1 Test Clock (TCK/PSTCLK) ........................................................................................ 19-35
19.17.2 Test Mode Select and Force Breakpoint (TMS/BKPT) ..............................................19-35
19.17.3 Test and Debug Data Out (TDO/DSO) ...................................................................... 19-36
19.17.4 Test and Debug Data In (TDI/DSI) ............................................................................ 19-36
19.17.5 JTAG TRST and BDM Data Clock (TRST/DSCLK) ................................................ 19-36
19.17.6 Freescale Test Mode Select (MTMOD) ..................................................................... 19-36
19.17.7 Debug Transfer Error Acknowledge (TEA) ...............................................................19-36
19.17.8 Processor Status Outputs (PST[3:0]) ..........................................................................19-36
19.17.9 Debug Data (DDATA[3:0]) ........................................................................................ 19-37
19.17.10 Device Test Enable (TEST) ......................................................................................19-37
19.18 Operating Mode Configuration Pins ......................................................................................19-37
19.19 Power Supply Pins ................................................................................................................. 19-38
Chapter 20
Bus Operation
20.1 Features ...................................................................................................................................... 20-1
20.2 Bus and Control Signals ............................................................................................................ 20-1
20.2.1 Address Bus (A[22:0]) ................................................................................................... 20-2
20.2.2 Data Bus (D[31:0]) ......................................................................................................... 20-2
20.2.3 Read/Write (R/W) ...........................................................................................................20-2
20.2.4 Transfer Acknowledge (TA) ........................................................................................... 20-2
20.2.5 Transfer Error Acknowledge (TEA) ............................................................................... 20-3
20.3 Bus Exception: Double Bus Fault .............................................................................................. 20-3
20.4 Bus Characteristics .................................................................................................................... 20-3
20.5 Data Transfer Mechanism ..........................................................................................................20-4
20.5.1 Bus Sizing ....................................................................................................................... 20-4
20.6 External Bus Interface Types ..................................................................................................... 20-7
20.6.1 Interface for FLASH/SRAM Devices with Byte Strobes ............................................... 20-8
20.6.2 Interface for FLASH/SRAM Devices without Byte Strobes ........................................20-12
20.7 Burst Data Transfers ................................................................................................................ 20-17
20.8 Misaligned Operands ............................................................................................................... 20-18
20.9 Interrupt Cycles ........................................................................................................................ 20-19
20.10 Bus Errors .............................................................................................................................. 20-19
20.11 Bus Arbitration .......................................................................................................................20-21
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20.12 Reset Operation ...................................................................................................................... 20-21
20.12.1 Master Reset ............................................................................................................... 20-22
20.12.2 Normal Reset .............................................................................................................. 20-23
20.12.3 Software Watchdog Timer Reset Operation ............................................................... 20-24
20.12.4 Soft Reset Operation ................................................................................................... 20-25
Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
21.1 Overview .................................................................................................................................... 21-1
21.2 JTAG Test Access Port and BDM Debug Port .......................................................................... 21-2
21.3 TAP Controller ........................................................................................................................... 21-3
21.4 Boundary Scan Register ............................................................................................................. 21-4
21.5 Instruction Register ....................................................................................................................21-7
21.6 Restrictions ................................................................................................................................ 21-8
21.7 Non-IEEE 1149.1 Operation ......................................................................................................21-8
Chapter 22
Mechanical Data
22.1 Pinout ......................................................................................................................................... 22-1
22.2 Package Dimensions .................................................................................................................. 22-2
Chapter 23
Electrical Characteristics
23.1 Maximum Ratings ...................................................................................................................... 23-1
23.1.1 Supply, Input Voltage, and Storage Temperature ........................................................... 23-1
23.1.2 Operating Temperature ...................................................................................................23-2
23.1.3 Resistance .......................................................................................................................23-2
23.2 DC Electrical Specifications ...................................................................................................... 23-3
23.2.1 Output Driver Capability and Loading ...........................................................................23-3
23.3 AC Electrical Specifications ...................................................................................................... 23-5
23.3.1 Clock Input and Output Timing Specifications .............................................................. 23-5
23.3.2 Processor Bus Input Timing Specifications ....................................................................23-6
23.3.3 Processor Bus Output Timing Specifications .................................................................23-8
23.4 Debug AC Timing Specifications ............................................................................................ 23-13
23.5 SDRAM Interface Timing Specifications ................................................................................ 23-14
23.6 Fast Ethernet AC Timing Specifications ................................................................................. 23-17
23.6.1 MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER, and E_RxCLK) ........ 23-17
23.6.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER, E_TxCLK) .............. 23-18
23.6.3 MII Async Inputs Signal Timing (CRS and COL) .......................................................23-19
23.6.4 MII Serial Management Channel Timing (MDIO and MDC) ..................................... 23-20
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23.7 Timer Module AC Timing Specifications ................................................................................23-21
23.8 UART Modules AC Timing Specifications ............................................................................. 23-22
23.9 PLIC Module: IDL and GCI Interface Timing Specifications ................................................23-23
23.10 General-Purpose I/O Port AC Timing Specifications ............................................................23-28
23.11 USB Interface AC Timing Specifications ..............................................................................23-29
23.12 IEEE 1149.1 (JTAG) AC Timing Specifications ................................................................... 23-30
23.13 QSPI Electrical Specifications ............................................................................................... 23-31
23.14 PWM Electrical Specifications .............................................................................................. 23-32
Appendix A
List of Memory Maps
A.1 List of Memory Map Tables............................................................................................................ A-1
Appendix B
Buffering and Impedance Matching
Index 1
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
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