How it Works
Freescale
Loading...
MCF5272
DATA SHEET
544 pgs6.44 Mb0
Table of contents
Loading...

Freescale MCF5272 DATA SHEET

Download
MCF5272 ColdFire® Integrated Microprocessor
ColdFire Microcontrollers
MCF5272UM Rev. 3 03/2007
®
freescale.com
Overview
1
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
System Integration Module (SIM)
Interrupt Controller
Chip-Select Module
SDRAM Controller
DMA Controller Module
Ethernet Module
Universal Serial Bus (USB)
Physical Layer Interface Controller (PLIC)
2
3
4
5
6
7
8
9
10
11
12
13
Queued Serial Peripheral Interface (QSPI) Module
Timer Module
UART Modules
General-Purpose I/O Module
Pulse-Width Modulation (PWM) Module
Signal Descriptions
Bus Operation
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
Appendix A: List of Memory Maps
Appendix B: Buffering and Impedence Matching
14
15
16
17
18
19
20
21
22
23
A
B
Index
IND
1
Overview
2
3
4
5
6
7
8
9
10
11
12
13
ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC)
14
15
16
17
18
19
20
21
22
23
A
B
Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module Pulse-Width Modulation (PWM) Module Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Appendix B: Buffering and Impedence Matching
IND
Index
List of Figures
Figure Page Number Title Number
1-1 MCF5272 Block Diagram........................................................................................................1-2
2-1 ColdFire Pipeline.....................................................................................................................2-2
2-2 ColdFire Multiply-Accumulate Functionality Diagram..............................................................2-3
2-3 ColdFire Programming Model .................................................................................................2-5
2-4 Condition Code Register (CCR)..............................................................................................2-6
2-5 Status Register (SR) ...............................................................................................................2-8
2-6 Vector Base Register (VBR) ...................................................................................................2-8
2-7 Organization of Integer Data Formats in Data Registers...................................................... 2-10
2-8 Organization of Integer Data Formats in Address Registers.................................................2-10
2-9 Memory Operand Addressing ............................................................................................... 2-11
2-10 Exception Stack Frame Form................................................................................................2-27
3-1 ColdFire MAC Multiplication and Accumulation ...................................................................... 3-1
3-2 MAC Programming Model.......................................................................................................3-2
4-1 SRAM Base Address Register (RAMBAR) .............................................................................4-3
4-2 ROM Base Address Register (ROMBAR).............................................................................. 4-5
4-3 Instruction Cache Block Diagram............................................................................................ 4-8
4-4 Cache Control Register (CACR) ...........................................................................................4-12
4-5 Access Control Register Format (ACRn) .............................................................................. 4-14
5-1 Processor/Debug Module Interface.........................................................................................5-1
5-2 PSTCLK Timing ......................................................................................................................5-2
5-3 Example JMP Instruction Output on PST/DDATA .................................................................. 5-5
5-4 Debug Programming Model .................................................................................................... 5-6
5-5 Address Attribute Trigger Register (AATR)............................................................................. 5-7
5-6 Address Breakpoint Registers (ABLR, ABHR)........................................................................ 5-9
5-7 Configuration/Status Register (CSR) .................................................................................... 5-10
5-8 Data Breakpoint/Mask Registers (DBR and DBMR).............................................................5-12
5-9 Program Counter Breakpoint Register (PBR) .......................................................................5-13
5-10 Program Counter Breakpoint Mask Register (PBMR)...........................................................5-13
5-11 Trigger Definition Register (TDR)..........................................................................................5-14
5-12 BDM Serial Interface Timing .................................................................................................5-17
5-13 Receive BDM Packet ............................................................................................................ 5-18
5-14 Transmit BDM Packet ........................................................................................................... 5-18
5-15 BDM Command Format ........................................................................................................5-20
5-16 Command Sequence Diagram..............................................................................................5-21
5-17 5-18 5-19 5-20 5-21 5-22
RAREG/RDREG Command Format ..........................................................................................5-22
RAREG/RDREG Command Sequence......................................................................................5-22
WAREG/WDREG Command Format .........................................................................................5-23
WAREG/WDREG Command Sequence ....................................................................................5-23
READ Command/Result Formats ...........................................................................................5-24
READ Command Sequence ...................................................................................................5-24
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor v
List of Figures (Continued)
Figure Page Number Title Number
5-23 WRITE Command Format.......................................................................................................5-25
5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40
5-41 Recommended BDM Connector ...........................................................................................5-41
6-1 SIM Block Diagram .................................................................................................................6-1
6-2 Module Base Address Register (MBAR).................................................................................6-4
6-3 System Configuration Register (SCR) ....................................................................................6-5
6-4 System Protection Register (SPR).......................................................................................... 6-6
6-5 Power Management Register (PMR) ...................................................................................... 6-7
6-6 Activate Low-Power Register (ALPR) ................................................................................... 6-10
6-7 Device Identification Register (DIR)......................................................................................6-11
6-8 Watchdog Reset Reference Register (WRRR).....................................................................6-12
6-9 Watchdog Interrupt Reference Register (WIRR)...................................................................6-12
6-10 Watchdog Counter Register (WCR)......................................................................................6-13
6-11 Watchdog Event Register (WER)..........................................................................................6-13
7-1 Interrupt Controller Block Diagram.......................................................................................... 7-2
7-2 Interrupt Control Register 1 (ICR1) ......................................................................................... 7-4
7-3 Interrupt Control Register 2 (ICR2) ......................................................................................... 7-5
7-4 Interrupt Control Register 3 (ICR3) ......................................................................................... 7-5
7-5 Interrupt Control Register 4(ICR4) ..........................................................................................7-5
7-6 Interrupt Source Register (ISR)............................................................................................... 7-6
7-7 Programmable Interrupt Transition Register (PITR) ...............................................................7-7
7-8 Programmable Interrupt Wakeup Register (PIWR)................................................................. 7-8
7-9 Programmable Interrupt Vector Register (PIVR).....................................................................7-9
8-1 Chip Select Base Registers (CSBRn).....................................................................................8-3
8-2 Chip Select Option Registers (CSORn) .................................................................................8-5
9-1 SDRAM Controller Signals...................................................................................................... 9-2
9-2 54-Pin TSOP SDRAM Pin Definition....................................................................................... 9-3
9-3 SDRAM Configuration Register (SDCR).................................................................................9-6
WRITE Command Sequence..................................................................................................5-26
DUMP Command/Result Formats..........................................................................................5-27
DUMP Command Sequence...................................................................................................5-27
FILL Command Format .........................................................................................................5-28
FILL Command Sequence......................................................................................................5-29
GO Command Format............................................................................................................5-29
GO Command Sequence.......................................................................................................5-29
NOP Command Format..........................................................................................................5-30
NOP Command Sequence .....................................................................................................5-30
RCREG Command/Result Formats......................................................................................... 5-30
RCREG Command Sequence................................................................................................. 5-31
WCREG Command/Result Formats ........................................................................................5-31
WCREG Command Sequence ................................................................................................5-31
RDMREG BDM Command/Result Formats..............................................................................5-32
RDMREG Command Sequence...............................................................................................5-32
WDMREG BDM Command Format..........................................................................................5-33
WDMREG Command Sequence..............................................................................................5-33
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
vi Freescale Semiconductor
List of Figures (Continued)
Figure Page Number Title Number
9-4 SDRAM Timing Register (SDTR)............................................................................................9-8
9-5 Example Setup Time Violation on SDRAM Data Input during Write.....................................9-12
9-6 Timing Refinement with Inverted SDCLK..............................................................................9-13
9-7 Timing Refinement with True CAS Latency and Inverted SDCLK ........................................ 9-13
9-8 Timing Refinement with Effective CAS Latency....................................................................9-14
9-9 SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1........................................... 9-16
9-10 SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1..............................................9-17
9-11 SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 ...........................................9-18
9-12 SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 ..............................................9-19
9-13 SDRAM Refresh Cycle..........................................................................................................9-20
9-14 Enter SDRAM Self-Refresh Mode.........................................................................................9-21
9-15 Exit SDRAM Self-Refresh Mode ...........................................................................................9-22
10-1 DMA Mode Register (DMR) ..................................................................................................10-2
10-2 DMA Interrupt Register (DIR)................................................................................................10-4
10-3 DMA Source Address Register (DSAR)................................................................................10-5
10-4 DMA Destination Address Register (DDAR).........................................................................10-6
10-5 DMA Byte Count Register (DBCR) .......................................................................................10-6
11-1 Ethernet Block Diagram ........................................................................................................11-2
11-2 Fast Ethernet Module Block Diagram ...................................................................................11-2
11-3 Ethernet Frame Format.........................................................................................................11-4
11-4 Ethernet Address Recognition Flowchart.............................................................................. 11-7
11-5 Ethernet Control Register (ECR).........................................................................................11-11
11-6 Interrupt Event Register (EIR).............................................................................................11-12
11-7 Interrupt Mask Register (EIMR) .........................................................................................11-13
11-8 Interrupt Vector Status Register (IVSR)..............................................................................11-14
11-9 Receive Descriptor Active Register (RDAR).......................................................................11-15
11-10 Transmit Descriptor Active Register (TDAR) ......................................................................11-16
11-11 MII Management Frame Register (MMFR) ......................................................................... 11-17
11-12 MII Speed Control Register (MSCR)..................................................................................11-18
11-13 FIFO Receive Bound Register (FRBR)..............................................................................11-19
11-14 FIFO Receive Start Register (FRSR)................................................................................. 11-20
11-15 Transmit FIFO Watermark (TFWR)....................................................................................11-21
11-16 FIFO Transmit Start Register (TFSR) ................................................................................. 11-22
11-17 Receive Control Register (RCR)......................................................................................... 11-23
11-18 Maximum Frame Length Register (MFLR)..........................................................................11-24
11-19 Transmit Control Register (TCR) ........................................................................................11-25
11-20 RAM Perfect Match Address Low (MALR).......................................................................... 11-26
11-21 RAM Perfect Match Address High (MAUR) ........................................................................11-27
11-22 Hash Table High (HTUR)...................................................................................................11-28
11-23 Hash Table Low (HTLR) ....................................................................................................11-29
11-24 Pointer-to-Receive Descriptor Ring (ERDSR).....................................................................11-30
11-25 Pointer-to-Transmit Descriptor Ring (ETDSR)....................................................................11-31
11-26 Receive Buffer Size (EMRBR) ............................................................................................11-32
11-27 Receive Buffer Descriptor (RxBD) ......................................................................................11-35
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor vii
List of Figures (Continued)
Figure Page Number Title Number
11-28 Transmit Buffer Descriptor (TxBD)..................................................................................... 11-37
12-1 The USB “Tiered Star” Topology...........................................................................................12-2
12-2 USB Module Block Diagram..................................................................................................12-3
12-3 USB Frame Number Register (FNR) ....................................................................................12-9
12-4 USB Frame Number Match Register (FNMR).......................................................................12-9
12-5 USB Real-Time Frame Monitor Register (RFMR)...............................................................12-10
12-6 USB Real-Time Frame Monitor Match Register (RFMMR).................................................12-11
12-7 USB Function Address Register (FAR)............................................................................... 12-11
12-8 USB Alternate Settings Register (ASR) .............................................................................. 12-12
12-9 USB Device Request Data 1 Register (DRR1) ...................................................................12-13
12-10 USB Device Request Data 2 Register (DRR2) ...................................................................12-13
12-11 USB Specification Number Register (SPECR) ...................................................................12-14
12-12 USB Endpoint 0 Status Register (EP0SR)..........................................................................12-14
12-13 USB Endpoint 0 IN Configuration Register (IEP0CFG) ......................................................12-15
12-14 USB Endpoint 0 OUT Configuration Register ..................................................................... 12-16
12-15 USB Endpoint 1–7 Configuration Register..........................................................................12-16
12-16 USB Endpoint 0 Control Register (EP0CTL).......................................................................12-17
12-17 USB Endpoint 1-7 Control Register (EPnCTL) ...................................................................12-20
12-18 USB Endpoint 0 Interrupt Mask (EP0IMR)
and General/Endpoint 0 Interrupt Registers (EP0ISR) .......................................................12-22
12-19 USB Endpoints 1–7 Interrupt Status Registers (EPnISR)...................................................12-25
12-20 USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR) ...................................................... 12-26
12-21 USB Endpoint 0-7 Data Registers (EPnDR) ....................................................................... 12-27
12-22 USB Endpoint 0-7 Data Present Registers (EPnDPR) ....................................................... 12-28
12-23 Example USB Configuration Descriptor Structure .............................................................. 12-29
12-24 Recommended USB Line Interface.....................................................................................12-36
12-25 USB Protection Circuit ........................................................................................................12-37
13-1 PLIC System Diagram...........................................................................................................13-2
13-2 GCI/IDL Receive Data Flow..................................................................................................13-3
13-3 GCI/IDL B-Channel Receive Data Register Demultiplexing..................................................13-4
13-4 GCI/IDL Transmit Data Flow.................................................................................................13-4
13-5 GCI/IDL B Data Transmit Register Multiplexing....................................................................13-5
13-6 B-Channel Unencoded and HDLC Encoded Data................................................................13-6
13-7 D-Channel HDLC Encoded and Unencoded Data................................................................13-7
13-8 D-Channel Contention ..........................................................................................................13-8
13-9 GCI/IDL Loopback Mode ......................................................................................................13-9
13-10 Periodic Frame Interrupt .....................................................................................................13-10
13-11 PLIC Internal Timing Signal Routing...................................................................................13-12
13-12 PLIC Clock Generator.........................................................................................................13-12
13-13 B1 Receive Data Registers P0B1RR–P3B1RR..................................................................13-15
13-14 B2 Receive Data Registers P0B2RR – P3B2RR................................................................13-16
13-15 D Receive Data Registers P0DRR–P3DRR .......................................................................13-16
13-16 B1 Transmit Data Registers P0B1TR–P3B1TR.................................................................. 13-17
13-17 B2 Transmit Data Registers P0B2TR–P3B2TR.................................................................. 13-17
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
viii Freescale Semiconductor
List of Figures (Continued)
Figure Page Number Title Number
13-18 D Transmit Data Registers P0DTR–P3DTR .......................................................................13-18
13-19 Port Configuration Registers (P0CR–P3CR) ......................................................................13-18
13-20 Loopback Control Register (PLCR).....................................................................................13-20
13-21 Interrupt Configuration Registers (P0ICR–P3ICR)..............................................................13-20
13-22 Periodic Status Registers (P0PSR–P3PSR)....................................................................... 13-22
13-23 Aperiodic Status Register (PASR) ......................................................................................13-23
13-24 GCI Monitor Channel Receive Registers (P0GMR–P3GMR) .............................................13-24
13-25 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT).............................................13-25
13-26 GCI Monitor Channel Transmit Abort Register (PGMTA) ...................................................13-26
13-27 GCI Monitor Channel Transmit Status Register (PGMTS)..................................................13-27
13-28 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) ...................................................13-28
13-29 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ................................................... 13-29
13-30 GCI C/I Channel Transmit Status Register (PGCITSR)...................................................... 13-30
13-31 D-Channel Status Register (PDCSR) .................................................................................13-31
13-32 D-Channel Request Registers (PDRQR)............................................................................13-32
13-33 Sync Delay Registers (P0SDR–P3SDR) ............................................................................13-33
13-34 Clock Select Register (PCSR) ............................................................................................13-34
13-35 Port 1 Configuration Register (P1CR)................................................................................. 13-36
13-36 Port 1 Interrupt Configuration Register (P1ICR) .................................................................13-37
13-37 ISDN SOHO PABX Example ..............................................................................................13-38
13-38 Standard IDL2 10-Bit Mode ................................................................................................13-39
13-39 ISDN SOHO PABX Example ..............................................................................................13-40
13-40 Standard IDL2 10-Bit Mode ................................................................................................13-41
13-41 Two-Line Remote Access ...................................................................................................13-41
13-42 Standard IDL2 8-Bit Mode ..................................................................................................13-42
14-1 QSPI Block Diagram .............................................................................................................14-2
14-2 QSPI RAM Model..................................................................................................................14-5
14-3 QSPI Mode Register (QMR) .................................................................................................14-9
14-4 QSPI Clocking and Data Transfer Example........................................................................14-10
14-5 SPI Modes Timing...............................................................................................................14-11
14-6 QSPI Delay Register (QDLYR) ........................................................................................... 14-11
14-7 QSPI Wrap Register (QWR) ...............................................................................................14-12
14-8 QSPI Interrupt Register (QIR).............................................................................................14-13
14-9 QSPI Address Register.......................................................................................................14-14
14-10 QSPI Data Register ............................................................................................................14-14
14-11 Command RAM Registers (QCR0–QCR15).......................................................................14-15
15-1 Timer Block Diagram.............................................................................................................15-2
15-2 Timer Mode Registers (TMR0–TMR3)..................................................................................15-3
15-3 Timer Reference Registers (TRR0–TRR3)...........................................................................15-4
15-4 Timer Capture Registers (TCAP0–TCAP3) ..........................................................................15-4
15-5 Timer Counter (TCN0–TCN3)...............................................................................................15-4
15-6 Timer Event Registers (TER0–TER3)................................................................................... 15-5
16-1 Simplified Block Diagram ...................................................................................................... 16-1
16-2 UART Mode Registers 1 (UMR1n)........................................................................................16-4
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor ix
List of Figures (Continued)
Figure Page Number Title Number
16-3 UART Mode Register 2 (UMR2n) .........................................................................................16-6
16-4 UART Status Registers (USRn)............................................................................................16-7
16-5 UART Clock-Select Registers (UCSRn) ...............................................................................16-8
16-6 UART Command Registers (UCRn) .....................................................................................16-9
16-7 UART Receiver Buffer (URBn)............................................................................................16-10
16-8 UART Transmitter Buffers (UTBn) ......................................................................................16-11
16-9 UART Input Port Change Registers (UIPCRn) ................................................................... 16-11
16-10 UART Auxiliary Control Registers (UACRn) .......................................................................16-12
16-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn).....................................................16-13
16-12 UART Divider Upper Registers (UDUn)..............................................................................16-14
16-13 UART Divider Lower Registers (UDLn)...............................................................................16-14
16-14 UART Autobaud Upper Registers (UABUn)........................................................................16-14
16-15 UART Autobaud Lower Registers (UABLn) ........................................................................ 16-14
16-16 UART Transmitter FIFO Registers (UTFn) .........................................................................16-15
16-17 UART Receiver FIFO Registers (URFn).............................................................................16-16
16-18 UART Fractional Precision Divider Control Registers (UFPDn)..........................................16-17
16-19 UART Input Port Registers (UIPn) ......................................................................................16-17
16-20 UART Output Port Command Registers (UOP1/UOP0) .....................................................16-18
16-21 UART Block Diagram Showing External and Internal Interface Signals............................. 16-18
16-22 UART/RS-232 Interface ......................................................................................................16-19
16-23 Clocking Source Diagram ...................................................................................................16-20
16-24 Transmitter and Receiver Functional Diagram....................................................................16-22
16-25 Transmitter Timing ..............................................................................................................16-23
16-26 Receiver Timing .................................................................................................................. 16-24
16-27 Automatic Echo...................................................................................................................16-27
16-28 Local Loop-Back .................................................................................................................16-27
16-29 Remote Loop-Back .............................................................................................................16-28
16-30 Multidrop Mode Timing Diagram.........................................................................................16-29
16-31 UART Mode Programming Flowchart (Sheet 1 of 5) .......................................................... 16-30
17-1 Port A Control Register (PACNT)..........................................................................................17-3
17-2 Port B Control Register (PBCNT)..........................................................................................17-5
17-3 Port D Control Register (PDCNT) .........................................................................................17-8
17-4 Port A Data Direction Register (PADDR)............................................................................17-10
17-5 Port B Data Direction Register (PBDDR)............................................................................17-10
17-6 Port C Data Direction Register (PCDDR)............................................................................17-11
17-7 Port x Data Register (PADAT, PBDAT, and PCDAT) .........................................................17-11
18-1 PWM Block Diagram (3 Identical Modules)...........................................................................18-1
18-2 PWM Control Registers (PWCRn) ........................................................................................18-3
18-3 PWM Width Register (PWWDn)............................................................................................18-4
18-4 PWM Waveform Examples (PWCRn[EN] = 1)......................................................................18-4
19-1 MCF5272 Block Diagram with Signal Interfaces...................................................................19-2
20-1 Internal Operand Representation..........................................................................................20-5
20-2 MCF5272 Interface to Various Port Sizes............................................................................. 20-5
20-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination................................................20-8
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
x Freescale Semiconductor
List of Figures (Continued)
Figure Page Number Title Number
20-4 Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination................................................. 20-9
20-5 Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination................20-9
20-6 Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination.............. 20-10
20-7 Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................20-10
20-8 Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................ 20-11
20-9 Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State ................20-11
20-10 Longword Read; EBI=11; 32-Bit Port; Internal Termination................................................20-12
20-11 Word Write; EBI=11; 16/32-Bit Port; Internal Termination ..................................................20-13
20-12 Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination.................................20-14
20-13 Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination................ 20-14
20-14 Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination...................................20-15
20-15 Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination.................. 20-15
20-16 Longword Read with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination .........................................................................20-16
20-17 Longword Write with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination .........................................................................20-17
20-18 Example of a Misaligned Longword Transfer......................................................................20-18
20-19 Example of a Misaligned Word Transfer.............................................................................20-18
20-20 Longword Write Access To 32-Bit Port Terminated with TEA Timing................................. 20-20
20-21 Master Reset Timing........................................................................................................... 20-22
20-22 Normal Reset Timing ..........................................................................................................20-23
20-23 Software Watchdog Timer Reset Timing ............................................................................20-24
20-24 Soft Reset Timing ...............................................................................................................20-25
21-1 Test Access Port Block Diagram...........................................................................................21-2
21-2 TAP Controller State Machine...............................................................................................21-3
21-3 Output Cell (O.Cell) (BC–1) ..................................................................................................21-4
21-4 Input Cell (I.Cell). Observe only (BC–4)................................................................................ 21-5
21-5 Output Control Cell (En.Cell) (BC–4) .................................................................................... 21-5
21-6 Bidirectional Cell (IO.Cell) (BC–6).........................................................................................21-6
21-7 General Arrangement for Bidirectional Pins..........................................................................21-6
21-8 Bypass Register....................................................................................................................21-8
22-1 MCF5272 Pinout (196 MAPBGA) .........................................................................................22-1
22-2 196 MAPBGA Package Dimensions (Case No. 1128A-01)..................................................22-2
23-1 Clock Input Timing Diagram..................................................................................................23-5
23-2 General Input Timing Requirements.....................................................................................23-7
23-3 Read/Write SRAM Bus Timing..............................................................................................23-9
23-4 SRAM Bus Cycle Terminated by TA...................................................................................23-10
23-5 SRAM Bus Cycle Terminated by TEA.................................................................................23-11
23-6 Reset and Mode Select/HIZ Configuration Timing.............................................................. 23-12
23-7 Real-Time Trace AC Timing................................................................................................23-13
23-8 BDM Serial Port AC Timing.................................................................................................23-13
23-9 SDRAM Signal Timing ........................................................................................................23-15
23-10 SDRAM Self-Refresh Cycle Timing ....................................................................................23-16
23-11 MII Receive Signal Timing Diagram....................................................................................23-17
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xi
List of Figures (Continued)
Figure Page Number Title Number
23-12 MII Transmit Signal Timing Diagram................................................................................... 23-18
23-13 MII Async Inputs Timing Diagram ....................................................................................... 23-19
23-14 MII Serial Management Channel Timing Diagram .............................................................. 23-20
23-15 Timer Timing .......................................................................................................................23-21
23-16 UART Timing.......................................................................................................................23-22
23-17 IDL Master Timing...............................................................................................................23-23
23-18 IDL Slave Timing.................................................................................................................23-25
23-19 GCI Slave Mode Timing......................................................................................................23-26
23-20 GCI Master Mode Timing....................................................................................................23-27
23-21 General-Purpose I/O Port Timing........................................................................................23-28
23-22 USB Interface Timing..........................................................................................................23-29
23-23 IEEE 1149.1 (JTAG) Timing................................................................................................23-30
23-24 QSPI Timing........................................................................................................................23-31
23-25 PWM Timing........................................................................................................................23-32
B-1 Buffering and Termination.......................................................................................................B-2
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xii Freescale Semiconductor
Table of Contents
Paragraph Page Number Title Number
Chapter 1
Overview
1.1 MCF5272 Key Features ................................................................................................................. 1-1
1.2 MCF5272 Architecture .................................................................................................................. 1-4
1.2.1 Version 2 ColdFire Core ..................................................................................................... 1-4
1.2.2 System Integration Module (SIM) ...................................................................................... 1-5
1.2.2.1 External Bus Interface .......................................................................................... 1-5
1.2.2.2 Chip Select and Wait State Generation ................................................................. 1-5
1.2.2.3 System Configuration and Protection ...................................................................1-5
1.2.2.4 Power Management .............................................................................................. 1-6
1.2.2.5 Parallel Input/Output Ports ................................................................................... 1-6
1.2.2.6 Interrupt Inputs ..................................................................................................... 1-6
1.2.3 UART Module .................................................................................................................... 1-6
1.2.4 Timer Module .....................................................................................................................1-7
1.2.5 Test Access Port ................................................................................................................. 1-7
1.3 System Design .............................................................................................................................. 1-7
1.3.1 System Bus Configuration ..................................................................................................1-7
1.4 MCF5272-Specific Features .......................................................................................................... 1-7
1.4.1 Physical Layer Interface Controller (PLIC) ....................................................................... 1-7
1.4.2 Pulse-Width Modulation (PWM) Unit ............................................................................... 1-8
1.4.3 Queued Serial Peripheral Interface (QSPI) ........................................................................ 1-8
1.4.4 Universal Serial Bus (USB) Module .................................................................................. 1-8
Chapter 2
ColdFire Core
2.1 Features and Enhancements ........................................................................................................... 2-1
2.1.1 Decoupled Pipelines ........................................................................................................... 2-1
2.1.1.1 Instruction Fetch Pipeline (IFP) ............................................................................ 2-2
2.1.1.2 Operand Execution Pipeline (OEP) ...................................................................... 2-2
2.1.1.2.1 Illegal Opcode Handling.............................................................................. 2-3
2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit.............................................. 2-3
2.1.1.2.3 Hardware Divide Unit.................................................................................. 2-4
2.1.2 Debug Module Enhancements ............................................................................................ 2-4
2.2 Programming Model ...................................................................................................................... 2-4
2.2.1 User Programming Model .................................................................................................. 2-4
2.2.1.1 Data Registers (D0–D7) ....................................................................................... 2-5
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xiii
Table of Contents (Continued)
Paragraph Page Number Title Number
2.2.1.2 Address Registers (A0–A6) .................................................................................. 2-5
2.2.1.3 Stack Pointer (A7, SP) .......................................................................................... 2-5
2.2.1.4 Program Counter (PC) .......................................................................................... 2-6
2.2.1.5 Condition Code Register (CCR) ...........................................................................2-6
2.2.1.6 MAC Programming Model ................................................................................... 2-7
2.2.2 Supervisor Programming Model ........................................................................................ 2-7
2.2.2.1 Status Register (SR) ..............................................................................................2-8
2.2.2.2 Vector Base Register (VBR) ................................................................................. 2-8
2.2.2.3 Cache Control Register (CACR) .......................................................................... 2-9
2.2.2.4 Access Control Registers (ACR0–ACR1) ............................................................ 2-9
2.2.2.5 ROM Base Address Register (ROMBAR) ........................................................... 2-9
2.2.2.6 RAM Base Address Register (RAMBAR) ........................................................... 2-9
2.2.2.7 Module Base Address Register (MBAR) ............................................................. 2-9
2.3 Integer Data Formats ..................................................................................................................... 2-9
2.4 Organization of Data in Registers ................................................................................................2-10
2.4.1 Organization of Integer Data Formats in Registers .......................................................... 2-10
2.4.2 Organization of Integer Data Formats in Memory ........................................................... 2-11
2.5 Addressing Mode Summary ........................................................................................................ 2-12
2.6 Instruction Set Summary ............................................................................................................. 2-13
2.6.1 Instruction Set Summary .................................................................................................. 2-15
2.7 Instruction Timing ........................................................................................................................2-19
2.7.1 MOVE Instruction Execution Times ................................................................................2-20
2.7.2 Execution Timings—One-Operand Instructions .............................................................. 2-22
2.7.3 Execution Timings—Two-Operand Instructions ..............................................................2-22
2.7.4 Miscellaneous Instruction Execution Times .....................................................................2-24
2.7.5 Branch Instruction Execution Times ................................................................................ 2-25
2.8 Exception Processing Overview .................................................................................................. 2-25
2.8.1 Exception Stack Frame Definition ................................................................................... 2-27
2.8.2 Processor Exceptions ........................................................................................................ 2-28
Chapter 3
Hardware Multiply/Accumulate (MAC) Unit
3.1 Overview ........................................................................................................................................ 3-1
3.1.1 MAC Programming Model ................................................................................................. 3-2
3.1.2 General Operation .............................................................................................................. 3-3
3.1.3 MAC Instruction Set Summary .......................................................................................... 3-4
3.1.4 Data Representation ............................................................................................................ 3-4
3.2 MAC Instruction Execution Timings ............................................................................................. 3-4
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xiv Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
Chapter 4
Local Memory
4.1 Interactions between Local Memory Modules .............................................................................. 4-1
4.2 Local Memory Registers ................................................................................................................ 4-2
4.3 SRAM Overview ........................................................................................................................... 4-2
4.3.1 SRAM Operation ................................................................................................................4-2
4.3.2 SRAM Programming Model .............................................................................................. 4-2
4.3.2.1 SRAM Base Address Register (RAMBAR) ......................................................... 4-3
4.3.2.2 SRAM Initialization ............................................................................................. 4-4
4.3.2.3 Programming RAMBAR for Power Management ............................................... 4-4
4.4 ROM Overview .............................................................................................................................. 4-5
4.4.1 ROM Operation .................................................................................................................. 4-5
4.4.2 ROM Programming Model ................................................................................................. 4-5
4.4.2.1 ROM Base Address Register (ROMBAR) ........................................................... 4-5
4.4.2.2 Programming ROMBAR for Power Management ............................................... 4-6
4.5 Instruction Cache Overview .......................................................................................................... 4-7
4.5.1 Instruction Cache Physical Organization ........................................................................... 4-7
4.5.2 Instruction Cache Operation ...............................................................................................4-8
4.5.2.1 Interaction with Other Modules ............................................................................ 4-8
4.5.2.2 Cache Coherency and Invalidation ....................................................................... 4-8
4.5.2.3 Caching Modes ..................................................................................................... 4-9
4.5.2.3.1 Cacheable Accesses ..................................................................................... 4-9
4.5.2.3.2 Cache-Inhibited Accesses............................................................................ 4-9
4.5.2.4 Reset ...................................................................................................................4-10
4.5.2.5 Cache Miss Fetch Algorithm/Line Fills ............................................................. 4-10
4.5.3 Instruction Cache Programming Model ........................................................................... 4-12
4.5.3.1 Cache Control Register (CACR) ........................................................................ 4-12
4.5.3.2 Access Control Registers (ACR0 and ACR1) .................................................... 4-14
Chapter 5
Debug Support
5.1 Overview ........................................................................................................................................ 5-1
5.2 Signal Description .......................................................................................................................... 5-2
5.3 Real-Time Trace Support ...............................................................................................................5-3
5.3.1 Begin Execution of Taken Branch (PST = 0x5) ................................................................. 5-4
5.4 Programming Model ...................................................................................................................... 5-5
5.4.1 Revision A Shared Debug Resources .................................................................................5-7
5.4.2 Address Attribute Trigger Register (AATR) ...................................................................... 5-7
5.4.3 Address Breakpoint Registers (ABLR, ABHR) ................................................................. 5-9
5.4.4 Configuration/Status Register (CSR) ............................................................................... 5-10
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xv
Table of Contents (Continued)
Paragraph Page Number Title Number
5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR) ............................................................ 5-12
5.4.6 Program Counter Breakpoint/Mask Registers
(PBR, PBMR) ............................................................................................................................ 5-13
5.4.7 Trigger Definition Register (TDR) ................................................................................... 5-14
5.5 Background Debug Mode (BDM) ............................................................................................... 5-15
5.5.1 CPU Halt .......................................................................................................................... 5-16
5.5.2 BDM Serial Interface ....................................................................................................... 5-17
5.5.2.1 Receive Packet Format ....................................................................................... 5-18
5.5.2.2 Transmit Packet Format ......................................................................................5-18
5.5.3 BDM Command Set ......................................................................................................... 5-19
5.5.3.1 ColdFire BDM Command Format ...................................................................... 5-20
5.5.3.1.1 Extension Words as Required.................................................................... 5-20
5.5.3.2 Command Sequence Diagrams ........................................................................... 5-21
5.5.3.3 Command Set Descriptions ................................................................................ 5-22
5.5.3.3.1 Read A/D Register (RAREG/RDREG)...........................................................5-22
5.5.3.3.2 Write A/D Register (WAREG/WDREG)........................................................ 5-23
5.5.3.3.3 Read Memory Location (READ)................................................................. 5-24
5.5.3.3.4 Write Memory Location (WRITE)............................................................... 5-25
5.5.3.3.5 Dump Memory Block (DUMP) ................................................................... 5-27
5.5.3.3.6 Fill Memory Block (FILL) .......................................................................... 5-28
5.5.3.3.7 Resume Execution (GO) ............................................................................. 5-29
5.5.3.3.8 No Operation (NOP).................................................................................... 5-30
5.5.3.3.9 Read Control Register (RCREG).................................................................. 5-30
5.5.3.3.10 Write Control Register (WCREG)..............................................................5-31
5.5.3.3.11 Read Debug Module Register (RDMREG).................................................5-32
5.5.3.3.12 Write Debug Module Register (WDMREG)............................................... 5-33
5.6 Real-Time Debug Support ........................................................................................................... 5-33
5.6.1 Theory of Operation .......................................................................................................... 5-34
5.6.1.1 Emulator Mode ................................................................................................... 5-35
5.6.2 Concurrent BDM and Processor Operation ...................................................................... 5-35
5.7 Processor Status, DDATA Definition ........................................................................................... 5-36
5.7.1 User Instruction Set .......................................................................................................... 5-36
5.7.2 Supervisor Instruction Set ................................................................................................5-40
5.8 Freescale-Recommended BDM Pinout ....................................................................................... 5-41
Chapter 6
System Integration Module (SIM)
6.1 Features .......................................................................................................................................... 6-1
6.2 Programming Model ...................................................................................................................... 6-2
6.2.1 SIM Register Memory Map ................................................................................................ 6-2
6.2.2 Module Base Address Register (MBAR) ........................................................................... 6-3
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xvi Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
6.2.3 System Configuration Register (SCR) ............................................................................... 6-5
6.2.4 System Protection Register (SPR) ...................................................................................... 6-6
6.2.5 Power Management Register (PMR) .................................................................................. 6-7
6.2.6 Activate Low-Power Register (ALPR) ............................................................................ 6-10
6.2.7 Device Identification Register (DIR) ............................................................................... 6-11
6.2.8 Software Watchdog Timer ................................................................................................ 6-11
6.2.8.1 Watchdog Reset Reference Register (WRRR) ................................................... 6-12
6.2.8.2 Watchdog Interrupt Reference Register (WIRR) ................................................6-12
6.2.8.3 Watchdog Counter Register (WCR) ................................................................... 6-13
6.2.8.4 Watchdog Event Register (WER) .......................................................................6-13
Chapter 7
Interrupt Controller
7.1 Overview ........................................................................................................................................ 7-1
7.2 Interrupt Controller Registers ........................................................................................................ 7-2
7.2.1 Interrupt Controller Registers .............................................................................................7-3
7.2.2 Interrupt Control Registers (ICR1–ICR4) .......................................................................... 7-4
7.2.2.1 Interrupt Control Register 1 (ICR1) ..................................................................... 7-4
7.2.2.2 Interrupt Control Register 2 (ICR2) ..................................................................... 7-5
7.2.2.3 Interrupt Control Register 3 (ICR3) ..................................................................... 7-5
7.2.2.4 Interrupt Control Register 4 (ICR4) ..................................................................... 7-5
7.2.3 Interrupt Source Register (ISR) ..........................................................................................7-6
7.2.4 Programmable Interrupt Transition Register (PITR) .......................................................... 7-7
7.2.5 Programmable Interrupt Wakeup Register (PIWR) ............................................................7-8
7.2.6 Programmable Interrupt Vector Register (PIVR) ............................................................... 7-9
Chapter 8
Chip Select Module
8.1 Overview ........................................................................................................................................ 8-1
8.1.1 Features ............................................................................................................................... 8-1
8.1.2 Chip Select Usage ............................................................................................................... 8-1
8.1.3 Boot CS0 Operation ........................................................................................................... 8-2
8.2 Chip Select Registers ..................................................................................................................... 8-2
8.2.1 Chip Select Base Registers (CSBR0–CSBR7) ................................................................... 8-3
8.2.2 Chip Select Option Registers (CSOR0–CSOR7) ............................................................... 8-5
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xvii
Table of Contents (Continued)
Paragraph Page Number Title Number
Chapter 9
SDRAM Controller
9.1 Overview ........................................................................................................................................ 9-1
9.2 SDRAM Controller Signals ........................................................................................................... 9-1
9.3 Interface to SDRAM Devices ........................................................................................................ 9-4
9.4 SDRAM Banks, Page Hits, and Page Misses ................................................................................ 9-6
9.5 SDRAM Registers ......................................................................................................................... 9-6
9.5.1 SDRAM Configuration Register (SDCR) .......................................................................... 9-6
9.5.2 SDRAM Timing Register (SDTR) ..................................................................................... 9-8
9.6 Auto Initialization .......................................................................................................................... 9-9
9.7 Power-Down and Self-Refresh ...................................................................................................... 9-9
9.8 Performance ................................................................................................................................. 9-10
9.9 Solving Timing Issues with SDCR[INV] .................................................................................... 9-12
9.10 SDRAM Interface ...................................................................................................................... 9-14
9.10.1 SDRAM Read Accesses ................................................................................................. 9-15
9.10.2 SDRAM Write Accesses ................................................................................................9-18
9.10.3 SDRAM Refresh Timing ................................................................................................9-20
Chapter 10
DMA Controller
10.1 DMA Data Transfer Types ......................................................................................................... 10-1
10.2 DMA Address Modes ................................................................................................................ 10-2
10.3 DMA Controller Registers ......................................................................................................... 10-2
10.3.1 DMA Mode Register (DMR) ......................................................................................... 10-2
10.3.2 DMA Interrupt Register (DIR) .......................................................................................10-4
10.3.3 DMA Source Address Register (DSAR) ........................................................................ 10-5
10.3.4 DMA Destination Address Register (DDAR) ................................................................ 10-6
10.3.5 DMA Byte Count Register (DBCR) ............................................................................... 10-6
Chapter 11
Ethernet Module
11.1 Overview .................................................................................................................................... 11-1
11.1.1 Features ........................................................................................................................... 11-1
11.2 Module Operation ...................................................................................................................... 11-1
11.3 Transceiver Connection ............................................................................................................. 11-3
11.4 FEC Frame Transmission ........................................................................................................... 11-4
11.4.1 FEC Frame Reception .................................................................................................... 11-5
11.4.2 CAM Interface ................................................................................................................11-6
11.4.3 Ethernet Address Recognition ........................................................................................ 11-6
11.4.4 Hash Table Algorithm ..................................................................................................... 11-8
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xviii Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
11.4.5 Interpacket Gap Time ..................................................................................................... 11-8
11.4.6 Collision Handling ..........................................................................................................11-8
11.4.7 Internal and External Loopback ..................................................................................... 11-8
11.4.8 Ethernet Error-Handling Procedure ................................................................................ 11-9
11.4.8.1 Transmission Errors .......................................................................................... 11-9
11.4.8.2 Reception Errors ............................................................................................... 11-9
11.5 Programming Model ................................................................................................................ 11-10
11.5.1 Ethernet Control Register (ECR) ...................................................................................11-11
11.5.2 Interrupt Event Register (EIR) ..................................................................................... 11-12
11.5.3 Interrupt Mask Register (EIMR) .................................................................................. 11-13
11.5.4 Interrupt Vector Status Register (IVSR) ....................................................................... 11-14
11.5.5 Receive Descriptor Active Register (RDAR) ............................................................... 11-15
11.5.6 Transmit Descriptor Active Register (TDAR) ............................................................. 11-16
11.5.7 MII Management Frame Register (MMFR) ................................................................. 11-17
11.5.8 MII Speed Control Register (MSCR) ........................................................................... 11-18
11.5.9 FIFO Receive Bound Register (FRBR) ........................................................................ 11-19
11.5.10 FIFO Receive Start Register (FRSR) ......................................................................... 11-20
11.5.11 Transmit FIFO Watermark (TFWR) ........................................................................... 11-21
11.5.12 FIFO Transmit Start Register (TFSR) ........................................................................ 11-22
11.5.13 Receive Control Register (RCR) ................................................................................ 11-23
11.5.14 Maximum Frame Length Register (MFLR) ............................................................... 11-24
11.5.15 Transmit Control Register (TCR) ............................................................................... 11-25
11.5.16 RAM Perfect Match Address Low (MALR) .............................................................. 11-26
11.5.16.1 RAM Perfect Match Address High (MAUR) ............................................... 11-27
11.5.17 Hash Table High (HTUR) ........................................................................................... 11-28
11.5.18 Hash Table Low (HTLR) ............................................................................................ 11-29
11.5.19 Pointer-to-Receive Descriptor Ring (ERDSR) ........................................................... 11-30
11.5.20 Pointer-to-Transmit Descriptor Ring (ETDSR) .......................................................... 11-31
11.5.21 Receive Buffer Size Register (EMRBR) .................................................................... 11-32
11.5.22 Initialization Sequence ............................................................................................... 11-33
11.5.22.1 Hardware Initialization ................................................................................. 11-33
11.5.23 User Initialization (Prior to Asserting ETHER_EN) .................................................. 11-33
11.5.24 FEC Initialization ....................................................................................................... 11-34
11.5.24.1 User Initialization (after setting ETHER_EN) .............................................. 11-34
11.6 Buffer Descriptors .................................................................................................................... 11-34
11.6.1 FEC Buffer Descriptor Tables ...................................................................................... 11-35
11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD) .................................................. 11-35
11.6.1.2 Ethernet Transmit Buffer Descriptor .............................................................. 11-37
11.7 Differences between MCF5272 FEC and MPC860T FEC ...................................................... 11-39
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xix
Table of Contents (Continued)
Paragraph Page Number Title Number
Chapter 12
Universal Serial Bus (USB)
12.1 Introduction ................................................................................................................................ 12-1
12.2 Module Operation ...................................................................................................................... 12-2
12.2.1 USB Module Architecture .............................................................................................. 12-2
12.2.1.1 USB Transceiver Interface ................................................................................12-3
12.2.1.2 Clock Generator ................................................................................................ 12-4
12.2.1.3 USB Control Logic ........................................................................................... 12-4
12.2.1.4 Endpoint Controllers ......................................................................................... 12-5
12.2.1.5 USB Request Processor .................................................................................... 12-5
12.3 Register Description and Programming Model ......................................................................... 12-7
12.3.1 USB Memory Map ......................................................................................................... 12-7
12.3.2 Register Descriptions ......................................................................................................12-9
12.3.2.1 USB Frame Number Register (FNR) ............................................................... 12-9
12.3.2.2 USB Frame Number Match Register (FNMR) ................................................. 12-9
12.3.2.3 USB Real-Time Frame Monitor Register (RFMR) ........................................ 12-10
12.3.2.4 USB Real-Time Frame Monitor Match Register (RFMMR) ......................... 12-11
12.3.2.5 USB Function Address Register (FAR) .......................................................... 12-11
12.3.2.6 USB Alternate Settings Register (ASR) ......................................................... 12-12
12.3.2.7 USB Device Request Data 1 and 2 Registers (DRR1/ 2) ............................... 12-13
12.3.2.8 USB Specification Number Register (SPECR) .............................................. 12-14
12.3.2.9 USB Endpoint 0 Status Register (EP0SR) ...................................................... 12-14
12.3.2.10 USB Endpoint 0 IN Configuration Register (IEP0CFG) ............................. 12-15
12.3.2.11 USB Endpoint 0 OUT Configuration Register (OEP0CFG) ........................12-16
12.3.2.12 USB Endpoint 1–7 Configuration Register (EPnCFG) ................................ 12-16
12.3.2.13 USB Endpoint 0 Control Register (EP0CTL) .............................................. 12-17
12.3.2.14 USB Endpoint 1–7 Control Register (EPnCTL) .......................................... 12-20
12.3.2.15 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0 Interrupt
Registers (EP0ISR) .......................................................................................................... 12-22
12.3.2.16 USB Endpoints 1–7 Status / Interrupt Registers (EPnISR) .......................... 12-25
12.3.2.17 USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR) ............................. 12-26
12.3.2.18 USB Endpoint 0–7 Data Registers (EPnDR) ................................................ 12-27
12.3.2.19 USB Endpoint 0–7 Data Present Registers (EPnDPR) ................................. 12-28
12.3.3 Configuration RAM ...................................................................................................... 12-28
12.3.3.1 Configuration RAM Content .......................................................................... 12-28
12.3.3.2 USB Device Configuration Example .............................................................. 12-29
12.3.4 USB Module Access Times .......................................................................................... 12-30
12.3.4.1 Registers ......................................................................................................... 12-30
12.3.4.2 Endpoint FIFOs .............................................................................................. 12-30
12.3.4.3 Configuration RAM ........................................................................................ 12-30
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xx Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
12.4 Software Architecture and Application Notes ......................................................................... 12-31
12.4.1 USB Module Initialization ........................................................................................... 12-31
12.4.2 USB Configuration and Interface Changes .................................................................. 12-31
12.4.3 FIFO Configuration ...................................................................................................... 12-32
12.4.4 Data Flow ..................................................................................................................... 12-32
12.4.4.1 Control, Bulk, and Interrupt Endpoints .......................................................... 12-33
12.4.4.1.1 IN Endpoints .......................................................................................... 12-33
12.4.4.1.2 OUT Endpoints ...................................................................................... 12-33
12.4.4.2 Isochronous Endpoints .................................................................................... 12-33
12.4.4.2.1 IN Endpoints .......................................................................................... 12-34
12.4.4.2.2 OUT Endpoints ...................................................................................... 12-34
12.4.5 Class- and Vendor-Specific Request Operation ............................................................ 12-34
12.4.6 remote wakeup and resume Operation ......................................................................... 12-35
12.4.7 Endpoint Halt Feature ................................................................................................... 12-35
12.5 Line Interface ........................................................................................................................... 12-36
12.5.1 Attachment Detection ................................................................................................... 12-36
12.5.2 PCB Layout Recommendations ................................................................................... 12-36
12.5.3 Recommended USB Protection Circuit ........................................................................12-37
Chapter 13
Physical Layer Interface Controller (PLIC)
13.1 Introduction ................................................................................................................................ 13-1
13.2 GCI/IDL Block .......................................................................................................................... 13-3
13.2.1 GCI/IDL B- and D-Channel Receive Data Registers .....................................................13-3
13.2.2 GCI/IDL B- and D-Channel Transmit Data Registers ................................................... 13-4
13.2.3 GCI/IDL B- and D-Channel Bit Alignment ................................................................... 13-5
13.2.3.1 B-Channel Unencoded Data ............................................................................. 13-5
13.2.3.2 B-Channel HDLC Encoded Data ...................................................................... 13-6
13.2.3.3 D-Channel HDLC Encoded Data ..................................................................... 13-6
13.2.3.4 D-Channel Unencoded Data ............................................................................. 13-7
13.2.3.5 GCI/IDL D-Channel Contention ..................................................................... 13-8
13.2.4 GCI/IDL Looping Modes ............................................................................................... 13-8
13.2.4.1 Automatic Echo Mode ...................................................................................... 13-9
13.2.4.2 Local Loopback Mode ...................................................................................... 13-9
13.2.4.3 Remote Loopback Mode ................................................................................... 13-9
13.2.5 GCI/IDL Interrupts ......................................................................................................... 13-9
13.2.5.1 GCI/IDL Periodic Frame Interrupt ................................................................... 13-9
13.2.5.2 GCI Aperiodic Status Interrupt ...................................................................... 13-10
13.2.5.3 Interrupt Control ............................................................................................. 13-11
13.3 PLIC Timing Generator ........................................................................................................... 13-11
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxi
Table of Contents (Continued)
Paragraph Page Number Title Number
13.3.1 Clock Synthesis ............................................................................................................ 13-11
13.3.2 Super Frame Sync Generation ......................................................................................13-13
13.3.3 Frame Sync Synthesis ................................................................................................... 13-13
13.4 PLIC Register Memory Map ................................................................................................... 13-13
13.5 PLIC Registers ......................................................................................................................... 13-15
13.5.1 B1 Data Receive Registers (P0B1RR–P3B1RR) ......................................................... 13-15
13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR) ......................................................... 13-16
13.5.3 D Data Receive Registers (P0DRR–P3DRR) .............................................................. 13-16
13.5.4 B1 Data Transmit Registers (P0B1TR–P3B1TR) ......................................................... 13-17
13.5.5 B2 Data Transmit Registers (P0B2TR–P3B2TR) ........................................................13-17
13.5.6 D Data Transmit Registers (P0DTR–P3DTR) ............................................................. 13-18
13.5.7 Port Configuration Registers (P0CR–P3CR) ............................................................... 13-18
13.5.8 Loopback Control Register (PLCR) .............................................................................13-20
13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR) ..................................................... 13-20
13.5.10 Periodic Status Registers (P0PSR–P3PSR) ................................................................13-22
13.5.11 Aperiodic Status Register (PASR) ..............................................................................13-23
13.5.12 GCI Monitor Channel Receive Registers (P0GMR–P3GMR) ...................................13-24
13.5.13 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT) .................................. 13-25
13.5.14 GCI Monitor Channel Transmit Abort Register (PGMTA) ....................................... 13-26
13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS) ....................................... 13-27
13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) ..........................................13-28
13.5.17 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ......................................... 13-29
13.5.18 GCI C/I Channel Transmit Status Register (PGCITSR) ............................................ 13-30
13.5.19 D-Channel Status Register (PDCSR) ......................................................................... 13-31
13.5.20 D-Channel Request Register (PDRQR) ..................................................................... 13-32
13.5.21 Sync Delay Registers (P0SDR–P3SDR) .................................................................... 13-33
13.5.22 Clock Select Register (PCSR) .................................................................................... 13-34
13.6 Application Examples .............................................................................................................. 13-35
13.6.1 Introduction .................................................................................................................. 13-35
13.6.2 PLIC Initialization ........................................................................................................ 13-35
13.6.2.1 Port Configuration Example ........................................................................... 13-35
13.6.2.2 Interrupt Configuration Example .................................................................... 13-37
13.6.3 Example 1: ISDN SOHO PBX with Ports 0, 1, 2, and 3 .............................................. 13-38
13.6.4 Example 2: ISDN SOHO PBX with Ports 1, 2, and 3 .................................................. 13-40
13.6.5 Example 3: Two-Line Remote Access with Ports 0 and 1 ........................................... 13-41
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxii Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
Chapter 14
Queued Serial Peripheral Interface (QSPI) Module
14.1 Overview .................................................................................................................................... 14-1
14.2 Features ...................................................................................................................................... 14-1
14.3 Module Description ................................................................................................................... 14-1
14.3.1 Interface and Pins ........................................................................................................... 14-3
14.3.2 Internal Bus Interface ..................................................................................................... 14-3
14.4 Operation ................................................................................................................................... 14-3
14.4.1 QSPI RAM ..................................................................................................................... 14-4
14.4.1.1 Receive RAM ................................................................................................... 14-5
14.4.1.2 Transmit RAM ..................................................................................................14-6
14.4.1.3 Command RAM ............................................................................................... 14-6
14.4.2 Baud Rate Selection ....................................................................................................... 14-6
14.4.3 Transfer Delays ...............................................................................................................14-7
14.4.4 Transfer Length ..............................................................................................................14-8
14.4.5 Data Transfer .................................................................................................................. 14-8
14.5 Programming Model .................................................................................................................. 14-9
14.5.1 QSPI Mode Register (QMR) .......................................................................................... 14-9
14.5.2 QSPI Delay Register (QDLYR) ................................................................................... 14-11
14.5.3 QSPI Wrap Register (QWR) ........................................................................................ 14-12
14.5.4 QSPI Interrupt Register (QIR) ...................................................................................... 14-13
14.5.5 QSPI Address Register (QAR) ..................................................................................... 14-14
14.5.6 QSPI Data Register (QDR) .......................................................................................... 14-14
14.5.7 Command RAM Registers (QCR0–QCR15) ............................................................... 14-15
14.5.8 Programming Example ................................................................................................. 14-16
Chapter 15
Timer Module
15.1 Overview .................................................................................................................................... 15-1
15.2 Timer Operation .........................................................................................................................15-1
15.3 General-Purpose Timer Registers .............................................................................................. 15-3
15.3.1 Timer Mode Registers (TMR0–TMR3) ..........................................................................15-3
15.3.2 Timer Reference Registers (TRR0–TRR3) .................................................................... 15-4
15.3.3 Timer Capture Registers (TCAP0–TCAP3) ...................................................................15-4
15.3.4 Timer Counters (TCN0–TCN3) .....................................................................................15-4
15.3.5 Timer Event Registers (TER0–TER3) ...........................................................................15-5
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxiii
Table of Contents (Continued)
Paragraph Page Number Title Number
Chapter 16
UART Modules
16.1 Overview .................................................................................................................................... 16-1
16.2 Serial Module Overview ............................................................................................................ 16-2
16.3 Register Descriptions ................................................................................................................. 16-2
16.3.1 UART Mode Registers 1 (UMR1n) ............................................................................... 16-4
16.3.2 UART Mode Register 2 (UMR2n) ................................................................................. 16-6
16.3.3 UART Status Registers (USRn) ..................................................................................... 16-7
16.3.4 UART Clock-Select Registers (UCSRn) ........................................................................16-8
16.3.5 UART Command Registers (UCRn) .............................................................................. 16-9
16.3.6 UART Receiver Buffers (URBn) ................................................................................. 16-10
16.3.7 UART Transmitter Buffers (UTBn) ............................................................................. 16-11
16.3.8 UART Input Port Change Registers (UIPCRn) ............................................................ 16-11
16.3.9 UART Auxiliary Control Registers (UACRn) ............................................................. 16-12
16.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) ..........................................16-12
16.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn) ............................................ 16-14
16.3.12 UART Autobaud Registers (UABUn/UABLn) .......................................................... 16-14
16.3.13 UART Transmitter FIFO Registers (UTFn) ............................................................... 16-15
16.3.14 UART Receiver FIFO Registers (URFn) ................................................................... 16-16
16.3.15 UART Fractional Precision Divider Control Registers (UFPDn) .............................. 16-17
16.3.16 UART Input Port Registers (UIPn) ............................................................................ 16-17
16.3.17 UART Output Port Command Registers (UOP1n/UOP0n) ....................................... 16-18
16.4 UART Module Signal Definitions ........................................................................................... 16-18
16.5 Operation ................................................................................................................................. 16-19
16.5.1 Transmitter/Receiver Clock Source .............................................................................. 16-19
16.5.1.1 Programmable Divider .................................................................................... 16-20
16.5.1.2 Calculating Baud Rates ................................................................................... 16-20
16.5.1.2.1 CLKIN Baud Rates................................................................................ 16-20
16.5.1.2.2 External Clock........................................................................................ 16-21
16.5.1.2.3 Autobaud Detection ............................................................................... 16-21
16.5.2 Transmitter and Receiver Operating Modes .................................................................16-22
16.5.2.1 Transmitting ................................................................................................... 16-22
16.5.2.2 Receiver .......................................................................................................... 16-24
16.5.2.3 Transmitter FIFO ............................................................................................ 16-25
16.5.2.4 Receiver FIFO ............................................................................................... 16-25
16.5.3 Looping Modes ............................................................................................................. 16-26
16.5.3.1 Automatic Echo Mode .................................................................................... 16-27
16.5.3.2 Local Loop-Back Mode .................................................................................. 16-27
16.5.3.3 Remote Loop-Back Mode ............................................................................... 16-27
16.5.4 Multidrop Mode ............................................................................................................ 16-28
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxiv Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
16.5.5 Bus Operation ............................................................................................................... 16-29
16.5.5.1 Read Cycles .................................................................................................... 16-29
16.5.5.2 Write Cycles ...................................................................................................16-29
16.5.5.3 Interrupt Acknowledge Cycles ....................................................................... 16-29
16.5.6 Programming ................................................................................................................ 16-30
16.5.6.1 UART Module Initialization Sequence .......................................................... 16-30
Chapter 17
General Purpose I/O Module
17.1 Overview .................................................................................................................................... 17-1
17.2 Port Control Registers ................................................................................................................ 17-2
17.2.1 Port A Control Register (PACNT) ..................................................................................17-3
17.2.2 Port B Control Register (PBCNT) .................................................................................. 17-5
17.2.3 Port C Control Register .................................................................................................. 17-8
17.2.4 Port D Control Register (PDCNT) ................................................................................. 17-8
17.3 Data Direction Registers .......................................................................................................... 17-10
17.3.1 Port A Data Direction Register (PADDR) .................................................................... 17-10
17.3.2 Port B Data Direction Register (PBDDR) .................................................................... 17-10
17.3.3 Port C Data Direction Register (PCDDR) .................................................................... 17-11
17.4 Port Data Registers .................................................................................................................. 17-11
17.4.1 Port Data Register (PxDAT) ......................................................................................... 17-11
Chapter 18
Pulse-Width Modulation (PWM) Module
18.1 Overview .................................................................................................................................... 18-1
18.2 PWM Operation ......................................................................................................................... 18-2
18.3 PWM Programming Model ....................................................................................................... 18-2
18.3.1 PWM Control Register (PWCRn) .................................................................................. 18-3
18.3.2 PWM Width Register (PWWDn) ................................................................................... 18-4
Chapter 19
Signal Descriptions
19.1 MCF5272 Block Diagram with Signal Interfaces ..................................................................... 19-1
19.2 Signal List .................................................................................................................................. 19-3
19.3 Address Bus (A[22:0]/SDA[13:0]) .......................................................................................... 19-19
19.4 Data Bus (D[31:0]) .................................................................................................................. 19-19
19.4.1 Dynamic Data Bus Sizing ............................................................................................ 19-19
19.5 Chip Selects (CS7/SDCS, CS[6:0]) ......................................................................................... 19-19
19.6 Bus Control Signals ................................................................................................................. 19-20
19.6.1 Output Enable/Read (OE/RD) ......................................................................................19-20
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxv
Table of Contents (Continued)
Paragraph Page Number Title Number
19.6.2 Byte Strobes (BS[3:0]) ................................................................................................. 19-20
19.6.3 Read/Write (R/W) .........................................................................................................19-21
19.6.4 Transfer Acknowledge (TA/PB5) ................................................................................. 19-22
19.6.5 Hi-Z .............................................................................................................................. 19-22
19.6.6 Bypass ........................................................................................................................... 19-22
19.6.7 SDRAM Row Address Strobe (RAS0) ........................................................................ 19-22
19.6.8 SDRAM Column Address Strobe (CAS0) ................................................................... 19-22
19.6.9 SDRAM Clock (SDCLK) ............................................................................................. 19-22
19.6.10 SDRAM Write Enable (SDWE) ................................................................................. 19-22
19.6.11 SDRAM Clock Enable (SDCLKE) ............................................................................ 19-22
19.6.12 SDRAM Bank Selects (SDBA[1:0]) .......................................................................... 19-23
19.6.13 SDRAM Row Address 10 (A10)/A10 Precharge (A10_PRECHG) .......................... 19-23
19.7 CPU Clock and Reset Signals ..................................................................................................19-23
19.7.1 RSTI ............................................................................................................................. 19-23
19.7.2 DRESETEN .................................................................................................................. 19-23
19.7.3 CPU External Clock (CLKIN) ..................................................................................... 19-23
19.7.4 Reset Output (RSTO) ................................................................................................... 19-23
19.8 Interrupt Request Inputs (INT[6:1]) ......................................................................................... 19-23
19.9 General-Purpose I/O (GPIO) Ports .......................................................................................... 19-24
19.10 UART0 Module Signals and PB[4:0] .................................................................................... 19-24
19.10.1 Transmit Serial Data Output (URT0_TxD/PB0) ........................................................ 19-24
19.10.2 Receive Serial Data Input (URT0_RxD/PB1) ............................................................ 19-25
19.10.3 Clear-to-Send (URT0_CTS/PB2) ............................................................................... 19-25
19.10.4 Request to Send (URT0_RTS/PB3) ............................................................................ 19-25
19.10.5 Clock (URT0_CLK/PB4) ........................................................................................... 19-25
19.11 USB Module Signals and PA[6:0] ......................................................................................... 19-25
19.11.1 USB Transmit Serial Data Output (USB_TP/PA0) .................................................... 19-25
19.11.2 USB Receive Serial Data Input (USB_RP/PA1) ........................................................ 19-25
19.11.3 USB Receive Data Negative (USB_RN/PA2) ............................................................19-25
19.11.4 USB Transmit Data Negative (USB_TN/PA3) ........................................................... 19-26
19.11.5 USB Suspend Driver (USB_SUSP/PA4) .................................................................... 19-26
19.11.6 USB Transmitter Output Enable (USB_TxEN/PA5) ..................................................19-26
19.11.7 USB Rx Data Output (USB_RxD/PA6) ..................................................................... 19-26
19.11.8 USB_D+ and USB_D- ................................................................................................19-26
19.11.9 USB_CLK ..................................................................................................................19-26
19.11.10 INT1/USB Wake-on-Ring (USB_WOR) ................................................................. 19-26
19.12 Timer Module Signals ............................................................................................................19-27
19.12.1 Timer Input 0 (TIN0) .................................................................................................. 19-27
19.12.2 Timer Output (TOUT0)/PB7 ...................................................................................... 19-27
19.12.3 Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2) .................................... 19-27
19.12.4 Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1) .............................. 19-27
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxvi Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
19.13 Ethernet Module Signals ........................................................................................................ 19-27
19.13.1 Transmit Clock (E_TxCLK) ....................................................................................... 19-27
19.13.2 Transmit Data (E_TxD0) ............................................................................................19-28
19.13.3 Collision (E_COL) ..................................................................................................... 19-28
19.13.4 Receive Data Valid (E_RxDV) ................................................................................... 19-28
19.13.5 Receive Clock (E_RxCLK) ........................................................................................ 19-28
19.13.6 Receive Data (E_RxD0) ............................................................................................. 19-28
19.13.7 Transmit Enable (E_TxEN) ........................................................................................19-28
19.13.8 Transmit Data (E_TxD[3:1]/PB[10:8]) ...................................................................... 19-28
19.13.9 Receive Data (E_RxD[3:1]/PB[13:11]) ......................................................................19-28
19.13.10 Receive Error (E_RxER/PB14) ................................................................................ 19-29
19.13.11 Management Data Clock (E_MDC/PB15) ............................................................... 19-29
19.13.12 Management Data (E_MDIO) .................................................................................. 19-29
19.13.13 Transmit Error (E_TxER) .........................................................................................19-29
19.13.14 Carrier Receive Sense (E_CRS) ............................................................................... 19-29
19.14 PWM Module Signals (PWM_OUT0–PWM_OUT2]) ......................................................... 19-29
19.15 Queued Serial Peripheral Interface (QSPI) Signals ............................................................... 19-29
19.15.1 QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL) .................................... 19-30
19.15.2 QSPI Synchronous Serial Data Input (QSPI_Din) ..................................................... 19-30
19.15.3 QSPI Serial Clock (QSPI_CLK/BUSW1) .................................................................. 19-30
19.15.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0) ................................... 19-30
19.15.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................................ 19-30
19.15.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............................. 19-30
19.15.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3) ............................ 19-30
19.16 Physical Layer Interface Controller TDM Ports and UART 1 .............................................. 19-31
19.16.1 GCI/IDL TDM Port 0. ................................................................................................ 19-31
19.16.1.1 Frame Sync (FSR0/FSC0/PA8) .................................................................... 19-31
19.16.1.2 D-Channel Grant (DGNT0/PA9) .................................................................. 19-31
19.16.1.3 Data Clock (DCL0/URT1_CLK) .................................................................. 19-31
19.16.1.4 Serial Data Input (DIN0/URT1_RxD) ..........................................................19-31
19.16.1.5 UART1 CTS (URT1_CTS/QSPI_CS2) ........................................................ 19-32
19.16.1.6 UART1 RTS (URT1_RTS
19.16.1.7 Serial Data Output (DOUT0/URT1_TxD) ................................................... 19-32
19.16.1.8 D-Channel Request(DREQ0/PA10) .............................................................19-32
19.16.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11) ........................................................ 19-32
19.16.2 GCI/IDL TDM Port 1 ................................................................................................. 19-32
19.16.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT) ............................................... 19-32
19.16.2.2 GCI/IDL Data Out (DOUT1) ....................................................................... 19-33
19.16.2.3 GCI/IDL Data In (DIN1) .............................................................................. 19-33
19.16.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ............................................... 19-33
19.16.2.5 D-Channel Request (DREQ1/PA14) ............................................................19-33
/INT5) ................................................................. 19-32
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxvii
Table of Contents (Continued)
Paragraph Page Number Title Number
19.16.2.6 D-Channel Grant (DGNT1_INT6/PA15_INT6) ...........................................19-33
19.16.3 GCI/IDL TDM Ports 2 and 3 ...................................................................................... 19-34
19.16.3.1 GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) .........................................19-34
19.16.3.2 GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13) .........................................19-34
19.16.3.3 QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7 (PA7/DOUT3/QSPI_CS3) ... 19-34
19.16.3.4 INT4 and Port 3 GCI/IDL Data In (INT4/DIN3) ......................................... 19-35
19.17 JTAG Test Access Port and BDM Debug Port ...................................................................... 19-35
19.17.1 Test Clock (TCK/PSTCLK) ........................................................................................ 19-35
19.17.2 Test Mode Select and Force Breakpoint (TMS/BKPT) ..............................................19-35
19.17.3 Test and Debug Data Out (TDO/DSO) ...................................................................... 19-36
19.17.4 Test and Debug Data In (TDI/DSI) ............................................................................ 19-36
19.17.5 JTAG TRST and BDM Data Clock (TRST/DSCLK) ................................................ 19-36
19.17.6 Freescale Test Mode Select (MTMOD) ..................................................................... 19-36
19.17.7 Debug Transfer Error Acknowledge (TEA) ...............................................................19-36
19.17.8 Processor Status Outputs (PST[3:0]) ..........................................................................19-36
19.17.9 Debug Data (DDATA[3:0]) ........................................................................................ 19-37
19.17.10 Device Test Enable (TEST) ......................................................................................19-37
19.18 Operating Mode Configuration Pins ......................................................................................19-37
19.19 Power Supply Pins ................................................................................................................. 19-38
Chapter 20
Bus Operation
20.1 Features ...................................................................................................................................... 20-1
20.2 Bus and Control Signals ............................................................................................................ 20-1
20.2.1 Address Bus (A[22:0]) ................................................................................................... 20-2
20.2.2 Data Bus (D[31:0]) ......................................................................................................... 20-2
20.2.3 Read/Write (R/W) ...........................................................................................................20-2
20.2.4 Transfer Acknowledge (TA) ........................................................................................... 20-2
20.2.5 Transfer Error Acknowledge (TEA) ............................................................................... 20-3
20.3 Bus Exception: Double Bus Fault .............................................................................................. 20-3
20.4 Bus Characteristics .................................................................................................................... 20-3
20.5 Data Transfer Mechanism ..........................................................................................................20-4
20.5.1 Bus Sizing ....................................................................................................................... 20-4
20.6 External Bus Interface Types ..................................................................................................... 20-7
20.6.1 Interface for FLASH/SRAM Devices with Byte Strobes ............................................... 20-8
20.6.2 Interface for FLASH/SRAM Devices without Byte Strobes ........................................20-12
20.7 Burst Data Transfers ................................................................................................................ 20-17
20.8 Misaligned Operands ............................................................................................................... 20-18
20.9 Interrupt Cycles ........................................................................................................................ 20-19
20.10 Bus Errors .............................................................................................................................. 20-19
20.11 Bus Arbitration .......................................................................................................................20-21
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxviii Freescale Semiconductor
Table of Contents (Continued)
Paragraph Page Number Title Number
20.12 Reset Operation ...................................................................................................................... 20-21
20.12.1 Master Reset ............................................................................................................... 20-22
20.12.2 Normal Reset .............................................................................................................. 20-23
20.12.3 Software Watchdog Timer Reset Operation ............................................................... 20-24
20.12.4 Soft Reset Operation ................................................................................................... 20-25
Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
21.1 Overview .................................................................................................................................... 21-1
21.2 JTAG Test Access Port and BDM Debug Port .......................................................................... 21-2
21.3 TAP Controller ........................................................................................................................... 21-3
21.4 Boundary Scan Register ............................................................................................................. 21-4
21.5 Instruction Register ....................................................................................................................21-7
21.6 Restrictions ................................................................................................................................ 21-8
21.7 Non-IEEE 1149.1 Operation ......................................................................................................21-8
Chapter 22
Mechanical Data
22.1 Pinout ......................................................................................................................................... 22-1
22.2 Package Dimensions .................................................................................................................. 22-2
Chapter 23
Electrical Characteristics
23.1 Maximum Ratings ...................................................................................................................... 23-1
23.1.1 Supply, Input Voltage, and Storage Temperature ........................................................... 23-1
23.1.2 Operating Temperature ...................................................................................................23-2
23.1.3 Resistance .......................................................................................................................23-2
23.2 DC Electrical Specifications ...................................................................................................... 23-3
23.2.1 Output Driver Capability and Loading ...........................................................................23-3
23.3 AC Electrical Specifications ...................................................................................................... 23-5
23.3.1 Clock Input and Output Timing Specifications .............................................................. 23-5
23.3.2 Processor Bus Input Timing Specifications ....................................................................23-6
23.3.3 Processor Bus Output Timing Specifications .................................................................23-8
23.4 Debug AC Timing Specifications ............................................................................................ 23-13
23.5 SDRAM Interface Timing Specifications ................................................................................ 23-14
23.6 Fast Ethernet AC Timing Specifications ................................................................................. 23-17
23.6.1 MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER, and E_RxCLK) ........ 23-17
23.6.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER, E_TxCLK) .............. 23-18
23.6.3 MII Async Inputs Signal Timing (CRS and COL) .......................................................23-19
23.6.4 MII Serial Management Channel Timing (MDIO and MDC) ..................................... 23-20
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxix
Table of Contents (Continued)
Paragraph Page Number Title Number
23.7 Timer Module AC Timing Specifications ................................................................................23-21
23.8 UART Modules AC Timing Specifications ............................................................................. 23-22
23.9 PLIC Module: IDL and GCI Interface Timing Specifications ................................................23-23
23.10 General-Purpose I/O Port AC Timing Specifications ............................................................23-28
23.11 USB Interface AC Timing Specifications ..............................................................................23-29
23.12 IEEE 1149.1 (JTAG) AC Timing Specifications ................................................................... 23-30
23.13 QSPI Electrical Specifications ............................................................................................... 23-31
23.14 PWM Electrical Specifications .............................................................................................. 23-32
Appendix A
List of Memory Maps
A.1 List of Memory Map Tables............................................................................................................ A-1
Appendix B
Buffering and Impedance Matching
Index 1
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxx Freescale Semiconductor
List of Tables
Tabl e Page Number Title Number
2-1 CCR Field Descriptions .......................................................................................................... 2-6
2-2 MOVEC Register Map............................................................................................................. 2-7
2-3 Status Field Descriptions ........................................................................................................2-8
2-4 Integer Data Formats ..............................................................................................................2-9
2-5 ColdFire Effective Addressing Modes..................................................................................2-12
2-6 Notational Conventions........................................................................................................2-13
2-7 User-Mode Instruction Set Summary....................................................................................2-15
2-8 Supervisor-Mode Instruction Set Summary ......................................................................... 2-18
2-9 Misaligned Operand References..........................................................................................2-19
2-10 Move Byte and Word Execution Times.................................................................................2-20
2-11 Move Long Execution Times................................................................................................2-21
2-12 Move Execution Times......................................................................................................... 2-21
2-13 One-Operand Instruction Execution Times...........................................................................2-22
2-14 Two-Operand Instruction Execution Times...........................................................................2-22
2-13oove Tcec
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxxi
List of Tables (Continued)
Tabl e Page Number Title Number
5-10 DBMR Field Descriptions......................................................................................................5-12
5-11 Access Size and Operand Data Location .............................................................................5-12
5-12 PBR Field Descriptions .........................................................................................................5-13
5-13 PBMR Field Descriptions ......................................................................................................5-13
5-14 TDR Field Descriptions .........................................................................................................5-14
5-15 Receive BDM Packet Field Description ................................................................................5-18
5-16 Transmit BDM Packet Field Description ...............................................................................5-18
5-17 BDM Command Summary ....................................................................................................5-19
5-18 BDM Field Descriptions.........................................................................................................5-20
5-19 Control Register Map ............................................................................................................ 5-30
5-20 Definition of DRc Encoding—Read.......................................................................................5-32
5-21 DDATA[3:0]/CSR[BSTAT] Breakpoint Response .................................................................5-34
5-22 PST/DDATA Specification for User-Mode Instructions .........................................................5-37
5-23 PST/DDATA Specification for Supervisor-Mode Instructions................................................5-40
6-1 SIM Registers .........................................................................................................................6-3
6-2 MBAR Field Descriptions .......................................................................................................6-4
6-3 SCR Field Descriptions...........................................................................................................6-5
6-4 SPR Field Descriptions ...........................................................................................................6-6
6-5 PMR Field Descriptions...........................................................................................................6-8
6-6 USB and USART Power Down Modes ...................................................................................6-9
6-7 Exiting Sleep and Stop Modes..............................................................................................6-10
6-8 DIR Field Descriptions ..........................................................................................................6-11
6-9 WRRR Field Descriptions .....................................................................................................6-12
6-10 WIRR Field Descriptions.......................................................................................................6-13
6-11 WER Field Descriptions ........................................................................................................6-13
7-1 Interrupt Controller Registers..................................................................................................7-2
7-2 Interrupt and Power Management Register Mnemonics.........................................................7-3
7-3 ICR Field Descriptions ............................................................................................................7-4
7-4 ISR Field Descriptions.............................................................................................................7-6
7-5 PITR Field Descriptions ..........................................................................................................7-7
7-6 PIWR Field Descriptions .........................................................................................................7-8
7-7 PIVR Field Descriptions ..........................................................................................................7-9
7-8 MCF5272 Interrupt Vector Table...........................................................................................7-10
8-1 CSCR and CSOR Values after Reset.....................................................................................8-2
8-2 CSBRn Field Descriptions....................................................................................................... 8-3
8-3 Output Read/Write Strobe Levels versus Chip Select EBI Code............................................8-4
8-4 Chip Select Memory Address Decoding Priority .....................................................................8-5
8-5 CSORn Field Descriptions ......................................................................................................8-5
9-1 SDRAM Controller Signal Descriptions................................................................................... 9-2
9-2 Connecting BS[3:0] to DQMx..................................................................................................9-4
9-3 Configurations for 16-Bit Data Bus..........................................................................................9-4
9-4 Configurations for 32-Bit Data Bus..........................................................................................9-4
9-5 Internal Address Multiplexing (16-Bit Data Bus) .....................................................................9-5
9-6 Internal Address Multiplexing (32-Bit Data Bus) .....................................................................9-5
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxxii Freescale Semiconductor
List of Tables (Continued)
Tabl e Page Number Title Number
9-7 SDCR Field Descriptions ........................................................................................................9-7
9-8 SDTR Field Descriptions......................................................................................................... 9-8
9-9 SDRAM Controller Performance, 32-Bit Port, (RCD = 0, RP = 1) or (RCD = 1, RP = 0)......9-10
9-10 SDRAM Controller Performance, 32–Bit Port, (RCD = 0, RP = 0)........................................9-10
9-11 SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port..........................................9-11
9-12 SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=1) or (RCD=1, RP = 0)9-11
9-13 SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=0).............................................9-12
10-1 DMA Data Transfer Matrix ....................................................................................................10-1
10-2 DMR Field Descriptions ........................................................................................................10-2
10-3 DIR Field Descriptions ..........................................................................................................10-4
11-1 MII Mode ...............................................................................................................................11-3
11-2 Seven-Wire Mode Configuration...........................................................................................11-4
11-3 Ethernet Address Recognition ..............................................................................................11-7
11-4 Transmission Errors..............................................................................................................11-9
11-5 Reception Errors ...................................................................................................................11-9
11-6 FEC Register Memory Map.................................................................................................11-10
11-7 ECR Field Descriptions.......................................................................................................11-11
11-8 EIR Field Descriptions.........................................................................................................11-12
11-9 EIMR Register Field Descriptions .......................................................................................11-13
11-10 IVSR Field Descriptions ......................................................................................................11-14
11-11 RDAR Register Field Descriptions......................................................................................11-15
11-12 TDAR Field Descriptions.....................................................................................................11-16
11-13 MMFR Field Descriptions.................................................................................................... 11-17
11-14 MSCR Field Descriptions....................................................................................................11-18
11-15 Programming Examples for MSCR Register.......................................................................11-19
11-16 FRBR Field Descriptions.....................................................................................................11-19
11-17 FRSR Field Descriptions.....................................................................................................11-20
11-18 TFWR Field Descriptions ....................................................................................................11-21
11-19 TFSR Field Descriptions .....................................................................................................11-22
11-20 RCR Field Descriptions....................................................................................................... 11-23
11-21 MFLR Field Descriptions.....................................................................................................11-24
11-22 TCR Field Descriptions .......................................................................................................11-25
11-23 MALR Field Descriptions.....................................................................................................11-26
11-24 MAUR Field Descriptions....................................................................................................11-27
11-25 HTUR Field Descriptions.....................................................................................................11-28
11-26 HTLR Field Descriptions .....................................................................................................11-29
11-27 ERDSR Field Descriptions..................................................................................................11-30
11-28 ETDSR Field Descriptions ..................................................................................................11-31
11-29 EMRBR Field Descriptions..................................................................................................11-32
11-30 Hardware Initialization.........................................................................................................11-33
11-31 ETHER_EN = 0...................................................................................................................11-33
11-32 User Initialization Process (before ETHER_EN).................................................................11-33
11-33 User Initialization (after ETHER_EN)..................................................................................11-34
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxxiii
List of Tables (Continued)
Tabl e Page Number Title Number
11-34 RxBD Field Descriptions .....................................................................................................11-36
11-35 TxBD Field Descriptions......................................................................................................11-37
12-1 USB Device Requests...........................................................................................................12-5
12-2 USB Memory Map.................................................................................................................12-7
12-3 FNR Field Descriptions .........................................................................................................12-9
12-4 FNMR Field Descriptions ......................................................................................................12-9
12-5 RFMR Field Descriptions ....................................................................................................12-10
12-6 RFMMR Field Descriptions .................................................................................................12-11
12-7 FAR Field Descriptions .......................................................................................................12-11
12-8 ASR Field Descriptions .......................................................................................................12-12
12-9 SPECR Field Descriptions ..................................................................................................12-14
12-10 EP0SR Field Descriptions...................................................................................................12-14
12-11 IEP0CFG Field Descriptions ............................................................................................... 12-15
12-12 EP0CTL Field Descriptions.................................................................................................12-17
12-13 EPnCTL Field Descriptions.................................................................................................12-20
12-14 EP0IMR and EP0ISR Field Descriptions ............................................................................12-22
12-15 EPnISR Field Descriptions..................................................................................................12-25
12-16 EPnIMR Field Descriptions .................................................................................................12-26
12-17 EPnDR Field Descriptions...................................................................................................12-27
12-18 EPnDPR Field Descriptions ................................................................................................12-28
12-19 USB FIFO Access Timing ...................................................................................................12-30
12-20 Example FIFO Setup ..........................................................................................................12-32
13-1 PLIC Module Memory Map .................................................................................................13-13
13-2 P0CR–P3CR Field Descriptions .........................................................................................13-19
13-3 PLCR Field Description.......................................................................................................13-20
13-4 P0ICR–P3ICR Field Descriptions .......................................................................................13-21
13-5 P0PSR–P3PSR Field Descriptions.....................................................................................13-22
13-6 PASR Field Descriptions..................................................................................................... 13-23
13-7 P0GMR–P3GMR Field Descriptions...................................................................................13-24
13-8 P0GMT–P3GMT Field Descriptions.................................................................................... 13-25
13-9 PGMTA Field Descriptions..................................................................................................13-26
13-10 PGMTS Field Descriptions..................................................................................................13-27
13-11 P0GCIR–P3GCIR Field Descriptions..................................................................................13-28
13-12 P0GCIT–P3GCIT Field Descriptions...................................................................................13-29
13-13 PGCITSR Field Descriptions............................................................................................... 13-30
13-14 PDCSR Field Descriptions..................................................................................................13-31
13-15 PDRQR Field Descriptions..................................................................................................13-32
13-16 P0SDR–P3SDR Field Descriptions.....................................................................................13-33
13-17 PCSR Field Descriptions.....................................................................................................13-34
14-1 QSPI Input and Output Signals and Functions .....................................................................14-3
14-2 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate .......................................14-7
14-3 QMR Field Descriptions ........................................................................................................14-9
14-4 QDLYR Field Descriptions ..................................................................................................14-11
14-5 QWR Field Descriptions......................................................................................................14-12
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxxiv Freescale Semiconductor
List of Tables (Continued)
Tabl e Page Number Title Number
14-6 QIR Field Descriptions ........................................................................................................ 14-13
14-7 QCR0–QCR15 Field Descriptions.......................................................................................14-15
15-1 TMRn Field Descriptions....................................................................................................... 15-3
15-2 TERn Field Descriptions .......................................................................................................15-5
16-1 UART Module Programming Model ......................................................................................16-3
16-2 UMR1n Field Descriptions ....................................................................................................16-5
16-3 UMR2n Field Descriptions ....................................................................................................16-6
16-4 USRn Field Descriptions.......................................................................................................16-7
16-5 UCSRn Field Descriptions ....................................................................................................16-8
16-6 UCRn Field Descriptions....................................................................................................... 16-9
16-7 UIPCRn Field Descriptions .................................................................................................16-11
16-8 UACRn Field Descriptions ..................................................................................................16-12
16-9 UISRn/UIMRn Field Descriptions........................................................................................ 16-13
16-10 UTFn Field Descriptions......................................................................................................16-15
16-11 URFn Field Descriptions .....................................................................................................16-16
16-12 UFPDn Field Descriptions...................................................................................................16-17
16-13 UIPn Field Descriptions.......................................................................................................16-17
16-14 UOP1/UOP0 Field Descriptions..........................................................................................16-18
16-15 UART Module Signals.........................................................................................................16-19
16-16 Transmitter FIFO Status Bits...............................................................................................16-25
16-17 Receiver FIFO Status Bits...................................................................................................16-26
17-1 GPIO Signal Multiplexing ......................................................................................................17-1
17-2 GPIO Port Register Memory Map ......................................................................................... 17-2
17-3 PACNT Field Descriptions ....................................................................................................17-3
17-4 Port A Control Register Function Bits ...................................................................................17-5
17-5 PBCNT Field Descriptions ....................................................................................................17-6
17-6 Port B Control Register Function Bits ...................................................................................17-7
17-7 PDCNT Field Descriptions ....................................................................................................17-8
17-8 Port D Control Register Function Bits ...................................................................................17-9
17-9 PADDR Field Descriptions..................................................................................................17-10
18-1 PWM Module Memory Map...................................................................................................18-2
18-2 PWCRn Field Descriptions....................................................................................................18-3
18-3 PWWDn Field Descriptions................................................................................................... 18-4
19-1 Signal Descriptions Sorted by Function ................................................................................19-3
19-2 Signal Name and Description by Pin Number..................................................................... 19-11
19-3 Byte Strobe Operation for 32-Bit Data Bus.........................................................................19-20
19-4 Byte Strobe Operation for 16-Bit Data Bus—SRAM Cycles19-21 19-5 Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles19-21
19-6 Connecting BS[3:0] to DQMx..............................................................................................19-21
19-7 Processor Status Encoding.................................................................................................19-37
19-8 MCF5272 Bus Width Selection19-38
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxxv
List of Tables (Continued)
Tabl e Page Number Title Number
19-9 MCF5272 CS0 Memory Bus Width Selection19-38 19-10 MCF5272 High Impedance Mode Selection19-38
20-1 ColdFire Bus Signal Summary.............................................................................................20-1
20-2 Chip Select Memory Address Decoding Priority20-4
20-3 Byte Strobe Operation for 32-Bit Data Bus...........................................................................20-6
20-4 Byte Strobe Operation for 16-Bit Data Bus—SRAM Cycles20-6 20-5 Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles20-6
20-6 Data Bus Requirement for Read/Write Cycles......................................................................20-7
20-7 External Bus Interface Codes for CSBRs .............................................................................20-8
21-1 JTAG Signals ........................................................................................................................21-2
21-2 Instructions............................................................................................................................21-7
23-1 Maximum Supply, Input Voltage and Storage Temperature ................................................. 23-1
23-2 Operating Temperature.........................................................................................................23-2
23-3 Thermal Resistance ..............................................................................................................23-2
23-4 DC Electrical Specifications ................................................................................................. 23-3
23-5 I/O Driver Capability..............................................................................................................23-3
23-6 Clock Input and Output Timing Specifications ......................................................................23-5
23-7 Processor Bus Input Timing Specifications........................................................................... 23-6
23-8 Processor Bus Output Timing Specifications........................................................................23-8
23-9 Debug AC Timing Specification ..........................................................................................23-13
23-10 SDRAM Interface Timing Specifications .............................................................................23-14
23-11 MII Receive Signal Timing ..................................................................................................23-17
23-12 MII Transmit Signal Timing .................................................................................................23-18
23-13 MII Async Inputs Signal Timing...........................................................................................23-19
23-14 MII Serial Management Channel Timing.............................................................................23-20
23-15 Timer Module AC Timing Specifications ............................................................................. 23-21
23-16 UART Modules AC Timing Specifications........................................................................... 23-22
23-17 IDL Master Mode Timing, PLIC Ports 1, 2, and 3 ............................................................... 23-23
23-18 IDL Slave Mode Timing, PLIC Ports 0–3 ............................................................................23-24
23-19 GCI Slave Mode Timing, PLIC Ports 0–3............................................................................23-25
23-20 GCI Master Mode Timing, PLIC PORTs 1, 2, 3 .................................................................. 23-26
23-21 General-Purpose I/O Port AC Timing Specifications .......................................................... 23-28
23-22 USB Interface AC Timing Specifications............................................................................. 23-29
23-23 IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................................23-30
23-24 QSPI Modules AC Timing Specifications............................................................................23-31
23-25 PWM Modules AC Timing Specifications............................................................................ 23-32
A-1 On-Chip Module Base Address Offsets from MBAR...............................................................A-1
A-2 CPU Space Registers Memory Map .......................................................................................A-2
A-3 On-Chip Peripherals and Configuration Registers Memory Map............................................A-2
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxxvi Freescale Semiconductor
List of Tables (Continued)
Tabl e Page Number Title Number
A-4 Interrupt Control Register Memory Map..................................................................................A-2
A-5 Chip Select Register Memory Map .........................................................................................A-3
A-6 GPIO Port Register Memory Map ...........................................................................................A-3
A-7 QSPI Module Memory Map.....................................................................................................A-4
A-8 PWM Module Memory Map.....................................................................................................A-4
A-9 DMA Module Memory Map .....................................................................................................A-4
A-10 UART0 Module Memory Map..................................................................................................A-5
A-11 UART1 Module Memory Map..................................................................................................A-6
A-12 SDRAM Controller Memory Map.............................................................................................A-7
A-13 Timer Module Memory Map ....................................................................................................A-7
A-14 PLIC Module Memory Map .....................................................................................................A-8
A-15 Ethernet Module Memory Map................................................................................................A-9
A-16 USB Module Memory Map....................................................................................................A-10
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxxvii
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xxxviii Freescale Semiconductor
MCF5272 ColdFire® Integrated Microprocessor
User’s Manual
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Y our printed copy may be an earlier revision. T o ve rify you have the latest information available, refer to:
http://www.freescale.com/
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Document Revision History
Rev. No. Substantive Change(s)
2.1 Updated to meet Freescale identity guidelines.
3 • Formatting, layout, spelling, and grammar corrections.
• Corrected the TxFIFO bit description In Table 16-9 (was “Once set, this bit is cleared by reading UTBn”, is “After being set, this bit is cleared by writing UTBn”).
• Corrected Figure 20-12 (OE second SDCLK clock cycle).
• Corrected Figure 20-13 (R/W asserting on the second SDCLK clock cycle).
• Corrected Figure 20-16 (OE second SDCLK clock cycle).
• Corrected Figure 20-17 (R/W asserting on the second SDCLK clock cycle).
signal was asserting on the third SDCLK clock cycle, is asserting on the
and BS signals were asserting on the third SDCLK clock cycle, are
signal was asserting on the third SDCLK clock cycle, is asserting on the
and BS signals were asserting on the third SDCLK clock cycle, are
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xxxix
About This Book
The primary objective of this user’s manual is to define the functionality of the MCF5272 processors for use by software and hardware developers.
The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure he is using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com.
Audience
This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5272. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire® architecture.
Organization
Following is a summary and brief description of the major sections of this manual:
• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in the MCF5272, focussing in particular on new features.
• Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the MCF5272. The chapter describes the organization of the Version 2 (V2) ColdFire 5200 processor core and an overview of the program-visible registers (the programming model) as they are implemented on the MCF5272. It also includes a full description of exception handling and a table of instruction timings.
• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5272 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).
• Chapter 4, “Local Memory.” This chapter describes the MCF5272 implementation of the ColdFire V2 local memory specification. It consists of three major sections, as follows.
— Section 4.3, “SRAM Overview,” describes the MCF5272 on-chip static RAM (SRAM)
implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM.
— Section 4.4, “ROM Overview,” describes the MCF5272 on-chip static ROM. The ROM
module contains tabular data that the ColdFire core can access in a single cycle.
— Section 4.5, “Instruction Cache Overview,” describes the MCF5272 cache implementation,
including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xl Freescale Semiconductor
• Chapter 5, “Debug Support,” describes the Revision A hardware debug support in the MCF5272.
• Chapter 6, “System Integration Module (SIM),” describes the SIM programming model, bus arbitration, power management, and system-protection functions for the MCF5272.
• Chapter 7, “Interrupt Controller,” describes operation of the interrupt controller portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme.
• Chapter 8, “Chip Select Module,” describes the MCF5272 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers.
• Chapter 9, “SDRAM Controller,” describes configuration and operation of the synchronous DRAM controller component of the SIM, including a general description of signals involved in SDRAM operations. It provides interface information for memory configurations using most common SDRAM devices for both 16- and 32-bit-wide data buses. The chapter concludes with signal timing diagrams.
• Chapter 10, “DMA Controller,” provides an overview of the MCF5272’s one-channel DMA controller intended for memory-to-memory block data transfers. This chapter describes in detail its signals, registers, and operating modes.
• Chapter 11, “Ethernet Module,” describes the MCF5272 fast Ethernet media access controller (MAC). This chapter begins with a feature-set overview, a functional block diagram, and transceiver connection information for both MII and seven-wire serial interfaces. The chapter concludes with detailed descriptions of operation and the programming model.
• Chapter 12, “Universal Serial Bus (USB),” provides an overview of the USB module of the MCF5272, including detailed operation information and the USB programming model. Connection examples and circuit board layout considerations are also provided.
• The USB Specification, Revision 1.1 is a recommended supplement to this chapter. It can be downloaded from http://www.usb.org. Chapter 2 of this specification, Terms and Abbreviations, provides definitions of many of the words found here.
• Chapter 13, “Physical Layer Interface Controller (PLIC),” provides detailed information about the MCF5272’s physical layer interface controller, a module intended to support ISDN applications. The chapter begins with a description of operation and a series of related block diagrams starting with a high-level overview. Each successive diagram depicts progressively more internal detail. The chapter then describes timing generation and the programming model and concludes with three application examples.
• Chapter 14, “Queued Serial Peripheral Interface (QSPI) Module,” provides a feature-set overview and description of operation, including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram.
• Chapter 15, “Timer Module,” describes configuration and operation of the four general-purpose timer modules, timer 0, 1, 2 and 3.
• Chapter 16, “UART Modules,” describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5272, including example register values for typical configurations.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xli
• Chapter 17, “General Purpose I/O Module,” describes the operation and programming model of the three general purpose I/O (GPIO) ports on the MCF5272. The chapter details pin assignment, direction-control, and data registers.
• Chapter 18, “Pulse-Width Modulation (PWM) Module,” describes the configuration and operation of the pulse-width modulation (PWM) module. It includes a block diagram, programming model, and timing diagram.
• Chapter 19, “Signal Descriptions,” provides a listing and brief description of all the MCF5272 signals. Specifically , it shows which are inputs or outputs, how they are multiplexed, and the state of each signal at reset. The first listing is organized by function, with signals appearing alphabetically within each functional group. This is followed by a second listing sorted by pin number.
• Chapter 20, “Bus Operation,” describes the functioning of the bus for data-transfer operations, error conditions, bus arbitration, and reset operations. It includes detailed timing diagrams showing signal interaction. Operation of the bus is defined for transfers initiated by the MCF5272 as a bus master. The MCF5272 does not support external bus masters. Note that Chapter 9, “SDRAM
Controller,” describes DRAM cycles.
• Chapter 21, “IEEE 1149.1 T est Access Port (JTAG),” describes configuration and operation of the MCF5272 Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE 1149.1 standard and provides additional information specific to the MCF5272. For internal details and sample applications, see the IEEE 1149.1 document.
• Chapter 22, “Mechanical Data,” provides a functional pin listing and package diagram for the MCF5272.
• Chapter 23, “Electrical Characteristics,” describes AC and DC electrical specifications and thermal characteristics for the MCF5272. Because additional speeds may have become available since the publication of this book, consult Freescale’s ColdFire web page,
http://www.freescale.com, to confirm that this is the latest information.
This manual includes the following two appendixes:
• Appendix A, “List of Memory Maps,” provides the entire address-map for MCF5272 memory-mapped registers.
• Appendix B, “Buffering and Impedance Matching,” provides some suggestions regarding interface circuitry between the MCF5272 and SDRAMs.
This manual also includes an index.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xlii Freescale Semiconductor
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture.
General Information
The following documentation provides useful information about the Cold
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xliii
Conventions
This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics In code and tables, instruction mnemonics are shown in lowercase. italics Italics indicate variable command parameters.
Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don’t care. n Used to express an undefined numerical value
1
¬ NOT logical operator & AND logical operator | OR logical operator
1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xliv Freescale Semiconductor
Acronyms and Abbreviations
Table i lists acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term Meaning
ADC Analog-to-digital conversion
ALU Arithmetic logic unit
AVEC Autovector
BDM Background debug mode
BIST Built-in self test
BSDL Boundary-scan description language
CODEC Code/decode
DAC Digital-to-analog conversion
DMA Direct memory access
DSP Digital signal processing
EA Effective address
EDO Extended data output (DRAM)
FIFO First-in, first-out
GPIO General-purpose I/O
2
C Inter-integrated circuit
I
IEEE Institute for Electrical and Electronics Engineers
IFP Instruction fetch pipeline
IPL Interrupt priority level
JEDEC Joint Electron Device Engineering Council
JTAG Joint Test Action Group
LIFO Last-in, first-out
LRU Least recently used
LSB Least-significant byte
lsb Least-significant bit
MAC Multiply accumulate unit, also Media access controller
MBAR Memory base address register
MSB Most-significant byte
msb Most-significant bit
Mux Multiplex
NOP No operation
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xlv
Table i. Acronyms and Abbreviated Terms (continued)
Term Meaning
OEP Operand execution pipeline
PC Program counter
PCLK Processor clock
PLIC Physical layer interface controller
PLL Phase-locked loop
PLRU Pseudo least recently used
POR Power-on reset
PQFP Plastic quad flat pack
PWM Pulse-width modulation
QSPI Queued serial peripheral interface
RISC Reduced instruction set computing
Rx Receive
SIM System integration module
SOF Start of frame
TAP Test access port
TTL Transistor transistor logic
Tx Transmit
UART Universal asynchronous/synchronous receiver transmitter
USB Universal serial bus
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xlvi Freescale Semiconductor
Terminology Conventions
Table ii shows terminology conventions used throughout this document.
Table ii. Notational Conventions
Instruction Operand Syntax
Opcode Wildcard
cc Logical condition (example: NE for not equal)
Register Specifications
An Any address register n (example: A3 is address register 3)
Ay,Ax Source and destination address registers, respectively
Dn Any data register n (example: D5 is data register 5)
Dy,Dx Source and destination data registers, respectively
Rc Any control register (example VBR is the vector base register)
Rm MAC registers (ACC, MAC, MASK)
Rn Any address or data register
Rw Destination register w (used for MAC instructions only)
Ry,Rx Any source and destination registers, respectively
Xi index register i (can be an address or data register: Ai, Di)
Register Names
ACC MAC accumulator register
CCR Condition code register (lower byte of SR)
MACSR MAC status register
MASK MAC mask register
PC Program counter
SR Status register
Port Name
DDATA Debug data port
PST Processor status port
Miscellaneous Operands
#<data> Immediate data following the 16-bit operation word of the instruction
<ea> Effective address
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xlvii
Table ii. Notational Conventions (continued)
Instruction Operand Syntax
<ea>y,<ea>x Source and destination effective addresses, respectively
<label> Assembly language program label
<list> List of registers for MOVEM instruction (example: D3–D0)
<shift> Shift operation: shift left (<<), shift right (>>)
<size> Operand data size: byte (B), word (W), longword (L)
bc Both instruction and data caches
dc Data cache
ic Instruction cache
# <vector> Identifies the 4-bit vector number for trap instructions
<> identifies an indirect data address referencing memory
<xxx> identifies an absolute address referencing memory
dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+ Arithmetic addition or postincrement indicator
– Arithmetic subtraction or predecrement indicator
x Arithmetic multiplication
/ Arithmetic division
~ Invert; operand is logically complemented
& Logical AND
| Logical OR
^ Logical exclusive OR
<< Shift left (example: D0 << 3 is shift D0 left 3 bits)
>> Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→ Source operand is moved to destination operand
←→ Two operands are exchanged
sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition> then <operations> else <operations>
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xlviii Freescale Semiconductor
Table ii. Notational Conventions (continued)
Instruction Operand Syntax
Subfields and Qualifiers
{} Optional operation
() Identifies an indirect address
d
n
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
Address Calculated effective address (pointer)
Bit Bit selection (example: Bit 3 of D0)
lsb Least significant bit (example: lsb of D0)
LSB Least significant byte
LSW Least significant word
msb Most significant bit
MSB Most significant byte
MSW Most significant word
Condition Code Register Bit Names
CCarry
N Negative
VOverflow
X Extend
ZZero
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor xlix
Register Identifiers
Register identifiers in this user’s manual were changed from names used in early versions of the manual released under non-disclosure agreement (NDA). Because a significant amount of collateral documentation, such as source code, was developed using the old register names, Table iii through
Table xvi list the new register names and mnemonics as they should appear in the data book, along with
the old ones. Identifiers that have changed are displayed in boldface type. Those that have not changed are marked “no change” in the ‘New Mnemonic’ column.
Table iii. On-Chip Peripherals and Configuration Registers Memory Map
MBAR Offset
0x0000 Module Base Address Register, Read Only MBAR No change
0x0004 System Configuration Register SCR No change
0x0006 System Protection Register SPR No change
0x0008 Power Management Register PMR No change
0x000E Activate Low Power Register ALPR No change
0x0010 Device Identification Register DIR No change
Register Name Old Mnemonic New Mnemonic
Table iv. Interrupt Control Register Memory Map
MBAR Offset
0x0020 Interrupt Control Register 1 ICR1 No change
0x0024 Interrupt Control Register 2 ICR2 No change
0x0028 Interrupt Control Register 3 ICR3 No change
0x002C Interrupt Control Register 4 ICR4 No change
0x0030 Interrupt Source Register ISR No change
Register Name Old Mnemonic New Mnemonic
0x0034 Programmable Interrupt Transition Register PITR No change
0x0038 Programmable Interrupt Wakeup Register PIWR No change
0x003F Programmable Interrupt Vector Register PIVR No change
Table v. Chip Select Register Memory Map
MBAR Offset
0x0040 CS Base Register 0 CSBR0 No change
0x0044 CS Option Register 0 CSOR0 No change
0x0048 CS Base Register 1 CSBR1 No change
0x004C CS Option Register 1 CSOR1 No change
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
l Freescale Semiconductor
Register Name Old Mnemonic New Mnemonic
Table v. Chip Select Register Memory Map (continued)
MBAR Offset
0x0050 CS Base Register 2 CSBR2 No change
0x0054 CS Option Register 2 CSOR2 No change
0x0058 CS Base Register 3 CSBR3 No change
0x005C CS Option Register 3 CSOR3 No change
0x0060 CS Base Register 4 CSBR4 No change
0x0064 CS Option Register 4 CSOR4 No change
0x0068 CS Base Register 5 CSBR5 No change
0x006C CS Option Register 5 CSOR5 No change
0x0070 CS Base Register 6 CSBR6 No change
0x0074 CS Option Register 6 CSOR6 No change
0x0078 CS Base Register 7 CSBR7 No change
0x007C CS Option Register 7 CSOR7 No change
Register Name Old Mnemonic New Mnemonic
Table vi. GPIO Port Register Memory Map
MBAR Offset
Register Name Old Mnemonic New Mnemonic
0x0080 Port A Control Register PACNT No change
0x0084 Port A Data Direction Register PADDR No change
0x0086 Port A Data Register PADAT No change
0x0088 Port B Control Register PBCNT No change
0x008C Port B Data Direction Register PBDDR No change
0x008E Port B Data Register PBDAT No change
0x0094 Port C Data Direction Register PCDDR No change
0x0096 Port C Data Register PCDAT No change
0x0098 Port D Control Register PDCNT No change
Table vii. QSPI Module Memory Map
MBAR Offset
0x00A0 QSPI Mode Register SPMODE QMR
0x00A4 QSPI Delay Register SPDELAY QDLYR
0x00A8 QSPI Wrap Register SPWRAP QWR
Register Name Old Mnemonic New Mnemonic
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor li
Table vii. QSPI Module Memory Map (continued)
MBAR Offset
0x00AC QSPI Interrupt Register SPINT QIR
0x00B0 QSPI Address Register SPADDR QAR
0x00B4 QSPI Data Register SPDATA QDR
Register Name Old Mnemonic New Mnemonic
Table viii. PWM Module Memory Map
MBAR Offset
0x00C0 PWM Control Register 0 PWMCR1 PWCR0
0x00C4 PWM Control Register 1 PWMCR2 PWCR1
0x00C8 PWM Control Register 2 PWMCR3 PWCR2
0x00D0 PWM Pulse-Width Register 0 PWMWD1 PWWD0
0x00D4 PWM Pulse-Width Register 1 PWMWD2 PWWD1
0x00D8 PWM Pulse-Width Register 2 PWMWD3 PWWD2
Register Name Old Mnemonic New Mnemonic
Table ix. DMA Module Memory Map
MBAR Offset
0x00E0 DMA Mode Register DCMR No change
0x00E6 DMA Interrupt Register DCIR No change
0x00E8 DMA Byte Count Register DBCR No change
0x00EC DMA Source Address Register DSAR No change
0x00F0 DMA Destination Address Register DDAR No change
Register Name Old Mnemonic New Mnemonic
Table x. UART0 Module Memory Map
MBAR Offset
0x0100 UART0 Mode Register 1/2 U1MR1/U1MR2 U0MR1/U0MR2
0x0104 UART0 Status U1SR U0SR
0x0104 UART0 Clock Select Register U1CSR U0CSR
0x0108 UART0 Command Register U1CR U0CR
0x010C UART0 Receive Buffer U1RxB U0RxB
0x010C UART0 Transmit Buffer U1TxB U0TxB
Register Name Old Mnemonic New Mnemonic
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
lii Freescale Semiconductor
Table x. UART0 Module Memory Map (continued)
MBAR Offset
0x0110 UART0 CTS Change Register U1CCR U0CCR
0x0110 UART0 Auxiliary Control Register U1ACR U0ACR
0x0114 UART0 Interrupt Status Register U1ISR U0ISR
0x0114 UART0 Interrupt Mask Register U1IMR U0IMR
0x0118 UART0 Baud Prescaler MSB U1BG1 U0BG1
0x011C UART0 Baud Prescaler LSB U1BG2 U0BG2
0x0120 UART0 AutoBaud MSB Register U1ABR1 U0ABR1
0x0124 UART0 AutoBaud LSB Register U1ABR2 U0ABR2
0x0128 UART0 TxFIFO Control/Status Register U1TxFCSR U0TxFCSR
0x012C UART0 RxFIFO Control/Status Register U1RxFCSR U0RxFCSR
0x0134 UART0 CTS Unlatched Input U1IP U0IP
0x0138 UART0 RTS O/P Bit Set Command Register U1OP1 U0OP1
0x013C UART0 RTS O/P Bit Reset Command Register U1OP0 U0OP0
Register Name Old Mnemonic New Mnemonic
Table xi. UART1 Module Memory Map
MBAR Offset
0x0140 UART1 Mode Register 1/2 U2MR1/U2MR2 U1MR1/U1MR2
0x0144 UART1 Status U2SR U1SR
0x0144 UART1 Clock Select Register U2CSR U1CSR
0x0148 UART1 Command Register U2CR U1CR
0x014C UART1 Receive Buffer U2RxB U1RxB
0x014C UART1 Transmit Buffer U2TxB U1TxB
0x0150 UART1 CTS Change Register U2CCR U1CCR
0x0150 UART1 Auxiliary Control Register U2ACR U1ACR
0x0154 UART1 Interrupt Status Register U2ISR U1ISR
0x0154 UART1 Interrupt Mask Register U2IMR U1IMR
0x0158 UART1 Baud Prescaler MSB U2BG1 U1BG1
0x015C UART1 Baud Prescaler LSB U2BG2 U1BG2
0x0160 UART1 AutoBaud MSB Register U2ABR1 U1ABR1
0x0164 UART1 AutoBaud LSB Register U2ABR2 U1ABR2
0x0168 UART1 TxFIFO Control/Status Register U2TxFCSR U1TxFCSR
Register Name Old Mnemonic New Mnemonic
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor liii
Table xi. UART1 Module Memory Map (continued)
MBAR Offset
0x016C UART1 RxFIFO Control/Status Register U2RxFCSR U1RxFCSR
0x0174 UART1 CTS Unlatched Input U2IP U1IP
0x0178 UART1 RTS O/P Bit Set Command Register U2OP1 U1OP1
0x017C UART1 RTS O/P Bit Reset Command Register U2OP0 U1OP0
Register Name Old Mnemonic New Mnemonic
Table xii. SDRAM Controller Memory Map
MBAR Offset
0x0182 SDRAM Configuration Register SDCCR SDCR
0x0186 SDRAM Timing Register SDCTR SDTR
Register Name Old Mnemonic New Mnemonic
Table xiii. Timer Module Memory Map
MBAR Offset
0x0200 Timer 0 Mode Register TMR1 TMR0
Register Name Old Mnemonic New Mnemonic
0x0204 Timer 0 Reference Register TRR1 TRR0
0x0208 Timer 0 Capture Register TCR1 TCAP0
0x020C Timer 0 Counter Register TCN1 TCN0
0x0210 Timer 0 Event Register TER1 TER0
0x0220 Timer 1 Mode Register TMR2 TMR1
0x0224 Timer 1 Reference Register TRR2 TRR1
0x0228 Timer 1 Capture Register TCR2 TCAP1
0x022C Timer 1 Counter Register TCN2 TCN1
0x0230 Timer 1 Event Register TER2 TER1
0x0240 Timer 2 Mode Register TMR3 TMR2
0x0244 Timer 2 Reference Register TRR3 TRR2
0x0248 Timer 2 Capture Register TCR3 TCAP2
0x024C Timer 2 Counter Register TCN3 TCN2
0x0250 Timer 2 Event Register TER3 TER2
0x0260 Timer 3 Mode Register TMR4 TMR3
0x0264 Timer 3 Reference Register TRR4 TRR3
0x0268 Timer 3 Capture Register TCR4 TCAP3
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
liv Freescale Semiconductor
Table xiii. Timer Module Memory Map (continued)
MBAR Offset
0x026C Timer 3 Counter Register TCN4 TCN3
0x0270 Timer 3 Event Register TER4 TER3
0x0280 Watchdog Reset Reference Register WRRR No change
0x0284 Watchdog Interrupt Reference Register WIRR No change
0x0288 Watchdog Counter Register WCR No change
0x028C Watchdog Event Register WER No change
Register Name Old Mnemonic New Mnemonic
Table xiv. PLIC Module Memory Map
MBAR Offset
0x0300 Port0 B1 Data Receive PLRB10 P0B1RR
0x0304 Port1 B1 Data Receive PLRB11 P1B1RR
0x0308 Port2 B1 Data Receive PLRB12 P2B1RR
0x030C Port3 B1 Data Receive PLRB13 P3B1RR
0x0310 Port0 B2 Data Receive PLRB20 P0B2RR
Register Name Old Mnemonic New Mnemonic
0x0314 Port1 B2 Data Receive PLRB21 P1B2RR
0x0318 Port2 B2 Data Receive PLRB22 P2B2RR
0x031C Port3 B2 Data Receive PLRB23 P3B2RR
0x0320 Port0-3 D Data Receive PLRD0
PLRD1 PLRD2 PLRD3
0x0328 Port0 B1 Data Transmit PLTB10 P0B1TR
0x032C Port1 B1 Data Transmit PLTB11 P1B1TR
0x0330 Port2 B1 Data Transmit PLTB12 P2B1TR
0x0334 Port3 B1 Data Transmit PLTB13 P3B1TR
0x0338 Port0 B2 Data Transmit PLTB20 P0B2TR
0x033C Port1 B2 Data Transmit PLTB21 P1B2TR
0x0340 Port2 B2 Data Transmit PLTB22 P2B2TR
0x0344 Port3 B2 Data Transmit PLTB23 P3B2TR
0x0348 Port0-3 D Data Transmit PLTD0
PLTD1 PLTD2 PLTD3
P0DRR P1DRR P2DRR P3DRR
P0DTR P1DTR P2DTR P3DTR
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor lv
Table xiv. PLIC Module Memory Map (continued)
MBAR Offset
0x0350 Port0-1 GCI/IDL Configuration Register PLCR0
0x0354 Port2-3 GCI/IDL Configuration Register PLCR2
0x0358 Port0-1 Interrupt Configuration Register PLICR0
0x035C Port2-3 Interrupt Configuration Register PLICR2
0x0360 Port0-1 GCI Monitor RX PLGMR0
0x0364 Port2-3 GCI Monitor RX PLGMR2
0x0368 Port0-1 GCI Monitor TX PLGMT0
0x036C Port2-3 GCI Monitor TX PLGMT2
0x0370 GCI Monitor TX Status
GCI Monitor TX abort
Register Name Old Mnemonic New Mnemonic
PLCR1
PLCR3
PLICR1
PLICR3
PLGMR1
PLGMR3
PLGMT1
PLGMT3
PLGMTS PLGMTA
P0CR P1CR
P2CR P3CR
P0ICR P1ICR
P2ICR P3ICR
P0GMR P1GMR
P2GMR P3GMR
P0GMT P1GMT
P2GMT P3GMT
PGMTS PGMTA
0x0374 Port0-3 GCI C/I RX PLGCIR0
PLGCIR1 PLGCIR2 PLGCIR3
0x0378 Port0-3 GCI C/I TX PLGCIT0
PLGCIT1 PLGCIT2 PLGCIT3
0x037C GCI C/I TX Status PGCITSR No change
0x0384 Port0-1 Periodic Status PLPSR0
PLPSR1
0x0388 Port2-3 Periodic Status PLPSR2
PLPSR3
0x038C Aperiodic Interrupt Status Register;
Loop back Control
0x0392 D Channel Request PLDRQ PDRQR
0x0394 Port0-1 Sync Delay PLSD0
0x0398 Port2-3 Sync Delay PLSD2
0x039C Clock Select PLCKSEL PCSR
PLASR PLLCR
PLSD1
PLSD3
P0GCIR P1GCIR P2GCIR P3GCIR
P0GCIT P1GCIT P2GCIT P3GCIT
P0PSR P1PSR
P2PSR P3PSR
PASR PLCR
P0SDR P1SDR
P2SDR P3SDR
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
lvi Freescale Semiconductor
Table xv. Ethernet Module Memory Map
MBAR Offset
0x0840 Ethernet Control Register ECNTRL ECR
0x0844 Ethernet Interrupt Event Register IEVENT EIR
0x0848 Ethernet Interrupt Mask Register IMASK EIMR
0x084C Ethernet Interrupt Vector Status IVEC IVSR
0x0850 Ethernet Rx Ring Updated Flag R_DES_ACTIVE RDAR
0x0854 Ethernet Tx Ring Updated Flag X_DES_ACTIVE TDAR
0x0880 Ethernet MII Data Register MII_DATA MMFR
0x0884 Ethernet MII Speed Register MII_SPEED MSCR
0x08CC Ethernet Receive Bound Register R_BOUND FRBR
0x08D0 Ethernet Rx FIFO Start Address R_FSTART FRSR
0x08E4 Transmit FIFO Watermark X_WMRK TFWR
0x08EC Ethernet Tx FIFO Start Address X_FSTART TFSR
0x0944 Ethernet Rx Control Register R_CNTRL RCR
0x0948 Maximum Frame Length Register MAX_FRM_LEN MFLR
0x0984 Ethernet Tx Control Register X_CNTRL TCR
Register Name Old Mnemonic New Mnemonic
0x0C00 Ethernet Address (Lower) ADDR_LOW MALR
0x0C04 Ethernet Address (Upper) ADDR_HIGH MAUR
0x0C08 Ethernet Hash Table (Upper) HASH_TABLE_HIGH HTUR
0x0C0C Ethernet Hash Table (Lower) HASH_TABLE_LOW HTLR
0x0C10 Ethernet Rx Descriptor Ring R_DES_START ERDSR
0x0C14 Ethernet Tx Descriptor Rin X_DES_START ETDSR
0x0C18 Ethernet Rx Buffer Size R_BUFF_SIZE EMRBR
0x0C40– 0x0DFF
FIFO RAM E_FIFO EFIFO
Table xvi. USB Module Memory Map
MBAR Offset
0x1002 USB Frame Number Register USBFNR FNR
0x1006 USB Frame Number Match Register USBFNMR FNMR
0x100A USB Real-time Frame Monitor Register USBRTFMR RFMR
0x100E USB Real-time Frame Monitor Match Register USBRTFMMR RFMMR
Register Name Old Mnemonic New Mnemonic
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor lvii
Table xvi. USB Module Memory Map (continued)
MBAR Offset
0x1013 USB Function Address Register USBFAR FAR
0x1014 USB Alternate Setting Register USBASR ASR
0x1018 USB Device Request Data1 Register USBDRR1 DRR1
0x101C USB Device Request Data2 Register USBDRR2 DRR2
0x1022 USB Specification Number Register USBSPECR SPECR
0x1026 USB Endpoint 0 Status Register USBEPSR0 EP0SR
0x1028 USB Endpoint 0 IN Config Register USBEPICFG0 IEP0CFG
0x102C USB Endpoint 0 OUT Config Register USBEPOCFG0 OEP0CFG
0x1030 USB Endpoint 1 Configuration Register USBEPCFG1 EP1CFG
0x1034 USB Endpoint 2 Configuration Register USBEPCFG2 EP2CFG
0x1038 USB Endpoint 3 Configuration Register USBEPCFG3 EP3CFG
0x103C USB Endpoint 4 Configuration Register USBEPCFG4 EP4CFG
0x1040 USB Endpoint 5 Configuration Register USBEPCFG5 EP5CFG
0x1044 USB Endpoint 6 Configuration Register USBEPCFG6 EP6CFG
0x1048 USB Endpoint 7 Configuration Register USBEPCFG7 EP7CFG
Register Name Old Mnemonic New Mnemonic
0x104C USB Endpoint 0 Control Register USBEPCTL0 EP0CTL
0x1052 USB Endpoint 1 Control Register USBEPCTL1 EP1CTL
0x1056 USB Endpoint 2 Control Register USBEPCTL2 EP2CTL
0x105A USB Endpoint 3 Control Register USBEPCTL3 EP3CTL
0x105E USB Endpoint 4 Control Register USBEPCTL4 EP4CTL
0x1062 USB Endpoint 5 Control Register USBEPCTL5 EP5CTL
0x1066 USB Endpoint 6 Control Register USBEPCTL6 EP6CTL
0x106A USB Endpoint 7 Control Register USBEPCTL7 EP7CTL
0x106C USB General/Endpoint 0 Interrupt Status Register USBEPISR0 EP0ISR
0x1072 USB Endpoint 1 Interrupt Status Register USBEPISR1 EP1ISR
0x1076 USB Endpoint 2 Interrupt Status Register USBEPISR2 EP2ISR
0x107A USB Endpoint 3 Interrupt Status Register USBEPISR3 EP3ISR
0x107E USB Endpoint 4 Interrupt Status Register USBEPISR4 EP4ISR
0x1082 USB Endpoint 5 Interrupt Status Register USBEPISR5 EP5ISR
0x1086 USB Endpoint 6 Interrupt Status Register USBEPISR6 EP6ISR
0x108A USB Endpoint 7 Interrupt Status Register USBEPISR7 EP7ISR
0x108C USB Endpoint 0 Interrupt Mask Register USBEPIMR0 EP0IMR
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
lviii Freescale Semiconductor
Table xvi. USB Module Memory Map (continued)
MBAR Offset
0x1092 USB Endpoint 1 Interrupt Mask Register USBEPIMR1 EP1IMR
0x1096 USB Endpoint 2 Interrupt Mask Register USBEPIMR2 EP2IMR
0x109A USB Endpoint 3 Interrupt Mask Register USBEPIMR3 EP3IMR
0x109E USB Endpoint 4 Interrupt Mask Register USBEPIMR4 EP4IMR
0x10A2 USB Endpoint 5 Interrupt Mask Register USBEPIMR5 EP5IMR
0x10A6 USB Endpoint 6 Interrupt Mask Register USBEPIMR6 EP6IMR
0x10AA USB Endpoint 7 Interrupt Mask Register USBEPIMR7 EP7IMR
0x10AC USB Endpoint 0 Data Register USBEPDAT0 EP0DR
0x10B0 USB Endpoint 1 Data Register USBEPDAT1 EP1DR
0x10B4 USB Endpoint 2 Data Register USBEPDAT2 EP2DR
0x10B8 USB Endpoint 3 Data Register USBEPDAT3 EP3DR
0x10BC USB Endpoint 4 Data Register USBEPDAT4 EP4DR
0x10C0 USB Endpoint 5 Data Register USBEPDAT5 EP5DR
0x10C4 USB Endpoint 6 Data Register USBEPDAT6 EP6DR
0x10C8 USB Endpoint 7 Data Register USBEPDAT7 EP7DR
Register Name Old Mnemonic New Mnemonic
0x10CE USB Endpoint 0 Data Present Register USBEPDP0 EP0DPR
0x10D2 USB Endpoint 1 Data Present Register USBEPDP1 EP1DPR
0x10D6 USB Endpoint 2 Data Present Register USBEPDP2 EP2DPR
0x10DA USB Endpoint 3 Data Present Register USBEPDP3 EP3DPR
0x10DE USB Endpoint 4 Data Present Register USBEPDP4 EP4DPR
0x10E2 USB Endpoint 5 Data Present Register USBEPDP5 EP5DPR
0x10E6 USB Endpoint 6 Data Present Register USBEPDP6 EP6DPR
0x10EA USB Endpoint 7 Data Present Register USBEPDP7 EP7DPR
0x1400– 0x17FF
USB Configuration RAM, 1 K Bytes USB_CFG_RAM No change
NOTE
The MBAR Offset column corresponds to the tables found in Appendix A,
“List of Memory Maps.” 16- and/or 8-bit wide registers may be offset by 0,
1, 2, or 3 bytes from the offset address shown above. Refer to the appropriate discussions in this document for actual positioning of 16- or 8-bit registers in a 32-bit long word.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor lix
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
lx Freescale Semiconductor

Chapter 1 Overview

This chapter provides an overview of the MCF5272 microprocessor features, including the major functional components.

1.1 MCF5272 Key Features

A block diagram of the MCF5272 is shown in Figure 1-1. The main features are as follows:
• Static Version 2 ColdFire variable-length RISC processor — 32-bit address and data path on-chip — 66-MHz processor core and bus frequency — Sixteen general-purpose 32-bit data and address registers — Multiply-accumulate unit (MAC) for DSP and fast multiply operations
• On-chip memories — 4-Kbyte SRAM on CPU internal bus — 16-Kbyte ROM on CPU internal bus — 1-Kbyte instruction cache
• Power management — Fully-static operation with processor sleep and whole-chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used — Software-controlled disable of external clock input for virtually zero power consumption
(low-power stop mode)
• Two universal asynchronous/synchronous receiver transmitters (UARTs) — Full-duplex operation — Based on MC68681 dual-UART (DUART) programming model — Flexible baud rate generator — Modem control signals available (CTS — Processor interrupt and wakeup capability — Enhanced Tx, Rx FIFOs, 24 bytes each
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 1-1
and RTS)
Overview
JTAG
V2 ColdFire Processor Complex
Instruction Unit
IFP
Instruction Fetch
Local
OEP
FIFO Instruction Buffer (3 X 32)
Decode, Select, Operand Fetch
Address Generation, Execute
Local Memory
SRAM Controller
RAMBAR
4-Kbyte
SRAM
ROM Controller
ROMBAR
16-Kbyte
ROM
Instruction Cache
Controller
ACR0 ACR1
CACR
1-Kbyte
Cache
31 0
Local Memory Data Bus
4-Entry Store Buffer
D[31:0]
Figure 1-1. MCF5272 Block Diagram
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
1-2 Freescale Semiconductor
• Ethernet Module — 10 baseT capability, half or full duplex — 100 baseT capability, half duplex and limited throughput full duplex (MCF5272) — On-chip transmit and receive FIFOs — Off-chip flexible buffer descriptor rings — Media-independent interface (MII)
• Universal serial bus (USB) module — 12 Mbps (full speed) — Fully compatible with USB 1.1 specifications — Eight endpoints (control, bulk, interrupt Rx, isochronous) — Endpoint FIFOs — Selectable on-chip analog interface
• External memory interface — External glueless 8, 16, and 32-bit SRAM and ROM interface bus — SDRAM controller supports 16–256 Mbit devices — External bus configurable for 16 or 32 bits width for SDRAM
Overview
— Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator
• Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfer — Up to four chip selects available — Master operation — Programmable master bit rates — Up to 16 preprogrammed transfers
• Timer module — 4x16-bit general-purpose multi-mode timer
– Input capture and output compare pins for timers 1 and 2
– Programmable prescaler — 15-nS resolution at 66-MHz clock frequency — Software watchdog timer — Software watchdog can generate interrupt before reset — Processor interrupt for each timer
• Pulse-width modulation (PWM) unit — Three identical channels — Independent prescaler TAP point — Period/duty range variable
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 1-3
Overview
• System integration module (SIM) — System configuration including internal and external address mapping — System protection by hardware watchdog — Versatile programmable chip-select signals with wait-state generation logic — Up to three 16-bit parallel input/output ports — Latchable interrupt inputs with programmable priority and edge triggering — Programmable interrupt vectors for on-chip peripherals
• Physical layer interface controller (PLIC) — Allows connection using general circuit interface (GCI) or interchip digital link (IDL) physical
layer protocols for 2B + D data — Three physical interfaces — Four time-division multiplex (TDM) ports
• IEEE 1149.1 boundary-scan test access port (JTAG) for board-level testing
• Operating voltage: 3.3 V ±0.3 V
• Operating temperature: 0 –70°C
• Operating frequency: DC to 66 MHz, from external CMOS oscillator
• Compact ultra low-profile 196 ball-molded plastic ball-grid array package (PGBA)

1.2 MCF5272 Architecture

This section briefly describes the MCF5272 core, SIM, UART, and timer modules, and test access port.

1.2.1 Version 2 ColdFire Core

Based on the concept of variable-length RISC technology, ColdFire combines the simplicity of conventional 32-bit RISC architectures with a memory-saving, variable-length instruction set. The main features of the MCF5272 core are as follows:
• 32-bit address bus directly addresses up to 4 Gbytes of address space
• 32-bit data bus
• Variable-length RISC
• Optimized instruction set for high-level language constructs
• Sixteen general-purpose 32-bit data and address registers
• MAC unit for DSP applications
• Supervisor/user modes for system protection
• Vector base register to relocate exception-vector table
• Special core interfacing signals for integrated memories
• Full debug support
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
1-4 Freescale Semiconductor
Overview
The Version 2 ColdFire core has a 32-bit address bus and a 32-bit data bus. The address bus allows direct addressing of up to 4 Gbytes. It supports misaligned data accesses and a bus arbitration unit for multiple bus masters.
The Version 2 ColdFire supports an enhanced subset of the 68000 instruction set. The MAC provides new instructions for DSP applications; otherwise, Version 2 ColdFire user code runs unchanged on 68020, 68030, 68040, and 68060 processors. The removed instructions include BCD, bit field, logical rotate, decrement and branch, integer division, and integer multiply with a 64-bit result. Also, four indirect addressing modes have been eliminated.
The ColdFire 2 core incorporates a complete debug module that provides real-time trace, background debug mode, and real-time debug support.

1.2.2 System Integration Module (SIM)

The MCF5272 SIM provides the external bus interface for the ColdFire 2 architecture. It also eliminates most or all of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system. The SIM provides programmable circuits to perform address-decoding and chip selects, wait-state insertion, interrupt handling, clock generation, discrete I/O, and power management features.
1.2.2.1 External Bus Interface
The external bus interface (EBI) handles the transfer of information between the internal core and memory , peripherals, or other processing elements in the external address space.
1.2.2.2 Chip Select and Wait State Generation
Programmable chip select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a multiple of the block size. Each chip select is general purpose; however, any one of the chip selects can be programmed to provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access.
1.2.2.3 System Configuration and Protection
The SIM provides configuration registers that allow general system functions to be controlled and monitored. For example, all on-chip registers can be relocated as a block by programming a module base address, power management modes can be selected, and the source of the most recent RESET or BERR can be checked. The hardware watchdog features can be enabled or disabled, and the bus time-out period can be programmed.
A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset to the MCF5272 if it is not refreshed periodically by software.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 1-5
Overview
1.2.2.4 Power Management
The sleep and stop power management modes reduce power consumption by allowing software to shut down the core, peripherals, or the whole device during inactive periods. To reduce power consumption further, software can individually disable internal clocks to the on-chip peripheral modules. The power-saving modes are described as follows:
• Sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. As the MCF5272 is fully static, sleep mode is simply the disabling of the core’ s clock after the current instruction completes. An interrupt from any internal or external source causes on-chip power management logic to reenable the core’s clock; execution resumes with the next instruction. This allows rapid return from power-down state as compared to a dynamic implementation that must perform power-on reset processing before software can handle the interrupt request. If interrupts are enabled at the appropriate priority level, program control passes to the relevant interrupt service routine.
• Stop mode is entered by the disabling of the external clock input and is achieved by software setting a bit in a control register. Program execution stops after the current instruction. In stop mode, neither the core nor peripherals are active. The MCF5272 consumes very little power in this mode. To resume normal operation, the external interrupts cause the power management logic to re-enable the external clock input. The MCF5272 resumes program execution from where it entered stop mode (if no interrupt are pending), or starts interrupt exception processing if interrupts are pending.
1.2.2.5 Parallel Input/Output Ports
The MCF5272 has up to three 16-bit general-purpose parallel ports, each line of which can be programmed as either an input or output. Some port lines have dedicated pins and others are shared with other MCF5272 functions. Some outputs have high drive current capability.
1.2.2.6 Interrupt Inputs
The MCF5272 has flexible latched interrupt inputs each of which can generate a separate, maskable interrupt with programmable interrupt priority level and triggering edge (falling or rising). Each interrupt has its own interrupt vector.

1.2.3 UART Module

The MCF5272 has two full-duplex UART modules with an on-chip baud rate generator providing both standard and non-standard baud rates up to 5 Mbps. The module is functionally equivalent to the MC68681 DUAR T with enhanced features including 24-byte Tx and Rx FIFOs. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and up to 2 stop bits in 1/16-bit increments. Receive and transmit FIFOs minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided.
Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud rates. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) lines available externally. Full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
1-6 Freescale Semiconductor
Overview
The UART can be programmed to interrupt or wake up the CPU on various normal or abnormal events. To reduce power consumption, the UART can be disabled by software if not in use.

1.2.4 Timer Module

The timer module contains five timers arranged in two submodules. One submodule contains a programmable software watchdog timer. The other contains four independent, identical general-purpose timer units, each containing a free-running 16-bit timer for use in various modes, including capturing the timer value with an external event, counting external events, or triggering an external signal or interrupting the CPU when the timer reaches a set value. Each unit has an 8-bit prescaler for deriving the clock input frequency from the system clock or external clock input. The output pin associated with each timer has programmable modes.
To reduce power consumption, the timer module can be disabled by software.

1.2.5 Test Access Port

For system diagnostics and manufacturing testing, the MCF5272 includes user-accessible test logic that complies with the IEEE 1149.1 standard for boundary scan testing, often referred to as JTAG (Joint Test Action Group). The IEEE 1149.1 Standard provides more information.

1.3 System Design

This section presents issues to consider when designing with the MCF5272. It describes differences between the MCF5272 (core and peripherals) and various other standard components that are replaced by moving to an integrated device like the MCF5272.

1.3.1 System Bus Configuration

The MCF5272 has flexibility in its system bus interfacing due to the dynamic bus sizing feature in which 32-,16-, and 8-bit data bus sizes are programmable on a per-chip select basis. The programmable nature of the strobe signals (including OE minimal or nonexistent. Configuration software is required upon power-on reset before chip-selected devices can be used, except for chip select 0 (CS0 otherwise. BUSW1 and BUSW0 select the initial data bus width for CS0 or a restart from stop mode does not require reconfiguration of the chip select registers or other system configuration registers.
/RD, R/W, BS[3:0], and CSn) should ensure that external decode logic is
), which is active after power-on reset until programmed
only . A wake-up from sleep mode

1.4 MCF5272-Specific Features

This section describes features peculiar to the MCF5272.

1.4.1 Physical Layer Interface Controller (PLIC)

The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with external CODECs and other peripheral devices that use either the general circuit interface (GCI), or
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 1-7
Overview
interchip digital link (IDL), physical layer protocols. This module is primarily intended to facilitate designs that include ISDN interfaces.

1.4.2 Pulse-Width Modulation (PWM) Unit

The PWM unit is intended for use in control applications. With a suitable low-pass filter, it can be used as a digital-to-analog converter . This module generates a synchronous series of pulses. The duty cycle of the pulses is under software control.
Its main features include the following:
• Double-buffered width register
• Variable-divide prescale
• Three identical, independent PWM modules
• Byte-wide width register provides programmable control of duty cycle.
The PWM implements a simple free-running counter with a width register and comparator such that the output is cleared when the counter exceeds the value of the width register . When the counter wraps around, its value is not greater than the width register value, and the output is set high. With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter.

1.4.3 Queued Serial Peripheral Interface (QSPI)

The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to 16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfer RAMs in the QSPI are indirectly accessible using address and data registers. Functionality is similar to the QSPI portion of the QSM (queued serial module) implemented in the MC68332.
The QSPI has the following features:
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines for control of up to 15 devices
• Baud rates from 129.4 Kbps to 33 Mbps at 66 MHz.
• Programmable delays before and after transfers
• Programmable clock phase and polarity
• Supports wrap-around mode for continuous transfers

1.4.4 Universal Serial Bus (USB) Module

The USB controller on the MCF5272 supports device mode data communications with a USB host (typically a PC). One host and up to 127 attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The USB uses a tiered star topology with a hub at the center of each star. Each wire segment is a point-to-point connection between the host connector and a peripheral connector.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
1-8 Freescale Semiconductor

Chapter 2 ColdFire Core

This chapter provides an overview of the microprocessor core of the MCF5272. The chapter describes the V2 programming model as it is implemented on the MCF5272. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings.

2.1 Features and Enhancements

The MCF5272 is the most highly-integrated V2 standard product, containing a variety of communications and general-purpose peripherals. The V2 core was designed to maximize code density and performance while minimizing die area.
The following list summarizes MCF5272 features:
• Variable-length RISC Version 2 microprocessor core
• Two independent, decoupled pipelines—two-stage instruction fetch pipeline (IFP) and two-stage operand execution pipeline (OEP)
• Three longword FIFO buffer provides decoupling between the pipelines
• 32-bit internal address bus supporting 4 Gbytes of linear address space
• 32-bit data bus
• 16 user-accessible, 32-bit-wide, general-purpose registers
• Supervisor/user modes for system protection
• Vector base register to relocate exception-vector table
• Optimized for high-level language constructs

2.1.1 Decoupled Pipelines

The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes the specified function. The two independent, decoupled pipeline structures maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1 and are summarized as follows:
• Two-stage IFP (plus optional instruction buffer stage) — Instruction address generation (IAG) calculates the next prefetch address. — Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction bus. — Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of fetch latency.
• Two-stage OEP — Decode, select/operand fetch (DSOC) decodes the instruction and selects the required
components for the effective address calculation, or the operand fetch cycle.
— Address generation/execute (AGEX) calculates the operand address, or performs the execution
of the instruction.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-1
ColdFire Core
IAG
Instruction
Address
Generation
Instruction Fetch Pipeline
Operand Execution Pipeline
IC
IB
DSOC
AGEX
Instruction
Fetch Cycle
FIFO
Instruction Buffer
Decode & Select,
Operand Fetch
Address
Generation,
Execute
Figure 2-1. ColdFire Pipeline
Address [31:0]
Data[31:0]
2.1.1.1 Instruction Fetch Pipeline (IFP)
The IFP generates instruction addresses and fetches. Because the fetch and execution pipelines are decoupled by a three longword FIFO buffer, the IFP ca n prefetch instructions before the OEP needs them, minimizing stalls.
2.1.1.2 Operand Execution Pipeline (OEP)
The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register file feeding an arithmetic/logic unit (ALU). For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC), while the actual instruction execution is performed in the second stage (EX).
For memory-to-register instructions, the instruction is effectively staged through the OEP twice in the following way:
• The instruction is decoded and the components of the operand address are selected (DS).
• The operand address is generated using the execute engine (AG).
• The memory operand is fetched while any register operand is simultaneously fetched (OC).
• The instruction is executed (EX).
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-2 Freescale Semiconductor
ColdFire Core
For register-to-memory operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. For read-modify-write instructions, the pipeline effectively combines a memory-to-register operation with a store operation.
2.1.1.2.1 Illegal Opcode Handling
On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC) are decoded and generate an illegal instruction exception. Additionally , attempting to execute an illegal line A or line F opcode generates unique exception types. If any other unsupported opcode is executed, the resulting operation is undefined.
2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit
The MAC is an optional unit in Version 2 that provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family . The MAC features a three-stage execution pipeline, optimized for 16 x 16 multiplies. It is tightly coupled to the OEP, which can issue a 16 x 16 multiply with a 32-bit accumulation plus fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued.
Figure 2-2 shows basic functionality of the MAC. A full set of instructions are provided for signed and
unsigned integers plus signed, fixed-point fractional input operands.
Operand Y Operand X
X
Shift 0,1,-1
+/-
Accumulator
Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram
The MAC provides functionality in the following three related areas, which are described in detail in
Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit.”
• Signed and unsigned integer multiplies
• Multiply-accumulate operations with signed and unsigned fractional operands
• Miscellaneous register operations
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-3
ColdFire Core
2.1.1.2.3 Hardware Divide Unit
The hardware divide unit performs the following integer division operations:
• 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder
• 32-bit operand/32-bit operand producing a 32-bit quotient
• 32-bit operand/32-bit operand producing a 32-bit remainder

2.1.2 Debug Module Enhancements

The ColdFire processor core debug interface supports system integration in conjunction with low-cost development tools. Real-time trace and debug information can be accessed through a standard interface, which allows the processor and system to be debugged at full speed without costly in-circuit emulators. On-chip breakpoint resources include the following:
• Configuration/status register (CSR)
• Bus attributes and mask register (AATR)
• Breakpoint registers. These can be used to define triggers combining address, data, and PC conditions in single- or dual-level definitions. They include the following:
— PC breakpoint register (PBR) — PC breakpoint mask register (PBMR) — Data operand address breakpoint registers (ABHR/ABLR) — Data breakpoint register (DBR)
• Data breakpoint mask register (DBMR)
• Trigger definition register (TDR) can be programmed to generate a processor halt or initiate a debug interrupt exception
These registers can be accessed through the dedicated debug serial communication channel, or from the processor’s supervisor programming model, using the WDEBUG instruction.

2.2 Programming Model

The MCF5272 programming model consists of three instruction and register groups—user, MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are restricted to user and MAC instructions and programming models. Supervisor-mode system software can reference all user-mode and MAC instructions and registers and additional supervisor instructions and control registers. The user or supervisor programming model is selected based on SR[S]. The following sections describe the registers in the user, MAC, and supervisor programming models.

2.2.1 User Programming Model

As Figure 2-3 shows, the user programming model consists of the following registers:
• 16 general-purpose 32-bit registers, D0–D7 and A0–A7
• 32-bit program counter
• 8-bit condition code register
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-4 Freescale Semiconductor
User Registers
Supervisor
Registers
31 0
31 0
31 0
15
31 19
Must be zeros VBR Vector base register
(CCR) SR Status register
ColdFire Core
D0 Data registers D1 D2 D3 D4 D5 D6 D7
A0 Address registers A1 A2 A3 A4 A5 A6 A7 Stack pointer PC Program counter CCR Condition code register
MACSR MAC status register ACC MAC accumulator MASK MAC mask register
CACR Cache control register ACR0 Access control register 0 ACR1 Access control register 1 ROMBAR ROM base address register RAMBAR RAM base address register MBAR Module base address register
Figure 2-3. ColdFire Programming Model
2.2.1.1 Data Registers (D0–D7)
Registers D0–D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit) operations. They may also be used as index registers.
2.2.1.2 Address Registers (A0–A6)
The address registers (A0–A6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations.
2.2.1.3 Stack Pointer (A7, SP)
The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register . The initial value of A7 is loaded
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-5
ColdFire Core
from the reset exception vector, address 0x0000. The same register is used for user and supervisor modes, and may be used for word and longword operations.
A subroutine call saves the program counter (PC) on the stack and the return restores the PC from the stack. The PC and the status register (SR) are saved on the stack during exception and interrupt processing. The return from exception instruction restores SR and PC values from the stack.
2.2.1.4 Program Counter (PC)
The PC holds the address of the executing instruction. For sequential instructions, the processor automatically increments the PC. When program flow changes, the PC is updated with the target instruction. For some instructions, the PC specifies the base address for PC-relative operand addressing modes.
2.2.1.5 Condition Code Register (CCR)
The CCR, Figure 2-4, occupies SR[7–0], as shown in Figure 2-3. CCR[4–0] are indicator flags based on results generated by arithmetic operations.
76543210
Field — X N Z V C
Reset 000 Undefined
R/W R R/W R/W R/W R/W R/W
Figure 2-4. Condition Code Register (CCR)
CCR fields are described in Table 2-1.
Table 2-1. CCR Field Descriptions
Bits Name Description
7–5 — Reserved, should be cleared.
4 X Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not
affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic. 3 N Negative condition code bit. Set if the msb of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared. 1 V Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be
represented in the operand size; otherwise cleared. 0 C Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a borrow
occurs in a subtraction; otherwise cleared.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-6 Freescale Semiconductor
ColdFire Core
2.2.1.6 MAC Programming Model
Figure 2-3 shows the registers in the MAC portion of the user programming model. These registers are
described as follows:
• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.
• Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.
• MAC status register (MACSR)—This 8-bit register defines configuration of the MAC unit and contains indicator flags affected by MAC instructions. Unless noted otherwise, MACSR indicator flag settings are based on the final result, that is, the result of the final operation involving the product and accumulator.

2.2.2 Supervisor Programming Model

The MCF5272 supervisor programming model is shown in Figure 2-3. Typically , system programmers use the supervisor programming model to implement operating system functions and provide memory and I/O control. The supervisor programming model provides access to the user registers and additional supervisor registers, which include the upper byte of the status register (SR), the vector base register (VBR), and registers for configuring attributes of the address space connected to the Version 2 processor core. Most supervisor-mode registers are accessed by using the MOVEC instruction with the control register definitions in Table 2-2.
Table 2-2. MOVEC Register Map
Rc[11–0] Register Definition
0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1)
0x801 Vector base register (VBR) 0xC00 ROM base address register 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR)
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-7
ColdFire Core
2.2.2.1 Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software can read or write the entire SR; user software can read or write only SR[7–0], described in Section 2.2.1.5,
“Condition Code Register (CCR).” The control bits indicate processor states—trace mode (T), supervisor
or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.
15 8 7 0
System Byte Condition Code Register (CCR)
Field T — S M — I — X N Z V C
Reset00100 111 000 —————
R/W R/W R R/W R/W R R/W R R/W R/W R/W R/W R/W
Figure 2-5. Status Register (SR)
Table 2-3 describes SR fields.
Table 2-3. Status Field Descriptions
Bits Name Description
15 T Trace enable. When T is set, the processor performs a trace exception after every instruction. 13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode 1 Supervisor mode
12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
10–8 I Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request, which cannot be masked.
7–0 CCR Condition code register. See Figure 2-4.
2.2.2.2 Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte boundary.
31 20 19 0
Field Exception vector table base address —
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
Rc[11–0] 0x801
Figure 2-6. Vector Base Register (VBR)
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-8 Freescale Semiconductor
ColdFire Core
2.2.2.3 Cache Control Register (CACR)
The CACR controls operation of the instruction and data cache memory. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and write-protect fields. See Section 4.5.3.1, “Cache Control Register (CACR).”
2.2.2.4 Access Control Registers (ACR0–ACR1)
The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions. Attributes include definition of cache mode, write protect, and buffer write enables. See Section 4.5.3.2,
“Access Control Registers (ACR0 and ACR1).”
2.2.2.5 ROM Base Address Register (ROMBAR)
The ROMBAR base address register determines the base address of the internal ROM module and indicates the types of references mapped to it. The ROMBAR includes a base address, write-protect bit, address space mask bits, and an enable. Note that the MCF5272 ROM contains data for the HDLC module and is not user programmable. See Section 4.4.2.1, “ROM Base Address Register (ROMBAR).”
2.2.2.6 RAM Base Address Register (RAMBAR)
The RAMBAR register determines the base address location of the internal SRAM module and indicates the types of references mapped to it. The RAMBAR includes a base address, write-protect bit, address space mask bits, and an enable. The RAM base address must be aligned on a 0-modulo-4-Kbyte boundary . See Section 4.3.2.1, “SRAM Base Address Register (RAMBAR).”
2.2.2.7 Module Base Address Register (MBAR)
The module base address register (MBAR) defines the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. See Section 6.2.2, “Module Base Address
Register (MBAR).”

2.3 Integer Data Formats

Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or
instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation.
Table 2-4. Integer Data Formats
Operand Data Format Size
Bit 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-9
ColdFire Core

2.4 Organization of Data in Registers

The following sections describe data organization within the data, address, and control registers.

2.4.1 Organization of Integer Data Formats in Registers

Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and
word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. Longword operands occupy the entire 32 bits of integer data registers. A data register that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations, respectively . The remaining high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero, the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7.
31 30 1 0
msb lsb Bit (0 ð bit number ð 31)
31 87610
Not used msb Low order byte lsb Byte (8 bits)
31 16 15 14 1 0
Not used msb Lower order word lsb Word (16 bits)
31 30 1 0
msb Longword lsb Longword (32 bits)
Figure 2-7. Organization of Integer Data Formats in Data Registers
The instruction set encodings do not allow the use of address registers for byte-sized operands. When an address register is a source operand, either the low-order word or the entire longword operand is used, depending on the operation size. Word-length source operands are sign-extended to 32 bits and then used in the operation with an address register destination. When an address register is a destination, the entire register is affected, regardless of the operation size. Figure 2-8 shows integer formats for address registers.
31 16 15 0
Sign-Extended 16-Bit Address Operand
31 0
Full 32-Bit Address Operand
Figure 2-8. Organization of Integer Data Formats in Address Registers
The size of control registers varies according to function. Some have undefined bits reserved for future definition by Freescale. Those particular bits read as zeros and must be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-10 Freescale Semiconductor
ColdFire Core

2.4.2 Organization of Integer Data Formats in Memory

All ColdFire processors use a big-endian addressing scheme. The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a longword data item corresponds to the address of the high-order word. The lower order word is located at address N + 2. The address N of a word data item corresponds to the address of the high-order byte. The lower order byte is located at address N + 1. This organization is shown in Figure 2-9.
31 24 23 16 15 8 7 0
Longword 0x0000_0000
Word 0x0000_0000 Word 0x0000_0002
Byte 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003
Longword 0x0000_0004
Word 0x0000_0004 Word 0x0000_0006
Byte 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007
.
.
.
Longword 0xFFFF_FFFC
Word 0xFFFF_FFFC Word 0xFFFF_FFFE
Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF
Figure 2-9. Memory Operand Addressing
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-11
ColdFire Core

2.5 Addressing Mode Summary

Addressing modes are categorized by how they are used. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable (writable) data operands. Control addressing modes refer to memory operands without an associated size.
These categories sometimes combine to form more restrictive categories. Two combined classifications are alterable memory (both alterable and memory) and data alterable (both alterable and data). Twelve of the most commonly used effective addressing modes from the M68000 family are available on ColdFire microprocessors. Table 2-5 summarizes these modes and their categories.
Table 2-5. ColdFire Effective Addressing Modes
— —
X X X X
X X
Category
— —
— —
X
X
X X
— —
Addressing Modes Syntax
Register direct
Data Address
Register indirect
Address Address with Postincrement Address with Predecrement Address with Displacement
Address register indirect with scaled index
8-bit displacement
Program counter indirect
with displacement (d16, PC) 111 010 X X X —
Program counter indirect with scaled index
8-bit displacement
Absolute data addressing
Short Long
Immediate #<xxx> 111 100 X X — —
Dn An
(An) (An)+ –(An)
, An)
(d
16
(d8, An,
Xi*SF)
(d8, PC,
Xi*SF)
(xxx).W
(xxx).L
Mode Field
000 001
010 011 100 101
110 reg. no. X X X X
111 011 X X X —
111 111
Reg. Field
reg. no. reg. no.
reg. no. reg. no. reg. no. reg. no.
000 001
Data Memory Control Alterable
X
—
X X X X
X X
X X
X X X X
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-12 Freescale Semiconductor
ColdFire Core

2.6 Instruction Set Summary

The ColdFire instruction set is a simplified version of the M68000 instruction set. The removed instructions include BCD, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit result. Nine new MAC instructions have been added.
Table 2-6 lists notational conventions used throughout this manual.
Table 2-6. Notational Conventions
Instruction Operand Syntax
Opcode Wildcard
cc Logical condition (example: NE for not equal)
Register Specifications
An Any address register n (example: A3 is address register 3)
Ay,Ax Source and destination address registers, respectively
Dn Any data register n (example: D5 is data register 5)
Dy,Dx Source and destination data registers, respectively
Rc Any control register (example VBR is the vector base register)
Rm MAC registers (ACC, MAC, MASK)
Rn Any address or data register Rw Destination register w (used for MAC instructions only)
Ry,Rx Any source and destination registers, respectively
Xi index register i (can be an address or data register: Ai, Di)
Register Names
ACC MAC accumulator register
CCR Condition code register (lower byte of SR)
MACSR MAC status register
MASK MAC mask register
PC Program counter SR Status register
Port Names
DDATA Debug data port
PST Processor status port
Miscellaneous Operands
#<data> Immediate data following the 16-bit operation word of the instruction
<ea> Effective address
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-13
ColdFire Core
Table 2-6. Notational Conventions (continued)
Instruction Operand Syntax
<ea>y,<ea>x Source and destination effective addresses, respectively
<label> Assembly language program label
<list> List of registers for MOVEM instruction (example: D3–D0)
<shift> Shift operation: shift left (<<), shift right (>>)
<size> Operand data size: byte (B), word (W), longword (L)
bc Instruction cache
# <vector> Identifies the 4-bit vector number for trap instructions
<> identifies an indirect data address referencing memory
<xxx> identifies an absolute address referencing memory
dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+ Arithmetic addition or postincrement indicator
– Arithmetic subtraction or predecrement indicator x Arithmetic multiplication
/ Arithmetic division ~ Invert; operand is logically complemented & Logical AND
| Logical OR
^ Logical exclusive OR << Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→ Source operand is moved to destination operand
←→ Two operands are exchanged
sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition> then <operations> else <operations>
Test the condition. If the condition is true, the operations in the then clause are performed. If the condition is false and the optional else clause is present, the operations in the else clause are performed. If the condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-14 Freescale Semiconductor
Table 2-6. Notational Conventions (continued)
Instruction Operand Syntax
Subfields and Qualifiers
{} Optional operation () Identifies an indirect address
d
n
Address Calculated effective address (pointer)
Bit Bit selection (example: Bit 3 of D0) lsb Least significant bit (example: lsb of D0)
LSB Least significant byte
LSW Least significant word
msb Most significant bit
MSB Most significant byte
MSW Most significant word
CCarry N Negative VOverflow X Extend ZZero
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
Condition Code Register Bit Names
ColdFire Core

2.6.1 Instruction Set Summary

Table 2-7 lists implemented user-mode instructions by opcode.
Table 2-7. User-Mode Instruction Set Summary
Instruction Operand Syntax Operand Size Operation
ADD Dy,<ea>x
<ea>y,Dx ADDA <ea>y,Ax .L Source + destination → destination ADDI #<data>,Dx .L Immediate data + destination → destination ADDQ #<data>,<ea>x .L Immediate data + destination → destination ADDX Dy,Dx .L Source + destination + X → destination AND Dy,<ea>x
<ea>y,Dx ANDI #<data>,Dx .L Immediate data & destination → destination ASL Dy,Dx
#<data>,Dx ASR Dy,Dx
#<data>,Dx Bcc <label> .B,.W If condition true, then PC + 2 + d
.L .L
.L .L
.L .L
.L .L
Source + destination → destination
Source & destination → destination
X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #<data>) ← 0
MSB → (Dx >> Dy) → X/C MSB → (Dx >> #<data>) → X/C
n
→ PC
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-15
ColdFire Core
Table 2-7. User-Mode Instruction Set Summary (continued)
Instruction Operand Syntax Operand Size Operation
BCHG Dy,<ea>x
#<data>,<ea-1>x BCLR Dy,<ea>x
#<data>,<ea-1>x BRA <label> .B,.W PC + 2 + d BSET Dy,<ea>x
#<data>,<ea-1>x
.B,.L .B,.L
.B,.L .B,.L
.B,.L .B,.L
~(<bit number> of destination) → Z, Bit of destination
~(<bit number> of destination) → Z; 0 → bit of destination
→ PC
n
~(<bit number> of destination) → Z;
1→ bit of destination BSR <label> .B,.W SP – 4 → SP; next sequential PC→ (SP); PC + 2 + d BTST Dy,<ea>x
#<data>,<ea-1>x
.B,.L .B,.L
~(<bit number> of destination) → Z
CLR <ea>y,Dx .B,.W,.L 0 → destination CMP <ea>y,Ax .L Destination – source CMPA <ea>y,Dx .L Destination – source CMPI <ea>y,Dx .L Destination – immediate data DIVS <ea-1>y,Dx
<ea>y,Dx
.W .L
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Signed operation DIVU <ea-1>y,Dx
Dy,<ea>x
.W .L
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Unsigned operation EOR Dy,<ea>x .L Source ^ destination → destination EORI #<data>,Dx .L Immediate data ^ destination → destination EXT #<data>,Dx .B →.W
Sign-extended destination → destination
.W →.L
EXTB Dx .B →.L Sign-extended destination → destination
1
HALT
None Unsized Enter halted state JMP <ea-3>y Unsized Address of <ea> → PC JSR <ea-3>y Unsized SP – 4 → SP; next sequential PC → (SP); <ea> → PC LEA <ea-3>y,Ax .L <ea> → Ax LINK Ax,#<d16> .W SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP LSL Dy,Dx
#<data>,Dx LSR Dy,Dx
#<data>,Dx MAC Ry,RxSF .L + (.W × .W) → .L
.L .L
.L .L
.L + (.L × .L) → .L
X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #<data>) ← 0
0 → (Dx >> Dy) → X/C 0 → (Dx >> #<data>) → X/C
ACC + (Ry × Rx){<< 1 | >> 1} → ACC ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea>y{&MASK}) → Rw
MACL Ry,RxSF,<ea-1>y,Rw .L + (.W × .W) → .L, .L
.L + (.L × .L) → .L, .L
ACC + (Ry × Rx){<< 1 | >> 1} → ACC ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) → Rw
MOVE <ea>y,<ea>x .B,.W,.L <ea>y → <ea>x
→ PC
n
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-16 Freescale Semiconductor
Table 2-7. User-Mode Instruction Set Summary (continued)
Instruction Operand Syntax Operand Size Operation
ColdFire Core
MOVE from MAC
MASK,Rx
ACC,Rx
.L Rm → Rx
MACSR,Rx
MACSR,CCR .L MACSR → CCR MOVE to
MAC
Ry,ACC
Ry,MACSR
.L Ry → Rm
Ry,MASK
#<data>,ACC
.L #<data> → Rm #<data>,MACSR #<data>,MASK
MOVE from
CCR,Dx .W CCR → Dx
CCR MOVE to
CCR
Dy,CCR #<data>,CCR
.B Dy → CCR
#<data> → CCR MOVEA <ea>y,Ax .W,.L → .L Source → destination MOVEM #<list>,<ea-2>x
<ea-2>y,#<list>
.L .L
Listed registers → destination
Source → listed registers MOVEQ #<data>,Dx .B → .L Sign-extended immediate data → destination MSAC Ry,RxSF .L - (.W × .W) → .L
ACC – (Ry × Rx){<< 1 | >> 1} → ACC
.L - (.L × .L) → .L
MSACL Ry,RxSF,<ea-1>y,Rw .L - (.W × .W) → .L, .L
.L - (.L × .L) → .L, .L
MULS <ea>y,Dx .W X .W → .L
.L X .L → .L
MULU <ea>y,Dx .W X .W → .L
.L X .L → .L
ACC – (Ry × Rx){<< 1 | >> 1} → ACC;
(<ea-1>y{&MASK}) → Rw
Source × destination
→ destination
Signed operation
Source × destination → destination
Unsigned operation NEG Dx .L 0 – destination → destination NEGX Dx .L 0 – destination – X → destination NOP none Unsized Synchronize pipelines; PC + 2 → PC NOT Dx .L ~ Destination → destination OR <ea>y,Dx
.L Source | destination → destination
Dy,<ea>x ORI #<data>,Dx .L Immediate data | destination → destination PEA <ea-3>y .L SP – 4 → SP; Address of <ea> → (SP) PULSE none Unsized Set PST= 0x4 REMS <ea-1>,Dx .L Dx/<ea>y → Dw {32-bit remainder}
Signed operation
REMU <ea-1>,Dx .L Dx/<ea>y → Dw {32-bit remainder}
Unsigned operation RTS none Unsized (SP) → PC; SP + 4 → SP Scc Dx .B If condition true, then 1s ⎯ destination;
Else 0s → destination
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-17
ColdFire Core
Table 2-7. User-Mode Instruction Set Summary (continued)
Instruction Operand Syntax Operand Size Operation
SUB <ea>y,Dx
Dy,<ea>x
.L
Destination – source → destination
.L SUBA <ea>y,Ax .L Destination – source → destination SUBI #<data>,Dx .L Destination – immediate data → destination SUBQ #<data>,<ea>x .L Destination – immediate data → destination SUBX Dy,Dx .L Destination – source – X → destination SWAP Dx .W MSW of Dx ←→ LSW of Dx TRAP #<vector> Unsized SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP); SP – 2 → SP; format → (SP); Vector address → PC
TRAPF None
#<data>
Unsized
.W
.L
PC + 2 → PC PC + 4 → PC
PC + 6 → PC TST <ea>y .B,.W,.L Set condition codes UNLK Ax Unsized Ax →SP; (SP) → Ax; SP + 4 → SP WDDATA <ea>y .B,.W,.L <ea>y →DDATA port
1
By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode execution by setting CSR[UHE].
Table 2-8 describes supervisor-mode instructions.
Table 2-8. Supervisor-Mode Instruction Set Summary
Instruction Operand Syntax Operand Size Operation
CPUSHL (bc),(Ax) Unsized Invalidate instruction cache line
1
HALT MOVE from SR SR, Dx .W SR → Dx MOVE to SR Dy,SR
MOVEC Ry,Rc .L Ry → Rc
RTE None Unsized (SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield ⎯ SP STOP #<data> .W Immediate data → SR; enter stopped state WDEBUG <ea-2>y .L <ea-2>y → debug module
1
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
none Unsized Enter halted state
.W Source → SR
#<data>,SR
Rc Register Definition 0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x801 Vector base register (VBR) 0xC00 ROM base address register (ROMBAR) 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR)
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-18 Freescale Semiconductor
ColdFire Core

2.7 Instruction Timing

The timing data presented in this section assumes the following:
• The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP spends no time waiting for the IFP to supply opwords and/or extension words.
• The OEP experiences no sequence-related pipeline stalls. For the MCF5272,the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all store operations (except MOVEM), certain hardware resources within the processor are marked as busy for two clock cycles after the final DSOC cycle of the store instruction. If a subsequent store instruction is encountered within this two-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive store operations is two cycles.
• The OEP can complete all memory accesses without memory causing any stall conditions. Thus, timing details in this section assume an infinite zero-wait state memory attached to the core.
• All operand data accesses are assumed to be aligned on the same byte boundary as the operand size: — 16-bit operands aligned on 0-modulo-2 addresses — 32-bit operands aligned on 0-modulo-4 addresses Operands that do not meet these guidelines are misaligned. Table 2-9 shows how the core
decomposes a misaligned operand reference into a series of aligned accesses.
Table 2-9. Misaligned Operand References
A[1:0] Size Bus Operations Additional C(R/W)
x1 Word Byte, Byte 2(1/0) if read
1(0/1) if write
x1 Long Byte, Word, Byte 3(2/0) if read
2(0/2) if write
10 Long Word, Word 2(1/0) if read
1(0/1) if write
1
Each timing entry is presented as C(r/w), described as follows:
C is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all internal core cycles required to complete the instruction execution. r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation performing a read-modify write function is denoted as (1/1).
1
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-19
ColdFire Core

2.7.1 MOVE Instruction Execution Times

The execution times for the MOVE.{B,W,L} instructions are shown in the next tables. Table 2-12 shows the timing for the other generic move operations.
NOTE
For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is equivalent to the time using comparable An-relative mode.
ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)} ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}
The nomenclature “(xxx).wl” refers to both forms of absolute addressing, (xxx).w and (xxx).l.
Table 2-10 lists execution times for MOVE.{B,W} instructions.
Table 2-10. Move Byte and Word Execution Times
Destination
Source
Rx (Ax) (Ax)+ –(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl
Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) (Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) –(Ay) 3(1/0) 31/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)
(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —
(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —
(xxx).w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(xxx).l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —
(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —
#<xxx> 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — —
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-20 Freescale Semiconductor
Table 2-11 lists timings for MOVE.L.
Table 2-11. Move Long Execution Times
ColdFire Core
Source
Rx (Ax) (Ax)+ –(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl
Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (Ay)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) –(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
(d16,Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(xxx).w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(xxx).l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
#<xxx> 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —
Destination
Table 2-12 gives execution times for MOVE.L instructions accessing program-visible registers of the
MAC unit, along with other MOVE.L timings. Execution times for moving contents of the ACC or MACSR into a destination location represent the best-case scenario when the store instruction is executed and no load, MAC, or MSAC instructions are in the MAC execution pipeline. In general, these store operations require only one cycle for execution, but if they are preceded immediately by a load, MAC, or MSAC instruction, the MAC pipeline depth is exposed and execution time is three cycles.
Table 2-12. Move Execution Times
Effective Address
Opcode <ea>
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
move.l <ea>,ACC 1(0/0) — — — — — — 1(0/0)
move.l <ea>,MACSR 2(0/0) — — — — — — 2(0/0)
move.l <ea>,MASK 1(0/0) — — — — — — 1(0/0)
move.l ACC,Rx 1(0/0) — — — — — — —
move.l MACSR,CCR 1(0/0) — — — — — — —
move.l MACSR,Rx 1(0/0) — — — — — — —
move.l MASK,Rx 1(0/0) — — — — — — —
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-21
ColdFire Core
2.7.2 Execution Timings—One-Operand Instructions
Table 2-13 shows standard timings for single-operand instructions.
Table 2-13. One-Operand Instruction Execution Times
Effective Address
Opcode <ea>
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #xxx
clr.b <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — clr.w <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
clr.l <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
ext.w Dx 1(0/0) — — — — — — —
ext.l Dx 1(0/0) — — — — — — —
extb.l Dx 1(0/0) — — — — — — —
neg.l Dx 1(0/0) — — — — — — —
negx.l Dx 1(0/0) — — — — — — —
not.l Dx 1(0/0) — — — — — — —
scc Dx 1(0/0) — — — — — — —
swap Dx 1(0/0) — — — — — — —
tst.b <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
tst.w <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
tst.l <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)
2.7.3 Execution Timings—Two-Operand Instructions
Table 2-14 shows standard timings for two-operand instructions.
Table 2-14. Two-Operand Instruction Execution Times
Effective Address
Opcode <ea>
add.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) add.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
addi.l #imm,Dx 1(0/0) — — — — — — —
addq.l #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
addx.l Dy,Dx 1(0/0) — — — — — — —
and.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) and.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
andi.l #imm,Dx 1(0/0) — — — — — — —
asl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)
asr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0) bchg Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bchg #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-22 Freescale Semiconductor
ColdFire Core
Table 2-14. Two-Operand Instruction Execution Times (continued)
Effective Address
Opcode <ea>
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
bclr Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —
bclr #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — bset Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bset #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —
btst Dy,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —
btst #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —
cmp.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
cmpi.l #imm,Dx 1(0/0) — — — — — — — divs.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divu.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)
divs.l <ea>,Dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) — — — divu.l <ea>,Dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) — — —
eor.l Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
eori.l #imm,Dx 1(0/0) — — — — — — —
lea <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) — lsl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0) lsr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)
mac.w Ry,Rx 1(0/0) — — — — — — —
mac.l Ry,Rx 3(0/0) — — — — — — —
msac.w Ry,Rx 1(0/0) — — — — — — —
msac.l Ry,Rx 3(0/0) — — — — — — — mac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —
mac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — —
moveq #imm,Dx — — — — — — — 1(0/0)
msac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —
msac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — — muls.w <ea>,Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(0/0) mulu.w <ea>,Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 8(1/0) 6(1/0) 4(0/0)
muls.l <ea>,Dx 6(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) — — — mulu.l <ea>,Dx 6(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) — — —
or.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) or.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
or.l #imm,Dx 1(0/0) — — — — — — — rems.l <ea>,Dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) — — — remu.l <ea>,Dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) — — —
sub.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-23
ColdFire Core
Table 2-14. Two-Operand Instruction Execution Times (continued)
Effective Address
Opcode <ea>
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
sub.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
subi.l #imm,Dx 1(0/0) — — — — — — — subq.l #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — subx.l Dy,Dx 1(0/0) — — — — — — —

2.7.4 Miscellaneous Instruction Execution Times

Table 2-15 lists timings for miscellaneous instructions.
Table 2-15. Miscellaneous Instruction Execution Times
Effective Address
Opcode <ea>
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
cpushl (Ax) — 11(0/1) — — — — — —
link.w Ay,#imm 2(0/1) — — — — — — —
move.w CCR,Dx 1(0/0) — — — — — — — move.w <ea>,CCR 1(0/0) — — — — — — 1(0/0) move.w SR,Dx 1(0/0) — — — — — — — move.w <ea>,SR 7(0/0) — — — — — — 7(0/0)
movec Ry,Rc 9(0/1) — — — — — — —
1
movem.l
movem.l &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — —
nop 3(0/0) — — — — — — — pea <ea> — 2(0/1) — — 2(0/1)
pulse 1(0/0) — — — — — — —
stop #imm — — — — — — — 3(0/0)
trap #imm — — — — — — — 15(1/2)
trapf 1(0/0) — — — — — — —
trapf.w 1(0/0) — — — — — — —
trapf.l 1(0/0) — — — — — — —
unlk Ax 2(1/0) — — — — — — —
wddata.l <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —
wdebug.l <ea> — 5(2/0) — — 5(2/0) — — —
1
n is the number of registers moved by the MOVEM opcode.
2
PEA execution times are the same for (d16,PC).
3
PEA execution times are the same for (d8,PC,Xi*SF).
4
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
<ea>,&list — 1+n(n/0) — — 1+n(n/0) — — —
2
3(0/1)
3
2(0/1) —
4
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-24 Freescale Semiconductor

2.7.5 Branch Instruction Execution Times

Table 2-16 shows general branch instruction timing.
Opcode <ea>
bra — — — — 2(0/1) — — — bsr — — — — 3(0/1) — — —
jmp <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) —
jsr <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — rte — — 10(2/0) — — — — — rts — — 5(1/0) — — — — —
Table 2-17 shows timing for Bcc instructions.
Opcode Forward Taken Forward Not Taken Backward Taken Backward Not Taken
Table 2-16. General Branch Instruction Execution Times
Effective Address
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
Table 2-17. Bcc Instruction Execution Times
ColdFire Core
bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0)

2.8 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 family processors include the following:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single, self-aligning system stack pointer
ColdFire processors use an instruction restart exception model but require more software support to recover from certain access errors. See Table 2-18 for details.
Exception processing can be defined as the time from the detection of the fault condition until the fetch of the first handler instruction has been initiated. It is comprised of the following four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an interrupt exception also forces SR[M] to be cleared and the interrupt priority mask to be set to the level of the current interrupt request.
2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a peripheral device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-25
ColdFire Core
3. The processor saves the current context by creating an exception stack frame on the system stack. ColdFire processors support a single stack pointer in the A7 address register; therefore, there is no notion of separate supervisor and user stack pointers. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally , the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter in the exception stack frame defines the address of the faulting instruction (fault) or of the next instruction to be executed (next).
4. The processor acquires the address of the first instruction of the exception handler. The exception vector table is aligned on a 1-Mbyte boundary. This instruction address is obtained by fetching a value from the table at the address defined in the vector base register . The index into the exception table is calculated as 4 x vector_number. When the index value is generated, the vector table contents determine the address of the first instruction of the desired handler . After the fetch of the first opcode of the handler is initiated, exception processing terminates and normal instruction processing continues in the handler.
ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address boundary; see
Table 2-18. The table contains 256 exception vectors where the first 64 are defined by Freescale; the
remaining 192 are user-defined interrupt vectors.
Table 2-18. Exception Vector Assignments
Vector
Numbers
0 000 — Initial stack pointer 1 004 — Initial program counter 2 008 Fault Access error 3 00C Fault Address error 4 010 Fault Illegal instruction 5 014 Fault Divide by zero
6–7 018–01C — Reserved
8 020 Fault Privilege violation
9 024 Next Trace 10 028 Fault Unimplemented line-a opcode 11 02C Fault Unimplemented line-f opcode 12 030 Next Debug interrupt 13 034 — Reserved 14 038 Fault Format error 15 03C Next Uninitialized interrupt
16–23 040–05C — Reserved
24 060 Next Spurious interrupt
25–31 064–07C Next Level 1–7 autovectored interrupts 32–47 080–0BC Next Trap #0–15 instructions 48–60 0C0–0F0 — Reserved
Vector Offset
(Hex)
Stacked
Program Counter
1
Assignment
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-26 Freescale Semiconductor
Table 2-18. Exception Vector Assignments (continued)
ColdFire Core
Vector
Numbers
61 0F4 Fault Unsupported instruction
62–63 0F8–0FC — Reserved
64–255 100–3FC Next User-defined interrupts
1
The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC of the instruction that immediately follows the instruction that caused the fault.
Vector Offset
(Hex)
Stacked
Program Counter
1
Assignment
ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register.

2.8.1 Exception Stack Frame Definition

The exception stack frame is shown in Figure 2-10. The first longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register . The second longword contains the 32-bit program counter address.
31 28 27 26 25 18 17 16 15 0
A7→ Format FS[3–2] Vector[7–0] FS[1–0] Status Register
+ 0x04 Program Counter [31–0]
Figure 2-10. Exception Stack Frame Form
The 16-bit format/vector word contains three unique fields:
• Format field—This 4-bit field at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. See Table 2-19. This field records any longword misalignment of the stack pointer that may have existed when the exception occurred.
Table 2-19. Format Field Encoding
Original A7 at Time of
Exception, Bits 1–0
00 Original A[7–8] 0100 01 Original A[7–9] 0101 10 Original A[7–10] 0110 11 Original A[7–11] 0111
A7 at First Instruction of
Handler
Format Field Bits
31–28
• Fault status field—The 4-bit field, FS[3–0], at the top of the system stack is defined for access and address errors along with interrupted debug service routines. See Table 2-20.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-27
ColdFire Core
Table 2-20. Fault Status Encodings
FS[3–0] Definition
0000-001x Reserved
0100 Error on instruction fetch
0101–011x Reserved
1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read
1101–111x Reserved
• Vector number—This 8-bit field, vector[7–0], defines the exception type. It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-18.

2.8.2 Processor Exceptions

Table 2-21 describes MCF5272 exceptions.
Table 2-21. MCF5272 Exceptions
Exception Description
Access Error Caused by an error when accessing memory. For an access error on an instruction fetch, the processor
postpones the error reporting until the instruction at the faulted reference is executed. Thus, faults that occur during instruction prefetches that are followed by a change of instruction flow do not generate an exception. When the processor attempts to execute an instruction with a faulted opword or extension word, the access error is signaled, and the instruction is aborted. For this type of exception, the programming model is not altered by the faulted instruction. If an access error occurs on an operand read, the processor immediately aborts the current instruction execution and initiates exception processing. In this case, any address register changes caused by the auto-addressing modes, (An)+ and -(An), have already occurred. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, registers updated before the fault occurs contain the memory operand. Due to the processor pipeline implementation, a write cycle may be decoupled from the execution of the instruction causing the write. Thus, if an access error occurs on an operand write, the signaling of the error is imprecise. Accordingly, the PC contained in the exception stack frame represents the location in the program when the access error is signaled, not necessarily the instruction causing the fault. All programming model updates associated with the write instruction are complete. The NOP instruction can be used to help identify write access errors. A NOP is not executed until all previous operations, including any pending writes are complete. Thus if any previous write terminates with an access error, it is guaranteed to be reported on the NOP.
Address Error Caused by an attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target
address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of 8 on an indexed effective addressing mode, or attempted execution of an instruction with a full-format indexed addressing mode.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
2-28 Freescale Semiconductor
Table 2-21. MCF5272 Exceptions (continued)
Exception Description
ColdFire Core
Illegal
Instruction
On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC) are decoded and generate an illegal instruction exception. Additionally, attempting to execute an illegal line A or line F opcode generates unique exception types: vectors 10 and 11, respectively. If any other nonsupported opcode is executed, the resulting operation is undefined. ColdFire processors do not provide illegal instruction detection on extension words of any instruction, including MOVEC. Attempting to execute an instruction with an illegal extension word causes undefined results.
Divide by Zero Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points to the
faulting instruction (DIVU, DIVS, REMU, REMS).
Privilege Violation
Tr ac e
Exception
Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire Programmer’s Reference Manual lists supervisor- and user-mode instructions.
ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this definition is the STOP instruction. If the processor is in trace mode, the instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reflects the just-loaded value. If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets the trace bit in the SR, hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reflects the just-loaded value. Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider a TRAP instruction executing in trace mode. The processor initiates the TRAP exception and passes control to the corresponding handler. If the system requires that a trace exception be processed, the TRAP exception handler must check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception.
Debug
Interrupt
Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the processor internally calculates the vector number (12). Additionally, the M bit and the interrupt priority mask fields of the SR are unaffected by the interrupt. See Section 2.2.2.1, “Status Register (SR).”
RTE and
Format Error
Exceptions
When an RTE instruction executes, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire processor, any attempted execution of an RTE where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original exception frame and the stacked PC points to RTE.The selection of the format value provides limited debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero; so, attempting an RTE using this old format generates a format error on a ColdFire processor. If the format field defines a valid type, the processor does the following: 1 Reloads the SR operand. 2 Fetches the second longword operand. 3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first longword
fetch.
4 Transfers control to the instruction address defined by the second longword operand in the stack frame.
TRAP Executing TRAP always forces an exception and is useful for implementing system calls. The trap instruction
may be used to change from user to supervisor mode.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 2-29

Chapter 3 Hardware Multiply/Accumulate (MAC) Unit

This chapter describes the MCF5272 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP).

3.1 Overview

The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family.
The MAC unit provides signal processing capabilities for the MCF5272 in a variety of applications including digital audio and servo control. Integrated as an execution unit in the processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-point fractional input operands.
The MAC unit provides functionality in three related areas:
• Signed and unsigned integer multiplies
• Multiply-accumulate operations supporting signed, unsigned, and signed fractional operands
• Miscellaneous register operations
Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this functionality is contained in a MAC module, as shown in Figure 3-1.
Operand Y Operand X
X
Shift 0,1,-1
+/-
Accumulator
Figure 3-1. ColdFire MAC Multiplication and Accumulation
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 3-1
Hardware Multiply/Accumulate (MAC) Unit
The MAC unit is tightly coupled to the OEP and features a three-stage execution pipeline. To minimize silicon costs, the ColdFire MAC is optimized for 16 x 16 multiply instructions. The OEP can issue a 16 x 16 multiply with a 32-bit accumulation and fetch a 32-bit operand in the same cycle. A 32 x 32 multiply with a 32-bit accumulation takes three cycles before the next instruction can be issued. Figure 3-1 shows the basic functionality of the ColdFire MAC. A full set of instructions is provided for signed and unsigned integers plus signed, fixed-point, fractional input operands.
The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints. For example, small digital filters can tolerate some variance in the execution time of the algorithm; larger , more complicated algorithms such as orthogonal transforms may have more demanding speed requirements exceeding the scope of any processor architecture and requiring a fully developed DSP implementation.
The M68000 architecture was not designed for high-speed signal processing, and a large DSP engine would be excessive in an embedded environment. In striking a middle ground between speed, size, and functionality , the ColdFire MAC unit is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle, 16 x 16 multiplies producing a 32-bit result, with a possible accumulation cycle following. This is common in a large portion of signal processing applications. In addition, the ColdFire core architecture has been modified to allow for an operand fetch in parallel with a multiply, increasing overall performance for certain DSP operations.

3.1.1 MAC Programming Model

Figure 3-2 shows the registers in the MAC portion of the user programming model.
31 0
MACSR MAC status register ACC MAC accumulator MASK MAC mask register
Figure 3-2. MAC Programming Model
These registers are described as follows:
• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.
• Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.
• MAC status register (MACSR)—This 8-bit register defines configuration of the MAC unit and contains indicator flags affected by MAC instructions. Unless noted otherwise, the setting of MACSR indicator flags is based on the final result, that is, the result of the final operation involving the product and accumulator.
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
3-2 Freescale Semiconductor
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use