Freescale MCF5235, MCF5234, MCF5233, MCF5232 User Guide

M5235EVB User’s Manual

Devices Supported:

MCF5235
MCF5234
MCF5233
MCF5232

Document Number: M5235EVBUM

Rev. 1.2
08/2005

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© Freescale Semiconductor, Inc. 2005. All rights reserved.

Document Number: M5235EVBUM
Rev. 1.2
08/2005

EMC Information on M523xEVB

1. This product as shipped from the factory with associated power supplies and cables, has been tested and
meets with requirements of EN5022 and EN 50082-1: 1998 as a CLASS A product.

2. This product is designed and intended for use as a development platform for hardware or software in an
educational or professional laboratory.

3. In a domestic environment this product may cause radio interference in which case the user may be
required to take adequate measures.

4. Anti-static precautions must be adhered to when using this product.

5. Attaching additional cables or wiring to this product or modifying the products operation from the factory
default as shipped may effect its performance and also cause interference with other apparatus in the
immediate vicinity. If such interference is detected, suitable mitigating measures should be taken.

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor iii

WARNING

This board generates, uses, and can radiate radio frequency energy and, if not
installed properly, may cause interference to radio communications. As
temporarily permitted by regulation, it has not been tested for compliance with the
limits for class a computing devices pursuant to Subpart J of Part 15 of FCC rules,
which are designed to provide reasonable protection against such interference.
Operation of this product in a residential area is likely to cause interference, in
which case the user, at his/her own expense, will be required to correct the
interference.

M523xEVB User’s Manual, Rev. 1.2

iv Freescale Semiconductor

Contents

Paragraph
Number

Title

Page

Number

Chapter 1

M523xEVB

1.1 MCF5235 Microprocessor .............................................................................................. 1-3

1.2 System Memory .............................................................................................................. 1-6

1.2.1 External Flash ............................................................................................................. 1-6

1.2.2 SDRAM ...................................................................................................................... 1-7

1.2.3 ASRAM ...................................................................................................................... 1-7

1.2.4 Internal SRAM ............................................................................................................ 1-7

1.2.5 M523xEVB Memory Map .......................................................................................... 1-7

1.2.5.1 Reset Vector Mapping ............................................................................................ 1-8

1.3 Support Logic ................................................................................................................. 1-8

1.3.1 Reset Logic ................................................................................................................. 1-8

1.3.2 Clock Circuitry ......................................................................................................... 1-10

1.3.3 Watchdog Timer ....................................................................................................... 1-10

1.3.4 Exception Sources ..................................................................................................... 1-11

1.3.5 TA Generation .......................................................................................................... 1-11

1.3.6 User’s Program ......................................................................................................... 1-12

1.4 Communication Ports ................................................................................................... 1-12

1.4.1 UART0 and UART1 Ports ........................................................................................ 1-12

1.4.2 UART2/FlexCAN1 Port ........................................................................................... 1-13

1.4.3 FlexCAN0 Port ......................................................................................................... 1-13

1.4.4 10/100T Ethernet Port ............................................................................................... 1-14

1.4.5 eTPU ......................................................................................................................... 1-15

1.4.6 BDM/JTAG Port ....................................................................................................... 1-16

1.4.7 I2C ............................................................................................................................ 1-17

1.4.8 QSPI .......................................................................................................................... 1-18

1.4.9 USB Host and Device ............................................................................................... 1-18

1.5 Connectors and User Components ................................................................................ 1-19

1.5.1 Daughter Card Expansion Connectors ...................................................................... 1-19

1.5.2 Reset Switch (SW6) .................................................................................................. 1-23

1.5.3 User LEDs .................................................................................................................1-23

1.5.4 Other LEDs ............................................................................................................... 1-24

Chapter 2

Initialization and Setup

2.1 System Configuration ..................................................................................................... 2-1

2.2 Installation and Setup ......................................................................................................2-3

2.2.1 Unpacking ................................................................................................................... 2-3

2.2.2 Preparing the Board for Use ....................................................................................... 2-3

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor v

Contents

Paragraph
Number

2.2.3 Providing Power to the Board ..................................................................................... 2-3

2.2.4 Power Switch (SW4) .................................................................................................. 2-4

2.2.5 Power Status LEDs and Fuse ...................................................................................... 2-4

2.2.6 Selecting Terminal Baud Rate .................................................................................... 2-4

2.2.7 The Terminal Character Format ................................................................................. 2-5

2.2.8 Connecting the Terminal ............................................................................................ 2-5

2.2.9 Using a Personal Computer as a Terminal .................................................................. 2-5

2.3 System Power-up and Initial Operation .......................................................................... 2-8

2.4 Using The BDM Port ...................................................................................................... 2-8

Title

Page

Number

Chapter 3

Using the Monitor/Debug Firmware

3.1 What Is dBUG? ...............................................................................................................3-1

3.2 Operational Procedure .................................................................................................... 3-2

3.2.1 System Power-up ........................................................................................................ 3-2

3.2.2 System Initialization ................................................................................................... 3-3

3.2.2.1 External RESET Button .......................................................................................... 3-4

3.2.2.2 ABORT Button ....................................................................................................... 3-4

3.2.2.3 Software Reset Command ...................................................................................... 3-4

3.3 Command Line Usage .................................................................................................... 3-4

3.4 Commands ...................................................................................................................... 3-5

3.5 TRAP #15 Functions .................................................................................................... 3-39

3.5.1 OUT_CHAR ............................................................................................................. 3-39

3.5.2 IN_CHAR ................................................................................................................. 3-40

3.5.3 CHAR_PRESENT .................................................................................................... 3-40

3.5.4 EXIT_TO_dBUG ...................................................................................................... 3-41

Appendix A

Configuring dBUG for Network Downloads

A.1 Required Network Parameters ......................................................................................... 4-1

A.2 Configuring dBUG Network Parameters......................................................................... 4-1

A.3 Troubleshooting Network Problems................................................................................ 4-2

Appendix B
Schematics

Appendix C

Evaluation Board BOM

M523xEVB User’s Manual, Rev. 1.2

vi Freescale Semiconductor

Figures

Figure
Number

1-1 M523xEVB Block Diagram ..................................................................................................... 1-3

1-2 MCF5235 Block Diagram ........................................................................................................1-5

1-3 External Memory Scheme ........................................................................................................ 1-6

1-4 J1- BDM Connector Pin Assignment ..................................................................................... 1-17

2-1 Minimum System Configuration .............................................................................................. 2-2

2-2 2.1mm Power Connector .......................................................................................................... 2-3

2-3 2-Lever Power Connector......................................................................................................... 2-4

2-4 Pin Assignment for Female (Terminal) Connector................................................................... 2-5

2-5 Jumper Locations...................................................................................................................... 2-7

3-1 Flow Diagram of dBUG Operational Mode ............................................................................. 3-3

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor Freescale Semiconductor Internal Use Only vii

Figures

Figure
Number

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

viii Freescale Semiconductor Internal Use Only Freescale Semiconductor

Tables

Table
Number

1-1 M523x Product Family ............................................................................................................. 1-1

1-2 The M523xEVB Default Memory Map.................................................................................... 1-8

1-3 D[20:19] External Boot Chip Select Configuration ................................................................. 1-8

1-4 SW7-1 RCON ........................................................................................................................... 1-9

1-5 SW7-2 JTAG_EN ..................................................................................................................... 1-9

1-6 SW7-[4:3] Encoded Clock Mode ............................................................................................. 1-9

1-7 SW7-5 Chip Configuration Mode............................................................................................. 1-9

1-8 SW7-[7:6] Boot Device ............................................................................................................ 1-9

1-11 M523xEVB Clock Source Selection ...................................................................................... 1-10

1-9 SW7-8 Bus Drive Strength .....................................................................................................1-10

1-10 SW7-[10:9] Address/Chip Select Mode ................................................................................. 1-10

1-12 UART2/FlexCAN1 Jumper Configuration............................................................................. 1-13

1-13 FlexCAN1 Jumper Configuration........................................................................................... 1-13

1-14 FlexCAN0 Jumper Configuration........................................................................................... 1-13

1-15 CAN Bus Connector Pinout....................................................................................................1-14

1-16 Ethernet/eTPU Jumper Configuration .................................................................................... 1-15

1-17 eTPU Header Pin Assignment ................................................................................................ 1-16

1-18 USB DMA Enable and Disable Settings ................................................................................ 1-18

1-19 J7............................................................................................................................................. 1-19

1-20 J8............................................................................................................................................. 1-20

1-21 J9............................................................................................................................................. 1-21

1-22 J10........................................................................................................................................... 1-22

1-23 User LEDs............................................................................................................................... 1-23

1-24 LED Functions........................................................................................................................ 1-24

2-1 Power LEDs.............................................................................................................................. 2-4

2-2 Pin Assignment for Female (Terminal) Connector................................................................... 2-5

3-1 dBUG Command Summary...................................................................................................... 3-5

C-1 M523xEVB Bill of Materials ...................................................................................................6-2

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor Freescale Semiconductor Internal Use Only ix

Tables

Table
Number

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

x Freescale Semiconductor Internal Use Only Freescale Semiconductor

Chapter 1 M523xEVB

This document details the setup and configuration of the ColdFire M523xEVB evaluation board (hereafter
referred to as the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the
MCF523x family of ColdFire microprocessors and to facilitate hardware and software development. The
EVB can be used by software and hardware developers to test programs, tools, or circuits without having
to develop a complete microprocessor system themselves. All special features of the MCF523x family are
supported.

The heart of the evaluation board is the MCF5235, all the other M523x family members have a subset of
the MCF5235 specification and can therefore be fully emulated using the MCF5235 device. Table 1-1
below details the full product family.

Table 1 - 1 . M5 2 3x Product Family

Part Number Package eTPU FEC CRYPTO CAN

MCF5232CAB80 160 QFP 16-channel No No 1

MCF5232CVM100 196 MAPBGA 16-channel No No 1

MCF5232CVM150 196 MAPBGA 16-channel No No 1

MCF5233CVM100 256 MAPBGA 32-channel No No 2

MCF5233CVM150 256 MAPBGA 32-channel No No 2

MCF5234CVM100 256 MAPBGA 16-channel Yes No 1

MCF5234CVM150 256 MAPBGA 16-channel Yes No 1

MCF5235CVM100 256 MAPBGA 16-channel Yes Yes 2

MCF5235CVM150 256 MAPBGA 16-channel Yes Yes 2

All of the devices in the same package are pin compatible.

The EVB provides for low cost software testing with the use of a ROM resident debug monitor, dBUG,
programmed into the external Flash device. Operation allows the user to load code in the on-board RAM,
execute applications, set breakpoints, and display or modify registers or memory. No additional hardware
or software is required for basic operation.

Specifications:

• Motorola MCF5235 Microprocessor (150 MHz max core frequency)

• External Clock source: 25 MHz

• Operating temperature: 0°C to +70°C

• Power requirement: 7–14V DC @ 300 ma Typical

• Power output: 5V, 3.3V and 1.5V regulated supplies

• Board Size: 10.00 × 5.40 inches, 8 layers

Memory Devices:

• 16-Mbyte SDRAM

• 2-Mbyte (512K × 16) Page Mode FLASH or 4-Mbyte (512K × 32) Page mode FLASH

• 1-Mbyte ASRAM (optional)

• 64-Kbyte SRAM internal to MCF523x device

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor 1-1

M523xEVB

Peripherals:

• Ethernet port 10/100Mb/s (Dual-Speed Fast Ethernet Transceiver, with MII)

• UART0 (RS-232 serial port for dBUG firmware)

• UART1 (auxiliary RS-232 serial port)

• UART2 (auxiliary1 RS-232 serial port jumper selectable with FlexCAN1)

• Enhanced Time Processor Unit (eTPU)

2

•I

C interface

• QSPI interface to ADC

• FlexCan0 interface

• USB Host and Device Interface

• BDM/JTAG interface

User Interface:

• Reset logic switch (debounced)

• Boot logic selectable (dip switch)

• Abort/IRQ7 logic switch (debounced)

• PLL Clocking options - Oscillator, Crystal or SMA for external clocking signals

• LEDs for power-up indication, general purpose I/O, and timer output signals

• Expansion connectors for daughter card

• UNI-3 connector for motor control cards

Software:

• Resident firmware package that provides a self-contained programming and operating
environment (dBUG)

M523xEVB User’s Manual, Rev. 1.2

1-2 Freescale Semiconductor

MCF5235 Microprocessor

r

DB-9 (2)

connector

RJ-45

connector

DB-9

connector

DB-9

connector

RS-232

transceivers (2)

Ethernet

Transceiver*

25 MHz

Osc.

CAN Transceiver

RS-232 / CAN

Transceiver

ColdFire MCF523X

Peripheral signals

Data [31:0]

Address [23:0]

Control Signals

26-pin Debug Heade

Clocking

circuitry

25 MHz

Osc.

USB 2.0 Host & Device

ADC

ETPU Headers*

SDRAM

16 Mbytes

Flash

2-4 Mbytes

ASRAM

1 Mbyte

(4) 60 pin Daughter Card

expansion connectors

*There is a jumper that allows the option of choosing between 16 eTPU channels and

Ethernet or 32 eTPU channels and no Ethernet

Figure 1-1. M523xEVB Block Diagram

1.1 MCF5235 Microprocessor

The microprocessor used on the EVB is the highly integrated Motorola MCF5235 32-bit ColdFire
variable-length RISC processor. The MCF5235 implements a ColdFire Version 2 core with a maximum
core frequency of 150 MHz and external bus speed of 75 MHz. Features of the MCF5235 include:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 (Dhrystone 2.1)
MIPS @ 150 MHz

• eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with
debug support

• 64 Kbytes of internal SRAM

• External bus speed of one half the CPU operating frequency (75 MHz bus @ 150 MHz core)

• 10/100 Mbps bus-mastering Ethernet controller

• 8 Kbytes of configurable instruction/data cache

• Three universal asynchronous receiver/transmitters (UARTs) with DMA support

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Freescale Semiconductor 1-3

M523xEVB

• Controller area network 2.0B (FlexCAN module)
— Optional second FlexCAN module multiplexed with the third UART

• Inter-integrated circuit (I

2

C) bus controller

• Queued serial peripheral interface (QSPI) module

• Hardware cryptography accelerator (optional)
— Random number generator

— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator

• Four channel 32-bit direct memory access (DMA) controller

• Four channel 32-bit input capture/output compare timers with optional DMA support

• Four channel 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Interrupt controller capable of handling up to 126 interrupt sources

• Clock module with Phase Locked Loop (PLL)

• External bus interface module including a 2-bank synchronous DRAM controller

• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode FLASH
memories

The MCF5235 communicates with external devices over a 32-bit wide data bus, D[31:0]. The MCF5235
can address a 32 bit address range. However, only 24 bits are available on the external bus A[23:0]. There
are internally generated chip selects to allow the full 32 bit address range to be selected. There are regions
that can be decoded to allow supervisor, user, instruction, and data each to have the 32-bit address range.

All the processor's signals are available via daughter card expansion connectors. Refer to the schematic
(Appendix B) for their pin assignments.

The MCF5235 processor has the capability to support both BDM and JTAG. These ports are multiplexed
and can be used with third party tools to allow the user to download code to the board. The board is
configured to boot up in the normal/BDM mode of operation. The BDM signals are available at the port
labeled BDM.

Figure 1-2 shows the MCF5235 processor block diagram.

M523xEVB User’s Manual, Rev. 1.2

1-4 Freescale Semiconductor

(To/From PADI)

(To/From PADI)

(To/From

PAD I)

MUX

DREQ[2:0]

JTAG_EN

FAST

ETHERNET

CONTROLLER

(FEC)

4 CH DMA

DACK[2:0]

(To/From SRAM backdoor)

Arbiter

UART

UART

0

1

DTIM

DTIM

0

V2 ColdFire CPU

BDM

UART

2

1

DIV

INTC0

DTIM

2

2

I

INTC1

C

EMAC

QSPI

DTIM

3

EIM

CHIP

SELECTS

EBI

SDRAMC

MCF5235 Microprocessor

SDRAMC

QSPI

SDA

SCL

UnTXD

UnRXD

UnRTS

UnCTS

TnOUT

TnIN

FEC

PAD I

D[31:0]

A[23:0]

R/

W

CS[3:0]

TA

TSIZ[1:0]

TEA

BS[3:0]

JTAG

TAP

Watchdog

Timer

SKHA

RNGA

MDHA

Cryptography

Modules

64 Kbytes

SRAM

(8Kx16)x4

8 Kbytes

CACHE

(1Kx32)x2

(To/From Arbiter)

PLL

PIT0

CLKGEN

(To/From INTC)

Edge

Port

Figure 1-2. MCF5235 Block Diagram

PORTS

(GPIO)

CIM

PIT1 PIT2 PIT3

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Freescale Semiconductor 1-5

M523xEVB

1.2 System Memory

The following diagram shows the external memory implementation on the EVB.

MPU

Data

Address

Control

Buffers

SDRAM

(16 Mbytes)

Expansion

Connectors

Figure 1-3. External Memory Scheme

NOTE:

ASRAM

(1 Mbyte)

Flash

(512K × 16

or

512K × 32)

The external bus interface signals to the external ASRAM and FLASH (and
USB) are buffered. This is in order not to exceed the maximum output load
capacitance of the microprocessor on the EVB. The signals to the expansion
connectors remain unbuffered to provide a “true” interface to the user.

1.2.1 External Flash

The EVB is fitted with a single 512K × 16 page-mode FLASH memory (U19) giving a total memory space
of 2Mbytes. Alternatively a footprint is available for the EVB user to upgrade this device to a 512K × 32
page-mode FLASH memory (U35), doubling the memory size to 4Mbytes. Either U19 OR U35 should be
fitted on the board - both devices cannot be populated at the same time. Refer to the specific device data
sheet and sample software provided for configuring the FLASH memory.

Users should note that the debug monitor firmware is installed in this flash device. Development tools or
user application programs may erase or corrupt the debug monitor. If the debug monitor becomes
corrupted and it’s operation is desired, the firmware must be programmed into the flash by applying a
development port tool such as BDM. Users should use caution to avoid this situation. The M523xEVB
dBUG debugger/monitor firmware is programmed into the lower sectors of Flash (0xFFE0_0000 to
0xFFE2_FFFF for 2Mbytes of FLASH or 0xFFC0_0000 to 0xFFC2_FFFF for 4 Mbytes of FLASH).

By default with U19 fitted on the EVB, jumper 64 (JP64) provides an alternative hardware mechanism for
write protection.

M523xEVB User’s Manual, Rev. 1.2

1-6 Freescale Semiconductor

System Memory

If the user has replaced U19 with the 32-bit FLASH device (U35), jumper 31 (JP31) has the same
functionality as JP64. U35 also has it’s own hardware write protect pin (C5) which protects the bottom
boot sector when pulled to ground.

1.2.2 SDRAM

The EVB is populated with 16 Mbytes of SDRAM. This is done with two devices (Micron
MT48LC4M16A2TG) each with a 16 bit data bus. Each device is organized as 1 Meg × 16 × 4 banks with
a 16 bit data bus. One device stores the upper 16-bit word and the other the lower 16 bit word of the
MCF523x 32 bit data bus.

1.2.3 ASRAM

The EVB has a footprint for two 512K × 16 Asynchronous SRAM devices (Cypress Semiconductor -
CY7C1041CV3310ZC). These memory devices (U1 and U2) may be populated by the user for
benchmarking purposes.

Also see Section 1.2.5, “M523xEVB Memory Map”.

1.2.4 Internal SRAM

The MCF5235 processor has 64-Kbytes of internal SRAM memory which may be used as data or
instruction memory. This memory is mapped to 0x2000_0000 and configured as data space but is not used
by the dBUG monitor except during system initialization. After system initialization is complete, the
internal memory is available to the user. The memory is relocatable to any 32-Kbyte boundary within the
processor’s four gigabyte address space.

1.2.5 M523xEVB Memory Map

Interface signals to support the interface to external memory and peripheral devices are generated by the
memory controller. The MCF5235 supports 8 external chip selects, CS[1:0] are used with external
memories, CS2 is used for the USB controller and CS[7:3] are easily accessible to users via the daughter
card expansion connectors. CS0 also functions as the global (boot) chip-select for booting out of external
flash.

Since the MCF5235 chip selects are fully programmable, the memory banks may be located at any
64-Kbyte boundary within the processor’s four gigabyte address space.

The default memory map for this board as configured by the Debug Monitor located in the external
FLASH bank can be found in table 1-2. The internal memory space of the MCF5235 is detailed further in
the MCF5235 Reference Manual. Chip Selects 0 and 1 can be changed by user software to map the external
memory in different locations but the chip select configuration such as wait states and transfer
acknowledge for each memory type should be maintained.

Chip Select Usage:

External FLASH Memory CS0
External ASRAM Memory CS1

Table 1-2 shows the M523xEVB memory map.

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor 1-7

M523xEVB

Table 1-2. The M523xEVB Default Memory Map

Address Range Signal and Device

0x0000_0000–0x00FF_FFFF 16 Mbyte SDRAM

0x2000_0000–0x2000_FFFF 64 Kbytes Internal SRAM

0x3000_0000–0x300F_FFFF External ASRAM (not fitted)

0xFFE0_0000–0xFFFF_FFFF
or
0xFFC0_0000–0xFFFF_FFFF

2 Mbytes External Flash
or
4 Mbytes External Flash

1.2.5.1 Reset Vector Mapping

Asserting the reset input signal to the processor causes a reset exception. The reset exception has the
highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.

The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing
by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s interrupt
priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero (0x00000000).
The control registers specifying the operation of any memories (e.g., cache and/or RAM modules)
connected directly to the processor are disabled.

Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword
at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program
counter. After the initial instruction is fetched from memory, program execution begins at the address in
the PC. If an access error or address error occurs before the first instruction is executed, the processor
enters the fault-on-fault halted state.

The Memory that the MCF5235 accesses at address 0 is determined at reset by sampling D[20:19].

Table 1-3. D[20:19] External Boot Chip Select Configuration

D[20:19] Boot Device/Data Port Size

00 External (32-bit)

01 External (16-bit)

10 External (8-bit)

11 External (32-bit)

1.3 Support Logic

1.3.1 Reset Logic

The reset logic provides system initialization. Reset occurs during power-on or via assertion of the signal
RESET which causes the MCF5235 to reset. RESET is triggered by the reset switch (SW6) which resets
the entire processor/system.

dBUG configures the MCF5235 microprocessor internal resources during initialization. The contents of
the exception table are copied to address 0x0000_0000 in the SDRAM. The Software Watchdog Timer is

M523xEVB User’s Manual, Rev. 1.2

1-8 Freescale Semiconductor

Support Logic

disabled, the Bus Monitor is enabled, and the internal timers are placed in a stop condition. A memory map
for the entire board can be seen in Table 1-2.

If the external RCON

pin is asserted (SW7-1 ON) during reset, then various chip functions, including the
reset configuration pin functions after reset, are configured according to the levels driven onto the external
data pins. See tables below on settings for reset configurations.

If the RCON

pin is not asserted (SW7-1 OFF) during reset, the chip configuration and the reset
configuration pin functions after reset are determined by the RCON register or fixed defaults, regardless
of the states of the external data pins.

SW7-1 Reset Configuration

OFF RCON

ON RCON is asserted, Chip functions, including the reset configuration after reset,

SW1-2 JTAG Enable

OFF JTAG interface enabled

ON BDM interface enabled

not asserted, Default Chip configuration or RCON register settings

are configured according to the levels driven onto the external data pins.

Table 1-6. SW7-[4:3] Encoded Clock Mode

SW7-3 SW7-4 Clock Mode

Table 1-4. SW7-1 RCON

Table 1-5. SW7-2 JTAG_EN

OFF OFF External clock mode- (PLL disabled)

OFF ON 1:1 PLL

ON OFF Normal PLL mode with external clock reference

ON ON Normal PLL mode w/crystal oscillator reference

Table 1-7. SW7-5 Chip Configuration Mode

SW7-5 RCON (SW7-1) Mode

OFF ON Reserved

ON ON Master

XOFF Master

Table 1-8. SW7-[7:6] Boot Device

SW7-6 SW7-7 RCON (SW7-1) Boot Device

OFF OFF ON External (32-bit)

OFF ON ON External (8-bit)

ON OFF ON External (16-bit)

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M523xEVB

Table 1-8. SW7-[7:6] Boot Device

SW7-6 SW7-7 RCON (SW7-1) Boot Device

ON ON ON External (32-bit)

X X OFF External (32-bit)

Table 1-9. SW7-8 Bus Drive Strength

SW7-8 RCON (SW7-1) Drive Strength

OFF ON Partial Bus Drive

ON ON Full Bus Drive

X OFF Partial Bus Drive

Table 1-10. SW7-[10:9] Address/Chip Select Mode

SW7-9 SW7-10 RCON (SW7-1) Mode

OFF OFF ON PADDR[7:5] = /CS[6:4]

OFF ON ON PADDR[7] = /CS6, PADDR[6:5] = A[22:21]

ON OFF ON PADDR[7:6] = /CS[6:5], PADDR[5] = A21

ON ON ON PADDR[7:5] = A[23:21]

X X OFF PADDR[7:5] = A[23:21]

1.3.2 Clock Circuitry

The are three options to provide the clock to the CPU. These options can be configured by setting
JP[35:37]. See Table 1-11 below.

Table 1-11. M523xEVB Clock Source Selection

JP35 JP36 JP37 Clock Selection

1-2 1-2 ON 25 MHz Oscillator (default setting)

2-3 1-2 ON 25 MHz External Clock

X 2-3 OFF 25 MHz Crystal (not populated)

The 25-MHz oscillator (U23) also feeds the Ethernet chip (U11).

There is also a 12-MHz crystal feeding the USB controller (U33).

1.3.3 Watchdog Timer

The dBUG Firmware does NOT enable the watchdog timer on the MCF5235.

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1-10 Freescale Semiconductor

Support Logic

1.3.4 Exception Sources

The ColdFire® family of processors can receive seven levels of interrupt priorities. When the processor
receives an interrupt which has a higher priority than the current interrupt mask (in the status register), it
will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt
acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the
device should provide the proper vector number to indicate where the service routine for this interrupt level
is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as an
autovector interrupt which directs the processor to a predefined entry in the exception table (refer to the
MCF5235 Reference Manual).

The processor goes to an exception routine via the exception table. This table is stored in the Flash
EEPROM. The address of the table location is stored in the VBR. The dBUG ROM monitor writes a copy
of the exception table into the RAM starting at $00000000. To set an exception vector, the user places the
address of the exception handler in the appropriate vector in the vector table located at $00000000 and then
points the VBR to $00000000.

The MCF5235 microprocessor has seven external interrupt request lines IRQ

[7:1]. The interrupt controller

is capable of providing up to 63 interrupt sources. These sources are:-

• External interrupt signals IRQ

[7:1] (EPORT)

• Software watchdog timer module

• Timer modules

• UART modules 0, 1 and 2

2

•I

C module

• DMA module

• QSPI module

• FEC module

•PIT

• Security module

• FlexCAN0 and FlexCAN1

•eTPU

All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request
must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have
it’s priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers apart from
interrupts 1-7 which have fixed priority already allocated to them.

No interrupt sources should have the same level and priority as another. Programming two interrupt
sources with the same level and priority can result in undefined operation.

The M523xEVB hardware uses IRQ7

to support the ABORT function using the ABORT switch (SW5).
This switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be
aborted without issuing a RESET (refer to Chapter 2 for more information on ABORT). Since the ABORT
switch is not capable of generating a vector in response to a level seven interrupt acknowledge from the
processor, the dBUG programs this interrupt request for autovector mode.

Refer to MCF5235 Reference Manual for more information about the interrupt controller.

1.3.5 TA Generation

The processor starts a bus cycle by asserting CSx with the other control signals. The processor then waits
for a transfer acknowledgment (TA) either from within (Auto acknowledge - AA mode) or from the

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M523xEVB

externally addressed device before it can complete the bus cycle. TA is used to indicate the completion of
the bus cycle. It also allows devices with different access times to communicate with the processor
properly asynchronously. The MCF5235 processor, as part of the chip-select logic, has a built-in
mechanism to generate TA for all external devices which do not have the capability to generate this signal.
For example the Flash ROM cannot generate a TA signal. The chip-select logic is programmed by the
dBUG ROM Monitor to generate TA internally after a pre-programmed number of wait states. In order to
support future expansion of the M523xEVB, the TA input of the processor is also connected to the
Processor Expansion Bus (J9, pin 44). This allows any expansion boards to assert this line to provide a TA
signal to the processor. On the expansion boards this signal should be generated through an open collector
buffer with no pull-up resistor; a pull-up resistor is included on this board. All TA signals from expansion
boards should be connected to this line.

1.3.6 User’s Program

JP64 on the 16Mbit FLASH (U19) or JP31 if using 32Mbit FLASH (U35) allows users to test code from
boot/POR without having to overwrite the ROM Monitor.

When the jumper is set between pins 1 and 2, the behavior of the system is normal, dBUG boots and then
runs from 0xFFE00000 (0xFFC00000). When the jumper is set between pins 2 and 3, the board boots from
the top half of the FLASH (0xFFF00000).

Procedure:

1. Compile and link as though the code was to be placed at the base of the flash.

2. Set up the jumper JP64 (JP31) for Normal operation, pin1 connected to pin 2.

3. Download to SDRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM via
a wiggler cable, download first, then start ROM Monitor by pointing the program counter (PC) to
0xFFE00400(0xFFC00400) and run.)

4. In the ROM Monitor, execute the 'FL write <dest> <src> <bytes>' command.

5. Move jumper JP64 (JP31) to pin 2 connected to pin 3 and push the reset button (SW6). User code
should now be running from reset/POR.

1.4 Communication Ports

The EVB provides external communication interfaces for two UART serial ports, a UART/FlexCAN1
port, FlexCan0 port, QSPI, I2C port, 10/100T ethernet port, eTPU port (including UNI3 and HS/ENCO
connectors for auxiliary motor control cards), USB Host port, USB Device port, and BDM/JTAG port.

1.4.1 UART0 and UART1 Ports

The MCF5235 device has three built in UARTs, each with its own software programmable baud rate
generator. Two of these UART interfaces are brought out to RS232 transceivers. One channel is the ROM
Monitor to Terminal output and the other is available to the user. The ROM Monitor programs the interrupt
level for UART0 to Level 3, priority 2 and autovector mode of operation. The interrupt level for UART1
is programmed to Level 3, priority 1 and autovector mode of operation. The signals from these channels
are available on expansion connectors J7 and J8. The signals of UART0 and UART1 are passed through
the RS-232 transceivers (U30) & (U31) and are available on DB-9 connectors (P4) and (P5).

Refer to the MCF5235 Reference Manual for programming the UART’s and their register maps.

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1-12 Freescale Semiconductor

Communication Ports

1.4.2 UART2/FlexCAN1 Port

The third UART on the MCF5235 is multiplexed with the second FlexCAN (FlexCAN1) module. As these
two modules are multiplexed such that the user has access to one or the other, the functionality on the EVB
is jumper selectable. Table 1-12 shows the jumper configuration to activate UART2 or FlexCAN1.

Table 1-12. UART2/FlexCAN1 Jumper Configuration

Jumper UART2 Setting FlexCAN1 Setting

JP7 1-2 2-3

JP12 1-2 2-3

JP25 2-3 X

JP26 2-3 X

JP50 2-3 1-2

JP51 2-3 1-2

JP52 2-3 1-2

The signals of UART2 are passed through RS-232 transceiver U32 and are jumper selectable (for settings
see Table 1-12) on DB-9 connector P6.

The CAN1TX and CAN1RX signals from FlexCAN1 are brought out to a 3.3-V CAN transceiver (Texas
Instruments - SN65HVD230D) and are jumper selectable (for settings see Table 1-12) on DB-9 connector
P6. Jumpers JP3 and JP4 control the CAN hardware configuration.

Table 1-13. FlexCAN1 Jumper Configuration

Jumper Function ON OFF

JP3 Transceiver mode Standby High Speed (No Slope

Control)

JP4 CAN Termination Terminating resistor

between CANL and CANH

No terminating resistor

1.4.3 FlexCAN0 Port

The EVB provides 1 dedicated CAN transceiver. The CAN0TX and CAN0RX signals are brought out to
a 3.3V CAN transceiver (Texas Instruments - SN65HVD230D). Jumper JP1 and JP2 control the CAN
hardware configuration.

Table 1-14. FlexCAN0 Jumper Configuration

Jumper Function ON OFF

JP1 Transceiver mode Standby High Speed (No Slope

Control)

JP2 CAN Termination Terminating resistor

between CANL and CANH

No terminating resistor

The CANL and CANH signals are brought out from the CAN transceiver to a female DB-9 connector (P1)
in the configuration below.

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M523xEVB

Table 1-15. CAN Bus Connector Pinout

DB-9 pin Signal

1,4-6,7-9 Not Connected

2CANL

3 Ground

7CANH

1.4.4 10/100T Ethernet Port

The MCF5235 microprocessor populated on the EVB is a superset device of the MCF523x family. The
upper 16 eTPU channels are multiplexed with the ethernet port giving the EVB user the choice of utilizing
either the full 32-channels of eTPU or 16-channels of eTPU with the Fast Ethernet Controller (FEC)
activated. Pin M4 on the MCF5235 configures the internal functionality of these 16 pins. If the user is
using the FEC, pin M4 must be pulled low by setting SW7-11 to the ON position.

These 16 pins are also jumper selectable between the eTPU and the FEC in order to isolate the external
circuitry required to implement the functionality of these modules. Table 1-16 lists the appropriate jumper
settings to enable eTPU or FEC functionality on these pins.

The MCF5235 device performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and
channel interface functions. The MCF5235 Ethernet Controller requires an external interface adaptor and
transceiver function to complete the interface to the ethernet media. The MCF5235 Ethernet module also
features an integrated fast (100baseT) Ethernet media access controller (MAC).

The Fast Ethernet controller (FEC) incorporates the following features:

• Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)

• IEEE 802.3 full duplex flow control

• Programmable max frame length supports IEEE 802.1 VLAN tags and priority

• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of
50 MHz

• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of
25 MHz

• Retransmission from transmit FIFO following a collision (no processor bus utilization)

• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)

• Address recognition
— Frames with broadcast address may be always accepted or always rejected

— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode

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1-14 Freescale Semiconductor

Communication Ports

For more details see the MCF523x Reference Manual. The on board ROM MONITOR is programmed to
allow a user to download files from a network to memory in different formats. The current compiler
formats supported are S-Record, COFF, ELF or Image.

Table 1-16. Ethernet/eTPU Jumper Configuration

Jumper Pin

JP5 D5 2-3 ERXER 1-2 23

JP9 C5 2-3 ETXCLK 1-2 22

JP10 B5 2-3 ETXD2 1-2 18

JP11 A5 2-3 ETXD1 1-2 17

JP13 D6 2-3 ETXEN 1-2 21

JP14 C6 2-3 ETXER 1-2 20

JP15 B6 2-3 ETXD3 1-2 19

JP16 C4 2-3 ERXD0 1-2 24

JP17 B7 2-3 ETXD0 1-2 16

JP18 C3 2-3 ERXD1 1-2 25

JP19 D4 2-3 ERXD2 1-2 26

JP20 D3 2-3 ERXD3 1-2 27

JP21 E3 2-3 ERXCLK 1-2 29

JP22 E4 2-3 ERXDV 1-2 28

JP23 F3 2-3 ECOL 1-2 31

JP24 F4 2-3 ECRS 1-2 30

Ethernet

Setting

Ethernet

Signal

eTPU

Setting

eTPU

Channel

1.4.5 eTPU

The eTPU is an intelligent programmable I/O controller with its own core and memory system, allowing
it to perform complex timing and I/O management independently of the CPU. The eTPU is essentially a
co-processor designed for timing control, I/O handling, serial communications, motor control. and engine
control applications and accesses data without the host CPU’s intervention. Consequently, the host CPU
setup and service times for each timer event are minimized or eliminated.

The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500
products. Enhancements of the eTPU include a more powerful processor which handles high-level C code
efficiently and allows for more functionality and increased performance. Although there is no
compatibility at microcode level, the eTPU maintains several features of older TPU versions and is
conceptually almost identical. The eTPU library is a superset of the standard TPU library functions
modified to take advantage of enhancements in the eTPU. These, along with a C compiler, make it
relatively easy to port older applications. By providing source code for the Motorola library, it is possible
for the eTPU to support the users own function development.

The eTPU has up to 32 timer channels in addition to having 6 Kbytes of code memory and 1.5 Kbytes of
data memory that stores software modules downloaded at boot time and that can be mixed and matched as
required for any specific application.

As mentioned in Section 1.4.4, “10/100T Ethernet Port,” the upper 16-channels of the eTPU are
multiplexed with the Fast Ethernet Controller.

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Refer to Table 1-16 to set the appropriate jumpers to enable 16 or 32-channels.

To configure the device to operate with the top 16-channels of the eTPU activated, pin M4 must be pulled
high by setting SW7-11 to the OFF position.

All 32 eTPU channels are available on a 0.1” 2x20 Molex connector providing easy access to the eTPU
for the EVB user.

Table 1-17. eTPU Header Pin Assignment

Pin eTPU Signal Pin eTPU Signal

1 +3.3V 2 +5V

3 TPUCH16 4 UTPUODIS

5 TPUCH17 6 LTPUODIS

7TPUCH18 8TPUCH0

9 TPUCH19 10 TPUCH1

11 TPUCH20 12 TPUCH2

13 TPUCH21 14 TPUCH3

15 TPUCH22 16 TPUCH4

17 TPUCH23 18 TPUCH5

19 TPUCH24 20 TPUCH6

21 TPUCH25 22 TPUCH7

23 TPUCH26 24 TPUCH8

25 TPUCH27 26 TPUCH9

27 TPUCH28 28 TPUCH10

29 TPUCH29 30 TPUCH11

31 TPUCH30 32 TPUCH12

33 TPUCH31 34 TPUCH13

35 GND 36 TPUCH14

37 TCRCLK 38 TPUCH15

39 GND 40 GND

There is a UNI3 connector and HS/ENCO connector on the EVB for connection to an auxiliary card.

The auxiliary card is intended for evaluation of the eTPU functionality.

1.4.6 BDM/JTAG Port

The MCF5235 processor has a Background Debug Mode (BDM) port, which supports Real-Time Trace
and Real-Time Debug. The signals which are necessary for debug are available at connector (J1).
Figure 1-4 shows the (J1) Connector pin assignment.

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1-16 Freescale Semiconductor

Communication Ports

DEVELOPER RESERVED

GND

GND

RESET

I/O or Pad Voltage

GND

PST2

PST0

DDATA2

DDATA0

MOTOROLA RESERVED

GND

Core Voltage

11

13

15

17

19

21

23

25

1

3

5

7

9

2

4

6

8

10

12

14

16

18

20

22

24

26

BKPT

DSCLK

DEVELOPER RESERVED

DSI

DSO

PST3

PST1

DDATA3

DDATA1

GND

MOTOROLA RESERVED

PSTCLK

TA

Figure 1-4. J1- BDM Connector Pin Assignment

The BDM connector can also be used to interface to JTAG signals. On reset, the JTAG_EN signal selects
between multiplexed debug module and JTAG signals. See Table 1-5.

1.4.7 I2C

The MCF5235’s I2C module includes the following features:

2

• Compatibility with the I

• Multi master operation

• Software programmable for one of 50 different clock frequencies

• Software selectable acknowledge bit

• Interrupt driven byte by byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Start and stop signal generation and detection

• Repeated start signal generation

• Acknowledge bit generation and detection

• Bus busy detection

Please see the MCF523x Reference Manual for more detail. The I
are brought out to expansion connector (J13).

2

The I

C functionality of the MCF5235 is multiplexed on the same pins as the QSPI. Jumpers JP6 and JP8
are used to connect/disconnect the I2C signals, SDA and SCL. To enable I2C JP6 and JP8 should be set
between pins 2 and 3.

C bus standard version 2.1

2

C signals from the MCF5235 device

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M523xEVB

1.4.8 QSPI

The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued
transfer capability. It will support up to 16 stacked transfers at one time, minimizing CPU intervention
between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.

Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module)
implemented in the MC68332 processor.

• Programmable queue to support up to 16 transfers without user intervention

• Supports transfer sizes of 8 to 16 bits in 1-bit increments

• Four peripheral chip-select lines for control of up to 15 devices

• Baud rates from 147.1-Kbps to 18.75-Mbps at 75 MHz.

• Programmable delays before and after transfers

• Programmable QSPI clock phase and polarity

• Supports wrap-around mode for continuous transfers

Please see the MCF523x Reference Manual for more detail. The QSPI signals from the MCF5235 device
are brought out to expansion connector (J12).

Some of the QSPI signals are multiplexed with the I
and 2 to enable the QSPI module.

The EVB features an A to D converter (ADC) interfaced to the CPU via the QSPI. The ADC uses QSPI
chip select 0. This chip select has a jumper that can be removed if the EVB user is not using the ADC and
wishes to connect QSPI_CS0 to an alternative device.

2

C module. JP6 and JP8 should be set between pins 1

1.4.9 USB Host and Device

The EVB features a USB controller interfaced externally to the MCF5235 via the DMA and external bus
modules. The USB controller can be configured to run in Host or Device mode.

There is a series “A” connector (Host) and a series “B” connector (Device) populated on the EVB. Either
one or the other can be used depending on whether the USB controller is configured to run in Host or
Device mode. JP56 must be set between pins 2 and 3 if the controller is configured in Host mode and
between pin 1 and 2 if the controller is configured in Device mode.

The USB controller also has On-The-Go (OTG) functionality. There is a footprint on the EVB for an OTG
Mini-AB connector if the user wants to utilize USB OTG. If using OTG JP55 must be fitted.

For more details see the Philips Semiconductor datasheet for the ISP1362 USB OTG controller.

There are a series of jumpers connected to the USB controller that allow the user to disconnect the DMA
and interrupt signals between the CPU and the USB controller if the USB controller is not in use. This
gives the user access to the DMA timer module channels 1 and 2 and an extra interrupt signal if they do
not require USB functionality. Table 1-18 details these jumper settings.

Table 1-18. USB DMA Enable and Disable Settings

Jumper Functionality when Jumper is Fitted Functionality when Jumper is NOT Fitted

JP57 USB DMA request signal DMA Timer 1 input enabled

JP58 USB DMA request signal DMA Timer 2 input enabled

JP59 USB DMA acknowledge signal DMA Timer 2 output enabled

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Connectors and User Components

Table 1-18. USB DMA Enable and Disable Settings

Jumper Functionality when Jumper is Fitted Functionality when Jumper is NOT Fitted

JP60 USB DMA acknowledge signal DMA Timer 1 output enabled

JP61 DACK1 not in use - pulled high DMA acknowledge 1 enabled

JP62 Interrupt 4 enabled for USB Interrupt 4 disabled from USB

JP63 DACK2 not in use - pulled high DMA acknowledge 2 enabled

1.5 Connectors and User Components

1.5.1 Daughter Card Expansion Connectors

Four, 60-way SMT connectors (J7, J8, J9 and J10) provide access to all MCF5235 signals. These
connectors are ideal for interfacing to a custom daughter card or for simple probing of processor signals.
Below is a pinout description of these connectors.

Table 1 - 1 9 . J 7

Pin Signal Pin Signal

1+5V 2+5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7GND 8GND

9 TPUCH24 10 TPUCH6

11 TPUCH17 12 TPUCH4

13 TPUCH18 14 TPUCH5

15 TPUCH22 16 TPUCH2

17 TPUCH23 18 TPUCH3

19 TPUCH19 20 TPUCH1

21 TPUCH20 22 TPUCH0

23 TPUCH21 24 GND

25 TPUCH16 26 EMDIO

27 U2CTS

29 I2C_SCL 30 I2C_SDA

31 QSPI_SCK 32 QSPI_DIN

33 BS3 34 QSPI_DOUT

28 EMDC

35 BS2 36 QSPI_PCS0

37 BS1

39 BS0 40 CAN1RX

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38 SD_SCKE

M523xEVB

Table 1-19. J7 (continued)

Pin Signal Pin Signal

41 U2RTS

43 QSPI_PCS1 44 U1CTS

45 U1RTS 46 CAN1TX

47 U1RXD 48 U2TXD

49 U1TXD 50 CS2

51 CS3 52 CS7

53 CS6 54 CS5

55 CS1 56 CS0

57 CS4 58 A23

59 GND 60 GND

42 U2RXD

Table 1 - 2 0 . J 8

Pin Signal Pin Signal

1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 TPUCH8 6 TPUCH7

7 TPUCH10 8 TPUCH9

9 TPUCH25 10 TPUCH12

11 TPUCH27 12 TPUCH11

13 TPUCH26 14 TPUCH14

15 TPUCH29 16 TPUCH13

17 TPUCH28 18 TCRCLK

19 TPUCH31 20 TPUCH15

21 TPUCH30 22 GND

23 GND 24 U0CTS

25 U0RXD 26 DTOUT0

27 DTIN0 28 U0TXD

29 U0RTS 30 GND

31 CLKMOD0 32 +3.3V

33 CLKMOD1 34 GND

35 GND 36 D28

37 D30 38 D29

39 D31 40 D24

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1-20 Freescale Semiconductor

Table 1-20. J8 (continued)

Pin Signal Pin Signal

41 D26 42 D25

43 D27 44 D21

45 D23 46 D22

Connectors and User Components

47 EXT_RSTIN

49 GND 50 GND

51 D13 52 D20

53 D9 54 D17

55 D12 56 D18

57 D15 58 D16

59 GND 60 GND

48 D19

Table 1 - 2 1 . J 9

Pin Signal Pin Signal

1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7GND 8GND

9A21 10A22

11 A19 12 A20

13 A17 14 A18

15 A16 16 A14

17 A15 18 A11

19 A13 20 GND

21 GND 22 A10

23 A12 24 A8

25 A9 26 A7

27 A6 28 A4

29 A5 30 GND

31 A2 32 A0

33 A3 34 A1

35 GND 36 GND

37 DTIN3 38 UTPUODIS

39 DTOUT3 40 LTPUODIS

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Table 1-21. J9 (continued)

Pin Signal Pin Signal

41 TIP

43 TS 44 TA

45 CAN0RX 46 SD_WE

47 R/W 48 CAN0TX

49 SD_CAS 50 SD_CS0

51 CLKOUT 52 SD_RAS

53 SD_CS1 54 DDATA3

55 XTAL 56 EXTAL

57 GND 58 GND

59 GND 60 GND

42 TEA

Table 1-22. J10

Pin Signal Pin Signal

1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5D14 6D10

7D11 8D6

9D7 10D8

11 D5 12 D4

13 GND 14 GND

15 D1 16 D2

17 D3 18 OE

19 D0 20 DTOUT1

21 DTIN1 22 +3.3V

23 +3.3V 24 IRQ6

25 IRQ7 26 TSIZ0

27 TSIZ1 28 IRQ2

29 IRQ3 30 IRQ4

31 IRQ5 32 TCLK/PSTCLK

33 DTOUT2 34 DTIN2

35 IRQ1

37 TDO/DSO 38 TMS/BKPT

39 TRST/DSCLK 40 GND

36 TDI/DSI

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Connectors and User Components

Table 1-22. J10 (continued)

Pin Signal Pin Signal

41 GND 42 PST3

43 PST1 44 PST2

45 PST0 46 DDATA0

47 DDATA2 48 DDATA1

49 GND 50 GND

51 JTAG_EN 52 RCON

53 GND 54 RSTOUT

55 GND 56 RESET

57 GND 58 GND

59 GND 60 GND

1.5.2 Reset Switch (SW6)

The reset logic provides system initilization. Reset occurs during power-on or via assertion of the signal
RESET which causes the MCF5235 to reset. Reset is also triggered by the reset switch (SW6) which resets
the entire processor/system.

A hard reset and voltage sense controller (U25) is used to produce an active low power-on RESET signal.
The reset switch SW6 is fed into U25 which generates the signal which is fed to the MCF5235 reset,
RESET

. The RESET signal is an open collector signal and so can be wire OR’ed with other reset signals
from additional peripherals. On the EVB, RESET is wire OR’d with the BDM reset signal and there is a
reset signal brought out to the expansion connectors for use with user hardware.

dBUG configures the MCF5235 microprocessor internal resources during initialization. The instruction
cache is invalidated and disabled. The Vector Base Register, VBR, contains an address which initially
points to the Flash memory. The contents of the exception table are written to address $00000000 in the
SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers
are placed in a stop condition. The interrupt controller registers are initialized with unique interrupt
level/priority pairs.

1.5.3 User LEDs

There are eight LEDs available to the user. Each of these LEDs are pulled to +3.3V through a 10 ohm
resistor and can be illuminated by driving a logic “0” on the appropriate signal to “sink” the current. Each
of these signals can be disconnected from it’s associated LED with a jumper. The table below details which
MCF5235 signal is associated with which LED.

Table 1-23. User LEDs

LED MCF5235 Signal Jumper to disconnect

D25 DTOUT0 JP38

D26 DTIN0 JP39

D27 DTOUT1 JP40

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Table 1-23. User LEDs

LED MCF5235 Signal Jumper to disconnect

D28 DTIN1 JP41

D29 DTOUT2 JP42

D30 DTIN2 JP43

D31 DTOUT3 JP44

D32 DTIN3 JP45

1.5.4 Other LEDs

There are several other LED’s on the M523xEVB to signal to the user various board/processor/component
states. Below is a list of those LEDs and their functions:

Table 1-24. LED Functions

LED Function

D1-D4 Ethernet Phy functionality

D5-D12 eTPU functionality

D14 +3.3V Power Good

D17 +5V Power Good

D23 Abort (IRQ7

D24 Reset (RSTI) asserted

D25-D32 User LEDs (See Table 1-23)

) asserted

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Chapter 2 Initialization and Setup

2.1 System Configuration

The M523xEVB board requires the following items for minimum system configuration:

• The M523xEVB board (provided).

• Power supply, +7V to 14V DC with minimum of 300 mA.

• RS232C compatible terminal or a PC with terminal emulation software.

• RS232 Communication cable (provided).

Figure 2-1 displays the minimum system configuration.

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RS-232 Terminal

Or PC

dBUG>

Figure 2-1. Minimum System Configuration

+7 to +14VDC

Input Power

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Installation and Setup

2.2 Installation and Setup

The following sections describe all the steps needed to prepare the board for operation. Please read the
following sections carefully before using the board. When you are preparing the board for the first time,
be sure to check that all jumpers are in the default locations. Default jumper markings are documented on
the master jumper table and printed on the underside of the board. After the board is functional in its
default mode, the Ethernet interface may be used by following the instructions provided in Appendix A.

2.2.1 Unpacking

Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the
following list and verify that all the items are present. You should have received:

•M523xEVB Single Board Computer

•M523xEVB User's Manual (this document)

• One RS232 communication cable

• One BDM (Background Debug Mode) “wiggler” cable

• MCF5235 ColdFire Integrated Microprocessor Reference Manual

• ColdFire® Programmers Reference Manual

• A selection of Third Party Developer Tools and Literature

NOTE

Avoid touching the MOS devices. Static discharge can and will damage
these devices.

Once you have verified that all the items are present, remove the board from its protective jacket and
anti-static bag. Check the board for any visible damage. Ensure that there are no broken, damaged, or
missing parts. If you have not received all the items listed above or they are damaged, please contact
Freescale Semiconductor immediately. For contact details, please see the front of this manual.

2.2.2 Preparing the Board for Use

The board, as shipped, is ready to be connected to a terminal and power supply without any need for
modification. Figure 2-5 shows the position of the jumpers and connectors.

2.2.3 Providing Power to the Board

The EVB requires an external supply voltage of 7–14 V DC, minimum 1 Amp. This is regulated on board
using three switching voltage regulators to provide the necessary EVB voltages of 5V, 3.3V and 1.5V.
There are two different power supply input connectors on the EVB. Connector P2 is a 2.1mm power jack
(Figure 2-2), P3 a lever actuated connector (Figure 2-3).

Figure 2-2. 2.1mm Power Connector

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Initialization and Setup

V+(7-14V)

GND

Figure 2-3. 2-Lever Power Connector

2.2.4 Power Switch (SW4)

Slide switch SW4 can be used to isolate the power supply input from the EVB voltage regulators if
required.

Moving the slide switch to the left (towards connector P3) will turn the EVB ON.

Moving the slide switch to the right (away from connector P3) will turn the EVB OFF.

2.2.5 Power Status LEDs and Fuse

When power is applied to the EVB, green power LEDs adjacent to the voltage regulators show the
presence of the supply voltage as follows:

Table 2-1. Power L E Ds

LED Function

D17 Indicates that the +5V regulator is working correctly

D14 Indicates that the +3.3V regulator is working correctly

If no LEDs are illuminated when the power is applied to the EVB, it is possible that either power switch
SW4 is in the “OFF” position or that the fuse F1 has blown. This can occur if power is applied to the EVB
in reverse-bias where a protection diode ensures that the fuse blows rather than causing damage to the
EVB. Replace F1 with a 20mm 1A fast blow fuse.

2.2.6 Selecting Terminal Baud Rate

The serial channel UART0 of the MCF5235 is used for serial communication and has a built in timer. This
timer is used by the dBUG ROM monitor to generate the baud rate used to communicate with a serial
terminal. A number of baud rates can be programmed. On power-up or manual RESET, the dBUG ROM
monitor firmware configures the channel for 19200 baud. Once the dBUG ROM monitor is running, a SET
command may be issued to select any baud rate supported by the ROM monitor.

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Installation and Setup

2.2.7 The Terminal Character Format

The character format of the communication channel is fixed at power-up or RESET. The default character
format is 8 bits per character, no parity and one stop bit with no flow control. It is necessary to ensure that
the terminal or PC is set to this format.

2.2.8 Connecting the Terminal

The board is now ready to be connected to a PC/terminal. Use the RS-232 serial cable to connect the
PC/terminal to the M523xEVB PCB. The cable has a 9-pin female D-sub terminal connector at one end
and a 9-pin male D-sub connector at the other end. Connect the 9-pin male connector to connector P4 on
the M523xEVB board. Connect the 9-pin female connector to one of the available serial communication
channels normally referred to as COM1 (COM2, etc.) on the PC running terminal emulation software. The
connector on the PC/terminal may be either male 25-pin or 9-pin. It may be necessary to obtain a
25pin-to-9pin adapter to make this connection. If an adapter is required, refer to Figure 2-4.

2.2.9 Using a Personal Computer as a Terminal

A personal computer may be used as a terminal provided a terminal emulation software package is
available. Examples of this software are PROCOMM, KERMIT, QMODEM, Windows 95/98/2000/XP
Hyper Terminal or similar packages. The board should then be connected as described in Section 2.2.8,
“Connecting the Terminal.”

Once the connection to the PC is made, power may be applied to the PC and the terminal emulation
software can be run. In terminal mode, it is necessary to select the baud rate and character format for the
channel. Most terminal emulation software packages provide a command known as "Alt-p" (press the p
key while pressing the Alt key) to choose the baud rate and character format. The character format should
be 8 bits, no parity, one stop bit. (see 2.2.7, “The Terminal Character Format”) The baud rate should be set
to 19200. Power can now be applied to the board.

5

Figure 2-4. Pin Assignment for Female (Terminal) Connector

1

69

Pin assignments are as follows:

Table 2-2. Pin Assignment for Female (Terminal) Connector

DB9 Pin Function

1 Data Carrier Detect, Output (shorted to pins 4 and 6)

2 Receive Data, Output from board (receive refers to terminal side)

3 Transmit Data, Input to board (transmit refers to terminal side)

4 Data Terminal Ready, Input (shorted to pin 1 and 6)

5 Signal Ground

6 Data Set Ready, Output (shorted to pins 1 and 4)

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Table 2-2. Pin Assignment for Female (Terminal) Connector

DB9 Pin Function

7 Request to Send, Input

8 Clear to send, Output

9 Not connected

Figure 2-5 on the next page shows the jumper locations for the board.

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Figure 2-5. Jumper Locations

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2.3 System Power-up and Initial Operation

When all of the cables are connected to the board, power may be applied. The dBUG ROM Monitor
initializes the board and then displays a power-up message on the terminal, which includes the amount of
memory present on the board.

Hard Reset
DRAM Size: 16M

Copyright 1995-2004 Motorola, Inc. All Rights Reserved.
ColdFire MCF523x EVS Firmware v2e.1a.xx (Build XXX on XXX XX 20XX
xx:xx:xx)

Enter 'help' for help.

dBUG>

The board is now ready for operation under the control of the debugger as described in Chapter 2. If you
do not get the above response, perform the following checks:

1. Make sure that the power supply is properly configured for polarity, voltage level and current
capability (~1A) and is connected to the board.

2. Check that the terminal and board are set for the same character format and baud.

3. Press the RESET button to insure that the board has been initialized properly.

If you still are not receiving the proper response, your board may have been damaged. Contact Freescale
Semiconductor for further instructions, please see the beginning of this manual for contact details.

2.4 Using The BDM Port

The MCF5235 microprocessor has a built in debug module referred to as BDM (background debug
module). In order to use BDM, simply connect the 26-pin debug connector on the board, J1, to the P&E
BDM wiggler cable provided in the kit. No special setting is needed. Refer to the ColdFire® Reference
Manual BDM Section for additional instructions.

NOTE

BDM functionality and use is supported via third party developer software
tools. Details may be found on the CD-ROM included in this kit.

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Chapter 3 Using the Monitor/Debug Firmware

The M523xEVB single board computer has a resident firmware package that provides a self-contained
programming and operating environment. The firmware, named dBUG, provides the user with a
monitor/debug interface, inline assembler and disassembly, program download, register and memory
manipulation, and I/O control functions. This chapter is a how-to-use description of the dBUG package,
including the user interface and command structure.

3.1 What Is dBUG?

dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitive command line
interface that can be used to download and execute code. It contains all the primary features needed in a
debugger to create a useful debugging environment.

The firmware provides a self-contained programming and operating environment. dBUG interacts with the
user through pre-defined commands that are entered via the terminal. These commands are defined in
Section 3.4, “Commands”.

The user interface to dBUG is the command line. A number of features have been implemented to achieve
an easy and intuitive command line interface.

dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to the debugger. For serial
communications, dBUG requires eight data bits, no parity, and one stop bit (8-N-1) with no flow control.
The default baud rate is 19200 but can be changed after power-up.

The command line prompt is “dBUG> ”. Any dBUG command may be entered from this prompt. dBUG
does not allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80
columns or less. dBUG echoes each character as it is typed, eliminating the need for any “local echo” on
the terminal side.

In general, dBUG is not case sensitive. Commands may be entered either in upper or lower case, depending
upon the user’s equipment and preference. Only symbol names require that the exact case be used.

Most commands can be recognized by using an abbreviated name. For instance, entering “h” is the same
as entering “help”. Thus, it is not necessary to type the entire command name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes
this and allows for repeated execution of these commands with minimal typing. After a command is
entered, simply press <RETURN> or <ENTER> to invoke the command again. The command is executed
as if no command line parameters were provided.

An additional function called the "System Call" allows the user program to utilize various routines within
dBUG. The System Call is discussed at the end of this chapter.

The operational mode of dBUG is demonstrated in Figure 3-1. After the system initialization, the board
waits for a command-line input from the user terminal. When a proper command is entered, the operation
continues in one of the two basic modes. If the command causes execution of the user program, the dBUG
firmware may or may not be re-entered, at the discretion of the user’s program. For the alternate case, the
command will be executed under control of the dBUG firmware, and after command completion, the
system returns to command entry mode.

During command execution, additional user input may be required depending on the command function.

For commands that accept an optional <width> to modify the memory access size, the valid values are:

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• B 8-bit (byte) access

• W 16-bit (word) access

• L 32-bit (long) access

When no <width> option is provided, the default width is.W, 16-bit.

The core ColdFire® register set is maintained by dBUG. These are listed below:

•A0-A7

•D0-D7

•PC

•SR

All control registers on ColdFire® are not readable by the supervisor-programming model, and thus not
accessible via dBUG. User code may change these registers, but caution must be exercised as changes may
render dBUG inoperable.

A reference to “SP” (stack pointer) actually refers to general purpose address register seven, “A7.”

3.2 Operational Procedure

System power-up and initial operation are described in detail in Chapter 2. This information is repeated
here for convenience and to prevent possible damage.

3.2.1 System Power-up

• Be sure the power supply is connected properly prior to power-up.

• Make sure the terminal is connected to TERMINAL (P4) connector.

• Turn power on to the board.

Figure 3-1 shows the dBUG operational mode.

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INITIALIZE

Operational Procedure

COMMAND LINE

INPUT FROM TERMINAL

EXECUTE
COMMAND
FUNCTION

YES

NO

DOES COMMAND LINE

CAUSE USER PROGRAM

EXECUTION

BEGIN EXECUTION

Figure 3-1. Flow Diagram of dBUG Operational Mode

NO

YES

JUMP TO USER
PROGRAM AND

3.2.2 System Initialization

After the EVB is powered-up and initialized, the terminal will display:

Hard Reset

DRAM Size: 16M

ColdFire MCF5235 on the M523xEVB

Firmware vXX.XX.XX (Build X on XXXX)

Copyright 1995-2004 Motorola, Inc. All Rights Reserved.

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Using the Monitor/Debug Firmware

Enter 'help' for help.

dBUG>

Other means can be used to re-initialize the M523xEVB firmware. These means are discussed in the
following paragraphs.

3.2.2.1 External RESET Button

External RESET (SW6) is the red button. Depressing this button causes all processes to terminate, resets
the MCF5235 processor and board logic and restarts the dBUG firmware. Pressing the RESET button
would be the appropriate action if all else fails.

3.2.2.2 ABORT Button

ABORT (SW5) is the button located next to the RESET button. The abort function causes an interrupt of
the present processing (a level 7 interrupt on MCF5235) and gives control to the dBUG firmware. This
action differs from RESET in that no processor register or memory contents are changed, the processor
and peripherals are not reset, and dBUG is not restarted. Also, in response to depressing the ABORT
button, the contents of the MCF5235 core internal registers are displayed.

The abort function is most appropriate when software is being debugged. The user can interrupt the
processor without destroying the present state of the system. This is accomplished by forcing a
non-maskable interrupt that will call a dBUG routine that will save the current state of the registers to
shadow registers in the monitor for display to the user. The user will be returned to the ROM monitor
prompt after exception handling.

3.2.2.3 Software Reset Command

dBUG does have a command that causes the dBUG to restart as if a hardware reset was invoked. The
command is “RESET”.

3.3 Command Line Usage

The user interface to dBUG is the command line. A number of features have been implemented to achieve
an easy and intuitive command line interface.

dBUG assumes that an 80x24 ASCII character dumb terminal is used to connect to the debugger. For serial
communications, dBUG requires eight data bits, no parity, and one stop bit (8-N-1). The baud rate default
is 19200 bps — a speed commonly available from workstations, personal computers and dedicated
terminals.

The command line prompt is: dBUG>

Any dBUG command may be entered from this prompt. dBUG does not allow command lines to exceed
80 characters. Wherever possible, dBUG displays data in 80 columns or less. dBUG echoes each character
as it is typed, eliminating the need for any local echo on the terminal side.

The <Backspace> and <Delete> keys are recognized as rub-out keys for correcting typographical
mistakes.

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Commands

Command lines may be recalled using the <Control> U, <Control> D and <Control> R key sequences.
<Control> U and <Control> D cycle up and down through previous command lines. <Control> R recalls
and executes the last command line.

In general, dBUG is not case-sensitive. Commands may be entered either in uppercase or lowercase,
depending upon the user’s equipment and preference. Only symbol names require that the exact case be
used.

Most commands can be recognized by using an abbreviated name. For instance, entering h is the same as
entering help. Thus it is not necessary to type the entire command name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes
this and allows for repeated execution of these commands with minimal typing. After a command is
entered, press the <Return> or <Enter> key to invoke the command again. The command is executed as if
no command line parameters were provided.

3.4 Commands

This section lists the commands that are available with all versions of dBUG. Some board or CPU
combinations may use additional commands not listed below.

Table 3-1. dBUG Command Summary

Mnemonic Syntax Description

ASM asm <<addr> stmt> Assemble

BC bc addr1 addr2 length Block Compare

BF bf <width> begin end data <inc> Block Fill

BM bm begin end dest Block Move

BR br addr <-r> <-c count> <-t trigger> Breakpoint

BS bs <width> begin end data Block Search

DC dc value Data Convert

DI di<addr> Disassemble

DL dl <offset> Download Serial

DLDBUG dldbug Download dBUG

DN dn <-c> <-e> <-i> <-s <-o offset>> <filename> Download Network

FL fl erase addr bytes

fl write dest src bytes

GO go <addr> Execute

GT gt addr Execute To

HELP help <command> Help

IRD ird <module.register> Internal Register Display

Flash Utilities

IRM irm module.register data Internal Register Modify

LR lr<width> addr Loop Read

LW lw<width> addr data Loop Write

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Mnemonic Syntax Description

ASM asm <<addr> stmt> Assemble

BC bc addr1 addr2 length Block Compare

BF bf <width> begin end data <inc> Block Fill

MD md<width> <begin> <end> Memory Display

MM mm<width> addr <data> Memory Modify

MMAP mmap Memory Map Display

RD rd <reg> Register Display

RM rm reg data Register Modify

RESET reset Reset

SD sd Stack Dump

SET set <option value> Set Configurations

SHOW show <option> Show Configurations

STEP step Step (Over)

Table 3-1. dBUG Command Summary (continued)

SYMBOL symbol <symb> <-a symb value> <-r symb> -C|l|s> Symbol Management

TRACE trace <num> Trace (Into)

UP up begin end filename Upload Memory to File

VERSION version Show Version

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Commands

ASM Assembler

Usage: ASM <<addr> stmt>

The ASM command is a primitive assembler. The <stmt> is assembled and the resulting code placed at
<addr>. This command has an interactive and non-interactive mode of operation.

The value for address <addr> may be an absolute address specified as a hexadecimal value, or a symbol
name. The value for stmt must be valid assembler mnemonics for the CPU.

For the interactive mode, the user enters the command and the optional <addr>. If the address is not
specified, then the last address is used. The memory contents at the address are disassembled, and the user
prompted for the new assembly. If valid, the new assembly is placed into memory, and the address
incremented accordingly. If the assembly is not valid, then memory is not modified, and an error message
produced. In either case, memory is disassembled and the process repeats.

The user may press the <Enter> or <Return> key to accept the current memory contents and skip to the
next instruction, or a enter period to quit the interactive mode.

In the non-interactive mode, the user specifies the address and the assembly statement on the command
line. The statement is then assembled, and if valid, placed into memory, otherwise an error message is
produced.

Examples:

To place a NOP instruction at address 0x00010000, the command is:

asm 10000 nop

To interactively assemble memory at address 0x00400000, the command is:

asm 400000

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Using the Monitor/Debug Firmware

BC Block Compare

Usage:BC addr1 addr2 length

The BC command compares two contiguous blocks of memory on a byte by byte basis. The first block
starts at address addr1 and the second starts at address addr2, both of length bytes.

If the blocks are not identical, the address of the first mismatch is displayed. The value for addresses addr1
and addr2 may be an absolute address specified as a hexadecimal value or a symbol name. The value for
length may be a symbol name or a number converted according to the user defined radix (hexadecimal by
default).

Example:

To verify that the data starting at 0x20000 and ending at 0x30000 is identical to the data starting at
0x80000, the command is:

bc 20000 80000 10000

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Commands

BF Block Fill

Usage:BF<width> begin end data <inc>

The BF command fills a contiguous block of memory starting at address begin, stopping at address end,
with the value data. <Width> modifies the size of the data that is written. If no <width> is specified, the
default of word sized data is used.

The value for addresses begin and end may be an absolute address specified as a hexadecimal value, or a
symbol name. The value for data may be a symbol name, or a number converted according to the
user-defined radix, normally hexadecimal.

The optional value <inc> can be used to increment (or decrement) the data value during the fill.

This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.

Examples:

To fill a memory block starting at 0x00020000 and ending at 0x00040000 with the value 0x1234, the
command is:

bf 20000 40000 1234

To fill a block of memory starting at 0x00020000 and ending at 0x0004000 with a byte value of 0xAB, the
command is:

bf.b 20000 40000 AB

To zero out the BSS section of the target code (defined by the symbols bss_start and bss_end), the
command is:

bf bss_start bss_end 0

To fill a block of memory starting at 0x00020000 and ending at 0x00040000 with data that increments by
2 for each <width>, the command is:

bf 20000 40000 0 2

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Using the Monitor/Debug Firmware

BM Block Move

Usage:BM begin end dest

The BM command moves a contiguous block of memory starting at address begin and stopping at address
end to the new address dest. The BM command copies memory as a series of bytes, and does not alter the
original block.

The values for addresses begin, end, and dest may be absolute addresses specified as hexadecimal values,
or symbol names. If the destination address overlaps the block defined by begin and end, an error message
is produced and the command exits.

Examples:

To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to the location 0x00200000,
the command is:

bm 40000 80000 200000

To copy the target code’s data section (defined by the symbols data_start and data_end) to 0x00200000,
the command is:

bm data_start data_end 200000

NOTE

Refer to “upuser” command for copying code/data into Flash memory.

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Commands

BR Breakpoints

Usage:BR addr <-r> <-c count> <-t trigger>

The BR command inserts or removes breakpoints at address addr. The value for addr may be an absolute
address specified as a hexadecimal value, or a symbol name. Count and trigger are numbers converted
according to the user-defined radix, normally hexadecimal.

If no argument is provided to the BR command, a listing of all defined breakpoints is displayed.

The -r option to the BR command removes a breakpoint defined at address addr. If no address is specified
in conjunction with the -r option, then all breakpoints are removed.

Each time a breakpoint is encountered during the execution of target code, its count value is incremented
by one. By default, the initial count value for a breakpoint is zero, but the -c option allows setting the initial
count for the breakpoint.

Each time a breakpoint is encountered during the execution of target code, the count value is compared
against the trigger value. If the count value is equal to or greater than the trigger value, a breakpoint is
encountered and control returned to dBUG. By default, the initial trigger value for a breakpoint is one, but
the -t option allows setting the initial trigger for the breakpoint.

If no address is specified in conjunction with the -c or -t options, then all breakpoints are initialized to the
values specified by the -c or -t option.

Examples:

To set a breakpoint at the C function main() (symbol _main; see “symbol” command), the command is:

br _main

When the target code is executed and the processor reaches main(), control will be returned to dBUG.

To set a breakpoint at the C function bench() and set its trigger value to 3, the command is:

br _bench -t 3

When the target code is executed, the processor must attempt to execute the function bench() a third time
before returning control back to dBUG.

To remove all breakpoints, the command is:

br -r

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BS Block Search

Usage:BS<width> begin end data

The BS command searches a contiguous block of memory starting at address begin, stopping at address
end, for the value data. <Width> modifies the size of the data that is compared during the search. If no
<width> is specified, the default of word sized data is used.

The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or
symbol names. The value for data may be a symbol name or a number converted according to the
user-defined radix, normally hexadecimal.

This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.

Examples:

To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 and ending at
0x00080000:

bs 40000 80000 1234

This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value 0x1234. If no
match is found, then the address is incremented to 0x00040002 and the next 16-bit value is read and
compared.

To search for the 32-bit value 0xABCD in the memory block starting at 0x00040000 and ending at
0x00080000:

bs.l 40000 80000 ABCD

This reads the 32-bit word located at 0x00040000 and compares it against the 32-bit value 0x0000ABCD.
If no match is found, then the address is incremented to 0x00040004 and the next 32-bit value is read and
compared.

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Commands

DC Data Conversion

Usage:DC data

The DC command displays the hexadecimal or decimal value data in hexadecimal, binary, and decimal
notation.

The value for data may be a symbol name or an absolute value. If an absolute value passed into the DC
command is prefixed by ‘0x’, then data is interpreted as a hexadecimal value. Otherwise data is interpreted
as a decimal value.

All values are treated as 32-bit quantities.

Examples:

To display the decimal and binary equivalent of 0x1234, the command is:

dc 0x1234

To display the hexadecimal and binary equivalent of 1234, the command is:

dc 1234

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Using the Monitor/Debug Firmware

DI Disassemble

Usage:DI <addr>

The DI command disassembles target code pointed to by addr. The value for addr may be an absolute
address specified as a hexadecimal value, or a symbol name.

Wherever possible, the disassembler will use information from the symbol table to produce a more
meaningful disassembly. This is especially useful for branch target addresses and subroutine calls.

The DI command attempts to track the address of the last disassembled opcode. If no address is provided
to the DI command, then the DI command uses the address of the last opcode that was disassembled.

The DI command is repeatable.

Examples:

To disassemble code that starts at 0x00040000, the command is:

di 40000

To disassemble code of the C function main(), the command is:

di _main

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Commands

DL Download Console

Usage:DL <offset>

The DL command performs an S-record download of data obtained from the console, typically a serial
port. The value for offset is converted according to the user-defined radix, normally hexadecimal. Please
reference the ColdFire Microprocessor Family Programmer’s Reference Manual for details on the
S-Record format.

If offset is provided, then the destination address of each S-record is adjusted by offset.

The DL command checks the destination download address for validity. If the destination is an address
outside the defined user space, then an error message is displayed and downloading aborted.

If the S-record file contains the entry point address, then the program counter is set to reflect this address.

Examples:

To download an S-record file through the serial port, the command is:

dl

To download an S-record file through the serial port, and add an offset to the destination address of 0x40,
the command is:

dl 0x40

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Using the Monitor/Debug Firmware

DLDBUG Download dBUG

Usage:DL <offset>

The DLDBUG command is used to update the dBUG image in Flash. It erases the Flash sectors containing
the dBUG image, downloads a new dBUG image in S-record format obtained from the console, and
programs the new dBUG image into Flash.

When the DLDBUG command is issued, dBUG will prompt the user for verification before any actions
are taken. If the command is affirmed, the Flash is erased and the user is prompted to begin sending the
new dBUG S-record file. The file should be sent as a text file with no special transfer protocol.

Use this command with extreme caution, as any error can render dBUG useless!

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Commands

DN Download Network

Usage:DN <-c> <-e> <-i> <-s> <-o offset> <filename>

The DN command downloads code from the network. The DN command handle files which are either
S-record, COFF, ELF or Image formats. The DN command uses Trivial File Transfer Protocol (TFTP) to
transfer files from a network host.

In general, the type of file to be downloaded and the name of the file must be specified to the DN
command. The -c option indicates a COFF download, the -e option indicates an ELF download, the -i
option indicates an Image download, and the -s indicates an S-record download. The -o option works only
in conjunction with the -s option to indicate an optional offset for S-record download. The filename is
passed directly to the TFTP server and therefore must be a valid filename on the server.

If neither of the -c, -e, -i, -s or filename options are specified, then a default filename and filetype will be
used. Default filename and filetype parameters are manipulated using the SET and SHOW commands.

The DN command checks the destination download address for validity. If the destination is an address
outside the defined user space, then an error message is displayed and downloading aborted.

For ELF and COFF files which contain symbolic debug information, the symbol tables are extracted from
the file during download and used by dBUG. Only global symbols are kept in dBUG. The dBUG symbol
table is not cleared prior to downloading, so it is the user’s responsibility to clear the symbol table as
necessary prior to downloading.

If an entry point address is specified in the S-record, COFF or ELF file, the program counter is set
accordingly.

Examples:

To download an S-record file with the name “srec.out”, the command is:

dn -s srec.out

To download a COFF file with the name “coff.out”, the command is:

dn -c coff.out

To download a file using the default filetype with the name “bench.out”, the command is:

dn bench.out

To download a file using the default filename and filetype, the command is:

dn

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Using the Monitor/Debug Firmware

FL Flash Utilities

Info Usage: FL

Erase Usage: FL erase addr bytes

Write Usage: FL write dest src bytes

The FL command provides a set of flash utilities that will display information about the Flash devices on
the EVB, erase a specified range of Flash, or erase and program a specified range of Flash.

When issued with no parameters, the FL command will display usage information as well as device
specific information for the Flash devices available. This information includes size, address range,
protected range, access size, and sector boundaries.

When the erase command is given, the FL command will attempt to erase the number of bytes specified
on the command line beginning at addr. If this range doesn’t start and end on Flash sector boundaries, the
range will be adjusted automatically and the user will be prompted for verification before proceeding.

When the write command is given, the FL command will program the number of bytes specified from src
to dest. An erase of this region will first be attempted. As with the erase command, if the Flash range to be
programmed doesn’t start and end on Flash sector boundaries, the range will be adjusted and the user will
be prompted for verification before the erase is performed. The specified range is also checked to insure
that the entire destination range is valid within the same Flash device and that the src and dest are not
within the same device.

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Commands

GO Execute

Usage:GO <addr>

The GO command executes target code starting at address addr. The value for addr may be an absolute
address specified as a hexadecimal value, or a symbol name.

If no argument is provided, the GO command begins executing instructions at the current program counter.

When the GO command is executed, all user-defined breakpoints are inserted into the target code, and the
context is switched to the target program. Control is only regained when the target code encounters a
breakpoint, illegal instruction, trap #15 exception, or other exception which causes control to be handed
back to dBUG.

The GO command is repeatable.

Examples:

To execute code at the current program counter, the command is:

go

To execute code at the C function main(), the command is:

go _main

To execute code at the address 0x00040000, the command is:

go 40000

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Using the Monitor/Debug Firmware

GT Execute To

Usage:GT addr

The GT command inserts a temporary breakpoint at addr and then executes target code starting at the
current program counter. The value for addr may be an absolute address specified as a hexadecimal value,
or a symbol name.

When the GT command is executed, all breakpoints are inserted into the target code, and the context is
switched to the target program. Control is only regained when the target code encounters a breakpoint,
illegal instruction, or other exception which causes control to be handed back to dBUG.

Examples:

To execute code up to the C function bench(), the command is:

gt _bench

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Commands

IRD Internal Register Display

Usage:IRD <module.register>

This command displays the internal registers of different modules inside the MCF5235. In the command
line, module refers to the module name where the register is located and register refers to the specific
register to display.

The registers are organized according to the module to which they belong. Use the IRD command without
any parameters to get a list of all the valid modules. Refer to the MCF5235 user’s manual for more
information on these modules and the registers they contain.

Example:

ird sim.rsr

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Using the Monitor/Debug Firmware

IRM Internal Register Modify

Usage:IRM module.register data

This command modifies the contents of the internal registers of different modules inside the MCF5235. In
the command line, module refers to the module name where the register is located and register refers to
the specific register to modify. The data parameter specifies the new value to be written into the register.

.

Example:

To modify the TMR register of the first Timer module to the value 0x0021, the command is:

irm timer1.tmr 0021

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Commands

HELP Help

Usage:HELP <command>

The HELP command displays a brief syntax of the commands available within dBUG. In addition, the
address of where user code may start is given. If command is provided, then a brief listing of the syntax of
the specified command is displayed.

Examples:

To obtain a listing of all the commands available within dBUG, the command is:

help

To obtain help on the breakpoint command, the command is:

help br

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Using the Monitor/Debug Firmware

LR Loop Read

Usage:LR<width> addr

The LR command continually reads the data at addr until a key is pressed. The optional <width> specifies
the size of the data to be read. If no <width> is specified, the command defaults to reading word sized data.

Example:

To continually read the longword data from address 0x20000, the command is:

lr.l 20000

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Commands

LW Loop Write

Usage:LW<width> addr data

The LW command continually writes data to addr. The optional width specifies the size of the access to
memory. The default access size is a word.

Examples:

To continually write the longword data 0x12345678 to address 0x20000, the command is:

lw.l 20000 12345678

Note that the following command writes 0x78 into memory:

lw.b 20000 12345678

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Using the Monitor/Debug Firmware

MD Memory Display

Usage:MD<width> <begin> <end>

The MD command displays a contiguous block of memory starting at address begin and stopping at
address end. The values for addresses begin and end may be absolute addresses specified as hexadecimal
values, or symbol names. Width modifies the size of the data that is displayed. If no <width> is specified,
the default of word sized data is used.

Memory display starts at the address begin. If no beginning address is provided, the MD command uses
the last address that was displayed. If no ending address is provided, then MD will display memory up to
an address that is 128 beyond the starting address.

This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.

Examples:

To display memory at address 0x00400000, the command is:

md 400000

To display memory in the data section (defined by the symbols data_start and data_end), the command is:

md data_start

To display a range of bytes from 0x00040000 to 0x00050000, the command is:

md.b 40000 50000

To display a range of 32-bit values starting at 0x00040000 and ending at 0x00050000:

md.l 40000 50000

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Commands

MM Memory Modify

Usage:MM<width> addr <data>

The MM command modifies memory at the address addr. The value for addr may be an absolute address
specified as a hexadecimal value, or a symbol name. Width specifies the size of the data that is modified.
If no <width> is specified, the default of word sized data is used. The value for data may be a symbol name,
or a number converted according to the user-defined radix, normally hexadecimal.

If a value for data is provided, then the MM command immediately sets the contents of addr to data. If no
value for data is provided, then the MM command enters into a loop. The loop obtains a value for data,
sets the contents of the current address to data, increments the address according to the data size, and
repeats. The loop terminates when an invalid entry for the data value is entered, i.e., a period.

This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.

Examples:

To set the byte at location 0x00010000 to be 0xFF, the command is:

mm.b 10000 FF

To interactively modify memory beginning at 0x00010000, the command is:

mm 10000

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Using the Monitor/Debug Firmware

MMAP Memory Map Display

Usage:mmap

This command displays the memory map information for the M523xEVB evaluation board. The
information displayed includes the type of memory, the start and end address of the memory, and the port
size of the memory. The display also includes information on how the Chip-selects are used on the board
and which regions of memory are reserved for dBUG use (protected).

Here is an example of the output from this command:

Type Start End Port Size

---------------------------------------------------

SDRAM 0x00000000 0x00FFFFFF 32-bit

SRAM (Int) 0x20000000 0x2000FFFF 32-bit

ASRAM (Ext) 0x30000000 0x3007FFFF 32-bit

IPSBAR 0x40000000 0x7FFFFFFF 32-bit

Flash (Ext) 0xFFE00000 0xFFFFFFFF 16-bit

Protected Start End

----------------------------------------

dBUG Code 0xFFE00000 0xFFE3FFFF

dBUG Data 0x00000000 0x0000FFFF

Chip Selects

----------------

CS0 Ext Flash

CS1 Ext ASRAM

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Commands

RD Register Display

Usage:RD <reg>

The RD command displays the register set of the target. If no argument for reg is provided, then all
registers are displayed. Otherwise, the value for reg is displayed.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RD command displays
register values from the register buffer.

Examples:

To display all the registers and their values, the command is:

rd

To display only the program counter:

rd pc

Here is an example of the output from this command:

PC: 00000000 SR: 2000 [t.Sm.000...xnzvc]

An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000

Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

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Using the Monitor/Debug Firmware

RM Register Modify

Usage:RM reg data

The RM command modifies the contents of the register reg to data. The value for reg is the name of the
register, and the value for data may be a symbol name, or it is converted according to the user-defined
radix, normally hexadecimal.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RM command updates
the copy of the register in the buffer. The actual value will not be written to the register until target code is
executed.

Examples:

To change register D0 to contain the value 0x1234, the command is:

rm D0 1234

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Commands

RESET Reset the Board and dBUG

Usage:RESET

The RESET command resets the board and dBUG to their initial power-on states.

The RESET command executes the same sequence of code that occurs at power-on. If the RESET
command fails to reset the board adequately, cycle the power or press the reset button.

Examples:

To reset the board and clear the dBUG data structures, the command is:

reset

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Using the Monitor/Debug Firmware

SD Stack Dump

Usage:SD

The SD command displays a back trace of stack frames. This command is useful after some user code has
executed that creates stack frames (i.e. nested function calls). After control is returned to dBUG, the SD
command will decode the stack frames and display a trace of the function calls.

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Commands

SET Set Configurations

Usage: SET <option value>

The SET command allows the setting of user-configurable options within dBUG. With no arguments, SET
displays the options and values available. The SHOW command displays the settings in the appropriate
format. The standard set of options is listed below.

baud - This is the baud rate for the first serial port on the board. All communications between dBUG and
the user occur using either 9600 or 19200 bps, eight data bits, no parity, and one stop bit, 8-N-1, with no
flow control.

base - This is the default radix for use in converting a number from its ASCII text representation to the
internal quantity used by dBUG. The default is hexadecimal (base 16), and other choices are binary (base

2), octal (base 8), and decimal (base 10).

client - This is the network Internet Protocol (IP) address of the board. For network communications, the
client IP is required to be set to a unique value, usually assigned by your local network administrator.

server - This is the network IP address of the machine which contains files accessible via TFTP. Your local
network administrator will have this information and can assist in properly configuring a TFTP server if
one does not exist.

gateway - This is the network IP address of the gateway for your local subnetwork. If the client IP address
and server IP address are not on the same subnetwork, then this option must be properly set. Your local
network administrator will have this information.

netmask - This is the network address mask to determine if use of a gateway is required. This field must
be properly set. Your local network administrator will have this information.

filename - This is the default filename to be used for network download if no name is provided to the DN
command.

filetype - This is the default filetype to be used for network download if no type is provided to the DN
command. Valid values are: “srecord”, “coff”, and “elf”.

mac - This is the ethernet Media Access Control (MAC) address (a.k.a hardware address) for the
evaluation board. This should be set to a unique value, and the most significant nibble should always be
even.

Examples: To set the baud rate of the board to be 19200, the command is:

set baud 19200

NOTE

See the SHOW command for a display containing the correct formatting of
these options.

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Using the Monitor/Debug Firmware

SHOW Show Configurations

Usage: SHOW <option>

The SHOW command displays the settings of the user-configurable options within dBUG. When no option
is provided, SHOW displays all options and values.

Examples:

To display all options and settings, the command is:

show

To display the current baud rate of the board, the command is:

show baud

Here is an example of the output from a show command:

dBUG> show

base: 16

baud: 19200

server: 0.0.0.0

client: 0.0.0.0

gateway: 0.0.0.0

netmask: 255.255.255.0

filename: test.s19

filetype: S-Record

ethaddr: 00:CF:52:82:CF:01

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Commands

STEP Step Over

Usage:STEP

The STEP command can be used to “step over” a subroutine call, rather than tracing every instruction in
the subroutine. The ST command sets a temporary breakpoint one instruction beyond the current program
counter and then executes the target code.

The STEP command can be used to “step over” BSR and JSR instructions.

The STEP command will work for other instructions as well, but note that if the STEP command is used
with an instruction that will not return, i.e. BRA, then the temporary breakpoint may never be encountered
and dBUG may never regain control.

Examples:

To pass over a subroutine call, the command is:

step

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Using the Monitor/Debug Firmware

SYMBOL Symbol Name Management

Usage:SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s>

The SYMBOL command adds or removes symbol names from the symbol table. If only a symbol name is
provided to the SYMBOL command, then the symbol table is searched for a match on the symbol name
and its information displayed.

The -a option adds a symbol name and its value into the symbol table. The -r option removes a symbol
name from the table.

The -c option clears the entire symbol table, the -l option lists the contents of the symbol table, and the -s
option displays usage information for the symbol table.

Symbol names contained in the symbol table are truncated to 31 characters. Any symbol table lookups,
either by the SYMBOL command or by the disassembler, will only use the first 31 characters. Symbol
names are case-sensitive.

Symbols can also be added to the symbol table via in-line assembly labels and ethernet downloads of ELF
formatted files.

Examples:

To define the symbol “main” to have the value 0x00040000, the command is:

symbol -a main 40000

To remove the symbol “junk” from the table, the command is:

symbol -r junk

To see how full the symbol table is, the command is:

symbol -s

To display the symbol table, the command is:

symbol -l

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Commands

TRACE Trace Into

Usage:TRACE <num>

The TRACE command allows single-instruction execution. If num is provided, then num instructions are
executed before control is handed back to dBUG. The value for num is a decimal number.

The TRACE command sets bits in the processors’ supervisor registers to achieve single-instruction
execution, and the target code executed. Control returns to dBUG after a single-instruction execution of
the target code.

This command is repeatable.

Examples:

To trace one instruction at the program counter, the command is:

tr

To trace 20 instructions from the program counter, the command is:

tr 20

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Using the Monitor/Debug Firmware

UP Upload Data

Usage:UP begin end filename

The UP command uploads the data from a memory region (specified by begin and end) to a file (specified
by filename) over the network. The file created contains the raw binary data from the specified memory
region. The UP command uses the Trivial File Transfer Protocol (TFTP) to transfer files to a network host.

Example:

To upload a portion of SDRAM to a file “sdram.bin”, the command is:

up 40000 50000 sdram.bin

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TRAP #15 Functions

VERSION Display dBUG Version

Usage:VERSION

The VERSION command displays the version information for dBUG. The dBUG version, build number
and build date are all given.

The version number is separated by a decimal, for example, “v 2b.1c.1a”.

In this example, v 2b . 1c . 1a

dBUG common
major and minor
revision

CPU major

and minor

revision

{

{

{

board major
and minor
revision

The version date is the day and time at which the entire dBUG monitor was compiled and built.

Examples:

To display the version of the dBUG monitor, the command is:

version

3.5 TRAP #15 Functions

An additional utility within the dBUG firmware is a function called the TRAP 15 handler. This function
can be called by the user program to utilize various routines within the dBUG, to perform a special task,
and to return control to the dBUG. This section describes the TRAP 15 handler and how it is used.

There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR, CHAR_PRESENT, and
EXIT_TO_dBUG.

3.5.1 OUT_CHAR

This function ( function code 0x0013) sends a character, which is in the lower 8 bits of D1, to the terminal.

Assembly example:

/* assume d1 contains the character */

move.l #$0013,d0 Selects the function

TRAP #15 The character in d1 is sent to terminal

C example:

void board_out_char (int ch)

{

/* If your C compiler produces a LINK/UNLK pair for this routine,

* then use the following code which takes this into account

*/

#if l

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Using the Monitor/Debug Firmware

/* LINK a6,#0 -- produced by C compiler */

asm (“ move.l8(a6),d1”); /* put ‘ch’into d1 */

asm (“ move.l#0x0013,d0”); /* select the function */

asm (“ trap#15”); /* make the call */

/* UNLK a6 -- produced by C compiler */

#else

/* If C compiler does not produce a LINK/UNLK pair, the use

* the following code.

*/

asm (“ move.l4(sp),d1”); /* put ‘ch’into d1 */

asm (“ move.l#0x0013,d0”); /* select the function */

asm (“ trap#15”); /* make the call */

#endif

}

3.5.2 IN_CHAR

This function (function code 0x0010) returns an input character (from terminal) to the caller. The returned
character is in D1.

Assembly example:

move.l #$0010,d0 Select the function

trap #15 Make the call, the input character is in d1.

C example:

int board_in_char (void)

{

asm (“ move.l#0x0010,d0”); /* select the function */

asm (“ trap#15”); /* make the call */

asm (“ move.ld1,d0”); /* put the character in d0 */

}

3.5.3 CHAR_PRESENT

This function (function code 0x0014) checks if an input character is present to receive. A value of zero is
returned in D0 when no character is present. A non-zero value in D0 means a character is present.

Assembly example:

move.l #$0014,d0 Select the function

trap #15 Make the call, d0 contains the response (yes/no).

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TRAP #15 Functions

C example:

int board_char_present (void)

{

asm (“ move.l#0x0014,d0”); /* select the function */

asm (“ trap#15”); /* make the call */

}

3.5.4 EXIT_TO_dBUG

This function (function code 0x0000) transfers the control back to the dBUG, by terminating the user code.
The register context are preserved.

Assembly example:

move.l #$0000,d0 Select the function

trap #15 Make the call, exit to dBUG.

C example:

void board_exit_to_dbug (void)

{

asm (“ move.l#0x0000,d0”); /* select the function */

asm (“ trap#15”); /* exit and transfer to dBUG */

}

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Appendix A Configuring dBUG for Network Downloads

The dBUG module has the ability to perform downloads over an Ethernet network using the Trivial File
Transfer Protocol, TFTP (NOTE: this requires a TFTP server to be running on the host attached to the
board). Prior to using this feature, several parameters are required for network downloads to occur. The
information that is required and the steps for configuring dBUG are described below.

A.1 Required Network Parameters

For performing network downloads, dBUG needs 6 parameters; 4 are network-related, and 2 are
download-related. The parameters are listed below, with the dBUG designation following in parenthesis.

All computers connected to an Ethernet network running the IP protocol need 3 network-specific
parameters. These parameters are:

• Internet Protocol, IP, address for the computer (client IP),

• IP address of the Gateway for non-local traffic (gateway IP), and

• Network netmask for flagging traffic as local or non-local (netmask).

In addition, the dBUG network download command requires the following three parameters:

• IP address of the TFTP server (server IP),

• Name of the file to download (filename),

• Type of the file to download (filetype of S-record, COFF, ELF, or Image).

Your local system administrator can assign a unique IP address for the board, and also provide you the IP
addresses of the gateway, netmask, and TFTP server. Fill out the lines below with this information.

Client IP:___.___.___.___(IP address of the board)
Server IP:___.___.___.___(IP address of the TFTP server)
Gateway:___.___.___.___(IP address of the gateway)
Netmask:___.___.___.___(Network netmask)

A.2 Configuring dBUG Network Parameters

Once the network parameters have been obtained, the dBUG Rom Monitor must be configured. The
following commands are used to configure the network parameters.

set client <client IP>
set server <server IP>
set gateway <gateway IP>
set netmask <netmask>
set mac <addr>

For example, the TFTP server is named ‘santafe’ and has IP address 123.45.67.1. The board is assigned
the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250, and the netmask is

255.255.255.0. The MAC address is chosen arbitrarily and is unique. The commands to dBUG are:

set client 123.45.68.15
set server 123.45.67.1
set gateway 123.45.68.250
set netmask 255.255.255.0
set mac 00:CF:52:82:EB:01

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor A-1

Configuring dBUG for Network Downloads

The last step is to inform dBUG of the name and type of the file to download. Prior to giving the name of
the file, keep in mind the following.

Most, if not all, TFTP servers will only permit access to files starting at a particular sub-directory. (This
is a security feature which prevents reading of arbitrary files by unknown persons.) For example, SunOS
uses the directory /tftp_boot as the default TFTP directory. When specifying a filename to a SunOS TFTP
server, all filenames are relative to /tftp_boot. As a result, you normally will be required to copy the file
to download into the directory used by the TFTP server.

A default filename for network downloads is maintained by dBUG. To change the default filename, use
the command:

set filename <filename>

When using the Ethernet network for download, either S-record, COFF, ELF, or Image files may be
downloaded. A default filetype for network downloads is maintained by dBUG as well. To change the
default filetype, use the command:

set filetype <srecord|coff|elf|image>

Continuing with the above example, the compiler produces an executable COFF file, ‘a.out’. This file is
copied to the /tftp_boot directory on the server with the command:

rcp a.out santafe:/tftp_boot/a.out

Change the default filename and filetype with the commands:

set filename a.out
set filetype coff

Finally, perform the network download with the ‘dn’ command. The network download process uses the
configured IP addresses and the default filename and filetype for initiating a TFTP download from the
TFTP server.

A.3 Troubleshooting Network Problems

Most problems related to network downloads are a direct result of improper configuration. Verify that all
IP addresses configured into dBUG are correct. This is accomplished via the ‘show ’command.

Using an IP address already assigned to another machine will cause dBUG network download to fail, and
probably other severe network problems. Make certain the client IP address is unique for the board.

Check for proper insertion or connection of the network cable. Is the status LED lit indicating that network
traffic is present?

Check for proper configuration and operation of the TFTP server. Most Unix workstations can execute a
command named ‘tftp’ which can be used to connect to the TFTP server as well. Is the default TFTP root
directory present and readable?

If ‘ICMP_DESTINATION_UNREACHABLE’ or similar ICMP message appears, then a serious error has
occurred. Reset the board, and wait one minute for the TFTP server to time out and terminate any open
connections. Verify that the IP addresses for the server and gateway are correct. Also verify that a TFTP
server is running on the server.

M523xEVB User’s Manual, Rev. 1.2

A-2 Freescale Semiconductor

Appendix B Schematics

M532xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor B-1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SHEET 12

SHEET 11

SHEET 9

HIERARCHICAL INTERCONNECTS

ASRAM MEMORY

ETHERNET INTERFACE

POWER SUPPLY UNIT

EXPANSION CONNECTORS

SHEET 8

M523X CPU

- All connectors are denoted Jx

Table Of Contents:

SERIAL I/O INTERFACE

SHEET 6

- All decoupling caps less than 0.1uF are COG SMD 0805 unless otherwise stated

Date

SHEET 13

FLASH MEMORY

Rev

SHEET 14

ETPU INTERFACE

Revision Information

SHEET 7

SHEET 5

SHEET 15

Designer

SHEET 2

CAN INTERFACE

Notes:

- All test points are denoted TPx

0.0SHEET 4 02 Feb 04

RESET CONFIGURATION AND CLOCKING CIRCUITRY

SHEET 10

ADDRESS AND DATA BUS BUFFERS

- All decoupling caps greater than 0.1uF are X7R SMD 0805 unless otherwise stated

L. Anderson Provisional release

M523X Evaluation Board

- All Switches are denoted SWx

- All jumpers are denoted JPx

CommentsSHEET 3

DEBUG

SDRAM MEMORY

SHEET 16

USB INTERFACE

Motorola SPS TSPG - TECD ColdFire Group

A 05 Mar 04 P. Highton Added Metrowerks schematic part number and revision letter.

B 30 Apr 04 L. Anderson Removed alternative footprint for 90-pin SSOP 32-bit Flash and

replaced with 16-bit Flash, corrected RJ45 pinout and added

18Kohm pull-down resistors to U11 (ethernet transceiver).

C 23 Jun 04 L. Anderson &

Pete Highton

Final update including silkscreen modifications of the reset

configuration tables. Correction of signals on the RJ-45 connector

and addition of pull-down resistors on the ethernet signals.

D 27 Jul 05 L. Anderson Updated USB page. Jumpers 59 to 62 renumbered.

SCH-20380 General Notes and Information

D

M523xEVB

B

116Tuesday, July 26, 2005

Title

Size Document Number Rev

Date: Sheet

of

of

216Tuesday, July 26, 2005

1

2

3

4

Sheet 3ASRAM

Sheet 5CAN

Sheet 7Debug

Sheet 8Ethernet

Sheet 4Buffers

Sheet 9eTPU

Sheet 11Flash Memory

B_A[23:0]

/BS[3:0]

B_D[31:0]

/CS[7:0]

/OE

R/W

CANH1
CANL1

CAN0RX

CAN0TX

CAN1RX

CAN1TX

BDM_/RSTIN

TMS/BKPT

DDATA[3:0]

PST[3:0]

/TA

TCLK/PSTCLK
TDI/DSI
TDO/DSO
TRST/DSCLK

EMDC
EMDIO

ECOL
ECRS
ERXDV
ERXER

ERXCLK

ERXD0

ERXD1

ERXD2

ERXD3

ETXEN

ETXER

ETXCLK

ETXD0

ETXD1

ETXD2

ETXD3

ETH_CLK

/IRQ[7:1]

/RSTOUT

B_A[23:0]

B_D[31:0]

R/W

/CS[7:0]

D[31:0]

A[23:0]

TCRCLK

UTPUODIS

LTPUODIS

TPUCH[15:0]
TPUCH[31:16]

QSPI_PCS0
QSPI_DOUT
QSPI_DIN
QSPI_SCK

TSIZ1
TSIZ0

/TEA
/TIP

R/W

/CS[7:0]
B_D[31:0]
B_A[23:0]

/OE

CPU

B_A[23:0]

A[23:0]

A[23:0]

B_D[31:0]

/BS[3:0]

/BS[3:0]

/CS[7:0]

/OE

/CS[7:0]

/OE

D[31:0]

D[31:0]

R/W

/IRQ[7:1]

R/W

/IRQ[7:1]

M523xEVB

Title

1

SCH-20380 Hierarchical Block Diagram D

C

Size Document Number Rev

Date: Sheet

Sheet 15Serial I/O

2

Sheet 13Reset Config & Clocks

3

Sheet 14SDRAM

4

Sheet16USB

TSIZ0

TSIZ1

/TS

/TIP

/TA

/TEA

LTPUODIS

UTPUODIS

TPUCH[15:0]

TPUCH[31:16]

/TEA

/TA

TSIZ1

/TIP

/TS

TSIZ0

TPUCH[15:0]

TPUCH[31:16]

UTPUODIS

LTPUODIS

TCRCLK

TCRCLK

EMDC

EMDC

EMDIO

EMDIO

ECOL

ECOL

ECRS

ECRS

ERXDV

ERXDV

ERXER

ERXER

ERXCLK

ERXCLK

ERXD0

ERXD0

ERXD1

ERXD1

ERXD2

ERXD2

ERXD3

ERXD3

ETXEN

ETXER

ETXCLK

ETXD0

ETXER

ETXCLK

ETXEN

TCLK/PSTCLK

PST[3:0]

DDATA[3:0]

ETXD2

ETXD1

ETXD3

ETXD0

PST[3:0]

ETXD1

ETXD3

ETXD2

DDATA[3:0]

TMS/BKPT

TDI/DSI

TDI/DSI

TCLK/PSTCLK

TMS/BKPT

TDO/DSO

TRST/DSCLK

TDO/DSO

TRST/DSCLK

DTIN0

DTIN0

DTOUT0

DTOUT0

DTIN1

DTIN1

DTOUT1

DTOUT1

DTIN2

DTOUT2

DTIN2

DTOUT2

DTIN3

DTOUT3

DTIN3

DTOUT3

CLKMOD[1:0]

JTAG_EN

/RCON

/RCON

JTAG_EN

CLKMOD[1:0]

CAN1RX

CAN1RX

CAN1TX

CAN1TX

CAN0RX

CAN0RX

CAN0TX

CAN0TX

/SD_WE

/SD_SCKE

/SD_WE

/SD_CS1

/SD_CS0

SD_SCKE

/SD_CS1

/SD_CS0

/SD_RAS

/SD_CAS

/SD_CAS

/SD_RAS

/U2RTS

/U2RTS

/U2CTS

U2TXD

/U2CTS

U2TXD

U2RXD

U2RXD

/U1RTS

/U1RTS

/U1CTS

/U1CTS

U1TXD

U1TXD

U1RXD

U1RXD

/U0RTS

/U0CTS

/U0RTS

/U0CTS

U0TXD

U0TXD

U0RXD

U0RXD

CLKOUT

EXTAL

CLKOUT

XTAL

EXTAL

XTAL

/RESET

/RESET

/RSTOUT

/RSTOUT

QSPI_SCK

QSPI_DOUT

QSPI_DIN

QSPI_SCK

QSPI_DOUT

QSPI_DIN

QSPI_PCS1

QSPI_PCS0

QSPI_PCS0

QSPI_PCS1

I2C_SDA

I2C_SCL

I2C_SCL

I2C_SDA

ETPU/ETH

ETPU/ETH

Sheet 6

Motorola SPS TSPG - TECD ColdFire Group

U0RXD
U0TXD

/U0CTS
/U0RTS

U1RXD
U1TXD

/U1CTS
/U1RTS

U2RXD
U2TXD

/U2CTS
/U2RTS

/IRQ[7:1]

/RSTOUT

QSPI_PCS1
QSPI_PCS0
QSPI_DOUT

QSPI_DIN

QSPI_SCK

CANH1

CANL1

I2C_SCL

I2C_SDA

ETPU/ETH

DTOUT3

DTIN3

DTOUT2

DTIN2

DTOUT1

DTIN1

DTOUT0

DTIN0

JTAG_EN

/RCON

CLKMOD[1:0]

/RSTOUT

XTAL

EXTAL

CLKOUT

TRST/DSCLK

TDO/DSO

TDI/DSI

TMS/BKPT

/RESET

/BDM_RSTIN

ETH_CLK

/IRQ[7:1]

D[31:0]

TSIZ1

/CS[7:0]

TSIZ0

/BS[3:0]

/TEA

/TA

/TIP

/TS

R/W

/OE

UTPUODIS

LTPUODIS

/EXT_RSTIN

A[23:0]

/BS[3:0]

D[31:0]

/SD_CAS
/SD_RAS
/SD_CS0

CLKOUT

SD_SCKE

/SD_WE

/CS[7:0]

/IRQ[7:1]

B_A[23:0]
B_D[31:0]

/OE

R/W

/RSTOUT

DTIN1

DTOUT1

DTIN2

DTOUT2

/TS

5

Sheet 12PSU

A[23:0]

/BS[3:0]

Expansion Connectors

D D

/OE

/CS[7:0]

D[31:0]

R/W

/IRQ[7:1]

/TA

/TIP

/TEA

TSIZ0

TSIZ1

LTPUODIS

UTPUODIS

TPUCH[15:0]

TPUCH[31:16]

TCRCLK

EMDC

EMDIO

PST[3:0]

TMS/BKPT

DDATA[3:0]

TDI/DSI

TDO/DSO

TRST/DSCLK

TCLK/PSTCLK

DTIN0

DTIN1

DTOUT0

DTIN2

DTOUT1

DTIN3

DTOUT2

DTOUT3

/RCON

JTAG_EN

CLKMOD[1:0]

CAN1TX

CAN1RX

CAN0TX

CAN0RX

/SD_WE

SD_SCKE

/SD_CS1

/SD_CS0

/SD_CAS

/SD_RAS

/U2CTS

/U2RTS

U2TXD

U2RXD

/U1RTS

/U1CTS

U1TXD

U1RXD

/U0CTS

/U0RTS

U0TXD

U0RXD

EXTAL

CLKOUT

XTAL

/RESET

/RSTOUT

/EXT_RSTIN

QSPI_DIN

QSPI_SCK

QSPI_DOUT

QSPI_PCS1

QSPI_PCS0

I2C_SDA

I2C_SCL

5

Sheet 10

C C

B B

A A

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ASRAM Upper 16-bit word

NOTE: /BS3 selects the most

significant byte lane access and

/BS0 the least significant.

ASRAM Lower 16-bit word

TSOP II

Do not populate

TSOP II

Do not populate

Each ASRAM is 256K x 16bit (512KB)

Total ASRAM available = 1MB

NOTE: Alternative ASRAM's with the same PCB footprint

and functionality are :- Renesas HM62W16255HCJP-12

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 Asynchronous SRAM

D

M523xEVB

B

316Tuesday, July 26, 2005

Title

Size Document Number Rev

Date: Sheet

of

B_A[23:0]

/BS2

B_D20

B_A[23:0]

/BS0/CS1

B_A[23:0]

/BS1

/BS3

/BS[3:0]

/CS1

B_D10

B_D18

B_D11

B_D24

B_D16

B_D13

B_D5

B_D0

B_D8

B_D19

B_D25

B_D17

B_D7

B_D12

B_D1

B_D28

B_D31

B_D23

B_D26

B_D[31:0]

B_D[31:0]

B_D15

B_D22

B_D29

B_D21

B_D27

B_D9

B_D2

B_D3

B_D6

B_D4

B_D14

B_D30

B_A5

B_A3

B_A18

B_A18

B_A9

B_A7

B_A4

B_A10

B_A11

B_A17

B_A2

B_A5

B_A19

B_A14

B_A19

B_A9

B_A15

B_A15

B_A12

B_A4

B_A2

B_A10

B_A7

B_A16

B_A3

B_A6

B_A13

B_A12B_A11

B_A16

B_A8

B_A13

B_A17

B_A6

B_A8

B_A14

/CS[7:0]

+3.3V +3.3V

+3.3V+3.3V

+3.3V

U2

CY7C1041CV3310ZC

123456789

10111213141516171819202122 23

242526272829303132333435363738394041424344

A0A1A2A3A4

/CE

I/00

I/01

I/02

I/03

VCC

VSS

I/04

I/05

I/06

I/07

/WEA5A6A7A8

A9 A10

A11

A12

A13

A14

NC

I/O8

I/O9

I/O10

I/O11

VCC

VSS

I/O12

I/O13

I/O14

I/O15

/BLE

/BHE

/OE

A15

A16

A17

C1

1nF

C2

1nF

C3

1nF

C4

1nF

U1

CY7C1041CV3310ZC

123456789

10111213141516171819202122 23

242526272829303132333435363738394041424344

A0A1A2A3A4

/CE

I/00

I/01

I/02

I/03

VCC

VSS

I/04

I/05

I/06

I/07

/WEA5A6A7A8

A9 A10

A11

A12

A13

A14

NC

I/O8

I/O9

I/O10

I/O11

VCC

VSS

I/O12

I/O13

I/O14

I/O15

/BLE

/BHE

/OE

A15

A16

A17

C7

0.1uF

C6

0.1uF

C5

0.1uF

C8

0.1uF

B_A[23:0]

/BS[3:0]

/OE

B_D[31:0]

/CS[7:0]

R/W

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ADDRESS BUS BUFFERS

Address and Data Bus buffers/transceivers used to buffer

the signals for the ASRAM and Flash memories and the

USB controller.

DATA BUS TRANSCEIVERS

AND Gate

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 Buffers D

M523xEVB

B

416Tuesday, July 26, 2005

Title

Size Document Number Rev

Date: Sheet

of

B_A18

B_A15

B_D17

D7

A0

B_D8

D18

D28

D[31:0]

B_A17

A18

B_D16

A11

A7

B_D30

D10

D23

B_D21

B_D10

D30

B_D1

D2

B_A19

B_A4

B_D18

D20

B_D[31:0]

A1

D8

B_D9

D16

A19

B_D13

B_D2

D6

B_D26

A12

A8

D17

B_D31

B_D11

B_D22

B_A20

B_A5

B_D19

A2

B_D27

B_D3

A13

A9

D11

B_D12

D0

B_A21

B_A6

A20

A3

B_A10

A15

D9

B_D28

A14

B_A22

B_A7

B_D0

B_D23

D19

D22

D21

D24A4D25

B_A0

B_A11

B_D4

B_A16

B_A8

D5

A[23:0]

B_D24

D3

A21

D26

B_A12

B_A1

B_D5

D14

B_A[23:0]

B_A9

D12

B_D25

B_A2

B_A13

B_D6

D13

D15

A22

A16

B_D14

A5

B_A14

B_A3

D4

B_D7

D1

D27

A17

B_D15

A10

A6

B_D29

B_D20

D31

D29

B_A23

A23

/CS2

/CS0

/CS1

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

U3

MC74LCX16245DT

23568

9

111213141617192022

2314825244101521

283439

45

4746444341403837363533323029272671831

42

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1DIR

1OE

2OE

2DIR

GND

GND

GND

GND

GND

GND

GND

GND

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

VCC

VCC

VCC

VCC

U6

MC74LCX16245DT

23568

9

111213141617192022

2314825244101521

283439

45

4746444341403837363533323029272671831

42

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1DIR

1OE

2OE

2DIR

GND

GND

GND

GND

GND

GND

GND

GND

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

VCC

VCC

VCC

VCC

U4

MC74LCX16245DT

23568

9

111213141617192022

2314825244101521

283439

45

4746444341403837363533323029272671831

42

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1DIR

1OE

2OE

2DIR

GND

GND

GND

GND

GND

GND

GND

GND

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

VCC

VCC

VCC

VCC

U7

MC74LCX245DT

123456789

10

201918171615141312

11

T/R

A0A1A2A3A4A5A6

A7

GND

VCC

OE

B0B1B2B3B4B5B6

B7

C13

1nF

C9

0.1uF

C10

0.1uF

RP2

4x 4.7K

1 2

3 4

5 6

7 8

12

34

56

78

U5

SN74LVC1G11

A

GND

B

C

VCC

Y

RP1

4x 4.7K

1 2

3 4

5 6

7 8

12

34

56

78

C11

0.1uF

C12

1nF

C15

1nF

C14

1nF

D[31:0] B_D[31:0]

R/W

A[23:0] B_A[23:0]

/CS[7:0]

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Default setting for JP2 is fitted.

Default setting for JP4 is fitted.

Default setting for JP1 is NOT fitted.

CAN Bus Connector

- 9 way D-type

(Female)

CAN1 and UART2 share the same

DB9 connector on Sheet 15

Default setting for JP3 is NOT fitted.

CAN Channel 0

CAN Channel 1

Transceiver Mode

CAN Termination

CAN Termination

Transceiver Mode

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 CAN Transceivers D

M523xEVB

B

516Tuesday, July 26, 2005

Title

Size Document Number Rev

Date: Sheet

of

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

JP1

1 2

R3

1K

R2

62

U9

SN65HVD230D

123

4 5

678

D

GND

VCC

R VREF

CANL

CANH

RS

P1

594837261

C16

0.1uF

C17

0.1uF

JP3

1 2

C18

1nF

R1

1K

C19

1nF

R4

62

JP2

1 2

JP4

1 2

U8

SN65HVD230D

123

4 5

678

D

GND

VCC

R VREF

CANL

CANH

RS

CANL1

CANH1

CAN1RX

CAN1TX

CAN0RX

CAN0TX

C187

+1.5VP

F16

G12

G11

A9A8A7

VSS

VDD

VDD

TPUCH13

TPUCH29/ERXCLK

TPUCH28/ERXDV

VSS

E4

E5

A4

G13

TCRCLK

F1F2F3

C186

C185

C184

C183

C182

C181

C180

A5

G14

TPUCH15

0.1uF

0.1uF

0.1uF

0.1uF

1nF

1nF

100pF

100pF

A6

G16

G15

H10

A6A5A4

VSS

Core VDD

TPUCH31/ECOL

TPUCH30/ECRS

VDD

F4

F5

of

616Tuesday, July 26, 2005

/SD_CAS

78

M16

SD_CAS

D24

D25

4x 22

CLKOUT

N13

CLKOUT

D26

D27

L4

Place R6 as

close to pin N15

as possible.

R6

JTAG_EN

N14

DDATA3

JTAG_EN

VDD

L5

M1M2M3

/SD_CS1

N15

D21

22

N16

SD_CS1

D22

D23

+3.3VP

NOTE: Place C33, C34 & L1 as close

L1

10uH

EXTAL

P16

P15

P14

VSS

EXTAL

VDDPLL

DDATA2

D19

D20

D13D9D17

eTPU/EthENB

P1

P2

N1N2N3

M4

PLL Filter Circuit

to pins P15 & R15 as possible using a

separate ground plane.

C34

1000pF

C33

0.1uF

VSSPLL VSSPLL

VSSPLL

XTAL

DDATA3

T16

R16

R15

D18

R1

VSSPLL

D16

XTAL

RESET

T15

VSS

PLL_TEST

R14

RSTOUT

T14

RCON

P13

DDATA0

R13

DDATA1

T13

PST0

N12

PST1

P12

PST2

R12

PST3

T12

VDD

M11

TRST/DSCLK

N11

TMS/BKPT

P11

TDO/DSO

R11

TDI/DSI

T11

VDD

L10

VDD

M10

IRQ1

N10

DTIN2

P10

DTOUT2

R10

TCLK/PSTCLK

T10

VSS

K9

VDD

L9

VDD

M9

IRQ5

N9

IRQ4

P9

IRQ3

R9

IRQ2

T9

VSS

J8

VSS

K8

VDD

L8

VDD

M8

TSIZ1

N8

TSIZ0

P8

IRQ7

R8

IRQ6

T8

VSS

K7

VDD

L7

VDD

M7

D0

N7

DTIN1

P7

DTOUT1

R7

OE

T7

VSS

L6

VDD

M6

D3

N6

D2

P6

D1

R6

VSS

T6

VSS

M5

NC

N5

D5

P5

D4

R5

Core VDD

T5

N4

D8

P4

D7

R4

D6

T4

D12

P3

D11

R3

D10

T3

D15

R2

D14

T2

VSS

T1

MCF5235

256MapBGA

DDATA2

Motorola SPS TSPG - TECD ColdFire Group

M523xEVB

Title

DDATA[3:0]

/RESET

1

DDATA[3:0]

PLL Test Point

TP1

/RSTOUT

/RCON

DDATA0
DDATA1

PST0
PST1
PST2
PST3

TRST/DSCLK

TMS/BKPT

TDO/DSO

TDI/DSI

/IRQ1

DTIN2

DTOUT2

TCLK/PSTCLK

/IRQ5
/IRQ4
/IRQ3
/IRQ2

TSIZ1
TSIZ0

/IRQ7
/IRQ6

D0

DTIN1

DTOUT1

/OE

D3
D2
D1

1

VIA2

D5
D4

D9
D8
D7
D6
D12
D11
D10
D15
D14

Size Document Number Rev

SCH-20380 CPU D

C

PST[3:0]

PST[3:0]

/IRQ[7:1]

/IRQ[7:1]

1

Date: Sheet

2

3

4

/SD_CS0

/SD_RAS

/SD_WE

/U2CTS

Default setting for JP25 &

J16

K11

K10

VSS

VDD

DTIN3/U2CTS

DTOUT3/U2RTS

DTOUT3

/U2RTS

JP26 is bewteen pins 1&2

123

JP26

/TS

/TIP

/TA

/TEA

K16

K15

K14

K13

L12

L11

K12

TS

TA

TIP

TEA

VSS

VDD

VDD

CAN0TX

L14

L13

SD_WE

I2C_SCL/CAN0TX

123456

78

123456

RP3

Place RP3 as close to pins,

L13, M13, M14 & M15 as

possible.

R/W

CAN0RX

M15

M14

M13

L16

L15

M12

R/W

VSS

SD_CS0

SD_RAS

I2C_SDA/CAN0RX

DTIN3

A[23:0]

A[23:0]

A1

A3

A2

A0

H16

H15

H14

H13

H12

H11

A3A2A1

A0

VDD

VDD

123

JP25

LTPUODIS

UTPUODIS

J15

J14

J13

J12

J11

J10

J9

VSS

VSS

VDD

VDD

LTPUODIS

UTPUODIS

TM

Motorola ColdFire

Microprocessor MCF5235

U0CTS

U0RXD

DTOUT0

DTIN0

Core VDD

U0TXD

F6

VSS

G1G2G3

U0RTSNCVSS

VDD

VDD

VSS

H1H2H3

G5G6G7

H4

G4

VDD

H5H6H7

CLKMOD0

CLKMOD1

D28

D29

D30

VSS

H8

VSS

J1J2J3

TEST

J4

VDD

VDD

J5J6J7

D31

VDD

VSS

VDD

VDD

K1K2K3

L1L2L3

K4

K5

K6

C26

1nF

U2RXD

CAN1RX

U2TXD

CAN1TX

Default setting for JP7

& JP11 is pins 2&3

A23

A22

/CS[7:0]

/CS[7:0]

/BS[3:0]

/BS[3:0]

I2C_SCL

Default setting for

JP6 & JP8 is pins 1&2

I2C_SDA

JP12

A21

A20

SD_SCKE

123

+1.5VP

/CS4

/CS6
/CS1
/CS5
/CS0

U1TXD

/CS3
/CS7
/CS2

U1RXD
/U1RTS
/U1CTS

/BS0

QSPI_PCS1

Place R5 as

close to pin C10

as possible.

/BS1
/BS2
/BS3

QSPI_PCS0

QSPI_DOUT

EMDIO

EMDC

123

JP7

1

2

3

QSPI_SCK

123

JP8

JP6

123

QSPI_DIN

4

+3.3VP

R5 22

+3.3VP

A[23:0]

C25

1nF

C24

1nF

C23

100pF

C22

100pF

C21

100pF

C20

100pF

A18

A19

B16

A19

VSS

A16

A21

A15

A20

B15

CS4

A14

A23

B14

A22

C14

CS6

A13

CS1

B13

CS5

C13

CS0

D13

A12

CS3

B12

CS7

C12

CS2

D12

VSS

E12

A11
B11
C11
D11

VDD

E11

VSS

F11

BS0

A10

B10

C10

D10

VDD

E10

VDD

F10

VSS

G10

BS1

A9

BS2

B9

BS3

C9

D9

VDD

E9

VDD

F9

VSS

G9

VSS

H9
A8

B8
C8
D8

VDD

E8

VDD

F8

VSS

G8

A7
B7

C7
D7

VDD

E7

VDD

F7

A6
B6
C6
D6

VDD

E6

A5
B5
C5
D5
A4
B4
C4
A3
B3
A2

U10

C15

A18

U1TXD

U1RTS
U1CTS

EMDIO

EMDC

A17

C16

A17

U1RXD

Core VDD

TPUCH0

TPUCH1

TPUCH2
TPUCH3

TPUCH4
TPUCH5
TPUCH6

+3.3VP

A14

A15

D15

D14

A15

A14

QSPI_PCS1

SD_SCKE

QSPI_PCS0

QSPI_DOUT

VSS

A1B1B2

C32

C31

C30

C29

C28

C27

A10

A16

A11

A12

A13

E16

E15

E14

E13

D16

A12

A11

A10

A16

U2TXD/CAN1TX

U2RXD/CAN1RX

QSPI_SCK/I2C_SCL

QSPI_DIN/I2C_SDA

TPUCH16/ETXD0

TPUCH19/ETXD3
TPUCH20/ETXER
TPUCH21/ETXEN

TPUCH17/ETXD1
TPUCH18/ETXD2

TPUCH22/ETXCLK

TPUCH23/ERXER

TPUCH24/ERXD0

TPUCH8

TPUCH7

TPUCH10

TPUCH9

C1C2C3D1D2D3D4

10uF TANT.

0.1uF

0.1uF

0.1uF

0.1uF

1nF

A8

A7

F14

F13

F12

A13

VDD

TPUCH25/ERXD1

TPUCH12

TPUCH11

TPUCH27/ERXD3

TPUCH26/ERXD2

TPUCH14

E1E2E3

A9

F15

TPUCH12

TPUCH7

TPUCH14

TPUCH11

TPUCH10

ETXER

TPUCH[15:0]

JP15

123

TPUCH19

JP17

ETXD3

123

TPUCH16

TPUCH8

JP16

ETXD0

TPUCH9

123

TPUCH24

JP18

ERXD0

123

TPUCH25

JP19

ERXD1

TPUCH4

TPUCH0

TPUCH3

TPUCH1

TPUCH5

TPUCH6

TPUCH2

5

JP9

123

123

TPUCH23

ERXER

TPUCH22

ETXCLK

JP10

123

TPUCH18

ETXD2

JP5

JP11

123

TPUCH17

JP13

ETXD1

123

TPUCH21

D D

ETXEN

JP14

TPUCH20

123

TPUCH13

123

TPUCH26

JP20

ERXD2

TCRCLK

123

TPUCH27

TPUCH15

JP21

ERXD3

123

TPUCH29

TPUCH[15:0]

JP22

123

TPUCH28

ERXCLK

JP23

ERXDV

C C

U0RXD

/U0CTS

123

TPUCH31

DTOUT0

DTIN0

JP24

ECOL

123

TPUCH30

ECRS

VIA1

1

/U0RTS

U0TXD

CLKMOD[1:0]

Default setting for JP5, JP9, JP10,

JP11, JP13-24 is 2 & 3 connected

CLKMOD[1:0]

TPUCH[31:16]

CLKMOD0

CLKMOD1

TPUCH[31:16]

D[31:0]

D29

D30

D31

D28

B B

D21

D22

D23

D19

D17

D18

D13

D20

eTPU/Ethernet Enable

- see page 13

ETPU/ETH

D16

D[31:0]

5

D[31:0]

A A

D26

D24

D27

D25

of

1

1

716Tuesday, July 26, 2005

TCLK/PSTCLK

JP28

Default

setting -

FITTED

R7

1 2

10K

Motorola SPS TSPG - TECD ColdFire Group

2

M523xEVB

TMS/BKPT

TDO/DSO

TDI/DSI

TRST/DSCLK

PST3

DDATA3

PST1

/TA

Title

Size Document Number Rev

2

SCH-20380 BDM/JTAG Debug Port D

A

Date: Sheet

NOTE: JP27 is required for some of the legacy BDM

cables that connect pins 9 & 25 of the BDM interface

internally. More recent cables support both core & I/O

voltages. Please check with your BDM cable supplier.

3

I/O Voltage

+3.3V

246

8

101214161820222426

J11357911131517192123

3

25

DDATA[3:0]

1 2

+1.5V

JP27

IMPORTANT NOTE: ONLY 3.3V BDM debugging cables

Core Voltage

4

Default setting for

JP27 is fitted.

PST2

PST0

BDM_/RSTIN

DDATA2 DDATA1

DDATA0

NOTE: 4.7K pull up resistors are used on signals /BKPT, DSCLK, DSI, DSO

& /RESET. A 1K pull up is used for /TA. See page 13 of the schematics.

can be used with the MCF523x processors.

4

DDATA[3:0]

PST[3:0] PST[3:0]

5

5

PST[3:0]

DDATA[3:0]

D D

C C

B B

A A

of

816Tuesday, July 26, 2005

1

+2.5VA +2.5VA+2.5VA +2.5VA

2

Place R8, R9, R10 & R11 close to U11.

3

Analog Ethernet Plane

+2.5VPLL +2.5VA

4

C36

C35

R11

R10

R9

R8

0.1uF

0.1uF

49.9 1%

49.9 1%

49.9 1%

49.9 1%

+3.3V

U11

1

Link LED

GREEN

R17

220

GREEN

D4

R18

220

220

Place silk screen LED labels

next to D1 thru' D4.

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 10/100BaseT Ethernet Transceiver D

M523xEVB

B

Title

Size Document Number Rev

Date: Sheet

C51

10uF

2

J2

TX+

TX-

RX+

CT_TX

CT_RX

1234567

RX-NCGND

8

Halo HFJ11-2450E

Separate RJ45 connector

chassis ground.

/IRQ[7:1]

Collision

+3.3V

LED

+3.3V

+3.3V

Full Duplex

LED

GREEN

+3.3V

100BT LED

D3

GREEN

D2

R16

D1

C50

C49

10nF

0.1uF

/IRQ[7:1]

R15

220

12

/IRQ2

FB2

R13

6.49K 1%

+2.5VA +2.5VPLL

R14

10K

4x 51

RP7

78

7 8

56

5 6

34

3 4

12

1 2

4x 51

RP6

78

7 8

56

5 6

34

3 4

12

1 2

Place RP6 & RP7 as close to the

MCF523x (CPU) as possible.

PD#

VDDRX

LED1/SPD100

LED2/DUPLEX

LED3/NWAYEN

RXD0/PHYAD4

VDDIO

GND

RXDV/PCS_LPBK

RXC

101112

2526272829303132333435

LED0/TEST

INT#/PHYAD0

RXER/ISO

GND

VDDIO
GND
CRS/RMII_LPBK
COL/RMII
TXD3
TXD2
TXD1
TXD0
TXEN
TXC/REFCLK
TXER
VDDC

24
23
22
21
20
19
18
17
16
15
14
13

KS8721BL

36

RX-

RX+

GND

GND

FXSD/FXEN

REXT

37

VDDRCV

38

GND

39

TX-

40

TX+

41

VDDTX

42

GND

43

GND

44

XO

45

XI

46

VDDPLL

47

RST#

48

MDIO

MDC

RXD3/PHYAD1

RXD2/PHYAD2

RXD1/PHYAD3

123456789

R12

4.7K

12

FB1

+2.5V

STEWARD HI1206T500R-00

STEWARD HI1206T500R-00

C48

0.1uF

C47

0.1uF

C46

0.1uF

C45

47uF

3

+2.5V

12

34

56

1 2

3 4

5 6

78

RP4 4x 51

7 8

1 2

12

34

56

78

3 4

5 6

7 8

RP5 4x 51

Place RP4 & RP5 as close

to U11 as possible.

+2.5V

NOTE: RP27 is present to ensure

the correct configuration of U11

out of reset.

4x 18K

RP27

78

7 8

56

5 6

34

3 4

12

1 2

C44

C43

C42

0.1uF

0.1uF

0.1uF

4

C41

47uF

+2.5VA

NOTE: Ethernet Ch. physical addr. default setting is addr. =

NOTE: U11 KS8721BL has an on-chip LDO that

/RSTOUT

ETH_CLK

5

1 selected via internal resistor biasing during reset.

derives the +2.5V supply from the +3.3V supply.

EMDIO

EMDC

ERXD3

ERXD2

ERXD1

ERXD0

ERXDV

ERXCLK

ERXER

ETXCLK

C40

0.1uF

ETXER

ETXEN

ETXD0

ETXD1

ETXD2

ETXD3

ECOL

ECRS

C39

1nF

5

C38

0.1uF

Place the capacitors above

close to pins 7 and 24 on U11.

C37

1nF

+3.3V

D D

C C

B B

A A

1

2

Place these zero ohm resistors as close to the junction

with the eTPU signals as possible and at an accessible

3

+3.3V

+5V

J3

BEMF_sense_C

BEMF_sense_B

40

J4

R33 120

R26 120

AN7

AN6

R19 0

R24 0

R25 0

R21 0

R23 0

R22 0

R20 0

point to allow removal if required.

1234567891011

Sheilding

BEMF_sense_A

Zero_cross_C

R27 120

AN5

TPUCH6

TPUCH7

R32 0

12

Zero_cross_B

Zero_cross_A

TPUCH5

Place the capacitors & resistors immediately below as close as

ADC Header

possible to the VinX pins on U12, as they represent an RC filter

Sheilding

TPUCH15

for the ADC inputs.

VSSA

I_sense_DCB

I_sense_A

I_sense_B

I_sense_C

V_sense_DCB_3.3

R36 120

R31 120

R30 120

R34 120

R35 120

Place these resistors at an accesible

point to allow removal if required.

AN4

AN3

AN2

AN0

AN1

C64

C179

C63

C62

C61

C60

C59

C58

2.2nF

2.2nF

2.2nF

2.2nF

2.2nF

2.2nF

2.2nF

2.2nF

VSSA

Sheilding

PWM_CB

TPUCH13

VSSA

Sheilding

PWM_CT

TPUCH11

TPUCH12

+3.3V

R37 1M

Sheilding

PWM_BB

TPUCH10

R38

PWM_BT

22K

Sheilding

PWM_AB

TPUCH9

TPUCH[15:0]

Sheilding

TPUCH8

R40 150

R39 100

PWM_AT

123456789101112131415161718192021222324252627282930313233343536373839

LTPUODIS

Molex/39-26-7405

Please place UNI3 on the

silkscreen close to J4

UNI3 connection

+3.3V

V+

OutputB

OutputA

InputA

U15

123

C66

10nF

R41

10K

678

InputB

InputA

4 5

2

GND InputB

+3.3V

Place C67 as

close to U15

as possible

+3.3V

C68

1 3

+3.3V

C69

Place C69 as

close to U16

C67

100nF

LM393M

100nF

+3.3V

I_DCB_FAULT

D5

R42 270

Y1

U16

A1

100nF

as possible

Overcurrent comparator

+3.3V

+3.3V

LED_STATUS

D6

R43 270

Y2

VCC

GND

A2

/TIP

Using GPIO

Inverter

NL27WZ04

(secondary function

on the /TIP pin)

PWM_AT

D7

R44 270

+3.3V

PWM_AB

D8

R45 270

Place C86 as

close to U17 as

possible

+3.3V

+3.3V

+3.3V

PWM_BT

PWM_CB

D9

D10

R47 270

R46 270

+3.3V

14

VCC

1A1Y2A2Y3A3YGND 4Y

U17

1234567 8

C86

100nF

+3.3V

C85

0.1uF

C84

0.1uF

C83

0.1uF

C82

0.1uF

C81

0.1uF

C80

0.1uF

C79

0.1uF

C78

0.1uF

C77

1nF

C76

1nF

C75

1nF

C74

1nF

TPUCH8

PWM_CT

D11

R48 270

TPUCH9

+3.3V

910111213

4A5Y5A6Y6A

TPUCH10

TPUCH1

+3.3V

PWM_BB

D12

R50 270

Inverter

SN74HC04D

TPUCH11

+3.3V

Place C89

+3.3V

TPUCH12

TPUCH3

TPUCH2

C89

100nF

as close to

U18 as

R52

TPUCH13TPUCH4

possible

1k

R54 1K8R53 24

Red led: I_DCB_FAULT

TPUCH1

C90

+3.3V

of

916Tuesday, July 26, 2005

1

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 eTPU connectors and ADC D

M523xEVB

C

Title

Size Document Number Rev

Date: Sheet

Yellow led: PWM_AB, PWM_BB, PWM_CB

Green led: PWM_AT, PWM_BT, PWM_CT, LED_STATUS

2

TCRCLK

+3.3V

Y1

B2

A2

VCC

NL27WZ86

U18

A1B1Y2

470pF

GND

EXOR Logic Gate

TPUCH2

C91

470pF

R58 1K8

R57 24

R56

1k

+3.3V

R62 1K8

R61 24

R59

1k

TPUCH3

C92

+3.3V

470pF

TPUCH4

3

C93

470pF

R65 1K8

R64 24

R63

1k

C73

+3.3V

TPUCH8

23 24

TPUCH26

TPUCH9

25 26

TPUCH27

C72

C71

C70

TPUCH10

27 28

TPUCH28

1nF

1nF

1nF

1nF

TPUCH12

TPUCH11

29 30

TPUCH29

TPUCH30

C88

100nF

+5V

2.2uF

+3.3V

J6

Place C87 and

C88 as close

as possible to

pins 1 & 2 on

R55

4k7

-UP

SW2

+5V

C87

R49

4K7

TSIZ0

Using GPIO (secondary

function on the /TEA pin)

R51

1k8

1

3

SW1

2

+

RUN/STOP

TPUCH[15:0]

TPUCH15

TPUCH14

TPUCH13

eTPU Header

31 32

33 34

35 36

37 38

39 40

TPUCH31

TCRCLK

+3.3V

TPUCH[31:16]

B B

C56

10uF

C52

0.1uF

4

5

QSPI_DIN

QSPI_SCK

+3.3V+5VA

U12

QSPI_DOUT

DOUT

Vdrive

AGND

AGND

SCLK

DIN

CS

AGND

123456789

C54

C53

U13

+5VA

10uF

0.1uF

123

Vin0

AVDD

2.5/3.0V

NC

D D

VSSAVSSA

121314151617181920

Vin4

Vin3

Vin2

Vin1

AVDD

REFIN

AGND

Vin7

Vin6 Vin5

AD7928BRU

10 11

VSSA

C57

0.1uF

678

NC

Vout

+Vin

TEMP

GND TRIM

AD780BR

4 5

VSSA

C55

0.1uF

Please ensure VSSA has a plane of copper under J4, U11 & U12.

C65

100nF

+3.3V

+3.3V

Place C65

as close to

U14 as

possible

Y

VCC

U14

BAGND

AND Gate Logic

NL17SZ08

Please ensure there is thicker gauge copper

between Vout on U13 and REFIN on U12.

TPUCH14

JP29

1 2

QSPI chip select

jumper, default FITTED

QSPI_PCS0

+5V

J5

+3.3V

C C

1 2

UTPUODIS

3 4

5 6

TPUCH17

TPUCH16

LTPUODIS

TPUCH0

7 8

TPUCH18

TPUCH[15:0]

TPUCH1

9 10

TPUCH19

TPUCH3

TPUCH2

11 12

13 14

TPUCH21

TPUCH20

TPUCH4

15 16

TPUCH22

TPUCH6

TPUCH5

17 18

TPUCH23

TPUCH24

19 20

TPUCH7

21 22

TPUCH25

12345

J6

/TEA

Using GPIO (secondary

1 3

2 4

JP30

1 2

default FITTED

6

HS/ENCO Header

Please place HS/ENC0 on

the silkscreen close to J6

function on the TSIZ0 pin)

R60

4K7

+3.3V

-DOWN

SW3

KS11R22CQD

A A

Hall sensors/En coder connector

TSIZ1

Using GPIO (secondary

function on the TSIZ1 pin)

KS11R22CQD

1 3

2 4

4

5

Buttons & switch

A[23:0]

of

10 16Tuesday, July 26, 2005

1

A[23:0]A[23:0]A[23:0]

DDATA[3:0]

Motorola SPS TSPG - TECD ColdFire Group

DDATA[3:0]DDATA[3:0]

/SD_CS1

CLKOUT

/SD_CAS/SD_CS0

R/WCAN0TX

CAN0RX/SD_WE

/TS

/TIP

DTOUT3

DTIN3

A2A1A12

A6

A13

A15

A21

A9A7

A3

A5

A16

A17

13579111315171921232527293133353739414345474951535557

2

/BS[3:0]

/CS[7:0]

NOTE: if designing a daughter card to fit these expansion connectors

please ensure all signals are buffered on the daughter card.

/CS[7:0]

/CS[7:0]

/CS[7:0]

J9

246

8

10121416182022242628303234363840424446485052545658

A10

A11

A18

A20 A19

A22

A14A4A8

A0

/TEA

LTPUODIS

UTPUODIS

/BS[3:0]

AMP 177983-2

J7

60

59

58

57

/CS4

55

/CS1

53

/CS6

51

/CS3

U1TXD

U1RXD

/U1RTS

QSPI_PCS1

QSPI_SCK

I2C_SCL

/U2RTS

/U2CTS

3

49
47
45
43
41
39

/BS0

37

/BS1

35

/BS2

33

/BS3

31
29
27
25

TPUCH16

23

TPUCH21

21

TPUCH20

19

TPUCH19

17

TPUCH23

15

TPUCH22

13

TPUCH18

11

TPUCH17

9

TPUCH24

7
5
3
1

A23

56

/CS0

54

/CS5

52

/CS7

50

/CS2

48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

U2TXD

CAN1TX

/U1CTS

U2RXD

CAN1RX

SD_SCKE

QSPI_PCS0

QSPI_DOUT

QSPI_DIN

I2C_SDA

EMDC

EMDIO

TPUCH0
TPUCH1
TPUCH3
TPUCH2
TPUCH5
TPUCH4
TPUCH6

CLKMOD[1:0]

/TA

/SD_RAS

DDATA3

/EXT_RSTIN

59

AMP 177983-2

60

PST[3:0]

DDATA[3:0]

EXTAL XTAL

/IRQ[7:1]

JTAG_EN

TDO/DSO

DTOUT2DTIN2

TSIZ1

DTIN1

PST[3:0]

PST[3:0]

/IRQ[7:1]

/IRQ[7:1]

AMP 177983-2

J10

60

59

58

57

56

55

54

53

52

51

50

49

48

47

DDATA2
PST0
PST1PST2

TRST/DSCLK

/IRQ1

/IRQ5
/IRQ3/IRQ4

/IRQ7

D0
D3
D1

D5
D7
D11
D14D10

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

DDATA1
DDATA0

PST3

/IRQ2

/IRQ6

D2

D4
D8
D6

PST[3:0]

/OE

/IRQ[7:1]

TMS/BKPT

TDI/DSI

TCLK/PSTCLK

TSIZ0

DTOUT1

M523xEVB

Title

/RESET

/RCON

1

SCH-20380 Expansion Connectors D

C

Size Document Number Rev

Date: Sheet

2

/RSTOUT

3

TPUCH[31:16]TPUCH[31:16]

4

5

+3.3V

+5V

+1.5V

+3.3V

TPUCH[15:0]

U0RXDDTOUT0

DTIN0U0TXD

/U0RTS

TPUCH26

TPUCH29

TPUCH28

TPUCH31

TPUCH30

CLKMOD1

D31

TPUCH10TPUCH9

TPUCH25

TPUCH27

CLKMOD0

D26

13579111315171921232527293133353739414345474951535557

J8

246

8

10121416182022242628303234363840424446485052545658

+3.3V +1.5V +3.3V+5V +3.3V+1.5V+3.3V +5V

TPUCH7 TPUCH8

TPUCH12

TPUCH11

TPUCH14

TPUCH13

TCRCLK

TPUCH15

/U0CTS

D28

D24

D25

D29 D30

D[31:0]

D27

D13

D23

D9

D12

D15

59

AMP 177983-2

60

D19

D16

D21

D22

D20

D17

D18

TPUCH[15:0] TPUCH[15:0]

TPUCH[15:0]

TPUCH[31:16]

D D

C C

B B

+3.3V

+5V

+1.5V

+3.3V

+1.5V

D[31:0] D[31:0]

D[31:0]

D[31:0]

C109

470pF

C108

470pF

4

C107

470pF

C97

470pF

C106

470pF

C96

470pF

C105

10nF

C95

10nF

C104

10nF

C94

10nF

C103

10nF

C102

10nF

C101

0.1uF

5

C100

0.1uF

C99

1nF

C98

1nF

+5V +3.3V

A A

of

11 16Tuesday, July 26, 2005

1

1

B_A[23:0]

C117

0.1uF

C116

0.1uF

C115

0.1uF

C114

0.1uF

C113

1nF

C112

1nF

C111

+3.3V

C110

1nF

1nF

2

+3.3V

C120

C119

C118

0.1uF

0.1uF

1nF

B_D[31:0]

B_D[31:0]

+3.3V

R66

4.7K

JP31

32MBit Flash

Boot

Default setting - JP31 fitted

across pins 1 & 2

1

3

2

B_A21

B_A18

B_A19

B_A20

B_A15

B_A16

B_A17

B_A12

B_A11

B_A13

B_A14B_A2

B_A9

B_A8

B_A10

+3.3V

K8J8K7J7H7K6J6H6K5J5H5G5F5K4J4H4G4K3J3H3K2

B_D9
B_D24

B_D25

B_D26

B_D10
B_D11
B_D27

B_D28
B_D12
B_D31
B_D14
B_D29
B_D13
B_D15B_D0

B_D30

DQ24

H8

VCC

H9

DQ8

G6

DQ25

G7

VSS

G8

DQ26

G9

NC

F6

DQ10

F7

DQ11

F8

DQ27

F9

NC

E6

VSS

E7

DQ28

E8

DQ12

E9
D6

DQ14

D7

DQ29

D8

DQ13

D9

DQ15

C8

VCC

C9

DQ30

B9

U35

CE

A19

DQ9

J9

A8B8A7

NCNCNCNCNC

A16

A17

A18

A13

A14

A15

VCC

DQ31/A-1

VSSNCWORDOEWENCNCNCACCWPNCNCA1A2A3A0A4A5VCC

B7C7A6

B6C6A5

B5

A7A6A8

A10A9A11

A12

VSS

DQ23
DQ22
DQ7
VCC
DQ21
DQ6
VSS
NC
DQ5
DQ4
DQ20
DQ2
DQ18
DQ19
DQ3
DQ16
VSS
VCC
DQ0
DQ1
DQ17

E5A4B4

A3B3B2

C5

D5

C4

D4

B_D[31:0]

J2
J1
H2
H1
G3
G2
G1
F4
F3
F2
F1
E4
E3
E2
E1
D3
D2
D1
C3
C2
C1

Am29PL320D

B_D23
B_D22
B_D7 B_D8

B_D21
B_D6

B_D5
B_D4
B_D20
B_D2
B_D18
B_D19
B_D3
B_D16

B_D1
B_D17

B_D[31:0]

B_A[23:0]B_A[23:0] B_A[23:0]

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 Flash Memory (Fujitsu SSOP OR AMD BGA) D

M523xEVB

C

Title

Size Document Number Rev

Date: Sheet

2

B_A6

B_A4

B_A7

B_A5

Default setting - JP64

fitted across pins 1 & 2

B_A11

B_A12

B_A13

B_A14

B_A15

B_A16

B_A17

B_A3

B_D31

R69

B_D23

4.7K

B_D30

B_D22

B_D29

B_D21

B_D28

B_D20

B_D[31:0]

Only one or the other footprints

will be populated - BGA (U35)

OR SSOP (U19)

3

4

R67

3

4

4.7K

+3.3V

+3.3V

NOTE: The write protect pin (C5)

should not be left floating as

JP32

R68

4.7K

1

inconsistant behaviour of the

Flash device could result.

To use hardware protect on the

top/bottom boot sector set JP32

between pins 2 & 3. To disable

hardware protect set between

pins 1 & 2 (default).

3

2

16 MBit

Flash Boot

JP64

1

3

B_A20

2

B_A9

B_A10

+3.3V

242526272829303132333435363738394041424344

A9

A8

B_A[23:0]

NC

A19

U19

WE#

A18

123456789

B_A19

A10

A17A7A6A5A4A3A2A1A0

B_A7

B_A8

B_A18

A16

A15

A14

A13

A12

A11

BYTE#

CE#

10111213141516171819202122 23

B_A1

B_A2

B_A3

B_A4

B_A5

B_A6

Vss

Vss

DQ7

DQ15/A-1

OE#

DQ0

B_D16

B_D24

DQ14

DQ8

DQ6

DQ1

B_D17

DQ13

DQ9

B_D25

DQ5

DQ2

B_D18

DQ12

DQ10

B_D26

B_D19

DQ4

DQ3

DQ11 Vcc

AMD Am29PL160CB-65RS

B_D27

B_D[31:0]

Memory Size: 1M x 16-bit = 2MB Memory Size: 1M x 32-bit = 4MB

/CS0

5

/OE

R/W

/CS[7:0]

D D

C C

B B

A A

5

D

of

12 16Tuesday, July 26, 2005

1

2

3

JP33

JP33 SHOULD BE

INSTALLED DURING

ASSEMBLY

+3.3VP

1 2

1

FB5

1 2

VSSA

VSSA - analog ground for eTPU channels

FB6

1 2

VSSPLL

VSSPLL - filtered ground for CPU PLL module

Filtered ground for plane for ethernet RJ45 connector

+1.5V

D20

MBRS340T3

Motorola SPS TSPG - TECD ColdFire Group

SCH-20380 Power Supply

M523xEVB

B

Title

Size Document Number Rev

Date: Sheet

2

+3.3V

FB3

+5V +5VA

FB4

1 2

1 2

+5VA - filtered power for eTPU ADC

+5V

2 1

R70

270

C122

0.1uF

C121

330uF

R71

+3.3V GREEN POWER LED

D14

560

C127

C126

0.1uF

330uF

D17

+5V GREEN POWER LED

MRA4003T3

D19

D18

MRA4003T3

NOTE: Diodes prevent excessive

difference between 3.3V & 1.5V

rails, at power up

NOTE: Schottky Diode prevents excessive

+3.3V

D16

25uH

D13

25uH

MBRS340T3

L3

L2

2 1

MBRS340T3

2 1

21

MBRS340T3

D22

difference between 3.3V & 1.5V

rails, at power down

+3.3V +1.5V

3

3.3V Regulator
U20 LM2596S-3. 3

VIN VOUT

1 2

4

FB

TAB

GND

~ON/OFF

5

6

3

5.0V Regulator

U21 LM2596S-5

1 2

VIN VOUT

4

FB
TAB

GND

~ON/OFF

5

6

3

+1.5VP

JP34

1 2

C125

1000uF

D15

5A Fast blow.

C124

C123

2 1

MBRS340T3

1nF

0.1uF

4

F1

5

621

SW4

3

4

POWER SW SLIDE-SPST(Board Edge)

5

JP34 SHOULD BE

INSTALLED DURING

ASSEMBLY

LT1086CM

1.5V Regulator
U22

2

3

VOUT

VIN

ADJ

C130

C129

R73 120

1

C128

10uF TANT.

0.1uF

4

330uF

R74 22

5

123

+

Power Jack Connector -

2.1mm diameter

NOTE: the positive terminal of each

power connector must be shown on the

silkscreen of the PCB

DC voltage input range +7 to +14V

P2

-

2-way Bare Wire

Power Connector

Switchcraft RAPC712

1

2

P3

Augat 25V-02

-

+

+5V +1.5V

D D

C C

B B

A A

R80

12

4x 4.7K

78

4x 4.7K

+3.3V

+3.3V

RP17

RP16

1 2

/IRQ4

1 2

/CS4

123456

78

3 4

5 6

7 8

/IRQ5

/IRQ7/CS7

/IRQ6

123456

78

3 4

5 6

7 8

/CS6

/CS5

78

5 6

7 8

/BS3

4x 4.7K

/BS[3:0]

+3.3V

+3.3V

RP15

RP14

7 8

/IRQ1

1 2

/CS0

34

56

78

1 2

3 4

5 6

/IRQ3

/IRQ2

123456

3 4

5 6

7 8

/CS3

/CS2

/CS1

56

78

3 4

5 6

7 8

TDI/DSI/OE

TDO/DSO

56

78

3 4

5 6

7 8

/TEA

12

34

4x 4.7K

1 2

TMS/BKPT

TRST/DSCLK

12

34

4x 4.7K

1 2

R/W

/TIP

+3.3V

RP11

+3.3V

RP10

12

34

56

78

1 2

3 4

5 6

7 8

TSIZ0

TSIZ1

/TS

123456

78

1 2

3 4

5 6

7 8

/RSTOUT

UTPUODIS

LTPUODIS

4x 4.7K

4x 4.7K

+3.3V

RP12

1 2

/BS0

123456

3 4

/BS1

/BS2

+3.3V

RP9

1

+3.3V

RP8

4x 4.7K

4x 4.7K

+3.3V

/IRQ[7:1]

/IRQ[7:1]

/CS[7:0]

1K

1

CHIP SELECT 0

/CS0

1

TP7

TRANSFER ACKNOWLEDGE

/TA

1

TP5

TP3

OUTPUT ENABLE

/TA

/OE

1

GROUND

1

TP12

GROUND

TP10

of

13 16Tuesday, July 26, 2005

1

/CS[7:0]

Motorola SPS TSPG - TECD ColdFire Group

1

TP2

1

TRANSFER START

/TS

TP4

1

READ NOT WRITE

R/W

TP6

1

CPU CLOCK I/P

Place TP6 as

close to EXTAL

as possible

TP8

1

CPU CLOCK O/P

CLKOUT

1

TP11

TP9

GROUND

GROUND

Important Note - all unconnected pull-up and pull-down

resistor pack connections, on all schematics pages, need

to be connected to an unmasked via.

NOTE: Place TP9, TP10, TP11 & TP12 at the corners of the PCB

to allow easy connection of 'scope probe ground leads.

M523xEVB

Title

SCH-20380 Reset Configuration & Clock selection D

C

Size Document Number Rev

Date: Sheet

2

OSCILLATOR - dual layout footprint

3

+3.3V

4

+3.3V

ETH_CLK

NOTE: signal track lengths between these clock

circuits and the MCF523x should be minimised.

+3.3V

VDD

U23

OE

GND CLK

OE VDD

1

7 8144 11

for 8 AND 14 pin socketed DIL osc.'s

R76

10K

/IRQ[7:1]

/IRQ[7:1]

/IRQ7

R77 100

D23 RED -INT7 LED

R75

270

25MHz

VSSPLL

+3.3V

1

JP35

3

1

J11

External Clock Input (SMA connector)

R78

270

+3.3V

+3.3V

4x 10K

RP13

/BS[3:0]

2

5
4
3
2

78

7 8

56

5 6

34

3 4

12

1 2

JP36

1

VSSPLL

D24

RED RESET LED

C

U26

A

R79 100

EXTAL

2

3

25MHz

Y1

/RESET/BDM_RSTIN

Buffered and "OR'd" /RSTI signal to the CPU from the

BDM port, expansion connectors or reset switch.

+3.3V

Y

VCC

SN74LVC1G11

GND

B

/CS[7:0]

XTAL

RP19

4x 10

78
56
34
12

JP37

C132

C131

10pF

10pF

7 8
5 6
3 4
1 2

Crystal Enable

1 2

D26

VSSPLL

JP39

1 2

DTOUT0

DTIN0

D28

DTIN0 LED

JP41

DTOUT1

DTIN1

1 2

DTIN1 LED

D30

JP43

1 2

DTOUT2

DTIN2

D32

DTIN2 LED

JP45

DTOUT3

1 2

DTIN3

DTIN3 LED

JTAG_EN

/RCON

CLKMOD1

CLKMOD0

IMPORTANT NOTE: THE /RSTOUT SIGNAL MUST BE

USED TO DRIVE THE OUTPUT ENABLE PINS OF U7

TO ALLOW THE D16, D17, D18, D19, D21, D24, D25

& D26 SIGNALS TO BE LATCHED CORRECTLY BY

THE MCF523x FOR CONFIGURATION AT RESET.

+3.3V

123456

78

4x 4.7K

RP22

1 2

3 4

5 6

7 8

123456

78

4x 4.7K

RP21

1 2

3 4

5 6

7 8

+3.3V

123456

78

4x 4.7K

RP20

1 2

3 4

5 6

7 8

CLKMOD[1:0]

CLKMOD[1:0]

+3.3V

U27

123456789

/RSTOUT

CLKMOD0

CLKMOD1

JTAG_EN

RCON

D16

D20

D19

D24

D21

OE2

VCC

D0D1D2D3D4D5D6D7GND O7

OE1

D25

D24

D21

D20

D19

D16

D25

121314151617181920

O6O5O4O3O2O1O0

10 11

ETPU/ETH

D[31:0]

MC74LCX541DT

Encoded Boot Device (Port Size)

Encoded Operating Mode

Encoded Clock Mode

D[31:0]

2

Ethernet/eTPU Mode (eTPU channels 16 to 31)

SW7-11 Mode

----------- -----------

OFF eTPU enabled

ON Ethernet enabled

Encoded Address/Chip Select Mode

SW7-9 SW7-10 Mode

----------- ----------- --------------------------

SW7-6 SW7-7 Mode

----------- ----------- --------------------------

OFF OFF External (32-bit)

OFF ON External (8-bit)

SW7-5 Mode

----------- -----------

OFF Reserved

ON Master

3

OFF OFF PF[7:5] = /CS[6:4]

OFF ON PF7 = /CS6, PF[6:5] = A[22:21]

ON OFF PF[7:6] = /CS[6:5], PF[5] = A21

ON ON PF[7:5] = A[23:21]

ON OFF External (16-bit)

ON ON External (32-bit)

4

NOTE: Please place these tables on the silkscreen on the topside of the PCB close to SW7.

SW7-3 SW7-4 Mode

----------- ----------- --------------------------------------------------

OFF OFF External Clock - (No PLL)

OFF ON 1:1 PLL

ON OFF Normal PLL operation (Ext. Clock)

ON ON Normal PLL operation (Ext. Crystal)

/EXT_RSTIN

678

N.C.

RESET

RESET

MR

VCC

GND

PFI PFO

U24

123

4 5

ADM708SAR

DEBOUNCED /IRQ7

5

SIGNAL

+3.3V

SW5

KS11R22CQD

ABORT/-INT7

D D

678

N.C.

RESET

RESET

MR

VCC

GND

PFI PFO

U25

HARD RESET & VOLTAGE

SENSE CONTROLLER

123

4 5

+3.3V

SW6

RESET

KS11R23CQD

ADM708SAR

+3.3V

NOTE: Please place D25 through D32 together in a line.

Default setti ng for JP38 through JP45 is fitted.

SW7

1 2

DTOUT1 LED

JP42

1 2

DTOUT2 LED

JP44

1 2

DTOUT3 LED

Closed/On Open/Off

Configuration DIP switch - Grayhill 78RB12

5

JP38

1 2

DTOUT0 LED

JP40

+3.3V

4x 10

RP18

D25

78

7 8

56

5 6

34

3 4

12

1 2

C C

D27

D29

D31

------------------------ OFF - SW7 - ON ------------------------

Chip Config. Off 1 Chip Config. On

JTAG Interface Enabled 2 BDM Interface Enabled

Encoded Clock Mode 3 Encoded Clock Mode

Encoded Clock Mode 4 Encoded Clock Mode

Encoded Oper. Mode 5 Encoded Oper. Mode

Encoded Boot Device 6 Encoded Boot Device

Encoded Boot Device 7 Encoded Boot Device

Partial Bus Drive 8 Full Bus Drive

Encoded Address Mode 9 Encoded Address Mode

Encoded Address Mode 10 Encoded Address Mode

Note: default setting for SW7 is all switches closed/on.

B B

A A

eTPU Enabled 11 Ethernet Enabled