Freescale MCF5235, MCF5234, MCF5233, MCF5232 User Guide

M5235EVB User’s Manual

Devices Supported:

MCF5235
MCF5234
MCF5233
MCF5232

Document Number: M5235EVBUM

Rev. 1.2
08/2005

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© Freescale Semiconductor, Inc. 2005. All rights reserved.

Document Number: M5235EVBUM
Rev. 1.2
08/2005

EMC Information on M523xEVB

1. This product as shipped from the factory with associated power supplies and cables, has been tested and
meets with requirements of EN5022 and EN 50082-1: 1998 as a CLASS A product.

2. This product is designed and intended for use as a development platform for hardware or software in an
educational or professional laboratory.

3. In a domestic environment this product may cause radio interference in which case the user may be
required to take adequate measures.

4. Anti-static precautions must be adhered to when using this product.

5. Attaching additional cables or wiring to this product or modifying the products operation from the factory
default as shipped may effect its performance and also cause interference with other apparatus in the
immediate vicinity. If such interference is detected, suitable mitigating measures should be taken.

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor iii

WARNING

This board generates, uses, and can radiate radio frequency energy and, if not
installed properly, may cause interference to radio communications. As
temporarily permitted by regulation, it has not been tested for compliance with the
limits for class a computing devices pursuant to Subpart J of Part 15 of FCC rules,
which are designed to provide reasonable protection against such interference.
Operation of this product in a residential area is likely to cause interference, in
which case the user, at his/her own expense, will be required to correct the
interference.

M523xEVB User’s Manual, Rev. 1.2

iv Freescale Semiconductor

Contents

Paragraph
Number

Title

Page

Number

Chapter 1

M523xEVB

1.1 MCF5235 Microprocessor .............................................................................................. 1-3

1.2 System Memory .............................................................................................................. 1-6

1.2.1 External Flash ............................................................................................................. 1-6

1.2.2 SDRAM ...................................................................................................................... 1-7

1.2.3 ASRAM ...................................................................................................................... 1-7

1.2.4 Internal SRAM ............................................................................................................ 1-7

1.2.5 M523xEVB Memory Map .......................................................................................... 1-7

1.2.5.1 Reset Vector Mapping ............................................................................................ 1-8

1.3 Support Logic ................................................................................................................. 1-8

1.3.1 Reset Logic ................................................................................................................. 1-8

1.3.2 Clock Circuitry ......................................................................................................... 1-10

1.3.3 Watchdog Timer ....................................................................................................... 1-10

1.3.4 Exception Sources ..................................................................................................... 1-11

1.3.5 TA Generation .......................................................................................................... 1-11

1.3.6 User’s Program ......................................................................................................... 1-12

1.4 Communication Ports ................................................................................................... 1-12

1.4.1 UART0 and UART1 Ports ........................................................................................ 1-12

1.4.2 UART2/FlexCAN1 Port ........................................................................................... 1-13

1.4.3 FlexCAN0 Port ......................................................................................................... 1-13

1.4.4 10/100T Ethernet Port ............................................................................................... 1-14

1.4.5 eTPU ......................................................................................................................... 1-15

1.4.6 BDM/JTAG Port ....................................................................................................... 1-16

1.4.7 I2C ............................................................................................................................ 1-17

1.4.8 QSPI .......................................................................................................................... 1-18

1.4.9 USB Host and Device ............................................................................................... 1-18

1.5 Connectors and User Components ................................................................................ 1-19

1.5.1 Daughter Card Expansion Connectors ...................................................................... 1-19

1.5.2 Reset Switch (SW6) .................................................................................................. 1-23

1.5.3 User LEDs .................................................................................................................1-23

1.5.4 Other LEDs ............................................................................................................... 1-24

Chapter 2

Initialization and Setup

2.1 System Configuration ..................................................................................................... 2-1

2.2 Installation and Setup ......................................................................................................2-3

2.2.1 Unpacking ................................................................................................................... 2-3

2.2.2 Preparing the Board for Use ....................................................................................... 2-3

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor v

Contents

Paragraph
Number

2.2.3 Providing Power to the Board ..................................................................................... 2-3

2.2.4 Power Switch (SW4) .................................................................................................. 2-4

2.2.5 Power Status LEDs and Fuse ...................................................................................... 2-4

2.2.6 Selecting Terminal Baud Rate .................................................................................... 2-4

2.2.7 The Terminal Character Format ................................................................................. 2-5

2.2.8 Connecting the Terminal ............................................................................................ 2-5

2.2.9 Using a Personal Computer as a Terminal .................................................................. 2-5

2.3 System Power-up and Initial Operation .......................................................................... 2-8

2.4 Using The BDM Port ...................................................................................................... 2-8

Title

Page

Number

Chapter 3

Using the Monitor/Debug Firmware

3.1 What Is dBUG? ...............................................................................................................3-1

3.2 Operational Procedure .................................................................................................... 3-2

3.2.1 System Power-up ........................................................................................................ 3-2

3.2.2 System Initialization ................................................................................................... 3-3

3.2.2.1 External RESET Button .......................................................................................... 3-4

3.2.2.2 ABORT Button ....................................................................................................... 3-4

3.2.2.3 Software Reset Command ...................................................................................... 3-4

3.3 Command Line Usage .................................................................................................... 3-4

3.4 Commands ...................................................................................................................... 3-5

3.5 TRAP #15 Functions .................................................................................................... 3-39

3.5.1 OUT_CHAR ............................................................................................................. 3-39

3.5.2 IN_CHAR ................................................................................................................. 3-40

3.5.3 CHAR_PRESENT .................................................................................................... 3-40

3.5.4 EXIT_TO_dBUG ...................................................................................................... 3-41

Appendix A

Configuring dBUG for Network Downloads

A.1 Required Network Parameters ......................................................................................... 4-1

A.2 Configuring dBUG Network Parameters......................................................................... 4-1

A.3 Troubleshooting Network Problems................................................................................ 4-2

Appendix B
Schematics

Appendix C

Evaluation Board BOM

M523xEVB User’s Manual, Rev. 1.2

vi Freescale Semiconductor

Figures

Figure
Number

1-1 M523xEVB Block Diagram ..................................................................................................... 1-3

1-2 MCF5235 Block Diagram ........................................................................................................1-5

1-3 External Memory Scheme ........................................................................................................ 1-6

1-4 J1- BDM Connector Pin Assignment ..................................................................................... 1-17

2-1 Minimum System Configuration .............................................................................................. 2-2

2-2 2.1mm Power Connector .......................................................................................................... 2-3

2-3 2-Lever Power Connector......................................................................................................... 2-4

2-4 Pin Assignment for Female (Terminal) Connector................................................................... 2-5

2-5 Jumper Locations...................................................................................................................... 2-7

3-1 Flow Diagram of dBUG Operational Mode ............................................................................. 3-3

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor Freescale Semiconductor Internal Use Only vii

Figures

Figure
Number

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

viii Freescale Semiconductor Internal Use Only Freescale Semiconductor

Tables

Table
Number

1-1 M523x Product Family ............................................................................................................. 1-1

1-2 The M523xEVB Default Memory Map.................................................................................... 1-8

1-3 D[20:19] External Boot Chip Select Configuration ................................................................. 1-8

1-4 SW7-1 RCON ........................................................................................................................... 1-9

1-5 SW7-2 JTAG_EN ..................................................................................................................... 1-9

1-6 SW7-[4:3] Encoded Clock Mode ............................................................................................. 1-9

1-7 SW7-5 Chip Configuration Mode............................................................................................. 1-9

1-8 SW7-[7:6] Boot Device ............................................................................................................ 1-9

1-11 M523xEVB Clock Source Selection ...................................................................................... 1-10

1-9 SW7-8 Bus Drive Strength .....................................................................................................1-10

1-10 SW7-[10:9] Address/Chip Select Mode ................................................................................. 1-10

1-12 UART2/FlexCAN1 Jumper Configuration............................................................................. 1-13

1-13 FlexCAN1 Jumper Configuration........................................................................................... 1-13

1-14 FlexCAN0 Jumper Configuration........................................................................................... 1-13

1-15 CAN Bus Connector Pinout....................................................................................................1-14

1-16 Ethernet/eTPU Jumper Configuration .................................................................................... 1-15

1-17 eTPU Header Pin Assignment ................................................................................................ 1-16

1-18 USB DMA Enable and Disable Settings ................................................................................ 1-18

1-19 J7............................................................................................................................................. 1-19

1-20 J8............................................................................................................................................. 1-20

1-21 J9............................................................................................................................................. 1-21

1-22 J10........................................................................................................................................... 1-22

1-23 User LEDs............................................................................................................................... 1-23

1-24 LED Functions........................................................................................................................ 1-24

2-1 Power LEDs.............................................................................................................................. 2-4

2-2 Pin Assignment for Female (Terminal) Connector................................................................... 2-5

3-1 dBUG Command Summary...................................................................................................... 3-5

C-1 M523xEVB Bill of Materials ...................................................................................................6-2

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor Freescale Semiconductor Internal Use Only ix

Tables

Table
Number

Title

Page

Number

M523xEVB User’s Manual, Rev. 1.2

x Freescale Semiconductor Internal Use Only Freescale Semiconductor

Chapter 1 M523xEVB

This document details the setup and configuration of the ColdFire M523xEVB evaluation board (hereafter
referred to as the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the
MCF523x family of ColdFire microprocessors and to facilitate hardware and software development. The
EVB can be used by software and hardware developers to test programs, tools, or circuits without having
to develop a complete microprocessor system themselves. All special features of the MCF523x family are
supported.

The heart of the evaluation board is the MCF5235, all the other M523x family members have a subset of
the MCF5235 specification and can therefore be fully emulated using the MCF5235 device. Table 1-1
below details the full product family.

Table 1 - 1 . M5 2 3x Product Family

Part Number Package eTPU FEC CRYPTO CAN

MCF5232CAB80 160 QFP 16-channel No No 1

MCF5232CVM100 196 MAPBGA 16-channel No No 1

MCF5232CVM150 196 MAPBGA 16-channel No No 1

MCF5233CVM100 256 MAPBGA 32-channel No No 2

MCF5233CVM150 256 MAPBGA 32-channel No No 2

MCF5234CVM100 256 MAPBGA 16-channel Yes No 1

MCF5234CVM150 256 MAPBGA 16-channel Yes No 1

MCF5235CVM100 256 MAPBGA 16-channel Yes Yes 2

MCF5235CVM150 256 MAPBGA 16-channel Yes Yes 2

All of the devices in the same package are pin compatible.

The EVB provides for low cost software testing with the use of a ROM resident debug monitor, dBUG,
programmed into the external Flash device. Operation allows the user to load code in the on-board RAM,
execute applications, set breakpoints, and display or modify registers or memory. No additional hardware
or software is required for basic operation.

Specifications:

• Motorola MCF5235 Microprocessor (150 MHz max core frequency)

• External Clock source: 25 MHz

• Operating temperature: 0°C to +70°C

• Power requirement: 7–14V DC @ 300 ma Typical

• Power output: 5V, 3.3V and 1.5V regulated supplies

• Board Size: 10.00 × 5.40 inches, 8 layers

Memory Devices:

• 16-Mbyte SDRAM

• 2-Mbyte (512K × 16) Page Mode FLASH or 4-Mbyte (512K × 32) Page mode FLASH

• 1-Mbyte ASRAM (optional)

• 64-Kbyte SRAM internal to MCF523x device

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor 1-1

M523xEVB

Peripherals:

• Ethernet port 10/100Mb/s (Dual-Speed Fast Ethernet Transceiver, with MII)

• UART0 (RS-232 serial port for dBUG firmware)

• UART1 (auxiliary RS-232 serial port)

• UART2 (auxiliary1 RS-232 serial port jumper selectable with FlexCAN1)

• Enhanced Time Processor Unit (eTPU)

2

•I

C interface

• QSPI interface to ADC

• FlexCan0 interface

• USB Host and Device Interface

• BDM/JTAG interface

User Interface:

• Reset logic switch (debounced)

• Boot logic selectable (dip switch)

• Abort/IRQ7 logic switch (debounced)

• PLL Clocking options - Oscillator, Crystal or SMA for external clocking signals

• LEDs for power-up indication, general purpose I/O, and timer output signals

• Expansion connectors for daughter card

• UNI-3 connector for motor control cards

Software:

• Resident firmware package that provides a self-contained programming and operating
environment (dBUG)

M523xEVB User’s Manual, Rev. 1.2

1-2 Freescale Semiconductor

MCF5235 Microprocessor

r

DB-9 (2)

connector

RJ-45

connector

DB-9

connector

DB-9

connector

RS-232

transceivers (2)

Ethernet

Transceiver*

25 MHz

Osc.

CAN Transceiver

RS-232 / CAN

Transceiver

ColdFire MCF523X

Peripheral signals

Data [31:0]

Address [23:0]

Control Signals

26-pin Debug Heade

Clocking

circuitry

25 MHz

Osc.

USB 2.0 Host & Device

ADC

ETPU Headers*

SDRAM

16 Mbytes

Flash

2-4 Mbytes

ASRAM

1 Mbyte

(4) 60 pin Daughter Card

expansion connectors

*There is a jumper that allows the option of choosing between 16 eTPU channels and

Ethernet or 32 eTPU channels and no Ethernet

Figure 1-1. M523xEVB Block Diagram

1.1 MCF5235 Microprocessor

The microprocessor used on the EVB is the highly integrated Motorola MCF5235 32-bit ColdFire
variable-length RISC processor. The MCF5235 implements a ColdFire Version 2 core with a maximum
core frequency of 150 MHz and external bus speed of 75 MHz. Features of the MCF5235 include:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 (Dhrystone 2.1)
MIPS @ 150 MHz

• eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with
debug support

• 64 Kbytes of internal SRAM

• External bus speed of one half the CPU operating frequency (75 MHz bus @ 150 MHz core)

• 10/100 Mbps bus-mastering Ethernet controller

• 8 Kbytes of configurable instruction/data cache

• Three universal asynchronous receiver/transmitters (UARTs) with DMA support

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Freescale Semiconductor 1-3

M523xEVB

• Controller area network 2.0B (FlexCAN module)
— Optional second FlexCAN module multiplexed with the third UART

• Inter-integrated circuit (I

2

C) bus controller

• Queued serial peripheral interface (QSPI) module

• Hardware cryptography accelerator (optional)
— Random number generator

— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator

• Four channel 32-bit direct memory access (DMA) controller

• Four channel 32-bit input capture/output compare timers with optional DMA support

• Four channel 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Interrupt controller capable of handling up to 126 interrupt sources

• Clock module with Phase Locked Loop (PLL)

• External bus interface module including a 2-bank synchronous DRAM controller

• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode FLASH
memories

The MCF5235 communicates with external devices over a 32-bit wide data bus, D[31:0]. The MCF5235
can address a 32 bit address range. However, only 24 bits are available on the external bus A[23:0]. There
are internally generated chip selects to allow the full 32 bit address range to be selected. There are regions
that can be decoded to allow supervisor, user, instruction, and data each to have the 32-bit address range.

All the processor's signals are available via daughter card expansion connectors. Refer to the schematic
(Appendix B) for their pin assignments.

The MCF5235 processor has the capability to support both BDM and JTAG. These ports are multiplexed
and can be used with third party tools to allow the user to download code to the board. The board is
configured to boot up in the normal/BDM mode of operation. The BDM signals are available at the port
labeled BDM.

Figure 1-2 shows the MCF5235 processor block diagram.

M523xEVB User’s Manual, Rev. 1.2

1-4 Freescale Semiconductor

(To/From PADI)

(To/From PADI)

(To/From

PAD I)

MUX

DREQ[2:0]

JTAG_EN

FAST

ETHERNET

CONTROLLER

(FEC)

4 CH DMA

DACK[2:0]

(To/From SRAM backdoor)

Arbiter

UART

UART

0

1

DTIM

DTIM

0

V2 ColdFire CPU

BDM

UART

2

1

DIV

INTC0

DTIM

2

2

I

INTC1

C

EMAC

QSPI

DTIM

3

EIM

CHIP

SELECTS

EBI

SDRAMC

MCF5235 Microprocessor

SDRAMC

QSPI

SDA

SCL

UnTXD

UnRXD

UnRTS

UnCTS

TnOUT

TnIN

FEC

PAD I

D[31:0]

A[23:0]

R/

W

CS[3:0]

TA

TSIZ[1:0]

TEA

BS[3:0]

JTAG

TAP

Watchdog

Timer

SKHA

RNGA

MDHA

Cryptography

Modules

64 Kbytes

SRAM

(8Kx16)x4

8 Kbytes

CACHE

(1Kx32)x2

(To/From Arbiter)

PLL

PIT0

CLKGEN

(To/From INTC)

Edge

Port

Figure 1-2. MCF5235 Block Diagram

PORTS

(GPIO)

CIM

PIT1 PIT2 PIT3

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Freescale Semiconductor 1-5

M523xEVB

1.2 System Memory

The following diagram shows the external memory implementation on the EVB.

MPU

Data

Address

Control

Buffers

SDRAM

(16 Mbytes)

Expansion

Connectors

Figure 1-3. External Memory Scheme

NOTE:

ASRAM

(1 Mbyte)

Flash

(512K × 16

or

512K × 32)

The external bus interface signals to the external ASRAM and FLASH (and
USB) are buffered. This is in order not to exceed the maximum output load
capacitance of the microprocessor on the EVB. The signals to the expansion
connectors remain unbuffered to provide a “true” interface to the user.

1.2.1 External Flash

The EVB is fitted with a single 512K × 16 page-mode FLASH memory (U19) giving a total memory space
of 2Mbytes. Alternatively a footprint is available for the EVB user to upgrade this device to a 512K × 32
page-mode FLASH memory (U35), doubling the memory size to 4Mbytes. Either U19 OR U35 should be
fitted on the board - both devices cannot be populated at the same time. Refer to the specific device data
sheet and sample software provided for configuring the FLASH memory.

Users should note that the debug monitor firmware is installed in this flash device. Development tools or
user application programs may erase or corrupt the debug monitor. If the debug monitor becomes
corrupted and it’s operation is desired, the firmware must be programmed into the flash by applying a
development port tool such as BDM. Users should use caution to avoid this situation. The M523xEVB
dBUG debugger/monitor firmware is programmed into the lower sectors of Flash (0xFFE0_0000 to
0xFFE2_FFFF for 2Mbytes of FLASH or 0xFFC0_0000 to 0xFFC2_FFFF for 4 Mbytes of FLASH).

By default with U19 fitted on the EVB, jumper 64 (JP64) provides an alternative hardware mechanism for
write protection.

M523xEVB User’s Manual, Rev. 1.2

1-6 Freescale Semiconductor

System Memory

If the user has replaced U19 with the 32-bit FLASH device (U35), jumper 31 (JP31) has the same
functionality as JP64. U35 also has it’s own hardware write protect pin (C5) which protects the bottom
boot sector when pulled to ground.

1.2.2 SDRAM

The EVB is populated with 16 Mbytes of SDRAM. This is done with two devices (Micron
MT48LC4M16A2TG) each with a 16 bit data bus. Each device is organized as 1 Meg × 16 × 4 banks with
a 16 bit data bus. One device stores the upper 16-bit word and the other the lower 16 bit word of the
MCF523x 32 bit data bus.

1.2.3 ASRAM

The EVB has a footprint for two 512K × 16 Asynchronous SRAM devices (Cypress Semiconductor -
CY7C1041CV3310ZC). These memory devices (U1 and U2) may be populated by the user for
benchmarking purposes.

Also see Section 1.2.5, “M523xEVB Memory Map”.

1.2.4 Internal SRAM

The MCF5235 processor has 64-Kbytes of internal SRAM memory which may be used as data or
instruction memory. This memory is mapped to 0x2000_0000 and configured as data space but is not used
by the dBUG monitor except during system initialization. After system initialization is complete, the
internal memory is available to the user. The memory is relocatable to any 32-Kbyte boundary within the
processor’s four gigabyte address space.

1.2.5 M523xEVB Memory Map

Interface signals to support the interface to external memory and peripheral devices are generated by the
memory controller. The MCF5235 supports 8 external chip selects, CS[1:0] are used with external
memories, CS2 is used for the USB controller and CS[7:3] are easily accessible to users via the daughter
card expansion connectors. CS0 also functions as the global (boot) chip-select for booting out of external
flash.

Since the MCF5235 chip selects are fully programmable, the memory banks may be located at any
64-Kbyte boundary within the processor’s four gigabyte address space.

The default memory map for this board as configured by the Debug Monitor located in the external
FLASH bank can be found in table 1-2. The internal memory space of the MCF5235 is detailed further in
the MCF5235 Reference Manual. Chip Selects 0 and 1 can be changed by user software to map the external
memory in different locations but the chip select configuration such as wait states and transfer
acknowledge for each memory type should be maintained.

Chip Select Usage:

External FLASH Memory CS0
External ASRAM Memory CS1

Table 1-2 shows the M523xEVB memory map.

M523xEVB User’s Manual, Rev. 1.2

Freescale Semiconductor 1-7

M523xEVB

Table 1-2. The M523xEVB Default Memory Map

Address Range Signal and Device

0x0000_0000–0x00FF_FFFF 16 Mbyte SDRAM

0x2000_0000–0x2000_FFFF 64 Kbytes Internal SRAM

0x3000_0000–0x300F_FFFF External ASRAM (not fitted)

0xFFE0_0000–0xFFFF_FFFF
or
0xFFC0_0000–0xFFFF_FFFF

2 Mbytes External Flash
or
4 Mbytes External Flash

1.2.5.1 Reset Vector Mapping

Asserting the reset input signal to the processor causes a reset exception. The reset exception has the
highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.

The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing
by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s interrupt
priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero (0x00000000).
The control registers specifying the operation of any memories (e.g., cache and/or RAM modules)
connected directly to the processor are disabled.

Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword
at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program
counter. After the initial instruction is fetched from memory, program execution begins at the address in
the PC. If an access error or address error occurs before the first instruction is executed, the processor
enters the fault-on-fault halted state.

The Memory that the MCF5235 accesses at address 0 is determined at reset by sampling D[20:19].

Table 1-3. D[20:19] External Boot Chip Select Configuration

D[20:19] Boot Device/Data Port Size

00 External (32-bit)

01 External (16-bit)

10 External (8-bit)

11 External (32-bit)

1.3 Support Logic

1.3.1 Reset Logic

The reset logic provides system initialization. Reset occurs during power-on or via assertion of the signal
RESET which causes the MCF5235 to reset. RESET is triggered by the reset switch (SW6) which resets
the entire processor/system.

dBUG configures the MCF5235 microprocessor internal resources during initialization. The contents of
the exception table are copied to address 0x0000_0000 in the SDRAM. The Software Watchdog Timer is

M523xEVB User’s Manual, Rev. 1.2

1-8 Freescale Semiconductor

Support Logic

disabled, the Bus Monitor is enabled, and the internal timers are placed in a stop condition. A memory map
for the entire board can be seen in Table 1-2.

If the external RCON

pin is asserted (SW7-1 ON) during reset, then various chip functions, including the
reset configuration pin functions after reset, are configured according to the levels driven onto the external
data pins. See tables below on settings for reset configurations.

If the RCON

pin is not asserted (SW7-1 OFF) during reset, the chip configuration and the reset
configuration pin functions after reset are determined by the RCON register or fixed defaults, regardless
of the states of the external data pins.

SW7-1 Reset Configuration

OFF RCON

ON RCON is asserted, Chip functions, including the reset configuration after reset,

SW1-2 JTAG Enable

OFF JTAG interface enabled

ON BDM interface enabled

not asserted, Default Chip configuration or RCON register settings

are configured according to the levels driven onto the external data pins.

Table 1-6. SW7-[4:3] Encoded Clock Mode

SW7-3 SW7-4 Clock Mode

Table 1-4. SW7-1 RCON

Table 1-5. SW7-2 JTAG_EN

OFF OFF External clock mode- (PLL disabled)

OFF ON 1:1 PLL

ON OFF Normal PLL mode with external clock reference

ON ON Normal PLL mode w/crystal oscillator reference

Table 1-7. SW7-5 Chip Configuration Mode

SW7-5 RCON (SW7-1) Mode

OFF ON Reserved

ON ON Master

XOFF Master

Table 1-8. SW7-[7:6] Boot Device

SW7-6 SW7-7 RCON (SW7-1) Boot Device

OFF OFF ON External (32-bit)

OFF ON ON External (8-bit)

ON OFF ON External (16-bit)

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Table 1-8. SW7-[7:6] Boot Device

SW7-6 SW7-7 RCON (SW7-1) Boot Device

ON ON ON External (32-bit)

X X OFF External (32-bit)

Table 1-9. SW7-8 Bus Drive Strength

SW7-8 RCON (SW7-1) Drive Strength

OFF ON Partial Bus Drive

ON ON Full Bus Drive

X OFF Partial Bus Drive

Table 1-10. SW7-[10:9] Address/Chip Select Mode

SW7-9 SW7-10 RCON (SW7-1) Mode

OFF OFF ON PADDR[7:5] = /CS[6:4]

OFF ON ON PADDR[7] = /CS6, PADDR[6:5] = A[22:21]

ON OFF ON PADDR[7:6] = /CS[6:5], PADDR[5] = A21

ON ON ON PADDR[7:5] = A[23:21]

X X OFF PADDR[7:5] = A[23:21]

1.3.2 Clock Circuitry

The are three options to provide the clock to the CPU. These options can be configured by setting
JP[35:37]. See Table 1-11 below.

Table 1-11. M523xEVB Clock Source Selection

JP35 JP36 JP37 Clock Selection

1-2 1-2 ON 25 MHz Oscillator (default setting)

2-3 1-2 ON 25 MHz External Clock

X 2-3 OFF 25 MHz Crystal (not populated)

The 25-MHz oscillator (U23) also feeds the Ethernet chip (U11).

There is also a 12-MHz crystal feeding the USB controller (U33).

1.3.3 Watchdog Timer

The dBUG Firmware does NOT enable the watchdog timer on the MCF5235.

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Support Logic

1.3.4 Exception Sources

The ColdFire® family of processors can receive seven levels of interrupt priorities. When the processor
receives an interrupt which has a higher priority than the current interrupt mask (in the status register), it
will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt
acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the
device should provide the proper vector number to indicate where the service routine for this interrupt level
is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as an
autovector interrupt which directs the processor to a predefined entry in the exception table (refer to the
MCF5235 Reference Manual).

The processor goes to an exception routine via the exception table. This table is stored in the Flash
EEPROM. The address of the table location is stored in the VBR. The dBUG ROM monitor writes a copy
of the exception table into the RAM starting at $00000000. To set an exception vector, the user places the
address of the exception handler in the appropriate vector in the vector table located at $00000000 and then
points the VBR to $00000000.

The MCF5235 microprocessor has seven external interrupt request lines IRQ

[7:1]. The interrupt controller

is capable of providing up to 63 interrupt sources. These sources are:-

• External interrupt signals IRQ

[7:1] (EPORT)

• Software watchdog timer module

• Timer modules

• UART modules 0, 1 and 2

2

•I

C module

• DMA module

• QSPI module

• FEC module

•PIT

• Security module

• FlexCAN0 and FlexCAN1

•eTPU

All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request
must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have
it’s priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers apart from
interrupts 1-7 which have fixed priority already allocated to them.

No interrupt sources should have the same level and priority as another. Programming two interrupt
sources with the same level and priority can result in undefined operation.

The M523xEVB hardware uses IRQ7

to support the ABORT function using the ABORT switch (SW5).
This switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be
aborted without issuing a RESET (refer to Chapter 2 for more information on ABORT). Since the ABORT
switch is not capable of generating a vector in response to a level seven interrupt acknowledge from the
processor, the dBUG programs this interrupt request for autovector mode.

Refer to MCF5235 Reference Manual for more information about the interrupt controller.

1.3.5 TA Generation

The processor starts a bus cycle by asserting CSx with the other control signals. The processor then waits
for a transfer acknowledgment (TA) either from within (Auto acknowledge - AA mode) or from the

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externally addressed device before it can complete the bus cycle. TA is used to indicate the completion of
the bus cycle. It also allows devices with different access times to communicate with the processor
properly asynchronously. The MCF5235 processor, as part of the chip-select logic, has a built-in
mechanism to generate TA for all external devices which do not have the capability to generate this signal.
For example the Flash ROM cannot generate a TA signal. The chip-select logic is programmed by the
dBUG ROM Monitor to generate TA internally after a pre-programmed number of wait states. In order to
support future expansion of the M523xEVB, the TA input of the processor is also connected to the
Processor Expansion Bus (J9, pin 44). This allows any expansion boards to assert this line to provide a TA
signal to the processor. On the expansion boards this signal should be generated through an open collector
buffer with no pull-up resistor; a pull-up resistor is included on this board. All TA signals from expansion
boards should be connected to this line.

1.3.6 User’s Program

JP64 on the 16Mbit FLASH (U19) or JP31 if using 32Mbit FLASH (U35) allows users to test code from
boot/POR without having to overwrite the ROM Monitor.

When the jumper is set between pins 1 and 2, the behavior of the system is normal, dBUG boots and then
runs from 0xFFE00000 (0xFFC00000). When the jumper is set between pins 2 and 3, the board boots from
the top half of the FLASH (0xFFF00000).

Procedure:

1. Compile and link as though the code was to be placed at the base of the flash.

2. Set up the jumper JP64 (JP31) for Normal operation, pin1 connected to pin 2.

3. Download to SDRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM via
a wiggler cable, download first, then start ROM Monitor by pointing the program counter (PC) to
0xFFE00400(0xFFC00400) and run.)

4. In the ROM Monitor, execute the 'FL write <dest> <src> <bytes>' command.

5. Move jumper JP64 (JP31) to pin 2 connected to pin 3 and push the reset button (SW6). User code
should now be running from reset/POR.

1.4 Communication Ports

The EVB provides external communication interfaces for two UART serial ports, a UART/FlexCAN1
port, FlexCan0 port, QSPI, I2C port, 10/100T ethernet port, eTPU port (including UNI3 and HS/ENCO
connectors for auxiliary motor control cards), USB Host port, USB Device port, and BDM/JTAG port.

1.4.1 UART0 and UART1 Ports

The MCF5235 device has three built in UARTs, each with its own software programmable baud rate
generator. Two of these UART interfaces are brought out to RS232 transceivers. One channel is the ROM
Monitor to Terminal output and the other is available to the user. The ROM Monitor programs the interrupt
level for UART0 to Level 3, priority 2 and autovector mode of operation. The interrupt level for UART1
is programmed to Level 3, priority 1 and autovector mode of operation. The signals from these channels
are available on expansion connectors J7 and J8. The signals of UART0 and UART1 are passed through
the RS-232 transceivers (U30) & (U31) and are available on DB-9 connectors (P4) and (P5).

Refer to the MCF5235 Reference Manual for programming the UART’s and their register maps.

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Communication Ports

1.4.2 UART2/FlexCAN1 Port

The third UART on the MCF5235 is multiplexed with the second FlexCAN (FlexCAN1) module. As these
two modules are multiplexed such that the user has access to one or the other, the functionality on the EVB
is jumper selectable. Table 1-12 shows the jumper configuration to activate UART2 or FlexCAN1.

Table 1-12. UART2/FlexCAN1 Jumper Configuration

Jumper UART2 Setting FlexCAN1 Setting

JP7 1-2 2-3

JP12 1-2 2-3

JP25 2-3 X

JP26 2-3 X

JP50 2-3 1-2

JP51 2-3 1-2

JP52 2-3 1-2

The signals of UART2 are passed through RS-232 transceiver U32 and are jumper selectable (for settings
see Table 1-12) on DB-9 connector P6.

The CAN1TX and CAN1RX signals from FlexCAN1 are brought out to a 3.3-V CAN transceiver (Texas
Instruments - SN65HVD230D) and are jumper selectable (for settings see Table 1-12) on DB-9 connector
P6. Jumpers JP3 and JP4 control the CAN hardware configuration.

Table 1-13. FlexCAN1 Jumper Configuration

Jumper Function ON OFF

JP3 Transceiver mode Standby High Speed (No Slope

Control)

JP4 CAN Termination Terminating resistor

between CANL and CANH

No terminating resistor

1.4.3 FlexCAN0 Port

The EVB provides 1 dedicated CAN transceiver. The CAN0TX and CAN0RX signals are brought out to
a 3.3V CAN transceiver (Texas Instruments - SN65HVD230D). Jumper JP1 and JP2 control the CAN
hardware configuration.

Table 1-14. FlexCAN0 Jumper Configuration

Jumper Function ON OFF

JP1 Transceiver mode Standby High Speed (No Slope

Control)

JP2 CAN Termination Terminating resistor

between CANL and CANH

No terminating resistor

The CANL and CANH signals are brought out from the CAN transceiver to a female DB-9 connector (P1)
in the configuration below.

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Table 1-15. CAN Bus Connector Pinout

DB-9 pin Signal

1,4-6,7-9 Not Connected

2CANL

3 Ground

7CANH

1.4.4 10/100T Ethernet Port

The MCF5235 microprocessor populated on the EVB is a superset device of the MCF523x family. The
upper 16 eTPU channels are multiplexed with the ethernet port giving the EVB user the choice of utilizing
either the full 32-channels of eTPU or 16-channels of eTPU with the Fast Ethernet Controller (FEC)
activated. Pin M4 on the MCF5235 configures the internal functionality of these 16 pins. If the user is
using the FEC, pin M4 must be pulled low by setting SW7-11 to the ON position.

These 16 pins are also jumper selectable between the eTPU and the FEC in order to isolate the external
circuitry required to implement the functionality of these modules. Table 1-16 lists the appropriate jumper
settings to enable eTPU or FEC functionality on these pins.

The MCF5235 device performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and
channel interface functions. The MCF5235 Ethernet Controller requires an external interface adaptor and
transceiver function to complete the interface to the ethernet media. The MCF5235 Ethernet module also
features an integrated fast (100baseT) Ethernet media access controller (MAC).

The Fast Ethernet controller (FEC) incorporates the following features:

• Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)

• IEEE 802.3 full duplex flow control

• Programmable max frame length supports IEEE 802.1 VLAN tags and priority

• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of
50 MHz

• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of
25 MHz

• Retransmission from transmit FIFO following a collision (no processor bus utilization)

• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)

• Address recognition
— Frames with broadcast address may be always accepted or always rejected

— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode

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Communication Ports

For more details see the MCF523x Reference Manual. The on board ROM MONITOR is programmed to
allow a user to download files from a network to memory in different formats. The current compiler
formats supported are S-Record, COFF, ELF or Image.

Table 1-16. Ethernet/eTPU Jumper Configuration

Jumper Pin

JP5 D5 2-3 ERXER 1-2 23

JP9 C5 2-3 ETXCLK 1-2 22

JP10 B5 2-3 ETXD2 1-2 18

JP11 A5 2-3 ETXD1 1-2 17

JP13 D6 2-3 ETXEN 1-2 21

JP14 C6 2-3 ETXER 1-2 20

JP15 B6 2-3 ETXD3 1-2 19

JP16 C4 2-3 ERXD0 1-2 24

JP17 B7 2-3 ETXD0 1-2 16

JP18 C3 2-3 ERXD1 1-2 25

JP19 D4 2-3 ERXD2 1-2 26

JP20 D3 2-3 ERXD3 1-2 27

JP21 E3 2-3 ERXCLK 1-2 29

JP22 E4 2-3 ERXDV 1-2 28

JP23 F3 2-3 ECOL 1-2 31

JP24 F4 2-3 ECRS 1-2 30

Ethernet

Setting

Ethernet

Signal

eTPU

Setting

eTPU

Channel

1.4.5 eTPU

The eTPU is an intelligent programmable I/O controller with its own core and memory system, allowing
it to perform complex timing and I/O management independently of the CPU. The eTPU is essentially a
co-processor designed for timing control, I/O handling, serial communications, motor control. and engine
control applications and accesses data without the host CPU’s intervention. Consequently, the host CPU
setup and service times for each timer event are minimized or eliminated.

The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500
products. Enhancements of the eTPU include a more powerful processor which handles high-level C code
efficiently and allows for more functionality and increased performance. Although there is no
compatibility at microcode level, the eTPU maintains several features of older TPU versions and is
conceptually almost identical. The eTPU library is a superset of the standard TPU library functions
modified to take advantage of enhancements in the eTPU. These, along with a C compiler, make it
relatively easy to port older applications. By providing source code for the Motorola library, it is possible
for the eTPU to support the users own function development.

The eTPU has up to 32 timer channels in addition to having 6 Kbytes of code memory and 1.5 Kbytes of
data memory that stores software modules downloaded at boot time and that can be mixed and matched as
required for any specific application.

As mentioned in Section 1.4.4, “10/100T Ethernet Port,” the upper 16-channels of the eTPU are
multiplexed with the Fast Ethernet Controller.

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Refer to Table 1-16 to set the appropriate jumpers to enable 16 or 32-channels.

To configure the device to operate with the top 16-channels of the eTPU activated, pin M4 must be pulled
high by setting SW7-11 to the OFF position.

All 32 eTPU channels are available on a 0.1” 2x20 Molex connector providing easy access to the eTPU
for the EVB user.

Table 1-17. eTPU Header Pin Assignment

Pin eTPU Signal Pin eTPU Signal

1 +3.3V 2 +5V

3 TPUCH16 4 UTPUODIS

5 TPUCH17 6 LTPUODIS

7TPUCH18 8TPUCH0

9 TPUCH19 10 TPUCH1

11 TPUCH20 12 TPUCH2

13 TPUCH21 14 TPUCH3

15 TPUCH22 16 TPUCH4

17 TPUCH23 18 TPUCH5

19 TPUCH24 20 TPUCH6

21 TPUCH25 22 TPUCH7

23 TPUCH26 24 TPUCH8

25 TPUCH27 26 TPUCH9

27 TPUCH28 28 TPUCH10

29 TPUCH29 30 TPUCH11

31 TPUCH30 32 TPUCH12

33 TPUCH31 34 TPUCH13

35 GND 36 TPUCH14

37 TCRCLK 38 TPUCH15

39 GND 40 GND

There is a UNI3 connector and HS/ENCO connector on the EVB for connection to an auxiliary card.

The auxiliary card is intended for evaluation of the eTPU functionality.

1.4.6 BDM/JTAG Port

The MCF5235 processor has a Background Debug Mode (BDM) port, which supports Real-Time Trace
and Real-Time Debug. The signals which are necessary for debug are available at connector (J1).
Figure 1-4 shows the (J1) Connector pin assignment.

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Communication Ports

DEVELOPER RESERVED

GND

GND

RESET

I/O or Pad Voltage

GND

PST2

PST0

DDATA2

DDATA0

MOTOROLA RESERVED

GND

Core Voltage

11

13

15

17

19

21

23

25

1

3

5

7

9

2

4

6

8

10

12

14

16

18

20

22

24

26

BKPT

DSCLK

DEVELOPER RESERVED

DSI

DSO

PST3

PST1

DDATA3

DDATA1

GND

MOTOROLA RESERVED

PSTCLK

TA

Figure 1-4. J1- BDM Connector Pin Assignment

The BDM connector can also be used to interface to JTAG signals. On reset, the JTAG_EN signal selects
between multiplexed debug module and JTAG signals. See Table 1-5.

1.4.7 I2C

The MCF5235’s I2C module includes the following features:

2

• Compatibility with the I

• Multi master operation

• Software programmable for one of 50 different clock frequencies

• Software selectable acknowledge bit

• Interrupt driven byte by byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Start and stop signal generation and detection

• Repeated start signal generation

• Acknowledge bit generation and detection

• Bus busy detection

Please see the MCF523x Reference Manual for more detail. The I
are brought out to expansion connector (J13).

2

The I

C functionality of the MCF5235 is multiplexed on the same pins as the QSPI. Jumpers JP6 and JP8
are used to connect/disconnect the I2C signals, SDA and SCL. To enable I2C JP6 and JP8 should be set
between pins 2 and 3.

C bus standard version 2.1

2

C signals from the MCF5235 device

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1.4.8 QSPI

The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued
transfer capability. It will support up to 16 stacked transfers at one time, minimizing CPU intervention
between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.

Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module)
implemented in the MC68332 processor.

• Programmable queue to support up to 16 transfers without user intervention

• Supports transfer sizes of 8 to 16 bits in 1-bit increments

• Four peripheral chip-select lines for control of up to 15 devices

• Baud rates from 147.1-Kbps to 18.75-Mbps at 75 MHz.

• Programmable delays before and after transfers

• Programmable QSPI clock phase and polarity

• Supports wrap-around mode for continuous transfers

Please see the MCF523x Reference Manual for more detail. The QSPI signals from the MCF5235 device
are brought out to expansion connector (J12).

Some of the QSPI signals are multiplexed with the I
and 2 to enable the QSPI module.

The EVB features an A to D converter (ADC) interfaced to the CPU via the QSPI. The ADC uses QSPI
chip select 0. This chip select has a jumper that can be removed if the EVB user is not using the ADC and
wishes to connect QSPI_CS0 to an alternative device.

2

C module. JP6 and JP8 should be set between pins 1

1.4.9 USB Host and Device

The EVB features a USB controller interfaced externally to the MCF5235 via the DMA and external bus
modules. The USB controller can be configured to run in Host or Device mode.

There is a series “A” connector (Host) and a series “B” connector (Device) populated on the EVB. Either
one or the other can be used depending on whether the USB controller is configured to run in Host or
Device mode. JP56 must be set between pins 2 and 3 if the controller is configured in Host mode and
between pin 1 and 2 if the controller is configured in Device mode.

The USB controller also has On-The-Go (OTG) functionality. There is a footprint on the EVB for an OTG
Mini-AB connector if the user wants to utilize USB OTG. If using OTG JP55 must be fitted.

For more details see the Philips Semiconductor datasheet for the ISP1362 USB OTG controller.

There are a series of jumpers connected to the USB controller that allow the user to disconnect the DMA
and interrupt signals between the CPU and the USB controller if the USB controller is not in use. This
gives the user access to the DMA timer module channels 1 and 2 and an extra interrupt signal if they do
not require USB functionality. Table 1-18 details these jumper settings.

Table 1-18. USB DMA Enable and Disable Settings

Jumper Functionality when Jumper is Fitted Functionality when Jumper is NOT Fitted

JP57 USB DMA request signal DMA Timer 1 input enabled

JP58 USB DMA request signal DMA Timer 2 input enabled

JP59 USB DMA acknowledge signal DMA Timer 2 output enabled

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Connectors and User Components

Table 1-18. USB DMA Enable and Disable Settings

Jumper Functionality when Jumper is Fitted Functionality when Jumper is NOT Fitted

JP60 USB DMA acknowledge signal DMA Timer 1 output enabled

JP61 DACK1 not in use - pulled high DMA acknowledge 1 enabled

JP62 Interrupt 4 enabled for USB Interrupt 4 disabled from USB

JP63 DACK2 not in use - pulled high DMA acknowledge 2 enabled

1.5 Connectors and User Components

1.5.1 Daughter Card Expansion Connectors

Four, 60-way SMT connectors (J7, J8, J9 and J10) provide access to all MCF5235 signals. These
connectors are ideal for interfacing to a custom daughter card or for simple probing of processor signals.
Below is a pinout description of these connectors.

Table 1 - 1 9 . J 7

Pin Signal Pin Signal

1+5V 2+5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7GND 8GND

9 TPUCH24 10 TPUCH6

11 TPUCH17 12 TPUCH4

13 TPUCH18 14 TPUCH5

15 TPUCH22 16 TPUCH2

17 TPUCH23 18 TPUCH3

19 TPUCH19 20 TPUCH1

21 TPUCH20 22 TPUCH0

23 TPUCH21 24 GND

25 TPUCH16 26 EMDIO

27 U2CTS

29 I2C_SCL 30 I2C_SDA

31 QSPI_SCK 32 QSPI_DIN

33 BS3 34 QSPI_DOUT

28 EMDC

35 BS2 36 QSPI_PCS0

37 BS1

39 BS0 40 CAN1RX

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Table 1-19. J7 (continued)

Pin Signal Pin Signal

41 U2RTS

43 QSPI_PCS1 44 U1CTS

45 U1RTS 46 CAN1TX

47 U1RXD 48 U2TXD

49 U1TXD 50 CS2

51 CS3 52 CS7

53 CS6 54 CS5

55 CS1 56 CS0

57 CS4 58 A23

59 GND 60 GND

42 U2RXD

Table 1 - 2 0 . J 8

Pin Signal Pin Signal

1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 TPUCH8 6 TPUCH7

7 TPUCH10 8 TPUCH9

9 TPUCH25 10 TPUCH12

11 TPUCH27 12 TPUCH11

13 TPUCH26 14 TPUCH14

15 TPUCH29 16 TPUCH13

17 TPUCH28 18 TCRCLK

19 TPUCH31 20 TPUCH15

21 TPUCH30 22 GND

23 GND 24 U0CTS

25 U0RXD 26 DTOUT0

27 DTIN0 28 U0TXD

29 U0RTS 30 GND

31 CLKMOD0 32 +3.3V

33 CLKMOD1 34 GND

35 GND 36 D28

37 D30 38 D29

39 D31 40 D24

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