Freescale MCF52211 DATA SHEET

Freescale Semiconductor

LQFP–64
10 mm x 10 mm

MAPBGA–81
10 mm x 10 mm

LQFP–100
14 mm x 14 mm

QFN–64
9mmx9mm

Data Sheet

MCF52211 ColdFire Microcontroller

Supports MCF52210 / 52211 /
52212 / 52213

The MCF52211 is a member of the ColdFire® family of
reduced instruction set computing (RISC) microprocessors.

This document provides an overview of the 32-bit MCF52211
microcontroller, focusing on its highly integrated and diverse
feature set.

This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
128 Kbytes of flash memory and 16 Kbytes of static random
access memory (SRAM). On-chip modules include:

• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with Multiply
Accumulate (MAC) Unit and hardware divider

• Universal Serial Bus On-The-Go (USBOTG)

• USB Transceiver

• Up to three universal asynchronous/synchronous
receiver/transmitters (UARTs)

• Two inter-integrated circuit (I2C™) bus interface modules

• Queued serial peripheral interface (QSPI) module

• Eight-channel 12-bit fast analog-to-digital converter
(ADC)

• Four 32-bit input capture/output compare timers with
DMA support (DTIM)

• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM), and pulse accumulation

• Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer

• Two 16-bit periodic interrupt timers (PITs)

• Real-time clock (RTC) module

• Programmable software watchdog timer

• Interrupt controller capable of handling 57 sources

• Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)

• Test access/debug port (JTAG, BDM)

Document Number: MCF52211

Rev. 1, 09/2007

MCF52211

This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Table of Contents

1 MCF52211 Family Configurations . . . . . . . . . . . . . . . . . . . . . .3

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.3 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .22

1.4 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .23

1.6 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .23

1.7 USB On-the-Go. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2

1.8 I

C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1.9 UART Module Signals. . . . . . . . . . . . . . . . . . . . . . . . . .24

1.10 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.11 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.12 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .25

1.13 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . . 25

1.14 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .25

1.15 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .26

1.16 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .27

2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .30

2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .31

2.5 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . 32

2.7 Clock Source Electrical Specifications . . . . . . . . . . . . .33

2.8 USB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

2.9 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .34

2.10 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

2

2.11 I

C Input/Output Timing Specifications . . . . . . . . . . . . .36

2.12 Analog-to-Digital Converter (ADC) Parameters . . . . . .37

2.13 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . . .38

2.14 DMA Timers Timing Specifications . . . . . . . . . . . . . . . . 39

2.15 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .39

2.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . .40

2.17 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .42

3 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .44

3.1 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .44

3.2 64 QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.3 81 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . .51

3.4 100-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .53

4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

List of Figures

Figure 1.MCF52211 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2.100 LQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . 14

Figure 3.81 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . . 15

Figure 4.64 LQFP and 64 QFN Pin Assignments . . . . . . . . . . . 16

Figure 5.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 6.RSTI and Configuration Override Timing . . . . . . . . . . 35

Figure 7.I

2

C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 37

Figure 8.Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . . 38

Figure 9.QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 10.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 11.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 41

Figure 12.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . . 42

Figure 15.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 43

List of Tables

Table 1. MCF52211 Family Configurations . . . . . . . . . . . . . . . . . 3

Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 12

Table 3. Pin Functions by Primary and Alternate Purpose . . . . 17

Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Mode Selection Signals . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 23

Table 9. Queued Serial Peripheral Interface (QSPI) Signals. . . 23
Table 10.I

Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15.PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 26

Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19.Absolute Maximum Ratings, . . . . . . . . . . . . . . . . . . . 28

Table 20.Current Consumption in Low-Power Mode
Table 21.Typical Active Current Consumption Specifications. . . 29

Table 22.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23.SGFM Flash Program and Erase Characteristics . . . . 31

Table 24.SGFM Flash Module Life Characteristics . . . . . . . . . . 32

Table 25.ESD Protection Characteristics, . . . . . . . . . . . . . . . . . 32

Table 26.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32

Table 27.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 33

Table 28.USB Operation Specifications . . . . . . . . . . . . . . . . . . . 34

Table 29.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 30.Reset and Configuration Override Timing . . . . . . . . . . 35

Table 31.I

Table 32.I

Table 33.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 34.Timer Module AC Timing Specifications . . . . . . . . . . . 39

Table 35.QSPI Modules AC Timing Specifications. . . . . . . . . . . 39

Table 36.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40

Table 37.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 42

Table 38.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2

C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

,

. . . . . . . . . 29

2

C Input Timing Specifications between I2C_SCL

and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2

C Output Timing Specifications between I2C_SCL

and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor2

1 MCF52211 Family Configurations

Table 1. MCF52211 Family Configurations

Module 52210 52211 52212 52213

MCF52211 Family Configurations

Version 2 ColdFire Core with MAC (Multiply-Accumulate
Unit)

System Clock 66, 80 MHz 50 MHz

Performance (Dhrystone 2.1 MIPS) up to 76 up to 46

Flash / Static RAM (SRAM) 64/16 Kbytes 128/16 Kbytes 64/8 Kbytes 128/8 Kbytes

Interrupt Controller (INTC)

Fast Analog-to-Digital Converter (ADC)

USB On-The-Go (USB OTG)

Four-channel Direct-Memory Access (DMA)

Software Watchdog Timer (WDT)

Secondary Watchdog Timer

Two-channel Periodic Interrupt Timer (PIT) 2 2 2 2

Four-Channel General Purpose Timer (GPT)

32-bit DMA Timers 4 4 4 4

QSPI

UART(s) 2 3 2 2

2

I

C2222

Eight/Four-channel 8/16-bit PWM Timer

••••

••••

••••

••••

••••

••••

••••

••••

••••

••••

General Purpose I/O Module (GPIO)

Chip Configuration and Reset Controller Module

Background Debug Mode (BDM)

JTAG - IEEE 1149.1 Test Access Port

Package 64 LQFP/QFN

1

The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller

packages.

1

••••

••••

••••

••••

81 MAPBGA

64 LQFP/QFN

81 MAPBGA

100 LQFP

64 LQFP 64 LQFP

Figure 1 shows a top-level block diagram of the MCF52211. Package options for this family are described later in this

document.

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 3

Arbiter

Interrupt

Controller

UART

0

QSPI

UART

1

UART

2

I2C

V2 ColdFire CPU

4 CH

JTAG

TAP

16 Kbytes

SRAM

(2K×32)×2

128 Kbytes

Flash

(16K×16)×4

PORTS

CIM_IBO

RSTI
RSTO

ADC

AN[7:0]

PLL OCO

CLKGEN

Edge

Port

TIM

EXTAL XTAL CLKOUT

PIT0 PIT1 PWM

IRQ[7:1]

PMM

V

STBY

PADI – Pin Muxing

AN

Slave Mode Access

(CIM_IBO/EzPort)

M3

TMS

TDI

TDO
TRST
TCLK

JTAG_EN

DMA

M2 M0

Watch

Dog

TMR

0

RTC

TMR

1

TMR

2

TMR

3

I

2

C

DDATA

QSPI
SDAn
SCLn
UTXDn
URXDn
URTS

n

UCTSn
PWMn
DTINn/DTOUTn
GPT
RCON_B
ALLPST
PST

BDM

PORT

IPS Bus Gasket

Watchdog

CIM_IBO

CFM

V

PP

CLKMOD

GPT[3:0]

Backup

USB

On-The-Go

USB TCVR

USBD+

USBD-

M1

MCF52211 Family Configurations

Figure 1. MCF52211 Block Diagram

1.1 Features

This document contains information on a new product under development. Freescale reserves the right to change or discontinue
this product without notice. Specifications and information herein are subject to change without not ice.

1.1.1 Feature Overview

The MCF52211 family includes the following features:

• Version 2 ColdFire variable-length RISC processor core

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor4

MCF52211 Family Configurations

— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— 40 MHz and 33 MHz off-platform bus frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions

for improved bit processing (ISA_A+)

— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 → 32 or 32×32 → 32 operations

• System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or

2-level trigger

• On-chi p memo r ies
— Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power

supply support

— Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses

• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption

• Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
— Full-speed / low-speed host controller
— USB 1.1 and 2.0 compliant full-speed / low speed device controller
— 16 bidirectional end points
— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic

• Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers

•Two I

2

C modules
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I

2

C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level

• Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 5

MCF52211 Family Configurations

— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers

• Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 μs conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
— Unused analog channels can be used as digital I/O

• Four 32-bit timers with DMA support
— 12.5 ns resolution at 80 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare

• Four-channel general purpose timer
— 16-bit architecture
— Programmable prescaler
— Output pulse-widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel

• Pulse-width modulation timer
— Support for PCM mode (resulting in superior signal quality compared to conventional PWM)
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached

(PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown

• Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down

• Real-Time Clock (RTC)
— Maintains system time-of-day clock
— Provides stopwatch and alarm interrupt functions

• Software watchdog timer

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor6

MCF52211 Family Configurations

— 32-bit counter
— Low-power mode support

• Backup watchdog timer (BWT)
— Independent timer that can be used to help software recover from runaway code
— 16-bit counter
— Low-power mode support

• Clock generation features
— One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference options
— Trimmed relaxation oscillator
— Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable from 1 to 8
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported

n

—2

(n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation

• Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes

• DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4×32-bit)

burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

• Reset
— Separate reset in and reset out signals
— Seven sources of reset:

– Power-on reset (POR)
– External
–Software
– Watchdog
– Loss of clock / loss of lock
– Low-voltage detection (LVD)
–JTAG

— Status flag indication of source of last reset

• Chip integration module (CIM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 7

MCF52211 Family Configurations

— Unique part identification number and part revision number

• General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO

• JTAG support for system level board testing

1.1.2 V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer . The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack
pointer register and four new instructions to assist in bit processing. Additionally, the core includes the multiply-accumulate
(MAC) unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for
16×16 bit operations, with support for one 32-bit accumulator. Supported operands in clude 16- and 32-bit signed and unsigned
integers, signed fractional operands, and a complete set of instructions to process these data types. The MAC provides support
for execution of DSP operations within the context of a single processor at a minimal hardware cost.

1.1.3 Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided
on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit
emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF52211 implements revision B+ of the ColdFire Debug Architecture.

The MCF52211’s interrupt servi cing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interr

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor8

MCF52211 Family Configurations

links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device
system logic.

The MCF52211 implementation can:

• Perform boundary-scan operations to test circuit board electrical continuity

• Sample MCF52211 system pins during operation and transparently shift out the result in the boundary scan register

• Bypass the MCF52211 for a given circuit board test by effectively reducing the boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

1.1.5 On-Chip Memories

1.1.5.1 SRAM

The dual-ported SRAM module provides a general-purpose 8- or 16-Kbyte memory block that the ColdFire core can access in
a single cycle. The location of the memory block can be set to any 8- or 16-Kbyte boundary within the 4-Gbyte address space.
This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or
memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing
applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to
maximize system performance.

1.1.5.2 Flash Memory

The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local
bus. The CFM is constructed with up to four banks of 16-Kbyte×16-bit flash memory arrays to generate up to 128 Kbytes of
32-bit flash memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory . The
flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without
requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory
controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory
is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also
be programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read,
erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.

1.1.6 Power Management

The MCF52211 incorporates several low-power modes of operation entered under program control and exited by several
external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the
supply voltage rises. The low voltage detector (L VD) monitors the supply voltage and is configurable to force a reset or interrupt
condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the
chip falls below the standby battery voltage.

1.1.7 USB On-The-Go Controller

The MCF52211 includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller . USB is a popular standard for
connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs.
The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly
to each other without the need for a PC. The dual-mode controller on the MCF52211 can act as a USB OTG host and as a USB
device. It also supports full-speed and low-speed modes.

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 9

MCF52211 Family Configurations

1.1.8 UARTs

The MCF52211 has three full-duplex UARTs that function independently. The three UAR Ts can be clocked by the system bus
clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital
I/O functions.

1.1.9 I2C Bus

The MCF52211 includes two I2C modules. The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient
method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices.

1.1.10 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.
It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.

1.1.11 Fast ADC

The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding
separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.

The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly
until manually stopped.

The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight
channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a
scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This
configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low
threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.

1.1.12 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the MCF52211.
Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured
to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected,
it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual
timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.
Timer events may optionally cause interrupt requests or DMA transfers.

1.1.13 General Purpose Timer (GPT)

The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a
seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare.
Additionally , channel th ree, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
The input capture and output compare functions allow simultaneous input waveform measurements and output waveform
generation. The input capture function can capture the time of a selected transition edge. The output compare function can

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor10

MCF52211 Family Configurations

generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a
gated time accumulator.

1.1.14 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal
processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running
down-counter.

1.1.15 Real-Time Clock (RTC)

The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm , and interrupt
functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions
along with an alarm interrupt.

1.1.16 Pulse-Width Modulation (PWM) Timers

The MCF52211 has an 8-channel, 8-bit PWM timer. Each channel has a programmable peri od a nd duty cycle as well as a
dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates
from 0% to 100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a
conventional PWM. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center
aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can
be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4
8-/16-bit channels.

1.1.17 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running
down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

1.1.18 Backup Watchdog Timer

The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from
runaway code. This timer is a free-running down-counter that gene

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 11

MCF52211 Family Configurations

1.1.21 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor
intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered
by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.

1.1.22 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what
caused the last reset. There are seven sources of reset:

• External reset input

• Power-on reset (POR)

• Watchdog timer

• Phase locked-loop (PLL) loss of lock / loss of clock

•Software

• Low-voltage detector (LVD)

•JTAG

Control of the L VD and its associated reset and interrupt are managed by the reset controller . Other registers provide status flags
indicating the last source of reset and a control bit for software assertion of the RSTO

pin.

1.1.23 GPIO

Nearly all pins on the MCF52211 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use
all eight bits. Each port has registers that configure, monitor, and control the port pins.

1.1.24 Part Numbers and Packaging

This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office for up-to-date RoHS
information.

Table 2. Orderable Part Number Summary

Freescale Part

Number

MCF52210CAE66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 64 LQFP -40 to +85

MCF52210CEP66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 64 QFN -40 to +85

MCF52210CVM66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 81 MAPBGA -40 to +85

MCF52210CVM80 MCF52210 Microcontroller, 2 UARTs 80 64 / 16 81 MAPBGA -40 to +85

MCF52211CAE66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 64 LQFP -40 to +85

MCF52211CAF80 MCF52211 Microcontroller, 3 UARTs 80 128 / 16 100 LQFP -40 to +85

MCF52211CEP66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 64 QFN -40 to +85

MCF52211CVM66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 81 MAPBGA -40 to +85

Description

Speed

(MHz)

Flash/SRAM

(Kbytes)

Package

Tem p rang e

(°C)

MCF52211CVM80 MCF52211 Microcontroller, 3 UARTs 80 128 / 16 81 MAPBGA -40 to +85

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor12

MCF52211 Family Configurations

Table 2. Orderable Part Number Summary (continued)

Freescale Part

Number

MCF52212CAE50 MCF52212 Microcontroller, 2 UARTs 50 64 / 8 64 LQFP -40 to +85

MCF52212AE50 MCF52212 Microcontroller, 2 UARTs 50 64 / 8 64 LQFP 0 to +70

MCF52213CAE50 MCF52213 Microcontroller, 2 UARTs 50 128 / 8 64 LQFP -40 to +85

MCF52213AE50 MCF52213 Microcontroller, 2 UARTs 50 128 / 8 64 LQFP 0 to +70

Description

Speed

(MHz)

Flash/SRAM

(Kbytes)

Package

Tem p rang e

(°C)

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 13

MCF52211 Family Configurations

AN5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

V

DD

V

DD

V

SS

URTS1

TEST

UCTS0

UTXD0
URTS0

SCL

SDA
QSPI_CS3
QSPI_CS2

V

DD

V

SS

QSPI-DIN

QSPI_DOUT

QSPI_CLK
QSPI_CS1
QSPI_CS0

RCON

V

DD

V

DD

V

SS

100 LQFP

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

V

SS

V

DDPLL

EXTAL
XTAL
V

SSPLL

PST3
PST2
V

DD

V

SS

PST1
PST0

PSTCLK

GPT3
V

DD

USB

USB_DM
USB_DP

V

SS

USB

GPT2
V

DD

V

SS

V

STBY

AN6
AN7

100

9998979695949392919089888786858483828180797877

76

URXD1

UTXD1

UCTS1

RSTO

RSTI

IRQ7

IRQ6

VDDVSSIRQ5

IRQ4

IRQ3

IRQ2

IRQ1

ALLPST

DDATA3

DDATA2

VSSVDDDSO

DSI

DDATA1

DDATA0

BKPT

26272829303132333435363738394041424344454647484950

JTAG_EN

UCTS2

URXD2

UTXD2

URTS2

DTIN2

DTIN3

GPT1

V

DD

V

SS

DTIN0

DTIN1

GPT0

CLKMOD1

CLKMOD0

V

DD

V

SS

AN0

AN1

AN2

AN3

V

SSA

V

RL

V

RH

V

DDA

V

SS

URXD0

AN4

DSCLK

Figure 2 shows the pinout configuration for the 100 LQFP.

Figure 2. 100 LQFP Pin Assignments

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor14

Figure 3 shows the pinout configuration for the 81 MAPBGA.

V

SS

UTXD1 RSTI IRQ5 IRQ3 ALLPST TDO TMS V

SS

A

123456789

URTS1 URXD1 RSTO IRQ6 IRQ2 TRST TDI VDDPLL EXTALB

UCTS0 TEST UCTS1 IRQ7 IRQ4 IRQ1 TCLK VSSPLL XTALC

URXD0 UTXD0 URTS0 V

SS

V

DD

V

SS

GPT3 VDDUSB USB_DMD

SCL SDA V

DD

V

DD

V

DD

V

DD

V

DD

GPT2 USB_DPE

QSPI_CS3 QSPI_CS2 QSPI_DIN V

SS

V

DD

V

SS

VSSUSB V

STBY

AN4F

QSPI_DOUT QSPI_CLK RCON DTIN1 CLKMOD0 AN2 AN3 AN5 AN6G

QSPI_CS0 QSPI_CS1 DTIN3 DTIN0 CLKMOD1 AN1 V

SSA

V

DDA

AN7H

V

SS

JTAG_EN DTIN2 GPT1 GPT0 AN0 V

RL

V

RH

V

SSA

J

Figure 3. 81 MAPBGA Pin Assignments

MCF52211 Family Configurations

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor 15

MCF52211 Family Configurations

Figure 4 shows the pinout configuration for the 64 LQFP and 64 QFN.

Figure 4. 64 LQFP and 64 QFN Pin Assignments

Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin.

MCF52211 ColdFire Microcontroller, Rev. 1

Freescale Semiconductor16

Freescale Semiconductor 17

Table 3. Pin Functions by Primary and Alternate Purpose

Pin

Group

Primary

Function

Secondary

Function

Ter tia r y

Function

Quaternary

Function

Drive

Strength /

Control

1

Slew Rate /

Control

1

Pull-up /

Pull-down

2

100 LQFP

Pin on

Pin on 81
MAPBGA

Pin on 64

LQFP/QFN

ADC AN7 — — GPIO Low FAST — 51 H9 33

AN6 — — GPIO Low FAST — 52 G9 34

AN5 — — GPIO Low FAST — 53 G8 35

AN4 — — GPIO Low FAST — 54 F9 36

AN3 — — GPIO Low FAST — 46 G7 28

MCF52211 ColdFire Microcontroller, Rev. 1

AN2 — — GPIO Low FAST — 45 G6 27

AN1 — — GPIO Low FAST — 44 H6 26

AN0 — — GPIO Low FAST — 43 J6 25

SYNCA

SYNCB

3

3

— — —N/AN/A————

— — —N/AN/A————

VDDA — — — N/A N/A — 50 H8 32

VSSA — — — N/A N/A — 47 H7, J9 29

VRH — — — N/A N/A — 49 J8 31

VRL — — — N/A N/A — 48 J7 30

Clock

Generation

EXTAL — — — N/A N/A — 73 B9 47

XTAL — — — N/A N/A — 72 C9 46

VDDPLL — — — N/A N/A — 74 B8 48

VSSPLL — — — N/A N/A — 71 C8 45

Debug Data ALLPST — — — High FAST — 86 A6 55

DDATA[3:0] — — GPIO High FAST — 84,83,78,77 — —

PST[3:0] — — GPIO High FAST — 70,69,66,65 — —

2

C SCL USB_DMI UTXD2 GPIO PDSR[0] PSRR[0] pull-up

I

SDA USB_DPI URXD2 GPIO PDSR[0] PSRR[0] pull-up

4

4

10 E1 8

11 E2 9

MCF52211 Family Configurations