Freescale MC9S12NE64 DATA SHEET

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MC9S12NE64

Data Sheet

HCS12 Microcontrollers

MC9S12NE64V1 Rev 1.0 09/2004

freescale.com

MC9S12NE64 Data Sheet

MC9S12NE64V1

Rev 1.0

09/2004

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Revision History

Date

September,

2004

Revision

Level

1.0 Initial external release.

Description

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.

MC9S12NE64 Data Sheet, Rev 1.0

4 Freescale Semiconductor

Device Overview

64K Byte Flash (FTS64K) Block Description

Port Integration Module (PIM) Block Description

Clocks and Reset Generator (CRG) Block Description

Oscillator (OSC) Block Description

16-Bit, 4-Channel Timer (TIM_16B4C) Block Description

Analog-to-Digital Converter (ATD_10B8C) Block Description

Serial Communications Interface (SCI) Block Description

Serial Peripheral Interface (SPI) Block Description

Inter-Integrated Circuit (IIC) Block Description

Ethernet Media Access Controller (EMAC) Block Description

Ethernet Physical Transceiver (EPHY) Block Description

Output Voltage Regulator (VREG_PHY) Block Description

Interrupt (INT) Block Description

Multiplexed External Bus Interface (MEBI) Block Description

Module Mapping Control (MMC) Block Description

Background Debug Module (BDM) Block Description

Debug Module (DBG) Block Description

Electrical Characteristics

Schematic and PCB Layout Design Recommendations

Package Information

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 5

MC9S12NE64 Data Sheet, Rev 1.0

6 Freescale Semiconductor

Contents

Section Number Title Page

Chapter 1

Device Overview

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

1.1.5 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

1.1.6 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1.2.1.1 112-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1.2.1.2 80-Pin TQFP-EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

1.2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

1.2.3.2

1.2.3.3 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

1.2.3.4 BKGD / MODC /

1.2.3.5 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . 73

1.2.3.6 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . 74

1.2.3.7 PE7 / NOACC — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.2.3.8 PE6 / IPIPE1/ MODB — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.2.3.9 PE5 / IPIPE0 / MODA — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.2.3.10 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output . . . . . . . . . . . . . . . . . . . . 74

1.2.3.11 PE3 /

1.2.3.12 PE2 / R/

1.2.3.13 PE1 /

1.2.3.14 PE0 /

1.2.3.15 PK7 /

1.2.3.16 PK6 /

1.2.3.17 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . 76

1.2.3.18 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0] . . . . . . . . . . . . . . . . . . . . . 76

1.2.3.19 PG7 / KWG7 — Port G I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

1.2.3.20 PG6 / KWG6 / MII_RXER — Port G I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . 76

1.2.3.21 PG5 / KWG5 / MII_RXDV — Port G I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . 76

1.2.3.22 PG4 / KWG4 / MII_RXCLK — Port G I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . 77

RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

TAGHI — Background Debug / Tag High / Mode Pin . . 73

TAGLO / LSTRB — Port E I/O Pin 3 / Low-Byte Strobe

(LSTRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

W — Port E I/O Pin 2 / Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . 75

IRQ — Port E Input Pin 1 / Maskable Interrupt Pin . . . . . . . . . . . . . . 75

XIRQ — Port E input Pin 0 / Non-Maskable Interrupt Pin . . . . . . . . . 75

ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . 75

XCS — Port K I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 7

Section Number Title Page

1.2.3.23 PG3 / KWG3 / MII_RXD3 — Port G I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . 77

1.2.3.24 PG2 / KWG2 / MII_RXD2 — Port G I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . 77

1.2.3.25 PG1 / KWG1 / MII_RXD1 — Port G I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . 77

1.2.3.26 PG0 / KWG0 / MII_RXD0 — Port G I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . 77

1.2.3.27 PH6 / KWH6 / MII_TXER — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . 77

1.2.3.28 PH5 / KWH5 / MII_TXEN — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . 78

1.2.3.29 PH4 / KWH4 / MII_TXCLK — Port H I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . 78

1.2.3.30 PH3 / KWH3 / MII_TXD3 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . 78

1.2.3.31 PH2 / KWH2 / MII_TXD2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . 78

1.2.3.32 PH1 / KWH1 / MII_TXD1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . 78

1.2.3.33 PH0 / KWH0 / MII_TXD0 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . 78

1.2.3.34 PJ7 / KWJ7 / IIC_SCL — Port J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . 79

1.2.3.35 PJ6 / KWJ6 / IIC_SDA — Port J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 79

1.2.3.36 PJ3 / KWJ3 / MII_COL — Port J I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . 79

1.2.3.37 PJ2 / KWJ2 / MII_CRS /— Port J I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . 79

1.2.3.38 PJ1 / KWJ1 / MII_MDIO — Port J I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . 79

1.2.3.39 PJ0 / KWJ0 / MII_MDC — Port J I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . 79

1.2.3.40 PL6 — Port L I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.2.3.41 PL5 — Port L I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.2.3.42 PL4 / COLLED — Port L I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.2.3.43 PL3 / DUPLED — Port L I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.2.3.44 PL2 / SPDLED — Port L I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.2.3.45 PL1 / LNKLED — Port L I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.2.3.46 PL0 / ACTLED — Port L I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.2.3.47 PS7 / SPI_

1.2.3.48 PS6 / SPI_SCK — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.2.3.49 PS5 / SPI_MOSI — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.2.3.50 PS4 / SPI_MISO — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.2.3.51 PS3 / SCI1_TXD — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.2.3.52 PS2 / SCI1_RXD — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.53 PS1 / SCI0_TXD — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.54 PS0 / SCI0_RXD — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.55 PT[7:4] / IOC1[7:4] — Port T I/O Pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.56 PHY_TXP — EPHY Twisted Pair Output + . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.57 PHY_TXN — EPHY Twisted Pair Output – . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.58 PHY_RXP — EPHY Twisted Pair Input + . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.59 PHY_RXN — EPHY Twisted Pair Input – . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.2.3.60 PHY_RBIAS — EPHY Bias Control Resistor . . . . . . . . . . . . . . . . . . . . . . . 83

1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

1.2.4.1 V

DDX1

Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

1.2.4.2 V

DDR/VREGEN

SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

, V

DDX2

, V

SSX1

, V

— Power & Ground Pins for I/O & Internal

SSX2

— Power Pin for Internal Voltage Regulator . . . . . . . . . . . . 83

MC9S12NE64 Data Sheet, Rev 1.0

8 Freescale Semiconductor

Section Number Title Page

1.2.4.3 V

1.2.4.4 V

DD1

DDA

, V

DD2

SSA

, V

SS1

, V

— Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . 83

SS2

— Power Supply Pins for ATD and VREG_PHY . . . . . . . . . . 83

1.2.4.5 PHY_VDDA, PHY_VSSA — Power Supply Pins for EPHY Analog . . . . . 83

1.2.4.6 PHY_VDDRX, PHY_VSSRX — Power Supply Pins for EPHY

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

1.2.4.7 PHY_VDDTX, PHY_VSSTX — Power Supply Pins for EPHY

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

1.2.4.8 V

1.2.4.9 V

, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . 84

DDPLL

, V

— Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . 84

SSPLL

1.3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

1.4.1 Chip Conﬁguration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

1.4.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

1.4.2.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

1.4.2.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.4.2.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.5.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.5.2 Pseudo Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.5.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1.5.4 Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1.6.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1.6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.6.2.1 Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.6.2.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.7 Block Conﬁguration for MC9S12NE64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.7.1 V

1.7.2 V

DDR/VREGEN

, V

DD1

DD2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

, V

SS1

, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SS2

1.7.3 Clock Reset Generator (CRG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.7.3.1

XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.7.4 Ethernet Media Access Controller (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.7.4.1 EMAC MII External Pin Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.7.4.2 EMAC Internal PHY Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.7.4.3 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.7.5 Ethernet Physical Transceiver (EPHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

1.7.5.1 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

1.7.6 RAM 8K Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 9

Section Number Title Page

Chapter 2

64K Byte Flash (FTS64K) Block Description

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.3.2.1 Flash Clock Divider Register (FCLKDIV) . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.3.2.2 Flash Security Register (FSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.3.2.3 RESERVED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

2.3.2.4 Flash Conﬁguration Register (FCNFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

2.3.2.5 Flash Protection Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

2.3.2.6 Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2.3.2.7 Flash Command Register (FCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

2.3.2.8 RESERVED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.3.2.9 Flash Address Register (FADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.3.2.10 Flash Data Register (FDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.3.2.11 RESERVED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.3.2.12 RESERVED4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.3.2.13 RESERVED5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

2.3.2.14 RESERVED6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.4.1 Program and Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.4.1.1 Writing the FCLKDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.4.1.2 Program and Erase Sequences in Normal Mode . . . . . . . . . . . . . . . . . . . . . 112

2.4.1.3 Valid Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2.4.1.4 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.4.4 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.4.5 Flash Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.4.5.1 Unsecuring the Flash via the Backdoor Access Sequence . . . . . . . . . . . . . . 116

2.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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Chapter 3

Port Integration Module (PIM) Block Description

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

3.3.2.1 Port T Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

3.3.2.2 Port S Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

3.3.2.3 Port G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3.3.2.4 Port H Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.3.2.5 Port J Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

3.3.2.6 Port L Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

3.4.1 I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

3.4.2 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

3.4.3 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.4.4 Pull Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.4.5 Polarity Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.4.6 Port T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.4.7 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3.4.8 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3.4.8.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3.4.9 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

3.4.10 Port J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

3.4.11 Port L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4.12 Port A, B, E and BKGD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4.13 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4.14 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4.14.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4.14.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.4.14.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

3.6.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

3.6.2 Recovery from Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

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Chapter 4

Clocks and Reset Generator (CRG) Block Description

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

4.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

4.2.1 V

DDPLL

, V

SSPLL

4.2.2 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

4.2.3

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

4.3.2.1 CRG Synthesizer Register (SYNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

4.3.2.2 CRG Reference Divider Register (REFDV) . . . . . . . . . . . . . . . . . . . . . . . . 160

4.3.2.3 Reserved Register (CTFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

4.3.2.4 CRG Flags Register (CRGFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.3.2.5 CRG Interrupt Enable Register (CRGINT) . . . . . . . . . . . . . . . . . . . . . . . . . 162

4.3.2.6 CRG Clock Select Register (CLKSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

4.3.2.7 CRG PLL Control Register (PLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

4.3.2.8 CRG RTI Control Register (RTICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

4.3.2.9 CRG COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

4.3.2.10 Reserved Register (FORBYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

4.3.2.11 Reserved Register (CTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

4.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) . . . . . . . . . . . . . . . . . . . 170

4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

4.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

4.4.1.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

4.4.1.2 System Clocks Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

4.4.1.3 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

4.4.1.4 Clock Quality Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

4.4.1.5 Computer Operating Properly Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . 177

4.4.1.6 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

4.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.2.2 Self-Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.3.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.3.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.3.3 CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

4.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

4.5.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

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4.5.2 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . 190

4.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

4.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

4.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

4.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Chapter 5

Oscillator (OSC) Block Description

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

5.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

5.2.1 V

DDPLL

, V

SSPLL

5.2.2 EXTAL, XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

5.2.3 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

5.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

5.4.1 Amplitude Limitation Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

5.4.2 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 6

16-Bit, 4-Channel Timer (TIM_16B4C) Block Description

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.2.1 IOC7 – Input capture and Output compare channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.2.2 IOC6 – Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . 199

6.2.3 IOC5 – Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . 199

6.2.4 IOC4 – Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . 199

6.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

6.3.2.1 Timer Input Capture/Output Compare Select (TIOS) . . . . . . . . . . . . . . . . . 200

6.3.2.2 Timer Compare Force Register (CFORC) . . . . . . . . . . . . . . . . . . . . . . . . . . 201

6.3.2.3 Output Compare 7 Mask Register (OC7M) . . . . . . . . . . . . . . . . . . . . . . . . . 201

6.3.2.4 Output Compare 7 Data Register (OC7D) . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.3.2.5 Timer Count Register (TCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.3.2.6 Timer System Control Register 1 (TSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 203

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6.3.2.7 Timer Toggle On Overﬂow Register 1 (TTOV) . . . . . . . . . . . . . . . . . . . . . . 204

6.3.2.8 Timer Control Register 1 (TCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

6.3.2.9 Timer Control Register 3 (TCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3.2.10 Timer Interrupt Enable Register (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3.2.11 Timer System Control Register 2 (TSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.3.2.14 Timer Input Capture/Output Compare Registers (TC4 – TC7) . . . . . . . . . . 208

6.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . . . . . . 209

6.3.2.16 Pulse Accumulator Flag Register (PAFLG) . . . . . . . . . . . . . . . . . . . . . . . . . 210

6.3.2.17 Pulse Accumulators Count Registers (PACNT) . . . . . . . . . . . . . . . . . . . . . . 211

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

6.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

6.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

6.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

6.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

6.4.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

6.4.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.6.1 Channel [7:4] Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.6.2 Pulse Accumulator Input Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

6.6.3 Pulse Accumulator Overﬂow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

6.6.4 Timer Overﬂow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Chapter 7

Analog-to-Digital Converter (ATD_10B8C)

Block Description

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.2.1 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.2.2 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

7.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

7.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.2.3 V

7.2.4 V

7.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

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, VRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

DDA

, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

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7.3.2.1 ATD Control Register 0 (ATDCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

7.3.2.2 ATD Control Register 1 (ATDCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

7.3.2.3 ATD Control Register 2 (ATDCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

7.3.2.4 ATD Control Register 3 (ATDCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.3.2.5 ATD Control Register 4 (ATDCTL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

7.3.2.6 ATD Control Register 5 (ATDCTL5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.3.2.7 ATD Status Register 0 (ATDSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.3.2.8 Reserved Register (ATDTEST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

7.3.2.9 ATD Test Register 1 (ATDTEST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

7.3.2.10 ATD Status Register 1 (ATDSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.3.2.11 ATD Input Enable Register (ATDDIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.3.2.12 Port Data Register (PORTAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.3.2.13 ATD Conversion Result Registers (ATDDRx) . . . . . . . . . . . . . . . . . . . . . . 235

7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.4.1.1 Sample and Hold Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.4.1.2 Analog Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.4.1.3 Sample Buffer Ampliﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.4.1.4 Analog-to-Digital (A/D) Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.4.2.1 External Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.4.2.2 General Purpose Digital Input Port Operation . . . . . . . . . . . . . . . . . . . . . . . 238

7.4.2.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Chapter 8

Serial Communications Interface (SCI) Block Description

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

8.2.1 SCI_TXD — SCI Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

8.2.2 SCI_RXD — SCI Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

8.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

8.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) . . . . . . . . . . . . . . . . . . . . . . 245

8.3.2.2 SCI Control Register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

8.3.2.3 SCI Control Register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

8.3.2.4 SCI Status Register 1 (SCISR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

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8.3.2.5 SCI Status Register 2 (SCISR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

8.3.2.6 SCI Data Registers (SCIDRH, SCIDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 252

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

8.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

8.4.1.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

8.4.1.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

8.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

8.4.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

8.4.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

8.4.4.1 Transmitter Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

8.4.4.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

8.4.4.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

8.4.4.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

8.4.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.4.5.1 Receiver Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.4.5.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.4.5.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

8.4.5.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

8.4.5.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

8.4.5.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

8.4.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

8.4.7 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

8.4.8 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

8.4.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.9.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.9.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.9.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.10 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.10.1 System Level Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.10.2 Interrupt Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8.4.10.3 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

8.6.1 TDRE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

8.6.2 TC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

8.6.3 RDRF Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

8.6.4 OR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

8.6.5 IDLE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

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Chapter 9

Serial Peripheral Interface (SPI) Block Description

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

9.2.1 SPI_MOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

9.2.2 SPI_MISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

9.2.3 SPI_

9.2.4 SPI_SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

9.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

9.3.2.1 SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

9.3.2.2 SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

9.3.2.3 SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

9.3.2.4 SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

9.3.2.5 SPI Data Register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

9.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

9.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

9.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

9.4.4 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

9.4.5 CPHA = 0 Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

9.4.6 CPHA = 1 Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

9.4.7 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

9.4.8 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

9.4.8.1

9.4.8.2 Bidirectional Mode (MOMI or SISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

9.4.9 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

9.4.9.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

9.4.10 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

9.4.10.1 SPI in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

9.4.10.2 SPI in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

9.4.10.3 SPI in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

9.4.10.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

9.4.10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

SS Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

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Chapter 10

Inter-Integrated Circuit (IIC) Block Description

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

10.2.1 IIC_SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

10.2.2 IIC_SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

10.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

10.3.2.1 IIC Address Register (IBAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

10.3.2.2 IIC Frequency Divider Register (IBFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

10.3.2.3 IIC Control Register (IBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

10.3.2.4 IIC Status Register (IBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

10.3.2.5 IIC Data I/O Register (IBDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

10.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

10.4.1.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

10.4.1.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

10.4.1.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

10.4.1.4 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

10.4.1.5 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

10.4.1.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

10.4.1.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

10.4.1.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.4.1.9 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.4.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.4.2.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.4.2.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.4.2.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.5.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.5.1.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

10.5.1.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

10.5.1.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

10.5.1.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

10.5.1.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

10.5.1.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

10.5.1.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

10.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

10.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

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Chapter 11

Ethernet Media Access Controller (EMAC) Block Description

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

11.2.1 MII_TXCLK — MII Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

11.2.2 MII_TXD[3:0] — MII Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

11.2.3 MII_TXEN — MII Transmit Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

11.2.4 MII_TXER — MII Transmit Coding Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

11.2.5 MII_RXCLK — MII Receive Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

11.2.6 MII_RXD[3:0] — MII Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

11.2.7 MII_RXDV — MII Receive Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

11.2.8 MII_RXER — MII Receive Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

11.2.9 MII_CRS — MII Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

11.2.10 MII_COL — MII Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

11.2.11 MII_MDC — MII Management Data Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

11.2.12 MII_MDIO — MII Management Data Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . 325

11.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

11.3.2.1 Network Control (NETCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

11.3.2.2 Receive Control and Status (RXCTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

11.3.2.3 Transmit Control and Status (TXCTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

11.3.2.4 Ethertype Control (ETCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

11.3.2.5 Programmable Ethertype (ETYPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

11.3.2.6 PAUSE Timer Value and Counter (PTIME) . . . . . . . . . . . . . . . . . . . . . . . . 333

11.3.2.7 Interrupt Event (IEVENT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

11.3.2.8 Interrupt Mask (IMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

11.3.2.9 Software Reset (SWRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

11.3.2.10 MII Management PHY Address (MPADR) . . . . . . . . . . . . . . . . . . . . . . . . . 337

11.3.2.11 MII Management Register Address (MRADR) . . . . . . . . . . . . . . . . . . . . . . 337

11.3.2.12 MII Management Write Data (MWDATA) . . . . . . . . . . . . . . . . . . . . . . . . . 337

11.3.2.13 MII Management Read Data (MRDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 338

11.3.2.14 MII Management Command and Status (MCMST) . . . . . . . . . . . . . . . . . . 338

11.3.2.15 Ethernet Buffer Conﬁguration (BUFCFG) . . . . . . . . . . . . . . . . . . . . . . . . . 340

11.3.2.16 Receive A End-of-Frame Pointer (RXAEFP) . . . . . . . . . . . . . . . . . . . . . . . 341

11.3.2.17 Receive B End-of-Frame Pointer (RXBEFP) . . . . . . . . . . . . . . . . . . . . . . . 341

11.3.2.18 Transmit End-of-Frame Pointer (TXEFP) . . . . . . . . . . . . . . . . . . . . . . . . . . 341

11.3.2.19 Multicast Hash Table (MCHASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

11.3.2.20 MAC Unicast Address (MACAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

11.3.2.21 Miscellaneous (EMISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

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11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

11.4.1 Ethernet Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

11.4.1.1 Preamble and SFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

11.4.1.2 Address Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

11.4.1.3 Type/Length Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

11.4.1.4 Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

11.4.1.5 Frame Check Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

11.4.1.6 End-of-Frame Delimiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

11.4.1.7 Interframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

11.4.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

11.4.2.1 Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

11.4.2.2 Type/Length Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

11.4.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

11.4.3.1 Interframe Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

11.4.3.2 Deferring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

11.4.3.3 Collision Detection and Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

11.4.4 Ethernet Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

11.4.4.1 Receive Ethernet Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

11.4.4.2 Transmit Ethernet Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

11.4.5 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

11.4.5.1 MAC Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

11.4.5.2 Hardware Generated PAUSE Control Frame Transmission . . . . . . . . . . . . 356

11.4.5.3 PAUSE Control Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

11.4.6 MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

11.4.6.1 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

11.4.6.2 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

11.4.6.3 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

11.4.7 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

11.4.8 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

11.4.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

11.4.10 Debug and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Chapter 12

Ethernet Physical Transceiver (EPHY) Block Description

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

12.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

12.2.1 PHY_TXP — EPHY Twisted Pair Output + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

12.2.2 PHY_TXN — EPHY Twisted Pair Output – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

12.2.3 PHY_RXP — EPHY Twisted Pair Input + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

12.2.4 PHY_RXN — EPHY Twisted Pair Input – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

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12.2.5 PHY_RBIAS — EPHY Bias Control Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

12.2.6 PHY_VDDRX, PHY_VSSRX — Power Supply Pins for EPHY Receiver . . . . . . . . 364

12.2.7 PHY_VDDTX, PHY_VSSTX — Power Supply Pins for EPHY Transmitter . . . . . . 364

12.2.8 PHY_VDDA, PHY_VSSA — Power Supply Pins for EPHY Analog . . . . . . . . . . . . 364

12.2.9 COLLED — Collision LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

12.2.10 DUPLED — Duplex LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

12.2.11 SPDLED — Speed LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

12.2.12 LNKLED — Link LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

12.2.13 ACTLEC — Activity LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

12.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

12.3.2.1 Ethernet Physical Transceiver Control Register 0 (EPHYCTL0) . . . . . . . . 365

12.3.2.2 Ethernet Physical Transceiver Control Register 1 (EPHYCTL1) . . . . . . . . 366

12.3.2.3 Ethernet Physical Transceiver Status Register (EPHYSR) . . . . . . . . . . . . . 367

12.3.3 MII Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

12.3.3.1 EPHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

12.3.3.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

12.3.3.3 EPHY Identiﬁer Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

12.3.3.4 EPHY Identiﬁer Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

12.3.3.5 Auto-Negotiate (A/N) Advertisement Register . . . . . . . . . . . . . . . . . . . . . . 373

12.3.3.6 Auto Negotiation Link Partner Ability (Base Page) . . . . . . . . . . . . . . . . . . 374

12.3.3.7 Auto Negotiation Link Partner Ability (Next Page) . . . . . . . . . . . . . . . . . . 375

12.3.3.8 Auto-Negotiation Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

12.3.3.9 Auto Negotiation Next Page Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

12.3.4 PHY-Speciﬁc Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

12.3.4.1 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

12.3.4.2 Proprietary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

12.3.4.3 Proprietary Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

12.4.1 Power Down/Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

12.4.2 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

12.4.3 10BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

12.4.4 100BASE-TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

12.4.4.1 Sublayers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

12.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

12.4.5.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

12.4.5.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

12.4.5.3 MII Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

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Chapter 13

Output Voltage Regulator (VREG_PHY)

Block Description

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

13.2.1 V

13.2.2 V

13.2.3 V

13.2.4 V

13.2.5 V

13.2.6 V

DDR,VDDRAUX1,2,3

, V

DDA

, VSS — Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

DDPLL

DDAUX1,2,3

REGEN

— Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

SSA

, V

SSPLL

, V

— Optional Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

, V

— Regulator Output2 (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

SSAUX1,2,3

13.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

13.4.1 REG — Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

13.4.1.1 Full Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.4.1.2 Reduced Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.4.2 POR — Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.4.3 LVR — Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.4.4 CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

13.5.2 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

— Regulator Power Inputs . . . . . . . . . . . . . . . . . . . . . . . 395

SSR

— Regulator Output3,4,5 . . . . . . . . . . . . . . . . . . . . . . . . . 396

Chapter 14

Interrupt (INT) Block Description

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.1.2.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.1.2.2 Special Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.1.2.3 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.1.3 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.1.3.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

14.1.3.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

14.1.3.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

14.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

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14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

14.3.2.1 Interrupt Test Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

14.3.2.2 Interrupt Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

14.3.2.3 Highest Priority I Interrupt (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

14.4.1 Interrupt Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

14.4.1.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

14.4.1.2 Highest Priority I-Bit Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 405

14.4.1.3 Interrupt Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

14.4.2 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

14.4.3 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Chapter 15

Multiplexed External Bus Interface (MEBI)

Block Description

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

15.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

15.3.2.1 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

15.3.2.2 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

15.3.2.3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

15.3.2.4 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

15.3.2.5 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

15.3.2.6 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

15.3.2.7 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

15.3.2.8 Port E Assignment Register (PEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

15.3.2.9 Mode Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

15.3.2.10 Pull-Up Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

15.3.2.11 Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

15.3.2.12 External Bus Interface Control Register (EBICTL) . . . . . . . . . . . . . . . . . . 427

15.3.2.13 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

15.3.2.14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

15.3.2.15 Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

15.3.2.16 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

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15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

15.4.1 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

15.4.1.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . 431

15.4.1.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

15.4.2 External Data Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

15.4.2.1 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

15.4.2.2 Secure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

15.4.3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

15.4.3.1 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

15.4.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Chapter 16

Module Mapping Control (MMC) Block Description

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

16.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

16.3.2.1 Initialization of Internal RAM Position Register (INITRM) . . . . . . . . . . . . 437

16.3.2.2 Initialization of Internal Registers Position Register (INITRG) . . . . . . . . . 438

16.3.2.3 Initialization of Internal EEPROM Position Register (INITEE) . . . . . . . . . 438

16.3.2.4 Miscellaneous System Control Register (MISC) . . . . . . . . . . . . . . . . . . . . . 439

16.3.2.5 Reserved Test Register 0 (MTST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

16.3.2.6 Reserved Test Register 1 (MTST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

16.3.2.7 Memory Size Register 0 (MEMSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

16.3.2.8 Memory Size Register 1 (MEMSIZ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

16.3.2.9 Program Page Index Register (PPAGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

16.4.1 Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

16.4.2 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

16.4.2.1 Select Priority and Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 446

16.4.2.2 Emulation Chip Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

16.4.2.3 External Chip Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

16.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

16.4.3.1 CALL and Return from Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 448

16.4.3.2 Extended Address (XAB19:14) and ECS Signal Functionality . . . . . . . . . 449

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Chapter 17

Background Debug Module (BDM) Block Description

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

17.1.2.1 Regular Run Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

17.1.2.2 Secure Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

17.1.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

17.2.1 Background Interface Pin (BKGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

17.2.2 High Byte Instruction Tagging Pin (

17.2.3 Low Byte Instruction Tagging Pin (

17.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

17.3.1 BDM Status Register (BDMSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

17.3.2 BDM CCR Holding Register (BDMCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

17.3.3 BDM Internal Register Position Register (BDMINR) . . . . . . . . . . . . . . . . . . . . . . . . 460

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

17.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

17.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

17.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

17.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

17.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

17.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

17.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

17.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

17.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

17.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

17.4.11 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

17.4.12 Serial Communication Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

TAGHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

TAGLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Chapter 18

Debug Module (DBG) Block Description

18.1 Introduction to the Debug (DBG) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

18.3 Memory Map and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

18.3.2.1 Debug Control Register 1 (DBGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

18.3.2.2 Debug Status and Control Register (DBGSC) . . . . . . . . . . . . . . . . . . . . . . . 485

18.3.2.3 Debug Trace Buffer Register (DBGTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

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18.3.2.4 Debug Count Register (DBGCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

18.3.2.5 Debug Comparator C Extended Register (DBGCCX) . . . . . . . . . . . . . . . . 488

18.3.2.6 Debug Comparator C Register (DBGCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 489

18.3.2.7 Debug Control Register 2 (DBGC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

18.3.2.8 Debug Control Register 3 (DBGC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

18.3.2.9 Debug Comparator A Extended Register (DBGCAX) . . . . . . . . . . . . . . . . 494

18.3.2.10 Debug Comparator A Register (DBGCA) . . . . . . . . . . . . . . . . . . . . . . . . . . 495

18.3.2.11 Debug Comparator B Extended Register (DBGCBX) . . . . . . . . . . . . . . . . 495

18.3.2.12 Debug Comparator B Register (DBGCB) . . . . . . . . . . . . . . . . . . . . . . . . . . 495

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

18.4.1 DBG Operating in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

18.4.1.1 Dual Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

18.4.1.2 Full Breakpoint Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

18.4.1.3 Breakpoint Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

18.4.1.4 Using Comparator C in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

18.4.2 DBG Operating in DBG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

18.4.2.1 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

18.4.2.2 Trace Buffer Control (TBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

18.4.2.3 Begin- and End-Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

18.4.2.4 Arming the DBG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

18.4.2.5 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

18.4.2.6 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

18.4.2.7 Storage Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

18.4.2.8 Storing Data in Memory Storage Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

18.4.2.9 Reading Data from Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

18.4.3 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

18.4.3.1 Breakpoint Based on Comparator A and B . . . . . . . . . . . . . . . . . . . . . . . . . 505

18.4.3.2 Breakpoint Based on Comparator C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

18.4.4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

18.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Appendix A

Electrical Characteristics

A.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

A.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

A.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

A.3.1 3.3 V I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

A.3.2 Analog Reference, Special Function Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

A.3.3 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

A.3.4 TEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

A.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

A.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

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A.6 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

A.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

A.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

A.9 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

A.10 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

A.10.1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

A.10.2 Additional Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

A.11 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

A.11.1 ATD Operating Characteristics — 3.3 V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

A.11.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

A.11.2.1 Source Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

A.11.2.2 Source Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

A.11.2.3 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

A.11.3 ATD Accuracy — 3.3 V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

A.12 Reset, Oscillator, and PLL Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

A.12.1 Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

A.12.1.1 POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

A.12.1.2 LVR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

A.12.1.3 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

A.12.1.4 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

A.12.1.5 Stop Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

A.12.1.6 Pseudo Stop and Wait Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

A.12.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

A.12.3 Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

A.12.3.1 XFC Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

A.13 EMAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

A.13.1 MII Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

A.13.1.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RXDV, MII_RXER,

MII_RXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

A.13.1.2 MII Transmit Signal Timing (TXD[3:0], TXEN, TXER, TXCLK). . . . . . . 530

A.13.1.3 MII Asynchronous Inputs Signal Timing (CRS, COL) . . . . . . . . . . . . . . . . 530

A.13.1.4 MII Management Timing (MDIO, MDC) . . . . . . . . . . . . . . . . . . . . . . . . . . 531

A.14 EPHY Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

A.14.1 10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

A.14.2 Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

A.14.2.1 MII – 100BASE-TX Transmit Timing Parameters . . . . . . . . . . . . . . . . . . . 534

A.14.2.2 MII — 10BASE-T Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

A.15 FLASH NVM Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

A.15.1 NVM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

A.15.1.1 Single Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

A.15.1.2 Burst Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

A.15.1.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

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A.15.1.4 Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

A.15.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

A.16 SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

A.16.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

A.16.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

A.17 Voltage Regulator Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

A.17.1 MCU Power-Up and LVR Graphical Explanation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

A.17.2 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

A.17.2.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

A.17.2.2 Capacitive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

A.18 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Appendix B

Schematic and PCB Layout Design Recommendations

B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

B.1.1 Schematic Designing with the MC9S12NE64 and Adding an Ethernet Interface . . . . 549

B.1.2 Power Supply Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

B.1.3 Clocking Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

B.1.4 EPHY Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

B.1.5 EPHY LED Indicator Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

B.2 PCB Design Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

B.2.1 General PCB Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

B.2.2 Ethernet PCB Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

B.2.2.1 High-Speed LAN Magnetics Isolation Module Requirements. . . . . . . . . . . 553

B.2.2.2 80-Pin Package Exposed Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Appendix C

Package Information

C.1 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

C.2 80-Pin TQFP-EP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

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List of Figures

Figure Number Title Page

Figure 1-1. MC9S12NE64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 1-2. MC9S12NE64 User Configurable Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 1-3. Pin Assignments in 112-Pin LQFP for MC9S12NE64 . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 1-4. Pin Assignments in 80-Pin TQFP-EP for MC9S12NE64 . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 1-5. Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 2-1. Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 2-2. Flash Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 2-3. Flash Clock Divider Register (FCLKDIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 2-4. Flash Security Register (FSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 2-5. RESERVED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 2-6. Flash Configuration Register (FCNFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 2-7. Flash Protection Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 2-8. Flash Status Register (FSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 2-9. Flash Command Register (FCMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 2-10. RESERVED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 2-11. Flash Address High Register (FADDRHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 2-12. Flash Address Low Register (FADDRLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 2-13. Flash Data High Register (FDATAHI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 2-14. Flash Data Low Register (FDATALO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 2-15. RESERVED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 2-16. RESERVED4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 2-17. RESERVED5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 2-18. RESERVED6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 2-19. PRDIV8 and FDIV Bits Determination Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 2-20. Example Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 2-21. Flash Interrupt Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 3-1. PIM_9NE64 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 3-2. Port T I/O Register (PTT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 3-3. Port T Input Register (PTIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 3-4. Port T Data Direction Register (DDRT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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Figure 3-5. Port T Reduced Drive Register (RDRT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 3-6. Port T Pull Device Enable Register (PERT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 3-7. Port T Polarity Select Register (PPST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 3-8. Port S I/O Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 3-9. Port S Input Register (PTIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 3-10. Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 3-11. Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 3-12. Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 3-13. Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 3-14. Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 3-15. Port G I/O Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 3-16. Port G Input Register (PTIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 3-17. Port G Data Direction Register (DDRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 3-18. Port G Reduced Drive Register (RDRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 3-19. Port G Pull Device Enable Register (PERG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 3-20. Port G Polarity Select Register (PPSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 3-21. Port G Interrupt Enable Register (PIEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 3-22. Port G Interrupt Flag Register (PIFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 3-23. Port H I/O Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 3-24. Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 3-25. Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 3-26. Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 3-27. Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 3-28. Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 3-29. Port H Interrupt Enable Register (PIEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 3-30. Port H Interrupt Flag Register (PIFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 3-31. Port J I/O Register (PTJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 3-32. Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 3-33. Port J Data Direction Register (DDRJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 3-34. Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 3-35. Port J Pull Device Enable Register (PERJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 3-36. Port J Polarity Select Register (PPSJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 3-37. Port J Interrupt Enable Register (PIEJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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Figure 3-38. Port J Interrupt Flag Register (PIFJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 3-39. Port L I/O Register (PTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 3-40. Port L Input Register (PTIL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 3-41. Port L Data Direction Register (DDRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 3-42. Port L Reduced Drive Register (RDRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 3-43. Port L Pull Device Enable Register (PERL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 3-44. Port L Polarity Select Register (PPSL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 3-45. Port L Wired-Or Mode Register (WOML). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 3-46. Illustration of I/O Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 3-47. Interrupt Glitch Filter on Port G, H, and J (PPS=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 3-48. Pulse Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 4-1. Block Diagram of CRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 4-2. PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 4-3. CRG Synthesizer Register (SYNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 4-4. CRG Reference Divider Register (REFDV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 4-5. Reserved Register (CTFLG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 4-6. CRG Flags Register (CRGFLG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 4-7. CRG Interrupt Enable Register (CRGINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 4-8. CRG Clock Select Register (CLKSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 4-9. CRG PLL Control Register (PLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 4-10. CRG RTI Control Register (RTICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 4-11. CRG COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 4-12. Reserved Register (FORBYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 4-13. Reserved Register (CTCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 4-14. ARMCOP Register Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 4-15. PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 4-16. System Clocks Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 4-17. Core Clock and Bus Clock Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 4-18. Check Window Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 4-19. Sequence for Clock Quality Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 4-20. Clock Chain for COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 4-21. Clock Chain for RTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 4-22. Wait Mode Entry/Exit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

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Figure 4-23. Stop Mode Entry/Exit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 4-24. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 4-25. RESET Pin Tied to VDD (by a Pull-Up Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 4-26. RESET Pin Held Low Externally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 5-1. Colpitts Oscillator Connections (XCLKS=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 5-2. Pierce Oscillator Connections (XCLKS=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 5-3. External Clock Connections (XCLKS=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 6-1. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 6-2. Timer Input Capture/Output Compare Select (TIOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 6-3. Timer Compare Force Register (CFORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 6-4. Output Compare 7 Mask Register (OC7M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 6-5. Output Compare 7 Data Register (OC7D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 6-6. Timer Count Register (TCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 6-7. Timer System Control Register 1 (TSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 6-8. Timer Toggle On Overflow Register 1 (TTOV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 6-9. Timer Control Register 1 (TCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 6-10. Timer Control Register 3 (TCTL3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 6-11. Timer Interrupt Enable Register (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 6-12. Timer System Control Register 2 (TSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 6-13. Main Timer Interrupt Flag 1 (TFLG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 6-14. Main Timer Interrupt Flag 2 (TFLG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 6-15. Timer Input Capture/Output Compare Registers (TC4 – TC7) . . . . . . . . . . . . . . . . . . . 208

Figure 6-16. 16-Bit Pulse Accumulator Control Register (PACTL). . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 6-17. Pulse Accumulator Flag Register (PAFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 6-18. Pulse Accumulators Count Registers (PACNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 6-19. Detailed Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 6-20. Pulse Accumulator System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 7-1. ATD_10B8C Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 7-2. ATD Control Register 0 (ATDCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 7-3. ATD Control Register 1 (ATDCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 7-4. ATD Control Register 2 (ATDCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 7-5. ATD Control Register 3 (ATDCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 7-6. ATD Control Register 4 (ATDCTL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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Figure 7-7. ATD Control Register 5 (ATDCTL5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 7-8. ATD Status Register 0 (ATDSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 7-9. Reserved Register (ATDTEST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 7-10. ATD Test Register 1 (ATDTEST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 7-11. ATD Status Register 1 (ATDSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 7-12. ATD Input Enable Register (ATDDIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 7-13. Port Data Register (PORTAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 7-14. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH) . . . . . . . . . . 235

Figure 7-15. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) . . . . . . . . . . 235

Figure 7-16. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH) . . . . . . . . . 236

Figure 7-17. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) . . . . . . . . . 236

Figure 8-1. SCI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 8-2. SCI Baud Rate Registers (SCIBDH/L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 8-3. SCI Control Register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 8-4. SCI Control Register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 8-5. SCI Status Register 1 (SCISR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 8-6. SCI Status Register 2 (SCISR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 8-7. SCI Data Registers (SCIDRH/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 8-8. Detailed SCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 8-9. SCI Data Formats (Standard SCI and Infrared) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 8-10. Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 8-11. SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 8-12. Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 8-13. Start Bit Search Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 8-14. Start Bit Search Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 8-15. Start Bit Search Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 8-16. Start Bit Search Example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 8-17. Start Bit Search Example 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 8-18. Start Bit Search Example 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 8-19. Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 8-20. Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 8-21. Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 8-22. Loop Operation (LOOPS = 1, RSRC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

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Figure 9-1. SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 9-2. SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 9-3. SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 9-4. SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 9-5. SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 9-6. SPI Data Register (SPIDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure 9-7. Master/Slave Transfer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 9-8. SPI Clock Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 9-9. SPI Clock Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 9-10. Baud Rate Divisor Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Figure 10-1. IIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 10-2. IIC Bus Address Register (IBAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 10-3. IIC Bus Frequency Divider Register (IBFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 10-4. SCL Divider and SDA Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 10-5. IIC-Bus Control Register (IBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 10-6. IIC Bus Status Register (IBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 10-7. IIC Bus Data I/O Register (IBDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 10-8. IIC-Bus Transmission Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 10-9. Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 10-10. IIC-Bus Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 10-11. Flow-Chart of Typical IIC Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 11-1. EMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 11-2. Network Control (NETCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 11-3. Receive Control and Status (RXCTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 11-4. Transmit Control and Status (TXCTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 11-5. Ethertype Control (ETCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Figure 11-6. Programmable Ethertype (ETYPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 11-7. PAUSE Timer Value and Counter (PTIME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Figure 11-8. Interrupt Event (IEVENT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Figure 11-9. Interrupt Mask (IMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Figure 11-10. Software Reset (SWRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 11-11. MII Management PHY Address (MPADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 11-12. MII Management Register Address (MRADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

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Figure 11-13. MII Management Write Data (MWDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 11-14. MII Management Read Data (MRDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 11-15. MII Management Command and Status (MCMST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 11-16. Ethernet Buffer Configuration (BUFCFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 11-17. Receive A End-of-Frame Pointer (RXAEFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 11-18. Receive B End-of-Frame Pointer (RXBEFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 11-19. Transmit End-of-Frame Pointer (TXEFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 11-20. Multicast Hash Table (MCHASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 11-21. MAC Address (MACAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 11-22. Miscellaneous (EMISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 11-23. MII Nibble/Byte-to-Byte/Nibble Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Figure 11-24. Receive Address Recognition Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Figure 11-25. Receive Type/Length Recognition Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Figure 11-26. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Figure 11-27. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Figure 12-1. Ethernet Physical Transceiver (EPHY) Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 362

Figure 12-2. PHY Sub Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 12-3. Ethernet Physical Transceiver Control Register 0 (EPHYCTL0) . . . . . . . . . . . . . . . . . 365

Figure 12-4. Ethernet Physical Transceiver Control Register 1 (EPHYCTL1) . . . . . . . . . . . . . . . . . 366

Figure 12-5. Ethernet Physical Transceiver Status Register (EPHYSR) . . . . . . . . . . . . . . . . . . . . . . 367

Figure 12-6. Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 12-7. Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Figure 12-8. EPHY Identifier Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 12-9. EPHY Identifier Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 12-10. Auto Negotiate Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Figure 12-11. Auto Negotiation Link Partner Ability Register (Base Page). . . . . . . . . . . . . . . . . . . . . 374

Figure 12-12. Auto Negotiation Link Partner Ability Register (Next Page). . . . . . . . . . . . . . . . . . . . . 375

Figure 12-13. Auto-Negotiation Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Figure 12-14. Auto Negotiation Next Page Transmit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Figure 12-15. Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 12-16. Proprietary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Figure 12-17. Proprietary Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Figure 12-18. EPHY Start-Up / Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

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Figure 12-19. EPHY Start-Up Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Figure 12-20. Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 12-21. 10BASE-T Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 12-22. 100BASE-TX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Figure 13-1. VREG_PHY Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Figure 14-1. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Figure 14-2. Interrupt Test Control Register (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Figure 14-3. Interrupt TEST Registers (ITEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Figure 14-4. Highest Priority I Interrupt Register (HPRIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

Figure 15-1. MEBI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Figure 15-2. Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Figure 15-3. Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Figure 15-4. Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Figure 15-5. Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Figure 15-6. Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Figure 15-7. Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Figure 15-8. Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Figure 15-9. Port E Assignment Register (PEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Figure 15-10. Mode Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Figure 15-11. Pullup Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Figure 15-12. Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Figure 15-13. External Bus Interface Control Register (EBICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Figure 15-14. Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 15-15. IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 15-16. Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Figure 15-17. Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Figure 16-1. Module Mapping Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Figure 16-2. Initialization of Internal RAM Position Register (INITRM) . . . . . . . . . . . . . . . . . . . . . 437

Figure 16-3. Initialization of Internal Registers Position Register (INITRG). . . . . . . . . . . . . . . . . . . 438

Figure 16-4. Initialization of Internal EEPROM Position Register (INITEE) . . . . . . . . . . . . . . . . . . 438

Figure 16-5. Miscellaneous System Control Register (MISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Figure 16-6. Reserved Test Register 0 (MTST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

Figure 16-7. Reserved Test Register 1 (MTST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

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Figure 16-8. Memory Size Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Figure 16-9. Memory Size Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

Figure 16-10. Program Page Index Register (PPAGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Figure 16-11. Memory Paging Example: 1M Byte On-Chip FLASH/ROM, 64K Allocation . . . . . . . 451

Figure 17-1. BDM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 17-2. BDM Status Register (BDMSTS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Figure 17-3. BDM CCR Holding Register (BDMCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Figure 17-4. BDM Internal Register Position (BDMINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Figure 17-5. BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 17-6. BDM Host-to-Target Serial Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Figure 17-7. BDM Target-to-Host Serial Bit Timing (Logic 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Figure 17-8. BDM Target-to-Host Serial Bit Timing (Logic 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Figure 17-9. Target Acknowledge Pulse (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Figure 17-10. Handshake Protocol at Command Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Figure 17-11. ACK Abort Procedure at the Command Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Figure 17-12. ACK Pulse and SYNC Request Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Figure 18-1. DBG Block Diagram in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Figure 18-2. DBG Block Diagram in DBG Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Figure 18-3. Debug Control Register (DBGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Figure 18-4. Debug Status and Control Register (DBGSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Figure 18-5. Debug Trace Buffer Register (DBGTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Figure 18-6. Debug Count Register (DBCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

Figure 18-7. Debug Comparator C Extended Register (DBGCCX) . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Figure 18-9. Debug Comparator C Register (DBGCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Figure 18-8. Comparator C Extended Comparison in BKP/DBG Mode . . . . . . . . . . . . . . . . . . . . . . 489

Figure 18-10. Debug Control Register 2 (DBGC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Figure 18-11. Debug Control Register 3 (DBGC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Figure 18-12. Debug Comparator A Extended Register (DBGCAX). . . . . . . . . . . . . . . . . . . . . . . . . . 494

Figure 18-13. Comparators A and B Extended Comparison in BKP Mode . . . . . . . . . . . . . . . . . . . . . 494

Figure 18-14. Debug Comparator A Register (DBGCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Figure 18-15. Debug Comparator B Extended Register (DBGCBX) . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Figure 18-16. Debug Comparator B Register (DBGCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Figure A-1. ATD Accuracy Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

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Figure 18-17. Basic PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Figure 18-18. Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Figure 18-19. MII Receive Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Figure A-2. MII Transmit Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Figure A-3. MII Asynchronous Inputs Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Figure A-4. MII Serial Management Channel Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

Figure A-5. 10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Figure A-6. 10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Figure A-7. Auto-Negotiation and Fast Link Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Figure A-8. Fast Link Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

Figure A-9. Auto-Negotiation Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

Figure A-10. Fast Link Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Figure A-11. SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure A-12. SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Figure A-13. SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure A-14. SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure A-15. Voltage Regulator — MCU Power-Up And Voltage Drops (Not Scaled). . . . . . . . . . . 546

Figure 18-20. General External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Figure B-1. MC9S12NE64 Minimum System Circuit Implementation in the 80-Pin Package . . . . 550

Figure B-2. Ethernet Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Figure C-1. 112-Pin LQFP Mechanical Drawing (Case No. 987-01) . . . . . . . . . . . . . . . . . . . . . . . . 555

Figure C-2. 80-Pin TQFP-EP Mechanical Drawing (Case No. 1355-01) . . . . . . . . . . . . . . . . . . . . . 556

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List of Tables

Table Number Title Page

Table 1-1. Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 1-2. Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 1-3. Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 1-4. Signal Properties (Sheet 1 of 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 1-5. MC9S12NE64 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 1-6. Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 1-7. Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 1-8. Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 2-1. Flash Protection/Options Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 2-2. Flash Module Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 2-3. Flash Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Table 2-4. Flash Security States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 2-5. Flash Higher Address Range Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 2-6. Flash Lower Address Range Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 2-7. Flash Normal Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 2-8. Valid Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 2-9. Flash Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 3-1. Pin Functions and Priorities (Sheet 1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 3-2. PIM Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 3-3. Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 3-4. Pulse Detection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 3-5. Port Reset State Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 3-6. Port Integration Module Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 4-1. CRG Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 4-2. RTI Frequency Divide Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 4-3. COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 4-4. MCU Configuration During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 4-5. Outcome of Clock Loss in Wait Mode (Sheet 1 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 4-6. Outcome of Clock Loss in Pseudo-Stop Mode (Sheet 1 of 3) . . . . . . . . . . . . . . . . . . . . . 186

Table 4-7. Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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Table 4-8. Reset Vector Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 4-9. CRG Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 5-1. Clock Selection Based on XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 6-1. TIM Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 6-2. Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 6-3. Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 6-4. Timer Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 6-5. Pin Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 6-6. Timer Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 6-7. TIM_16B4C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 7-1. ATD Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 7-2. Multi-Channel Wrap Around Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 7-3. External Trigger Channel Select Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 7-4. External Trigger Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 7-5. Conversion Sequence Length Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 7-6. ATD Behavior in Freeze Mode (breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 7-7. Sample Time Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 7-8. Clock Prescaler Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 7-9. Available Result Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 7-10. Left Justified, Signed and Unsigned ATD Output Codes. . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 7-11. Analog Input Channel Select Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 7-12. Special Channel Select Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 7-13. External Trigger Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 7-14. ATD_10B8C Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 8-1. SCI Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 8-2. SCI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 8-3. IRSCI Transmit Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 8-4. Loop Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 8-6. Example of 9-Bit Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 8-5. Example of 8-bit Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 8-7. Baud Rates (Example: Module Clock = 10.2 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 8-8. Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 8-9. Data Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

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Table 8-10. Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Table 8-11. SCI Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 8-12. SCI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 9-1. SPI Module Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 9-2. SS Input / Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 9-3. Bidirectional Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Table 9-4. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3). . . . . . . . . . . . . . 281

Table 9-5. Normal Mode and Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table 10-1. IIC Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 10-2. I-Bus Tap and Prescale Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 10-3. Multiplier Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 10-4. IIC Divider and Hold Values (Sheet 1 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 10-5. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Table 11-1. Permissible Encoding of MII_TXD, MII_TXEN, and MII_TXER . . . . . . . . . . . . . . . . . 323

Table 11-2. Permissible Encoding of MII_RXD, MII_RXDV, and MII_RXER. . . . . . . . . . . . . . . . . 324

Table 11-3. EMAC Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table 11-4. Transmit Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Table 11-5. MII Management Frame Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Table 11-6. Programming Examples for MDCSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Table 11-7. Buffer Mapping Configuration on System RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Table 11-8. Miscellaneous Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Table 11-9. Ethernet Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Table 11-10. Backoff Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Table 11-11. Ethernet PAUSE Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Table 11-12. Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Table 12-1. EPHY Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Table 12-2. MII Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Table 12-3. Operational Configuration While Auto-Negotiation is Disabled . . . . . . . . . . . . . . . . . . . 384

Table 13-1. VREG_PHY — Signal Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Table 13-2. VREG_PHY — Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Table 14-1. INT Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Table 14-2. Interrupt Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Table 14-3. Exception Vector Map and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 41

Table Number Title Page

Table 15-1. External System Pins Associated With MEBI (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . 410

Table 15-2. MEBI Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 15-3. MEBI Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

Table 15-4. MODC, MODB, and MODA Write Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 15-5. Mode Select and State of Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 15-6. Access Type vs. Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Table 16-1. Module Mapping Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Table 16-2. External Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

Table 16-3. Allocated EEPROM Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Table 16-4. Allocated RAM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

Table 16-5. Allocated FLASH/ROM Physical Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Table 16-6. Allocated Off-Chip Memory Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Table 16-7. Program Page Index Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Table 16-8. Select Signal Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Table 16-9. Allocated Off-Chip Memory Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 16-10. External/Internal Page Window Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 16-11. 0K Byte Physical FLASH/ROM Allocated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Table 16-12. 16K Byte Physical FLASH/ROM Allocated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Table 16-13. 48K Byte Physical FLASH/ROM Allocated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Table 16-14. 64K Byte Physical FLASH/ROM Allocated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Table 17-1. BDM Register Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Table 17-2. BDM Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Table 17-3. Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Table 17-4. Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

Table 17-5. Tag Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Table 18-1. External System Pins Associated with DBG and MEBI. . . . . . . . . . . . . . . . . . . . . . . . . . 482

Table 18-2. DBG Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Table 18-3. CAPMOD Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Table 18-4. Trigger Mode Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Table 18-5. CNT Decoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

Table 18-6. PAGSEL Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Table 18-7. Comparator C Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Table 18-8. Breakpoint Mask Bits for First Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

MC9S12NE64 Data Sheet, Rev 1.0

42 Freescale Semiconductor

Table Number Title Page

Table 18-9. Breakpoint Mask Bits for Second Address (Dual Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 492

Table 18-10. Breakpoint Mask Bits for Data Breakpoints (Full Mode). . . . . . . . . . . . . . . . . . . . . . . . . 493

Table 18-11. Comparator A or B Compares. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 18-12. Read or Write Comparison Logic Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

Table 18-13. Resolution of Mode Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 18-14. Breakpoint Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

Table A-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Table A-2. ESD and Latch-Up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Table A-3. ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Table A-4. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Table A-5. Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Table A-6. Preliminary 3.3 V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table A-7. Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table A-8. EPHY Twisted Pair Transmit Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 18-15. 3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table A-9. ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

Table A-10. 3.3-V A/D Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Table A-11. Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

Table A-12. Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Table A-13. PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

Table A-14. MII Receive Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table A-15. MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Table A-16. MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Table A-17. MII Management Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Table A-18. 10BASE-T SQE (Heartbeat) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Table A-19. 10BASE-T Jab and Unjab Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Table A-20. MII – Auto Negotiation and Fast Link Pulse Timing Parameters. . . . . . . . . . . . . . . . . . . 534

Table A-21. Auto-Negotiation and Fast Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

Table A-22. 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Table A-23. 100BASE-TX Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Table A-24. EPHY Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Table A-25. NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Table A-26. NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 43

Table Number Title Page

Table A-27. Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Table A-28. SPI Master Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Table A-29. SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Table A-30. VREG_PHY - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

Table A-31. Voltage Regulator — Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Table A-32. Expanded Bus Timing Characteristics (3.3 V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

MC9S12NE64 Data Sheet, Rev 1.0

44 Freescale Semiconductor

Chapter 1 Device Overview

1.1 Introduction

The MC9S12NE64 is a 112-/80-pin cost-effective, low-end connectivity applications MCU family. The MC9S12NE64 is composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of FLASH EEPROM, 8K bytes of RAM, Ethernet media access controller (EMAC) with integrated 10/100 Mbps Ethernet physical transceiver (EPHY), two asynchronous serial communications interface modules (SCI), a serial peripheral interface (SPI), one inter-IC bus (IIC), a 4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ATD), up to 21 pins available as keypad wakeup inputs (KWU), and two additional external asynchronous interrupts. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. Furthermore, an on-chip bandgap-based voltage regulator (VREG_PHY) generates the internal digital supply voltage of 2.5 V (VDD) from a 3.15 V to 3.45 V external supply range. The MC9S12NE64 has full 16-bit data paths throughout. The 112-pin package version has a total of 70 I/O port pins and 10 input-only pins available. The 80-pin package version has a total of 38 I/O port pins and 10 input-only pins available.

1.1.1 Features

• 16-bit HCS12 core — HCS12 CPU

– Upward compatible with M68HC11 instruction set – Interrupt stacking and programmer’s model identical to M68HC11 – Instruction queue

– Enhanced indexed addressing — Memory map and interface (MMC) — Interrupt control (INT) — Background debug mode (BDM) — Enhanced debug12 module, including breakpoints and change-of-ﬂow trace buffer (DBG) — Multiplexed expansion bus interface (MEBI) — available only in 112-pin package version

• Wakeup interrupt inputs — Up to 21 port bits available for wakeup interrupt function with digital ﬁltering

• Memory — 64K bytes of FLASH EEPROM — 8K bytes of RAM

• Analog-to-digital converter (ATD) — One 8-channel module with 10-bit resolution — External conversion trigger capability

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 45

Chapter 1 Device Overview

• Timer module (TIM) — 4-channel timer — Each channel conﬁgurable as either input capture or output compare — Simple PWM mode — Modulo reset of timer counter — 16-bit pulse accumulator — External event counting — Gated time accumulation

• Serial interfaces — Two asynchronous serial communications interface (SCI) — One synchronous serial peripheral interface (SPI) — One inter-IC bus (IIC)

• Ethernet Media access controller (EMAC) — IEEE 802.3 compliant — Medium-independent interface (MII) — Full-duplex and half-duplex modes — Flow control using pause frames — MII management function — Address recognition

– Frames with broadcast address are always accepted or always rejected – Exact match for single 48-bit individual (unicast) address – Hash (64-bit hash) check of group (multicast) addresses – Promiscuous mode

• Ethertype ﬁlter

• Loopback mode

• Two receive and one transmit Ethernet buffer interfaces

• Ethernet 10/100 Mbps transceiver (EPHY) — IEEE 802.3 compliant — Digital adaptive equalization — Half-duplex and full-duplex — Auto-negotiation next page ability — Baseline wander (BLW) correction — 125-MHz clock generator and timing recovery — Integrated wave-shaping circuitry — Loopback modes

• CRG (clock and reset generator module) — Windowed COP watchdog — Real-time interrupt

MC9S12NE64 Data Sheet, Rev 1.0

46 Freescale Semiconductor

— Clock monitor — Pierce oscillator — Phase-locked loop clock frequency multiplier — Limp home mode in absence of external clock — 25-MHz crystal oscillator reference clock

• Operating frequency — 50 MHz equivalent to 25 MHz bus speed for single chip — 32 MHz equivalent to 16 MHz bus speed in expanded bus modes

• Internal 2.5-V regulator — Supports an input voltage range from 3.3 V ± 5% — Low-power mode capability — Includes low-voltage reset (LVR) circuitry

• 80-pin TQFP-EP or 112-pin LQFP package — Up to 70 I/O pins with 3.3 V input and drive capability (112-pin package) — Up to two dedicated 3.3 V input only lines (

IRQ, XIRQ)

• Development support — Single-wire background debug™ mode (BDM) — On-chip hardware breakpoints — Enhanced DBG debug features

Introduction

1.1.2 Modes of Operation

• Normal modes — Normal single-chip mode — Normal expanded wide mode — Normal expanded narrow mode — Emulation expanded wide mode — Emulation expanded narrow mode

• Special operating modes — Special single-chip mode with active background debug mode

• Each of the above modes of operation can be configured for three low-power submodes — Stop mode — Pseudo stop mode — Wait mode

• Secure operation, preventing the unauthorized read and write of the memory contents

1.MEBI is available only in the 112-pin package and specified at a maximum speed of 16 MHz. If using MEBI from

2.5 MHz to 16 MHz, only 10BASE-T communication is available.

2.No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying

the FLASH difficult for unauthorized users.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 47

Chapter 1 Device Overview

1.1.3 Block Diagram

64K Byte FLASH EEPROM

8K Byte RAM

TEST

VDDX1,2

VDDR /

VREGEN

VDD1,2

VSS1,2

BKGD

XFC

VDDPLL VSSPLL

EXTAL

XTAL

RESET

PE0 PE1

PE2 PE3

PE4

PE5 PE6 PE7

PK0 PK1 PK2 PK3

Single-wire Background

Clock and Reset

PTE

PTK

Voltage Regulator

Debug Module

Generator

XIRQ IRQ

R/ LSTRB ECLK

DDRE

MODA MODB NOACC

XADDR14 XADDR15 XADDR16 XADDR17 XADDR18PK4

DDRE

XADDR19PK5 XCSPK6 ECS/ROMCTLPK7

Debugger

Breakpoints

CPU12

Periodic Interrupt

COP Watchdog

Clock Monitor

Expanded Bus

Interface

Multiplexed Address/Data Bus

DDRA DDRB

PTA PTB

PA 4

PA 3

PA 2

PA 1

ADDR11

ADDR10

ADDR9

DATA11

DATA10

DATA9

DATA3

DATA2

DATA1

PA 0

ADDR8

DATA8

DATA0

PB7

PB6

ADDR7

ADDR6

DATA7

DATA6

PB4

PB5

ADDR4

ADDR5

DATA4

DATA5

PHY_TXP

PHY_TXN PHY_RXP

PHY_RXN

PB3

ADDR3

DATA3

Multiplexed Wide Bus

Multiplexed Narrow Bus

PA 7

PA 6

PA 5

ADDR15

ADDR14

ADDR13

DATA15

DATA14

DATA13

DATA7

DATA6

DATA5

ADDR12

DATA12

DATA4

Signals shown in Bold are not available on the 80-pin package

Figure 1-1. MC9S12NE64 Block Diagram

PB2

PB1

ADDR2

ADDR1

DATA2

DATA1

Analog-to-Digital

Converter

Timer

Serial Communication Interface 0

Serial Communication Interface 1

Serial Peripheral Interface

IIC

MII_MDC

MII_MDIO

MII_CRS MII_COL

MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3

MII_RXCLK

MII_RXDV MII_RXER

EMAC

MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3

MII_TXCLK

MII_TXEN MII_TXER

MII

PB0

10BASE-T/

ADDR0

100BASE-TX Ethernet Physical

Transceiver

DATA0

(EPHY)

SDA SCL

VRH

VRL

VDDA

VSSA

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

IOC4 IOC5 IOC6 IOC7

RXD

TXD

RXD

TXD MISO MOSI

SCK

KWJ6 PJ6 KWJ7

KWJ0 KWJ1 KWJ2 KWJ3

KWG0 KWG1 KWG2 KWG3 KWG4 KWG5 KWG6 KWG7

KWH0 KWH1 KWH2

KWH3 KWH4 KWH5 KWH6

ACTLED

LNKLED

SPDLED

DUPLED

COLLED

PHY_RBIAS

DDRS

DDRJ

DDRG

DDRH

PAD

PTT

DDRT

PTS

PTJ

PTG

PTH

PTL

DDRL

PHY_VSSA PHY_VDDA

PHY_VSSRX PHY_VDDRX

PHY_VSSTX PHY_VDDTX

VRH VRL VDDA VSSA

PAD0 PAD1 PAD2

PAD3 PAD4 PAD5 PAD6 PAD7

PT4 PT5

PT6 PT7

PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7

PJ7 PJ0 PJ1 PJ2 PJ3

PG0 PG1 PG2 PG3 PG4 PG5 PG6

PG7

PH0 PH1 PH2 PH3 PH4 PH5 PH6

PL0

PL1

PL2

PL3 PL4

PL5 PL6

MC9S12NE64 Data Sheet, Rev 1.0

48 Freescale Semiconductor

Introduction

1.1.4 Device Memory Map

Table 1-1 shows the device register map of the MC9S12NE64 after reset. Figure 1-1 illustrates the full

device memory map with FLASH and RAM.

Table 1-1. Device Register Map Overview

Address

$0000 – $0017

$0018 – $0019 Reserved 2

$001A – $001B Device ID register (PARTID) 2

$001C – $001F CORE (MEMSIZ,

$0020 – $002F CORE (DBG) 16

$0030 – $0033 CORE (PPAGE, Port K — MEBI, MMC) 4

$0034 – $003F Clock and Reset Generator (PLL, RTI, COP) 12

$0040 – $006F Standard Timer 16-bit 4 channels (TIM) 48

$0070 – $007F Reserved 16

$0080 – $009F Analog-to-Digital Converter 10-bit, 8-channel (ATD) 32

$00A0 – $00C7 Reserved 40

$00C8 – $00CF Serial Communications Interface 0 (SCI0) 8

$00D0 – $00D7 Serial Communications Interface 1 (SCI1) 8

$00D8 – $00DF Serial Peripheral Interface (SPI) 8

$00E0 – $00E7 Inter IC Bus (IIC) 8

$00E8 – $00FF Reserved 24

$0100 – $010F FLASH Control Register 16

$0110 – $011F Reserved 16

$0120 – $0123 Ethernet Physical Interface (EPHY) 4

$0124 – $013F Reserved 28

$0140 – $016F Ethernet Media Access Controller (EMAC) 48

$0170 – $023F Reserved 208

$0240 – $026F Port Integration Module (PIM) 48

$0270 – $03FF Reserved 400

Information about the HCS12 core can be found in the MMC, INT, MEBI, BDM, and DBG block description chapters in this data sheet, and also in the HCS12 CPU Reference Manual, S12CPUV2/D.

CORE (Ports A, B, E, Modes, Inits — MMC, INT, MEBI)

Module

IRQ, HPRIO — INT, MMC) 4

Size

(in Bytes)

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 49

Chapter 1 Device Overview

This ﬁgure shows a suggested map, which is not the map out of reset. After reset the map is:

$0000 – $03FF: register space $0000 – $1FFF: 7K RAM (1K RAM hidden behind register space)

$0000 $0400

$2000

$4000

$8000

$C000

$FF00 $FFFF

VECTORS

NORMAL

SINGLE CHIP

EXT

VECTORS

EXPANDED SPECIAL

VECTORS

SINGLE CHIP

$0000

$03FF

$2000

$3FFF

$4000

$7FFF

$8000

$BFFF

$C000

$FFFF

$FF00

$FFFF

1K REGISTER SPACE

MAPPABLE TO ANY 2K BOUNDARY

8K BYTES RAM

MAPPABLE TO ANY 8K BOUNDARY

0.5K, 1K, 2K, OR 4K PROTECTED SECTOR

16K FIXED FLASH EEPROM

16K PAGE WINDOW FOUR * 16K FLASH EEPROM PAGES

16K FIXED FLASH EEPROM

2K, 4K, 8K, OR 16K PROTECTED BOOT SECTOR

BDM (IF ACTIVE)

Figure 1-2. MC9S12NE64 User Conﬁgurable Memory Map

1.1.5 Detailed Register Map

The following tables show the register maps of the MC9S12NE64. For detailed information about register functions, please see the appropriate block description chapter.

MC9S12NE64 Data Sheet, Rev 1.0

50 Freescale Semiconductor

Introduction

$0000 - $000F Multiplexed External Bus Interface Module (MEBI) Map 1 of 3

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0000 PORTA

$0001 PORTB

$0002 DDRA

$0003 DDRB

$0004 Reserved

$0005

–$0007

$0008 PORTE

$0009 DDRE

$000A PEAR

$000B MODE

$000C PUCR

$000D RDRIV

$000E EBICTL

$000F Reserved

Reserved

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

Bit 7 654321Bit 0

Bit 7 65432

NOACCE

MODC MODB MODA

PUPKE

RDPK

PIPOE NECLK LSTRE RDWE

PUPEE

RDPE

IVIS

1 Bit 0

EMK EME

PUPBE PUPAE

RDPB RDPA

ESTR

$0010 - $0014 Module Mapping Control Module (MMC) Map 1 of 4

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0010 INITRM

$0011 INITRG

$0012 INITEE

$0013 MISC

$0014 MTST0

Freescale Semiconductor 51

Read:

Write:

Write:

Read:

Write:

Write:

Read: Bit 7 654321Bit 0

Write:

RAM15 RAM14 RAM13 RAM12 RAM11

REG14 REG13 REG12 REG11

EE15 EE14 EE13 EE12 EE11

EXSTR1 EXSTR0 ROMHM ROMON

MC9S12NE64 Data Sheet, Rev 1.0

000

RAMHAL

EEON

Chapter 1 Device Overview

$0015 - $0016 Interrupt Module (INT) Map 1 of 2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0015 ITCR

$0016 ITEST

Write:

Read:

Write:

INTE INTC INTA INT8 INT6 INT4 INT2 INT0

WRTINT ADR3 ADR2 ADR1 ADR0

$0017 - $0017 Module Mapping Control Module (MMC) Map 2 of 4

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0017 MTST1

Read: Bit 7 654321Bit 0

Write:

$0018 - $0019 Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0018 –

$0019

Reserved

Write:

$001A - $001B Miscellaneous Peripherals

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001A PARTIDH

$001B PARTIDL

Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8

Write:

Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Write:

$001C - $001D Module Mapping Control Module (MMC) Map 3 of 4

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

REG_SW0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0

$001C MEMSIZ0

$001D MEMSIZ1

Read:

Write:

ROM_SW1 ROM_SW0 0000PAG_SW1 PAG_SW0

Read:

Write:

$001E - $001E Multiplexed External Bus Interface Module (MEBI) Map 2 of 3

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001E IRQCR

Read:

Write:

IRQE IRQEN

000000

MC9S12NE64 Data Sheet, Rev 1.0

52 Freescale Semiconductor

Introduction

$001F - $001F Interrupt Module (INT) Map 2 of 2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001F HPRIO

Read:

Write:

PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1

$0020 - $002F Debug Module (DBG) Including BKP Map 1 of 1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0020 DBGC1

$0021 DBGSC

$0022 DBGTBH

$0023 DBGTBL

$0024 DBGCNT

$0025 DBGCCX

$0026 DBGCCH

$0027 DBGCCL

$0028

$0029

$002A

$002B

$002C

$002D

$002E

$002F

Legacy HCS12 MCUs used this name for this register.

DBGC2 Read:

(BKPCT0)

DBGC3 Read:

(BKPCT1)

DBGCAX Read:

(BKP0X)

DBGCAH Read:

(BKP0H)

DBGCAL Read:

(BKP0L)

DBGCBX Read:

(BKP1X)

DBGCBH Read:

(BKP1H)

DBGCBL Read:

(BKP1L)

Read:

Write:

DBGEN ARM TRGSEL BEGIN DBGBRK

Read: AF BF CF 0

Write:

Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Write:

Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Write:

Read: TBF 0 CNT

Write:

Read:

Write:

Read:

Write:

Read:

Write:

PAGSEL EXTCMP

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC

BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB

PAGSEL EXTCMP

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

PAGSEL EXTCMP

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CAPMOD

TRG

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 53

Chapter 1 Device Overview

$0030 - $0031 Module Mapping Control Module (MMC) Map 4 of 4

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0030 PPAGE

$0031 Reserved

Write:

Write:

PIX5 PIX4 PIX3 PIX2 PIX1 PIX0

$0032 - $0033 Multiplexed External Bus Interface Module (MEBI) Map 3 of 3

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0032 PORTK

$0033 DDRK

Read:

Write:

Read:

Write:

Bit 7 654321Bit 0

$0034 - $003F Clock and Reset Generator (CRG)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0034 SYNR

$0035 REFDV

$0036

$0037 CRGFLG

$0038 CRGINT

$0039 CLKSEL

$003A PLLCTL

$003B RTICTL

$003C COPCTL

$003D

$003E

$003F ARMCOP

CTFLG

Reserved

FORBYP

Reserved

CTCTL

Reserved

Write:

Write:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Read:

Write:

Write:

Write:

Write: Bit 7 654321Bit 0

RTIF PORF LVRF LOCKIF

RTIE

PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI

CME PLLON AUTO ACQ

WCOP RSBCK

RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0

SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

REFDV3 REFDV2 REFDV1 REFDV0

LOCK TRACK

LOCKIE

000

PRE PCE SCME

CR2 CR1 CR0

SCMIF

SCMIE

SCM

MC9S12NE64 Data Sheet, Rev 1.0

54 Freescale Semiconductor

Introduction

$0040 - $006F 16-Bit, 4-Channel Timer Module (TIM) (Sheet 1 of 2)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0040 TIOS

$0041 CFORC

$0042 OC7M

$0043 OC7D

$0044 TCNT (hi)

$0045 TCNT (lo)

$0046 TSCR1

$0047 TTOV

$0048 TCTL1

$0049 Reserved

$004A TCTL3

$004B Reserved

$004C TIE

$004D TSCR2

$004E TFLG1

$004F TFLG2

$0050 –

$0057

Reserved

$0058 TC4 (hi)

$0059 TC4 (lo)

$005A TC5 (hi)

$005B TC5 (lo)

$005C TC6 (hi)

Read:

Write:

IOS7 IOS6 IOS5 IOS4

Write: FOC7 FOC6 FOC5 FOC4

Read:

Write:

Read:

Write:

OC7M7 OC7M6 OC7M5 OC7M4

OC7D7 OC7D6 OC7D5 OC7D4

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Read: Bit 7 654321Bit 0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

TEN TSWAI TSFRZ TFFCA

TOV7 TOV6 TOV5 TOV4

OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4

Write:

Read:

Write:

EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

C7I C6I C5I C4I

TOI

000

C7F C6F C5F C4F

TOF

0000000

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

0000

TCRE PR2 PR1 PR0

0000

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 55

Chapter 1 Device Overview

$0040 - $006F 16-Bit, 4-Channel Timer Module (TIM) (Sheet 2 of 2)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$005D TC6 (lo)

$005E TC7 (hi)

$005F TC7 (lo)

$0060 PACTL

$0061 PAFLG

$0062 PACNT (hi)

$0063 PACNT (lo)

$0064 –

$006F

Reserved

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

Read:

Write:

Read:

Write:

Write:

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

PAOVF PAIF

$0080 - $009F 10-Bit, 8-Channel Analog-to-Digital Converter Module (ATD)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0080 ATDCTL0

$0081 ATDCTL1

$0082 ATDCTL2

$0083 ATDCTL3

$0084 ATDCTL4

$0085 ATDCTL5

$0086 ATDSTAT0

$0087 Reserved

$0088

$0089 ATDTEST1

$008A Unimplemented

$008B ATDSTAT1

ATDTEST0

Reserved

Write:

Read:

Write:

Read:

Write:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Read: UUUUUUUU

Write:

Read: U U 00000

Write:

Read: UUUUUUUU

Write:

Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0

Write:

ETRIG

SEL

ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE

SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0

DJM DSGN SCAN MULT

SCF

0000

S8C S4C S2C S1C FIFO FRZ1 FRZ0

ETORF FIFOR

0 CC2 CC1 CC0

WRAP2 WRAP1 WRAP0

ETRIG

CH2

CC CB CA

ETRIG

CH1

ETRIG

ASCIF

CH0

MC9S12NE64 Data Sheet, Rev 1.0

56 Freescale Semiconductor

Introduction

$0080 - $009F 10-Bit, 8-Channel Analog-to-Digital Converter Module (ATD)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$008C Unimplemented

$008D ATDDIEN

$008E Unimplemented

$008F PORTAD

$0090 ATDDR0H

$0091 ATDDR0L

$0092 ATDDR1H

$0093 ATDDR1L

$0094 ATDDR2H

$0095 ATDDR2L

$0096 ATDDR3H

$0097 ATDDR3L

$0098 ATDDR4H

$0099 ATDDR4L

$009A ATDDR5H

$009B ATDDR5L

$009C ATDDR6H

$009D ATDDR6L

$009E ATDDR7H

$009F ATDDR7L

Read: UUUUUUUU

Write:

Read:

Write:

Read: UUUUUUUU

Write:

Read: PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0

$00A0 - $00C7 Reserved

$00A0

– $00C7

Freescale Semiconductor 57

Reserved

Write:

MC9S12NE64 Data Sheet, Rev 1.0

Chapter 1 Device Overview

$00C8 - $00CF Asynchronous Serial Communications Interface Module (SCI0)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00C8 SCIBDH

$00C9 SCIBDL

$00CA SCICR1

$00CB SCICR2

$00CC SCISR1

$00CD SCISR2

$00CE SCIDRH

$00CF SCIDRL

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

Write:

Read: R8

Write:

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

LOOPS SCISWAI RSRC M WAKE ILT PE PT

TIE TCIE RIE ILIE TE RE RWU SBK

BRK13 TXDIR

000000

RAF

$00D0 - $00D7 Asynchronous Serial Communications Interface Module (SCI1)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00D0 SCIBDH

$00D1 SCIBDL

$00D2 SCICR1

$00D3 SCICR2

$00D4 SCISR1

$00D5 SCISR2

$00D6 SCIDRH

$00D7 SCIDRL

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

Write:

Read: R8

Write:

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

LOOPS SCISWAI RSRC M WAKE ILT PE PT

TIE TCIE RIE ILIE TE RE RWU SBK

BRK13 TXDIR

000000

RAF

MC9S12NE64 Data Sheet, Rev 1.0

58 Freescale Semiconductor

Introduction

$00D8 - $00DF Serial Peripheral Interface Module (SPI)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00D8 SPICR1

$00D9 SPICR2

$00DA SPIBR

$00DB SPISR

$00DC Reserved

$00DD SPIDR

$00DE Reserved

$00DF Reserved

Read:

Write:

Write:

Write:

Read: SPIF 0 SPTEF MODF 0000

Write:

Write:

Read:

Write:

Write:

Write:

SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

MODFEN BIDIROE

SPPR2 SPPR1 SPPR0

Bit7 654321Bit0

SPISWAI SPC0

SPR2 SPR1 SPR0

$00E0 - $00E7 Inter-IC Bus Module (IIC)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00E0 IBAD

$00E1 IBFD

$00E2 IBCR

$00E3 IBSR

$00E4 IBDR

$00E5 –

$00E7

Reserved

Read:

Write:

Read:

Write:

Read:

Write: RSTA

Read: TCF IAAS IBB

Write:

Read:

Write:

Write:

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1

IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0

IBEN IBIE MS/

D7 D6 D5 D4 D3 D2 D1 D0

SL Tx/Rx TXAK

IBAL

0 SRW

IBIF

IBSWAI

RXAK

$00E8 - $00FF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00E8-

$00FF

Reserved

Write:

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 59

Chapter 1 Device Overview

$0100 - $010F FLASH Control Register (fts64k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0100 FCLKDIV

$0101 FSEC

$0102 Reserved

$0103 FCNFG

$0104 FPROT

$0105 FSTAT

$0106 FCMD

$0107 –

$010F

Reserved

Read: FDIVLD

Write:

Read: KEYEN NV6 NV5 NV4 NV3 NV2 SEC1 SEC0

Write:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

CBEIE CCIE KEYACC

FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0

CBEIF

PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0

CCIF

CMDB6 CMDB5

00000

PVIOL ACCERR

0 BLANK 0 0

CMDB2

CMDB0

$0110 - $011F Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0110

– $011F

Reserved

Write:

$0120 - $0123 Ethernet Physical Transceiver Module (EPHY)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0120 EPHYCTL0

$0121 EPHYCTL1

$0122 EPHYSR

$0123

EPHYTST

Reserved

Read:

EPHYEN ANDIS DIS100 DIS10 LEDEN EPHYWAI

Write:

Write:

Read: 0 0 100DIS 10DIS 0 0 0

Write:

Write:

PHYADD4 PHYADD3 PHYADD2 PHYADD1 PHYADD0

EPHYIEN

EPHYIF

$0124 - $013F Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0124

– $013F

Reserved

Write:

MC9S12NE64 Data Sheet, Rev 1.0

60 Freescale Semiconductor

Introduction

$0140 - $016F Ethernet Media Access Controller (EMAC)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0140 NETCTL

$0141 Reserved

$0142 Reserved

$0143 RXCTS

$0144 TXCTS

$0145 ETCTL

$0146 ETYPE

$0147 ETYPE

$0148 PTIME

$0149 PTIME

$014A

$014B

$0141C

$014D

IEVENT

[15:8]

IEVENT

[7:0]

IMASK

[15:8]

IMASK

[7:0]

$014E SWRST

$014F Reserved

$0150 MPADR

$0151 MRADR

$0152 MWDATA

$0123 MWDATA

$0154 MRDATA

$0155 MRDATA

Read:

Write:

EMACE

Write:

Write:

Read: RXACT 0 0

Write:

Read: TXACT 0

Write:

Read:

Write:

FPET

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

RFCIF

MMCIF

RFCIE

MMCIE

MACRST

Write:

Write:

Write:

Write:

Read:

Write:

Read:

Write:

Read: RDATA[15:8]

Write:

Read: RDATA[7:0]

Write:

ESWAI EXTPHY MLB FDX

RFCE

CSLF PTRC SSB

BREIF RXEIF RXAOIF RXBOIF RXACIF RXBCIF

LCIF ECIF

BREIE RXEIE RXAOIE RXBOIE RXACIE RXBCIE

LCIE ECIE

FEMW FIPV6 FARP FIPV4 FIEEE

ETYPE[15:8]

ETYPE[7:0]

PTIME[15:8]

PTIME[7:0]

WDATA[15:8]

WDATA[7:0]

PROM CONMC BCREJ

000

TXCIF

TXCIE

PADDR

RADDR

TCMD

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 61

Chapter 1 Device Overview

$0140 - $016F Ethernet Media Access Controller (EMAC) (Continued)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0156 MCMST

$0157 Reserved

$0158

$0159

$015A

$015B

$015C

$015D

$015E

BUFCFG

[15:8]

BUFCFG

[7:0]

RXAEFP

[15:8]

RXAEFP

[7:0]

RXBEFP

[15:8]

RXBEFP

[7:0]

TXEFP

[15:8]

$015F TXEFP

$0160 MCHASH

$0161 MCHASH

$0162 MCHASH

$0163 MCHASH

$0164 MCHASH

$0165 MCHASH

$0166 MCHASH

$0167 MCHASH

$0168 MACAD

$0169 MACAD

$016A MACAD

$016B MACAD

$016C MACAD

Read: 0 0 BUSY

Write: OP

NOPRE MDCSEL

Write:

Write:

Read:

Write:

BUFMAP

MAXFL[7:0]

Write:

Read:

Write:

RXAEFP[7:0]

Write:

Read:

Write:

RXBEFP[7:0]

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

TXEFP[7:0]

MCHASH[63:56]

MCHASH[55:48]

MCHASH[47:40]

MCHASH[39:32]

MCHASH[31:24]

MCHASH[23:16]

MCHASH[15:8]

MCHASH[63:56]

MACAD0[55:48]

MACAD1[47:32]

MACAD2[31:24]

MACAD3[23:16]

MACAD4[15:8]

MAXFL[10:8]

RXAEFP[10:8]

RXBEFP[10:8]

TXEFP[10:8]

MC9S12NE64 Data Sheet, Rev 1.0

62 Freescale Semiconductor

Introduction

$0140 - $016F Ethernet Media Access Controller (EMAC) (Continued)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$016D MACAD

$016E EMISC

$016F EMISC

Read:

Write:

Read:

Write:

Read: MISC[7:0]

Write:

INDEX

MACAD5[7:0]

0 0 MISC[10:8]

$0170 - $023F Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0170

- $023F

Reserved

Write:

$0240 - $026F Port Integration Module (PIM) (Sheet 1 of 3)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0240 PTT

$0241 PTIT

$0242 DDRT

$0243 RDRT

$0244 PERT

$0245 PPST

$0246 Reserved

$0247 Reserved

$0248 PTS

$0249 PTIS

$024A DDRS

$024B RDRS

$024C PERS

$024D PPSS

Read:

Write:

Read: PTIT7 PTIT6 PTIT5 PTIT4 0000

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

Read:

Write:

Read: PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

PTT7 PTT6 PTT5 PTT4

DDRT7 DDRT6 DDRT5 DDRT4

RDRT7 RDRT6 RDRT5 RDRT4

PERT7 PERT6 PERT5 PERT4

PPST7 PPST6 PPST5 PPST4

PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0

DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0

RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0

PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0

PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0

0000

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 63

Chapter 1 Device Overview

$0240 - $026F Port Integration Module (PIM) (Sheet 2 of 3)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$024E WOMS

$024F Reserved

$0250 PTG

$0251 PTIG

$0252 DDRG

$0253 RDRG

$0254 PERG

$0255 PPSG

$0256 PIEG

$0257 PIFG

$0258 PTH

$0259 PTIH

$025A DDRH

$025B RDRH

$025C PERH

$025D PPSH

$025E PIEH

$025F PIFH

$0260 PTJ

$0262 PTIJ

$0262 DDRJ

$0263 RDRJ

$0264 PERJ

Read:

WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0

Write:

Write:

Read:

Write:

PTG7 PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0

Read: PTIG7 PTIG6 PTIG5 PTIG4 PTIG3 PTIG2 PTIG1 PTIG0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0

RDRG7 RDRG6 RDRG5 RDRG4 RDRG3 RDRG2 RDRG1 RDRG0

PERG7 PERG6 PERG5 PERG4 PERG3 PERG2 PERG1 PERG0

PPSG7 PPSG6 PPSG5 PPSG4 PPSG3 PPSG2 PPSG1 PPSG0

PIEG7 PIEG6 PIEG5 PIEG4 PIEG3 PIEG2 PIEG1 PIEG0

PIFG7 PIFG6 PIFG5 PIFG4 PIFG3 PIFG2 PIFG1 PIFG0

PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0

Read: 0 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0

Write:

Write:

Write:

Write:

Write:

Write:

Write:

Read:

Write:

PTJ7 PTJ6

DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0

RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0

PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0

PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0

PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0

PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0

Read: PTIJ7 PTIJ6 0 0 PTIJ3 PTIJ2 PTIJ1 PTIJ0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

DDRJ7 DDRJ6

RDRJ7 RDRJ6

PERJ7 PERJ6

PTJ3 PTJ2 PTJ1 PTJ0

DDRJ3 DDRJ2 DDRJ1 DDRJ0

RDRJ3 RDRJ2 RDRJ1 RDRJ0

PERJ3 PERJ2 PERJ1 PERJ0

MC9S12NE64 Data Sheet, Rev 1.0

64 Freescale Semiconductor

Introduction

$0240 - $026F Port Integration Module (PIM) (Sheet 3 of 3)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0265 PPSJ

$0266 PIEJ

$0267 PIFJ

$0268 PTL

$0269 PTIL

$026A DDRL

$026B RDRL

$026C PERL

$026D PPSL

$026E WOML

$026F Reserved

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Read: 0 PTIL6 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0

Write:

Write:

Write:

Write:

Write:

Write:

Write:

PPSJ7 PPSJ6

PIEJ7 PIEJ6

PIFJ7 PIFJ6

PTL6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0

DDRL6 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0

RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0

PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0

PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0

WOML6 WOML5 WOML4 WOML3 WOML2 WOML1 WOML0

PPSJ3 PPSJ2 PPSJ1 PPSJ0

PIEJ3 PIEJ2 PIEJ1 PIEJ0

PIFJ3 PIFJ2 PIFJ1 PIFJ0

$0270 - $03FF Reserved Space

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0270

– $3FF

Reserved

Write:

1.1.6 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the MCU. Table 1-2 shows the assigned part ID number.

Table 1-2. Assigned Part ID Numbers

Device Mask Set Number

MC9S12NE64 0L19S $8200 MC9S12NE64 1L19S $8201

The coding is as follows:

Bit 15-12: Major family identiﬁer Bit 11-8: Minor family identiﬁer Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor (or non full) mask set revision

Part ID

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 65

Chapter 1 Device Overview

The PRTIDH register is constructed of four hexadecimal digits (0xABCD) as follows:

Digit “A” = Family ID Digit “B” = Memory ID (ﬂash size) Digit “C” = Major mask revision Digit “D” = Minor mask revision

Currently, family IDs are:

0x0 = D family 0x1 = H family 0x2 = B family 0x3 = C family 0x4 = T family 0x5 = E family 0x6 = reserved 0x7 = reserved 0x8 = NE family

Current memory IDs are:

0x0 = 256K 0x1 = 128K 0x2 = 64K 0x3 = 32K 0x4 = 512K

The major and minor mask revision increments from 0x0 as follows:

• Major mask increments on a complete (full/all layer) mask change.

• Minor mask increments on a single or smaller than full mask change.

The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-3 shows the read-only values of these registers. See the module mapping and control (MMC) block description chapter for further details.

Table 1-3. Memory Size Registers

MC9S12NE64 MEMSIZ0 $03 MC9S12NE64 MEMSIZ1 $80

1.2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals.

MC9S12NE64 Data Sheet, Rev 1.0

66 Freescale Semiconductor

Signal Description

1.2.1 Device Pinout

The MC9S12NE64 is available in a 112-pin low-proﬁle quad ﬂat pack (LQFP) and in an 80-pin quad ﬂat pack (TQFP-EP). Most pins perform two or more functions, as described in this section. Figure 1-3 and

Figure 1-4 show the pin assignments.

1.2.1.1 112-Pin LQFP

ECS/ROMCTL

XCS

PJ6/KWJ6/IIC_SDA

PJ7/KWJ7/IIC_SCL

PT4/TIM_IOC4

PT5/TIM_IOC5

PT6/TIM_IOC6

PT7/TIM_IOC7

PK7/

PK6/

PK5/XADDR19

PK4/XADDR18

VDD1

VSS1

PK3/XADDR17

PK2/XADDR16

PK1/XADDR15

PK0/XADDR14

VSSA

VRL

VRH

VDDA

PAD7/AN7

PAD6/AN6

PAD5/AN5

PAD4/AN4

PAD3/AN3

PAD2/AN2

PAD1/AN1

PAD0/AN0

MII_TXER/KWH6/PH6 MII_TXEN/KWH5/PH5

MII_TXCLK/KWH4/PH4

MII_TXD3/KWH3/PH3 MII_TXD2/KWH2/PH2 MII_TXD1/KWH1/PH1 MII_TXD0/KWH0/PH0

MII_MDC/KWJ0/PJ0

MII_MDIO/KWJ1/PJ1

ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3

VDDX1

VSSX1 ADDR4/DATA4/PB4 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7

MII_CRS/KWJ2/PJ2

MII_COL/KWJ3/PJ3 MII_RXD0/KWG0/PG0 MII_RXD1/KWG1/PG1 MII_RXD2/KWG2/PG2 MII_RXD3/KWG3/PG3

MII_RXCLK/KWG4/PG4

MII_RXDV/KWG5/PG5

MII_RXER/KWG6/PG6

112

111

110

109

108

107

106

105

104

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Signals shown in Bold are not available on the 80-pin package

293031323334353637383940414243444546474849505152535455

103

999897969594939291908988878685

102

101

100

112-PIN LQFP

PL0/ACTLED

PL1/LNKLED

VDDR

PL2/SPDLED

PA7/ADDR15/DATA15

PA6/ADDR14/DATA14

PA5/ADDR13/DATA13

PA4/ADDR12/DATA12

PHY_VSSRX

PHY_VDDRX

PHY_RXN

PHY_RXP

PHY_VSSTX

PHY_TXN

PHY_TXP

PHY_VDDTX

PHY_VDDA

PHY_VSSA

PHY_RBIAS

VDD2

VSS2

PA3/ADDR11/DATA11

PA2/ADDR10/DATA10

PA1/ADDR9/DATA9

PA0/ADDR8/DATA8

PL3/DUPLED

PL4/COLLED

BKGD/MODC/

TAGHI

PL6

XTAL

TEST

PL5

LSTRB/TAGLO/PE3

W/PE2

IRQ/PE1

XIRQ/PE0

KWG7/PG7

SCI0_TXD/PS1

SCI1_TXD/PS3

SCI0_RXD/PS0

SCI1_RXD/PS2

SS/PS7

SPI_

NOACC/PE7

SPI_SCK/PS6

SPI_MISO/PS4

SPI_MOSI/PS5

VSSX2

RESET

VDDX2

ECLK/PE4

MODA/IPIPE0/PE5

MODB/IPIPE1/PE6

VDDPLL

XFC

VSSPLL

EXTAL

Figure 1-3. Pin Assignments in 112-Pin LQFP for MC9S12NE64

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 67

Chapter 1 Device Overview

1.2.1.2 80-Pin TQFP-EP

The MEBI is not available in the 80-pin package. The 80-pin package features an exposed tab that is used for enhanced thermal management. The exposed tab requires special PCB layout considerations as described in Appendix B, “Schematic and PCB Layout Design Recommendations.”

PJ6/KWJ6/IIC_SDA

PJ7/KWJ7/IIC_SCL

PT4/TIM_IOC4/

PT5/TIM_IOC5

PT6/TIM_IOC6

PT7/TIM_IOC7

VDD1

VSS1

VSSA

VRL

VRH

VDDA

PAD7/AN7

PAD6/AN6

PAD5/AN5

PAD4/AN4

PAD3/AN3

PAD2/AN2

PAD1/AN1

PAD0/AN0

MII_TXER/KWH6/PH6 MII_TXEN/KWH5/PH5

MII_TXCLK/KWH4/PH4

MII_TXD3/KWH3/PH3 MII_TXD2/KWH2/PH2 MII_TXD1/KWH1/PH1 MII_TXD0/KWH0/PH0

MII_MDC/KWJ0/PJ0

MII_MDIO/KWJ1/PJ1

VDDX1

VSSX1 MII_CRS/KWJ2/PJ2 MII_COL/KWJ3/PJ3

MII_RXD0/KWG0/PG0 MII_RXD1/KWG1/PG1 MII_RXD2/KWG2/PG2 MII_RXD3/KWG3/PG3

MII_RXCLK/KWG4/PG4

MII_RXDV/KWG5/PG5 MII_RXER/KWG6/PG6

80797877767574737271706968676665646362

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21222324252627282930313233343536373839

80-PIN TPFP-EP

XFC

VSSPLL

VDDPLL

EXTAL

SPI_MISO/PS4

SCI0_TXD/PS1

SCI1_TXD/PS3

SCI0_RXD/PS0

SCI1_RXD/PS2

VSSX2

SS/PS7

ECLK/PE4

SPI_

SPI_SCK/PS6

SPI_MOSI/PS5

VDDX2

RESET

XTAL

TEST

IRQ/PE1

PL0/ACTLED

PL1/LNKLED

VDDR

PL2/SPDLED

PHY_VSSRX

PHY_VDDRX

PHY_RXN

PHY_RXP

PHY_VSSTX

PHY_TXN

PHY_TXP

PHY_VDDTX

PHY_VDDA

PHY_VSSA

PHY_RBIAS

VDD2

VSS2

PL3/DUPLED

PL4/COLLED

BKGD/MODC

XIRQ/PE0

Figure 1-4. Pin Assignments in 80-Pin TQFP-EP for MC9S12NE64

MC9S12NE64 Data Sheet, Rev 1.0

68 Freescale Semiconductor

1.2.2 Signal Properties Summary

Table 1-4. Signal Properties (Sheet 1 of 4)

Signal Description

orig. order

28 1 1 PH6 KWH6 MII_TXER VDDX

29 2 2 PH5 KWH5 MII_TXEN VDDX

30 3 3 PH4 KWH4

31 4 4 PH3 KWH3 MII_TXD3 VDDX

32 5 5 PH2 KWH2 MII_TXD2 VDDX

33 6 6 PH1 KWH1 MII_TXD1 VDDX

34 7 7 PH0 KWH0 MII_TXD0 VDDX

40 8 8 PJ0 KWJ0 MII_MDC VDDX

39 9 9 PJ1 KWJ1 MII_MDIO VDDX

15 —

62 10 14 VDDX1 — — See Table 1-5

63 11 15 VSSX1 — — See Table 1-5

38 12 20 PJ2 KWJ2 MII_CRS VDDX

37 13 21 PJ3 KWJ3 MII_COL VDDX

27 14 22 PG0 KWG0 MII_RXD0 VDDX

26 15 23 PG1 KWG1 MII_RXD1 VDDX

80 Pin

No.

112 Pin

No.

10–13 16–19

Name

Function

PB[7:0]

Name

Function

ADDR[7:0]

DATA[7:0]

Name

Function

MII_TXCLK

— VDDX PUCR Disabled

Power

Domain

VDDX

Internal Pull

Resistor

CTRL

PERH/

PPSH

PERH/

PPSH

PERH/

PPSH

PERH/

PPSH

PERH/

PPSH

PERH/

PPSH

PERH/

PPSH

PERJ/

PPSJ

PERJ/

PPSJ

PERJ/

PPSJ

PERJ/

PPSJ

PERG/

PPSG

PERG/

PPSG

Reset

State

Disabled

Port H I/O pin; EMAC MII transmit error; interrupt

Port H I/O pin; EMAC MII transmit enable; interrupt

Port H I/O pin; EMAC MII transmit clock; interrupt

Port H I/O pin; EMAC MII transmit data; interrupt

Port J I/O pin; EMAC MII management data clock; interrupt

Port J I/O pin; EMAC MII management data I/O; interrupt

Port B I/O pin; multiplexed address/data

Port J I/O pin; EMAC MII carrier sense; interrupt

Port J I/O pin; EMAC MII collision; interrupt

Port G I/O pin; EMAC MII receive data; interrupt

Description

Reset

State

Input

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 69

Chapter 1 Device Overview

Table 1-4. Signal Properties (Sheet 2 of 4)

orig. order

25 16 24 PG2 KWG2 MII_RXD2 VDDX

24 17 25 PG3 KWG3 MII_RXD3 VDDX

23 18 26 PG4 KWG4 MII_RXCLK VDDX

22 19 27 PG5 KWG5 MII_RXDV VDDX

21 20 28 PG6 KWG6 MII_RXER VDDX

20 — 29 PG7 KWG7 — VDDX

55 21 30 PS0 SCI0_RXD — VDDX

54 22 31 PS1 SCI0_TXD — VDDX

53 23 32 PS2 SCI1_RXD — VDDX

52 24 33 PS3 SCI1_TXD — VDDX

51 25 34 PS4 SPI_MISO — VDDX

50 26 35 PS5 SPI_MOSI — VDDX

49 27 36 PS6 SPI_SCK — VDDX

48 28 37 PS7 SPI_

6 — 38 PE7 NOACC — VDDX PUCR Up

7 — 39 PE6 IPIPE1 MODB VDDX

8 — 40 PE5 IPIPE0 MODA VDDX

9 29 41 PE4 ECLK — VDDX PUCR Up

64 30 42 VSSX2 — — See Table 1-5

65 31 43 VDDX2 — — See Table 1-5

80 Pin

No.

112 Pin

No.

Name

Function

Name

Function

SS — VDDX

Name

Function

Power

Domain

Internal Pull

Resistor

CTRL

PERG/

PPSG

PERG/

PPSG

PERG/

PPSG

PERG/

PPSG

PERG/

PPSG

PERG/

PPSG

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

While

pin is low: Down

While RESET

pin is low: Down

Reset

State

Disabled

RESET

Port G I/O pin; EMAC MII receive data; interrupt

Port G I/O pin; EMAC MII receive clock; interrupt

Port G I/O pin; EMAC MII receive data valid; interrupt

Port G I/O pin; EMAC MII receive error; interrupt

Port G I/O pin; interrupt

Port S I/O pin; SCI0 receive signal

Port S I/O pin; SCI0 transmit signal

Port S I/O pin; SCI1 receive signal

Port S I/O pin; SCI1 transmit signal

Port S I/O pin; SPI MISO signal

Port S I/O pin; SPI MOSI signal

Port S I/O pin; SPI SCK signal

Port S I/O pin; SPI SS signal

Port E I/O pin; access

Port E I/O pin; pipe status; mode selection

Port E I/O pin; bus clock output

Description

Reset

State

Input

MC9S12NE64 Data Sheet, Rev 1.0

70 Freescale Semiconductor

Table 1-4. Signal Properties (Sheet 3 of 4)

Signal Description

Internal Pull

Resistor

CTRL

Reset

Description

State

orig. order

80 Pin

No.

4 32 44

112 Pin

No.

Name

Function

Name

Function

Name

Function

Power

Domain

RESET — — VDDX None None External reset pin Input

66 33 45 VDDPLL — — See Table 1-5

3 34 46 XFC — — VDDPLL NA NA PLL ﬁlter pin

67 35 47 VSSPLL — — See Table 1-5

1 36 48 EXTAL — — VDDPLL NA NA

2 37 49 XTAL — — VDDPLL NA NA Output

Oscillator pins

68 38 50 TEST — — VDDX None None Must be grounded Input

41 — 51 PL6 — — VDDX

42 — 52 PL5 — — VDDX

PERL/

PPSL

PERL/

PPSL

Disabled Port L I/O pin Input

Port E I/O pin; low

10 — 53 PE3

TAGLO LSTRB VDDX PUCR Up

strobe; tag signal low

Port E I/O pin; R/

11 — 54 PE2 R/

W — VDDX PUCR Up

in expanded modes

12 39 55 PE1

IRQ — VDDX PUCR Up

Port E input; external interrupt pin

Port E input;

13 40 56 PE0

XIRQ — VDDX PUCR Up

non-maskable interrupt pin

Background debug;

5 41 57 BKGD MODC TAGHI VDDX None Up

mode pin; tag signal high

43 42 58 PL4 COLLED — VDDX

44 43 59 PL3 DUPLED — VDDX

14 —

60–63 77–80

PA[7:0]

ADDR[15:8]/

DATA[15:8]

— VDDX PUCR Disabled

PERL/

PPSL

PERL/

PPSL

Disabled

Port L I/O pin; EPHY collision LED

Port L I/O pin; EPHY full duplex LED

Port A I/O pin; multiplexed address/data

69 44 64 VSS2 — — See Table 1-5

70 45 65 VDD2 — — See Table 1-5

Bias control:1.0%

61 46 66 PHY_RBIAS — —

PHY_

VSSA

NA NA

external resistor (see the Electricals Chapter for R

Bias

)

71 47 67 PHY_VSSA — — See Table 1-5

72 48 68 PHY_VDDA — — See Table 1-5

73 49 69 PHY_VDDTX — — See Table 1-5

58 50 70 PHY_TXP — —

PHY_

VDDTX

NA NA Twisted pair output +

Reset

State

Input

Analog

Input

Analog Output

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 71

Chapter 1 Device Overview

Table 1-4. Signal Properties (Sheet 4 of 4)

orig. order

57 51 71 PHY_TXN — —

74 52 72 PHY_VSSTX — — See Table 1-5

60 53 73 PHY_RXP — —

59 54 74 PHY_RXN — —

75 55 75 PHY_VDDRX — — See Table 1-5

76 56 76 PHY_VSSRX — — See Table 1-5

45 57 81 PL2 SPDLED — VDDX

77 58 82

46 59 83 PL1 LNKLED — VDDX

47 60 84 PL0 ACTLED — VDDX

16 61–68 85–92 PAD[7:0] AN[7:0] — VDDA None None

78 69 93 VDDA — — See Table 1-5

79 70 94 VRH — — See Table 1-5

80 71 95 VRL — — See Table 1-5

81 72 96 VSSA — — See Table 1-5

19 —

82 73 101 VSS1 — — See Table 1-5

83 74 102 VDD1 — — See Table 1-5

18 — 105 PK[6]

17 — 106 PK[7]

56 75–78 107–110 PT[7:4]

35 79 111 PJ7 KWJ7 IIC_SCL VDDX

36 80 112 PJ6 KWJ6 IIC_SDA VDDX

80 Pin

No.

112 Pin

No.

97–100

103–104

Name

Function

VDDR/

VREGEN

PK[5:0]

Name

Function

— — See Table 1-5

XADDR

[19:14]

XCS — VDDX PUCR Up

ECS ROMCTL VDDX PUCR Up

TIM_IOC

[7:4]

Name

Function

— VDDX PUCR Up

— VDDX

Power

Domain

PHY_

VDDTX

PHY_

VDDRX

PHY_

VDDRX

Internal Pull

Resistor

CTRL

NA NA Twisted pair output –

NA NA Twisted pair input +

NA NA Twisted pair input –

PERL/

PPSL

PERL/

PPSL

PERL/

PPSL

PERT/

PPST

PERJ/

PPSJ

PERJ/

PPSJ

Reset

State

Disabled

Port L I/O pin; EPHY 100 Mbps LED

Port L I/O pin; EPHY valid link LED

Port L I/O pin; EPHY transmit or receive LED

Port AD input pins; ATD inputs

Port K I/O pins; extended addresses

Port K I/O pin; external chip select

Port K I/O pin; emulation chip select;

Port T I/O pins; timer TIM input cap. output compare

Port J I/O pin; IIC SCL; interrupt

Port J I/O pin; IIC SDA; interrupt

Description

Reset

State

Analog Output

Analog

Input

Analog

Input

MC9S12NE64 Data Sheet, Rev 1.0

72 Freescale Semiconductor

Signal Description

NOTE

Signals shown in bold are not available in the 80-pin package.

NOTE

If the port pins are not bonded out in the chosen package, the user must initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins:

(80-Pin TQFP-EP): Port A[7:0], Port B[7:0], Port E[7,6,5,3,2], Port K[7:0]; Port G[7]; Port L[6:5]

1.2.3 Detailed Signal Descriptions

1.2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the external clock and crystal driver pins. Upon reset, all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.

1.2.3.2 RESET — External Reset Pin

RESET is an active-low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. External circuitry connected to the

RESET pin must not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the processing. The

RESET pin low and a clocked reset sequence controls when the MCU can begin normal

RESET pin includes an internal pull-up device.

1.2.3.3 XFC — PLL Loop Filter Pin

Dedicated pin used to create the PLL ﬁlter. See A.12.3.1, “XFC Component Selection,” and the CRG block description chapter for more detailed information.

1.2.3.4 BKGD / MODC / TAGHI — Background Debug / Tag High / Mode Pin

The BKGD / MODC / TAGHI pin is used as a pseudo-open-drain pin for background debug communication. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of

RESET. In MCU expanded modes of operation, while instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. This pin always has an internal pull-up.

1.2.3.5 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA[7:0] are general-purpose I/O pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:0] pins are not available in the 80-pin package version.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 73

Chapter 1 Device Overview

1.2.3.6 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins

PB[7:0] are general-purpose I/O pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80-pin package version.

1.2.3.7 PE7 / NOACC — Port E I/O Pin 7

PE7 is a general-purpose I/O pin. During MCU expanded modes of operation, the NOACC signal, while enabled, is used to indicate that the current bus cycle is an unused or free cycle. This signal will assert when the CPU is not using the bus.

1.2.3.8 PE6 / IPIPE1/ MODB — Port E I/O Pin 6

PE6 is a general-purpose I/O pin. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of queue tracking signal IPIPE1. PE6 is an input with a pulldown device that is active only while

RESET. This pin is shared with the instruction

RESET is

low. PE6 is not available in the 80-pin package version.

1.2.3.9 PE5 / IPIPE0 / MODA — Port E I/O Pin 5

PE5 is a general-purpose I/O pin. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of queue tracking signal IPIPE0. This pin is an input with a pull-down device that is only active while is low. PE5 is not available in the 80-pin package version.

RESET. This pin is shared with the instruction

RESET

1.2.3.10 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output

PE4 is a general-purpose I/O pin. In normal single chip mode, PE4 is conﬁgured with an active pull-up while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. In all modes except normal single chip mode, the PE4 pin is initially conﬁgured as the output connection for the internal bus clock (ECLK). ECLK is used as a timing reference and to demultiplex the address and data in expanded modes. The ECLK frequency is equal to 1/2 the crystal frequency out of reset. The ECLK output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register, and the ESTR bit in the EBICTL register. All clocks, including the ECLK, are halted while the MCU is in stop mode. It is possible to conﬁgure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. The PE4 pin is initially conﬁgured as ECLK output with stretch in all expanded modes. See the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the ECLK is available for use in external select decode logic or as a constant speed clock for use in the external application system.

MC9S12NE64 Data Sheet, Rev 1.0

74 Freescale Semiconductor

Signal Description

1.2.3.11 PE3 / TAGLO / LSTRB — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB)

PE3 can be used as a general-purpose I/O in all modes and is an input with an active pull-up out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. PE3 can also be conﬁgured as a Low-Byte Strobe ( not be possible until this function is enabled. register. In expanded wide and emulation narrow modes, and while BDM tagging is enabled, the function is multiplexed with the

LSTRB). The LSTRB signal is used in write operations, so external low byte writes will

LSTRB can be enabled by setting the LSTRE bit in the PEAR

LSTRB

TAGLO function. While enabled, a logic zero on the TAGLO pin at the falling edge of ECLK will tag the low byte of an instruction word being read into the instruction queue. PE3 is not available in the 80-pin package version.

1.2.3.12 PE2 / R/W — Port E I/O Pin 2 / Read/Write

PE2 can be used as a general-purpose I/O in all modes and is conﬁgured as an input with an active pull-up out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. If the read/write function is required, it must be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until the read/write function is enabled. The PE2 pin is not available in the 80-pin package version.

1.2.3.13 PE1 / IRQ — Port E Input Pin 1 / Maskable Interrupt Pin

PE1 is always an input and can be read anytime. The PE1 pin is also the IRQ input used for requesting an asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and

IRQ interrupt is masked until the I bit is cleared. The IRQ is software programmable to either

any falling-edge-sensitive triggering or level-sensitive triggering based on the setting of the IRQE bit in the IRQCR register. The

IRQ is always enabled and conﬁgured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.

1.2.3.14 PE0 / XIRQ — Port E input Pin 0 / Non-Maskable Interrupt Pin

PE0 is always an input and can be read anytime. The PE0 pin is also the XIRQ input for requesting a non-maskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register (CCR) is set and any

XIRQ interrupt is masked until the X bit is cleared. Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR network. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.

1.2.3.15 PK7 / ECS / ROMCTL — Port K I/O Pin 7

PK7 is a general-purpose I/O pin. During MCU expanded modes of operation, while the EMK bit in the MODE register is set to 1, this pin is used as the emulation chip select output ( the PK7 pin can be used to determine the reset state of the ROMON bit in the MISC register. At the rising edge of

RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPKE in the PUCR register. PK7 is not available in the 80-pin package version.

ECS). In expanded modes,

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 75

Chapter 1 Device Overview

1.2.3.16 PK6 / XCS — Port K I/O Pin 6

PK6 is a general-purpose I/O pin. During MCU expanded modes of operation, while the EMK bit in the MODE register is set to 1, this pin is used as an external chip select signal for most external accesses that are not selected by ECS. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPKE in the PUCR register. See the multiplexed external bus interface (MEBI) block description chapter for further details. PK6 is not available in the 80-pin package version.

1.2.3.17 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]

PK[5:0] are general-purpose I/O pins. In MCU expanded modes of operation, when the EMK bit in the MODE register is set to 1, PK[5:0] provide the expanded address XADDR[19:14] for the external bus. There are active pull-ups on PK[5:0] pins while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPKE in the PUCR register. See multiplexed external bus interface (MEBI) block description chapter for further details. PK[5:0] are not available in the 80-pin package version.

1.2.3.18 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]

PAD[7:0] are the analog inputs for the analog-to-digital converter (ATD). They can also be conﬁgured as general-purpose digital input. See the port integration module (PIM) PIM_9NE64 block description chapter and the ATD_10B8C block description chapter for information about pin conﬁgurations.

1.2.3.19 PG7 / KWG7 — Port G I/O Pin 7

PG7 is a general-purpose I/O pin. It can be conﬁgured to generate an interrupt (KWG7) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG7 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter for information about pin conﬁgurations.

1.2.3.20 PG6 / KWG6 / MII_RXER — Port G I/O Pin 6

PG6 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive error (MII_RXER) signal. It can be conﬁgured to generate an interrupt (KWG6) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG6 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.21 PG5 / KWG5 / MII_RXDV — Port G I/O Pin 5

PG5 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive data valid (MII_RXDV) signal. It can be conﬁgured to generate an interrupt (KWG5) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG5 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

MC9S12NE64 Data Sheet, Rev 1.0

76 Freescale Semiconductor

Signal Description

1.2.3.22 PG4 / KWG4 / MII_RXCLK — Port G I/O Pin 4

PG4 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive clock (MII_RXCLK) signal. It can be conﬁgured to generate an interrupt (KWG4) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG4 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.23 PG3 / KWG3 / MII_RXD3 — Port G I/O Pin 3

PG3 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive data (MII_RXD3) signal. It can be conﬁgured to generate an interrupt (KWG3) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG3 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.24 PG2 / KWG2 / MII_RXD2 — Port G I/O Pin 2

PG2 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive data (MII_RXD2) signal. It can be conﬁgured to generate an interrupt (KWG2) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG2 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.25 PG1 / KWG1 / MII_RXD1 — Port G I/O Pin 1

PG1 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive data (MII_RXD1) signal. It can be conﬁgured to generate an interrupt (KWG1) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG1 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.26 PG0 / KWG0 / MII_RXD0 — Port G I/O Pin 0

PG0 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the receive data (MII_RXD0) signal. It can be conﬁgured to generate an interrupt (KWG0) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG0 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.27 PH6 / KWH6 / MII_TXER — Port H I/O Pin 6

PH6 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit error (MII_TXER) signal. It can be conﬁgured to generate an interrupt (KWH6) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH6 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 77

Chapter 1 Device Overview

1.2.3.28 PH5 / KWH5 / MII_TXEN — Port H I/O Pin 5

PH5 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit enabled (MII_TXEN) signal. It can be conﬁgured to generate an interrupt (KWH5) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH5 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.29 PH4 / KWH4 / MII_TXCLK — Port H I/O Pin 4

PH4 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit Clock (MII_TXCLK) signal. It can be conﬁgured to generate an interrupt (KWH4) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH4 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.30 PH3 / KWH3 / MII_TXD3 — Port H I/O Pin 3

PH3 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit data (MII_TXD3) signal. It can be conﬁgured to generate an interrupt (KWH3) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH3 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.31 PH2 / KWH2 / MII_TXD2 — Port H I/O Pin 2

PH2 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit data (MII_TXD2) signal. It can be conﬁgured to generate an interrupt (KWH2) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH2 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.32 PH1 / KWH1 / MII_TXD1 — Port H I/O Pin 1

PH1 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit data (MII_TXD1) signal. It can be conﬁgured to generate an interrupt (KWH1) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH1 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.33 PH0 / KWH0 / MII_TXD0 — Port H I/O Pin 0

PH0 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the transmit data (MII_TXD0) signal. It can be conﬁgured to generate an interrupt (KWH0) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH0 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

MC9S12NE64 Data Sheet, Rev 1.0

78 Freescale Semiconductor

Signal Description

1.2.3.34 PJ7 / KWJ7 / IIC_SCL — Port J I/O Pin 7

PJ7 is a general-purpose I/O pin. When the IIC module is enabled, it becomes the serial clock line (IIC_SCL) for the IIC module (IIC). It can be conﬁgured to generate an interrupt (KWJ7) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ7 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the IIC block description chapter for information about pin conﬁgurations.

1.2.3.35 PJ6 / KWJ6 / IIC_SDA — Port J I/O Pin 6

PJ6 is a general-purpose I/O pin. When the IIC module is enabled, it becomes the serial data line (IIC_SDL) for the IIC module (IIC). It can be conﬁgured to generate an interrupt (KWJ6) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ6 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the IIC block description chapter for information about pin conﬁgurations.

1.2.3.36 PJ3 / KWJ3 / MII_COL — Port J I/O Pin 3

PJ3 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the collision (MII_COL) signal. It can be conﬁgured to generate an interrupt (KWJ3) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ3 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.37 PJ2 / KWJ2 / MII_CRS /— Port J I/O Pin 2

PJ2 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the carrier sense (MII_CRS) signal. It can be conﬁgured to generate an interrupt (KWJ2) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ2 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.38 PJ1 / KWJ1 / MII_MDIO — Port J I/O Pin 1

PJ1 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the Management Data I/O (MII_MDIO) signal. It can be conﬁgured to generate an interrupt (KWH1) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ1 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

1.2.3.39 PJ0 / KWJ0 / MII_MDC — Port J I/O Pin 0

PJ0 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the management data clock (MII_MDC) signal. It can be conﬁgured to generate an interrupt (KWJ0) causing the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ0 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin conﬁgurations.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 79

Chapter 1 Device Overview

1.2.3.40 PL6 — Port L I/O Pin 6

PL6 is a general-purpose I/O pin. While in reset and immediately out of reset, the PL6 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter for information about pin conﬁgurations.

1.2.3.41 PL5 — Port L I/O Pin 5

PL5 is a general-purpose I/O pin. While in reset and immediately out of reset, the PL5 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter for information about pin conﬁgurations.

1.2.3.42 PL4 / COLLED — Port L I/O Pin 4

PL4 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with the EPHYCTL0 LEDEN bit set, it becomes the collision status signal (COLLED). While in reset and immediately out of reset the PL4 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for information about pin conﬁgurations.

1.2.3.43 PL3 / DUPLED — Port L I/O Pin 3

PL3 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with the EPHYCTL0 LEDEN bit set, it becomes the duplex status signal (DUPLED). While in reset and immediately out of reset, the PL3 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for information about pin conﬁgurations.

1.2.3.44 PL2 / SPDLED — Port L I/O Pin 2

PL2 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with the EPHYCTL0 LEDEN bit set, it becomes the speed status signal (SPDLED). While in reset and immediately out of reset, the PL2 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for information about pin conﬁgurations.

1.2.3.45 PL1 / LNKLED — Port L I/O Pin 1

PL1 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with the EPHYCTL0 LEDEN bit set, it becomes the link status signal (LNKLED). While in reset and immediately out of reset, the PL1 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for information about pin conﬁgurations.

MC9S12NE64 Data Sheet, Rev 1.0

80 Freescale Semiconductor

Signal Description

1.2.3.46 PL0 / ACTLED — Port L I/O Pin 0

PL0 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with the EPHYCTL0 LEDEN bit set, it becomes the active status signal (ACTLED). While in reset and immediately out of reset, the PL0 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for information about pin conﬁgurations.

1.2.3.47 PS7 / SPI_SS — Port S I/O Pin 7

PS7 is a general-purpose I/O. When the serial peripheral interface (SPI) is enabled, PS7 becomes the slave select pin

SS. While in reset and immediately out of reset, the PS7 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about pin conﬁgurations.

1.2.3.48 PS6 / SPI_SCK — Port S I/O Pin 6

PS6 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS6 becomes the serial clock pin, SCK. While in reset and immediately out of reset, the PS6 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about pin conﬁgurations.

1.2.3.49 PS5 / SPI_MOSI — Port S I/O Pin 5

PS5 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS5 becomes the master output (during master mode) or slave input (during slave mode) pin. While in reset and immediately out of reset, the PS5 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about pin conﬁgurations.

1.2.3.50 PS4 / SPI_MISO — Port S I/O Pin 4

PS4 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS4 becomes the master input (during master mode) or slave output (during slave mode) pin. While in reset and immediately out of reset, the PS4 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about pin conﬁgurations.

1.2.3.51 PS3 / SCI1_TXD — Port S I/O Pin 3

PS3 is a general-purpose I/O. When the serial communications interface 1 (SCI1) transmitter is enabled, PS3 becomes the transmit pin, TXD, of SCI1. While in reset and immediately out of reset, the PS3 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SCI block description chapter for information about pin conﬁgurations.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 81

Chapter 1 Device Overview

1.2.3.52 PS2 / SCI1_RXD — Port S I/O Pin 2

PS2 is a general-purpose I/O. When the serial communications interface 1 (SCI1) receiver is enabled, PS2 becomes the receive pin RXD of SCI1. While in reset and immediately out of reset, the PS2 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SCI block description chapter for information about pin conﬁgurations.

1.2.3.53 PS1 / SCI0_TXD — Port S I/O Pin 1

PS1 is a general-purpose I/O. When the serial communications interface 0 (SCI0) transmitter is enabled, PS1 becomes the transmit pin, TXD, of SCI0. While in reset and immediately out of reset, the PS1 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SCI block description chapter for information about pin conﬁgurations.

1.2.3.54 PS0 / SCI0_RXD — Port S I/O Pin 0

PS0 is a general-purpose I/O. When the serial communications interface 0 (SCI0) receiver is enabled, PS0 becomes the receive pin RXD0 of SCI0. While in reset and immediately out of reset, the PS0 pin is conﬁgured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SCI block description chapter for information about pin conﬁgurations.

1.2.3.55 PT[7:4] / IOC1[7:4] — Port T I/O Pins [7:4]

PT[7:4] are general-purpose I/O pins. While the timer system 1 (TIM1) is enabled, these pins can also be conﬁgured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and immediately out of reset, the PT[7:4] pins are conﬁgured as a high-impedance input pins. See the port integration module (PIM) PIM_9NE64 block description chapter and the TIM_16B4C block description chapter for information about pin conﬁgurations.

1.2.3.56 PHY_TXP — EPHY Twisted Pair Output +

Ethernet twisted pair output pin. This pin is hi-z out of reset.

1.2.3.57 PHY_TXN — EPHY Twisted Pair Output –

Ethernet twisted pair output pin. This pin is hi-z out of reset.

1.2.3.58 PHY_RXP — EPHY Twisted Pair Input +

Ethernet twisted pair input pin. This pin is hi-z out of reset.

1.2.3.59 PHY_RXN — EPHY Twisted Pair Input –

Ethernet twisted pair input pin. This pin is hi-z out of reset.

MC9S12NE64 Data Sheet, Rev 1.0

82 Freescale Semiconductor

Signal Description

1.2.3.60 PHY_RBIAS — EPHY Bias Control Resistor

Connect a 1.0% external resistor, RBIAS, between PHY_RBIAS pin and PHY_VSSA. This resistor must be placed as near as possible to the chip pin. Stray capacitance must be kept to less than 10 pF (> 50 pF may cause instability). No high-speed signals are allowed in the region of RBIAS.

1.2.4 Power Supply Pins

1.2.4.1 V

DDX1

, V

DDX2

, V

SSX1

, V

— Power & Ground Pins for I/O & Internal

SSX2

Voltage Regulator

External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded.

1.2.4.2 V

DDR/VREGEN

— Power Pin for Internal Voltage Regulator

External power for internal voltage regulator.

1.2.4.3 V

DD1

, V

DD2

, V

SS1

, V

— Core Power Pins

SS2

Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off, if VDDR/VREGEN is tied to ground.

1.2.4.4 V

DDA

, V

— Power Supply Pins for ATD and VREG_PHY

SSA

VDDA and VSSA are the power supply and ground input pins for the voltage regulator and the analog-to-digital converter.

1.2.4.5 PHY_VDDA, PHY_VSSA — Power Supply Pins for EPHY Analog

Power is supplied to the Ethernet physical transceiver (EPHY) PLLs through PHY_VDDA and PHY_VSSA. This 2.5V supply is derived from the internal voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off, if VDDR/VREGEN is tied to ground.

1.2.4.6 PHY_VDDRX, PHY_VSSRX — Power Supply Pins for EPHY Receiver

Power is supplied to the Ethernet physical transceiver (EPHY) receiver through PHY_VDDRX and PHY_VSSRX. This 2.5V supply is derived from the internal voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off, if VDDR/VREGEN is tied to ground.

1.2.4.7 PHY_VDDTX, PHY_VSSTX — Power Supply Pins for EPHY Transmitter

External power is supplied to the Ethernet physical transceiver (EPHY) transmitter through PHY_VDDTX and PHY_VSSTX. This 2.5 V supply is derived from the internal voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off, if V

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 83

DDR/VREGEN

is tied to ground.

Chapter 1 Device Overview

1.2.4.8 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog-to-digital converter.

1.2.4.9 V

DDPLL

, V

SSPLL

— Power Supply Pins for PLL

Provides operating voltage and ground for the oscillator and the phase-locked loop. This allows the supply voltage to the oscillator and PLL to be bypassed independently. This 2.5 V voltage is generated by the internal voltage regulator. The internal voltage regulator is turned off, if V

Table 1-5. MC9S12NE64 Power and Ground Connection Summary

Mnemonic

DDR/VREGEN

DDX1

DDX2

SSX1

SSX2

DDA

SSA

PHY_VDDTX

PHY_VDDRX

PHY_VDDA

PHY_VSSTX PHY_VSSRX

PHY_VSSA

DD1

DD2

SS1

SS2

DDPLL

SSPLL

Nominal

Voltage

3.3 V

0 V

3.3 V Operating voltage and ground for the analog-to-digital converter, the

0 V

3.3 V Reference voltage high for the analog-to-digital converter.

0 V Reference voltage low for the analog-to-digital converter.

2.5 V

0 V

2.5 V Provide operating voltage and ground for the phase-locked loop. This

0 V

External power and ground, supply to internal voltage regulator. To disable voltage regulator attach V

External power and ground, supply to pin drivers.

reference for the internal voltage regulator and the digital-to-analog converters, allows the supply voltage to the A/D to be bypassed independently.

Internal power and ground generated by internal regulator for internal Ethernet Physical Transceiver (EPHY). These also allow an external source to supply the EPHY voltages and bypass the internal voltage regulator.

Internal power and ground generated by internal regulator. These also allow an external source to supply the core V

bypass the internal voltage regulator.

allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.

Description

REGEN

DDR/VREGEN

to V

SSX

DD/VSS

voltages and

is tied to ground.

NOTE

All V

pins must be connected together in the application. Because fast

signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as near to the MCU as possible. Bypass requirements depend on MCU pin load.

MC9S12NE64 Data Sheet, Rev 1.0

84 Freescale Semiconductor

System Clock Description

1.3 System Clock Description

The clock and reset generator provides the internal clock signals for the core and all peripheral modules.

Figure 1-5 shows the clock connections from the CRG to all modules. See the CRG block description

chapter for details on clock generation.

EXTAL

XTAL

CRG

bus clock

oscillator clock

core clock

S12_CORE

FLASH

RAM

TIM

ATD

PIM

SCI

SPI

IIC

EMAC

EPHY

VREG_PHY

Figure 1-5. Clock Connections

1.4 Modes of Operation

There are eight possible modes of operation available on the MC9S12NE64. Each mode has an associated default memory map and external bus conﬁguration.

1.4.1 Chip Conﬁguration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the the ROMON bit in the MISC register thus controlling whether the internal FLASH is visible in the memory map. ROMON = 1 means the FLASH is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 85

RESET signal. The ROMCTL signal allows the setting of

RESET signal.

Chapter 1 Device Overview

Table 1-6. Mode Selection

BKGD =

MODC

000X1

001

0 1 0 X 0 Special Test (Expanded Wide), BDM allowed.

011

1 0 0 X 1 Normal Single Chip, BDM allowed.

101

110X1

111

PE6 =

MODB

PE5 =

MODA

PP6 =

ROMCTL

ROMON

Bit

Mode Description

Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active.

Emulation Expanded Narrow, BDM allowed.

Emulation Expanded Wide, BDM allowed.

Normal Expanded Narrow, BDM allowed.

Peripheral; BDM allowed but bus operations would cause bus conﬂicts (must not be used).

Normal Expanded Wide, BDM allowed.

For further explanation on the modes, see the MEBI block description chapter.

1.4.2 Security

The MC9S12NE64 provides a security feature that prevents the unauthorized read and write of the memory contents

. This feature allows:

• Protection of the contents of FLASH

• Operation in single-chip mode

• Operation from external memory with internal FLASH disabled

On-chip security can be compromised by user code. An extreme example would be user code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user program. An example of this would be the user downloading a key through the SCI, which would allow access to a programming routine that could update parameters.

1.4.2.1 Securing the Microcontroller

After the user has programmed the FLASH, the MCU can be secured by programming the security bits located in the FLASH module. These nonvolatile bits will keep the MCU secured through resetting the MCU and through powering down the MCU.

The security byte resides in a portion of the FLASH array.

See the FLASH block description chapter for more details on the security conﬁguration.

1.No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

MC9S12NE64 Data Sheet, Rev 1.0

86 Freescale Semiconductor

Low-Power Modes

1.4.2.2 Operation of the Secured Microcontroller

1.4.2.2.1 Normal Single Chip Mode

This will be the most common usage of the secured MCU. Everything will appear the same as if the MCU were not secured, with the exception of BDM operation. The BDM operation will be blocked.

1.4.2.2.2 Executing from External Memory

The user may wish to execute from external memory with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be blocked.

1.4.2.3 Unsecuring the Microcontroller

In order to unsecure the microcontroller, the internal FLASH must be erased. This can be performed through an external program in expanded mode.

After the user has erased the FLASH, the MCU can be reset into special single chip mode. This invokes a program that veriﬁes the erasure of the internal FLASH. After this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally performed through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the MCU goes through a reset before the security bits are reprogrammed to the unsecure state, the MCU will be secured again.

1.5 Low-Power Modes

The microcontroller features three main low-power modes. See the respective block description chapter for information on the module behavior in stop, pseudo stop, and wait mode. An important source of information about the clock system is the clock and reset generator (CRG) block description chapter.

1.5.1 Stop

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wakeup from this mode can be performed via reset or external interrupts.

1.5.2 Pseudo Stop

This mode is entered by executing the CPU STOP instruction. In this mode, the oscillator stays running and the real-time interrupt (RTI) or watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full stop mode, but the wakeup time from this mode is signiﬁcantly shorter.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 87

Chapter 1 Device Overview

1.5.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode, the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption, the peripherals can individually turn off their local clocks.

1.5.4 Run

Although this is not a low-power mode, unused peripheral modules must not be enabled in order to save power.

1.6 Resets and Interrupts

See the exception processing section of the CPU12 reference manual for information on resets and interrupts. System resets can be generated through external control of the and reset generator module (CRG), or through the low-voltage reset (LVR) generator of the voltage regulator module. See the CRG and VREG_PHY block description sections for detailed information on reset generation.

1.6.1 Vectors

RESET pin, through the clock

Table 1-7 lists interrupt sources and vectors in default order of priority.

Table 1-7. Interrupt Vector Locations

Vector

No.

0 $FFFE, $FFFF Vreset

1 $FFFC, $FFFD Vclkmon Clock monitor fail reset None

2 $FFFA, $FFFB Vcop COP failure reset None COP rate select —

3 $FFF8, $FFF9 Vtrap Unimplemented instruction trap None None —

4 $FFF6, $FFF7 Vswi SWI None None —

5 $FFF4, $FFF5 Vxirq

6 $FFF2, $FFF3 Virq

7 $FFF0, $FFF1 Vrti Real-time interrupt I-Bit CRGINT (RTIE) $F0

through11$FFE8 to $FFEF

12 $FFE6, $FFE7 Vtimch4 Standard timer channel 4 I-Bit T0IE (T0C4I) $E6

13 $FFE4, $FFE5 Vtimch5 Standard timer channel 5 I-Bit T0IE (T0C5I) $E4

14 $FFE2, $FFE3 Vtimch6 Standard timer channel 6 I-Bit T0IE (T0C6I) $E2

15 $FFE0, $FFE1 Vtimch7 Standard timer channel 7 I-Bit T0IE (T0C7I) $E0

Vector

Address

Vector

Name

Interrupt Source

External reset, power on reset or

low voltage reset (see CRG ﬂags

source)

XIRQ X-Bit None —

IRQ I-Bit INTCR (IRQEN) $F2

Reserved

CCR

Mask

None None —

Local Enable

COPCTL (CME,

FCME)

HPRIO Value

to Elevate

—

MC9S12NE64 Data Sheet, Rev 1.0

88 Freescale Semiconductor

Table 1-7. Interrupt Vector Locations (Continued)

Resets and Interrupts

Vector

No.

16 $FFDE, $FFDF Vtimovf Standard timer overﬂow I-Bit T0MSK2 (T0OI) $DE

17 $FFDC, $FFDD Vtimpaovf Pulse accumulator overﬂow I-Bit PACTL0 (PAOVI0) $DC

18 $FFDA, $FFDB Vtimpaie Pulse accumulator input edge I-Bit PACTL0 (PAI0) $DA

19 $FFD8, $FFD9 Vspi SPI I-Bit SPCR1 (SPIE, SPTIE) $D8

20 $FFD6, $FFD7 Vsci0 SCI0 I-Bit

21 $FFD4, $FFD5 Vsci1 SCI1 I-Bit

22 $FFD2, $FFD3 Vatd ATD I-Bit ATDCTL2 (ASCIE) $D2

23 $FFD0, $FFD1

24 $FFCE, $FFCF Vportj Port J I-Bit PTJIF (PTJIE) $CE

25 $FFCC, $FFCD Vporth Port H I-Bit PTHIF (PTHIE) $CC

26 $FFCA, $FFCB Vportg Port G I-Bit PTGIF (PTGIE) $CA

27 $FFC8, $FFC9

28 $FFC6, $FFC7 Vcrgplllck CRG PLL lock I-Bit PLLCR (LOCKIE) $C6

29 $FFC4, $FFC5 Vcrgscm CRG self clock mode I-Bit PLLCR (SCMIE) $C4

30 $FFC2, $FFC3

31 $FFC0, $FFC1 Viic IIC bus I-Bit IBCR (IBIE) $C0

through34$FFBA to $FFBF

Vector

Address

Vector

Name

Interrupt Source

CCR

Mask

Reserved

Local Enable

SC0CR2

(TIE, TCIE, RIE, ILIE)

SC1CR2

(TIE, TCIE, RIE, ILIE)

HPRIO Value

to Elevate

$D6

$D4

35 $FFB8, $FFB9 Vﬂash FLASH I-Bit FCNFG (CCIE, CBEIE) $B8

36 $FFB6, $FFB7 Vephy EPHY interrupt I-Bit EPHYCTL0 (EPHYIE) $B6

37 $FFB4, $FFB5 Vemacrxbac EMAC receive buffer A complete I-Bit IMASK (RXACIE) $B4

38 $FFB2, $FFB3 Vemacrxbbc EMAC receive buffer B complete I-Bit IMASK (RXBCIE) $B2

39 $FFB0, $FFB1 Vemactxc

40 $FFAE, $FFAF Vemacrxfc EMAC receive ﬂow control I-Bit IMASK (RFCIE) $AE

41 $FFAC, $FFAD Vemacmii

42 $FFAA, $FFAB Vemacrxerr EMAC receive error I-Bit IMASK (RXAIE) $AA

43 $FFA8, $FFA9 Vemacrxbao EMAC receive buffer A overrun I-Bit IMASK (RXAOIE) $A8

44 $FFA6, $FFA7 Vemacrxbbo EMAC receive buffer B overrun I-Bit IMASK (RXBOIE) $A6

45 $FFA4, $FFA5 Vemacbrxerr EMAC babbling receive error I-Bit IMASK (BREIE) $A4

46 $FFA2, $FFA3 Vemaclc EMAC late collision I-Bit IMASK (LCIE) $A2

47 $FFA0, $FFA1 Vemacec EMAC excessive collision I-Bit IMASK (ECIE) $A0

through63$FF80 to $FF9F

EMAC frame transmission

complete

EMAC MII management transfer

complete

Reserved

MC9S12NE64 Data Sheet, Rev 1.0

I-Bit IMASK (TXCIE) $B0

I-Bit IMASK (MMCIE) $AC

Freescale Semiconductor 89

Chapter 1 Device Overview

1.6.2 Resets

Resets are a subset of the interrupts featured inTable 1-7. The different sources capable of generating a system reset are summarized in Table 1-8.

1.6.2.1 Reset Summary Table

Table 1-8. Reset Summary

Reset Priority Source Vector

Power-on reset 1 CRG module $FFFE, $FFFF

External reset 1

Low-voltage reset 1 VREG_PHY module $FFFE, $FFFF

Clock monitor reset 2 CRG module $FFFC, $FFFD

COP watchdog reset 3 CRG module $FFFA, $FFFB

1.6.2.2 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. See the respective module block description chapter for register reset states. See the MEBI block description chapter for mode-dependent pin conﬁguration of port A, B, E, and K out of reset.

RESET pin $FFFE, $FFFF

See the PIM block description chapter for reset conﬁgurations of all peripheral module ports.

See Table 1-1 for locations of the memories depending on the operating mode after reset.

The RAM array is not automatically initialized out of reset.

1.7 Block Conﬁguration for MC9S12NE64

This section contains information regarding how the modules are implemented on the MC9S12NE64 device.

1.7.1 V

On the MC9S12NE64, the V regulator. If this pin is tied low, then V PHY_VDDA must be supplied externally.

1.7.2 V

In both the 112-pin LQFP and the 80-pin TQFP-EP package versions, both internal VDD and VSS of the

2.5 V domain are bonded out on two sides of the device as two pin pairs (V and V

DD1

allows systems to employ better supply routing and further decoupling.

DDR/VREGEN

DD1

, V

DD1

are connected together internally. V

DD2

, V

SS1

, V

SS2

pin is used to enable or disable the internal voltage 3.3V to 2.5V

, V

DD2

, V

DDPLL

and V

SS1

, PHY_VDDRX, PHY_VDDTX, and

DD1/VSS1

are connected together internally. This

SS2

and V

DD2/VSS2

MC9S12NE64 Data Sheet, Rev 1.0

90 Freescale Semiconductor

Block Conﬁguration for MC9S12NE64

1.7.3 Clock Reset Generator (CRG) Block Description

See the CRG block description chapter for information about the clock and reset generator module. The CRG is part of the IPBus domain. For the MC9S12NE64, only the Pierce circuitry is available for the oscillator.

The low-voltage reset feature uses the low-voltage reset signal from the VREG_PHY module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a speciﬁed threshold, the LVR signal from the VREG_PHY module causes the CRG module to generate a reset. See the VREG_PHY block description chapter for voltage level speciﬁcations.

1.7.3.1 XCLKS

The XCLKS input signal is not available on the MC9S12NE64. The signal is internally tied low to select the Pierce oscillator or external clock conﬁguration.

1.7.4 Ethernet Media Access Controller (EMAC)

See the EMAC block description chapter for information about the Ethernet media access controller module. The EMAC is part of the IPBus domain.

1.7.4.1 EMAC MII External Pin Conﬁguration

When the EMAC is conﬁgured for and external Ethernet physical transceiver internal pull-ups and pull-downs are not automatically conﬁgured on the MII inputs. Any internal pull-up or pull-down resistors, which may be required, must be conﬁgured by setting the appropriate pull control registers in the port integration module (PIM). This implementation allows the use of external pull-up and pull-down resistors.

1.7.4.2 EMAC Internal PHY Conﬁguration

When the EXTPHY bit (in the EMAC NETCTL register) is set to 1, the EMAC is conﬁgured to work with the internal EPHY block. Please see 1.7.5, “Ethernet Physical Transceiver (EPHY),” for more information regarding the EPHY block.

1.7.4.3 Low-Power Operation

Special care must be taken when executing STOP and WAIT instructions while using the EMAC, or undesired operation may result.

1.7.4.3.1 Wait

Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL register because the clocks to the transmit and receive buffers are stopped. It is recommended that the EMAC ESWAI bit be set if wait mode is entered with the CWAI set.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 91

Chapter 1 Device Overview

1.7.4.3.2 Stop

During system low-power stop mode, the EMAC is immediately disabled. Any receive in progress is dropped and any PAUSE time-out is cleared. The user must not to enter low-power stop mode when TXACT or BUSY are set.

1.7.5 Ethernet Physical Transceiver (EPHY)

See the EPHY block description chapter for information about the Ethernet physical transceiver module. The EPHY is part of the IPBus domain. The EPHY also has MII register space which is not part of the MCU address space and not accessible via the IP bus. The MII registers can be accessed using the MDIO functions of the EMAC when the EMAC is conﬁgured for internal PHY operation.

The MII pins of the EPHY are not externally accessible. All communication and management of the EPHY must be performed using the EMAC.

The organization unique identiﬁer (OUI) for the MC9S12NE64 is 00-60-11 (hex).

1.7.5.1 Low-Power Operation

Special care must be taken when executing STOP and WAIT instructions while using the EPHY or undesired operation may result.

1.7.5.1.1 Wait

Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL register because the clocks to the internal MII interface are stopped.

1.7.5.1.2 Stop

During system low-power stop mode, the EPHY is immediately reset and powered down. Upon exiting stop mode, the a start-up delay is required prior to initiating MDIO communications with the EPHY. See

A.14, “EPHY Electrical Characteristics” for details.

It is not possible to use an EPHY interrupt to wake the system from stop mode.

1.7.6 RAM 8K Block Description

This module supports single-cycle misaligned word accesses without wait states. The RAM is part of the HCS12 Bus domain.

In addition to operating as the CPU storage, the 8K system RAM also functions as the Ethernet buffer while the EMAC module is enabled. While the EMAC is enabled, the Ethernet buffer will occupy 0.375K to 4.5K of RAM with physical addresses starting at $0000 and ending at $017F up to $11FF, depending on the setting of the BUFMAP bits in the EMAC Ethernet buffer conﬁguration register (BUFCFG). The relative RAM address, which are controlled by settings in the internal RAM position register (INTRM), must be tracked in software.

MC9S12NE64 Data Sheet, Rev 1.0

92 Freescale Semiconductor

Block Conﬁguration for MC9S12NE64

The Ethernet buffer operation of the RAM is independent of the CPU and allows same cycle read/write access from the CPU and the EMAC. No hardware blocking mechanism is implemented to prevent the CPU from accessing the Ethernet RAM space, so care must be taken to ensure that the CPU does not corrupt the RAM Ethernet contents.

MC9S12NE64 Data Sheet, Rev 1.0

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Chapter 1 Device Overview

MC9S12NE64 Data Sheet, Rev 1.0

94 Freescale Semiconductor

Chapter 2 64K Byte Flash (FTS64K) Block Description

2.1 Introduction

This document describes the FTS64K module which is a 64K byte Flash (nonvolatile) memory. The Flash array is organized as 1 block of 64K bytes organized as 1024 rows of 64 bytes. The Flash block’s erase sector size is 8 rows (512 bytes).

The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.

Program and erase functions are controlled by a command driven interface. Both sector erase and mass erase of the entire 64K byte Flash block are supported. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase is generated internally by on-chip charge pumps.

It is not possible to read from the Flash block while it is being erased or programmed.

The Flash block is ideal for program and data storage for single-supply applications allowing for ﬁeld reprogramming without requiring external programming voltage sources.

NOTE

A word must be erased before being programmed. Cumulative programming of bits within a word is not allowed.

2.1.1 Glossary

Command Sequence — A three-step MCU instruction sequence to program, erase, or erase verify a Flash block.

2.1.2 Features

• 64K bytes of Flash memory

• Automated program and erase algorithm

• Interrupts on Flash command completion and command buffer empty

• Fast sector erase and word program operation

• 2-stage command pipeline

• Flexible protection scheme for protection against accidental program or erase

• Single power supply program and erase

• Security feature

2.1.3 Modes of Operation

• Program and erase operation (please refer to Section 2.4.1, “Program and Erase Operation,” for details).

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 95

Chapter 2 64K Byte Flash (FTS64K) Block Description

2.1.4 Block Diagram

Figure 2-1 shows a block diagram of the FTS64K module.

FTS64K

Command

Interface

Command Complete Interrupt

Registers

Command Pipeline

Flash Array

32K * 16 Bits

row0 row1

Command Buffer Empty

Interrupt

Oscillator Clock

comm2 addr2 data2

Protection

Security

comm1 addr1 data1

Clock Divider

Figure 2-1. Module Block Diagram

FCLK

row1023

2.2 External Signal Description

The FTS64K module contains no signals that connect off-chip.

2.3 Memory Map and Register Descriptions

This section describes the FTS64K memory maps and registers.

MC9S12NE64 Data Sheet, Rev 1.0

96 Freescale Semiconductor

Memory Map and Register Descriptions

2.3.1 Module Memory Map

Figure 2-2 shows the FTS64K memory map. The HCS12 architecture places the Flash memory address

between $4000 and $FFFF, which corresponds to three 16-Kbyte pages. The content of the HCS12 core PPAGE register is used to map the logical middle page ranging from address $8000 to $BFFF to any physical 16K byte page in the physical memory ﬁeld, described in Table 2-1, and user deﬁned Flash protected sectors, described in Table 2-2.

The FPOPEN bit in the FPROT register (see Section 2.3.2.5, “Flash Protection Register (FPROT)”) can globally protect the entire Flash array. However, two protected areas, one starting from the Flash page $3E starting address (called lower) towards higher addresses and the other one growing downward from the Flash page $3F end address (called higher) can be activated. The latter is mainly targeted to hold the boot loader code because it covers the vector space. All the other areas may be used to keep critical parameters.

Security information that allows the MCU to prevent intrusive access to the Flash module is stored in the Flash protection/options ﬁeld described in Table 2-1.

Table 2-1. Flash Protection/Options Field

. Shown within the pages are the Flash protection/options

Array Address

$FF00 - $FF07 8 Backdoor comparison keys

$FF08 - $FF0C 5 Reserved

$FF0D 1 Flash protection byte

$FF0E 1 Reserved

$FF0F 1 Flash Options/Security byte

Size

(bytes)

Description

Refer to Section 2.3.2.5, “Flash

Protection Register (FPROT)”

Refer to Section 2.3.2.2, “Flash

Security Register (FSEC)”

1.By placing $3F/$3E in the HCS12 Core PPAGE register, the bottom /top “fixed” 16-Kbyte pages can be seen twice

in the MCU memory map.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 97

Chapter 2 64K Byte Flash (FTS64K) Block Description

(16 bytes)

Flash Registers

FLASHSTART = $4000

$4200 $4400

$4800

$5000

12K

$8000

$C000

Flash Protected Low Sectors

0.5K, 1K, 2K, 4K bytes

$3E

16K PAGED

MEMORY

$3C $3C $3E $3F

$E000

$F000

$F800

FLASH END = $FFFF

$3F

Flash Protected High Sectors 2K, 4K, 8K, 16K bytes

$FF00 - $FF0F, Flash Protection/Security Field

Note: $3C-$3F correspond to the PPAGE register content

Figure 2-2. Flash Memory Map

MC9S12NE64 Data Sheet, Rev 1.0

98 Freescale Semiconductor

Memory Map and Register Descriptions

Table 2-2. Flash Module Memory Map Summary

MCU Address

Range

PPAGE

$4000-$7FFF Unpaged

($3E)

ProtectableLow

Range

ProtectableHigh

Range

Block Relative

Address

$4000-$41FF N.A. $8000-$BFFF

$4000-$43FF

$4000-$47FF

$4000-$4FFF

$8000-$BFFF $3C N.A. N.A. $0000-$3FFF

$3D N.A. N.A. $4000-$7FFF

$3E $8000-$81FF N.A. $8000-$BFFF

$8000-$83FF

$8000-$87FF

$8000-$8FFF

$3F N.A. $B800-$BFFF $C000-$FFFF

$B000-$BFFF

$A000-$BFFF

$8000-$BFFF

$C000-$FFFF Unpaged

($3F)

N.A. $F800-$FFFF $C000-$FFFF

$F000-$FFFF

$E000-$FFFF

$C000-$FFFF

Inside Flash block.

The Flash module also contains a set of 16 control and status registers located in address space register base + $100 to register base + $10F. A summary of these registers is given in Table 2-3.

Table 2-3. Flash Module Memory Map

Address

Offset

$_00 Flash Clock Divider Register (FCLKDIV) R/W $_03 Flash Security Register (FSEC) R $_02 Reserved1 $_03 Flash Conﬁguration Register (FCNFG) R/W $_04 Flash Protection Register (FPROT) R/W $_05 Flash Status Register (FSTAT) R/W $_06 Flash Command Register (FCMD) R/W $_07 Reserved2 $_08 Flash High Address Register (FADDRHI) R/W

$_09 Flash Low Address Register (FADDRLO) R/W $_0A Flash High Data Register (FDATAHI) R/W $_0B Flash Low Data Register (FDATALO) R/W $_0C Reserved3 $_0D Reserved4 $_0E Reserved5 $_0F Reserved6

Intended for factory test purposes only.

Use Access

R R R R

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor 99

Chapter 2 64K Byte Flash (FTS64K) Block Description

NOTE

Register address = register base address +$100 + address offset, where the register base address is deﬁned by the HCS12 core INITRG register and the address offset is deﬁned by the Flash module.

2.3.2 Register Descriptions

2.3.2.1 Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms.

Module Base + $0

76543210

R FDIVLD

RESET: 00000000

PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0

= Unimplemented or Reserved

Figure 2-3. Flash Clock Divider Register (FCLKDIV)

All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.

FDIVLD — Clock Divider Loaded.

1 = Register has been written to since the last reset. 0 = Register has not been written.

PRDIV8 — Enable Prescaler by 8.

1 = Enables a prescaler by 8, to divide the Flash module input oscillator clock before feeding into

the CLKDIV divider.

0 = The input oscillator clock is directly fed into the FCLKDIV divider.

FDIV[5:0] — Clock Divider Bits.

The combination of PRDIV8 and FDIV[5:0] effectively divides the Flash module input oscillator clock down to a frequency of 150 kHz - 200 kHz. The maximum divide ratio is 512. Please refer to

Section 2.4.1.1, “Writing the FCLKDIV Register,” for more information.

2.3.2.2 Flash Security Register (FSEC)

This FSEC register holds all bits associated with the security of the MCU.

MC9S12NE64 Data Sheet, Rev 1.0

100 Freescale Semiconductor

Freescale MC9S12NE64 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

List of Figures

List of Tables

1.1 Introduction

1.1.1 Features

1.1.2 Modes of Operation

1.1.3 Block Diagram

1.1.4 Device Memory Map

1.1.5 Detailed Register Map

1.1.6 Part ID Assignments

1.2 Signal Description

1.2.1 Device Pinout

1.2.1.1 112-Pin LQFP

1.2.1.2 80-Pin TQFP-EP

1.2.2 Signal Properties Summary

1.2.3 Detailed Signal Descriptions

1.2.3.1 EXTAL, XTAL — Oscillator Pins

1.2.3.2 RESET — External Reset Pin

1.2.3.3 XFC — PLL Loop Filter Pin

1.2.3.4 BKGD / MODC / TAGHI — Background Debug / Tag High / Mode Pin

1.2.3.5 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

1.2.3.6 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins

1.2.3.7 PE7 / NOACC — Port E I/O Pin 7

1.2.3.8 PE6 / IPIPE1/ MODB — Port E I/O Pin 6

1.2.3.9 PE5 / IPIPE0 / MODA — Port E I/O Pin 5

1.2.3.10 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output

1.2.3.11 PE3 / TAGLO / LSTRB — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB)

1.2.3.12 PE2 / R/W — Port E I/O Pin 2 / Read/Write

1.2.3.13 PE1 / IRQ — Port E Input Pin 1 / Maskable Interrupt Pin

1.2.3.14 PE0 / XIRQ — Port E input Pin 0 / Non-Maskable Interrupt Pin

1.2.3.15 PK7 / ECS / ROMCTL — Port K I/O Pin 7

1.2.3.16 PK6 / XCS — Port K I/O Pin 6

1.2.3.17 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]

1.2.3.18 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]

1.2.3.19 PG7 / KWG7 — Port G I/O Pin 7

1.2.3.20 PG6 / KWG6 / MII_RXER — Port G I/O Pin 6

1.2.3.21 PG5 / KWG5 / MII_RXDV — Port G I/O Pin 5

1.2.3.22 PG4 / KWG4 / MII_RXCLK — Port G I/O Pin 4

1.2.3.23 PG3 / KWG3 / MII_RXD3 — Port G I/O Pin 3

1.2.3.24 PG2 / KWG2 / MII_RXD2 — Port G I/O Pin 2

1.2.3.25 PG1 / KWG1 / MII_RXD1 — Port G I/O Pin 1

1.2.3.26 PG0 / KWG0 / MII_RXD0 — Port G I/O Pin 0

1.2.3.27 PH6 / KWH6 / MII_TXER — Port H I/O Pin 6

1.2.3.28 PH5 / KWH5 / MII_TXEN — Port H I/O Pin 5

1.2.3.29 PH4 / KWH4 / MII_TXCLK — Port H I/O Pin 4

1.2.3.30 PH3 / KWH3 / MII_TXD3 — Port H I/O Pin 3

1.2.3.31 PH2 / KWH2 / MII_TXD2 — Port H I/O Pin 2

1.2.3.32 PH1 / KWH1 / MII_TXD1 — Port H I/O Pin 1

1.2.3.33 PH0 / KWH0 / MII_TXD0 — Port H I/O Pin 0

1.2.3.34 PJ7 / KWJ7 / IIC_SCL — Port J I/O Pin 7

1.2.3.35 PJ6 / KWJ6 / IIC_SDA — Port J I/O Pin 6

1.2.3.36 PJ3 / KWJ3 / MII_COL — Port J I/O Pin 3

1.2.3.37 PJ2 / KWJ2 / MII_CRS /— Port J I/O Pin 2

1.2.3.38 PJ1 / KWJ1 / MII_MDIO — Port J I/O Pin 1

1.2.3.39 PJ0 / KWJ0 / MII_MDC — Port J I/O Pin 0

1.2.3.40 PL6 — Port L I/O Pin 6

1.2.3.41 PL5 — Port L I/O Pin 5

1.2.3.42 PL4 / COLLED — Port L I/O Pin 4

1.2.3.43 PL3 / DUPLED — Port L I/O Pin 3

1.2.3.44 PL2 / SPDLED — Port L I/O Pin 2

1.2.3.45 PL1 / LNKLED — Port L I/O Pin 1

1.2.3.46 PL0 / ACTLED — Port L I/O Pin 0

1.2.3.47 PS7 / SPI_SS — Port S I/O Pin 7

1.2.3.48 PS6 / SPI_SCK — Port S I/O Pin 6

1.2.3.49 PS5 / SPI_MOSI — Port S I/O Pin 5

1.2.3.50 PS4 / SPI_MISO — Port S I/O Pin 4

1.2.3.51 PS3 / SCI1_TXD — Port S I/O Pin 3

1.2.3.52 PS2 / SCI1_RXD — Port S I/O Pin 2

1.2.3.53 PS1 / SCI0_TXD — Port S I/O Pin 1

1.2.3.54 PS0 / SCI0_RXD — Port S I/O Pin 0

1.2.3.55 PT[7:4] / IOC1[7:4] — Port T I/O Pins [7:4]

1.2.3.56 PHY_TXP — EPHY Twisted Pair Output +

1.2.3.57 PHY_TXN — EPHY Twisted Pair Output –

1.2.3.58 PHY_RXP — EPHY Twisted Pair Input +

1.2.3.59 PHY_RXN — EPHY Twisted Pair Input –

1.2.3.60 PHY_RBIAS — EPHY Bias Control Resistor

1.2.4 Power Supply Pins