Freescale MC9S12KT256, MC9S12KG256, MC9S12KG128, MC9S12KL128, MC9S12KC128 User Guide
...
MC9S12K Family
Device User Guide
Covers MC9S12KT256, MC9S12KG256,
MC9S12KG128, MC9S12KL128, MC9S12KC128,
MC9S12KG64, MC9S12KL64, MC9S12KC64
and MC9S12KG32
HCS12
Microcontrollers
9S12KT256DGV1/D
V01.09
9 SEP 2004
freescale.com
Device User Guide — 9S12KT256DGV1/D V01.09
Revision History
Version
Number
01.00 16 JUL 02 Original Version.
01.01 22 NOV 02
01.02 15 JAN 03
01.03 13 JUN 03 Expand to a K-Family SoC Guide and include 9S12KT256.
01.04 18 JUN 03 Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.
01.05 14 NOV 03
01.06 10 FEB 04 Updated Table A-7 3.3V I/O Characteristics.
01.07 13 MAY 04
01.08 20 JUL 04
01.09 9 SEP 04
Revision
Date
Author Description of Changes
Change load cap value on VDD and VDDPLL.
Correct expanded bus timing from 20MHz to 25 MHz.
Move ATD interrupt vector from $ffd0 to $ffd2.
Change PWeh and tDSW parameter in external bus timing.
Changed to a Device User Guide and added Document number.
Updated Table A-17 Oscillator Characteristics.
Replaced XCLKS with PE7 for Clock Selection diagrams.
Added CTRL to Table 2-1 Signal Properties.
Replaced Burst programming with Row Programming in NVM
electricals.
Changed Digital logic to Internal Logic.
Added LRAE bootloader information.
Changed PWEL, PWEH, t
and t
t
P0V
Added voltage regulator characteristics.
Updated Table A-16 NVM Timing Characteristics.
Corrected A.6.1.2 Row Programming time t
Expanded K-family to include 9S12KC128, 9S12KC64, 9S12KL128
and 9S12KL64.
Updated osciilator start up time and supply current characteristics.
Added ATDCTL0 and ATDCTL1 register bits to Sec 1.7.
in the external bus timing.
P1V
DSW
, t
ACCE
, t
, t
NAD
NAV
bwpgm
, t
RWV
equation
, t
, t
LSV
NOV
,
2
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Table of Contents
Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4 MC9S12KG(L)(C)128(64)(32) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5 MC9S12KT(G)256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.8 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.4 VREGEN — Voltage Regulator Enable Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.5 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 61
2.3.7 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]. . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.8 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 61
2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 62
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.14 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.16 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.17 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.18 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Device User Guide — 9S12KT256DGV1/D V01.09
2.3.20 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.21 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.22 PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.23 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.24 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.25 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.26 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.27 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.28 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . 65
2.3.29 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.30 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.31 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.32 PM7 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.33 PM6 / RXCAN4 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.34 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . 66
2.3.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . 66
2.3.36 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . 67
2.3.37 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . 67
2.3.38 PM1 / TXCAN0 — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.39 PM0 / RXCAN0 — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.40 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.41 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.42 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . .67
2.3.43 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . .68
2.3.44 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.45 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.46 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . .68
2.3.47 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . .68
2.3.48 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.49 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.50 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
2.3.51 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
2.3.52 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
2.3.53 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.54 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
2.3.55 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Device User Guide — 9S12KT256DGV1/D V01.09
2.3.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4.1 VDDX,VSSX — Power Supply Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.2 VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage Regulator
70
2.4.3 VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic . . . . . . . . . 70
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 70
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . 70
Section 3 System Clock Description
Section 4 Modes of Operation
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.1 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2 HCS12 Background Debug Module (BDM) Block Description. . . . . . . . . . . . . . . . . 78
6.3 HCS12 Debug (DBG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.4 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Device User Guide — 9S12KT256DGV1/D V01.09
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 79
6.6 HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . 79
Section 7 Analog to Digital Converter (ATD) Block Description
Section 8 Clock Reset Generator (CRG) Block Description
8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Section 9 EEPROM Block Description
Section 10 Flash EEPROM Block Description
Section 11 IIC Block Description
Section 12 MSCAN Block Description
Section 13 OSC Block Description
Section 14 Port Integration Module (PIM) Block Description
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Serial Communications Interface (SCI) Block Description
Section 17 Serial Peripheral Interface (SPI) Block Description
Section 18 Timer (TIM) Block Description
Section 19 Voltage Regulator (VREG) Block Description
19.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
19.1.1 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Device User Guide — 9S12KT256DGV1/D V01.09
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.2 Voltage Regulator (VREG_3V3) Operating Characteristics. . . . . . . . . . . . . . . . . . . 94
A.3 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
A.5 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.5.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.5.2 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
A.5.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.6 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A.6.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A.6.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.7 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.7.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.7.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
A.7.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.8 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.9.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.9.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
A.10 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
A.10.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix B Package Information
B.1 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
B.2 100-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.3 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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Device User Guide — 9S12KT256DGV1/D V01.09
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Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
List of Figures
Figure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 1-1 MC9S12KG(L)(C)128(64)(32) Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 1-2 MC9S12KT(G)256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 1-3 MC9S12KT256 and MC9S12KG256 Memory Map. . . . . . . . . . . . . . . . . . . . 23
Figure 1-4 MC9S12KG128, MC9S12KL128 and MC9S12KC128 Memory Map . . . . . . 24
Figure 1-5 MC9S12KG64, MC9S12KL64 and MC9S12KC64 Memory Map . . . . . . . . . 25
Figure 1-6 MC9S12KG32 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-1 Pin assignments for 112 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-2 Pin assignments for 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-3 Pin assignments for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1). . . . . . . . . . . . . . . . 62
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . 63
Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure A-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 95
Figure A-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-4 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure B-1 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . 122
Figure B-2 100-pin LQFP Mechanical Dimensions (case no. 983) . . . . . . . . . . . . . . . 123
Figure B-3 112-pin LQFP Mechanical Dimensions (case no. 987) . . . . . . . . . . . . . . . 124
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Device User Guide — 9S12KT256DGV1/D V01.09
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Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
List of Tables
Table 0-1 List of MC9S12K-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 0-2 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 1-1 MC9S12KT(G)256 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-2 MC9S12KG(L)(C)128(64)(32) Device Memory Map . . . . . . . . . . . . . . . . . . . . 22
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 43
Table 1-4 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 1-5 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 2-2 Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 2-3 Clock selection based on PE7 during reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5-2 Reset Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table A-7 3.3V I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table A-8 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-9 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table A-10 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table A-11 5V ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table A-12 3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table A-13 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-14 5V ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-15 3.3V ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-16 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table A-17 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-18 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-19 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table A-20 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table A-21 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table A-22 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table A-23 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table A-24 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12
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Device User Guide — 9S12KT256DGV1/D V01.09
Preface
The Device User Guide provides information about the MC9S12K-Family devices made up of standard
HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A
complete set of device manuals also includes all the individual Block Guides of the implemented modules.
In a effort to reduce redundancy all module specific information is located only in the respective Block
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
Table 0-1 shows a feature overview of the MC9S12K-Family members.
Table 0-1 List of MC9S12K-Family members
Flash RAM EEPROM Device
256K 12K 4K MC9S12KT256 C, V, M 112 LQFP 3 2 3 1 16 8 8 91
256K 12K 4K MC9S12KG256 C, V, M
128K 8K 2K MC9S12KG128 C, V, M
64K 4K 1K MC9S12KG64 C, V, M
32K 2K 1K MC9S12KG32 C, V, M 80 QFP 2 2 2 1 8 7 8 59
128K 6K 2K MC9S12KL128 C, V, M
64K 4K 1K MC9S12KL64 C, V, M
128K 6K None MC9S12KC128 C, V, M
64K 4K None MC9S12KC64 C, V, M
NOTES:
1. C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
2. Number of channels
3. I/O is the sum of ports capable to act as digital input or output.
Temp Options
1
Package CAN SCI SPI IIC
112 LQFP 2 2 3 1 16 8 8 91
80 QFP 2 2 3 1 8 7 8 59
112 LQFP 2 2 3 1 16 8 8 91
100 LQFP 2 2 2 1 13 7 8 79
80 QFP 2 2 2 1 8 7 8 59
112 LQFP 2 2 2 1 16 8 8 91
80 QFP 2 2 2 1 8 7 8 59
112 LQFP 1 1 2 1 16 8 8 91
100 LQFP 1 1 2 1 13 7 8 79
80 QFP 1 1 2 1 8 7 8 59
112 LQFP 1 1 2 1 16 8 8 91
80 QFP 1 1 2 1 8 7 8 59
112 LQFP 1 1 2 1 16 8 8 91
100 LQFP 1 1 2 1 13 7 8 79
80 QFP 1 1 2 1 8 7 8 59
112 LQFP 1 1 2 1 16 8 8 91
80 QFP 1 1 2 1 8 7 8 59
2
A/D
PWM2TIM2I/O
3
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Device User Guide — 9S12KT256DGV1/D V01.09
Figure 0-1 shows the part number coding based on the package and temperature options for the
MC9S12K-Family.
MC9S12 KT256 C FU
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
Package Option
Temperature Option
Device Title
Controller Family
M = -40˚C to 125˚C
Package Options
PV = 112LQFP
PU = 100LQFP
FU = 80QFP
Figure 0-1 Order Part number Coding
Table 0-2 shows names and versions of the referenced documents throughout the Device User Guide.
Table 0-2 Document References
User Guide Version Document Order Number
CPU12 Reference Manual V02 S12CPUV2/D
HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D
HCS12 Debug (DBG) Block Guide V01 S12DBGV1/D
HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D
HCS12 Multiplexed Expanded Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D
HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D
Analog to Digital Converter: 10-Bit, 16 Channels (ATD_10B16C) Block Guide V03
Analog to Digital Converter: 10-Bit, 8 Channels (ATD_10B8C) Block Guide V03
Clock and Reset Generator (CRG) Block Guide V04 S12CRGV4/D
2K Byte EEPROM (EETS2K) Block Guide V01
4K Byte EEPROM (EETS4K) Block Guide V02
128K Byte Flash with Error Code Correction (FTS128K1ECC) Block Guide V01
256K Byte Flash with Error Code Correction (FTS256K2ECC) Block Guide V01
Inter IC Bus (IIC) Block Guide V02 S12IICV2/D
Motorola Scalable CAN (MSCAN) Block Guide V02 S12MSCANV2/D
Oscillator Loop Control Pierce (OSC_LCP) Block Guide V01 S12OSCLCPV1/D
Port Integration Module
Port Integration Module
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide V01 S12PWM8B6CV1/D
Serial Communications Interface (SCI) Block Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block Guide V03 S12SPIV3/D
Timer: 16-Bit, 8 Channels (TIM_16B8C) Block Guide V01 S12TIM16B8CV1/D
Voltage Regulator (VREG_3V3) Block Guide V01 S12VREG3V3V1/D
NOTES:
1. Block Guide for MC9S12K-Family except MC9S12KT256 and MC9S12KG256.
2. Block Guide for MC9S12KT256 and MC9S12KG256 only.
(1)
(PIM_9KG128) Block Guide
(2)
(PIM_9KT256) Block Guide
V01 S12KG128PIMV1/D
V01 S12KT256PIMV1/D
S12ATD10B16CV3/D
S12ATD10B8CV3/D
S12EETS2KV1/D
S12EETS4KV2/D
FTS128K1ECCV1/D
FTS256K2ECCV1/D
1
2
(1)
(2)
(1)
(2)
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Device User Guide — 9S12KT256DGV1/D V01.09
Section 1 Introduction
1.1 Overview
The MC9S12K-Family is a 112/100/80 pin 16-bit Flash-based microcontroller family targeted for high
reliability systems. Members of the MC9S12K-Family have an increased performance in reliability over
the life of the product due to a built-in Error Checking and Correction Code (ECC) in the Flash memory.
The program and erase operations automatically generate six parity bits per word making ECC transparent
to the user.
All members of the MC9S12K-Family are comprised of standard on-chip peripherals including a 16-bit
central processing unit (CPU12), up to 256K bytes of Flash EEPROM, up to 4K bytes of EEPROM, up to
12K bytes of RAM, up to two asynchronous serial communications interface (SCI), up to three serial
peripheral interface (SPI), IIC-bus, an 8-channel IC/OC timer, 16-channel or two 8-channel 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), up to three CAN 2.0 A,
B software compatible modules, 29 discrete digital I/O channels (Port A, Port B, Port E and Port K), and
20 discrete digital I/O lines with interrupt and wakeup capability. The MC9S12K-Family has full 16-bit
data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Memory Map and Interface)
– INT (Interrupt Controller)
– DBG (Debugger)
– BDM (Background Debug Mode)
• Oscillator
– 4Mhz to 16Mhz frequency range
– Pierce with amplitude loop control
– Clock monitor
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Device User Guide — 9S12KT256DGV1/D V01.09
• Clock and Reset Generator (CRG)
– Phase-locked loop clock frequency multiplier
– Self Clock mode in absence of external clock
– COP watchdog
– Real Time interrupt (RTI)
• Memory
– 32K, 64K, 128K or 256K Byte Flash EEPROM
i. Internal program/erase voltage generation
ii. Security and Block Protect bits
iii. Hamming Error Correction Coding (ECC)
– 1K, 2K or 4K Byte EEPROM
– 2K, 4K, 6K, 8K or 12K Byte static RAM
Single-cycle misaligned word accesses without wait states
• Analog-to-Digital Converter(s) (ADC)
– One 16-channel module with 10-bit resolution except for MC9S12KT256 and MC9S12KG256
– Two 8-channel module with 10-bit resolution for MC9S12KT256 and MC9S12KG256
– External conversion trigger capability
• 8-channel Timer (TIM)
– Programmable input capture or output compare channels
– Simple PWM mode
– Counter Modulo Reset
– External Event Counting
– Gated Time Accumulation
• 8-channel Pulse Width Modulator (PWM)
– Programmable period and duty cycle per channel
– 8-bit 8-channel or 16-bit 4-channel
– Edge and center aligned PWM signals
– Emergency shutdown input
• Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
16
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Device User Guide — 9S12KT256DGV1/D V01.09
– Low-pass filter wake-up function
– Loop-back for self test operation
• Serial interfaces
– Two asynchronous serial communication interface (SCI)
– Three synchronous serial peripheral interface (SPI)
– Inter-IC Bus (IIC)
• Internal 2.5V Regulator
– Input voltage range from 3.15V to 5.5V
– Low power mode capability
– Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)
• 20 key wake up inputs
– Rising or falling edge triggered interrupt capability
– Digital filter to prevent short pulses from triggering interrupts
– Programmable pull ups and pull downs
• Operating frequency for ambient temperatures (TA -40°C to 125°C)
– 50MHz equivalent to 25MHz Bus Speed
• 112-Pin LQFP, 100-Pin LQFP, or 80-Pin QFP package
– I/O lines with 3.3V/5V input and drive capability
– 3.3V/5V A/D converter inputs
1.3 Modes of Operation
• Normal modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
• Each of the above modes of operation can be configured for three Low power submodes
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Device User Guide — 9S12KT256DGV1/D V01.09
– Stop Mode
– Pseudo Stop Mode
– Wait Mode
• Secure operation, preventing the unauthorized read and write of the memory contents.
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Device User Guide — 9S12KT256DGV1/D V01.09
1.4 MC9S12KG(L)(C)128(64)(32) Block Diagram
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XTAL
EXTAL
VSSPLL
VDDPLL
XFC
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Single-wire BDM
OSC
PLL
PTE
PA7
PA6
ADDR15
ADDR14
DATA15
DATA14
DAT A7
DAT A6
Internal Logic 2.5V
V
DD1,2
V
SS1,2
Voltage Regulator 3.3V/5V
V
DDR
V
SSR
128K Byte Flash EEPROM
2K Byte EEPROM
8K Byte RAM
Voltage Regulator
Periodic Interrupt
COP Watchdog
Clock Monitor
CRG
XIRQ
IRQ
R/
W
LSTRB
ECLK
DDRE
MODA
MODB
NOACC/
XCLKS
CPU12
Breakpoints
Debugger
System
Integration
Module
(SIM)
Multiplexed Address/Data Bus
DDRA DDRB
PTA PTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
DATA11
DATA10
DAT A3
DAT A2
SSX
PA0
ADDR9
ADDR8
DAT A9
DAT A8
DAT A1
DAT A0
V
DDA
V
SSA
PB4
PB7
PB6
PB5
ADDR4
ADDR7
ADDR6
ADDR5
DAT A4
DAT A7
DAT A6
DAT A5
OSC/PLL 2.5V
V
DDPLL
V
SSPLL
PA5
ADDR12
ADDR13
DATA12
DATA13
DAT A4
DAT A5
I/O Driver 3.3V/5V
V
DDX
V
A/D Converter 3.3V/5V
Voltage Reference
PB3
PB2
ADDR3
ADDR2
DAT A3
DAT A2
PB1
PB0
ADDR1
ADDR0
DAT A1
DAT A0
ATD
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
Module to
Port Routing
KWJ0
KWJ1
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PAD
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
PPAGE
TIM
SCI0
SCI1
MISO
MOSI
SPI0
CAN0
CAN4
IIC
PWM
SPI1
SPI2
SCK
SS
RxCAN
TxCAN PM1
RxCAN
TxCAN
SDA
SCL
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VRH
VRL
VDDA
VSSA
DDRK
DDRT
DDRS
DDRM
DDRJ
DDRP
DDRH
PAD
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
Signals shown in Bold are not available on n the 80 Pin Package
Figure 1-1 MC9S12KG(L)(C)128(64)(32) Block Diagram
Freescale Semiconductor
19
Device User Guide — 9S12KT256DGV1/D V01.09
1.5 MC9S12KT(G)256 Block Diagram
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XTAL
EXTAL
VSSPLL
VDDPLL
XFC
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Single-wire BDM
OSC
PLL
PTE
PA7
PA6
ADDR15
ADDR14
DATA15
DATA14
DAT A7
DAT A6
Internal Logic 2.5V
V
DD1,2
V
SS1,2
Voltage Regulator 3.3V/5V
V
DDR
V
SSR
256K Byte Flash EEPROM
4K Byte EEPROM
12K Byte RAM
Voltage Regulator
Periodic Interrupt
COP Watchdog
Clock Monitor
CRG
XIRQ
IRQ
R/
W
LSTRB
ECLK
DDRE
MODA
MODB
NOACC/
XCLKS
CPU12
Breakpoints
Debugger
System
Integration
Module
(SIM)
Multiplexed Address/Data Bus
DDRA DDRB
PTA PTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
DATA11
DATA10
DAT A3
DAT A2
SSX
PA0
ADDR9
ADDR8
DAT A9
DAT A8
DAT A1
DAT A0
V
DDA
V
SSA
PB4
PB7
PB6
PB5
ADDR4
ADDR7
ADDR6
ADDR5
DAT A4
DAT A7
DAT A6
DAT A5
OSC/PLL 2.5V
V
DDPLL
V
SSPLL
PA5
ADDR12
ADDR13
DATA12
DATA13
DAT A4
DAT A5
I/O Driver 3.3V/5V
V
DDX
V
A/D Converter 3.3V/5V
Voltage Reference
PB3
PB2
ADDR3
ADDR2
DAT A3
DAT A2
PB1
PB0
ADDR1
ADDR0
DAT A1
DAT A0
VRH
ATD0
VRL
VDDA
VSSA
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PPAGE
TIM
SCI0
SCI1
SPI0
RxCAN
CAN0
TxCAN PM1
RxCAN
CAN1
TxCAN
RxCAN
CAN4
TxCAN
IIC
PWM
SPI1
SPI2
MISO
MOSI
SCK
SS
SDA
SCL
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
AD0
VRH
VRL
VDDA
VSSA
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
ATD1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
Module to
Port Routing
KWJ0
KWJ1
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
VRH
VRL
VDDA
VSSA
DDRK
DDRT
DDRS
DDRM
DDRJ
DDRP
DDRH
AD1
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
Signals shown in Bold are not available on n the 80 Pin Package
20
Figure 1-2 MC9S12KT(G)256 Block Diagram
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1.6 Device Memory Map
Table 1-1 shows the device register map of the MC9S12KT256 and MC9S12KG256 after reset. Table
1-2 shows the device register map of the MC9S12KG128(64)(32), MC9S12KL128(64) and
MC9S12KC128(64) after reset.
Table 1-1 MC9S12KT(G)256 Device Memory Map
Address Module Size
$000 - $017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$018 Reserved 1
$019 Voltage Regulator (VREG) 1
$01A - $01B Device ID register (PARTID) 2
$01C - $01F CORE (MEMSIZ, IRQ, HPRIO) 4
$020 - $02F CORE (DBG) 16
$030 - $033 CORE (PPAGE, Port K) 4
$034 - $03F Clock and Reset Generator (PLL, RTI, COP) 12
$040 - $06F Standard Timer 16-bit 8 channels (TIM) 48
$070 - $07F Reserved 16
$080 - $09F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
$0A0 - $0C7 Reserved 40
$0C8 - $0CF Serial Communications Interface 0 (SCI0) 8
$0D0 - $0D7 Serial Communications Interface 1 (SCI1) 8
$0D8 - $0DF Serial Peripheral Interface 0 (SPI0) 8
$0E0 - $0E7 Inter Integrated Circuit Bus (IIC) 8
$0E8 - $0EF Reserved 8
$0F0 - $0F7 Serial Peripheral Interface 1 (SPI1) 8
$0F8 - $0FF Serial Peripheral Interface 2 (SPI2) 8
$100- $10F Flash Control Register 16
$110- $11B EEPROM Control Register 12
$11C - $11F Reserved 4
$120 - $13F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
$140 - $17F Motorola Scalable Controller Area Network 0 (CAN0) 64
$180 - $1BF Motorola Scalable Controller Area Network 1 (CAN1) 64
$1C0 - $23F Reserved 128
$240 - $27F Port Integration Module (PIM) 64
$280 - $2BF Motorola Scalable Controller Area Network 4 (CAN4) 64
$2C0 - $2E7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$2E8 - $3FF Reserved 280
Freescale Semiconductor
21
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-2 MC9S12KG(L)(C)128(64)(32) Device Memory Map
Address Module Size
$000 - $017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$018 Reserved 1
$019 Voltage Regulator (VREG) 1
$01A - $01B Device ID register (PARTID) 2
$01C - $01F CORE (MEMSIZ, IRQ, HPRIO) 4
$020 - $02F CORE (DBG) 16
$030 - $033 CORE (PPAGE, Port K) 4
$034 - $03F Clock and Reset Generator (PLL, RTI, COP) 12
$040 - $06F Standard Timer 16-bit 8 channels (TIM) 48
$070 - $07F Reserved 16
$080 - $0AF Analog to Digital Converter 10-bit 16 channels (ATD) 48
$0B0 - $0C7 Reserved 24
$0C8 - $0CF Serial Communications Interface 0 (SCI0) 8
$0D0 - $0D7 Serial Communications Interface 1 (SCI1) 8
$0D8 - $0DF Serial Peripheral Interface 0 (SPI0) 8
$0E0 - $0E7 Inter Integrated Circuit Bus (IIC) 8
$0E8 - $0EF Reserved 8
$0F0 - $0F7 Serial Peripheral Interface 1 (SPI1) 8
$0F8 - $0FF Serial Peripheral Interface 2 (SPI2) 8
$100- $10F Flash Control Register 16
$110- $11B EEPROM Control Register 12
$11C - $13F Reserved 36
$140 - $17F Motorola Scalable Controller Area Network 0 (CAN0) 64
$180 - $23F Reserved 192
$240 - $27F Port Integration Module (PIM) 64
$280 - $2BF Motorola Scalable Controller Area Network 4 (CAN4) 64
$2C0 - $2E7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$2E8 - $3FF Reserved 280
22
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-4 illustrates the full user configurable device memory map of MC9S12KT256 and
MC9S12KG256.
$0000
$0400
$1000
$4000
$8000
$C000
$FF00
$FFFF
NORMAL
SINGLE CHIP
EXT
VECTORSVECTORS VECTORS
EXPANDED SPECIAL
SINGLE CHIP
$0000
$03FF
$0000
$0FFF
$1000
$3FFF
$4000
$7FFF
$8000
$BFFF
$C000
$FFFF
$FF00
$FFFF
1K Register Space
Mappable to any 2K Boundary
4K Bytes EEPROM
Mappable to any 4K Boundary
12K Bytes RAM
Mappable to any 16K Boundary
and alignable to top or bottom
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
16K Page Window
sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM
$0000 - $0FFF: 4K EEPROM (1K hidden behind Register Space)
Figure 1-3 MC9S12KT256 and MC9S12KG256 Memory Map
Freescale Semiconductor
23
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-4 illustrates the full user configurable device memory map of MC9S12KG128, MC9S12KL128
and MC9S12KC128.
$0000
$0400
$0800
$1000
$2000
$4000
$8000
$C000
$FF00
$FFFF
NORMAL
SINGLE CHIP
EXT
VECTORSVECTORS VECTORS
EXPANDED SPECIAL
SINGLE CHIP
$0000
$03FF
$0800
$0FFF
$2000
$3FFF
$4000
$7FFF
$8000
$BFFF
$C000
$FFFF
$FF00
$FFFF
1K Register Space
Mappable to any 2K Boundary
2K Bytes EEPROM
Mappable to any 2K Boundary
8K Bytes RAM
Mappable to any 8K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
16K Page Window
eight * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (1K RAM hidden behind Register Space)
$0000 - $07FF: 2K EEPROM (not visible)
Figure 1-4 MC9S12KG128, MC9S12KL128 and MC9S12KC128 Memory Map
24
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-5 illustrates the full user configurable device memory map of MC9S12KG64, MC9S12KL64
and MC9S12KC64.
$0000
$0400
$0800
$1000
$3000
$4000
$8000
$C000
$FF00
$FFFF
NORMAL
SINGLE CHIP
EXT
VECTORSVECTORS VECTORS
EXPANDED SPECIAL
SINGLE CHIP
$0000
$03FF
$0800
$0FFF
$3000
$3FFF
$4000
$7FFF
$8000
$BFFF
$C000
$FFFF
$FF00
$FFFF
1K Register Space
Mappable to any 2K Boundary
1K Bytes EEPROM
Mappable to any 2K Boundary
(1K mapped two times in 2K space)
4K Bytes RAM
Mappable to any 4K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
16K Page Window
four * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (1K RAM hidden behind Register Space)
$0000 - $03FF: 1K EEPROM (not visible)
Figure 1-5 MC9S12KG64, MC9S12KL64 and MC9S12KC64 Memory Map
Freescale Semiconductor
25
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-6 illustrates the full user configurable device memory map of MC9S12KG32.
$0000
$0400
$0800
$1000
$3800
$4000
$8000
$FF00
$FFFF
NORMAL
SINGLE CHIP
EXT
VECTORSVECTORS VECTORS
EXPANDED SPECIAL
SINGLE CHIP
$0000
$03FF
$0800
$0FFF
$3800
$3FFF
$8000
$FFFF
$FF00
$FFFF
1K Register Space
Mappable to any 2K Boundary
1K Bytes EEPROM
Mappable to any 2K Boundary
(1K mapped two times in 2K space)
2K Bytes RAM
Mappable to any 2K Boundary
32K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
26
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $07FF: 2K RAM (1K RAM hidden behind Register Space)
$0000 - $03FF: 1K EEPROM (not visible)
Figure 1-6 MC9S12KG32 Memory Map
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
1.7 Detailed Register Map
The following tables show the detailed register map of the MC9S12K-Family.
$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0000 PORTA
$0001 PORTB
$0002 DDRA
$0003 DDRB
$0004 Reserved
$0005 Reserved
$0006 Reserved
$0007 Reserved
$0008 PORTE
$0009 DDRE
$000A PEAR
$000B MODE
$000C PUCR
$000D RDRIV
$000E EBICTL
$000F Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0 0 0 0 0 0 0 0
Write:
Read: 0 0 0 0 0 0 0 0
Write:
Read: 0 0 0 0 0 0 0 0
Write:
Read: 0 0 0 0 0 0 0 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0 0 0 0 0 0 0
Write:
Read: 0 0 0 0 0 0 0 0
Write:
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2
Bit 7 6 5 4 3 Bit 2
NOACCE
MODC MODB MODA
PUPKE
RDPK
0
0 0
0 0
PIPOE NECLK LSTRE RDWE
0
PUPEE
RDPE
IVIS
0 0
0 0
0
Bit 1 Bit 0
0 0
0 0
EMK EME
PUPBE PUPAE
RDPB RDPA
ESTR
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0010 INITRM
$0011 INITRG
Freescale Semiconductor
Read:
Write:
Read: 0
Write:
RAM15 RAM14 RAM13 RAM12 RAM11
REG14 REG13 REG12 REG11
0 0
0 0 0
RAMHAL
27
Device User Guide — 9S12KT256DGV1/D V01.09
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0012 INITEE
$0013 MISC
$0014
Reserved
Read:
Write:
Read: 0 0 0 0
Write:
Read: 0 0 0 0 0 0 0 0
Write:
EE15 EE14 EE13 EE12 EE11
EXSTR1 EXSTR0 ROMHM ROMON
0 0
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0015 ITCR
$0016 ITEST
Read: 0 0 0
Write:
Read:
Write:
INTE INTC INTA INT8 INT6 INT4 INT2 INT0
WRINT ADR3 ADR2 ADR1 ADR0
$0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control)
EEON
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0017 Reserved
Read: 0 0 0 0 0 0 0 0
Write:
$0018 - $0018 Miscellaneous Peripherals (Device Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0018 Reserved
Read: 0 0 0 0 0 0 0 0
Write:
$0019 - $0019 VREG3V3 (Voltage Regulator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0019 VREGCTRL
Read: 0 0 0 0 0 LVDS
Write:
LVIE LVIF
$001A - $001B Miscellaneous Peripherals (Device Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001A PARTIDH
$001B PARTIDL
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
28
Freescale Semiconductor
Device User Guide — 9S12KT256DGV1/D V01.09
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Device
Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001C MEMSIZ0
$001D MEMSIZ1
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
Write:
Read: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0
Write:
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001E INTCR
Read:
Write:
IRQE IRQEN
0 0 0 0 0 0
$001F - $001F INT map 2 of 2 (HCS12 Interrupt)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001F HPRIO
Read:
Write:
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
$0020 - $002F DBG (including BKP) map 1of 1 (HCS12 Debug)
Addres
s
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DBGC1 read
-
write
DBGSC read
-
DBGTBH
-
DBGTBL read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- write
DBGCNT read TBF 0 CNT
- write
DBGCCX read
- write
DBGCCH read
DBGCCL read
- write
write
read
write
write
DBGC2 read
BKPCT0
write
DBGC3 read
BKPCT1
DBGCAX
BKP0X
DBGCAH read
BKP0H write
write
read
write
DBGEN ARM TRGSEL BEGIN DBGBRK
AF BF CF 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
PAGSEL EXTCMP
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC
BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB
PAGSEL EXTCMP
Bit 15 14 13 12 11 10 9 Bit 8
0
TRG
CAPMOD
Freescale Semiconductor
29
Device User Guide — 9S12KT256DGV1/D V01.09
$0020 - $002F DBG (including BKP) map 1of 1 (HCS12 Debug)
Addres
s
$002C
$002D
$002E
$002F
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DBGCAL read
BKP0L write
DBGCBX read
BKP1X write
DBGCBH read
BKP1H write
DBGCBL read
BKP1L write
Bit 7 6 5 4 3 2 1 Bit 0
PAGSEL EXTCMP
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0030 PPAGE
$0031 Reserved
Read: 0 0
Write:
Read: 0 0 0 0 0 0 0 0
Write:
PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0032 PORTK
$0033 DDRK
Read:
Write:
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0034 SYNR
$0035 REFDV
$0036
$0037 CRGFLG
$0038 CRGINT
$0039 CLKSEL
$003A PLLCTL
$003B RTICTL
$003C COPCTL
TEST ONLY
30
CTFLG
Read: 0 0
Write:
Read: 0 0 0 0
Write:
Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
RTIF PROF
RTIE
PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
CME PLLON AUTO ACQ
WCOP RSBCK
0 0
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
REFDV3 REFDV2 REFDV1 REFDV0
0
LOCKIF
LOCKIE
0 0 0
LOCK TRACK
0 0
0
PRE PCE SCME
CR2 CR1 CR0
SCMIF
SCMIE
Freescale Semiconductor
SCM
0
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