Device User Guide
Covers MC9S12KT256, MC9S12KG256,
MC9S12KG128, MC9S12KL128, MC9S12KC128,
MC9S12KG64, MC9S12KL64, MC9S12KC64
and MC9S12KG32
HCS12
Microcontrollers
9S12KT256DGV1/D
V01.09
9 SEP 2004
freescale.com
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Device User Guide — 9S12KT256DGV1/D V01.09
Revision History
Version
Number
01.0016 JUL 02Original Version.
01.0122 NOV 02
01.0215 JAN 03
01.0313 JUN 03Expand to a K-Family SoC Guide and include 9S12KT256.
01.0418 JUN 03Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.
01.0514 NOV 03
01.0610 FEB 04Updated Table A-7 3.3V I/O Characteristics.
01.0713 MAY 04
01.0820 JUL 04
01.099 SEP 04
Revision
Date
AuthorDescription of Changes
Change load cap value on VDD and VDDPLL.
Correct expanded bus timing from 20MHz to 25 MHz.
Move ATD interrupt vector from $ffd0 to $ffd2.
Change PWeh and tDSW parameter in external bus timing.
Changed to a Device User Guide and added Document number.
Updated Table A-17 Oscillator Characteristics.
Replaced XCLKS with PE7 for Clock Selection diagrams.
Added CTRL to Table 2-1 Signal Properties.
Replaced Burst programming with Row Programming in NVM
electricals.
Changed Digital logic to Internal Logic.
Added LRAE bootloader information.
Changed PWEL, PWEH, t
and t
t
P0V
Added voltage regulator characteristics.
Updated Table A-16 NVM Timing Characteristics.
Corrected A.6.1.2 Row Programming time t
Expanded K-family to include 9S12KC128, 9S12KC64, 9S12KL128
and 9S12KL64.
Updated osciilator start up time and supply current characteristics.
Added ATDCTL0 and ATDCTL1 register bits to Sec 1.7.
The Device User Guide provides information about the MC9S12K-Family devices made up of standard
HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A
complete set of device manuals also includes all the individual Block Guides of the implemented modules.
In a effort to reduce redundancy all module specific information is located only in the respective Block
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
Table 0-1 shows a feature overview of the MC9S12K-Family members.
Table 0-1 List of MC9S12K-Family members
Flash RAM EEPROMDevice
256K12K4KMC9S12KT256C, V, M112 LQFP3231168891
256K12K4KMC9S12KG256C, V, M
128K8K2KMC9S12KG128C, V, M
64K4K1KMC9S12KG64C, V, M
32K2K1KMC9S12KG32C, V, M80 QFP222187859
128K6K2KMC9S12KL128C, V, M
64K4K1KMC9S12KL64C, V, M
128K6KNoneMC9S12KC128C, V, M
64K4KNoneMC9S12KC64C, V, M
NOTES:
1. C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
2. Number of channels
3. I/O is the sum of ports capable to act as digital input or output.
Voltage Regulator (VREG_3V3) Block GuideV01S12VREG3V3V1/D
NOTES:
1. Block Guide for MC9S12K-Family except MC9S12KT256 and MC9S12KG256.
2. Block Guide for MC9S12KT256 and MC9S12KG256 only.
(1)
(PIM_9KG128) Block Guide
(2)
(PIM_9KT256) Block Guide
V01S12KG128PIMV1/D
V01S12KT256PIMV1/D
S12ATD10B16CV3/D
S12ATD10B8CV3/D
S12EETS2KV1/D
S12EETS4KV2/D
FTS128K1ECCV1/D
FTS256K2ECCV1/D
1
2
(1)
(2)
(1)
(2)
14
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Section 1 Introduction
1.1 Overview
The MC9S12K-Family is a 112/100/80 pin 16-bit Flash-based microcontroller family targeted for high
reliability systems. Members of the MC9S12K-Family have an increased performance in reliability over
the life of the product due to a built-in Error Checking and Correction Code (ECC) in the Flash memory.
The program and erase operations automatically generate six parity bits per word making ECC transparent
to the user.
All members of the MC9S12K-Family are comprised of standard on-chip peripherals including a 16-bit
central processing unit (CPU12), up to 256K bytes of Flash EEPROM, up to 4K bytes of EEPROM, up to
12K bytes of RAM, up to two asynchronous serial communications interface (SCI), up to three serial
peripheral interface (SPI), IIC-bus, an 8-channel IC/OC timer, 16-channel or two 8-channel 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), up to three CAN 2.0 A,
B software compatible modules, 29 discrete digital I/O channels (Port A, Port B, Port E and Port K), and
20 discrete digital I/O lines with interrupt and wakeup capability. The MC9S12K-Family has full 16-bit
data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
•HCS12 Core
–16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
–MEBI (Multiplexed External Bus Interface)
–MMC (Memory Map and Interface)
–INT (Interrupt Controller)
–DBG (Debugger)
–BDM (Background Debug Mode)
•Oscillator
–4Mhz to 16Mhz frequency range
–Pierce with amplitude loop control
–Clock monitor
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
•Clock and Reset Generator (CRG)
–Phase-locked loop clock frequency multiplier
–Self Clock mode in absence of external clock
–COP watchdog
–Real Time interrupt (RTI)
•Memory
–32K, 64K, 128K or 256K Byte Flash EEPROM
i. Internal program/erase voltage generation
ii. Security and Block Protect bits
iii. Hamming Error Correction Coding (ECC)
–1K, 2K or 4K Byte EEPROM
–2K, 4K, 6K, 8K or 12K Byte static RAM
Single-cycle misaligned word accesses without wait states
•Analog-to-Digital Converter(s) (ADC)
–One 16-channel module with 10-bit resolution except for MC9S12KT256 and MC9S12KG256
–Two 8-channel module with 10-bit resolution for MC9S12KT256 and MC9S12KG256
–External conversion trigger capability
•8-channel Pulse Width Modulator (PWM)
–Programmable period and duty cycle per channel
–8-bit 8-channel or 16-bit 4-channel
–Edge and center aligned PWM signals
–Emergency shutdown input
•Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules
–Five receive and three transmit buffers
–Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
–Four separate interrupt channels for Rx, Tx, error and wake-up
16
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
–Low-pass filter wake-up function
–Loop-back for self test operation
•Serial interfaces
–Two asynchronous serial communication interface (SCI)
–Three synchronous serial peripheral interface (SPI)
–Inter-IC Bus (IIC)
•Internal 2.5V Regulator
–Input voltage range from 3.15V to 5.5V
–Low power mode capability
–Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)
•20 key wake up inputs
–Rising or falling edge triggered interrupt capability
–Digital filter to prevent short pulses from triggering interrupts
–Programmable pull ups and pull downs
•Operating frequency for ambient temperatures (TA -40°C to 125°C)
–50MHz equivalent to 25MHz Bus Speed
•112-Pin LQFP, 100-Pin LQFP, or 80-Pin QFP package
–I/O lines with 3.3V/5V input and drive capability
–3.3V/5V A/D converter inputs
•Special Operating Modes
–Special Single-Chip Mode with active Background Debug Mode
–Special Test Mode (Motorola use only)
–Special Peripheral Mode (Motorola use only)
• Each of the above modes of operation can be configured for three Low power submodes
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
–Stop Mode
–Pseudo Stop Mode
–Wait Mode
•Secure operation, preventing the unauthorized read and write of the memory contents.
18
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
1.4 MC9S12KG(L)(C)128(64)(32) Block Diagram
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XTAL
EXTAL
VSSPLL
VDDPLL
XFC
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Single-wire BDM
OSC
PLL
PTE
PA7
PA6
ADDR15
ADDR14
DATA15
DATA14
DAT A7
DAT A6
Internal Logic 2.5V
V
DD1,2
V
SS1,2
Voltage Regulator 3.3V/5V
V
DDR
V
SSR
128K Byte Flash EEPROM
2K Byte EEPROM
8K Byte RAM
Voltage Regulator
Periodic Interrupt
COP Watchdog
Clock Monitor
CRG
XIRQ
IRQ
R/
W
LSTRB
ECLK
DDRE
MODA
MODB
NOACC/
XCLKS
CPU12
Breakpoints
Debugger
System
Integration
Module
(SIM)
Multiplexed Address/Data Bus
DDRADDRB
PTAPTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
DATA11
DATA10
DAT A3
DAT A2
SSX
PA0
ADDR9
ADDR8
DAT A9
DAT A8
DAT A1
DAT A0
V
DDA
V
SSA
PB4
PB7
PB6
PB5
ADDR4
ADDR7
ADDR6
ADDR5
DAT A4
DAT A7
DAT A6
DAT A5
OSC/PLL 2.5V
V
DDPLL
V
SSPLL
PA5
ADDR12
ADDR13
DATA12
DATA13
DAT A4
DAT A5
I/O Driver 3.3V/5V
V
DDX
V
A/D Converter 3.3V/5V
Voltage Reference
PB3
PB2
ADDR3
ADDR2
DAT A3
DAT A2
PB1
PB0
ADDR1
ADDR0
DAT A1
DAT A0
ATD
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
Module to
Port Routing
KWJ0
KWJ1
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PAD
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
PPAGE
TIM
SCI0
SCI1
MISO
MOSI
SPI0
CAN0
CAN4
IIC
PWM
SPI1
SPI2
SCK
SS
RxCAN
TxCANPM1
RxCAN
TxCAN
SDA
SCL
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VRH
VRL
VDDA
VSSA
DDRK
DDRT
DDRS
DDRM
DDRJ
DDRP
DDRH
PAD
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
Signals shown in Bold are not available on n the 80 Pin Package
Signals shown in Bold are not available on n the 80 Pin Package
20
Figure 1-2 MC9S12KT(G)256 Block Diagram
Freescale Semiconductor
Page 21
Device User Guide — 9S12KT256DGV1/D V01.09
1.6 Device Memory Map
Table 1-1 shows the device register map of the MC9S12KT256 and MC9S12KG256 after reset. Table
1-2 shows the device register map of the MC9S12KG128(64)(32), MC9S12KL128(64) and
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset. The read-only value is a unique part ID for each revision of the chip.
ID Numbers shows the assigned part ID number.
Freescale Semiconductor
Table 1-4 Assigned Part
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Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-4 Assigned Part ID Numbers
DeviceMask Set Number
MC9S12KT2560L33V$7000
MC9S12KG1280L74N$7100
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
Part ID
1
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset).
Table 1-5 shows the read-only values of these registers. Refer to HCS12 Module
Mapping and Control (MMC) Block Guide for further details.
The MC9S12K-Family and its derivatives are available in a 112-pin low profile quad flat pack (LQFP), a
100-pin low profile quad flat pack (LQFP), and a 80-pin quad flat pack (QFP). Most pins perform two or
more functions, as described in the Signal Descriptions.
the pin assignments for different packages.
Signals shown in Italic are only available in MC9S12KT256
VSSPLL
VDDPLL
EXTAL
W/PE2
IRQ/PE1
R/
LSTRB/TAGLO/PE3
61
60
VRH
59
VDDA
58
PAD07/AN07
57
PAD06/AN06
56
PAD05/AN05
55
PAD04/AN04
54
PAD03/AN03
53
PAD02/AN02
52
PAD01/AN01
51
PAD00/AN00
50
VSS2
49
VDD2
48
PA7/ADDR15/DATA15
47
PA6/ADDR14/DATA14
46
PA5/ADDR13/DATA13
45
PA4/ADDR12/DATA12
44
PA3/ADDR11/DATA11
43
PA2/ADDR10/DATA10
42
PA1/ADDR9/DATA9
41
PA0/ADDR8/DATA8
40
XIRQ/PE0
56
Figure 2-3 Pin assignments for 80 QFP
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
2.2 Signal Properties Summary
(Table 2-1) summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. (Table 2-2) summarizes the power and ground pins.
Table 2-1 Signal Properties
Internal Pull
Pin Name
Function 1
EXTAL———VDDPLLNANA
XTAL———VDDPLLNANA
RESET———VDDRNoneNoneExternal Reset
TEST———NANANATest Input
VREGEN———VDDXNANAVoltage Regulator Enable Input
XFC———VDDPLLNANAPLL Loop Filter
BKGDTAGHIMODC—VDDR
PAD[15:8]AN[15:8]
PAD[7:0]AN[7:0]
PA[7:0]
PB[7:0]
PE7NOACCXCLKS—VDDRPUCRUpPort E I/O, Access, Clock Select
PE6IPIPE1MODB—VDDR
PE5IPIPE0MODA—VDDR
PE4ECLK——VDDRPUCRUpPort E I/O, Bus Clock Output
PE3LSTRBTAGLO—VDDRPUCRUpPort E I/O, Byte Strobe, Tag Low
PE2R/W——VDDRPUCRUpPort E I/O, R/W in expanded modes
PE1IRQ——VDDR
PE0XIRQ——VDDRPort E Input, Non Maskable Interrupt
PH7KWH7SS2—VDDR
Pin Name
Function 2
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
Pin Name
Function 3
AN1[7:0]
AN0[7:0]
——VDDRPUCRDisabled Port A I/O, Multiplexed Address/Data
——VDDRPUCRDisabled Port B I/O, Multiplexed Address/Data
Pin Name
Function 4
1
1
Powered
by
—VDDANoneNone
—VDDANoneNone
Resistor
CTRL
Always
Up
While RESET
pin is low:
Down
While RESET
pin is low:
Down
Always Up
PERH/
PPSH
Disabled Port H I/O, Interrupt, SS of SPI2
Reset
State
Up
Description
Oscillator Pins
Background Debug, Tag High, Mode
Input
Port AD Input, Analog Inputs of ATD
in MC9S12KG128(64)(32),
MC9S12KL128(64) and
MC9S12KC128(64); Analog Inputs of
ATD1 in MC9S12KT256 and
MC9S12KG256
Port AD Input, Analog Inputs of ATD in
MC9S12KG128(64)(32),
MC9S12KL128(64) and
MC9S12KC128(64); Analog Inputs of
ATD0 in MC9S12KT256 and
MC9S12KG256
Port E I/O, Pipe Status, Mode Input
Port E I/O, Pipe Status, Mode Input
Port E Input, Maskable Interrupt
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Internal Pull
Pin Name
Function 1
PH6KWH6SCK2—VDDR
PH5KWH5MOSI2—VDDR
PH4KWH4MISO2—VDDR
PH3KWH3SS1—VDDR
PH2KWH2SCK1—VDDR
PH1KWH1MOSI1—VDDR
PH0KWH0MISO1—VDDR
PJ7KWJ7TXCAN4SCLVDDX
PJ6KWJ6RXCAN4SDAVDDX
PJ[1:0]KWJ[1:0]——VDDX
PK7ECSROMCTL—VDDXPUCRUp
PK[5:0]XADDR[19:14]——VDDXPUCRUpPort K I/O, Extended Addresses
PM7TXCAN4——VDDX
PM6RXCAN4——VDDX
PM5TXCAN0TXCAN4SCK0VDDX
PM4RXCAN0RXCAN4MOSI0VDDX
PM3
PM2
PM1TXCAN0——VDDX
PM0RXCAN0——VDDX
PP7KWP7 PWM7SCK2VDDX
PP6KWP6PWM6SS2VDDX
PP5KWP5 PWM5MOSI2VDDX
PP4KWP4PWM4MISO2VDDX
Pin Name
Function 2
TXCAN1
RXCAN1
1
1
Pin Name
Function 3
TXCAN0SS0VDDX
RXCAN0MISO0VDDX
Pin Name
Function 4
Powered
by
Resistor
CTRL
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERJ/
PPSJ
PERJ/
PPSJ
PERJ/
PPSJ
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
Reset
Description
State
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Up
Up
UpPort J I/O, Interrupts
Disabled Port M I/O, CAN4 TX
Disabled Port M I/O, CAN4 RX
Disabled
Disabled
Disabled
Disabled
Disabled Port M I/O, CAN0 TX
Disabled Port M I/O, CAN0 RX
Disabled
Disabled
Disabled
Disabled
Port H I/O, Interrupt, SCK of SPI2
Port H I/O, Interrupt, MOSI of SPI2
Port H I/O, Interrupt, MISO of SPI2
Port H I/O, Interrupt, SS of SPI1
Port H I/O, Interrupt, SCK of SPI1
Port H I/O, Interrupt, MOSI of SPI1
Port H I/O, Interrupt, MISO of SPI1
Port J I/O, Interrupt, TX of CAN4,
SCL of IIC
Port J I/O, Interrupt, RX of CAN4,
SDA of IIC
Port K I/O, Emulation Chip Select,
ROM On Enable
Port M I/O, CAN0 TX, CAN4 TX,
SPI0 SCK
Port M I/O, CAN0 RX, CAN4 RX,
SPI0 MOSI
Port M I/O, CAN1 TX, CAN0 TX, SPI0
SS
Port M I/O, CAN1 RX, CAN0 RX, SPI0
MISO
Port P I/O, Interrupt, PWM Channel 7,
SCK of SPI2
Port P I/O, Interrupt, PWM Channel 6,
SPI2
SS
Port P I/O, Interrupt, PWM Channel 5,
SPI2 MOSI
Port P I/O, Interrupt, PWM Channel 4,
SPI2 MISO
58
Freescale Semiconductor
Page 59
Pin Name
Function 1
PP3KWP3 PWM3SS1VDDX
PP2KWP2PWM2SCK1VDDX
PP1KWP1 PWM1MOSI1VDDX
PP0KWP0PWM0MISO1VDDX
PS7SS0——VDDX
PS6SCK0——VDDX
PS5MOSI0——VDDX
PS4MISO0——VDDX
PS3TXD1——VDDX
PS2RXD1——VDDX
PS1TXD0——VDDX
PS0RXD0——VDDX
PT[7:0]IOC[7:0]——VDDX
NOTES:
1. Only available on MC9S12KT256.
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Powered
by
Device User Guide — 9S12KT256DGV1/D V01.09
Internal Pull
Resistor
CTRL
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
Up or
Down
Reset
State
Disabled
Disabled
Disabled
Disabled
UpPort S I/O, SPI0 SS
UpPort S I/O, SPI0 SCK
UpPort S I/O, SPI0 MOSI
UpPort S I/O, SPI0 MISO
UpPort S I/O, SCI1TXD
UpPort S I/O, SCI1RXD
UpPort S I/O, SCI0 TXD
UpPort S I/O, SCI0 RXD
Disabled Port T I/O, Timer channels
Port P I/O, Interrupt, PWM Channel 3,
SPI1
Port P I/O, Interrupt, PWM Channel 2,
SPI1 SCK
Port P I/O, Interrupt, PWM Channel 1,
SPI1 MOSI
Port P I/O, Interrupt, PWM Channel 0,
SPI1 MISO
Description
SS
Mnemonic
VDD1
VDD2
VSS1
VSS2
VDDR3.3/5.0 V
VSSR0 V
VDDX3.3/5.0 V
VSSX0 V
VDDA3.3/5.0 VOperating voltage and ground for the analog-to-digital converter and
VSSA0 V
VRH3.3/5.0 VReference voltage high for the ATD converter.
VRL0 VReference voltage low for the ATD converter.
Freescale Semiconductor
Nominal
Voltage
2.5 V
0V
Table 2-2 Power and Ground
Description
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and
bypass the internal voltage regulator.
External power and ground, supply to pin drivers and internal voltage
regulator.
External power and ground, supply to pin drivers.
the reference for the internal voltage regulator, allows the supply
voltage to the A/D to be bypassed independently.
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Device User Guide — 9S12KT256DGV1/D V01.09
Mnemonic
VDDPLL2.5 VProvides operating voltage and ground for the Phased-Locked Loop.
VSSPLL0 V
Nominal
Voltage
Description
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
NOTE:All VSS pins must be connected together in the application. Because fast signal
transitions place high, short-duration current demands on the power supply, use
bypass capacitors with high-frequency characteristics and place them as close to
the MCU as possible. Bypass requirements depend on MCU pin load.
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE:The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
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2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
MCU
R
C
S
C
P
VDDPLLVDDPLL
Figure 2-4 PLL Loop Filter Connections
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of
RESET.
2.3.7 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]
PAD15 - PAD8 are general purpose input pins and analog inputs of the single analog to digital converter
with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD15 PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels
(ATD1) on MC9S12KT256 and MC9S12KG256.
2.3.8 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD7 - PAD0 are general purpose input pins and analog inputs of the single analog to digital converter
with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD7 PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels
(ATD0) on MC9S12KT256 and MC9S12KG256.
2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
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2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop
Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock
circuitry is used. The state of this pin is latched at the rising edge of
EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic
high a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an
input with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop
Controlled Pierce oscillator circuit on EXTAL and XTAL.
RESET. If the input is a logic low the
Table 2-3 Clock selection based on PE7 during reset
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
R
B
*
R
S
Crystal or
ceramic resonator
C
8
VSSPLL
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0)
MCU
EXTAL
XTAL
not connected
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
Figure 2-7 External Clock Connections (PE7=0)
2.3.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of
RESET. This pin is shared with the
instruction queue tracking signal IPIPE1.
2.3.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of
instruction queue tracking signal IPIPE0.
RESET. This pin is shared with the
2.3.14 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
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2.3.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.16 PE2 / R/W—Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.17 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin
2 (SPI2).
SS of the Serial Peripheral Interface
2.3.20 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK
2 (SPI2).
of the Serial Peripheral Interface
2.3.21 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI
of the Serial Peripheral Interface 2 (SPI2).
2.3.22 PH4 / KWH4 / MISO2 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO
of the Serial Peripheral Interface 2 (SPI2).
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2.3.23 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin
1 (SPI1).
SS of the Serial Peripheral Interface
2.3.24 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK
1 (SPI1).
of the Serial Peripheral Interface
2.3.25 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI
of the Serial Peripheral Interface 1 (SPI1).
2.3.26 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
2.3.29 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.30 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (
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enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.For all other modes the reset state of the ROMON bit is as
follows:
special single : ROMCTL = 1
normal single : ROMCTL = 1
emulation expanded wide : ROMCTL = 0
emulation expanded narrow : ROMCTL = 0
special test : ROMCTL = 0
peripheral test : ROMCTL = 1
2.3.31 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.32 PM7 / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.33 PM6 / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.34 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as
the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as
the master output (during master mode) or slave input pin (during slave mode) MOSI
Peripheral Interface 0 (SPI0).
for the Serial
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2.3.36 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the slave select pin
SS of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the master input (during master mode) or slave output pin (during slave mode) MISO
Peripheral Interface 0 (SPI0).
for the Serial
2.3.38 PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.39 PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.40 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It
can be configured as serial clock pin SCK
of the Serial Peripheral Interface 2 (SPI2).
2.3.41 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin
SS of the Serial Peripheral Interface 2 (SPI2).
2.3.42 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI
the Serial Peripheral Interface 2 (SPI2).
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2.3.43 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO
the Serial Peripheral Interface 2 (SPI2).
of
2.3.44 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin
SS of the Serial Peripheral Interface 1 (SPI1).
2.3.45 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK
of the Serial Peripheral Interface 1 (SPI1).
2.3.46 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI
the Serial Peripheral Interface 1 (SPI1).
of
2.3.47 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO
the Serial Peripheral Interface 1 (SPI1).
of
2.3.48 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.49 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
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2.3.50 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI
of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI
of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
2.3.53 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.54 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.55 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Timer (TIM).
2.4 Power Supply Pins
MC9S12K-Family power and ground pins are described below.
NOTE:All VSS pins must be connected together in the application.
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2.4.1 VDDX,VSSX — Power Supply Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage
Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE:No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
NOTE:No load allowed except for bypass capacitors.
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
HCS12 CORE
BDM
CPU
Core Clock
MEBIMMC
INTDBG
Flash
RAM
EXTAL
XTAL
OSC
CRG
Bus Clock
Oscillator Clock
Figure 3-1 Clock Connections
EEPROM
TIM
ATD
PWM
SCI0, SCI1
SPI0, SPI1, SPI2
CAN0, CAN1, CAN4
IIC
PIM
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12K-Family. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (
operating mode and provide limited mode switching during operation. The states of the MODC, MODB,
and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal
allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is
visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the
ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
(Table 4-1)). The MODC, MODB, and MODA bits in the MODE register show the current
Table 4-1 Mode Selection
BKGD =
MODC
000X1
001
010X0
011
100X1
101
110X1
111
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
01
10
01
10
00
11
00
11
ROMON
Bit
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed b ut b us oper ations would cause
bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 MEBI Block Guide.
Internal Voltage Regulator enabled
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•Protection of the contents of FLASH,
•Protection of the contents of EEPROM,
•Operation in single-chip mode,
•Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
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4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
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4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. Both local masking and CCR masking are included as listed in
be generated through external control of the RESET pin, through the clock and reset generator module
CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG
and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
5.2.1 Vector Table
(Table 5-1) lists interrupt sources and vectors in default order of priority.
1. Interrupt vector is only available on MC9S12KT256. Otherwise it is reserved.
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5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2.
Table 5-2 Reset Summary
ResetPrioritySourceVector
Power-on Reset 1CRG Module$FFFE, $FFFF
External Reset1RESET pin$FFFE, $FFFF
Low Voltage Reset1VREG Module$FFFE, $FFFF
Clock Monitor Reset2CRG Module$FFFC, $FFFD
COP Watchdog Reset 3CRG Module$FFFA, $FFFB
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode
dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
Refer to Table 1-2(Table 1-2) for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit.
When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods.
Consult the HCS12 BDM Block Guide for information about the Background Debug Module.
When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
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6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface
module.
6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). When the ATD_10B16C Block
Guide refers to freeze mode this is equivalent to active BDM mode.
Consult the ATD_10B8C Block Guide for further information about the A/D Converter module for the
MC9S12KT256 and MC9S12KG256. When the ATD_10B8C Block Guide refers to freeze mode this is
equivalent to active BDM mode.
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block Guide for voltage level specifications.
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Section 9 EEPROM Block Description
Consult the EETS2K Block Guide for information about the EEPROM module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the EETS4K Block Guide for information about the EEPROM module for the MC9S12KT256
and MC9S12KG256.
Section 10 Flash EEPROM Block Description
Consult the FTS128K1ECC Block Guide for information about the flash module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the FTS256K2ECC Block Guide for information about the flash module for the MC9S12KT256
and MC9S12KG256.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into
the flash memory of this device during manufacture. This LRAE program will provide greater
programming flexibility to the end users by allowing the device to be programmed directly using SCI after
it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not
required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its
implementation, please see the S12 LREA Application Note (AN2546/D) .
It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE
programmed in the Flash . Exact details of the changeover (ie blank to programmed) for each product will
be communicated in advance via GPCN and will be traceable by the customer via datecode marking on
the device.
Please contact Motorola SPS Sales if you have any additional questions.
Section 11 IIC Block Description
Consult the IIC Block Guide for information about the Inter-IC Bus module.
Section 12 MSCAN Block Description
There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12KT256. There
are only two MSCAN modules (CAN4 and CAN0) implemented on the MC9S12KG128(64)(32). There
is only one MSCAN module (CAN0) implemented on the MC9S12KL128(64) and MC9S12KC128(64).
Consult the MSCAN Block Guide for information about the Motorola Scalable CAN Module.
Section 13 OSC Block Description
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Consult the OSC_LCP Block Guide for information about the Oscillator module.
Section 14 Port Integration Module (PIM) Block Description
Consult the PIM_9KG128 Block Guide for information about the Port Integration Module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the PIM_9KT256 Block Guide for information about the Port Integration Module for the
MC9S12KT256 and MC9S12KG256.
Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator Module. When
the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 16 Serial Communications Interface (SCI) Block
Description
There are two Serial Communications Interface modules (SCI1 and SCI0). Consult the SCI Block Guide
for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block
Description
There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12K-Family.
Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 18 Timer (TIM) Block Description
Consult the TIM_16B8C Block Guide for information about the Timer module. When the TIM_16B8C
Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG_3V3 Block Guide for information about the dual output linear voltage regulator.
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19.1 Device-specific information
19.1.1 VDD1, VDD2, VSS1, VSS2
In all package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the
device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together
internally. VSS1 and VSS2 are connected together internally. This allows systems to employ better supply
routing and further decoupling.
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Appendix A Electrical Characteristics
A.1 General
NOTE:The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
This supplement contains the most accurate electrical information for the MC9S12K-Family of
microcontrollers available at the time of publication. The information should be considered
PRELIMINARY and is subject to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE:This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T:
Those parameters are achieved by design characterization on a small sample size from typical
devices. All values shown in the typical column are within this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12K-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator,
PLL and internal logic.
The VDDA, VSSA pair supplies the A/D converter.
The VDDX, VSSX pair supplies the I/O pins
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The VDDR, VSSR pair supplies the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic.
VDDPLL, VSSPLL supply the oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDD1 and VDD2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE:In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the
sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used
for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is
used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 3.3V/5V I/O pins
Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This
group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The
internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for
the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2 Analog Reference
This group of pins is comprised of the VRH and VRL pins.
A.1.3.3 Oscillator
The pins EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by
VDDPLL.
A.1.3.4 PLL
The pin XFC dedicated to the oscillator have a nominal 2.5V level. It is supplied by VDDPLL.
A.1.3.5 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating V
operating maximum current conditions. If positive injection current (V
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
84
or VDD range during instantaneous and
DD5
in
> V
) is greater than I
DD5
Freescale Semiconductor
DD5
, the
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Device User Guide — 9S12KT256DGV1/D V01.09
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
Table A-1 Absolute Maximum Ratings
NumRatingSymbolMinMaxUnit
SS5
or V
DD5
).
1I/O, Regulator and Analog Supply Voltage
2
Internal Logic Supply Voltage
3
PLL Supply Voltage
(1)
1
4Voltage difference VDDX to VDDR and VDDA
5Voltage difference VSSX to VSSR and VSSA
6Digital I/O Input Voltage
7Analog Reference
8XFC, EXTAL, XTAL inputs
9TEST input
Instantaneous Maximum Current
10
Single pin limit for all digital I/O pins
Instantaneous Maximum Current
11
Single pin limit for XFC, EXTAL, XTAL
Instantaneous Maximum Current
12
Single pin limit for TEST
4
2
3
13Operating Temperature Range (packaged)
14Operating Temperature Range (junction)
15Storage Temperature Range
V
DD5
V
DD
V
DDPLL
∆
VDDX
∆
VSSX
V
V
RH, VRL
V
ILV
V
TEST
I
I
DL
I
DT
T
T
T
stg
-0.36.5V
-0.33.0V
-0.33.0V
-0.30.3V
-0.30.3V
IN
-0.36.5V
-0.36.5V
-0.33.0V
-0.310.0V
D
-25+25mA
-25+25mA
-0.250mA
A
J
– 40 125°C
– 40 140°C
– 65155°C
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
2. All digital I/O pins are internally clamped to V
3. These pins are internally clamped to V
4. This pin is clamped low to V
SSR
SSPLL
, but not clamped high. This pin must be tied low in applications.
and V
SSX
and V
DDPLL
DDX
, V
SSR
and V
DDR
or V
SSA
and V
DDA
.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
ModelDescriptionSymbolValueUnit
Series ResistanceR11500Ohm
Storage CapacitanceC100pF
Human Body
Machine
Latch-up
Number of Pulse per pin
positive
negative
Series ResistanceR10Ohm
Storage CapacitanceC200pF
Number of Pulse per pin
positive
negative
Minimum input voltage limit-2.5V
Maximum input voltage limit7.5V
-
-
3
3
3
3
Table A-3 ESD and Latch-Up Protection Characteristics
NumCRatingSymbolMinMaxUnit
1C Human Body Model (HBM)
2C Machine Model (MM)
3C Charge Device Model (CDM)
Latch-up Current at 125°C
4C
5C
positive
negative
Latch-up Current at 27°C
positive
negative
V
V
HBM
V
CDM
I
LAT
I
LAT
MM
2000-V
200-V
500-V
+100
-100
+200
-200
-mA
-mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
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NOTE:Instead of specifying ambient temperature all parameters are specified for the more
meaningful silicon junction temperature. For power dissipation calculations refer
Section A.1.8 Power Dissipation and Thermal Characteristics.
to
Table A-4 Operating Conditions
RatingSymbolMinTypMaxUnit
(2)
(2)
V
DD5
V
DD
V
DDPLL
∆
VDDX
∆
VSSX
f
osc
f
bus
T
J
2
T
A
T
J
T
A
T
J
T
A
3.153.3/55.5V
2.352.52.75V
2.352.52.75V
-0.100.1V
-0.100.1V
0.5-16MHz
0.5-25MHz
-40-100°C
-402785°C
-40-120°C
-4027105°C
-40-140°C
-4027125°C
I/O, Regulator and Analog Supply Voltage
Internal Logic Supply Voltage
PLL Supply Voltage
Voltage Difference VDDX to VDDA
Voltage Difference VSSX to VSSR and VSSA
Oscillator
Bus Frequency
MC9S12K-FamilyC/MC9S12KT256C
Operating Ambient Temperature Range
MC9S12K-FamilyV/MC9S12KT256V
Operating Ambient Temperature Range
MC9S12K-FamilyM/MC9S12KT256M
Operating Ambient Temperature Range
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
(1)
Operating Junction Temperature Range
Operating Junction Temperature Range
Operating Junction Temperature Range
1
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T
obtained from:
T
T
J
A
Junction Temperature, [°C]=
Ambient Temperature, [°C]=
Freescale Semiconductor
T
T
J
A
P
D
ΘJA•()+=
) in °C can be
J
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Device User Guide — 9S12KT256DGV1/D V01.09
P
Θ
The total power dissipation can be calculated from:
P
Two cases with internal voltage regulator enabled and disabled must be considered:
Total Chip Power Dissipation, [W]=
D
JA
INT
1.Internal Voltage Regulator disabled
Package Thermal Resistance, [°C/W]=
P
Chip Internal Power Dissipation, [W]=
P
INT
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
I
⋅I
DDVDD
P
IO
P
D
INT
DDPLLVDDPLL
R
∑
DSON
i
PIO+=
⋅I
⋅=
+V
DDA
2
I
IO
i
⋅+=
DDA
For R
respectively
2.Internal voltage regulator enabled
I
DDR
additionally contains the current flowing into the external loads with output high.
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
is valid:
DSON
R
DSON
R
DSON
P
INT
is the current shown in Table A-8 and not the overall current flowing into VDDR, which
P
V
OL
------------ for outputs driven low;=
I
OL
V
------------------------------------ for outputs driven high;=
IO
–
DD5VOH
I
OH
I
⋅I
DDRVDDR
∑
i
R
DSON
DDAVDDA
⋅+=
2
I
⋅=
IO
i
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Table A-5 Thermal Package Characteristics
1
NumCRatingSymbolMinTypMaxUnit
1T
2T
3T Thermal Resistance QFP 80, single sided PCB
4T
NOTES:
1. The values for thermal resistance are achieved by package simulations
This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable,
e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
NumCRatingSymbolMinTypMaxUnit
1P Input High Voltage
2P Input Low Voltage
3C Input Hysteresis
Input Leakage Current (pins in high impedance input
4P
mode)
V
= V
in
DD5
or V
SS5
Output High Voltage (pins in output mode)
5P
Partial DriveI
Full DriveI
OH
OH
= –10.0mA
Output Low Voltage (pins in output mode)
6P
7P
8P
9P
Partial DriveI
Full DriveI
OL
= +10.0mA
OL
Internal Pull Up Device Current,
tested at VIL Max.
Internal Pull Up Device Current,
tested at VIH Min.
Internal Pull Down Device Current,
tested at VIH Min.
= –2.0mA
= +2.0mA
V
I
I
V
V
HYS
I
V
OH
V
OL
I
PUL
PUH
PDH
0.65*V
IH
IL
DD5
V
- 0.3
SS5
-
-
V
DD5
0.35*V
+ 0.3
DD5
V
V
250mV
in
–2.5-2.5µA
V
DD5
– 0.8
--V
--0.8V
-- –130µA
-10--µA
--130µA
10P
Internal Pull Down Device Current,
tested at VIL Max.
11D Input Capacitance
1
12T
Injection current
Single Pin limit
Total Device Limit. Sum of all injected currents
13P
14P
Port H, J, P Interrupt Input Pulse filtered
Port H, J, P Interrupt Input Pulse passed
2
(2)
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
I
PDL
C
I
ICS
I
ICP
t
pign
t
pval
10--µA
in
-2.5
-25
7-pF
-2.5
mA
25
3µs
10µs
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Table A-7 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num CRatingSymbolMinTypMaxUnit
1P Input High Voltage
2P Input Low Voltage
3C Input Hysteresis
Input Leakage Current (pins in high impedance input
4P
mode)
V
= V
in
DD5
or V
SS5
Output High Voltage (pins in output mode)
5P
Partial DriveI
Full DriveI
OH
OH
= –4.5mA
Output Low Voltage (pins in output mode)
6P
7P
8P
9P
Partial DriveI
Full DriveI
OL
= +5.5mA
OL
Internal Pull Up Device Current,
tested at VIL Max.
Internal Pull Up Device Current,
tested at VIH Min.
Internal Pull Down Device Current,
tested at VIH Min.
= –0.75mA
= +0.9mA
V
I
I
V
V
HYS
I
V
V
I
PUL
PUH
PDH
IH
IL
in
OH
OL
0.65*V
V
SS5
DD5
- 0.3
-
-
V
DD5
0.35*V
+ 0.3
DD5
250mV
–1-1µA
V
DD5
– 0.4
--V
--0.4V
-- –60µA
-6--µA
--60µA
V
V
10P
Internal Pull Down Device Current,
tested at VIL Max.
11D Input Capacitance
1
12T
Injection current
Single Pin limit
Total Device Limit. Sum of all injected currents
13P
14P
Port P, J Interrupt Input Pulse filtered
Port P, J Interrupt Input Pulse passed
2
(2)
I
PDL
C
I
ICS
I
ICP
t
PULSE
t
PULSE
6--µA
in
-2.5
-25
7-pF
-2.5
mA
25
3µs
10µs
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
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A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
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Table A-8 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
NumRatingSymbolMinTypMaxUnit
Run supply currents
1
Single Chip, Internal regulator enabled
Wait Supply current
2
Pseudo Stop Current (RTI and COP enabled)
All modules enabled
only RTI enabled
1,2
1
-40°C
27°C
70°C
3
"C" Temp Option 100°C
85°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Pseudo Stop Current (RTI and COP disabled)
1,2
-40°C
27°C
70°C
4
"C" Temp Option 100°C
85°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Stop Current
2
-40°C
27°C
70°C
5
"C" Temp Option 100°C
85°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
NOTES:
1. PLL off
2. All those low power dissipation levels TJ = TA can be assumed.
I
DD5
I
DDW
I
DDPS
I
DDPS
I
DDS
90
130
155
180
250
295
470
520
1000
40
80
105
130
200
245
420
470
800
20
60
85
110
180
225
400
450
600
65
40
5
350
1200
2400
5000
200
1000
2000
5000
100
800
1800
5000
mA
mA
µA
µA
µA
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A.2 Voltage Regulator (VREG_3V3) Operating Characteristics
This section describes the characteristics of the on chip voltage regulator.
Table A-9 VREG_3V3 - Operating Conditions
NumCCharacteristicSymbolMinTypicalMaxUnit
1PInput Voltages
Regulator Current
2P
Reduced Power Mode
Shutdown Mode
Output Voltage Core
3P
Full Performance Mode
Reduced Power Mode
Shutdown Mode
Output Voltage PLL
4P
Full Performance Mode
Reduced Power Mode2
Shutdown Mode
Low Voltage Interrupt
5P
Assert Level
Deassert Level
Low Voltage Reset
5P
Assert Level
Deassert Level
Power-on Reset
7C
Assert Level
Deassert Level
V
VDDR,A
I
REG
V
DD
1
V
DDPLL
(1)
3
V
LVIA
V
LVID
4
V
LVRA
V
LVRD
5
V
PORA
V
PORD
3.15— 5.5V
—
—
2.35
1.7
—
2.35
1.7
—
4.1
4.25
2.25
—
0.97
—
20
12
2.5
2.5
—
2.5
2.5
—
4.37
4.52
—
—
---
---
50
40
2.75
2.75
—
2.75
2.75
—
4.66
4.77
—
2.55
—
2.05
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
NOTES:
1. High Impedance Output
2. Current IDDPLL = 500µA
3. Monitors V
low supply voltage.
, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
DDA
4. Monitors VDD, active only in Full Performance Mode. V
5. Monitors VDD. Active in all modes.
NOTE:The electrical characteristics given in this section are preliminary and
should be used as a guide only. Values in this section cannot be
guaranteed by Motorola and are subject to change without notice.
94
LVRA
and V
must overlap
PORD
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Device User Guide — 9S12KT256DGV1/D V01.09
A.3 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage
reset) handle chip power-up or drops of the supply voltage. Their function is described in
Figure A-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
Figure A-1.
V
PORD
V
LVI
POR
V
V
V
V
LVID
LVIA
LVRD
LVRA
V
DDA
V
DD
t
LVI enabledLVI disabled due to LVR
LVR
A.4 Output Loads
A.4.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no
external DC loads.
Freescale Semiconductor
95
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Device User Guide — 9S12KT256DGV1/D V01.09
A.4.2 Capacitive Loads
The capacitive loads are specified in Table A-10. Ceramic capacitors with X7R dielectricum are required.
This section describes the characteristics of the analog to digital converter.
A.5.1 ATD Operating Characteristics
The Table A-11 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table A-11 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num CRatingSymbolMinTypMaxUnit
Reference Potential
1D
2C
Differential Reference Voltage
1
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA/2
VDDA
VRH-VRL4.755.05.25V
V
V
3D ATD Clock Frequency
ATD 10-Bit Conversion Period
4D
ATD 8-Bit Conversion Period
5D
6D
7P Reference Supply current (two ATD modules)
8P Reference Supply current (one ATD module)
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
3. Reduced accuracy see Table A-14 and Table A-15.
Stop Recovery Time (V
period of 16 ATD clocks.
Conv, Time at 2.0MHz ATD Clock f
Conv, Time at 4.0MHz3 ATD Clock f
Conv, Time at 2.0MHz ATD Clock f
=5.0 Volts)
DDA
Clock Cycles
ATDCLK
ATDCLK
Clock Cycles
ATDCLK
(1)
2
f
ATDCLK
N
CONV10
T
CONV10
T
CONV10
N
CONV8
T
CONV8
t
SR
I
REF
I
REF
0.52.0MHz
14
7
3.5
12
6
28
14
7
26
13
Cycles
µs
µs
Cycles
µs
20µs
0.750mA
0.375mA
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-12 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V
Num CRatingSymbolMinTypMaxUnit
Reference Potential
1D
2C Differential Reference Voltage
3D ATD Clock Frequency
ATD 10-Bit Conversion Period
4D
ATD 8-Bit Conversion Period
5D
6D
7PReference Supply current (two ATD modules)
8PReference Supply current (one ATD module)
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
2. Reduced accuracy see Table A-14 and Table A-15.
Recovery Time (V
period of 16 ATD clocks.
Conv, Time at 2.0MHz ATD Clock f
Conv, Time at 4.0MHz2 ATD Clock f
Conv, Time at 2.0MHz ATD Clock f
=3.3 Volts)
DDA
Clock Cycles
Clock Cycles
Low
High
ATDCLK
ATDCLK
(1)
ATDCLK
1
V
RL
V
RH
VRH-V
f
ATDCLK
N
CONV10
T
CONV10
T
CONV10
N
CONV8
T
CONV8
t
REC
I
REF
I
REF
RL
V
SSA
V
/2
DDA
3.03.33.6V
0.52.0MHz
14
7
3.5
12
6
<= 3.3V+10%
DDA
V
/2
DDA
V
DDA
28
Cycles
14
7
26
Cycles
13
20µs
0.500mA
0.250mA
V
V
µs
µs
µs
A.5.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.5.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
A.5.2.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C
A.5.2.3 Current injection
There are two cases to consider.
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
S
≥ 1024 * (C
f
INS
- C
INN
).
98
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Device User Guide — 9S12KT256DGV1/D V01.09
1.A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less
than VRL unless the current is higher than specified as disruptive conditions.
2.Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
I
INJ
, with I
being the sum of the currents injected into the two pins adjacent to the converted
INJ
= K * RS *
ERR
channel.
Table A-13 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
NumRatingSymbolMinTypMaxUnit
1Max input Source Resistance
Total Input Capacitance
2
Non Sampling
Sampling
3Disruptive Analog Input Current
4Coupling Ratio positive current injection
5Coupling Ratio negative current injection
R
S
C
INN
C
INS
I
NA
K
p
K
n
--1KΩ
10
22
-2.52.5mA
-4
10
-2
10
A.5.3 ATD accuracy
Table A-14 and Table A-15 specify the ATD conversion performance excluding any errors due to
current injection, input capacitance and source resistance.
Table A-14 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
V
= VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV