Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application,Buyershallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
1
MC9S12DT128 Device User Guide — V02.12
Revision History
Version
Number
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
V01.06
V02.00
V02.01
Revision
Date
18 Jun
2001
23 July
2001
23 Sep
2001
12 Oct
2001
27 Feb
2002
4 Mar
2002
8 July
2002
11 Jan
2002
01 Feb
2002
Effective
Date
18 June
2001
23 July
2001
23 Sep
2001
12 Oct
2001
27 Feb
2002
4 Mar
2002
22 July
2002
11 Jan
2002
01 Feb
2002
AuthorDescription of Changes
Initial version (parent doc v2.03 dug for dp256).
Updated version after review
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
Replaced Star12 by HCS12
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
NEW MASKSET
Changed part number from DTB128 to DT128
Functional Changes:
ROMCTL changes in Emulation Mode
80 Pin Byteflight package Option available
Flash with 2 Bit Backdoor Key Enable
Additional CAN0 routing to PJ7,6
Improved BDM with sync and acknowledge capabilities
New Part ID number
Improvements:
Significantly improved NVM reliability data
Corrections:
Interrupt vector Table
Updated Block User Guide versions in preface
Updated Appendix A Electrical Characteristics
2
MC9S12DT128 Device User Guide — V02.12
Version
Number
V02.02
V02.03
V02.04
V02.05
V02.06
Revision
Date
08 Mar
2002
14 Mar
2002
16 Aug
2002
12 Sep
2002
06 Nov
2002
Effective
Date
08 Mar
2002
14 Mar
2002
16 Aug
2002
12 Sep
2002
06 Nov
2002
AuthorDescription of Changes
Changed XCLKS to PE7 in Table 2-2
Updated device part numbers in Figure 2-1
Updated BDM clock in Figure 3-1
Removed SIM descriptionin overview & n
Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH
(Table A-6), C
Updated interrupt pulse timing variables in Table A-6
Updated device part numbers in Figure 2-1
Added document numbers on cover page and Table 0-2
Cleaned up Fig. 1-1, 2-1
Updated Section 1.5 descriptions
Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.
Corrected NVM sizes in Sections 16, 17
Added I
Added Blank Check in A.3.1.5 and Table A-11
Updated CRG spec in Table A-15
Added:
Pull-up columns to signal table,
Example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Device specific info on CRG
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
Changed leakage current for ADC inputs down to +-1uA
Minor modification of PLL frequency/ voltage gain values
Corrected:
Pin names/functions on 80 pin packages
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
Corrected:
Register address mismatches in 1.5.1
Removed document order no. from Revision History pages
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing
CAN0/1/4, BDLC, IIC and/or Byteflight
Added 2L40K mask set in section 1.6
Added OSC User Guide in Preface, “Document References”
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Added new section: “Oscillator (OSC) Block Description”
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
REF
(Table A-9), CIN(Table A-6 & A-15),
INS
spec for 1ATD in Table A-8
UPOSC
spec in Table A-15
3
MC9S12DT128 Device User Guide — V02.12
Version
Number
V02.07
V02.08
V02.09
V02.10
V02.11
Revision
Date
29 Jan
2003
26 Feb
2003
15 Oct
2003
6 Feb
2004
3 May
2004
Effective
Date
29 Jan
2003
26 Feb
2003
15 Oct
2003
6 Feb
2004
3 May
2004
AuthorDescription of Changes
Added 3L40K mask set in section 1.6
Corrected register entries in section 1.5.1 “Detailed Memory Map”
Updated description for ROMCTL in section 2.3.31
Updated section 4.3.3 “Unsecuring the Microcontroller”
Corrected and updated device-specific information for OSC
(section 8.1) & Byteflight (section 15.1)
Updated footnote in Table A-4 “Operating Conditions”
Changed reference of VDDM to VDDR in section A.1.8
Removed footnote on input leakage current in Table A-6 “5V I/O
Characteristics”
Added part numbers MC9S12DT128E, MC9S12DG128E, and
MC9S12DJ128E in “Preface” and related part number references
Removed mask sets 0L40K and 2L40K from Table 1-3
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;
updated Fig.3-1 “ClockConnections” to show the individual HCS12
blocks
Corrected PIM module name and document order number in Table
0-2 “Document References”
Corrected ECT pulse accumulators description in section 1.2
“Features”
Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments
Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in
Table 2.1 “Signal Properties”
Mentioned “S12LRAE” bootloader in Flash section 17
Corrected footnote on clamp of TEST pin under Table A-1
“Absolute Maximum Ratings”
Corrected minimum bus frequency to 0.25MHz in Table A-4
“Operating Conditions”
Replaced “burst programming” by “row programming” in A.3 “NVM,
Flash and EEPROM”
Corrected blank check time for EEPROM in Table A-11 “NVM
Timing Characteristics”
Corrected operating frequency in Table A-18 “SPI Master/Slave
Mode Timing Characteristics
Added A128 information in “Derivative Differences”, 2.1 “Device
Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4
Added lead-free package option (PVE) in Table 0-2 “Derivative
Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber
Example”
Added an “AEC qualified” row in the “Derivative Differences” tables
0-1 & 0-2.
Added part numbers SC515846, SC515847, SC515848, and
SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,
and section 23.
Corrected and added maskset 4L40K in tables 0-1 & 0-2 and
section 1.6.
Corrected BDLC module availability in DB128 80QFP part in
“Derivative Differences” table 0-2.
4
MC9S12DT128 Device User Guide — V02.12
Version
Number
V02.12
Revision
Date
06 Dec
2004
Effective
Date
06 Dec
2004
AuthorDescription of Changes
Added maskset 0L94R
Added items V
“Oscillator characteristics”
Removeditem “Oscillator” from tableA-4 “Operating Conditions”as
it is already covered in table “Oscillator Characteristics”
Table 0-1 and Table 0-2 show the availability of peripheral modules on the various derivatives. For
details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
Table 0-1 Derivative Differences
1
Modules
MC9S12DT128E
MC9S12DT128
SC515849
4
3
MC9S12DG128E
MC9S12DG128
SC515847
3
MC9S12DJ128E
MC9S12DJ128
4
SC515848
3
MC9S12A128
4
# of CANs3220
CAN4✓✓ ✓ ✕
CAN1✓✕ ✕ ✕
CAN0✓✓ ✓ ✕
J1850/BDLC✕✕ ✓ ✕
IIC✓✓ ✓ ✕
Byteflight✕✕ ✕ ✕
Package112 LQFP
112 LQFP/80 QFP2112 LQFP/80 QFP2112 LQFP/80 QFP
2
Package CodePVPV/FUPV/FUPV/FU
Mask set
1L40K3, 3L40K,
0L94R, 4L40K
1L40K3, 3L40K,
4
0L94R, 4L40K
1L40K3, 3L40K,
4
0L94R, 4L40K
4
3L40K, 0L94R
Temp OptionsM, V, CM, V, CM, V, CC
AEC qualifiedYesYesYesNo
Notes
An errata exists
contact Sales Office
Table 0-2 Derivative Differences for MC9S12DB128
Modules
An errata exists
contact Sales Office
MC9S12DB128
SC515846
4
An errata exists
contact Sales Office
MC9S12DB128
SC515846
4
An errata exists
contact Sales Office
1
# of CANs20
CAN4✓✕
CAN1✕✕
CAN0✓✕
J1850/BDLC✕✕
IIC✕✕
Byteflight✓✓
Package112 LQFP
80 QFP
2
Package CodePV/PVEFU
Mask set
3L40K, 0L94R,
4
4L40K
3L40K, 0L94R,
4
4L40K
Temp OptionsM, V, C/M, VM, V, C
AEC qualifiedYesYes
19
MC9S12DT128 Device User Guide — V02.12
Modules
Notes
NOTE:
1.
✓: Available for this device, ✕: Not available for this device.
2. 80 Pin bond-outfor MC9S12DG128E,MC9S12DG128, MC9S12DJ128E,MC9S12DJ128, MC9S12A128, SC515847, and
SC515848 is the same; MC9S12DB128 and SC515846 have a different bond-out.
3. Part numbers MC9S12DT128E, MC9S12DG128E, and MC9S12DJ128E are associated with the mask set 1L40K.
4. Part numbers SC515846, SC515847, SC515848, and SC515849 are associated with the mask set 4L40K.
MC9S12DB128
SC515846
An errata exists
contact Sales Office
4
MC9S12DB128
SC515846
An errata exists
contact Sales Office
4
The following figure provides an ordering number example for the MC9S12D128 devices.
MC9S12 DJ128 C FU
Package Option
Temperature Option
Temperature Options
C = -40˚C to85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Device Title
Package Options
Controller Family
FU =80QFP
PV = 112LQFP
PVE = lead-free 112LQFP
Figure 0-1 Order Partnumber Example
The following items should be considered when using a derivative.
•Registers
–Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0 (see Table 0-1 and Table 0-2).
–Do not write or read CAN1 registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1 (see Table 0-1 and Table 0-2).
–Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a
derivative without CAN4 (see Table 0-1 and Table 0-2).
–Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC (see Table 0-1 and Table 0-2).
–Do not write or read IIC registers (after reset: address range $00E0 - $00E7), if using a
derivative without IIC (see Table 0-1 and Table 0-2).
–Do not write or read Byteflight registers (after reset: address range $0300 - $035F), if using a
derivative without Byteflight registers (see Table 0-1 and Table 0-2).
•Interrupts
–Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for
unused interrupts, if using a derivative without CAN0 (see Table 0-1 and Table 0-2).
–Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for
unused interrupts, if using a derivative without CAN1 (see Table 0-1 and Table 0-2).
20
MC9S12DT128 Device User Guide — V02.12
–Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for
unused interrupts, if using a derivative without CAN4 (see Table 0-1 and Table 0-2).
–Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC (see Table 0-1 and Table 0-2).
–Fill the IIC interrupt vector ($FFC0, $FFC1) according to your coding policies for unused
interrupts, if using a derivative without IIC (see Table 0-1 and Table 0-2).
–Fill the fourByteflightinterrupt vectors ($FFA0 - $FFA7) according toyourcodingpolicies for
unused interrupts, if using a derivative without Byteflight (see Table 0-1 and Table 0-2).
•Ports
–The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0 (see Table 0-1 and
Table 0-2).
–The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if
using a derivative without CAN1 (see Table 0-1 and Table 0-2).
–The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7,
PM6, PM5 and PM4, if using a derivative without CAN4 (see Table 0-1 and Table 0-2).
–The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC (see Table 0-1 and Table 0-2).
–The IIC pin functionality (SCL, SCA) is not available on port PJ7 and PJ6, if using a derivative
RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative
without Byteflight (see Table 0-1 and Table 0-2).
–Do not write MODRR1 and MODRR0 Bit of Module Routing Register(PIM_9DTB128Block
User Guide), if using a derivative without CAN0 (see Table 0-1 and Table 0-2).
–Do not write MODRR3 and MODRR2 Bit of Module Routing Register(PIM_9DTB128Block
User Guide), if using a derivative without CAN4 (see Table 0-1 and Table 0-2).
•Pins not available in 80 pin QFP package for MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, and SC515848
–Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
–Port J[1:0]
PortJpull-up resistors areenabledout ofreseton all fourpins(7:6 and 1:0).Therefore care must
be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at
Base+$026C.
21
MC9S12DT128 Device User Guide — V02.12
–Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefore care must be taken not to clear this bit.
–Port M[7:6]
PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
–Port S[7:4]
PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–PAD[15:8] (ATD1 channels)
Out ofresetthe ATD1 is disabledpreventingcurrent flows in the pins.Donot modify the ATD1
registers!
•Pins not available in 80 pin QFP package for MC9S12DB128 and SC515846
–Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
–Port J[7:6, 1:0]
PortJpull-up resistors areenabledout ofreseton all fourpins(7:6 and 1:0).Therefore care must
be taken not to disable the pull enables on PJ[7:6, 1:0] by clearing the bits PERJ7, PERJ6,
PERJ1 and PERJ0 at Base+$026C.
–Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefore care must be taken not to clear this bit.
–Port M[1:0]
PM1:0 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
–Port S[3:2]
PS3:2 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–PAD[15:8] (ATD1 channels)
Out ofresetthe ATD1 is disabledpreventingcurrent flows in the pins.Donot modify the ATD1
registers!
Document References
22
MC9S12DT128 Device User Guide — V02.12
The Device User Guide provides information about the MC9S12DT128 device made up of standard
HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes all
theindividualBlock User Guidesofthe implemented modules. Ina effort to reduceredundancy all module
specific information is located only in the respective Block User Guide. If applicable, special
implementation details of the module are given in the block description sections of this document.
See Table 0-3 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-3 Document References
User GuideVersionDocument Order Number
HCS12 CPU Reference ManualV02S12CPUV2/D
HCS12 Module Mapping Control (MMC) Block GuideV04S12MMCV4/D
HCS12 Multiplexed External Bus Interface (MEBI) Block GuideV03S12MEBIV3/D
Clock and Reset Generator (CRG) Block User GuideV04S12CRGV4/D
Oscillator (OSC) Block User GuideV02S12OSCV2/D
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User GuideV01S12ECT16B8CV1/D
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User GuideV02S12ATD10B8CV2/D
Inter IC Bus (IIC) Block User GuideV02S12IICV2/D
Asynchronous Serial Interface (SCI) Block User GuideV02S12SCIV2/D
Serial Peripheral Interface (SPI) Block User GuideV02S12SPIV2/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User GuideV01S12PWM8B8CV1/D
128K Byte Flash (FTS128K) Block User GuideV02S12FTS128KV2/D
2K Byte EEPROM (EETS2K) Block User GuideV01S12EETS2KV1/D
Byte Level Data Link Controller -J1850 (BDLC) Block User GuideV01S12BDLCV1/D
Motorola Scalable CAN (MSCAN) Block User GuideV02S12MSCANV2/D
Voltage Regulator (VREG) Block User GuideV01S12VREGV1/D
Port Integration Module (PIM_9DTB128) Block User GuideV02S12DTB128PIMV2/D
Byteflight (BF) Block User GuideV01S12BFV1/D
23
MC9S12DT128 Device User Guide — V02.12
24
MC9S12DT128 Device User Guide — V02.12
Section 1 Introduction
1.1 Overview
The MC9S12DT128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K
bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters(ADC),an 8-channel pulse-width modulator(PWM),a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules
(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128 has full 16-bit data paths
throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory
can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements.
1.2 Features
•HCS12 Core
–16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.20-bit ALU
iv.Instruction queue
•CRG (Clock and Reset Generator)
–Choice of low current Colpitts oscillator or standard Pierce Oscillator
–PLL
–COP watchdog
–real time interrupt
–clock monitor
•8-bit and 4-bit ports with interrupt functionality
25
MC9S12DT128 Device User Guide — V02.12
–Digital filtering
–Programmable rising or falling edge trigger
•Three 1M bit per second, CAN 2.0 A, B software compatible modules
–Five receive and three transmit buffers
–Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit
–Four separate interrupt channels for Rx, Tx, error and wake-up
–Low-pass filter wake-up function
–Loop-back for self test operation
•Enhanced Capture Timer
–16-bit main counter with 7-bit prescaler
–8 programmable input capture or output compare channels
–Four 8-bit or two 16-bit pulse accumulators
•8 PWM channels
–Programmable period and duty cycle
–8-bit 8-channel or 16-bit 4-channel
–Separate control for each pulse width and duty cycle
–Center-aligned or left-aligned outputs
–Programmable clock select logic with a wide range of frequencies
–Fast emergency shutdown input
–Usable as interrupt inputs
•Serial interfaces
–Two asynchronous Serial Communications Interfaces (SCI)
–Two Synchronous Serial Peripheral Interface (SPI)
–Byteflight
•Byte Data Link Controller (BDLC)
26
MC9S12DT128 Device User Guide — V02.12
•SAE J1850 Class B Data Communications Network Interface
–Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in
Automotive Applications
•Inter-IC Bus (IIC)
–Compatible with I2C Bus standard
–Multi-master operation
–Software programmable for one of 256 different serial clock frequencies
•112-Pin LQFP and 80-Pin QFP package options
–I/O lines with 5V input and drive capability
–5V A/D converter inputs
–Operation at 50MHz equivalent to 25MHz Bus Speed
–Development support
–Single-wire background debug™ mode
–On-chip hardware breakpoints
•Special Operating Modes
–Special Single-Chip Mode with active Background Debug Mode
–Special Test Mode (Motorola use only)
–Special Peripheral Mode (Motorola use only)
Low power modes
•Stop Mode
•Pseudo Stop Mode
•Wait Mode
27
MC9S12DT128 Device User Guide — V02.12
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12DT128 device.
28
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Internal Logic 2.5V
V
DD1,2
V
SS1,2
PLL 2.5V
V
DDPLL
V
SSPLL
Figure 1-1 MC9S12DT128 Block Diagram
128K Byte Flash EEPROM
8K Byte RAM
2K Byte EEPROM
Voltage Regulator
Single-wire Background
Debug Module
Clock and
Reset
PLL
Generation
Module
XIRQ
IRQ
R/
W
LSTRB
PTE
PA7
ADDR15
DATA15
DATA7
ECLK
DDRE
MODA
MODB
XCLKS
NOACC/
Multiplexed Address/Data Bus
DDRADDRB
PTAPTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
ADDR9
DATA11
DATA10
DATA9
DATA3
DATA2
DATA1
PA0
ADDR8
DATA8
DATA0
PA6
PA5
ADDR12
ADDR14
ADDR13
DATA12
DATA14
DATA13
DATA4
DATA6
DATA5
I/O Driver 5V
V
DDX
V
SSX
A/D Converter 5V &
Voltage Regulator Reference
V
DDA
V
SSA
Voltage Regulator 5V & I/O
V
DDR
V
SSR
CPU
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
System
Integration
Module
(SIM)
PB4
PB6
PB5
ADDR6
ADDR5
DATA6
DATA5
PB3
ADDR4
ADDR3
DATA4
DATA3
PB7
ADDR7
DATA7
PB2
PB1
ADDR2
ADDR1
DATA2
DATA1
ATD0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Enhanced Capture
Timer
SCI0
SCI1
SPI0
BDLC
(J1850)
CAN0
PB0
CAN1
BYTEFLIGHT
ADDR0
DATA0
CAN0,4
IIC
MISO
MOSI
SCK
SS
SPI1
VRH
VRL
VDDA
VSSA
PPAGE
MISO
MOSI
SCK
SS
RxB
TxB
RxCAN
TxCAN
RxCAN
TxCAN
RX_BF
TX_BF
BF_PSYN
BF_PROK
BF_PERR
BF_PSLM
RxCAN
TxCAN
SDA
SCL
MC9S12DT128 Device User Guide — V02.12
AD0
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
ROMCTL
ATD1
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
VRH
VRL
VDDA
VSSA
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
DDRK
DDRT
DDRS
DDRM
Module to Port Routing
KWJ0
KWJ1
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
DDRJ
DDRP
DDRH
AD1
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS ROMCTL
are not available in the 80 Pin Package Option for DG and DJ128
are not available in the 80 Pin Package Option for B128
Bold-Italics
Italics
Signals shown in Bold are not available in any of the two the 80 Pin Package Options
Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
Size
(Bytes)
16384
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MC9S12DT128 Device User Guide — V02.12
Table 1-1 Device Memory Map
$0000
$0400
$0800
$1000
$2000
$4000
$8000
AddressModule
Fixed Flash EEPROM array
$C000 – $FFFF
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80
Figure 1-2 MC9S12DT128 Memory Map
EXT
– $FFFF
$0000
$03FF
$0800
$0FFF
$2000
$3FFF
$4000
$7FFF
$8000
Size
(Bytes)
16384
1K Register Space
Mappable to any 2K Boundary
2K Bytes EEPROM
Mappable to any 2K Boundary
8K Bytes RAM
Mappable to any 8K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
16K Page Window
eight * 16K Flash EEPROM Pages
$C000
$FF00
$FFFF
NORMAL
SINGLE CHIP
The address does not show the map after reset, but a useful map. After reset the map is:
$0000 – $03FF: Register Space
$0000 – $1FFF: 8K RAM
$0000 – $07FF: 2K EEPROM (not visible)
VECTORSVECTORSVECTORS
EXPANDEDSPECIAL
SINGLE CHIP
$BFFF
$C000
$FFFF
$FF00
$FFFF
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
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MC9S12DT128 Device User Guide — V02.12
1.5.1 Detailed Register Map
$0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset). The read-only value is a uniquepartIDforeachrevisionof the chip. Table 1-3showstheassigned
part ID number.
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
Part ID
1
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module
Mapping Control (MMC) Block Guide for further details.
Table 1-4 Memory size registers
Register nameValue
MEMSIZ0$13
MEMSIZ1$80
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MC9S12DT128 Device User Guide — V02.12
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MC9S12DT128 Device User Guide — V02.12
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12DT128 and its derivatives are available in a 112-pin low profile quad flat pack (LQFP) and
in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal
Descriptions. Figure 2-1, Figure 2-2, and Figure 2-3 show the pin assignments for different packages.
Figure 2-3 Pin Assignments in 80 QFP for MC9S12DB128 and SC515846 Bondout
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in Bold are not available on all the 80-pin
package options. Signals shown in Bold-Italics are not available on the MC9S12DG128E,
MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, and SC515848 80-pin
package options. Signals shown in Italics are not available on MC9S12DB128 and SC515846 80-pin
package options.
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MC9S12DT128 Device User Guide — V02.12
Table 2-1 Signal Properties
Internal Pull
Pin Name
Function 1
EXTAL————VDDPLLNANA
XTAL————VDDPLLNANA
RESET————VDDRNoneNoneExternal Reset
TEST————N.A.NoneNoneTest Input
VREGEN————VDDXNANA
XFC————VDDPLLNANAPLL Loop Filter
BKGD
PAD[15]AN1[7]ETRIG1——VDDANoneNone
PAD[14:8]AN1[6:0]———VDDANoneNone
PAD[7]AN0[7]ETRIG0——VDDANoneNone
PAD[6:0]AN0[6:0]———VDDANoneNone
PA[7:0]
PB[7:0]
PE7NOACC
PE6IPIPE1MODB——VDDR
PE5IPIPE0MODA——VDDR
PE4ECLK———VDDR
PE3
PE2R/
PE1
PE0
PH7KWH7---——VDDR
Pin Name
Function 2
TAGHIMODC——VDDR
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
LSTRBTAGLO——VDDR
W———VDDR
IRQ———VDDR
XIRQ———VDDR
Pin Name
Function 3
———VDDR
———VDDR
XCLKS——VDDR
Pin Name
Function 4
Pin Name
Function 5
Powered
by
Resistor
CTRL
Always
Up
PUCR/
PUPAE
PUCR/
PUPBE
PUCR/
PUPEE
While RESET pin
PUCR/
PUPEE
PERH/
PPSH
Reset
State
Up
Disabled
Disabled
Mode
depen-
dant
low:
Down
Mode
depen-
dant
Up
Disabled Port H I/O, Interrupt
Description
Oscillator Pins
Voltage Regulator
Enable Input
Background Debug,
Tag High, Mode Input
Port AD Input,
Analog Inputs,
External Trigger
Input (ATD1)
Port AD Input,
Analog Inputs
(ATD1)
Port AD Input, Analog
Inputs, External
Trigger Input (ATD0)
Port AD Input, Analog
Inputs (ATD0)
Port A I/O,
Multiplexed
Address/Data
Port B I/O,
Multiplexed
Address/Data
Port E I/O, Access,
Clock Select
1
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Bus Clock
Output
Port E I/O, Byte
Strobe, Tag Low
1
Port E I/O, R/
expanded modes
Port E Input,
Maskable Interrupt
Port E Input, Non
Maskable Interrupt
W in
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MC9S12DT128 Device User Guide — V02.12
Pin Name
Function 1
PH6KWH6---——VDDR
PH5KWH5---——VDDR
PH4KWH4---——VDDR
PH3KWH3
PH2KWH2SCK1——VDDR
PH1KWH1MOSI1——VDDR
PH0KWH0MISO1——VDDR
PJ7KWJ7TXCAN4SCLTXCAN0VDDX
PJ6KWJ6RXCAN4SDARXCAN0VDDX
PJ[1:0]KWJ[1:0]———VDDX
PK7
PK[5:0]
PM7BF_PSLMTXCAN4——VDDX
PM6BF_PERRRXCAN4——VDDX
PM5BF_PROKTXCAN0TXCAN4SCK0VDDX
PM4BF_PSYNRXCAN0RXCAN4MOSI0VDDX
PM3TX_BFTXCAN1TXCAN0
PM2RX_BFRXCAN1RXCAN0MISO0VDDX
Pin Name
Function 2
ECSROMCTL——VDDX
XADDR[19:
14]
Pin Name
Function 3
SS1——VDDR
———VDDX
Pin Name
Function 4
Pin Name
Function 5
SS0VDDX
Powered
by
Internal Pull
Resistor
CTRL
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERJ/
PPSJ
PERJ/
PPSJ
PERJ/
PPSJ
PUCR/
PUPKE
PUCR/
PUPKE
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
Reset
State
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled
Disabled
Disabled
Disabled
Description
Port H I/O,Interrupt,
SS of SPI1
Port H I/O,Interrupt,
SCK of SPI1
Port H I/O,Interrupt,
MOSI of SPI1
Port H I/O,Interrupt,
MISO of SPI1
Port J I/O, Interrupt,
Up
TX of CAN4, SCL of
IIC
Port J I/O, Interrupt,
Up
RX of CAN4, SDA of
IIC
UpPort J I/O, Interrupts
Port K I/O,
Up
Up
Emulation Chip
Select, ROM Control
Port K I/O, Extended
Addresses
Port M I/O, BF slot
Disabled
mismatch pulse, TX
of CAN4
Port MI/O, BF illegal
Disabled
pulse/message
format error pulse,
RX of CAN4
Port M I/O, BF
Disabled
Disabled
Disabled
Disabled
reception ok pulse,
TX of CAN0, CAN4,
SCK of SPI0
Port M I/O, BF sync
pulse (Rx/Tx) OK
pulse o/p, RX of
CAN0, CAN4, MOSI
of SPI0
Port M I/O, TX of BF,
CAN1, CAN0, SS of
SPI0
Port M I/O, RX of BF,
CAN1, CAN0, MISO
of SPI0
62
MC9S12DT128 Device User Guide — V02.12
Internal Pull
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Pin Name
Function 5
Powered
by
PM1TXCAN0TXB——VDDX
PM0RXCAN0RXB——VDDX
PP7KWP7PWM7——VDDX
PP6KWP6PWM6——VDDX
PP5KWP5PWM5——VDDX
PP4KWP4PWM4——VDDX
PP3KWP3PWM3
PP2KWP2PWM2SCK1—VDDX
PP1KWP1PWM1MOSI1—VDDX
PP0KWP0PWM0MISO1—VDDX
SS1—VDDX
PS7SS0———VDDX
PS6SCK0———VDDX
PS5MOSI0———VDDX
PS4MISO0———VDDX
PS3TXD1———VDDX
PS2RXD1———VDDX
PS1TXD0———VDDX
PS0RXD0———VDDX
PT[7:0]IOC[7:0]———VDDX
NOTES:
1. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide.
Resistor
CTRL
PERM/
PPSM
PERM/
PPSM
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERT/
PPST
Reset
State
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Up
Up
Up
Up
Up
Up
Up
Up
Disabled
Description
Port M I/O, TX of
CAN0, RX of BDLC
Port M I/O, RX of
CAN0, RX of BDLC
Port P I/O, Interrupt,
Channel 7 of PWM
Port P I/O, Interrupt,
Channel 6 of PWM
Port P I/O, Interrupt,
Channel 5 of PWM
Port P I/O, Interrupt,
Channel 4 of PWM
Port P I/O, Interrupt,
Channel 3 of PWM,
SS of SPI1
Port P I/O, Interrupt,
Channel 2 of PWM,
SCK of SPI1
Port P I/O, Interrupt,
Channel 1 of PWM,
MOSI of SPI1
Port P I/O, Interrupt,
Channel 0 of PWM,
MISO2 of SPI1
Port S I/O,
SPI0
Port S I/O, SCK of
SPI0
Port S I/O, MOSI of
SPI0
Port S I/O, MISO of
SPI0
Port S I/O, TXD of
SCI1
Port S I/O, RXD of
SCI1
Port S I/O, TXD of
SCI0
Port S I/O, RXD of
SCI0
Port T I/O, Timer
channels
SS of
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MC9S12DT128 Device User Guide — V02.12
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL andXTALare the crystal driver and externalclockpins.On reset all the deviceclocksarederived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
MCU
R
C
S
C
P
VDDPLLVDDPLL
Figure 2-4 PLL Loop Filter Connections
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of
64
RESET. This pin has a permanently enabled pull-up device.
MC9S12DT128 Device User Guide — V02.12
2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15]
PAD15 is a general purpose input pin and analog input of the analog to digital converter ATD1. It can act
as an external trigger input for the ATD1.
2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]
PAD14 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD1.
2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7]
PAD7 is a general purpose input pin and analog input of the analog to digital converter ATD0. It can act
as an external trigger input for the ATD0.
2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]
PAD6 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD0.
2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
The
(low power) oscillator isusedorwhether Pierce oscillator/external clock circuitry is used. The state of this
pin is latched at the rising edge of
external clockdrive.If input is a logichighan oscillator circuit is configured onEXTALand XTAL. Since
this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is
an oscillator circuit on EXTAL and XTAL.
RESET. If the input is a logic low the EXTAL pin is configured for an
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MC9S12DT128 Device User Guide — V02.12
EXTAL
MCU
XTAL
* Due to the nature of a translated ground Colpitts oscillator a
DC voltage bias is applied to the crystal
Please contact the crystal manufacturer for crystal DC
* Rs can be zero (shorted) when used with higher frequency crystals.
Refer to manufacturer’s data.
Figure 2-6 Pierce Oscillator Connections (PE7=0)
MCU
EXTAL
XTAL
not connected
CMOS-COMPATIBLE
EXTERNAL OSCILLATO
(VDDPLL-Level)
R
66
Figure 2-7 External Clock Connections (PE7=0)
MC9S12DT128 Device User Guide — V02.12
2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of
instruction queue tracking signalIPIPE1.Thispinis an input with a pull-down device which is only active
RESET is low.
when
RESET. This pin is shared with the
2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of
instruction queue tracking signalIPIPE0.Thispinis an input with a pull-down device which is only active
RESET is low.
when
RESET. This pin is shared with the
2.3.15 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.17 PE2 / R/W—Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.18 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.19 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PH7 / KWH7 — Port H I/O Pin 7
PH7isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode.
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MC9S12DT128 Device User Guide — V02.12
2.3.21 PH6 / KWH6 — Port H I/O Pin 6
PH6isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode.
2.3.22 PH5 / KWH5 — Port H I/O Pin 5
PH5isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode.
2.3.23 PH4 / KWH4 — Port H I/O Pin 2
PH4isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode.
2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode. It can be configured as slave select pin
1 (SPI1).
SS of the Serial Peripheral Interface
2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
toexitSTOP or WAITmode.It can beconfigured as serial clockpin SCK of the SerialPeripheralInterface
1 (SPI1).
2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
PJ7 is a generalpurposeinputoroutput pin. It can be configured to generate an interrupt causingtheMCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial clock pin SCL of the IIC module.
PJ6 is a generalpurposeinputoroutput pin. It can be configured to generate an interrupt causingtheMCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial data pin SDA of the IIC module.
2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (
enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of
stateofthis pin islatchedto the ROMONbit.For a completelist of modesreferto 4.2 ChipConfigurationSummary.
ECS). While configurating MCU expanded modes, this pin is used to
RESET, the
2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the slot mismatch output pulse pin
of Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area
Network controllers 4 (CAN4).
2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the illegal pulse or message format
error output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of the Motorola
Scalable Controller Area Network controllers 4 (CAN4).
2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the reception OK output pulse pin of
Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area
Network controllers 0or4(CAN0 or CAN4). It can be configured as the serialclockpinSCK of the Serial
Peripheral Interface 0 (SPI0).
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MC9S12DT128 Device User Guide — V02.12
2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the correct synchronisation pulse
reception/transmission output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of
the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured
as the master output (during master mode) or slave input pin (during slave mode) MOSI
Peripheral Interface 0 (SPI0).
for the Serial
2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a generalpurposeinputoroutput pin. It can be configured as the transmit pinTX_BF of Byteflight.
It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network
controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin
Interface 0 (SPI0).
SS of the Serial Peripheral
2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RX_BF of Byteflight.
It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network
controllers 1or0 (CAN1 or CAN0). It canbeconfigured as the master input(duringmaster mode) or slave
output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin
TXB of the BDLC.
2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin
RXB of the BDLC.
2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7
PP7 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.
2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6
PP6 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.
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2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5
PP5 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.
2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4
PP4 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output.
2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin
SS of the Serial Peripheral Interface 1 (SPI1).
2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
2.3.49 PS7 / SS0 — Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.50 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
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2.3.51 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
2.3.54 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.55 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.56 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12DT128 power and ground pins are described below.
Table 2-2 MC9S12DT128 Power and Ground Connection Summary
Mnemonic
Pin Number
112-pin QFP
VDD1, 213, 652.5V
VSS1, 214, 660V
Nominal
Voltage
Description
Internal power and ground generated by internal regulator
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Mnemonic
VDDR415.0V
VSSR400V
VDDX1075.0V
VSSX1060V
VDDA835.0VOperating voltage and ground for the analog-to-digital
VSSA860V
VRL850V
VRH845.0V
VDDPLL432.5VProvides operating voltage and ground for the Phased-Locked
VSSPLL450V
VREGEN975VInternal Voltage Regulator enable/disable
NOTE:
Pin Number
112-pin QFP
All VSS pins must be connected together in the application.
Nominal
Voltage
Description
External power and ground, supply to pin drivers and internal
voltage regulator.
External power and ground, supply to pin drivers.
converters and the reference for the internal voltageregulator,
allows the supply voltage to the A/D to be bypassed
independently.
Reference voltages for the analog-to-digital converter.
Loop. This allows the supply voltage to the PLL to be
bypassed independently. Internal power and ground
generated by internal regulator.
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demandsonthepower supply, use bypass capacitors withhigh-frequencycharacteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
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2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.
NOTE:
No load allowed except for bypass capacitors.
2.4.7 VREGEN — On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.
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Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
HCS12 CORE
BDM
CPU
MEBI
INT
Flash
RAM
MMC
BKP
core clock
EXTAL
XTAL
CRG
bus clock
oscillator clock
Figure 3-1 Clock Connections
EEPROM
ECT
ATD0, 1
PWM
SCI0, SCI1
SPI0, 1
CAN0, 1, 4
IIC
BDLC
PIM
BF
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12DT128. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operatingmode out of resetisdetermined by the statesof the MODC, MODB,andMODA pins during
reset (Table4-1).TheMODC,MODB, and MODA bits intheMODE register show the currentoperating
modeandprovide limited modeswitchingduring operation. Thestates of theMODC,MODB, and MODA
pinsarelatched into thesebitson the risingedge of theresetsignal. The ROMCTLsignalallows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the
memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
Table 4-1 Mode Selection
BKGD =
MODC
000X1
001
010X0Special Test (Expanded Wide), BDM allowed
011
100X1Normal Single Chip, BDM allowed
101
110X1
111
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
01
10
01
10
00
11
00
11
ROMON
Bit
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Expanded Narrow, BDM allowed
Special Peripheral; BDM allowed but bus operations
would cause bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide.
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•Protection of the contents of FLASH,
•Protection of the contents of EEPROM,
•Operation in single-chip mode, No BDM possible
•Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of theinternal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door inthe user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will bethemostcommon usage of the secured part. Everything will appear thesameasif the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
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4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode or via a .sequence of BDM commands. Unsecuring
is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes,theuser can eraseandprogram the FLASHsecurity bits totheunsecured state. Thisisgenerally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks andthe oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions.Theinternal CPU signals(addressand databus) willbe fully static.Allperipherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin
configuration of port A, B, E and K out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
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NOTE:
For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to
Table 2-1
for affected pins.
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
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Section 6 HCS12 Core Block Description
6.1 CPU Block Description
Consult the CPU Reference Manual for information on the CPU.
6.1.1 Device-specific information
When the CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is
equivalent to 1 Bus Clock period.
6.2 HCS12 Module Mapping Control (MMC) Block Description
Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.
6.2.1 Device-specific information
•INITEE
–Reset state: $01
–Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special
modes".
•PPAGE
–Reset state: $00
–Register is "Write anytime in all modes".
•MEMSIZ0
–Reset state: $13
•MEMSIZ1
–Reset state: $80
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module.
6.3.1 Device-specific information
•PUCR
–Reset state: $90
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6.4 HCS12 Interrupt (INT) Block Description
Consult the INT Block Guide for information on the HCS12 Interrupt module.
Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer
module.When the ECT_16B8C Block User Guide refers to freeze mode this is equivalent to active BDMmode.
Section 10 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT128.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module. When the ATD_10B8C Block User Guide refers to freeze mode this is equivalent to active BDMmode.
Section 11 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 12 Serial Communications Interface (SCI) Block
Description
There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DT128
device. Consult the SCI Block User Guide for information about each Serial Communications Interface
module.
Section 13 Serial Peripheral Interface (SPI) Block
Description
There are two Serial Peripheral Interfaces (SPI1 and SPI0) implemented on MC9S12DT128. Consult the
SPI Block User Guide for information about each Serial Peripheral Interface module.
Section 14 J1850 (BDLC) Block Description
Consult the BDLC Block User Guide for information about the J1850 module.
Section 15 Byteflight (BF) Block Description
Consult the BF Block User Guide for information about the 10 Mbps Byteflight module.
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15.1 Device-specific information
The read-only Module Version Register (BFMVR) contains the current version number of $80.
Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module.
When the PWM_8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.
Section 17 Flash EEPROM 128K Block Description
Consult the FTS128K Block User Guide for information about the flash module.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into
the flash memory of this device during manufacture. This LRAE program will provide greater
programming flexibility to the end users by allowing the device to be programmed directly using CAN or
SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if
not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and
its implementation, please see the S12 LREA Application Note (AN2546/D).
It isplanned that most HC9S12devicesmanufactured after Q1 of2004 will be shippedwiththe S12 LRAE
programmed in the Flash . Exact details of the changeover (ieblank to programmed) for each product will
be communicated in advance via GPCN and will be traceable by the customer via datecode marking on
the device.
Please contact Motorola SPS Sales if you have any additional questions.
Section 18 EEPROM 2K Block Description
Consult the EETS2K Block User Guide for information about the EEPROM module.
Section 19 RAM Block Description
This module supports single-cycle misaligned word accesses without wait states.
Section 20 MSCAN Block Description
There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12DT128.
Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.
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Section 21 Port Integration Module (PIM) Block Description
Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module.
Section 22 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 – C6).
•Central point of the ground star should be the VSSR pin.
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•Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
•VSSPLL must be directly connected to VSSR.
•Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
•Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
•Central power input should be fed in at the VDDA/VSSA pins.
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Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator
C1
VDD1
VSS1
VDDX
C6
VSSX
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
VSSR
VDDR
C4
C9
R1
C5
C10
C8
C11
VSSPLL
VDDPLL
C7
Q1
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Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, and SC515848) Colpitts
Oscillator
VDDX
C6
VSSX
VREGEN
VSSA
C3
VDDA
C1
VDD1
VSS1
VSSR
VDDR
C4
C9
R1
C5
C10
C8
C11
VSSPLL
VDDPLL
VSS2
C2
VDD2
C7
Q1
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Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator
C1
VDD1
VSS1
VDDX
C6
VSSX
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
VSSR
VDDR
VDDPLL
C4
C9
R1
C5
C10
C8
Q1
R2
R3
VSSPLL
C7
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Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, and SC515848) Pierce
Oscillator
VDDX
C6
VSSX
VDD1
C1
VSS1
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
VSSR
VDDR
C4
C9
R1
C5
C10
R2
Q1
C8
VSSPLL
VDDPLL
VSSPLL
R3
C7
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Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128 and SC515846)Pierce
Oscillator
VDDX
C6
VSSX
VDD1
C1
VSS1
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
VSSR
VDDR
C4
C9
R1
C5
C10
R2
Q1
C8
VSSPLL
VDDPLL
VSSPLL
R3
C7
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Appendix A Electrical Characteristics
A.1 General
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T:
Those parameters are achieved by design characterization on a small sample size from typical
devices. All values shown in the typical column are within this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12DT128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL
and internal logic.
The VDDA, VSSA pairsuppliestheA/D converter and the resistor ladder of the internal voltage regulator.
The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
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NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGDpin and the RESETinputs.Theinternal structure of allthosepins is identical, howeversome
of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This class is made up by the two VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
A.1.4 Current Injection
Power supply must maintain regulation within operating V
operating maximum current conditions. If positive injection current (V
injection current may flowoutofVDD5and could result in external power supply going out of regulation.
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
or VDD range during instantaneous and
DD5
in
>V
) is greater than I
DD5
DD5
, the
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MC9S12DT128 Device User Guide — V02.12
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
SS5
or V
DD5
).
Table A-1 Absolute Maximum Ratings
1
NumRatingSymbolMinMaxUnit
1I/O, Regulator and Analog Supply Voltage
2
Digital Logic Supply Voltage
3
PLL Supply Voltage
4Voltage difference VDDX to VDDR and VDDA
5Voltage difference VSSX to VSSR and VSSA
6Digital I/O Input Voltage
7Analog Reference
8XFC, EXTAL, XTAL inputs
9TEST input
Instantaneous Maximum Current
10
Single pin limit for all digital I/O pins
Instantaneous Maximum Current
11
Single pin limit for XFC, EXTAL, XTAL
Instantaneous Maximum Current
12
Single pin limit for TEST
13Storage Temperature Range
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generatethe logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V
4. Those pins are internally clamped to V
5. This pin is clamped low to V
2
2
3
4
5
and V
SSX
and V
SSPLL
, but not clamped high. This pin must be tied low in applications.
SSX
DDX
DDPLL
V
DD5
V
DD
V
DDPLL
∆
VDDX
∆
VSSX
V
IN
V
RH,VRL
V
ILV
V
TEST
I
D
I
DL
I
DT
T
stg
, V
and V
SSR
.
-0.36.0V
-0.33.0V
-0.33.0V
-0.30.3V
-0.30.3V
-0.36.0V
-0.36.0V
-0.33.0V
-0.310.0V
-25+25mA
-25+25mA
-0.250mA
– 65155°C
DDR
or V
SSA
and V
DDA
.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
99
MC9S12DT128 Device User Guide — V02.12
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
ModelDescriptionSymbolValueUnit
Series ResistanceR11500Ohm
Storage CapacitanceC100pF
Human Body
Machine
Number of Pulse per pin
positive
negative
Series ResistanceR10Ohm
Storage CapacitanceC200pF
Number of Pulse per pin
positive
negative
–
–
–
3
3
–
3
3
Latch-up
Minimum input voltage limit–2.5V
Maximum input voltage limit7.5V
Table A-3 ESD and Latch-Up Protection Characteristics
Num CRatingSymbolMinMaxUnit
1C Human Body Model (HBM)
2C Machine Model (MM)
3C Charge Device Model (CDM)
Latch-up Current at 125°C
4C
5C
positive
negative
Latch-up Current at 27°C
positive
negative
V
V
V
HBM
MM
CDM
I
LAT
I
LAT
2000–V
200–V
500–V
+100
–100
+200
–200
A.1.7 Operating Conditions
–mA
–mA
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE:
100
Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature T
and the junction temperature TJ. For power dissipation
A
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