Freescale MC9S12DP512 DATA SHEET
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
查询MC9S12A512供应商
MC9S12DP512
Device Guide
V01.23
Covers also
DOCUMENT NUMBER
9S12DP512DGV1/D
MC9S12DT512, MC9S12DJ512,
MC9S12A512
Original Release Date: 27 Nov 2001
Revised: 09 Feb 2005
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application,Buyershallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
1
Revision History
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
DOCUMENT NUMBER
9S12DP512DGV1/D
Version
Number
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
Revision
Date
27 Nov
2001
13 Mar
2002
02 Apr
2002
15 Apr
2002
06 Jun
2002
05 Jul
2002
Effective
Date
11 Feb
2002
13 Mar
2002
02 Apr
2002
15 Apr
2002
06 Jun
2002
05 Jul
2002
Author Description of Changes
- Initial version based on DP256 V2.09.
- Updated document formats.
- Removed reference to SIM in overview.
- Changed XCLKS to PE7 in signal description.
- Removed"Oscillator start-up time fromPOR or STOP"from Oscillator
Characterisitcs.
- Changed VDD and VDDPLL to 2.35V.
- Updated C
- Updated I
- Updated input capacitance.
- Updated NVM timing characteristics.
- Updated document reference (SPI, SCI).
- Corrected values in device memory map (RAM start, flash protected
sector sizes).
- Updated document reference (SCI).
- Changed all operating frequency references to 50MHz EXTAL and
removed references to 80 pin LQFP.
- Preface Table "Document References": Changed to full naming for
each block.
- Table "Interrupt Vector Locations", Column "Local Enable": Corrected
several register and bit names.
- Table "Signal Properties": Added column "Internal Pull Resistor".
- Table "PLL Characteristics": Updated parameters K1 and f1
- Figure "Basic Pll functional diagram": Inserted XFC pin in diagram
- Enhanced section "XFC Component Selection"
- Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode.
.
INS
OL/IOH
values.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application,Buyer shallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
2
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Version
Number
V01.06
V01.07
Revision
Date
24 Jul
2002
29 Jul
2002
Effective
Date
24 Jul
2002
05 Aug
2002
Author Description of Changes
- Updated SPI electrical characteristics.
- Updated Derivative Differences table.
- Added ordering number example.
- Added Detailed Register Map.
- Changed Internal Pull Resistor column of signal table.
- Added pull device description for MODC pin.
- Corrected XCLKS figure titles. Moved table to section Modes of
Operation.
- Removed ’1/2’ from BDM in Figure Clock Connections.
- Completely reworked section Modes of Operation. Added Chip
Configuration Summary and Low Power Mode description.
- Changed classification to C for internal pull currents inTable 5V I/O
Characteristics.
- Changed input leakage to 1uA for all pins.
- Updated VREG section and layout recommendation.
- Moved Power and Gound Connection Summary table to start of
Power Supply Pins section.
- Added ROMONE to pinout
- Corrected mem map: ’MEBI map x of 3’
- Corrected mem map: KEYEN bits in FSEC.
- Added section Printed Circuit Board Layout Proposal.
- Corrected addresses in Reserved, CAN and EEP buffer map.
- Updated NVM electricals.
V01.08
V01.09
V01.10
V01.11
V01.12
V01.13
V01.14
V01.15
21 Aug
2002
24 Sep
2002
18 Oct
2002
29 Oct
2002
03 Dec
2002
08 Jan
2003
23 Jan
2003
28 Feb
2003
21 Aug
2002
24 Sep
2002
18 Oct
2002
29 Oct
2002
03 Dec
2002
08 Jan
2003
23 Jan
2003
28 Feb
2003
- Updated table ’Document References’
- Added section ’Oscillator (OSC) Block Description’
- Section HCS12 Core Block Desciption: mentioned alternalte clock of
BDM to be equivalent to oscillator clock
- Corrected tables 0-1 and 0-2
- Added derivatives to cover sheet.
- Added part ID for 1L00M maskset.
- Corrected in footnote of Table "PLL Characteristics": f
- Renamed Preface section to Derivative Differences and Document
references.
- Added A512 derivative.
- Updated module set of DJ512 in Table 0-1.
- Added details for derivatives without CAN and/or BDLC modules.
- Corrected several entries in ’Detailed Memory Map’.
- Removed footnote on input leakage current from table ’5V I/O
Characteristics’.
- Updated section ’Unsecuring the Microcontroller’.
- Updated footnote 1 in table ’Operating Conditions’.
- Renamed ROMONE pin to ROMCTL.
- Corrected PE[1,0] pull specification in Signal Properties Summary
Table.
OSC
= 4MHz.
3
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Version
Number
V01.16
V01.17
V01.18
V01.19
V01.20
V01.21
V01.22
V01.23
Revision
Date
31 Mar
2003
30 May
2003
23 Jul
2003
24 Jul
2003
01 Sep
2003
08 Mar
2004
23 Aug
2004
09 Feb
2005
Effective
Date
31 Mar
2003
30 May
2003
23 Jul
2003
24 Jul
2003
01 Sep
2003
08 Mar
2004
23 Aug
2004
09 Feb
2005
Author Description of Changes
- Corrections in App. A ’NVM, Flash and EEPROM’:
- Number of words per flash row = 64
- Replaced ’burst programming’ with ’row programming’
- Sector erase size = 1024 bytes
- Corrected feature description ECT
- Corrected min. bus freq. in table ’Operating Conditions’
- Replacedreferences to HCS12Core Guide with theindividual HCS12
Block guides throughout document
- Table ’Absolute Maximum Ratings’ corrected footnote on clamp of
TEST pin
- Mentioned ’S12 LRAE’ bootloader in Flash section
- Document References: corrected S12 CPU document reference
- Added part ID for 2L00M maskset.
- Added part ID for 3L00M maskset.
- Added cycle definition to ’CPU 12 Block Description’.
- Diagram ’Clock Connections’: Connected Bus Clock to HCS12 Core.
- Corrected ’Background Debug Module’ to ’HCS12 Breakpoint’ at
address $0028 - $002F in table 1-1.
- Corrected ’Blank Check Time Flash’ value in table ’NVM Timing
Characteristics’
- Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to
’Oscillator Characteristics’. Updated oscillator description and table
note.
- Added part ID for 4L00M maskset.
- Corrected pin name KWP5 in device pinout.
- Updated V
- Removed item ’Oscillator’ from table ’Operating Conditions’ as
already covered in table ’Oscillator Characteristics’
- Corrected Flash Row Programming Time in NVM Timing
Characteristics
IH,EXTAL
and V
in table ’Oscillator Characteristics’
IL,EXTAL
4
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Table of Contents
Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
1.7 Memory Size Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.4 VREGEN — Voltage Regulator Enable Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.5 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .56
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .56
2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .56
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .56
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.19 PE1 / IRQ — Port E Input Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . . . .60
2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . . . .60
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.32 PK7 / ECS / ROMCTL — Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.34 PM7 / TXCAN3 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.35 PM6 / RXCAN3 / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.36 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5. . . . . . . . . . . . . . .61
2.3.37 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . . .61
2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . . . . . . . . .61
2.3.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.41 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.50 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.51 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.53 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.54 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.55 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
2.3.56 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.57 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . .65
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & Internal Voltage Regulator65
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins. . . . . . . . . . . . . . .65
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .65
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.4.7 VREGEN — On Chip Voltage Regulator Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Section 3 System Clock Description
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 4 Modes of Operation
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 6 HCS12 Core Block Description
7
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
6.1 CPU12 Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.2 HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . . . .77
6.2.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .77
6.3.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.5 HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.5.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 7 Clock and Reset Generator (CRG) Block Description
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 8 Oscillator (OSC) Block Description
8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 9 Enhanced Capture Timer (ECT) Block Description
Section 10 Analog to Digital Converter (ATD) Block Description
Section 11 Inter-IC Bus (IIC) Block Description
Section 12 Serial Communications Interface (SCI) Block Description
Section 13 Serial Peripheral Interface (SPI) Block Description
Section 14 J1850 (BDLC) Block Description
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Flash EEPROM 512K Block Description
Section 17 EEPROM 4K Block Description
Section 18 RAM Block Description
Section 19 MSCAN Block Description
8
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Section 20 Port Integration Module (PIM) Block Description
Section 21 Voltage Regulator (VREG) Block Description
Section 22 Printed Circuit Board Layout Proposal
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Appendix B Package Information
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
List of Figures
Figure 0-1 Order Part Number Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 1-1 MC9S12DP512 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 1-2 MC9S12DP512 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 2-1 Pin Assignments in 112-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 2-2 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 2-3 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 2-4 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 2-5 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .82
Figure 22-2 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .83
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure A-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-3 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-4 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-5 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-6 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-7 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-8 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 122
11
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
12
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
List of Tables
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 0-2 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .27
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control). . . . . . . . . . . . . . . . . .27
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$0017 - $0019 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$001A - $001B Device ID Register (Table 1-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4) . . . . . . . . .28
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface). . . . . . . . . .28
$001F - $001F INT map 2 of 2 (HCS12 Interrupt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$0020 - $0027 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$0028 - $002F BKP (HCS12 Breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control). . . . . . . . . . . . . . . . . .29
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .29
$0034 - $003F CRG (Clock and Reset Generator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) . . . . . . . . . . . . . . . . . .30
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .33
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel). . . . . . . . . . . . . . . . . . . . . .34
$00C8 - $00CF SCI0 (Asynchronous Serial Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
$00D8 - $00DF SPI0 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
$00E0 - $00E7 IIC (Inter IC Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
$00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850) . . . . . . . . . . . . . . . . . . . . . . .37
$00F0 - $00F7 SPI1 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
$00F8 - $00FF SPI2 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
$0100 - $010F Flash Control Register (fts512k4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
$0110 - $011B EEPROM Control Register (eets4k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
$011C - $011F Reserved for RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .40
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .42
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .43
13
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
$01C0 - $01FF CAN2 (Motorola Scalable CAN - MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .44
$0200 - $023F CAN3 (Motorola Scalable CAN - MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .45
$0240 - $027F PIM (Port Integration Module PIM_9DP256). . . . . . . . . . . . . . . . . . . . . . . .46
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .48
$02C0 - $03FF Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 2-2 MC9S12DP512 Power and Ground Connection Summary. . . . . . . . . . . . . . . . . .64
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table A-3 ESD and Latch-up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table A-13 Voltage Regulator Recommended Load Capacitances. . . . . . . . . . . . . . . . . . . .103
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table A-15 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table A-18 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table A-19 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table A-20 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table A-21 Expanded Bus Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Derivative Differences and Document References
Derivative Differences
Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the
compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
1
An errata exists
Office
Table 0-1 Derivative Differences
Modules MC9S12DP512 MC9S12DT512 MC9S12DJ512 MC9S12A512
# of CANs 5 3 2 0
CAN0 ✓✓ ✓ —
CAN1 ✓✓ ——
CAN2 ✓ ———
CAN3 ✓ ———
CAN4 ✓✓ ✓ —
J1850/BDLC ✓ — ✓ —
Package 112 LQFP 112 LQFP 112 LQFP 112 LQFP
Package
Code
Mask set L00M L00M L00M L00M
Temp Options M, V, C M, V, C M, V, C C
Notes
NOTES:
1.
✓: Available for this device, —: Not available for this device
PV PV PV PV
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
An errata exists
contact Sales
The following figure provides an ordering number example for the MC9S12D-Family devices.
contact Sales
Office
MC9S12 DP512 C PV
Figure 0-1 Order Part Number Example
Package Option
Temperature Option
Device Title
Controller Family
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU = 80 QFP
PV = 112 LQFP
15
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
The following items should be considered when using a derivative (Table 0-1):
• Registers
– Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0.
– Do not write or read CAN1registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1.
– Do not write or read CAN2 registers (after reset: address range $01C0 - $01FF), if using a
derivative without CAN2.
– Do not write or read CAN3 registers (after reset: address range $0200 - $023F), if using a
derivative without CAN3.
– Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a
derivative without CAN4.
– Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC.
• Interrupts
– Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for
unused interrupts, if using a derivative without CAN0.
– Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for
unused interrupts, if using a derivative without CAN1.
– Fill the four CAN2 interrupt vectors ($FFA0 - $FFA7) according to your coding policies for
unused interrupts, if using a derivative without CAN2.
– Fill the four CAN3 interrupt vectors ($FF98 - $FF9F) according to your coding policies for
unused interrupts, if using a derivative without CAN3.
– Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for
unused interrupts, if using a derivative without CAN4.
– Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC.
• Ports
– The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0.
– The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if
using a derivative without CAN1.
– The CAN2 pin functionality (TXCAN2, RXCAN2) is not available on port PM5 and PM4, if
using a derivative without CAN2.
– The CAN3 pin functionality (TXCAN3, RXCAN3) is not available on port PM7 and PM6, if
using a derivative without CAN3.
16
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
– The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7,
PM6, PM5 and PM4, if using a derivative without CAN0.
– The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC.
– Do not write MODRR1 and MODRR0 bits of Module Routing Register (PIM_9DP256 Block
Guide), if using a derivative without CAN0.
– Do not write MODRR3 and MODRR2 bits of Module Routing Register (PIM_9DP256 Block
Guide), if using a derivative without CAN4.
Document References
The Device Guide provides information about the MC9S12DP512 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
individual Block Guides of the implemented modules. In an effort to reduce redundancy, all module
specific information is located only in the respective Block Guide. If applicable, special implementation
details of the module are given in the block description sections of this document.
See Table 0-2 for names and versions of the referenced documents throughout the Device Guide.
Table 0-2 Document References
Block Guide Version Document Order Number
HCS12 CPU Reference Manual V02 S12CPUV2/D
HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D
HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D
HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D
HCS12 Breakpoint (BKP) Block Guide V01 S12BKPV1/D
Clock and Reset Generator (CRG) Block Guide V04 S12CRGV4/D
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block Guide V01 S12ECT16B8V1/D
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block Guide V02 S12ATD10B8CV2/D
Inter IC Bus (IIC) Block Guide V02 S12IICV2/D
Asynchronous Serial Interface (SCI) Block Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block Guide V03 S12SPIV3/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide V01 S12PWM8B8CV1/D
512K Byte Flash (FTS512K4) Block Guide V01 S12FTS512K4V1/D
4K Byte EEPROM (EETS4K) Block Guide V02 S12EETS4KV2/D
Byte Level Data Link Controller -J1850 (BDLC) Block Guide V01 S12BDLCV1/D
Motorola Scalable CAN (MSCAN) Block Guide V02 S12MSCANV2/D
Voltage Regulator (VREG) Block Guide V01 S12VREGV1/D
Port Integration Module (PIM_9DP256) Block Guide
Oscillator (OSC) Block Guide V02 S12OSCV2/D
1
V03 S12DP256PIMV3/D
17
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
NOTES:
1. Reused due to functional equivalence.
18
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Section 1 Introduction
1.1 Overview
The MC9S12DP512 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 512K bytes of Flash EEPROM, 14K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters(ADC),an 8-channel pulse-width modulator(PWM),a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wake up capability, five CAN 2.0 A, B software compatible modules
(MSCAN12), and an Inter-IC Bus. The MC9S12DP512 has full 16-bit data paths throughout. However,
the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for
lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements.
1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv.Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
• CRG (Clock and Reset Generation)
– Low current Colpitts oscillator or
– Pierce oscillator
– PLL
– COP watchdog
– Real Time Interrupt
– Clock Monitor
• 8-bit and 4-bit ports with interrupt functionality
19
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
– Digital filtering
– Programmable rising or falling edge trigger
• Memory
– 512K Flash EEPROM
– 4K byte EEPROM
– 14K byte RAM
• Two 8-channel Analog-to-Digital Converters
– 10-bit resolution
– External conversion trigger capability
• Five 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Enhanced Capture Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
• Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Three Synchronous Serial Peripheral Interface (SPI)
• Byte Data Link Controller (BDLC)
– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible
for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications
20
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
• Inter-IC Bus (IIC)
– Compatible with I
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP package
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
2
C Bus standard
– Operation at 50MHz equivalent to 25MHz Bus Speed over -40˚C <= T
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
1.3 Modes of Operation
User modes
• Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Low power modes
• Stop Mode
• Pseudo Stop Mode
<= 125˚C
A
• Wait Mode
21
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12DP512 device.
22
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Figure 1-1 MC9S12DP512 Block Diagram
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Internal Logic 2.5V
VDD1,2
VSS1,2
PLL 2.5V
VDDPLL
VSSPLL
512K Byte Flash EEPROM
14K Byte RAM
4K Byte EEPROM
Voltage Regulator
Single-wire Background
Debug Module
Clock and
Reset
PLL
Generation
Module
XIRQ
IRQ
W
R/
LSTRB
DDRE
ECLK
MODA
MODB
NOACC/
XCLKS
PTE
Multiplexed Address/Data Bus
DDRA DDRB
PTA PTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
ADDR9
DATA11
DATA10
DATA9
DATA3
DATA2
DATA1
PA0
ADDR8
DATA8
DATA0
PA7
PA6
PA5
ADDR15
ADDR14
ADDR13
DATA15
DATA14
DATA13
DATA7
DATA6
DATA5
ADDR12
DATA12
DATA4
I/O Driver 5V
VDDX
VSSX
A/D Converter 5V &
Voltage Regulator Reference
VDDA
VSSA
Voltage Regulator 5V & I/O
VDDR
VSSR
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
System
Integration
Module
(SIM)
PB4
PB6
PB5
ADDR6
ADDR5
DATA6
DATA5
PB3
ADDR4
ADDR3
DATA4
DATA3
PB7
ADDR7
DATA7
PB2
PB1
ADDR2
ADDR1
DATA2
DATA1
ATD0
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
Enhanced Capture
Timer
SCI0
SCI1
SPI0
BDLC
(J1850)
CAN0
PB0
CAN1
CAN2
ADDR0
CAN3
CAN4
DATA0
IIC
PWM
SPI1
SPI2
VRH
VRL
VDDA
VSSA
PPAGE
MISO
MOSI
SCK
RXB
TXB
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
SDA
SCL
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
MISO
MOSI
SCK
MISO
MOSI
SCK
SS
SS
SS
AD0
ATD1
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
Module to Port Routing
KWJ0
KWJ1
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
VRH
VRL
VDDA
VSSA
DDRK
DDRT
DDRS
DDRM
DDRJ
DDRP
DDRH
AD1
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
23
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
1.5 Device Memory Map
Table 1-1andFigure 1-2 show thedevicememory map oftheMC9S12DP512 after reset.Notethat after
reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space
Table 1-1 Device Memory Map
Address Module
$0000 - $000F HCS12 Multiplexed External Bus Interface 16
$0010 - $0014 HCS12 Module Mapping Control 5
$0015 - $0016 HCS12 Interrupt 2
$0017 - $0019 Reserved 3
$001A - $001B Device ID register (PARTID) 2
$001C - $001D HCS12 Module Mapping Control 2
$001E HCS12 Multiplexed External Bus Interface 1
$001F HCS12 Interrupt 1
$0020 - $0027 Reserved 8
$0028 - $002F HCS12 Breakpoint 8
$0030 - $0031 HCS12 Module Mapping Control 2
$0032 - $0033 HCS12 Multiplexed External Bus Interface 2
$0034 - $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 - $007F Enhanced Capture Timer 16-bit 8 channels 64
$0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$00C8 - $00CF Serial Communications Interface 0 (SCI0) 8
$00D0 - $00D7 Serial Communications Interface 0 (SCI1) 8
$00D8 - $00DF Serial Peripheral Interface (SPI0) 8
$00E0 - $00E7 Inter IC Bus 8
$00E8 - $00EF Byte Data Link Controller (BDLC) 8
$00F0 - $00F7 Serial Peripheral Interface (SPI1) 8
$00F8 - $00FF Serial Peripheral Interface (SPI2) 8
$0100- $010F Flash Control Register 16
$0110 - $011B EEPROM Control Register 12
$011C - $011F Reserved 4
$0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
$0140 - $017F Motorola Scalable Can (CAN0) 64
$0180 - $01BF Motorola Scalable Can (CAN1) 64
$01C0 - $01FF Motorola Scalable Can (CAN2) 64
$0200 - $023F Motorola Scalable Can (CAN3) 64
$0240 - $027F Port Integration Module (PIM) 64
$0280 - $02BF Motorola Scalable Can (CAN4) 64
$02C0 - $03FF Reserved 320
$0000 - $0FFF EEPROM array 4096
$0800 - $3FFF RAM array 14336
$4000 - $7FFF
Fixed Flash EEPROM array
incl. 1K, 2K, 4K or 8K Protected Sector at start
Size
(Bytes)
16384
24
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Table 1-1 Device Memory Map
Address Module
$8000 - $BFFF Flash EEPROM Page Window 16384
Fixed Flash EEPROM array
$C000 - $FFFF
incl. 2K, 4K, 8K or 16K Protected Sector at end
and 256 bytes of Vector Space at $FF80 - $FFFF
Size
(Bytes)
16384
25
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Figure 1-2 MC9S12DP512 Memory Map
$0000
$0400
$0800
$4000
$8000
EXTERN
$0000
$03FF
$0000
$0FFF
$0800
$3FFF
$4000
$7FFF
$8000
REGISTERS
(Mappable to any 2k Block
within the first 32K)
4K Bytes EEPROM
(Mappable to any 4K Block)
14K Bytes RAM
(Mappable to any 16K
and alignable to top or
bottom)
16K Fixed Flash
Page $3E = 62
(This is dependant on the
state of the ROMHM bit)
16K Page Window
32 x 16K Flash EEPROM
pages
$C000
$FF00
$FFFF
$BFFF
$C000
$FFFF
$FF00
VECTORS
EXPANDED*
* Assuming that a ‘0’ was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode.
VECTORS
NORMAL
SINGLE CHIP
VECTORS
SPECIAL
SINGLE CHIP
$FFFF
16K Fixed Flash
Page $3F = 63
BDM
(if active)
26
1.5.1 Detailed Register Map
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0000 PORTA
$0001 PORTB
$0002 DDRA
$0003 DDRB
$0004 -
$0007
$0008 PORTE
$0009 DDRE
$000A PEAR
$000B MODE
Reserved
$000C PUCR
$000D RDRIV
$000E EBICTL
$000F Reserved
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0010 INITRM
$0011 INITRG
$0012 INITEE
$0013 MISC
$0014 Reserved
MC9S12DP512 Device Guide V01.23
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0000000
Write:
Read: 00000000
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read: 0000
Write:
Read: 00000000
Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 65432
Bit 7 6543Bit 2
NOACCE
MODC MODB MODA
PUPKE
RDPK
RAM15 RAM14 RAM13 RAM12 RAM11
EE15 EE14 EE13 EE12 EE11
0
00
00
REG14 REG13 REG12 REG11
PIPOE NECLK LSTRE RDWE
0
PUPEE
RDPE
IVIS
00
00
EXSTR1 EXSTR0 ROMHM ROMON
0
00
000
00
Bit 1 Bit 0
00
00
EMK EME
PUPBE PUPAE
RDPB RDPA
ESTR
RAMHAL
EEON
27
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0015 ITCR
$0016 ITEST
$0017 - $0019 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0017-
$0019
Reserved
$001A - $001B Device ID Register (Table 1-3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001A PARTIDH
$001B PARTIDL
Read: 0 0 0
Write:
Read:
Write:
Read: 00000000
Write:
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
WRINT ADR3 ADR2 ADR1 ADR0
INTE INTC INTA INT8 INT6 INT4 INT2 INT0
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001C MEMSIZ0
$001D MEMSIZ1
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
Write:
Read: rom_sw1 rom_sw0 0000pag_sw1 pag_sw0
Write:
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001E INTCR
Read:
Write:
IRQE IRQEN
000000
$001F - $001F INT map 2 of 2 (HCS12 Interrupt)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001F HPRIO
Read:
Write:
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
$0020 - $0027 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 00000000
Write:
28
$0020 $0027
Reserved
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
$0028 - $002F BKP (HCS12 Breakpoint)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0028 BKPCT0
$0029 BKPCT1
$002A BKP0X
$002B BKP0H
$002C BKP0L
$002D BKP1X
$002E BKP1H
$002F BKP1L
Read:
Write:
Read:
Write:
Read: 0 0
Write:
Read:
Write:
Read:
Write:
Read: 0 0
Write:
Read:
Write:
Read:
Write:
BKEN BKFULL BKBDM BKTAG
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
0000
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0030 PPAGE
$0031 Reserved
Read: 0 0
Write:
Read: 00000000
Write:
PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0032 PORTK
$0033 DDRK
Read:
Write:
Read:
Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0034 SYNR
$0035 REFDV
$0036
$0037 CRGFLG
$0038 CRGINT
CTFLG
Test Only
Read: 0 0
Write:
Read: 0000
Write:
Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
Write:
Read:
Write:
Read:
Write:
RTIF PROF
RTIE
00
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
REFDV3 REFDV2 REFDV1 REFDV0
0
LOCKIF
LOCKIE
LOCK TRACK
00
SCMIF
SCMIE
SCM
0
29
MC9S12DP512 Device Guide V01.23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0039 CLKSEL
$003A PLLCTL
$003B RTICTL
$003C COPCTL
$003D
$003E
$003F ARMCOP
FORBYP
Test Only
CTCTL
Test Only
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read: TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0
Write:
Read: 00000000
Write: Bit 7 654321Bit 0
PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
CME PLLON AUTO ACQ
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
WCOP RSBCK
RTIBYP COPBYP
000
0
PLLBYP
0
00
PRE PCE SCME
CR2 CR1 CR0
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
FCM
0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0040 TIOS
$0041 CFORC
$0042 OC7M
$0043 OC7D
$0044 TCNT (hi)
$0045 TCNT (lo)
$0046 TSCR1
$0047 TTOV
$0048 TCTL1
$0049 TCTL2
$004A TCTL3
$004B TCTL4
$004C TIE
$004D TSCR2
$004E TFLG1
Read:
Write:
Read: 00000000
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Read:
Write:
Read:
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
TEN TSWAI TSFRZ TFFCA
TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
C7I C6I C5I C4I C3I C2I C1I C0I
TOI
C7F C6F C5F C4F C3F C2F C1F C0F
000
0000
TCRE PR2 PR1 PR0
30
Loading...