Freescale MC9S08QE128, MC9S08QE96, MC9S08QE64 Data Sheet

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Freescale Semiconductor

Data Sheet: Advance Information

MC9S08QE128 Series

Covers: MC9S08QE128, MC9S08QE96, MC9S08QE64

• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 50.33-MHz HCS08 CPU from 3.6V to 2.1V, and

20-MHz CPU at 2.1V to 1.8V across temperature range
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources

• On-Chip Memory
– Flash read/program/erase over fulloperatingvoltage and

temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to

RAM and flash contents

• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to

unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode

– Very low power external oscillator can be used in stop3

mode to provide accurate clock to active peripherals

– Very low power real time counter for use in run, wait,

and stop modes with internal and external clock sources

–6μs typical wake up time from stop modes

• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;

Crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 16 MHz

– Internal Clock Source (ICS) — FLL controlled by

internal or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation; supports CPU freq. from 2 to 50.33 MHz

• System Protection
– Watchdog computer operating properly (COP) reset

with option to run from dedicated 1-kHz internal clock
source or bus clock

– Low-voltage detection with reset or interrupt; selectable

trip points
– Illegal opcode detection with reset
– Flash block protection

• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting

during in-circuit debugging (plus two more breakpoints)

– On-chip in-circuit emulator (ICE) debug module

containing two comparators and nine trigger modes.

Document Number: MC9S08QE128

Rev. 3, 06/2007

MC9S08QE128

80-LQFP
Case 917A

2

14 mm

48-QFN
Case 1314

2

7 mm

32-LQFP
Case 873A

2

7 mm

Eight deep FIFO for storing change-of-flow addresses
and event-only data. Debug module supports both tag
and force breakpoints.

• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V

• ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap reference
voltage; outputs can be optionally routed to TPM module;
operation in stop3

• SCIx — Two SCIs with full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN slave
extended break detection; wake up on active edge

• SPIx— Two serial peripheral interfaces with Full-duplex or
single-wire bidirectional; Double-buffered transmit and
receive; MSB-first or LSB-first shifting

• IICx — Two IICs with; Up to 100 kbps with maximum bus
loading; Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10 bit addressing

• TPMx — One 6-channel and two 3-channel; Selectable
input capture, output compare, or buffered edge- or
center-aligned PWMs on each channel

• RTC — 8-bit modulus counter with binary or decimal
based prescaler; External clock source for precise time
base, time-of-day, calendar or task scheduling functions;
Free running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components

• Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input

pins; Configurable slew rate and drive strength on all
output pins.

– SET/CLR registers on 16 pins (PTC and PTE)

64-LQFP

Case 840F

2

10 mm

44-QFP
Case 824A

2

10 mm

This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Table of Contents

1 MC9S08QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . .4

2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12

3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12

3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13

3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14

3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18

3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .21

3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .22

3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 26

3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.10.4 Analog Comparator (ACMP) Electricals . . . . . . 30

3.10.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 30

3.10.6 Flash Specifications . . . . . . . . . . . . . . . . . . . . . 33

3.11 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.11.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 34

3.11.2 Conducted Transient Susceptibility . . . . . . . . . 34

4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . 36

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor2

BKGD/MS

V

DD

V

DD

V

SS

V

SS

PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0

V

REFH

V

REFL

V

DDA

V

SSA

PTH7/SDA2
PTH6/SCL2

PTH5
PTH4
PTH3
PTH2
PTH1
PTH0

HCS08 CORE

CPU

BDC

BKP

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

COP

INT

USER FLASH

128K / 96K / 64K

USER RAM

8K / 6K / 4K

DEBUG MODULE (DBG)

REAL TIME COUNTER (RTC)

VOLTAGE

REGULATOR

LV D

IRQ

PORT J

PORT H

- V

REFH/VREFL

- VDD and VSS pins are each internally connected to two pads in 32-pin package

3-CHANNEL TIMER/PWM

RESET

IRQ

SDA2
SCL2

internally connected to V

MODULE (TPM1)

ANALOG COMPARATOR

(ACMP1)

INTERNAL CLOCK

SOURCE (ICS)

OSCILLATOR (XOSC)

3-CHANNEL TIMER/PWM

MODULE (TPM2)

IIC MODULE (IIC1)

ANALOG COMPARATOR

(ACMP2)

6-CHANNEL TIMER/PWM

MODULE (TPM3)

SERIAL COMMUNICATIONS

INTERFACE (SCI1)

SERIAL PERIPHERAL

INTERFACE MODULE (SPI2)

SERIAL COMMUNICATIONS

INTERFACE (SCI2)

SERIAL PERIPHERAL

INTERFACE MODULE (SPI1)

24-CHANNEL,12-BIT

ANALOG-TO-DIGITAL

CONVERTER (ADC)

IIC MODULE (IIC2)

TPM1CH2-0

TPM1CLK

ACMP1O

ACMP1+
ACMP1-

EXTAL
XTAL

TPM2CH2-0

TPM2CLK

ACMP2+

ACMP2O

ACMP2-

TPM3CH5-0

TPM3CLK

in 48-pin and 32-pin packages

DDA/VSSA

SCL1
SDA1

TxD1
RxD1

SS2
MISO2

MOSI2
SPSCK2

TxD2
RxD2

SS1
MISO1

MOSI1
SPSCK1

PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTA5/IRQ/TPM1CLK/
PTA4/ACMP1O/BKGD/MS

PORT A

3

6

10

PTA3/KBI1P3/SCL1/ADP3
PTA2/KBI1P2/SDA1/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1­PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTB5/TPM1CH1/
PTB4/TPM2CH1/MISO1

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4

PTC7/TxD2/ACMP2­PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4/
PTC3/TPM3CH3
PTC2/TPM3CH2
PTC1/TPM3CH1
PTC0/TPM3CH0

PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTD4/KBI2P4
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2

PTE7/TPM3CLK
PTE6
PTE5
PTE4
PTE3/SS1
PTE2/MISO1
PTE1/MOSI1
PTE0/TPM2CLK/SPSCK1

PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTF3/ADP13
PTF2/ADP12
PTF1/ADP11
PTF0/ADP10

PTG7/ADP23

PTG6/ADP22
PTG5/ADP21
PTG4/ADP20
PTG3/ADP19
PTG2/ADP18
PTG1
PTG0

RESET

SS1

RSTO

Figure 1. MC9S08QE128 Series Block Diagram

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 3

MC9S08QE128 Series Comparison

1 MC9S08QE128 Series Comparison

The following table compares the various device derivatives available within the MC9S08QE128 series.

Table 1. MC9S08QE128 Series Features by MCU and Package

Feature MC9S08QE128 MC9S08QE96 MC9S08QE64

Flash size (bytes) 131072 98304 65536

RAM size (bytes) 8064 6016 4096

Pin quantity 80 64 48 44 80 64 48 44 64 48 44 32

ACMP1 yes

ACMP2 yes

ADC channels 24 22 10 10 24 22 10 10 22 10 10 10

DBG yes

ICS yes

IIC1 yes

IIC2 yes yes no no yes yes no no yes no no no

IRQ yes

KBI 16 16 16 16 16 16 16 16 16 16 16 12

Port I/O

RTC yes

SCI1 yes

SCI2 yes

SPI1 yes

SPI2 yes

TPM1 channels 3

TPM2 channels 3

TPM3 channels 6

XOSC yes

1

1

Port I/O count does not include the input only PTA5/IRQ/TPM1CLK/RESET or the output
only PTA4/ACMP1O/BKGD/MS.

70 54 38 34 70 54 38 34 54 38 34 26

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor4

Pin Assignments

2 Pin Assignments

This section describes the pin assignments for the available packages. See Table 2 for pin availability by package pin-count.

PTD1/KBI2P1/MOSI2

PTD0/KBI2P0/SPSCK2

PTH7/SDA2

PTH6/SCL2

PTH5

PTE7/TPM3CLK

PTB7/SCL1/EXTAL

PTB6/SDA1/XTAL

PTH4

V

V

DDAD

V

REFH

V

REFL

V

SSAD

V

PTH3
PTH2

PTH1
PTH0

PTE6

DD

SS

PTA4/ACMP1O/BKGD/MS

80797877767574737271706968676665646362

1

PTC5/TPM3CH5/ACMP2O

PTC4/TPM3CH4/RSTO

PTA5/IRQ/TPM1CLK/RESET

PTE0/TPM2CLK/SPSCK1

PTE1/MOSI1

PTG0

PTG3/ADP19

PTG2/ADP18

PTG1

PTE2/MISO1

PTE3/SS1

PTG5/ADP21

PTG4/ADP20

PTC7/TxD2/ACMP2-

PTC6/RxD2/ACMP2+

PTG7/ADP23

PTG6/ADP22

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

SS1

PTE5

PTC3/TPM3CH3

PTC2/TPM3CH2

PTB5/TPM1CH1/

PTB4/TPM2CH1/MISO1

PTD7/KBI2P7

PTD6/KBI2P6

PTD5/KBI2P5

PTJ7

PTJ6

PTJ5

PTJ4

PTF7/ADP17

PTC0/TPM3CH0

PTC1/TPM3CH1

PTF6/ADP16

PTF5/ADP15

PTF4/ADP14

Pins in bold are added from the next smaller package.

Figure 2. Pin Assignments in 80-Pin LQFP

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

61

60

PTA2/KBI1P2/SDA1/ADP2

59

PTA3/KBI1P3/SCL1/ADP3

58

PTD2/KBI2P2/MISO2

57

PTD3/KBI2P3/

56

PTD4/KBI2P4

55

PTJ0

54

PTJ1

53

PTF0/ADP10

52

PTF1/ADP11

51

V

SS

50

V

DD

49

PTE4

48

PTA6/TPM1CH2/ADP8

47

PTA7/TPM2CH2/ADP9

46

PTF2/ADP12

45

PTF3/ADP13

PTJ2

44

PTJ3

43

PTB0/KBI1P4/RxD1/ADP4

42

PTB1/KBI1P5/TxD1/ADP5

41

SS2

40

PTB3/KBI1P7/MOSI1/ADP7

PTB2/KBI1P6/SPSCK1/ADP6

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 5

Pin Assignments

RESET

RSTO

SS1

PTD1/KBI2P1/MOSI2

PTD0/KBI2P0/SPSCK2

PTH7/SDA2

PTH6/SCL2

PTE7/TPM3CLK

PTB7/SCL1/EXTAL

PTB6/SDA1/XTAL

V

DDAD

V

REFH

V

V

SSAD

PTH1
PTH0

PTE6

V

DD

REFL

V

Figure 3. Pin Assignments in 64-Pin LQFP Package

PTA4/ACMP1O/BKGD/MS

646362616059585756555453525150

1

PTC5/TPM3CH5/ACMP2O

PTC4/TPM3CH4/

PTE0/TPM2CLK/SPSCK1

PTA5/IRQ/TPM1CLK/

PTE1/MOSI1

PTG1

PTG0

PTE3/

PTE2/MISO1

PTG3/ADP19

PTG2/ADP18

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTC7/TxD2/ACMP2-

PTC6/RxD2/ACMP2+

2
3
4
5
6
7
8
9
10

SS

11
12
13
14
15
16

171819202122232425262728293031

SS1

PTE5

PTF7/ADP17

PTF6/ADP16

PTF5/ADP15

PTD7/KBI2P7

PTD6/KBI2P6

PTC3/TPM3CH3

PTC2/TPM3CH2

PTB5/TPM1CH1/

PTB4/TPM2CH1/MISO1

PTD5/KBI2P5

PTC0/TPM3CH0

PTC1/TPM3CH1

PTF4/ADP14

PTB3/KBI1P7/MOSI1/ADP7

Pins in bold are added from the next smaller package.

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

49

48

PTA2/KBI1P2/SDA11/ADP2
PTA3/KBI1P3/SCL1/ADP3

47

PTD2/KBI2P2/MISO2

46

PTD3/KBI2P3/

45

PTD4/KBI2P4

44

PTF0/ADP10

43

PTF1/ADP11

42

V

41

SS

V

40

DD

PTE4

39

PTA6/TPM1CH2/ADP8

38

PTA7/TPM2CH2/ADP9

37

PTF2/ADP12

36

PTF3/ADP13

35

PTB0/KBI1P4/RxD1/ADP4

34

PTB1/KBI1P5/TxD1/ADP5

33

SS2

32

PTB2/KBI1P6/SPSCK1/ADP6

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor6

PTD1/KBI2P1/MOSI2

PTD0/KBI2P0/SPSCK2

PTE7/TPM3CLK

V

DD

V

DDAD

V

REFH

V

REFL

V

SSAD

V

SS

PTB7/SCL1/EXTAL

PTB6/SDA11/XTAL

PTE6

RESET

RSTO

PTA5/IRQ/TPM1CLK/

PTC4/TPM3CH4/

PTA4/ACMP1O/BKGD/MS

48

47

PTC5/TPM3CH5/ACMP2O

46

45

1

2

3

4

5

6

7

8

9

10

11

12

14

15

13

16

PTE1/MOSI1

PTE0/TPM2CLK/SPSCK1

44

43

17

18

PTE2/MISO1

42

19

SS1

PTE3/

PTC6/RxD2/ACMP2+

PTC7/TxD2/ACMP2-

41

40

39

20

21

22

Pin Assignments

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTA1/KBI1P1/TPM2CH0/AD

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

37

38

23

PTA2/KBI1P2/SDA1/ADP2

36

PTA3/KBI1P3/SCL1/ADP3

35

PTD2/KBI2P2/MISO2

34

PTD3/KBI2P3/

33

PTD4/KBI2P4

32

V

31

SS

V

30

DD

PTE4

29

PTA6/TPM1CH2/ADP8

28

PTA7/TPM2CH2/ADP9

27

PTB0/KBI1P4/RxD1/ADP4

26

PTB1/KBI1P5/TxD1/ADP5

25

SS2

24

PTE5

PTD7/KBI2P7

PTD6/KBI2P6

PTC3/TPM3CH3

PTC2/TPM3CH2

PTD5/KBI2P5

PTC0/TPM3CH0

PTC1/TPM3CH1

PTB5/TPM1CH1/SS1

PTB4/TPM2CH1/MISO1

PTB3/KBI1P7/MOSI1/ADP7

PTB2/KBI1P6/SPSCK1/ADP6

Figure 4. Pin Assignments in 48-Pin QFN Package

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 7

Pin Assignments

PTD1/KBI2P1/MOSI2

PTD0/KBI2P0/SPSCK2

PTB7/SCL1/EXTAL

PTE7/TPM3CLK

V

DD

V

DDAD

V

REFH

V

REFL

V

SSAD

V

PTB6/SDA1/XTAL

SS

RESET

RSTO

PTA5/IRQ/TPM1CLK/

PTA4/ACMP1O/BKGD/MS

44

1

PTC4/TPM3CH4/

43

2

3

4

5

6

7

8

9

10

11

13

12

14

PTE1

17

39

PTE2

38

18

PTE0/TPM2CLK

PTC5/TPM3CH5/ACMP2O

42

41

40

15

16

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTC6/RxD2/ACMP2+

PTC7/TxD2/ACMP2-

37

36

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

35

34

33

32

31

30

29

28

27

26

25

24

23

19

20

21

22

PTA2/KBI1P2/SDA1/ADP2

PTA3/KBI1P3/SCL1/ADP3

PTD2/KBI2P2/MISO2

PTD3/KBI2P3/SS2

PTD4/KBI2P4

V

SS

V

DD

PTA6/TPM1CH2/ADP8

PTA7/TPM2CH2/ADP9

PTB0/KBI1P4/RxD1/ADP4

PTB1/KBI1P5/TxD1/ADP5

PTD7/KBI2P7

PTD6/KBI2P6

PTC3/TPM3CH3

PTC2/TPM3CH2

PTD5/KBI2P5

PTC0/TPM3CH0

PTC1/TPM3CH1

PTB5/TPM1CH1/SS1

PTB4/TPM2CH1/MISO1

PTB3/KBI1P7/MOSI1/ADP7

PTB2/KBI1P6/SPSCK1/ADP6

Figure 5. Pin Assignments in 44-Pin QFP Package

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor8

1

1

RSTO

PTC4/TPM3CH4/

PTA5/IRQ/TPM1CLK/RESET

PTA4/ACMP1O/BKGD/MS

PTC6/RxD2/ACMP2+

PTC5/TPM3CH5/ACMP2O

PTA1/KBIP1/TPM2CH0/ADP1/ACMP

PTA0/KBIP0/TPM1CH0/ADP0/ACMP

PTC7/TxD2/ACMP2-

Pin Assignments

PTD1/KBI2P1/MOSI2

PTD0/KBI2P0/SPSCK2

V

DD

V

REFH/VDDAD

V

REFL/VSSAD

V

SS

PTB7/SCL1/EXTAL

PTB6/SDA1/XTAL

Figure 6. Pin Assignments 32-Pin LQFP Package

31 30 29 28

32

1

2

3

4

5

6

7

8

9

10

PTB5/TPM1CH1/SS1

11

12 13 14

PTC3/TPM3CH3

PTC2/TPM3CH2

PTC1/TPM3CH1

PTC0/TPM3CH0

PTB4/TPM2CH1/MISO1

252627

PTA2/KBIP2/SDA1/ADP2

24

PTA3/KBIP3/SCL1/ADP3

23

22

PTD2/KBI2P2/MISO2

21

PTD3/KBI2P3/SS2

20

PTA6/TPM1CH2/ADP8

19

PTA7/TPM2CH2/ADP9

18

PTB0/KBI1P4/RxD1/ADP4

17

15

16

PTB3/KBI1P7/MOSI1/ADP7

PTB1/KBI1P5/TxD1/ADP5

PTB2/KBI1P6/SPSCK1/ADP6

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 9

Pin Assignments

Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count

Pin Number Lowest ←⎯ Priority ⎯→ Highest

80 64 48 44 32 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

11111PTD1 KBI2P1 MOSI2

22222PTD0 KBI2P0 SPSCK2

3 3 — — — PTH7 SDA2

4 4 — — — PTH6 SCL2

5 ————PTH5

6 ————PTH4

7533—PTE7 TPM3CLK

86443 V

97554 V

10866— V

11977— V

12 10 8 8 5 V

13 11 9 9 6 V

14 12 10 10 7 PTB7 SCL1 EXTAL

15 13 11 11 8 PTB6 SDA1 XTAL

16————PTH3

17————PTH2

18 14 — — — PTH1

19 15 — — — PTH0

20 16 12 — — PTE6

21 17 13 — — PTE5

22 18 14 12 9 PTB5 TPM1CH1

SS1

23 19 15 13 10 PTB4 TPM2CH1 MISO1

24 20 16 14 11 PTC3 TPM3CH3

25 21 17 15 12 PTC2 TPM3CH2

26 22 18 16 — PTD7 KBI2P7

27 23 19 17 — PTD6 KBI2P6

28 24 20 18 — PTD5 KBI2P5

29————PTJ7

30————PTJ6

31————PTJ5

32————PTJ4

33 25 21 19 13 PTC1 TPM3CH1

34 26 22 20 14 PTC0 TPM3CH0

35 27 — — — PTF7 ADP17

36 28 — — — PTF6 ADP16

37 29 — — — PTF5 ADP15

38 30 — — — PTF4 ADP14

39 31 23 21 15 PTB3 KBI1P7 MOSI1 ADP7

40 32 24 22 16 PTB2 KBI1P6 SPSCK1 ADP6

DD

DDA

REFH

REFL

SSA

SS

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor10

Pin Assignments

Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count (continued)

Pin Number Lowest ←⎯ Priority ⎯→ Highest

80 64 48 44 32 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

41 33 25 23 17 PTB1 KBI1P5 TxD1 ADP5

42 34 26 24 18 PTB0 KBI1P4 RxD1 ADP4

43————PTJ3

44————PTJ2

45 35 — — — PTF3 ADP13

46 36 — — — PTF2 ADP12

47 37 27 25 19 PTA7 TPM2CH2 ADP9

48 38 28 26 20 PTA6 TPM1CH2 ADP8

49 39 29 — — PTE4

50 40 30 27 — V

51 41 31 28 — V

52 42 — — — PTF1 ADP11

53 43 — — — PTF0 ADP10

54————PTJ1

55————PTJ0

56 44 32 29 — PTD4 KBI2P4

57 45 33 30 21 PTD3 KBI2P3

SS2

58 46 34 31 22 PTD2 KBI2P2 MISO2

59 47 35 32 23 PTA3 KBI1P3 SCL1 ADP3

60 48 36 33 24 PTA2 KBI1P2 SDA1 ADP2

61 49 37 34 25 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1-

62 50 38 35 26 PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1+

63 51 39 36 27 PTC7 TxD2 ACMP2-

64 52 40 37 28 PTC6 RxD2 ACMP2+

65————PTG7 ADP23

66————PTG6 ADP22

67————PTG5 ADP21

68————PTG4 ADP20

69 53 41 — — PTE3

SS1

70 54 42 38 — PTE2 MISO1

71 55 — — — PTG3 ADP19

72 56 — — — PTG2 ADP18

73 57 — — — PTG1

74 58 — — — PTG0

75 59 43 39 — PTE1 MOSI1

76 60 44 40 — PTE0 TPM2CLK SPSCK1

77 61 45 41 29 PTC5 TPM3CH5 ACMP2O

78 62 46 42 30 PTC4 TPM3CH4

79 63 47 43 31 PTA5 IRQ TPM1CLK

RSTO

RESET

80 64 48 44 32 PTA4 ACMP1O BKGD MS

DD

SS

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 11

Electrical Characteristics

3 Electrical Characteristics

3.1 Introduction

This section contains electrical and timing specifications for the MC9S08QE128 series of microcontrollers available at the time
of publication.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 3. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

Those parameters are achieved by the design characterization by measuring a statistically relevant sample

C

size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this

T

category.

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that
normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either
VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.

Table 4. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage V

Maximum current into V

Digital input voltage V

Instantaneous maximum current

Single pin limit (applies to all port pins)

Storage temperature range T

1

Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (V
voltages, then use the larger of the two resistance values.

2

All functional non-supply pins are internally clamped to VSS and VDD.

DD

1, 2, 3

DD

I

DD

In

I

D

stg

–0.3 to +3.8 V

120 mA

–0.3 to VDD+ 0.3 V

± 25 mA

–55 to 150 °C

) and negative (VSS) clamp

DD

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor12

Electrical Characteristics

3

Power supply must maintain regulation within operating VDDrange during instantaneous and
operating maximum current conditions. If positive injection current (V
I

, the injection current may flow out of VDD and could result in external power supply going

DD

out of regulation. Ensure external V

load will shunt current greater than maximum injection

DD

> VDD) is greater than

In

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it
is user-determined rather than being controlled by the MCU design. To take P
the difference between actual pin voltage and VSSor VDDand multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.

Table 5. Thermal Characteristics

Rating Symbol Value Unit

into account in power calculations, determine

I/O

Operating temperature range
(packaged)

Maximum junction temperature T

T

A

JM

Thermal resistance

Single-layer board

32-pin LQFP

θ

JA

48-pin QFN 81

64-pin LQFP

θ

80-pin LQFP 60

JA

Thermal resistance

Four-layer board

32-pin LQFP

θ

JA

48-pin QFN 26

64-pin LQFP

θ

80-pin LQFP 47

JA

The average chip-junction temperature (TJ) in °C can be obtained from:

TL to T

H

–40 to 85

95 °C

82

69

54

50

°C

°C/W44-pin LQFP 69

°C/W

°C/W44-pin LQFP 47

°C/W

TJ = TA + (PD×θJA) Eqn. 1

where:

TA= Ambient temperature, °C

θJA = Package thermal resistance, junction-to-ambient, °C/W

PD = P
P

int

P

I/O

Freescale Semiconductor 13

+ P

int

I/O

= IDD× VDD, Watts — chip internal power

= Power dissipation on input and output pins — user determined

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Electrical Characteristics

For most applications, P

I/O

<< P

and can be neglected. An approximate relationship between PDand TJ(if P

int

is neglected)

I/O

is:

PD = K ÷ (TJ + 273°C) Eqn. 2

Solving Equation 1 and Equation 2 for K gives:

K = PD× (TA + 273°C) + θJA× (PD)

2

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD(at equilibrium)
for a known TA. Using this value of K, the values of PDand TJcan be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.

Table 6. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series resistance R1 1500 Ω

Human

Body

Machine

Latch-up

Storage capacitance C 100 pF

Number of pulses per pin — 3

Series resistance R1 0 Ω

Storage capacitance C 200 pF

Number of pulses per pin — 3

Minimum input voltage limit – 2.5 V

Maximum input voltage limit 7.5 V

Table 7. ESD and Latch-Up Protection Characteristics

No. Rating

1 Human body model (HBM) V

2 Machine model (MM) V

3 Charge device model (CDM) V

4 Latch-up current at T

1

Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.

1

= 85°CI

A

Symbol Min Max Unit

HBM

MM

CDM

LAT

± 2000 — V

± 200 — V

± 500 — V

± 100 — mA

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor14

3.6 DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 8. DC Characteristics

Electrical Characteristics

Num C Characteristic Symbol Condition Min Typ

1

Max Unit

1 Operating Voltage 1.8 3.6 V

Output high

C

voltage

P All I/O pins,

2

T 2.3 V, I

C 1.8V, I

3D

4

Output high
current

Output low

C

voltage

P All I/O pins,

Max total I

T 2.3 V, I

C 1.8 V, I

Output low

D

current

P Input high

6

voltage

CV

P Input low voltage all digital inputs

7

CV

8 C Input hysteresis all digital inputs V

9P

Input leakage
current

All I/O pins,

low-drive strength

high-drive strength

for all

OH

ports

All I/O pins,

low-drive strength

high-drive strength

Max total I

OL

for all

ports

all digital inputs

all input only pins

(Per pin)

V

I

OHT

V

I

V

V

|I

OH

OL

OLT

IH

IL

hys

In|

1.8 V, I

2.7 V, I

= –2 mA VDD – 0.5 — —

Load

= –10 mA VDD – 0.5 — —

Load

= –6 mA VDD – 0.5 — —

Load

= –3 mA VDD – 0.5 — —

Load

— — 100 mA

1.8 V, I

2.7 V, I

= 2 mA — — 0.5

Load

= 10 mA — — 0.5

Load

= 6 mA — — 0.5

Load

= 3 mA — — 0.5

Load

— — 100 mA5

VDD> 2.7 V 0.70 x V

> 1.8 V 0.85 x V

DD

——

DD

——

DD

VDD> 2.7 V — — 0.35 x V

>1.8 V — — 0.30 x V

DD

VIn = VDD or V

SS

0.06 x V

— 0.1 1 μA

——mV

DD

DD

DD

V

V

V

10 P

Hi-Z (off-state)
leakage current

all input/output

(per pin)

|I

OZ|

VIn= VDDor V

SS

— 0.1 1 μA

Pull-up resistors all digital inputs, when

11 P

12 D

DC injection

2, 3, 4

current

Total MCU limit, includes

enabled

Single pin limit

sum of all stressed pins

13 C Input Capacitance, all pins C

14 C RAM retention voltage V

15 C POR re-arm voltage

5

16 D POR re-arm time t

Low-voltage detection threshold —

P

17

high range

R

V

V

PU

I

IC

In

RAM

POR

POR

LVDH

VIN< VSS, VIN> V

VDD falling

V

rising

DD

17.5 — 52.5 kΩ

–0.2 — 0.2 mA

DD

–5 — 5 mA

—— 8pF

— 0.6 1.0 V

0.9 1.4 2.0 V

10 — — μs

2.08

2.16

2.1

2.19

2.2

2.27

V

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 15

Electrical Characteristics

Table 8. DC Characteristics (continued)

1.82

1.90

2.46

2.46

2.1

2.19

1

Max Unit

1.91

1.99

2.56

2.56

2.2

2.27

Num C Characteristic Symbol Condition Min Typ

18 P

19 P

20 P

21 P Low-voltage inhibit reset/recover hysteresis V

22 P Bandgap Voltage Reference

1

Typical values are measured at 25°C. Characterized, not tested

2

All functional non-supply pins are internally clamped to VSS and VDD.

3

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

Low-voltage detection threshold —
low range

Low-voltage warning threshold —
high range

Low-voltage warning threshold —
low range

6

V

V

V

V

LVDL

LVWH

LVWL

hys

BG

VDD falling

V

rising

DD

VDD falling

V

rising

DD

VDD falling

V

rising

DD

1.80

1.88

2.36

2.36

2.08

2.16

—80—mV

1.19 1.20 1.21 V

resistance values for positive and negative clamp voltages, then use the larger of the two values.

4

Power supply must maintain regulation within operating VDDrange during instantaneous and operating maximum current
conditions. If positive injection current (V

In>VDD

in external power supply going out of regulation. Ensure external V

) is greater than IDD, the injection current may flow out of VDDand could result

load will shunt current greater than maximum injection

DD

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).

5

Maximum is highest voltage that POR is guaranteed.

6

Factory trimmed at VDD = 3.0 V, Temp = 25°C

40

35

PULL-UP RESISTOR TYPICALS

85°C

25°C
–40°C

40

35

PULL-DOWN RESISTOR TYPICALS

85°C

25°C

–40°C

V

V

V

30

25

PULL-UP RESISTOR (kΩ)

20

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

VDD (V)

Figure 7. Pull-up and Pull-down Typical Resistor Values

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

30

25

PULL-DOWN RESISTANCE (kΩ)

20

1.8 2.3 2.8 3.3

(V)

V

DD

3.6

Freescale Semiconductor16

Electrical Characteristics

1.2

1

85°C

25°C

–40°C

0.8

TYPICAL VOL VS IOL AT VDD= 3.0 V

0.6

(V)

OL

0.4

V

0.2

0

0 5 10 15 20

IOL (mA)

Figure 8. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

1

0.8

25°C
–40°C

0.6

(V)

0.4

OL

V

0.2

0

0102030

TYPICAL VOL VS IOL AT VDD= 3.0 V

85°C

(mA)

I

OL

Figure 9. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)

(V)

OL

V

0.2

TYPICAL VOL VS V

DD

0.15

0.1

85°C,

0.05

25°C,

–40°C,

IOL= 2 mA
IOL= 2 mA

IOL= 2 mA

0

1234

VDD (V)

(V)

OL

V

0.4

0.3

0.2

0.1

85°C
25°C
–40°C

TYPICAL VOL VS V

IOL = 6 mA

DD

I

OL

= 10 mA

IOL = 3 mA

0

1234

VDD (V)

(V)

OH

– V

DD

V

1.2

0.8

0.6

0.4

0.2

TYPICAL VDD– VOH VS IOH AT VDD= 3.0 V

(V)

OH

– V

DD

V

0.25

0.2

0.15

0.1

85°C

1

25°C

–40°C

TYPICAL VDD– VOH VS VDD AT SPEC I

85°C,

IOH= 2 mA

25°C,

IOH= 2 mA

–40°C,

IOH= 2 mA

OH

0.05

0

–20–15–10–50

(mA))

I

OH

0

1234

VDD (V)

Figure 10. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 17

Electrical Characteristics

TYPICAL VDD – VOH VS VDDAT SPEC I

(V)

OH

– V

DD

V

0.8

0.6

0.4

0.2

0.4

TYPICAL VDD– VOH VS IOH AT VDD= 3.0 V

85°C

25°C

–40°C

0

I

(mA)

OH

–30–25–20–15–10–50

(V)

OH

– V

DD

V

0.3

0.2

0.1

0

85°C

25°C
–40°C

IOH= –3 mA

1234

Figure 11. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

3.7 Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 9. Supply Current Characteristics

Num C Parameter Symbol

P Run supply current

FEI mode, all modules on

T 20 MHz 14.4 TBD

1

T 8 MHz 6.5 TBD

RI

DD

Bus

Freq

25.165 MHz

V

DD

(V)

3

Typ

17.5 TBD

VDD (V)

1

I

OH

= –6 mA

Max Unit

mA –40 to 85°C

I

OH

OH

= –10 mA

Temp

(°C)

T 1 MHz 1.4 TBD

DD

25.165 MHz

3

C Run supply current

FEI mode, all modules off

T 20 MHz 9.5 TBD

2

RI

T 8 MHz 4.6 TBD

T 1 MHz 1.0 TBD

Run supply current

T

3

LPS=0, all modules off

RI

DD

T

16 kHz

FBILP

3

16 kHz
FBELP

Run supply current

T

LPS=1, all modules off, running from
Flash

4

Run supply current

T

LPS=1, all modules off, running from

RI

DD

16 kHz
FBELP

3

RAM

DD

25.165 MHz

3

C Wait mode supply current

FEI mode, all modules off

T 20 MHz 4570 TBD

5

WI

T 8 MHz 2000 TBD

T 1 MHz 730 TBD

11.5 TBD

152

115

TBD

TBD

TBD

21.9
TBD

TBD 0 to 70°C

7.3
TBD

5740 TBD

mA –40 to 85°C

μA –40 to 85°C

0 to 70°C

–40 to 85°C

μA

–40 to 85°C

μA –-40 to 85°C

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor18

Table 9. Supply Current Characteristics (continued)

Electrical Characteristics

Num C Parameter Symbol

Bus

Freq

V

DD

(V)

Stop2 mode supply current

3 350

P TBD –40 to 85°C

6

S2I

DD

n/a

2 250

C TBD –40 to 85°C

Stop3 mode supply current
No clocks active

P 3 TBD –40 to 85°C

7

S3I

DD

n/a

3

2

C 2 TBD –40 to 85°C

8T

EREFSTEN=1 32 kHz

9 T IREFSTEN=1 32 kHz 70

10 T TPM PWM 100 Hz 12

11 T SCI, SPI, or IIC 300 bps 15

Low power

mode adders:

3

12 T RTC using LPO 1 kHz 200

Typ

450

350

500

1

Max Unit

TBD

nA

TBD 0 to 70°C

TBD

nA

TBD 0 to 70°C

TBD

nA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

nA

TBD –40 to 85°C

Temp

(°C)

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

13 T

RTC using

ICSERCLK

32 kHz 1

14 T LVD n/a 100

15 T ACMP n/a 20

1

Data in Typical column was characterized at 3.0 V, 25˚C or is typical recommended value.

TBD

0 to 70°C

μA

TBD –40 to 85°C

TBD

0 to 70°C

μA

TBD –40 to 85°C

TBD

0 to 70°

C

μA

TBD –40 to 85°C

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 19

Electrical Characteristics

TBD

Figure 12. Typical Run IDD for FBE and FEI, IDD vs. V

(ACMP and ADC off, All Other Modules Enabled)

DD

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor20

Electrical Characteristics

3.8 External Oscillator (XOSC) Characteristics

Reference Figure 13 and Figure 14 for crystal or resonator circuits.

Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)

Num C Characteristic Symbol Min Typ

1

Max Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

f

1C

Load capacitors

2D

Feedback resistor

3D

Series resistor —

4D

Crystal start-up time

5C

Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)

Low range (RANGE=0), low power (HGO=0)
Other oscillator settings

Low range, low power (RANGE=0, HGO=0)

2

Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)

Low range, low power (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)

≥ 8 MHz
4 MHz
1 MHz

4

Low range, low power
Low range, high power
High range, low power
High range, high power

2

f
f

C

1,C2

R

R

t

CSTL

t

CSTH

lo

hi

hi

F

S

32

—
—
—

—
—
—

—
—
—

—
—
—
—

—
1
1

—

—

See Note

See Note

—

10

1

—

0

100

0
0
0

200
400

5

15

38.4
16

8

2

3

—
—
—

—
—
—

0
10
20

—
—
—
—

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

6D

FEE mode
FBE or FBELP mode

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.

3

See crystal or resonator manufacturer’s recommendation.

4

Proper PC board layout procedures must be followed to achieve specifications.

f

extal

0.031250—
—

50.33

50.33

kHz
MHz
MHz

MΩ

kΩ

ms

MHz
MHz

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 21

Electrical Characteristics

XOSC

EXTAL XTAL

R

F

R

S

C

1

Crystal or Resonator

C

2

Figure 13. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain

XOSC

EXTAL XTAL

Crystal or Resonator

Figure 14. Typical Crystal or Resonator Circuit: Low Range/Low Gain

3.9 Internal Clock Source (ICS) Characteristics

Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)

Num C Characteristic Symbol Min Typ

1P

2P

3T

4

Average internal reference frequency — factory trimmed

at V

= 3.6 V and temperature = 25°C

DD

Internal reference frequency — user trimmed f

Internal reference start-up time t

P

Low range (DRS=00)

DCO output frequency range —
trimmed

2

P High range (DRS=10) 48 — 60

P

DCO output frequency

Reference = 32768 Hz

P Mid range (DRS=01) — 39.85 —

5

P

and

DMX32 = 1

2

Low range (DRS=00)

High range (DRS=10)

f

int_ft

int_ut

IRST

f

dco_u

f

dco_DMX32

— 32.768 — kHz

31.25 — 39.06 kHz

— 60 100 μs

16 — 20

— 19.92 —

59.77

—

1

Max Unit

MHzC Mid range (DRS=01) 32 — 40

MHz

—

6C

7C

Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)

Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Δf

dco_res_t

Δf

dco_res_t

— ± 0.1 ± 0.2

— ± 0.2 ± 0.4

Freescale Semiconductor22

%f

%f

dco

dco

Electrical Characteristics

Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)

+ 0.5

-1.0

1

Max Unit

± 2

Num C Characteristic Symbol Min Typ

8C

9C

10 C

11 C

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

3

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing

Total deviation of trimmed DCO output frequency over voltage
and temperature

Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C

FLL acquisition time

3

Long term jitter of DCO output clock (averaged over 2-ms interval)

4

Δf

dco_t

Δf

dco_t

t

Acquire

C

Jitter

—

— ± 0.5 ± 1

—— 1ms

— 0.02 0.2

from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.

4

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

Bus

.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V

and VSSand variation in crystal oscillator frequency increase the C

DD

percentage for a

Jitter

given interval.

%f

%f

%f

dco

dco

dco

TBD

Figure 15. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V)

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 23

Electrical Characteristics

TBD

Figure 16. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C)

3.10 AC Characteristics

This section describes timing characteristics for each peripheral system.

3.10.1 Control Timing

Table 12. Control Timing

Num C Rating Symbol Min Typ

Bus frequency (t

1D

2 D Internal low power oscillator period t

3 D External reset pulse width

4 D Reset low drive t

5D

6D

V

≤ 2.1V

DD

V

> 2.1V

DD

BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes

BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes

cyc

= 1/f

Bus

)

f

Bus

LPO

2

3

t

extrst

rstdrv

t

MSSU

t

MSH

dc
dc

700 — 1300 μs

100 — — ns

34 x t

cyc

500 — — ns

100 — — μs

1

Max Unit

—
—

——ns

10

25.165

MHz

IRQ pulse width

7D

Asynchronous path
Synchronous path

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

2

4

t

ILIH,tIHIL

100

1.5 x t

cyc

—
—

—
—

Freescale Semiconductor24

ns

Table 12. Control Timing (continued)

Electrical Characteristics

—
—

TBD
TBD

1

Max Unit

—
—

—
—

Num C Rating Symbol Min Typ

Keyboard interrupt pulse width

8D

Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)

Asynchronous path
Synchronous path

2

4

5

t

ILIH,tIHIL

, t

t

Rise

Fall

100

1.5 x t

—

cyc

—

9C

Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

10 C

1

Typical values are based on characterization data at VDD= 3.0V, 25°C unless otherwise stated.

2

This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not

Stop3 recovery time, from interrupt event to vector fetch t

t

Rise

STPREC

, t

Fall

—
—

TBD
TBD

—
—

—610μs

guaranteed to override reset requests from internal sources.

3

To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
rises above V

4

This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

LV D

.

MSH

after V

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.

5

Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.

ns

ns

ns

DD

RESET PIN

KBIPx

IRQ/KBIPx

t

extrst

Figure 17. Reset Timing

t

IHIL

t

ILIH

Figure 18. IRQ/KBIPx Timing

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 25

Electrical Characteristics

3.10.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 13. TPM Input Timing

No. C Function Symbol Min Max Unit

1 D External clock frequency f

2 D External clock period t

3 D External clock high time t

4 D External clock low time t

5 D Input capture pulse width t

t

TCLK

t

clkh

TCLK

Figure 19. Timer External Clock

t

ICPW

TPMCHn

TPMCHn

t

ICPW

TCLK

TCLK

clkh

clkl

ICPW

0f

4—t

1.5 — t

1.5 — t

1.5 — t

t

clkl

/4 Hz

Bus

cyc

cyc

cyc

cyc

Figure 20. Timer Input Capture Pulse

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor26

3.10.3 SPI Timing

Table 14 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.

Table 14. SPI Timing

No. C Function Symbol Min Max Unit

Electrical Characteristics

Operating frequency

—D

Master
Slave

SPSCK period

1D

Master

t

Slave

Enable lead time

2D

Master
Slave

Enable lag time

3D

Master
Slave

Clock (SPSCK) high or low time

4D

Master

t

WSPSCK

Slave

Data setup time (inputs)

5D

Master
Slave

Data hold time (inputs)

6D

Master
Slave

7 D Slave access time t

8 D Slave MISO disable time t

Data valid (after SPSCK edge)

9D

Master
Slave

f

op

SPSCK

t

Lead

t

Lag

t

SU

t

HI

a

dis

t

v

f

/2048

Bus

0

2
4

1/2

1

1/2

1

t

–30

cyc

t

– 30

cyc

15
15

0

25

—1t

—1t

—
—

f

Bus

f

Bus

2048

—

—
—

—
—

1024 t

—

—
—

—
—

25
25

/2
/4

cyc

Hz
Hz

t

cyc

t

cyc

t

SPSCK

t

cyc

t

SPSCK

t

cyc

ns
ns

ns
ns

ns
ns

cyc

cyc

ns
ns

10 D

Data hold time (outputs)

Master
Slave

t

HO

0
0

—
—

ns
ns

Rise time

11 D

Input
Output

t

t

RI

RO

—
—

t

cyc

– 25

25

ns
ns

Fall time

12 D

Input
Output

t

FI

t

FO

—
—

t

cyc

– 25

25

ns
ns

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 27

Electrical Characteristics

1

SS

(OUTPUT)

2

SPSCK

(CPOL = 0)

(OUTPUT)

1

4

4

SPSCK

(CPOL = 1)

(OUTPUT)

5

MISO

(INPUT)

9

MOSI

(OUTPUT)

MSB IN

MSB OUT

6

2

BIT 6 . . . 1

9

2

BIT 6 . . . 1

NOTES:

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 21. SPI Master Timing (CPHA = 0)

(1)

SS

(OUTPUT)

1

SPSCK

(CPOL = 0)

(OUTPUT)

SPSCK

(CPOL = 1)

(OUTPUT)

MISO

(INPUT)

2

4 4

5

MSB IN

6

(2)

12

11

BIT 6 . . . 1

LSB IN

LSB OUT

11

12

11

12

LSB IN

3

10

3

9 10

MOSI

(OUTPUT)

PORT DATA

MASTER MSB OUT

(2)

NOTES:

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 22. SPI Master Timing (CPHA =1)

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

BIT 6 . . . 1

MASTER LSB OUT

PORT DATA

Freescale Semiconductor28

SS

(INPUT)

SPSCK

(CPOL = 0)

(INPUT)

SPSCK

(CPOL = 1)

(INPUT)

MISO

(OUTPUT)

2

7

SLAVE

4

MSB OUT

1

4

9

BIT 6 . . . 1

Electrical Characteristics

3

12

11

10

SLAVE LSB OUT

11

12

8

10

SEE

NOTE

5

MOSI

(INPUT)

NOTE:

6

MSB IN

1. Not defined but normally MSB of character just received

Figure 23. SPI Slave Timing (CPHA = 0)

SS

(INPUT)

1

SEE

NOTE

7

2

4

4

9 10

SLAVE

5

MSB OUT

6

MSB IN

SPSCK

(CPOL = 0)

(INPUT)

SPSCK

(CPOL = 1)

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

BIT 6 . . . 1

12

11

BIT 6 . . . 1

BIT 6 . . . 1

LSB IN

3

11

12

8

SLAVE LSB OUT

LSB IN

NOTE:

1. Not defined but normally LSB of character just received

Figure 24. SPI Slave Timing (CPHA = 1)

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 29

Electrical Characteristics

3.10.4 Analog Comparator (ACMP) Electricals

Table 15. Analog Comparator Electrical Specifications

C Characteristic Symbol Min Typical Max Unit

D Supply voltage V

P Supply current (active) I

D Analog input voltage V

P Analog input offset voltage V

C Analog comparator hysteresis V

P Analog input leakage current I

C Analog comparator initialization delay t

DD

DDAC

AIN

AIO

H

ALKG

AINIT

VSS – 0.3 — V

3.10.5 ADC Characteristics

Table 16. 12-bit ADC Operating Conditions

C Characteristic Conditions Symb Min Typ

Supply voltage Absolute V

D

Delta to V

D Ground voltage Delta to V

(VDD-V

DD

SS

(VSS-V

DDAD

SSAD

2

)

)2ΔV

D Ref Voltage High V

D Ref Voltage Low V

D Input Voltage V

Input

C

Capacitance

C Input Resistance R

Analog Source
Resistance

C

ADC Conversion

D

Clock Freq.

1

Typical values assume V

12 bit mode

f

> 4MHz

ADCK

f

< 4MHz

ADCK

10 bit mode

f

> 4MHz

ADCK

f

< 4MHz

ADCK

8 bit mode (all valid f

)——10

ADCK

High Speed (ADLPC=0) f

Low Power (ADLPC=1) 0.4 — 4.0

= 3.0V, Temp = 25°C, f

DDAD

only and are not tested in production.

2

DC potential difference.

DDAD

ΔV

DDAD

SSAD

REFH

REFL

ADIN

C

ADIN

ADIN

R

AS

ADCK

=1.0MHz unless otherwise stated. Typical values are for reference

ADCK

1.8 — 3.6 V

-100 0 +100 mV

-100 0 +100 mV

1.8 V

V

SSAD

V

REFL

— 4.5 5.5 pF

—5 7kΩ

—
—

—
—

0.4 — 8.0 MHz

1.80 — 3.6 V

—2035μA

DD

20 40 mV

3.0 9.0 15.0 mV

— — 1.0 μA

— — 1.0 μs

1

Max Unit Comment

DDAD

V

SSAD

—V

V

DDAD

V

SSAD

REFH

V

V

V

kΩ External to MCU
—
—

—
—

2
5

5

10

V

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor30

Electrical Characteristics

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Z

AS

R

AS

Pad
leakage
due to
input
protection

Z

ADIN

SIMPLIFIED

CHANNEL SELECT

R

ADIN

CIRCUIT

ADC SAR

ENGINE

+

V

ADIN

C

V

+

AS

–

AS

–

R

ADIN

INPUT PIN

INPUT PIN

INPUT PIN

Figure 25. ADC Input Impedance Equivalency Diagram

Table 17. 12-bit ADC Characteristics (V

Characteristic Conditions C Symb Min Typ

Supply Current
ADLPC=1
ADLSMP=1
ADCO=1

Supply Current
ADLPC=1
ADLSMP=0
ADCO=1

Supply Current
ADLPC=0
ADLSMP=1
ADCO=1

Supply Current
ADLPC=0
ADLSMP=0
ADCO=1

TI

DDAD

TI

DDAD

TI

DDAD

PI

DDAD

= V

REFH

— 120 — μA

— 202 — μA

— 288 — μA

— 0.532 1 mA

DDAD

1

R

ADIN

R

ADIN

C

ADIN

, V

REFL

= V

SSAD

)

Max Unit Comment

Supply Current Stop, Reset, Module Off I

ADC
Asynchronous
Clock Source

High Speed (ADLPC=0) P f

Low Power (ADLPC=1) C 1.25 2 3.3

DDAD

ADACK

— 0.007 0.8 μA

2 3.3 5 MHz t

ADACK

= 1/f

ADACK

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 31

Electrical Characteristics

Table 17. 12-bit ADC Characteristics (V

REFH

= V

DDAD

Characteristic Conditions C Symb Min Typ

Conversion Time
(Including
sample time)

Sample Time Short Sample (ADLSMP=0) P t

Short Sample (ADLSMP=0) P t

ADC

— 20 — ADCK

Long Sample (ADLSMP=1) C — 40 —

ADS

— 3.5 — ADCK

Long Sample (ADLSMP=1) C — 23.5 —

Total Unadjusted
Error

12 bit mode T E

TUE

10 bit mode P — ±1 ±2.5

— ±3.0 — LSB

8 bit mode T — ±0.5 1.0

Differential
Non-Linearity

Integral
Non-Linearity

12 bit mode T DNL — ±1.75 — LSB

10 bit mode

8 bit mode

3

3

P—±0.5 ±1.0

T—±0.3 ±0.5

12 bit mode T INL — ±1.5 — LSB

10 bit mode P — ±0.5 ±1.0

8 bit mode T — ±0.3 ±0.5

Zero-Scale Error 12 bit mode T E

ZS

— ±1.5 — LSB

10 bit mode P — ±0.5 ±1.5

, V

REFL

1

= V

) (continued)

SSAD

Max Unit Comment

See the ADC

cycles

chapter in the

MC9S08QE128

Reference Manual

cycles

for conversion time

variances

2

Includes

Quantization

2

2

2

V

= V

ADIN

SSAD

8 bit mode T — ±0.5 ±0.5

Full-Scale Error 12 bit mode T E

FS

— ±1.0 — LSB

10 bit mode P — ±0.5 ±1

8 bit mode T — ±0.5 ±0.5

Quantization
Error

12 bit mode D E

Q

10 bit mode — — ±0.5

— -1 to 0 — LSB

8 bit mode — — ±0.5

Input Leakage
Error

12 bit mode D E

IL

10 bit mode — ±0.2 ±4

— ±2 — LSB2Pad leakage4 * R

8 bit mode — ±0.1 ±1.2

Temp Sensor
Slope

Temp Sensor
Voltage

1

Typical values assume V

-40°C to 25°C D m — 1.646 — mV/°C

25°C to 85°C — 1.769 —

25°CDV

= 3.0V, Temp = 25°C, f

DDAD

TEMP2

5

=1.0MHz unless otherwise stated. Typical values are for reference

ADCK

— 701.2 — mV

only and are not tested in production.

2

1 LSB = (V

3

Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes

4

Based on input pad leakage current. Refer to pad electricals.

REFH

- V

REFL

)/2

N

2

V

= V

ADIN

2

DDAD

AS

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor32

Electrical Characteristics

3.10.6 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.

Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section of the MC9S08QE128 Reference Manual.

Table 18. Flash Characteristics

C Characteristic Symbol Min Typical Max Unit

Supply voltage for program/erase

D

-40°C to 85°CV

D Supply voltage for read operation V

D Internal FCLK frequency

1

D Internal FCLK period (1/FCLK) t

P Byte program time (random location)

P Byte program time (burst mode)

P Page erase time

P Mass erase time

Byte program current

Page erase current

Program/erase endurance

C

TL to TH = –40°C to + 85°C

2

(2)

3

3

4

(2)

(2)

prog/erase

Read

f

FCLK

Fcyc

t

prog

t

Burst

t

Page

t

Mass

R

IDDBP

R

IDDPE

T = 25°C

C Data retention

1

The frequency of this clock is controlled by a software setting.

2

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied

5

t

D_ret

for calculating approximate time to program and erase.

3

The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with V

4

Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on

= 3.0 V, bus frequency = 4.0 MHz.

DD

how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.

5

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

1.8 3.6 V

1.8 3.6 V

150 200 kHz

5 6.67 μs

9t

4t

4000 t

20,000 t

Fcyc

Fcyc

Fcyc

Fcyc

—4—mA

—6—mA

10,000

—

—

100,000

—
—

cycles

15 100 — years

3.11 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 33

Electrical Characteristics

3.11.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).

The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.

Table 19. Radiated Emissions, Electric Field

1

Parameter Symbol Conditions Frequency f

OSC/fBUS

Level

(Max)

Unit

Radiated emissions,
electric field

1

Data based on qualification test results.

V

RE_TEM

VDD = TBD

T

= +25oC

A

package type

TBD

0.15 – 50 MHz

50 – 150 MHz TBD

150 – 500 MHz TBD

500 – 1000 MHz TBD

IEC Level TBD —

SAE Level TBD —

TBD crystal

TBD bus

TBD

dBμV

3.11.2 Conducted Transient Susceptibility

Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 20.

Table 20. Conducted Susceptibility, EFT/B

Parameter Symbol Conditions

VDD = TBD
Conducted susceptibility, electrical
fast transient/burst (EFT/B)

1

Data based on qualification test results. Not tested in production.

V

CS_EFT

T

A

package type

= +25oC

TBD

f

OSC/fBUS

TBD crystal

TBD bus

Result

A TBD

B TBD

C TBD

D TBD

Amplitude

(Min)

1

Unit

kV

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor34

The susceptibility performance classification is described in Table 21.

Table 21. Susceptibility Performance Classification

Result Performance Criteria

A No failure The MCU performs as designed during and after exposure.

Ordering Information

B

C Soft failure

D Hard failure

E Damage

Self-recovering

failure

The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.

The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.

The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.

The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.

4 Ordering Information

This section contains ordering information for MC9S08QE128, MC9S08QE96, and MC9S08QE64 devices.

Table 22. Ordering Information

Freescale Part Number

MC9S08QE128CLK

MC9S08QE128CLH 64 LQFP

MC9S08QE128CFT 48 QFN

MC9S08QE128CQD 44 QFP

MC9S08QE96CLK

MC9S08QE96CLH 64 LQFP

MC9S08QE96CFT 48 QFN

MC9S08QE96CQD 44 QFP

MC9S08QE64CLH

MC9S08QE64CFT 48 QFN

MC9S08QE64CQD 44 QFP

MC9S08QE64CLC 32 LQFP

1

See the reference manual, MC9S08QE128RM, for a complete description of modules included
on each device.

2

See Ta bl e 2 3 for package information.

1

Memory

Flash RAM

128K 8K

96K 6K

64K 4K

Package

80 LQFP

80 LQFP

64 LQFP

2

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 35

Package Information

4.1 Device Numbering System

Example of the device numbering system:

QE

128 C

XX

Package designator (see Ta bl e 2 3 )

Temperature range

(C = –40°C to 85°C)

Approximate flash size in Kbytes

(MC = Fully Qualified)

Status

Memory

(9 = Flash-based)

Core

Family

MC

9

S08

5 Package Information

The below table details the various packages available.

Table 23. Package Descriptions

Pin Count Package Type Abbreviation Designator Case No. Document No.

80 Low Quad Flat Package LQFP LK 917A 98ASS23237W

64 Low Quad Flat Package LQFP LH 840F 98ASS23234W

48 Quad Flat No-Leads QFN FT 1314 98ARH99048A

44 Quad Flat Package QFP QD 824A 98ASB42839B

32 Low Quad Flat Package LQFP LC 873A 98ASH70029A

5.1 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 23. For the latest available drawings please
visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor36

Package Information

4X

1

–L–

20

C

–H–
–T–

SEATING
PLANE

0.05 (0.002)

DATE 09/21/95

4X 20 TIPS

L–M0.20 (0.008) H N

6180

60

L–M0.20 (0.008) T N

C

L

AB

AB

–M–

VIEW Y

PLATING

J

F

D

M

SECTION AB–AB

ROTATED 90 CLOCKWISE

MILLIMETERS

14.00 BSC 0.551 BSC

0 10
0
9 14

_

____
__
__

__

21

3X

VIEW Y

A1

S1

C2

S

A
S

(W)

C1

VIEW AA

–N–

8X

(Z)

(K)

B

V

V1

B1

41

40

0.13 (0.005) N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD

2

q

0.10 (0.004) T

VIEW AA

1

q

q

0.25 (0.010)

GAGE
PLANE

R1

2X R

E

CASE 917A-02

ISSUE C

WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).

DIMAMIN MAX MIN MAX

A1 7.00 BSC 0.276 BSC

B 14.00 BSC 0.551 BSC

B1 7.00 BSC 0.276 BSC

C ––– 1.60 ––– 0.063
C1 0.04 0.24 0.002 0.009
C2 1.30 1.50 0.051 0.059

D 0.22 0.38 0.009 0.015

E 0.40 0.75 0.016 0.030

F 0.17 0.33 0.007 0.013

G 0.65 BSC 0.026 BSC

J 0.09 0.27 0.004 0.011
K 0.50 REF 0.020 REF
P 0.325 BSC 0.013 REF

R1 0.10 0.20 0.004 0.008

S 16.00 BSC 0.630 BSC

S1 8.00 BSC 0.315 BSC

U 0.09 0.16 0.004 0.006
V 16.00 BSC 0.630 BSC

V1 8.00 BSC 0.315 BSC
W 0.20 REF 0.008 REF

Z 1.00 REF 0.039 REF

0

01 ––– –––
02

Figure 26. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)

G

L–M

T

INCHES

0 10
0
9 14

–X–

X= L, M, N

U

S

BASE

METAL

P

S

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 37

Package Information

Figure 27. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor38

Package Information

Figure 28. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 39

Package Information

Figure 29. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor40

Package Information

Figure 30. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 1 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 41

Package Information

Figure 31. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 2 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor42

Package Information

Figure 32. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 3 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 43

Package Information

Figure 33. 44-pin QFP Package Drawing (Case 824A, Doc #98ASB42839B), Sheet 1 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor44

Package Information

Figure 34. 44-pin QFP Package Drawing (Case 824A, Doc #98ASB42839B), Sheet 2 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 45

Package Information

Figure 35. 44-pin QFP Package Drawing (Case 824A, Doc #98ASB42839B), Sheet 3 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor46

Package Information

Figure 36. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 1 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 47

Package Information

Figure 37. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 2 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor48

Package Information

Figure 38. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 3 of 3

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 49

Product Documentation

6 Product Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MC9S08QE128RM)

Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.

7 Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://www.freescale.com

The following revision history table summarizes changes contained in this document.

Table 24. Revision History

Revision Date Description of Changes

3 25 Jun 2007 Initial public Advance Information release.

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor50

Revision History

MC9S08QE128 Series Advance Information Data Sheet, Rev. 3

Freescale Semiconductor 51

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© Freescale Semiconductor, Inc. 2007. All rights reserved.

Document Number: MC9S08QE128

Rev. 3
06/2007