Freescale MC9328MXL Advance Information

查询MC9328MXLCVF15供应商

Freescale Semiconductor

Advance Information

MC9328MXL

MC9328MXL/D

Rev. 5, 08/2004

MC9328MXL

Package Information

Plastic Package

(MAPBGA–225 or 256)

Ordering Information

See Table 2 on page 5

1 Introduction

The i.MX family builds on the DragonBall family of
application processors which have demonstrated leadership
in the portable handheld market. Continuing this legacy, the
i.MX (Media Extensions) series provides a leap in
performance with an ARM9™ microprocessor core and
highly integrated system functions. The i.MX products
specifically address the requirements of the personal,
portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power
management capabilities.

The new MC9328MXL features the advanced and power­efficient ARM920T™ core that operates at speeds up to
200 MHz. Integrated modules, which include an LCD
controller, USB support, and an MMC/SD host controller,
support a suite of peripherals to enhance any product seeking
to provide a rich multimedia experience. It is packaged in
either a 256-pin Mold Array Process-Ball Grid Array
(MAPBGA) or 225-pin PBGA package. Figure 1 shows the
functional block diagram of the MC9328MXL.

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

2 Signals and Connections . . . . . . . . . . . . . . . . . . . .6

3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Pin-Out and Package Information. . . . . . . . . . . . .79

Contact Information . . . . . . . . . . . . . . . . . Last Page

© Freescale Semiconductor, Inc., 2004. All rights reserved.
This document contains information on a new product. Specifications and information herein are
subject to change without notice.

Introduction

JTAG/ICE

Connectivity

MMC/SD

Memory Stick®
Host Controller

SPI 1 and

SPI 2

UART 1

UART 2

SSI/I2S

I2C

USB Device

System Control

Bootstrap

AIPI 1

AIPI 2

Power

Control (PLLx2)

MC9328MXL

CPU Complex

ARM9TDMI™

I Cache

VMMU

(11 Chnl)

EIM &

SDRAMC

CGM

D Cache

Interrupt

Controller

BusDMAC

Control

Figure 1. MC9328MXL Functional Block Diagram

Standard

System I/O

GPIO

PWM

Timer 1 & 2

RTC

Watchdog

Multimedia

Multimedia

Accelerator

Video Port

Human Interface

LCD Controller

1.1 Conventions

This document uses the following conventions:

• OVERBAR

• Logic level one is a voltage that corresponds to Boolean true (1) state.

• Logic level zero is a voltage that corresponds to Boolean false (0) state.

•To set a bit or bits means to establish logic level one.

•To clear a bit or bits means to establish logic level zero.

•A signal is an electronic construct whose state conveys or changes in state convey information.

•A pin is an external physical connection. The same pin can be used to connect a number of signals.

• Asserted means that a discrete signal is in active logic state.

— Active low signals change from logic level one to logic level zero.

— Active high signals change from logic level zero to logic level one.

• Negated means that an asserted discrete signal changes logic state.

— Active low signals change from logic level zero to logic level one.

— Active high signals change from logic level one to logic level zero.

• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.

is used to indicate a signal that is active when pulled low: for example, RESET.

• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.

MC9328MXL Advance Information, Rev. 5

2 Freescale Semiconductor

Introduction

1.2 Features

To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the
following:

• ARM920T™ Microprocessor Core

• AHB to IP Bus Interfaces (AIPIs)

• External Interface Module (EIM)

• SDRAM Controller (SDRAMC)

• DPLL Clock and Power Control Module

• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)

• Two Serial Peripheral Interfaces (SPI1 and SPI2)

• Two General-Purpose 32-bit Counters/Timers

• Watchdog Timer

• Real-Time Clock/Sampling Timer (RTC)

• LCD Controller (LCDC)

• Pulse-Width Modulation (PWM) Module

• Universal Serial Bus (USB) Device

• Multimedia Card and Secure Digital (MMC/SD) Host Controller Module

• Memory Stick® Host Controller (MSHC)

• Direct Memory Access Controller (DMAC)

• Synchronous Serial Interface and Inter-IC Sound (SSI/I

2

• Inter-IC (I

C) Bus Module

2

S) Module

•Video Port

• General-Purpose I/O (GPIO) Ports

• Bootstrap Mode

• Multimedia Accelerator (MMA)

• Power Management Features

• Operating Voltage Range: 1.7 V to 1.98 V core, 1.7 V to 3.3V I/O

• 256-pin MAPBGA Package

• 225-pin MAPBGA Package

1.3 Target Applications

The MC9328MXL is targeted for advanced information appliances, smart phones, Web browsers, digital MP3
audio players, handheld computers, and messaging applications.

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 3

Introduction

1.4 Revision History

Table 1 provides revision history for this release. This history includes technical content revisions only and not
stylistic or grammatical changes.

Table 1. MC9328MXL Data Sheet Revision History Rev. 5

Revision Location Revision

Throughout Clarified instances where BCLK signal is burst clock.

Section 3.3, “Power Sequence
Requirements” on page 12

Added reference to AN2537.

1.5 Product Documentation

The following documents are required for a complete description of the MC9328MXL and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents are helpful when used in conjunction with this document.

ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)

ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)

ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)

EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)

MC9328MXL Product Brief (order number MC9328MXLP/D)

MC9328MXL Reference Manual (order number MC9328MXLRM/D)

The Motorola manuals are available on the Motorola Semiconductors Web site at
http://www.motorola.com/semiconductors. These documents may be downloaded directly from the Motorola Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.

MC9328MXL Advance Information, Rev. 5

4 Freescale Semiconductor

Introduction

1.6 Ordering Information

Table 2 provides ordering information for both the 256-lead mold array process ball grid array (MAPBGA)
package and the 225-lead BGA package.

Table 2. MC9328MXL Ordering Information

Package Type Frequency Temperature Solderball Type Order Number

256-lead MAPBGA 150 MHz

200 MHz

225-lead MAPBGA 150 MHz

200 MHz

-40OC to 85OC

0OC to 70OC

-30OC to 70OC

-40OC to 85OC

0OC to 70OC

O

C to 70OC

-30

Standard MC9328MXLCVH15(R2)

Pb-free MC9328MXLCVM15(R2)

Standard MC9328MXLVH20(R2)

Pb-free MC9328MXLVM20(R2)

Standard MC9328MXLDVH20(R2)

Pb-free MC9328MXLDVM20(R2)

Standard MC9328MXLCVF15(R2)

Pb-free MC9328MXLCVP15(R2)

Standard MC9328MXLVF20(R2)

Pb-free MC9328MXLVP20(R2)

Standard MC9328MXLDVF20(R2)

Pb-free MC9328MXLDVP20(R2)

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 5

Signals and Connections

2 Signals and Connections

Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.

Table 3. MC9328MXL Signal Descriptions

Signal Name Function/Notes

External Bus/Chip-Select (EIM)

A[24:0] Address bus signals

D[31:0] Data bus signals

EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].

EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16].

EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8].

EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].

OE Memory Output Enable—Active low output enables external data bus.

CS [5:0] Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the

Function Multiplexing Control Register (FMCR). By default CSD

ECB Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an

on-going burst sequence and initiate a new (long first access) burst sequence.

[1:0] is selected.

LBA Active low signal sent by a flash device causing the external burst device to latch the starting burst

address.

BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE

input signal by external DRAM.

DTACK DTACK signal—The external input data acknowledge signal. When using the external DTACK signal

as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is
not terminated by the external DTACK signal after 1022 clock counts have elapsed.

Bootstrap

BOOT [3:0] System Boot Mode Select—The operational system boot mode of the MC9328MXL upon system

reset is determined by the settings of these pins.

SDRAM Controller

SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].

These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.

SDIBA [3:0] SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A

[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.

MA [11:10] SDRAM address signals

MA [9:0] SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected

on SDRAM/SyncFlash cycles.

DQM [3:0] SDRAM data enable

CSD0 SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals

are selectable by programming the system control register.

MC9328MXL Advance Information, Rev. 5

6 Freescale Semiconductor

Signals and Connections

Table 3. MC9328MXL Signal Descriptions (Continued)

Signal Name Function/Notes

CSD1 SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are

selectable by programming the system control register. By default, CSD1 is selected, so it can be
used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins.

RAS SDRAM/SyncFlash Row Address Select signal

CAS SDRAM/SyncFlash Column Address Select signal

SDWE SDRAM/SyncFlash Write Enable signal

SDCKE0 SDRAM/SyncFlash Clock Enable 0

SDCKE1 SDRAM/SyncFlash Clock Enable 1

SDCLK SDRAM/SyncFlash Clock

RESET_SF SyncFlash Reset

Clocks and Resets

EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is

shut down.

XTAL16M Crystal output

EXTAL32K 32 kHz crystal input

XTAL32K 32 kHz crystal output

CLKO Clock Out signal selected from internal clock signals.

RESET_IN Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all

modules (except the reset module and the clock control module) are reset.

RESET_OUT Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from

the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally

generated by an external RC circuit designed to detect a power-up event.

JTAG

TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

TDO Serial Output for test instructions and data. Changes on the falling edge of TCK.

TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK.

TCK Test Clock to synchronize test logic and control register access through the JTAG port.

TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge

of TCK.

DMA

BIG_ENDIAN Big Endian—Input signal that determines the configuration of the external chip-select space. If it is

driven logic-high at reset, the external chip-select space will be configured to little endian. If it is
driven logic-low at reset, the external chip-select space will be configured to big endian.

DMA_REQ External DMA request pin.

ETM

ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 7

Signals and Connections

Table 3. MC9328MXL Signal Descriptions (Continued)

Signal Name Function/Notes

ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.

ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM

mode.

ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].

ETMTRACEPKT [7:0] are selected in ETM mode.

CMOS Sensor Interface

CSI_D [7:0] Sensor port data

CSI_MCLK Sensor port master clock

CSI_VSYNC Sensor port vertical sync

CSI_HSYNC Sensor port horizontal sync

CSI_PIXCLK Sensor port data latch clock

LCD Controller

LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.

FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for the gate

driver (dedicated signal SPS for Sharp panel HR-TFT).

LP/HSYNC Line pulse or H sync

LSCLK Shift clock

ACD/OE Alternate crystal direction/output enable.

CONTRAST This signal is used to control the LCD bias voltage as contrast control.

SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).

PS Control signal output for source driver (Sharp panel dedicated signal).

CLS Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated

signal).

REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal).

SPI 1 and 2

SPI1_MOSI Master Out/Slave In

SPI1_MISO Slave In/Master Out

SPI1_SS Slave Select (Selectable polarity)

SPI1_SCLK Serial Clock

SPI1_SPI_RDY Serial Data Ready

SPI2_TXD SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as a primary

or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters
in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.

SPI2_RXD SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a primary or

alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.

MC9328MXL Advance Information, Rev. 5

8 Freescale Semiconductor

Signals and Connections

Table 3. MC9328MXL Signal Descriptions (Continued)

Signal Name Function/Notes

SPI2_SS SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary or

alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.

SPI2_SCLK SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary or

alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.

General Purpose Timers

TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers

simultaneously.

TMR2OUT Timer 2 Output

USB Device

USBD_VMO USB Minus Output

USBD_VPO USB Plus Output

USBD_VM USB Minus Input

USBD_VP USB Plus Input

USBD_SUSPND USB Suspend Output

USBD_RCV USB Receive Data

USBD_OE USB OE

USBD_AFE USB Analog Front End Enable

Secure Digital Interface

SD_CMD SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-

up enable register, a 4.7K–69K external pull up resistor must be added.

SD_CLK MMC Output Clock

SD_DAT [3:0] Data—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable

register, a 50K–69K external pull up resistor must be added.

Memory Stick Interface

MS_BS Memory Stick Bus State (Output)—Serial bus control signal

MS_SDIO Memory Stick Serial Data (Input/Output)

MS_SCLKO Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider

MS_SCLKI Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is only for test

purposes, not for use in application mode.

MS_PI0 General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect

MS_PI1 General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect

UARTs – IrDA/Auto-Bauding

UART1_RXD Receive Data

UART1_TXD Transmit Data

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 9

Signals and Connections

Table 3. MC9328MXL Signal Descriptions (Continued)

Signal Name Function/Notes

UART1_RTS Request to Send

UART1_CTS Clear to Send

UART2_RXD Receive Data

UART2_TXD Transmit Data

UART2_RTS Request to Send

UART2_CTS Clear to Send

UART2_DSR Data Set Ready

UART2_RI Ring Indicator

UART2_DCD Data Carrier Detect

UART2_DTR Data Terminal Ready

Serial Audio Port – SSI (configurable to I2S protocol)

SSI_TXDAT Transmit Data

SSI_RXDAT Receive Data

SSI_TXCLK Transmit Serial Clock

SSI_RXCLK Receive Serial Clock

SSI_TXFS Transmit Frame Sync

SSI_RXFS Receive Frame Sync

I2C

I2C_SCL I2C Clock

I2C_SDA I2C Data

PWM

PWMO PWM Output

Digital Supply Pins

NVDD Digital Supply for the I/O pins

NVSS Digital Ground for the I/O pins

Supply Pins – Analog Modules

AVDD Supply for analog blocks

AVSS Quiet ground for analog blocks

Internal Power Supply

QVDD Power supply pins for silicon internal circuitry

QVSS Ground pins for silicon internal circuitry

MC9328MXL Advance Information, Rev. 5

10 Freescale Semiconductor

Specifications

Table 3. MC9328MXL Signal Descriptions (Continued)

Signal Name Function/Notes

Substrate Supply Pins

SVDD Supply routed through substrate of package; not to be bonded

SGND Ground routed through substrate of package; not to be bonded

3 Specifications

This section contains the electrical specifications and timing diagrams for the MC9328MXL processor.

3.1 Maximum Ratings

Table 4 provides information on maximum ratings.

Table 4. Maximum Ratings

Rating Symbol Minimum Maximum Unit

Supply voltage V

Maximum operating temperature range
MC9328MXLVH20/MC9328MXLVM20/
MC9328MXLVF20/MC9328MXLVP20

Maximum operating temperature range
MC9328MXLDVH20/MC9328MXLDVM20/
MC9328MXLDVF20/MC9328MXLDVP20

Maximum operating temperature range
MC9328MXLCVH15/MC9328MXLCVM15/
MC9328MXLCVF15/MC9328MXLCVP15

ESD at human body model (HBM) VESD_HBM – 2000 V

ESD at machine model (MM) VESD_MM – 100 V

Latch-up current ILatchup – 200 mA

Storage temperature Test -55 150 °C

Power Consumption Pmax

1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from
the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.

2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core
running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at

2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.

dd

T

A

T

A

T

A

-0.3 3.3 V

070°C

-30 70 °C

-40 85 °C

800

1

1300

2

mW

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 11

Specifications

3.2 Recommended Operating Range

Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MXL has multiple pairs
of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD
and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/
O pads. This design allows different peripheral supply voltage levels in a system.

Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the
AVDD pins from other VDD pins.

For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.

Table 5. Recommended Operating Range

Rating Symbol Minimum Maximum Unit

I/O supply voltage (if using MSHC, SPI, BTA, USBd, LCD and CSI
which are only 3 V interfaces)

I/O supply voltage (if not using the peripherals listed above) NVDD 1.70 3.30 V

Internal supply voltage (Core = 150 MHz) QVDD 1.70 1.90 V

Internal supply voltage (Core = 200 MHz) QVDD 1.80 2.00 V

Analog supply voltage AVDD 1.70 3.30 V

NVDD 2.70 3.30 V

3.3 Power Sequence Requirements

For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of
application note AN2537 on the i.MX website page.

3.4 DC Electrical Characteristics

Table 6 contains both maximum and minimum DC characteristics of the MC9328MXL.

Table 6. Maximum and Minimum DC Characteristics

Number or

Symbol

Iop Full running operating current at 1.8V for QVDD, 3.3V for

NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4
decoding playback from external memory card to both
external SSI audio decoder and TFT display panel, and OS
with MMU enabled memory system is running on external
SDRAM).

Parameter Min Typical Max Unit

– QVDD at

1.8v = 120mA;

NVDD+AVDD at

3.0v = 30mA

–mA

Sidd

Sidd

Sidd

12 Freescale Semiconductor

Standby current

1

(Core = 150 MHz, QVDD = 1.8V, temp = 25°C)

Standby current

2

(Core = 150 MHz, QVDD = 1.8V, temp = 55

Standby current

3

(Core = 150 MHz, QVDD = 2.0V, temp = 25

MC9328MXL Advance Information, Rev. 5

–25 –µA

–45 –µA

°C)

–35 –µA

°C)

Table 6. Maximum and Minimum DC Characteristics (Continued)

Specifications

Number or

Symbol

Sidd

4

V

IH

V

IL

V

OH

V

OL

I

IL

I

IH

I

OH

I

OL

I

OZ

Parameter Min Typical Max Unit

Standby current

–60 –µA

(Core = 150 MHz, QVDD = 2.0V, temp = 55°C)

Input high voltage 0.7V

DD

–Vdd+0.2V

Input low voltage – – 0.4 V

Output high voltage (IOH= 2.0 mA) 0.7V

DD

–VddV

Output low voltage (IOL= -2.5 mA) – – 0.4 V

Input low leakage current

= GND, no pull-up or pull-down)

(V

IN

Input high leakage current
(V

IN=VDD

, no pull-up or pull-down)

Output high current

=0.8VDD, VDD=1.8V)

(V

OH

Output low current

=0.4V, VDD=1.8V)

(V

OL

Output leakage current
(V

out=VDD

, output is tri-stated)

––±1µA

––±1µA

––4.0mA

-4.0 – – mA

––±5µA

C

i

C

o

Input capacitance – – 5 pF

Output capacitance‘ – – 5 pF

3.5 AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system
operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage
from V

DD min

to V

DD max

under an operating temperature from TL to TH. All timing is measured at 30 pF loading.

Table 7. Tristate Signal Timing

Pin Parameter Minimum Maximum Unit

TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z – 20.8 ns

Table 8. 32k/16M Oscillator Signal Timing

Parameter Minimum RMS Maximum Unit

EXTAL32k input jitter (peak to peak) – 5 20 ns

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 13

Specifications

Table 8. 32k/16M Oscillator Signal Timing (Continued)

Parameter Minimum RMS Maximum Unit

EXTAL32k startup time 800 – – ms

EXTAL16M input jitter (peak to peak) – TBD TBD –

EXTAL16M startup time TBD – – –

3.6 Embedded Trace Macrocell

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:

• 32-bit data field

• 7-bit address field

• A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
in Figure 2.

TRACECLK

TRACECLK

(Half-Rate Clocking Mode)

Output Trace Port

3a

2a

2b

3b

Valid Data

4a

1

Valid Data

4b

Figure 2. Trace Port Timing Diagram

Table 9. Trace Port Timing Diagram Parameter Table

Ref
No.

1 CLK frequency 0 85 0 100 MHz

2a Clock high time 1.3 – 2 – ns

Parameter

1.8V ± 0.10V 3.0V ± 0.30V
Unit

Minimum Maximum Minimum Maximum

2b Clock low time 3 – 2 – ns

MC9328MXL Advance Information, Rev. 5

14 Freescale Semiconductor

Table 9. Trace Port Timing Diagram Parameter Table (Continued)

Specifications

Ref
No.

3a Clock rise time – 4 – 3 ns

3b Clock fall time – 3 – 3 ns

4a Output hold time 2.28 – 2 – ns

4b Output setup time 3.42 – 3 – ns

Parameter

1.8V ± 0.10V 3.0V ± 0.30V
Unit

Minimum Maximum Minimum Maximum

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 15

Specifications

3.7 DPLL Timing Specifications

Parameters of the DPLL are given in Table 10. In this table, T
pre-divider and T

is the output double clock period.

dck

is a reference clock period after the

ref

Table 10. DPLL Specifications

Parameter Test Conditions Minimum Typical Maximum Unit

Reference clock freq range Vcc = 1.8V 5 – 100 MHz

Pre-divider output clock
freq range

Double clock freq range Vcc = 1.8V 80 – 220 MHz

Pre-divider factor (PD) – 1 – 16 –

Total multiplication factor (MF) Includes both integer

MF integer part – 5 – 15 –

MF numerator Should be less than the

MF denominator – 1 – 1023 –

Pre-multiplier lock-in time – – – 312.5

Vcc = 1.8V 5 – 30 MHz

5–15–

and fractional parts

0 – 1022 –

denominator

µsec

Freq lock-in time after
full reset

Freq lock-in time after
partial reset

Phase lock-in time after
full reset

Phase lock-in time after
partial reset

Freq jitter (p-p) – – 0.005

Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V – 1.0

Power supply voltage – 1.7 – 2.5 V

Power dissipation FOL mode, integer MF,

FOL mode for non-integer MF
(does not include pre-multi lock-in
time)

FOL mode for non-integer MF
(does not include pre-multi lock-in
time)

FPL mode and integer MF (does
not include pre-multi lock-in time)

FPL mode and integer MF (does
not include pre-multi lock-in time)

f

= 200 MHz, Vcc = 1.8V

dck

250 280

(56 µs)

220 250

(50 µs)

300 350

(70 µs)

270 320

(64 µs)

(0.01%)

(10%)

––4mW

300 T

270 T

400 T

370 T

0.01 2•T

1.5 ns

ref

ref

ref

ref

dck

MC9328MXL Advance Information, Rev. 5

16 Freescale Semiconductor

Specifications

3.8 Reset Module

The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.

NOTE:

Be aware that NVDD must ramp up to at least 1.8V before QVDD is
powered up to prevent forward biasing.

90% AVDD

1

POR

10% AVDD

RESET_POR

RESET_DRAM

HRESET

RESET_OUT

CLK32

HCLK

2

Exact 300ms

3

Figure 3. Timing Relationship with POR

7 cycles @ CLK32

4

14 cycles @ CLK32

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 17

Specifications

RESET_IN

5

HRESET

RESET_OUT

CLK32

Ref
No.

HCLK

6

Figure 4. Timing Relationship with RESET_IN

Table 11. Reset Module Timing Parameter Table

1.8V ± 0.10V 3.0V ± 0.30V

Parameter

Min Max Min Max

14 cycles @ CLK32

4

Unit

1 Width of input POWER_ON_RESET

2 Width of internal POWER_ON_RESET

note

1

–

300 300 300 300 ms

note

1

––

(CLK32 at 32 kHz)

3 7K to 32K-cycle stretcher for SDRAM reset 7 7 7 7 Cycles of

CLK32

4 14K to 32K-cycle stretcher for internal system reset

HRESERT

and output reset at pin RESET_OUT

5 Width of external hard-reset RESET_IN

14 14 14 14 Cycles of

CLK32

4 – 4 – Cycles of

CLK32

6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of

CLK32

1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should
allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence.
Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have
developed a working knowledge of start-up time of their crystals. Typically, start-up times range from
400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should
be ignored in calculating timing for the start-up process.

MC9328MXL Advance Information, Rev. 5

18 Freescale Semiconductor

Specifications

3.9 External Interface Module

The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 12 on page 20 defines the parameters of signals.

(HCLK) Bus Clock

1a 1b

Address

Chip-select

Read (Write

OE

(rising edge)

(falling edge)

OE

EB

(rising edge)

(falling edge)

EB

(negated falling edge)

LBA

LBA

(negated rising edge)

Burst Clock (rising edge)

2a 2b

3b3a

)

4a 4b

4c 4d

5a 5b

5c 5d

6a

6a

7a 7b

7c

6c

7d

6b

Burst Clock (falling edge)

8b

Read Data

9a

8a

9b

Write Data (negated falling)

9a

9c

Write Data (negated rising)

DTACK

10a

10a

Figure 5. EIM Bus Timing Diagram

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 19

Specifications

Ref No. Parameter

1a Clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns

1b Clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns

2a Clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns

2b Clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns

Table 12. EIM Bus Timing Parameter Table

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Min Typical Max Min Typical Max

3a Clock fall to Read (Write

3b Clock fall to Read (Write

4a Clock

4b Clock

4c Clock

4d Clock

5a Clock

5b Clock

5c Clock

5d Clock

6a Clock

6b Clock

6c Clock

7a Clock

1

rise to Output Enable Valid

1

rise to Output Enable Invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns

1

fall to Output Enable Valid 2.38 2.69 7.04 2.3 2.6 6.8 ns

1

fall to Output Enable Invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns

1

rise to Enable Bytes Valid 1.91 2.52 5.54 1.9 2.5 5.5 ns

1

rise to Enable Bytes Invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns

1

fall to Enable Bytes Valid 1.97 2.59 5.69 1.9 2.5 5.5 ns

1

fall to Enable Bytes Invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns

1

fall to Load Burst Address Valid 2.07 2.79 6.73 2.0 2.7 6.5 ns

1

fall to Load Burst Address Invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns

1

rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns

1

rise to Burst Clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns

) Valid 1.35 2.79 6.52 1.3 2.7 6.3 ns

) Invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns

2.32 2.62 6.85 2.3 2.6 6.8 ns

7b Clock

7c Clock

7d Clock

1

rise to Burst Clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns

1

fall to Burst Clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns

1

fall to Burst Clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns

8a Read Data setup time 5.54 – – 5.5 – – ns

8b Read Data hold time 0 – – 0 – – ns

9a Clock

9b Clock

1

rise to Write Data Valid 1.81 2.72 6.85 1.8 2.7 6.8 ns

1

fall to Write Data Invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns

9c Clock1 rise to Write Data Invalid 1.63 – – 1.62 – – ns

10a DTACK

setup time 2.52 – – 2.5 – – ns

1. Clock refers to the system clock signal, HCLK, generated from the System PLL

MC9328MXL Advance Information, Rev. 5

20 Freescale Semiconductor

Specifications

3.9.1 DTACK Signal Description

The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK

signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.

3.9.2 DTACK Signal Timing

Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 13.

HCLK

CS5

3

RW

1

OE

5

EXT_DTACK

2

INT_DTACK

Ref
No.

1CS5

2 External DTACK

3CS5

4 External DTACK

5OE

asserted to OE asserted –T–Tns

asserted

pulse width 3T – 3T – ns

negated

negated after CS5 is negated 0 4.5 0 4 ns

4

Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0

Table 13. Access Cycle Timing Parameters

1.8V ± 0.10V 3.0V ± 0.30V

Characteristic

Min Max Min Max

input setup from CS5

input hold after CS5 is

0–0–ns

0 1.5T 0 1.5T ns

Unit

Note:

1. n is the number of wait states in the current memory access cycle. The max n is 1022.

2. T is the system clock period (system clock is 96 MHz).

3. The external DTACK

Freescale Semiconductor 21

input requirement is eliminated when CS5 is programmed to use internal wait state.

MC9328MXL Advance Information, Rev. 5

Specifications

HCLK

CS5

RW

OE

EXT_DTACK (WAIT)

INT_DTACK

1

Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1

Table 14. Access Cycle Timing Parameters

Ref
No.

1 External DTACK

Characteristic

input setup from CS5

asserted

Note:

1. n is the number of wait states in the current memory access cycle. The max n is 1022.

2. T is the system clock period (system clock is 96 MHz).

3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

1.8V ± 0.10V 3.0V ± 0.30V

Min Max Min Max

0–0–ns

Unit

MC9328MXL Advance Information, Rev. 5

22 Freescale Semiconductor

3.9.3 EIM External Bus Timing

The timing diagrams in this section show the timing of accesses to memory or a peripheral.

hclk

hsel_weim_cs[0]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

weim_r/w

weim_lba

Seq/Nonseq

Read

V1

Last Valid Data

Last Valid Address

V1

V1

Read

weim_oe

weim_eb (EBC=0)

weim_eb

(EBC=1)

weim_data_in

V1

Figure 8. WSC = 1, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 23

Specifications

hsel_weim_cs[0]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[0]

weim_r/w

Nonseq

Write

V1

Last Valid Data

Last Valid Address

Write Data (V1) Unknown

Last Valid Data

V1

Write

weim_lba

weim_oe

weim_eb

weim_data_out

Last Valid Data Write Data (V1)

Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

24 Freescale Semiconductor

hclk

hsel_weim_cs[0]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[0]

weim_r/w

weim_lba

Nonseq

Read

V1

Last Valid Data

Address V1

Read

V1 Word

Address V1 + 2Last Valid Addr

weim_oe

weim_eb (EBC=0)

weim_eb (EBC=1)

weim_data_in

1/2 Half Word 2/2 Half Word

Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 25

Specifications

hsel_weim_cs[0]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[0]

weim_r/w

Nonseq

Write

V1

Last Valid Data

Write Data (V1 Word)

Last Valid Data

Address V1

Address V1 + 2Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_data_out

1/2 Half Word 2/2 Half Word

Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

26 Freescale Semiconductor

hclk

hsel_weim_cs[3]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

[3]

weim_cs

weim_r/w

weim_lba

Nonseq

Read

V1

Last Valid Data

Address V1

V1 Word

Address V1 + 2Last Valid Addr

Read

weim_oe

weim_eb (EBC=0)

weim_eb

(EBC=1)

weim_data_in

1/2 Half Word 2/2 Half Word

Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 27

Specifications

hsel_weim_cs[3]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[3]

weim_r/w

Nonseq

Write

V1

Last Valid

Data

Write Data (V1 Word)

Address V1

Last Valid Data

Address V1 + 2Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_data_out]

Last Valid Data

1/2 Half Word 2/2 Half Word

Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

28 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

weim_r/w

weim_lba

[2]

Nonseq

Read

V1

Last Valid Data

Address V1

V1 Word

Address V1 + 2Last Valid Addr

Read

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

1/2 Half Word 2/2 Half Word

Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 29

Specifications

hsel_weim_cs[2]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

Nonseq

Write

V1

Last Valid

Data

Address V1

Write Data (V1 Word)

Last Valid Data

Address V1 + 2Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_data_out

Last Valid Data

1/2 Half Word 2/2 Half Word

Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

30 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

weim_lba

Nonseq

Read

V1

Last Valid Data

Address V1

V1 Word

Address V1 + 2Last Valid Addr

Read

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

1/2 Half Word 2/2 Half Word

Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 31

Specifications

hsel_weim_cs[2]

hclk

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

weim_lba

Nonseq

Read

V1

Last Valid Data

Address V1

V1 Word

Address V1 + 2Last Valid Addr

Read

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

1/2 Half Word 2/2 Half Word

Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

32 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

Nonseq

Write

V1

Last Valid

Data

Address V1

Write Data (V1 Word)

Last Valid Data

Write

Unknown

Address V1 + 2Last Valid Addr

weim_lba

weim_oe

weim_eb

weim_data_out

Last Valid Data

1/2 Half Word 2/2 Half Word

Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 33

Specifications

hsel_weim_cs[2]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

Nonseq

Write

V1

Last Valid

Data

Write Data (V1 Word)

Last Valid Data

Address V1

Unknown

Address V1 + 2Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_data_out

Last Valid Data

1/2 Half Word 2/2 Half Word

Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

34 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

Nonseq

Read

V1

Last Valid Data

Last Valid Data Read Data

Read

Nonseq

Write

V8

Address V1

Write Data

Address V8Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_eb

(EBC=0)

(EBC=1)

weim_data_in

weim_data_out

Read Data

Last Valid Data Write Data

Figure 20. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 35

Specifications

hsel_weim_cs[2]

Read WriteIdle

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

Nonseq

Read

V1

Last Valid Data

Last Valid Data

Read

Nonseq

Write

V8

Write Data

Read Data

Address V1 Address V8Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_eb

(EBC=0)

(EBC=1)

weim_data_in

weim_data_out

Read Data

Last Valid Data Write Data

Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

36 Freescale Semiconductor

hclk

hsel_weim_cs[4]

Specifications

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

weim_r/w

Nonseq

Write

V1

Last Valid

Data

Write Data (Word)

Last Valid Data

Address V1 Address V1 + 2Last Valid Addr

Write

weim_lba

weim_oe

weim_eb

weim_data_out

Last Valid Data

Write Data (1/2 Half Word) Write Data (2/2 Half Word)

Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 37

Specifications

hsel_weim_cs[4]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[4]

weim_r/w

Nonseq

Read

V1

Nonseq

Write

V8

Last Valid Data

Last Valid Data Read Data

Address V1 Address V8Last Valid Addr

Read

Write Data

Write

weim_eb

weim_eb

weim_data_in

weim_lba

weim_oe

(EBC=0)

(EBC=1)

Read Data

Write DataLast Valid Dataweim_data_out

Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

38 Freescale Semiconductor

hclk

hsel_weim_cs[4]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[4]

weim_r/w

weim_lba

Nonseq

Read

V1

Last Valid Data

Idle

Seq

Read

V2

Address V1

Read

Read Data (V1)

CNC

Read Data (V2)

Address V2Last Valid

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

Read Data

Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = 0, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

Read Data

Freescale Semiconductor 39

Specifications

hsel_weim_cs[4]

hclk

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[4]

weim_r/w

Nonseq

Read

V1

Last Valid Data

Last Valid Data

Idle

Read

Nonseq

Write

V8

Write Data

Read Data

Address V1 Address V8Last Valid Addr

CNC

Write

weim_lba

weim_oe

weim_eb

weim_eb

(EBC=0)

(EBC=1)

weim_data_in

weim_data_out

Read Data

Last Valid Data Write Data

Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

40 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr]

weim_cs

[2]

weim_r/w

weim_lba

Nonseq Nonse

Read Read

V1 V5

Address V1Last Valid Addr Address V5

Idle

Read

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

weim_ecb

V1 Word V2 Word V5 Word V6 Word

Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 41

Specifications

hsel_weim_cs[2]

hclk

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

weim_r/w

weim_lba

Nonseq Seq

Read

V1

Last Valid Data V1 Word V2 Word V3 Word V4 Word

[2]

Seq Seq

Read Read Read

V2 V3 V4

Address V1Last Valid Addr

Read

Idle

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

weim_ecb

V1 Word V2 Word V3 Word V4 Word

Figure 27. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD

MC9328MXL Advance Information, Rev. 5

42 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

weim_lba

Nonseq

Read

V1

Last Valid Data V1 Word V2 Word

Address V1Last Valid

Seq

Read

V2

Address V2

Read

Idle

weim_eb

weim_eb

weim_data_in

weim_oe

(EBC=0)

(EBC=1)

weim_ecb

V1 1/2 V1 2/2 V2 1/2 V2 2/2

Figure 28. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 43

Specifications

hsel_weim_cs[2]

hclk

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

weim_lba

Non
seq

Read

V1

Last

Seq

Read

V2

Last Valid Data V1 Word V2 Word

Address V1

Read

Idle

weim_oe

weim_eb

weim_eb

(EBC=0)

(EBC=1)

weim_ecb

weim_data_in

V1 1/2 V1 2/2 V2 1/2 V2 2/2

Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

44 Freescale Semiconductor

hclk

hsel_weim_cs[2]

Specifications

htrans

hwrite

haddr

hready

weim_hrdata

weim_hready

weim_bclk

weim_addr

weim_cs

[2]

weim_r/w

weim_lba

Non
seq

Read

V1

Last

Seq

Read

V2

Last Valid Data V1 Word V2 Word

Address V1

Read

Idle

weim_oe

weim_eb

weim_eb

(EBC=0)

(EBC=1)

weim_ecb

weim_data_in

V1 1/2 V1 2/2 V2 1/2 V2 2/2

Figure 30. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 45

Specifications

3.10 SPI Timing Diagrams

To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as
a master, two control signals are used for data transfer rate control: the SS
SPI_RDY

signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2
Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for
either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1
Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as
well as to increment the data FIFO. Figure 31 through Figure 35 show the timing relationship of the master
SPI using different triggering mechanisms.

signal (output) and the

SPIRDY

SCLK, MOSI, MISO

Figure 31. Master SPI Timing Diagram Using SPI_RDY Edge Trigger

SS

SPIRDY

SCLK, MOSI, MISO

Figure 32. Master SPI Timing Diagram Using SPI_RDY

SS

2

1

3

5

4

Level Trigger

(output)

SS

SCLK, MOSI, MISO

Figure 33. Master SPI Timing Diagram Ignore SPI_RDY

SS (input)

SCLK, MOSI, MISO

Level Trigger

Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT

MC9328MXL Advance Information, Rev. 5

46 Freescale Semiconductor

SS

Specifications

(input)

6

SCLK, MOSI, MISO

Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge

Table 15. Timing Parameter Table for Figure 31 through Figure 35

Ref
No.

1 SPI_RDY to SS output low

2SS

edge

3 Last SCLK edge to SS

high

4SS

low

5SS

Parameter

output low to first SCLK

output

output high to SPI_RDY

output pulse width Tsclk +

7

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

1

2T

3 • Tsclk

–

2

–

1

2T

3 • Tsclk

–ns

2

–ns

Unit

2 • Tsclk – 2 • Tsclk – ns

0–0–ns

WAIT

3

WAIT

3

– Tsclk +

–ns

6SS

input low to first SCLK

T–T–ns

edge

7SS

input pulse width T – T – ns

1. T = CSPI system clock period (PERCLK2).

2. Tsclk = Period of SCLK.

3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.

3.11 LCD Controller

This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.

LSCLK

LD[15:0]

1

Figure 36. SCLK to LD Timing Diagram

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 47

Specifications

Table 16. LCDC SCLK Timing Parameter Table

1.8V ± 0.10V 3.0V ± 0.30V

Ref
No. Parameter

1 SCLK to LD valid – 2 – 2 ns

T1

Minimum Maximum Minimum Maximum

Display regionNon-display region

T3

T4

Unit

VSYN

HSYN

OE

LD[15:0]

HSYN

SCLK

OE

LD[15:0]

VSYN

T2

Line Y

T5

T6

T8

(1,1)

T9 T10

(1,2)

XMAX

Line 1 Line Y

T7

(1,X)

Figure 37. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing

Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing

Symbol Description Minimum Corresponding Register Value Unit

T1 End of OE to beginning of VSYN T5+T6

+T7+T9

T2 HSYN period XMAX+5 XMAX+T5+T6+T7+T9+T10 Ts

T3 VSYN pulse width T2 VWIDTH·(T2) Ts

T4 End of VSYN to beginning of OE 2 VWAIT2·(T2) Ts

T5 HSYN pulse width 1 HWIDTH+1 Ts

T6 End of HSYN to beginning to T9 1 HWAIT2+1 Ts

MC9328MXL Advance Information, Rev. 5

48 Freescale Semiconductor

(VWAIT1·T2)+T5+T6+T7+T9 Ts

Specifications

Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)

Symbol Description Minimum Corresponding Register Value Unit

T7 End of OE to beginning of HSYN 1 HWAIT1+1 Ts

T8 SCLK to valid LD data -3 3 ns

T9 End of HSYN idle2 to VSYN edge

22Ts

(for non-display region)

T9 End of HSYN idle2 to VSYN edge

11Ts

(for Display region)

T10 VSYN to OE active (Sharp = 0)

11Ts

when VWAIT2 = 0

T10 VSYN to OE active (Sharp = 1)

22Ts

when VWAIT2 = 0

Note:

• Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.

• VSYN, HSYN and OE can be programmed as active high or active low. In Figure 37, all 3 signals are active low.

• The polarity of SCLK and LD[15:0] can also be programmed.

• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK
is always active.

• For T9 non-display region, VSYN is non-active. It is used as an reference.

• XMAX is defined in pixels.

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 49

Specifications

3.12 Multimedia Card/Secure Digital Host Controller

The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).

Bus Clock

5a

CMD_DAT Input

CMD_DAT Output

Valid Data

Figure 38. Chip-Select Read Cycle Timing Diagram

Table 18. SDHC Bus Timing Parameter Table

Ref
No.

1 CLK frequency at Data transfer Mode

1

—10/30 cards

(PP)

2 CLK frequency at Identification Mode

Parameter

3a

1

2

3b

4a

Valid Data

7

Valid DataValid Data

6a

1.8V ± 0.10V 3.0 ± 0.30V

Minimum Maximum Minimum Maximum

0 25/5 0 25/5 MHz

2

0 400 0 400 kHz

4b

5b

6b

Unit

3a Clock high time1—10/30 cards 6/33 – 10/50 – ns

3b Clock low time

4a Clock fall time

4b Clock rise time1—10/30 cards – 14/67

5a Input hold time

1

—10/30 cards 15/75 – 10/50 – ns

1

—10/30 cards – 10/50

(5.00)

3

– 10/50 ns

– 10/50 ns

3

(6.67)

3

—10/30 cards

5.7/5.7 – 5/5 – ns

5b Input setup time3—10/30 cards 5.7/5.7 – 5/5 – ns

6a Output hold time

6b Output setup time

7 Output delay time

1. C

2. C

3. C

≤ 100 pF / 250 pF (10/30 cards)

L

≤ 250 pF (21 cards)

L

≤ 25 pF (1 card)

L

3

—10/30 cards 5.7/5.7 – 5/5 – ns

3

—10/30 cards 5.7/5.7 – 5/5 – ns

3

0 16 0 14 ns

MC9328MXL Advance Information, Rev. 5

50 Freescale Semiconductor

Specifications

3.12.1 Command Response Timing on MMC/SD Bus

The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly N
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 39. The symbols for Figure 39 through Figure 43
are defined in Table 19.

Table 19. State Signal Parameters for Figure 39 through Figure 43

Card Active Host Active

Symbol Definition Symbol Definition

Z High impedance state S Start bit (0)

D Data bits T Transmitter bit

* Repetition P One-cycle pull-up (1)

CRC Cyclic redundancy check bits (7 bits) E End bit (1)

Host Command

clock cycles. For the card address assignment,

ID

(Host = 1, Card = 0)

N

cycles

ID

CID/OCR

CMD

CMD

Content

S T E Z Z S T

Host Command

Content

S T E Z Z S T

CRC

CRC

******

N

CR

******

cycles

Content

Identification Timing

CID/OCR

Content

SET_RCA Timing

Z Z

Z Z

Z

Z

Figure 39. Timing Diagrams at Identification Mode

After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 40, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods N

and NCC.

RC

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 51

Specifications

Host Command

N

CR

cycles

Response

CMD

CMD

CMD

Content

S T E Z Z P P S T

Response

Content

S T E Z Z S T

Host Command

Content

S T E Z Z S T

CRC

CRC

Timing response end to next CMD start (data transfer mode)

CRC

******

Command response timing (data transfer mode)

N

cycles

RC

******

N

cycles

CC

******

Timing of command sequences (all modes)

Content

Host Command

Content

Host Command

Content

CRC

CRC

CRC

E Z Z

E Z Z

E Z Z

Z

Z

Z

Figure 40. Timing Diagrams at Data Transfer Mode

Figure 41 on page 53 shows basic read operation timing. In a read operation, the sequence starts with a
single block read command (which specifies the start address in the argument field). The response is sent
on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay N

AC

,
beginning from the last bit of the read command. If the system is in multiple block read mode, the card
sends a continuous flow of data blocks with distance N

until the card sees a stop transmission command.

AC

The data stops two clock cycles after the end bit of the stop command.

MC9328MXL Advance Information, Rev. 5

52 Freescale Semiconductor

Host Command

N

CR

Specifications

cycles

Response

CMD

DAT

Host Command

CMD

DAT

Content

S T E Z Z P P S T

Z****Z

CMD

Content

S T E Z Z P P S T

N

CRC

Z Z P P S D

Host Command

Content

S T E Z Z P P S T

Z****Z

cycles

CR

******

******

NAC cycles

CRC

Z Z P P S D

NAC cycles

CRC

******

******

Timing of single block read

Response

Content

D D D P

Read Data

N

cycles

CR

CRC

*****

******

Content

D D D

E Z

Content

Read Data

*****

cycles

N

AC

Response

CRC

E Z

*****

P S DD DD

Read Data

Timing of multiple block read

CRC

E Z

*****

NST

DAT

D D DD D DD D Z

*****

Valid Read Data

ZZE

Timing of stop command
(CMD12, data transfer mode)

*****

Figure 41. Timing Diagrams at Data Read

Figure 42 shows the basic write operation timing. As with the read operation, after the card response, the
data transfer starts after N

cycles. The data is suffixed with CRC check bits to allow the card to check

WR

for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If
there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC
status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple
block mode, with the flow terminated by a stop transmission command.

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 53

Specifications

P P P

******

CRC

Response

Content

L*L

Busy

X X X X X XX ZX XXE Z ZP P S

Status

X X X X X X

CRC status

L*L

Busy

E Z Z S E S E Z

CRC

CRC

Status

E Z Z S E S E Z

CRC

Content

X X X X X X

E Z Z X X X X X X XX X XZ

CRC

Content

Content

Write Data

Content

cycles

E Z Z P

Z Z Z P P S

Z Z Z

N

WR

******

CRC status

Write Data

cycles

WR

N

cycles

N

CR

Host Command

******

E Z Z P P S T

CRC

Content

S T

CMD

Status

E Z Z S E Z P P S

Z****Z

Z****Z

CRC

Content

Timing of the block write command

DAT

DAT

E Z Z P P P P

CMD

Z Z P P S

DAT

Figure 42. Timing Diagrams at Data Write

X X X X X X

E Z Z X X Z P P S

CRC

Content

Z Z P P S

DAT

CRC status

Write Data

cycles

WR

N

Timing of the multiple block write command

MC9328MXL Advance Information, Rev. 5

54 Freescale Semiconductor

Specifications

The stop transmission command may occur when the card is in different states. Figure 43 shows the
different scenarios on the bus.

E

CRC

Content

Host Command

S T

Stop transmission during CRC status transfer

Z

E Z Z

CRC

Stop transmission during data transfer

from the host.

from the card.

Stop transmission received after last data block.

Card becomes busy programming.

Stop transmission received after last data block.

Card becomes busy programming.

cycles

CR

N

Content

Card Response

******

CRC

Content

Host Command

S T E Z Z P P S T

CMD

******

D DD DD D Z Z Z ZD DD DD DD E Z Z S L Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE

DAT

******

Busy (Card is programming)

E

CRC

Write Data

D DD DD D Z Z Z ZD Z Z S Z Z S L Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE

DAT

******

S L Z Z Z Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE

DAT

******

Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z S L Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z Z Z Z Z Z Z ZE

DAT

Figure 43. Stop Transmission During Different Scenarios

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 55

Specifications

Table 20. Timing Values for Figure 39 through Figure 43

Parameter Symbol Minimum Maximum Unit Parameter

MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum
(VIL)

Command response cycle NCR 2 64 Clock

cycles

Identification response cycle NID 5 5 Clock

cycles

Access time delay cycle NAC 2 TAAC + NSAC Clock

cycles

Command read cycle NRC 8 – Clock

cycles

Command-command cycle NCC 8 – Clock

cycles

Command write cycle NWR 2 – Clock

cycles

Stop transmission cycle NST 2 2 Clock

cycles

TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register
bit[111:104]

MMC/SD bus clock, CLK
(All values are referred to
minimum (VIH) and
maximum (VIL)

Command response cycle

Identification response
cycle

Access time delay cycle

Command read cycle

Command-command cycle

Command write cycle

Stop transmission cycle

TAAC: Data read access
time -1 defined in CSD
register bit[119:112]
NSAC: Data read access
time -2 in CLK cycles
(NSAC·100) defined in
CSD register bit[111:104]

3.12.2 SDIO-IRQ and ReadWait Service Handling

In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).

In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt
Period" during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).

MC9328MXL Advance Information, Rev. 5

56 Freescale Semiconductor

Specifications

CMD

DAT[1]

For 4-bit

DAT[1]

For 1-bit

Content

S T E Z Z P E Z Z

Interrupt Period IRQ IRQ

CRC

Response

S Z Z

Block Data

ES

L H

Interrupt Period

******

Block Data

Z Z

ES

Figure 44. SDIO IRQ Timing Diagram

ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the
clock running, and allows the user to submit commands as normal. After all commands are submitted, the
user can switch back to the data transfer operation and all counter and status values are resumed as access
continues.

CMD

******

CMD52

P S T E Z Z

CRC

Z

******

DAT[1]

For 4-bit

DAT[2]

For 4-bit

Block Data

Block Data

ES

Z Z L H ES

E Z ZS

L L L L L L L L L L L L L L L L L L L L L H Z S

Block Data

Block Data

E

Figure 45. SDIO ReadWait Timing Diagram

3.13 Memory Stick Host Controller

The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.

The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).

The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 57

Specifications

2 3

MS_SCLKI

MS_SCLKO

MS_BS

MS_SDIO(output)

MS_SDIO (input)

(RED bit = 0)

MS_SDIO (input)

(RED bit = 1)

1

6

11

12

13

4 5

15

7

9 10

8

11

12

14

16

Figure 46. MSHC Signal Timing Diagram

Table 21. MSHC Signal Timing Parameter Table

Ref
No.

Parameter

1 MS_SCLKI frequency – 25 MHz

2 MS_SCLKI high pulse width 20 – ns

3 MS_SCLKI low pulse width 20 – ns

4 MS_SCLKI rise time – 3 ns

5 MS_SCLKI fall time – 3 ns

6 MS_SCLKO frequency

7 MS_SCLKO high pulse width

8 MS_SCLKO low pulse width

9 MS_SCLKO rise time

10 MS_SCLKO fall time

1

1

1

1

1

3.0 ± 0.3V

Minimum Maximum

–25MHz

20 – ns

15 – ns

–5ns

–5ns

Unit

MC9328MXL Advance Information, Rev. 5

58 Freescale Semiconductor

Table 21. MSHC Signal Timing Parameter Table (Continued)

Specifications

Ref
No.

11 MS_BS delay time

1

12 MS_SDIO output delay time

Parameter

1,2

13 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)

14 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)

15 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)

16 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)

3

3

4

4

3.0 ± 0.3V

Minimum Maximum

–3ns

–3ns

18 – ns

0–ns

23 – ns

0–ns

1. Loading capacitor condition is less than or equal to 30pF.

2. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the
MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick
SDIO pin when the pin direction changes.

3. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.

4. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.

Unit

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 59

Specifications

3.14 Pulse-Width Modulator

The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 47 and the parameters are listed in Table 22.

System Clock

PWM Output

Ref
No.

1 System CLK frequency

2a Clock high time

2b Clock low time

Parameter

1

3.3 – 5/10 – ns

1

7.5 – 5/10 – ns

2a

2b

4a

1

3b

3a

4b

Figure 47. PWM Output Timing Diagram

Table 22. PWM Output Timing Parameter Table

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

1

0870100MHz

Unit

3a Clock fall time

3b Clock rise time

4a Output delay time

4b Output setup time

1. CL of PWMO = 30 pF

1

1

1

1

–5–5/10ns

–6.67–5/10ns

5.7 – 5 – ns

5.7 – 5 – ns

3.15 SDRAM Controller

A write to an address within the memory region initiates the program sequence. The first command issued
to the SyncFlash is Load Command Register. The value in A [7:0] determines which operation the
command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank
and other address lines are driven with the address to be programmed. The next command is Active which
registers the row address and confirms the bank address. The third command supplies the column address,
re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes,
therefore a Burst Terminate command is not required.

A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash
is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register
operation. The bank and other address lines are driven to the selected address. The second command is

MC9328MXL Advance Information, Rev. 5

60 Freescale Semiconductor

Specifications

Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.

1

SDCLK

2

CS

3S

3

RAS

CAS

WE

ADDR

DQ

DQM

3S

3

S

3H

4S

4H

ROW/BA

3H

COL/BA

8

3S

3S

3H

3H

3H

5

6

Data

7

Note: CKE is high during the read/write cycle.

Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram

Table 23. SDRAM Timing Parameter Table

Ref
No.

Parameter

1 SDRAM clock high-level width 2.67 – 4 – ns

2 SDRAM clock low-level width

3 SDRAM clock cycle time 11.4 – 10 – ns

3S CS, RAS, CAS, WE, DQM setup time 3.42 – 3 – ns

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 61

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Minimum Maximum Minimum Maximum

6–4–ns

Specifications

Table 23. SDRAM Timing Parameter Table (Continued)

Ref
No.

Parameter

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Minimum Maximum Minimum Maximum

3H CS, RAS, CAS, WE, DQM hold time 2.28 – 2 – ns

4S Address setup time 3.42 – 3 – ns

4H Address hold time 2.28 – 2 – ns

5 SDRAM access time (CL = 3) – 6.84 – 6 ns

5 SDRAM access time (CL = 2) – 6.84 – 6 ns

5 SDRAM access time (CL = 1) – 22 – 22 ns

6 Data out hold time 2.85 – 2.5 – ns

7 Data out high-impedance time (CL = 3) – 6.84 – 6 ns

7 Data out high-impedance time (CL = 2) – 6.84 – 6 ns

7 Data out high-impedance time (CL = 1) – 22 – 22 ns

8 Active to read/write command period (RC = 1)

1. t

= SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.

RCD

t

RCD

1

–

t

RCD

1

–ns

MC9328MXL Advance Information, Rev. 5

62 Freescale Semiconductor

SDCLK

CS

RAS

CAS

WE

Specifications

3

1

2

6

ADDR

DQ

DQM

4

/ BA

5 7

ROW/BA

8

COL/BA

9

DATA

Figure 49. SDRAM/SyncFlash Write Cycle Timing Diagram

Table 24. SDRAM Write Timing Parameter Table

Ref
No.

Parameter

1 SDRAM clock high-level width 2.67 – 4 – ns

2 SDRAM clock low-level width

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

6–4–ns

Unit

3 SDRAM clock cycle time 11.4 – 10 – ns

4 Address setup time 3.42 – 3 – ns

5 Address hold time 2.28 – 2 – ns

6 Precharge cycle period

1

7 Active to read/write command delay

t

RP

t

RCD

2

2

–

–

t

t

RCD

RP

2

2

–ns

–ns

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 63

Specifications

Table 24. SDRAM Write Timing Parameter Table (Continued)

Ref
No.

Parameter

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

8 Data setup time 4.0 – 2 – ns

9 Data hold time 2.28 – 2 – ns

1. Precharge cycle timing is included in the write timing diagram.

2. t

RP

and t

= SDRAM clock cycle time. These settings can be found in the MC9328MXL reference

RCD

manual.

SDCLK

3

1 2

CS

RAS

6

CAS

Unit

Ref
No.

WE

ADDR

DQ

DQM

4

BA

Parameter

7

5

Figure 50. SDRAM Refresh Timing Diagram

Table 25. SDRAM Refresh Timing Parameter Table

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

7

ROW/BA

Unit

1 SDRAM clock high-level width 2.67 – 4 – ns

2 SDRAM clock low-level width

6–4–ns

MC9328MXL Advance Information, Rev. 5

64 Freescale Semiconductor

Table 25. SDRAM Refresh Timing Parameter Table (Continued)

Specifications

Ref
No.

Parameter

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

3 SDRAM clock cycle time 11.4 – 10 – ns

4 Address setup time 3.42 – 3 – ns

5 Address hold time 2.28 – 2 – ns

6 Precharge cycle period

7 Auto precharge command period

and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference

1. t

RP

1

t

RP

1

t

RC

–

–

t

t

RP

RC

1

1

–ns

–ns

manual.

SDCLK

CS

Unit

RAS

CAS

WE

ADDR

DQ

DQM

CKE

BA

Figure 51. SDRAM Self-Refresh Cycle Timing Diagram

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 65

Specifications

3.16 USB Device Port

Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous
transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is
identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section
covers the transfer modes and how they work from the ground up.

Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same
packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved
in the form of packets, however, because isochronous pipes are given a fixed portion of the USB
bandwidth at all times, there is no end-of-transfer.

USBD_AFE

(Output)

USBD_ROE

(Output)

USBD_VPO

(Output)

USBD_VMO

(Output)

USBD_SUSPND

(Output)

1

t

ROE_VPO

t

ROE_VMO

PERIOD

6

t

2

t

VMO_ROE

t

FEOPT

4

t

VPO_ROE

5

3

USBD_RCV

(Input)

USBD_VP

(Input)

USBD_VM

(Input)

Figure 52. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)

Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)

1.8V ± 0.10V 3.0V ± 0.30V

Ref No. Parameter

Minimum Maximum Minimum Maximum

1t

ROE_VPO

USBD_VPO low

2t

ROE_VMO

USBD_VMO high

3t

VPO_ROE

USBD_ROE deactivated

; USBD_ROE active to

; USBD_ROE active to

; USBD_VPO high to

83.14 83.47 83.14 83.47 ns

81.55 81.98 81.55 81.98 ns

83.54 83.80 83.54 83.80 ns

Unit

MC9328MXL Advance Information, Rev. 5

66 Freescale Semiconductor

Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)

1.8V ± 0.10V 3.0V ± 0.30V

Ref No. Parameter

Minimum Maximum Minimum Maximum

Specifications

Unit

4t

VMO_ROE

USBD_ROE deactivated (includes SE0)

5t

6t

USBD_SUSPND

FEOPT

PERIOD

USBD_AFE

(Output)

USBD_ROE

(Output)

USBD_VPO

(Output)

USBD_VMO

(Output)

(Output)

; USBD_VMO low to

248.90 249.13 248.90 249.13 ns

; SE0 interval of EOP 160.00 175.00 160.00 175.00 ns

; Data transfer rate 11.97 12.03 11.97 12.03 Mb/s

USBD_RCV

(Input)

1

t

USBD_VP

(Input)

USBD_VM

(Input)

FEOPR

Figure 53. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)

Table 27. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)

1.8V ± 0.10V 3.0V ± 0.30V

Ref No. Parameter

Minimum Maximum Minimum Maximum

1t

; Receiver SE0 interval of EOP 82 – 82 – ns

FEOPR

MC9328MXL Advance Information, Rev. 5

Unit

Freescale Semiconductor 67

Specifications

3.17 I2C Module

The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.

SDA

5

SCL

1

3

2

4

6

Figure 54. Definition of Bus Timing for I2C

Table 28. I2C Bus Timing Parameter Table

1.8V ± 0.10V 3.0V ± 0.30V

Ref No. Parameter

Minimum Maximum Minimum Maximum

1 Hold time (repeated) START condition 182 – 160 – ns

2 Data hold time

3 Data setup time 11.4 – 10 – ns

4 HIGH period of the SCL clock 80 – 120 – ns

5 LOW period of the SCL clock 480 – 320 – ns

6 Setup time for STOP condition 182.4 – 160 – ns

01710150ns

Unit

3.18 Synchronous Serial Interface

The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In
gated clock mode, the clock functions only during transmission. The internal and external clock timing
diagrams are shown in Figure 56 through Figure 58 on page 70.

Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.

MC9328MXL Advance Information, Rev. 5

68 Freescale Semiconductor

STCK Output

Specifications

1

STFS (bl) Output

STFS (wl) Output

STXD Output

SRXD Input

Note: SRXD input in synchronous mode only.

Figure 55. SSI Transmitter Internal Clock Timing Diagram

SRCK Output

2

4

6

8

12

10

31

11

32

1

3

5

SRFS (bl) Output

SRFS (wl) Output

SRXD Input

7

13

14

Figure 56. SSI Receiver Internal Clock Timing Diagram

9

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 69

Specifications

15

16

STCK Input

18

STFS (bl) Input

STFS (wl) Input

STXD Output

SRXD Input

Note: SRXD Input in Synchronous mode only

Figure 57. SSI Transmitter External Clock Timing Diagram

15

16

SRCK Input

17

17

22

26

20

33

24

28

27

34

SRFS (bl) Input

SRFS (wl) Input

SRXD Input

Figure 58. SSI Receiver External Clock Timing Diagram

Table 29. SSI (Port C Primary Function) Timing Parameter Table

Ref No. Parameter

Internal Clock Operation

1 STCK/SRCK clock period

2 STCK high to STFS (bl) high

3 SRCK high to SRFS (bl) high

19

23

21

25

30

29

1.8V ± 0.10V 3.0V ± 0.30V

Minimum Maximum Minimum Maximum

1

(Port C Primary Function2)

1

95 – 83.3 – ns

3

1.5 4.5 1.3 3.9 ns

3

-1.2 -1.7 -1.1 -1.5 ns

Unit

MC9328MXL Advance Information, Rev. 5

70 Freescale Semiconductor

Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)

1.8V ± 0.10V 3.0V ± 0.30V

Ref No. Parameter

Minimum Maximum Minimum Maximum

4 STCK high to STFS (bl) low3 2.5 4.3 2.2 3.8 ns

Specifications

Unit

5 SRCK high to SRFS (bl) low

6 STCK high to STFS (wl) high

7 SRCK high to SRFS (wl) high

8 STCK high to STFS (wl) low

9 SRCK high to SRFS (wl) low

10 STCK high to STXD valid from high

3

0.1 -0.8 0.1 -0.8 ns

3

1.48 4.45 1.3 3.9 ns

3

-1.1 -1.5 -1.1 -1.5 ns

3

2.51 4.33 2.2 3.8 ns

3

0.1 -0.8 0.1 -0.8 ns

14.25 15.73 12.5 13.8 ns

impedance

11a STCK high to STXD high 0.91 3.08 0.8 2.7 ns

11b STCK high to STXD low 0.57 3.19 0.5 2.8 ns

12 STCK high to STXD high impedance 12.88 13.57 11.3 11.9 ns

13 SRXD setup time before SRCK low 21.1 – 18.5 – ns

14 SRXD hold time after SRCK low 0 – 0 – ns

External Clock Operation (Port C Primary Function

15 STCK/SRCK clock period

1

92.8 – 81.4 – ns

2

)

16 STCK/SRCK clock high period 27.1 – 40.7 – ns

17 STCK/SRCK clock low period 61.1 – 40.7 – ns

18 STCK high to STFS (bl) high

19 SRCK high to SRFS (bl) high

20 STCK high to STFS (bl) low

21 SRCK high to SRFS (bl) low

22 STCK high to STFS (wl) high

23 SRCK high to SRFS (wl) high

24 STCK high to STFS (wl) low

25 SRCK high to SRFS (wl) low

26 STCK high to STXD valid from high

3

3

3

3

3

3

3

3

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

18.01 28.16 15.8 24.7 ns

impedance

27a STCK high to STXD high 8.98 18.13 7.0 15.9 ns

27b STCK high to STXD low 9.12 18.24 8.0 16.0 ns

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 71

Specifications

Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)

Ref No. Parameter

28 STCK high to STXD high impedance 18.47 28.5 16.2 25.0 ns

29 SRXD setup time before SRCK low 1.14 – 1.0 – ns

30 SRXD hole time after SRCK low 0 – 0 – ns

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Minimum Maximum Minimum Maximum

Synchronous Internal Clock Operation (Port C Primary Function

2

)

31 SRXD setup before STCK falling 15.4 – 13.5 – ns

32 SRXD hold after STCK falling 0 – 0 – ns

Synchronous External Clock Operation (Port C Primary Function

2

)

33 SRXD setup before STCK falling 1.14 – 1.0 – ns

34 SRXD hold after STCK falling 0 – 0 – ns

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.

2. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad

261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as input, the SSI module selects the input based on status of the FMCR register bits in the
Clock controller module (CRM). By default, the input are selected from Port C primary function.

bl = bit length; wl = word length.

3.

Table 30. SSI (Port B Alternate Function) Timing Parameter Table

Ref
No.

Parameter

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Minimum Maximum Minimum Maximum

Internal Clock Operation1 (Port B Alternate Function2)

1 STCK/SRCK clock period

2 STCK high to STFS (bl) high

3 SRCK high to SRFS (bl) high

4 STCK high to STFS (bl) low

5 SRCK high to SRFS (bl) low

6 STCK high to STFS (wl) high

7 SRCK high to SRFS (wl) high

8 STCK high to STFS (wl) low

1

95 – 83.3 – ns

3

3

-0.1 1.0 -0.1 1.0 ns

3

3.08 5.24 2.7 4.6 ns

3

1.25 2.28 1.1 2.0 ns

3

3

3

3.08 5.24 2.7 4.6 ns

1.7 4.8 1.5 4.2 ns

1.71 4.79 1.5 4.2 ns

-0.1 1.0 -0.1 1.0 ns

MC9328MXL Advance Information, Rev. 5

72 Freescale Semiconductor

Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)

Specifications

Ref
No.

9 SRCK high to SRFS (wl) low

Parameter

3

10 STCK high to STXD valid from high

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Minimum Maximum Minimum Maximum

1.25 2.28 1.1 2.0 ns

14.93 16.19 13.1 14.2 ns

impedance

11a STCK high to STXD high 1.25 3.42 1.1 3.0 ns

11b STCK high to STXD low 2.51 3.99 2.2 3.5 ns

12 STCK high to STXD high impedance 12.43 14.59 10.9 12.8 ns

13 SRXD setup time before SRCK low 20 – 17.5 – ns

14 SRXD hold time after SRCK low 0 – 0 – ns

External Clock Operation (Port B Alternate Function

15 STCK/SRCK clock period

1

92.8 – 81.4 – ns

2

)

16 STCK/SRCK clock high period 27.1 – 40.7 – ns

17 STCK/SRCK clock low period 61.1 – 40.7 – ns

18 STCK high to STFS (bl) high

19 SRCK high to SRFS (bl) high

20 STCK high to STFS (bl) low

21 SRCK high to SRFS (bl) low

22 STCK high to STFS (wl) high

23 SRCK high to SRFS (wl) high

24 STCK high to STFS (wl) low

25 SRCK high to SRFS (wl) low

26 STCK high to STXD valid from high

3

3

3

3

3

3

3

3

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

– 92.8 0 81.4 ns

18.9 29.07 16.6 25.5 ns

impedance

27a STCK high to STXD high 9.23 20.75 8.1 18.2 ns

27b STCK high to STXD low 10.60 21.32 9.3 18.7 ns

28 STCK high to STXD high impedance 17.90 29.75 15.7 26.1 ns

29 SRXD setup time before SRCK low 1.14 – 1.0 – ns

30 SRXD hold time after SRCK low 0 – 0 – ns

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 73

Specifications

Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)

Ref
No.

Parameter

1.8V ± 0.10V 3.0V ± 0.30V

Unit

Minimum Maximum Minimum Maximum

Synchronous Internal Clock Operation (Port B Alternate Function2)

31 SRXD setup before STCK falling 18.81 – 16.5 – ns

32 SRXD hold after STCK falling 0 – 0 – ns

Synchronous External Clock Operation (Port B Alternate Function

2

)

33 SRXD setup before STCK falling 1.14 – 1.0 – ns

34 SRXD hold after STCK falling 0 – 0 – ns

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.

2. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad

261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.

3. bl = bit length; wl = word length.

MC9328MXL Advance Information, Rev. 5

74 Freescale Semiconductor

Specifications

3.19 CMOS Sensor Interface

The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing, a control
register for statistic data generation, a status register, interface logic, a 32
16

× 32 statistic data FIFO.

3.19.1 Gated Clock Mode

Figure 59 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 60 on page 76 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 31 on page 76.

1

VSYNC

× 32 image data receive FIFO, and a

7

HSYNC

PIXCLK

DATA[7:0]

5 6

2

Valid Data

3 4

Valid Data Valid Data

Figure 59. Sensor Output Data on Pixel Clock Falling Edge

CSI Latches Data on Pixel Clock Rising Edge

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 75

Specifications

1

VSYNC

7

HSYNC

2

PIXCLK

DATA[7:0]

Valid Data

3 4

Valid Data Valid Data

Figure 60. Sensor Output Data on Pixel Clock Rising Edge

CSI Latches Data on Pixel Clock Falling Edge

Table 31. Gated Clock Mode Timing Parameters

Ref No. Parameter Min Max Unit

1 csi_vsync to csi_hsync 180 – ns

2 csi_hsync to csi_pixclk 1 – ns

3 csi_d setup time 1 – ns

4 csi_d hold time 1 – ns

56

5 csi_pixclk high time 10.42 – ns

6 csi_pixclk low time 10.42 – ns

7 csi_pixclk frequency 0 48 MHz

The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:

Rising-edge latch data

max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)

In most of case, duty cycle is 50 / 50, therefore

max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)

For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.

positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns

MC9328MXL Advance Information, Rev. 5

76 Freescale Semiconductor

Specifications

negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns

Falling-edge latch data

max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)

3.19.2 Non-Gated Clock Mode

Figure 61 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 62 on page 78 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 32 on page 78.

1

VSYNC

6

PIXCLK

DATA[7:0]

4 5

Valid Data

2

Valid Data

3

Valid Data

Figure 61. Sensor Output Data on Pixel Clock Falling Edge

CSI Latches Data on Pixel Clock Rising Edge

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 77

Specifications

1

VSYNC

6

5

PIXCLK

DATA[7:0]

Valid Data

2

3

Valid Data

Figure 62. Sensor Output Data on Pixel Clock Rising Edge

CSI Latches Data on Pixel Clock Falling Edge

Table 32. Non-Gated Clock Mode Parameters

Ref No. Parameter Min Max Unit

1 csi_vsync to csi_pixclk 180 – ns

2 csi_d setup time 1 – ns

3 csi_d hold time 1 – ns

4 csi_pixclk high time 10.42 – ns

5 csi_pixclk low time 10.42 – ns

6 csi_pixclk frequency 0 48 MHz

4

Valid Data

The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:

max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)

In most of case, duty cycle is 50 / 50, therefore:

max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)

For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.

positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns

negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns

Falling-edge latch data

max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)

MC9328MXL Advance Information, Rev. 5

78 Freescale Semiconductor

Pin-Out and Package Information

CSI_D7 TMS TDI

CSI_VSYNC CSI_D6 CSI_D5

HSYNC

PIXCLK

BOOT2 CSI_

CSI_D4 CSI_

AN

OUT

N.C. N.C. N.C. QVSS4 N.C. N.C. N.C.

NVDD3 N.C. N.C. QVDD4 N.C. N.C. N.C.

N.C. N.C. N.C. N.C. N.C. N.C. N.C.

N.C. N.C. N.C. N.C. N.C. N.C. N.C.

N.C. N.C. REV N.C. N.C. LSCLK SPL_SPR

N.C. CLS CONTRAST OE_ACD HSYNC VSYNC LD1

SCLK

TXCLK

RXCLK

ROE

TXD

UART1_

RXFS

SSI0_

RXD

UART2_

CTS

UART2_

RCV

SPI1_

SPI_RDY

SSI0_

RXDAT

VMO

USBD_

VPO

USBD_

SUSPND

SPI1_SS N.C. N.C. N.C. N.C. N.C. N.C. N.C.

SSI0_

TXDAT

RTS

MISO

SPI1_

TXFS

SSI0_

TXD

UART2_

TXFS

MOSI

SPI1_

CTS

UART1_

SSI1_

TXCLK

TXDAT

RXD

SPI1_

UART1_

RTS

SSI0_

NVDD4 NVSS3 UART1_

Table 33. MC9328MXL 256 MAPBGA Pin Assignments

USBD_VP SSI0_

AFE

D0 DQM0 SDCKE0 POR BOOT1 TDO QVDD2 EXTAL32K

1

BCLK

1234 5678910111213141516

4 Pin-Out and Package Information

Table 33 illustrates the package pin assignments for the 256-pin MAPBGA package.

A NVSS1 DAT3 CLK NVSS4 USBD_

B A24 DAT1 CMD SSI1_RXDAT USBD_

C A23 D31 DAT0 SSI1_RXCLK USBD_

D A22 D30 D29 SSI1_RXFS USBD_

E A20 A21 D28 D26 DAT2 USBD_VM UART2_

F A18 D27 D25 A19 A16 SSI1_

G A15 A17 D24 D 23 D21 SSI1_

J A12 A11 D18 D19 NVDD1 NVDD1 NVSS1 NVDD1 NVSS2 NVSS2 LD6 LD7 LD8 LD11 QVDD3 QVSS3

H A13 D22 A14 D20 NVDD1 NVDD1 NVSS1 QVSS1 QVDD1 PS LD0 LD2 LD4 LD5 LD9 LD3

K A10 D16 A9 D17 NVDD1 NVSS1 NVSS1 NVDD1 NVDD2 NVDD2 LD10 LD12 LD13 LD14 TOUT2 LD15

L A8 A7 D13 D15 D14 NVDD1 NVSS1 CAS TCK TIN PWMO CSI_MCLK CSI_D0 CSI_D1 CSI_D2 CSI_D3

M A5 D12 D11 A6 SDCLK NVSS1 RW MA10 RAS RESET_IN BIG_ENDI

N A4 EB1 D10D7 A0 D4PA17D1DQM1RESET_SFRESET_

P A3 D9 EB0 CS3 D6 ECB D2 D3 DQM3 SDCKE1 BOOT3 BOOT0 TRST I2C_CLK I2C_DATA XTAL32K

R EB2 EB3 A1 CS4 D8 D5 LBA

T NVSS1 A2 OE CS5 CS2 CS1 CS0 MA11 DQM2 SDWE CLKO AVDD1 TRISTATE EXTAL16M XTAL16M QVSS2

1. burst clock

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 79

Pin-Out and Package Information

REV PS LD2 LD4 LD5

SPI1_RDY SPI1_

SCLK

LD0 LD3 LD6 LD7

SPI1_SS LSCLK SPL_

SPR

CONTRAST VSYNC LD8 LD9 LD12 NVDD2

RTS

UART1_

MCLK

I2C_DATA TMS

CSI_

PIXCLK

LD10 TIN CSI_D0 CSI_

ACD

OE_

HSYNC LD1 LD11 TOUT2 LD13

CLS QVDD3 LD14 LD15 CSI_D2 CSI_D4

MISO

MOSI

SPI1_

CTS

SSI0_

NVDD3 SPI1_

UART1_

TXDAT

VSYNC

BOOT1 BOOT0

TCK TDO

CLK

XTAL32K

OUT

RESET_

ENDIAN

RW NVSS BOOT3 QVDD2 RESET_IN EXTAL16M

1

BCLK

Table 34. MC9328MXL 225 PBGA Pin Assignments

SSI0_

TXCLK

RXFS

USBD_VM SSI0_

USBD_

SUSPND

ROE

USBD_

SSI1_

TXCLK

RXCLK

TXD

UART1_

SSI0_

RXDAT

VMO

USBD_RCV USBD_

AFE

USBD_

RXDAT

TXFS

SSI0_

RXD

UART2_

VPO

DAT2 USBD_

TXFS

SSI1_

RXFS

TXD

NVDD1 USBD_VP QVDD4 UART2_

TXDAT

RXD

UART1_

RTS

SSI0_

RXCLK

CTS

D2 ECB NVSS NVSS POR QVSS XTAL16M EXTAL32K

NVDD1 CS4 CS1

D19 NVDD1 NVSS QVSS NVDD1 NVSS D1 BOOT2 TDI BIG_

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Table 34 illustrates the package pin assignments for the 225-pin PBGA package.

A CMD SSI1_

B DAT3 CLK SSI1_

C D31 DAT0 SSI1_

D A23 A24 DAT1 SSI1_

E A21 A22 D30 D29 NVDD1 QVSS UART2_

F A20 A19 D28 D27 NVDD1 NVDD1 UART2_

G A17 A18 D26 D25 NVDD1 NVSS NVDD4 NVSS NVSS QVSS PWMO CSI_D3 CSI_D7 CSI_HSYNC CSI_D5

J A14 A12 D21 D20 NVDD1 NVSS NVSS QVDD1 NVSS CSI_D6 I2C_

H A15 A16 D23 D24 D22 NVSS NVSS NVSS NVSS NVDD2 CSI_D1 CSI_

K A13 A11 CS2

L A10 A9 D17 D18 NVDD1 NVDD1 CS5

P D14 A5 A4 A3 A2 A1 D6 D5 MA10 MA11 DQM1 RAS SDCKE1 CLKO RESETSF

N A8 A7 D12 EB0 D9 D8 CS3 CS0 PA17 D0 DQM2 DQM0 SDCKE0 TRISTATE TRST

M D16 D15 D13 D10 EB3

R A6 D11 EB1 EB2 OE D7 A0 SDCLK D4 LBA D3 DQM3 CAS SDWE AVDD1

1. burst clock

MC9328MXL Advance Information, Rev. 5

80 Freescale Semiconductor

Pin-Out and Package Information

4.1 MAPBGA 256 Package Dimensions

Figure 63 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, which has 0.8 mm spacing between
the pads. The device designator for the MAPBGA package is VH.

Case Outline 1367

TOP VIEW

BOTTOM VIEW

SIDE VIEW

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.

3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.

Figure 63. MC9328MXL 256 MAPBGA Mechanical Drawing

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 81

Pin-Out and Package Information

4.2 PBGA 225 Package Dimensions

Figure 64 illustrates the 225 PBGA 13 mm × 13 mm × 0.8 mm package.

Case Outline 1304B

TOP VIEW

BOTTOM VIEW

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.

3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.

5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF

PACKAGE.

SIDE VIEW

Figure 64. MC9328MXL 225 PBGA Mechanical Drawing

MC9328MXL Advance Information, Rev. 5

82 Freescale Semiconductor

NOTES

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor 83

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MC9328MXL/D
Rev. 5
08/2004