Freescale MC9328MXL Advance Information
查询MC9328MXLCVF15供应商
Freescale Semiconductor
Advance Information
MC9328MXL
MC9328MXL/D
Rev. 5, 08/2004
MC9328MXL
Package Information
Plastic Package
(MAPBGA–225 or 256)
Ordering Information
See Table 2 on page 5
1 Introduction
The i.MX family builds on the DragonBall family of
application processors which have demonstrated leadership
in the portable handheld market. Continuing this legacy, the
i.MX (Media Extensions) series provides a leap in
performance with an ARM9™ microprocessor core and
highly integrated system functions. The i.MX products
specifically address the requirements of the personal,
portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power
management capabilities.
The new MC9328MXL features the advanced and powerefficient ARM920T™ core that operates at speeds up to
200 MHz. Integrated modules, which include an LCD
controller, USB support, and an MMC/SD host controller,
support a suite of peripherals to enhance any product seeking
to provide a rich multimedia experience. It is packaged in
either a 256-pin Mold Array Process-Ball Grid Array
(MAPBGA) or 225-pin PBGA package. Figure 1 shows the
functional block diagram of the MC9328MXL.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2 Signals and Connections . . . . . . . . . . . . . . . . . . . .6
3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Pin-Out and Package Information. . . . . . . . . . . . .79
Contact Information . . . . . . . . . . . . . . . . . Last Page
© Freescale Semiconductor, Inc., 2004. All rights reserved.
This document contains information on a new product. Specifications and information herein are
subject to change without notice.
Introduction
JTAG/ICE
Connectivity
MMC/SD
Memory Stick®
Host Controller
SPI 1 and
SPI 2
UART 1
UART 2
SSI/I2S
I2C
USB Device
System Control
Bootstrap
AIPI 1
AIPI 2
Power
Control (PLLx2)
MC9328MXL
CPU Complex
ARM9TDMI™
I Cache
VMMU
(11 Chnl)
EIM &
SDRAMC
CGM
D Cache
Interrupt
Controller
BusDMAC
Control
Figure 1. MC9328MXL Functional Block Diagram
Standard
System I/O
GPIO
PWM
Timer 1 & 2
RTC
Watchdog
Multimedia
Multimedia
Accelerator
Video Port
Human Interface
LCD Controller
1.1 Conventions
This document uses the following conventions:
• OVERBAR
• Logic level one is a voltage that corresponds to Boolean true (1) state.
• Logic level zero is a voltage that corresponds to Boolean false (0) state.
•To set a bit or bits means to establish logic level one.
•To clear a bit or bits means to establish logic level zero.
•A signal is an electronic construct whose state conveys or changes in state convey information.
•A pin is an external physical connection. The same pin can be used to connect a number of signals.
• Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
• Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
is used to indicate a signal that is active when pulled low: for example, RESET.
• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
MC9328MXL Advance Information, Rev. 5
2 Freescale Semiconductor
Introduction
1.2 Features
To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the
following:
• ARM920T™ Microprocessor Core
• AHB to IP Bus Interfaces (AIPIs)
• External Interface Module (EIM)
• SDRAM Controller (SDRAMC)
• DPLL Clock and Power Control Module
• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
• Two Serial Peripheral Interfaces (SPI1 and SPI2)
• Two General-Purpose 32-bit Counters/Timers
• Watchdog Timer
• Real-Time Clock/Sampling Timer (RTC)
• LCD Controller (LCDC)
• Pulse-Width Modulation (PWM) Module
• Universal Serial Bus (USB) Device
• Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
• Memory Stick® Host Controller (MSHC)
• Direct Memory Access Controller (DMAC)
• Synchronous Serial Interface and Inter-IC Sound (SSI/I
2
• Inter-IC (I
C) Bus Module
2
S) Module
•Video Port
• General-Purpose I/O (GPIO) Ports
• Bootstrap Mode
• Multimedia Accelerator (MMA)
• Power Management Features
• Operating Voltage Range: 1.7 V to 1.98 V core, 1.7 V to 3.3V I/O
• 256-pin MAPBGA Package
• 225-pin MAPBGA Package
1.3 Target Applications
The MC9328MXL is targeted for advanced information appliances, smart phones, Web browsers, digital MP3
audio players, handheld computers, and messaging applications.
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 3
Introduction
1.4 Revision History
Table 1 provides revision history for this release. This history includes technical content revisions only and not
stylistic or grammatical changes.
Table 1. MC9328MXL Data Sheet Revision History Rev. 5
Revision Location Revision
Throughout Clarified instances where BCLK signal is burst clock.
Section 3.3, “Power Sequence
Requirements” on page 12
Added reference to AN2537.
1.5 Product Documentation
The following documents are required for a complete description of the MC9328MXL and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents are helpful when used in conjunction with this document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXL Product Brief (order number MC9328MXLP/D)
MC9328MXL Reference Manual (order number MC9328MXLRM/D)
The Motorola manuals are available on the Motorola Semiconductors Web site at
http://www.motorola.com/semiconductors. These documents may be downloaded directly from the Motorola Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
MC9328MXL Advance Information, Rev. 5
4 Freescale Semiconductor
Introduction
1.6 Ordering Information
Table 2 provides ordering information for both the 256-lead mold array process ball grid array (MAPBGA)
package and the 225-lead BGA package.
Table 2. MC9328MXL Ordering Information
Package Type Frequency Temperature Solderball Type Order Number
256-lead MAPBGA 150 MHz
200 MHz
225-lead MAPBGA 150 MHz
200 MHz
-40OC to 85OC
0OC to 70OC
-30OC to 70OC
-40OC to 85OC
0OC to 70OC
O
C to 70OC
-30
Standard MC9328MXLCVH15(R2)
Pb-free MC9328MXLCVM15(R2)
Standard MC9328MXLVH20(R2)
Pb-free MC9328MXLVM20(R2)
Standard MC9328MXLDVH20(R2)
Pb-free MC9328MXLDVM20(R2)
Standard MC9328MXLCVF15(R2)
Pb-free MC9328MXLCVP15(R2)
Standard MC9328MXLVF20(R2)
Pb-free MC9328MXLVP20(R2)
Standard MC9328MXLDVF20(R2)
Pb-free MC9328MXLDVP20(R2)
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 5
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. MC9328MXL Signal Descriptions
Signal Name Function/Notes
External Bus/Chip-Select (EIM)
A[24:0] Address bus signals
D[31:0] Data bus signals
EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16].
EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8].
EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
OE Memory Output Enable—Active low output enables external data bus.
CS [5:0] Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD
ECB Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
[1:0] is selected.
LBA Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
DTACK DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is
not terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
BOOT [3:0] System Boot Mode Select—The operational system boot mode of the MC9328MXL upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDIBA [3:0] SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
MA [11:10] SDRAM address signals
MA [9:0] SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected
on SDRAM/SyncFlash cycles.
DQM [3:0] SDRAM data enable
CSD0 SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals
are selectable by programming the system control register.
MC9328MXL Advance Information, Rev. 5
6 Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXL Signal Descriptions (Continued)
Signal Name Function/Notes
CSD1 SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are
selectable by programming the system control register. By default, CSD1 is selected, so it can be
used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins.
RAS SDRAM/SyncFlash Row Address Select signal
CAS SDRAM/SyncFlash Column Address Select signal
SDWE SDRAM/SyncFlash Write Enable signal
SDCKE0 SDRAM/SyncFlash Clock Enable 0
SDCKE1 SDRAM/SyncFlash Clock Enable 1
SDCLK SDRAM/SyncFlash Clock
RESET_SF SyncFlash Reset
Clocks and Resets
EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is
shut down.
XTAL16M Crystal output
EXTAL32K 32 kHz crystal input
XTAL32K 32 kHz crystal output
CLKO Clock Out signal selected from internal clock signals.
RESET_IN Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from
the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK Test Clock to synchronize test logic and control register access through the JTAG port.
TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
DMA
BIG_ENDIAN Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to little endian. If it is
driven logic-low at reset, the external chip-select space will be configured to big endian.
DMA_REQ External DMA request pin.
ETM
ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 7
Signals and Connections
Table 3. MC9328MXL Signal Descriptions (Continued)
Signal Name Function/Notes
ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0] Sensor port data
CSI_MCLK Sensor port master clock
CSI_VSYNC Sensor port vertical sync
CSI_HSYNC Sensor port horizontal sync
CSI_PIXCLK Sensor port data latch clock
LCD Controller
LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC Line pulse or H sync
LSCLK Shift clock
ACD/OE Alternate crystal direction/output enable.
CONTRAST This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).
PS Control signal output for source driver (Sharp panel dedicated signal).
CLS Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1 and 2
SPI1_MOSI Master Out/Slave In
SPI1_MISO Slave In/Master Out
SPI1_SS Slave Select (Selectable polarity)
SPI1_SCLK Serial Clock
SPI1_SPI_RDY Serial Data Ready
SPI2_TXD SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as a primary
or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters
in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
SPI2_RXD SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
MC9328MXL Advance Information, Rev. 5
8 Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXL Signal Descriptions (Continued)
Signal Name Function/Notes
SPI2_SS SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
SPI2_SCLK SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
General Purpose Timers
TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT Timer 2 Output
USB Device
USBD_VMO USB Minus Output
USBD_VPO USB Plus Output
USBD_VM USB Minus Input
USBD_VP USB Plus Input
USBD_SUSPND USB Suspend Output
USBD_RCV USB Receive Data
USBD_OE USB OE
USBD_AFE USB Analog Front End Enable
Secure Digital Interface
SD_CMD SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-
up enable register, a 4.7K–69K external pull up resistor must be added.
SD_CLK MMC Output Clock
SD_DAT [3:0] Data—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable
register, a 50K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS Memory Stick Bus State (Output)—Serial bus control signal
MS_SDIO Memory Stick Serial Data (Input/Output)
MS_SCLKO Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider
MS_SCLKI Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is only for test
purposes, not for use in application mode.
MS_PI0 General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
MS_PI1 General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD Receive Data
UART1_TXD Transmit Data
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 9
Signals and Connections
Table 3. MC9328MXL Signal Descriptions (Continued)
Signal Name Function/Notes
UART1_RTS Request to Send
UART1_CTS Clear to Send
UART2_RXD Receive Data
UART2_TXD Transmit Data
UART2_RTS Request to Send
UART2_CTS Clear to Send
UART2_DSR Data Set Ready
UART2_RI Ring Indicator
UART2_DCD Data Carrier Detect
UART2_DTR Data Terminal Ready
Serial Audio Port – SSI (configurable to I2S protocol)
SSI_TXDAT Transmit Data
SSI_RXDAT Receive Data
SSI_TXCLK Transmit Serial Clock
SSI_RXCLK Receive Serial Clock
SSI_TXFS Transmit Frame Sync
SSI_RXFS Receive Frame Sync
I2C
I2C_SCL I2C Clock
I2C_SDA I2C Data
PWM
PWMO PWM Output
Digital Supply Pins
NVDD Digital Supply for the I/O pins
NVSS Digital Ground for the I/O pins
Supply Pins – Analog Modules
AVDD Supply for analog blocks
AVSS Quiet ground for analog blocks
Internal Power Supply
QVDD Power supply pins for silicon internal circuitry
QVSS Ground pins for silicon internal circuitry
MC9328MXL Advance Information, Rev. 5
10 Freescale Semiconductor
Specifications
Table 3. MC9328MXL Signal Descriptions (Continued)
Signal Name Function/Notes
Substrate Supply Pins
SVDD Supply routed through substrate of package; not to be bonded
SGND Ground routed through substrate of package; not to be bonded
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MXL processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings.
Table 4. Maximum Ratings
Rating Symbol Minimum Maximum Unit
Supply voltage V
Maximum operating temperature range
MC9328MXLVH20/MC9328MXLVM20/
MC9328MXLVF20/MC9328MXLVP20
Maximum operating temperature range
MC9328MXLDVH20/MC9328MXLDVM20/
MC9328MXLDVF20/MC9328MXLDVP20
Maximum operating temperature range
MC9328MXLCVH15/MC9328MXLCVM15/
MC9328MXLCVF15/MC9328MXLCVP15
ESD at human body model (HBM) VESD_HBM – 2000 V
ESD at machine model (MM) VESD_MM – 100 V
Latch-up current ILatchup – 200 mA
Storage temperature Test -55 150 °C
Power Consumption Pmax
1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from
the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core
running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at
2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
dd
T
A
T
A
T
A
-0.3 3.3 V
070°C
-30 70 °C
-40 85 °C
800
1
1300
2
mW
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 11
Specifications
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MXL has multiple pairs
of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD
and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/
O pads. This design allows different peripheral supply voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the
AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.
Table 5. Recommended Operating Range
Rating Symbol Minimum Maximum Unit
I/O supply voltage (if using MSHC, SPI, BTA, USBd, LCD and CSI
which are only 3 V interfaces)
I/O supply voltage (if not using the peripherals listed above) NVDD 1.70 3.30 V
Internal supply voltage (Core = 150 MHz) QVDD 1.70 1.90 V
Internal supply voltage (Core = 200 MHz) QVDD 1.80 2.00 V
Analog supply voltage AVDD 1.70 3.30 V
NVDD 2.70 3.30 V
3.3 Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of
application note AN2537 on the i.MX website page.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MXL.
Table 6. Maximum and Minimum DC Characteristics
Number or
Symbol
Iop Full running operating current at 1.8V for QVDD, 3.3V for
NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4
decoding playback from external memory card to both
external SSI audio decoder and TFT display panel, and OS
with MMU enabled memory system is running on external
SDRAM).
Parameter Min Typical Max Unit
– QVDD at
1.8v = 120mA;
NVDD+AVDD at
3.0v = 30mA
–mA
Sidd
Sidd
Sidd
12 Freescale Semiconductor
Standby current
1
(Core = 150 MHz, QVDD = 1.8V, temp = 25°C)
Standby current
2
(Core = 150 MHz, QVDD = 1.8V, temp = 55
Standby current
3
(Core = 150 MHz, QVDD = 2.0V, temp = 25
MC9328MXL Advance Information, Rev. 5
–25 –µA
–45 –µA
°C)
–35 –µA
°C)
Table 6. Maximum and Minimum DC Characteristics (Continued)
Specifications
Number or
Symbol
Sidd
4
V
IH
V
IL
V
OH
V
OL
I
IL
I
IH
I
OH
I
OL
I
OZ
Parameter Min Typical Max Unit
Standby current
–60 –µA
(Core = 150 MHz, QVDD = 2.0V, temp = 55°C)
Input high voltage 0.7V
DD
–Vdd+0.2V
Input low voltage – – 0.4 V
Output high voltage (IOH= 2.0 mA) 0.7V
DD
–VddV
Output low voltage (IOL= -2.5 mA) – – 0.4 V
Input low leakage current
= GND, no pull-up or pull-down)
(V
IN
Input high leakage current
(V
IN=VDD
, no pull-up or pull-down)
Output high current
=0.8VDD, VDD=1.8V)
(V
OH
Output low current
=0.4V, VDD=1.8V)
(V
OL
Output leakage current
(V
out=VDD
, output is tri-stated)
––±1µA
––±1µA
––4.0mA
-4.0 – – mA
––±5µA
C
i
C
o
Input capacitance – – 5 pF
Output capacitance‘ – – 5 pF
3.5 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system
operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage
from V
DD min
to V
DD max
under an operating temperature from TL to TH. All timing is measured at 30 pF loading.
Table 7. Tristate Signal Timing
Pin Parameter Minimum Maximum Unit
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z – 20.8 ns
Table 8. 32k/16M Oscillator Signal Timing
Parameter Minimum RMS Maximum Unit
EXTAL32k input jitter (peak to peak) – 5 20 ns
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 13
Specifications
Table 8. 32k/16M Oscillator Signal Timing (Continued)
Parameter Minimum RMS Maximum Unit
EXTAL32k startup time 800 – – ms
EXTAL16M input jitter (peak to peak) – TBD TBD –
EXTAL16M startup time TBD – – –
3.6 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
• 32-bit data field
• 7-bit address field
• A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
in Figure 2.
TRACECLK
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
3a
2a
2b
3b
Valid Data
4a
1
Valid Data
4b
Figure 2. Trace Port Timing Diagram
Table 9. Trace Port Timing Diagram Parameter Table
Ref
No.
1 CLK frequency 0 85 0 100 MHz
2a Clock high time 1.3 – 2 – ns
Parameter
1.8V ± 0.10V 3.0V ± 0.30V
Unit
Minimum Maximum Minimum Maximum
2b Clock low time 3 – 2 – ns
MC9328MXL Advance Information, Rev. 5
14 Freescale Semiconductor
Table 9. Trace Port Timing Diagram Parameter Table (Continued)
Specifications
Ref
No.
3a Clock rise time – 4 – 3 ns
3b Clock fall time – 3 – 3 ns
4a Output hold time 2.28 – 2 – ns
4b Output setup time 3.42 – 3 – ns
Parameter
1.8V ± 0.10V 3.0V ± 0.30V
Unit
Minimum Maximum Minimum Maximum
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 15
Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, T
pre-divider and T
is the output double clock period.
dck
is a reference clock period after the
ref
Table 10. DPLL Specifications
Parameter Test Conditions Minimum Typical Maximum Unit
Reference clock freq range Vcc = 1.8V 5 – 100 MHz
Pre-divider output clock
freq range
Double clock freq range Vcc = 1.8V 80 – 220 MHz
Pre-divider factor (PD) – 1 – 16 –
Total multiplication factor (MF) Includes both integer
MF integer part – 5 – 15 –
MF numerator Should be less than the
MF denominator – 1 – 1023 –
Pre-multiplier lock-in time – – – 312.5
Vcc = 1.8V 5 – 30 MHz
5–15–
and fractional parts
0 – 1022 –
denominator
µsec
Freq lock-in time after
full reset
Freq lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Freq jitter (p-p) – – 0.005
Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V – 1.0
Power supply voltage – 1.7 – 2.5 V
Power dissipation FOL mode, integer MF,
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
FPL mode and integer MF (does
not include pre-multi lock-in time)
FPL mode and integer MF (does
not include pre-multi lock-in time)
f
= 200 MHz, Vcc = 1.8V
dck
250 280
(56 µs)
220 250
(50 µs)
300 350
(70 µs)
270 320
(64 µs)
(0.01%)
(10%)
––4mW
300 T
270 T
400 T
370 T
0.01 2•T
1.5 ns
ref
ref
ref
ref
dck
MC9328MXL Advance Information, Rev. 5
16 Freescale Semiconductor
Specifications
3.8 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE:
Be aware that NVDD must ramp up to at least 1.8V before QVDD is
powered up to prevent forward biasing.
90% AVDD
1
POR
10% AVDD
RESET_POR
RESET_DRAM
HRESET
RESET_OUT
CLK32
HCLK
2
Exact 300ms
3
Figure 3. Timing Relationship with POR
7 cycles @ CLK32
4
14 cycles @ CLK32
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 17
Specifications
RESET_IN
5
HRESET
RESET_OUT
CLK32
Ref
No.
HCLK
6
Figure 4. Timing Relationship with RESET_IN
Table 11. Reset Module Timing Parameter Table
1.8V ± 0.10V 3.0V ± 0.30V
Parameter
Min Max Min Max
14 cycles @ CLK32
4
Unit
1 Width of input POWER_ON_RESET
2 Width of internal POWER_ON_RESET
note
1
–
300 300 300 300 ms
note
1
––
(CLK32 at 32 kHz)
3 7K to 32K-cycle stretcher for SDRAM reset 7 7 7 7 Cycles of
CLK32
4 14K to 32K-cycle stretcher for internal system reset
HRESERT
and output reset at pin RESET_OUT
5 Width of external hard-reset RESET_IN
14 14 14 14 Cycles of
CLK32
4 – 4 – Cycles of
CLK32
6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of
CLK32
1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should
allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence.
Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have
developed a working knowledge of start-up time of their crystals. Typically, start-up times range from
400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should
be ignored in calculating timing for the start-up process.
MC9328MXL Advance Information, Rev. 5
18 Freescale Semiconductor
Specifications
3.9 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 12 on page 20 defines the parameters of signals.
(HCLK) Bus Clock
1a 1b
Address
Chip-select
Read (Write
OE
(rising edge)
(falling edge)
OE
EB
(rising edge)
(falling edge)
EB
(negated falling edge)
LBA
LBA
(negated rising edge)
Burst Clock (rising edge)
2a 2b
3b3a
)
4a 4b
4c 4d
5a 5b
5c 5d
6a
6a
7a 7b
7c
6c
7d
6b
Burst Clock (falling edge)
8b
Read Data
9a
8a
9b
Write Data (negated falling)
9a
9c
Write Data (negated rising)
DTACK
10a
10a
Figure 5. EIM Bus Timing Diagram
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 19
Specifications
Ref No. Parameter
1a Clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns
1b Clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns
2a Clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns
2b Clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns
Table 12. EIM Bus Timing Parameter Table
1.8V ± 0.10V 3.0V ± 0.30V
Unit
Min Typical Max Min Typical Max
3a Clock fall to Read (Write
3b Clock fall to Read (Write
4a Clock
4b Clock
4c Clock
4d Clock
5a Clock
5b Clock
5c Clock
5d Clock
6a Clock
6b Clock
6c Clock
7a Clock
1
rise to Output Enable Valid
1
rise to Output Enable Invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns
1
fall to Output Enable Valid 2.38 2.69 7.04 2.3 2.6 6.8 ns
1
fall to Output Enable Invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns
1
rise to Enable Bytes Valid 1.91 2.52 5.54 1.9 2.5 5.5 ns
1
rise to Enable Bytes Invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns
1
fall to Enable Bytes Valid 1.97 2.59 5.69 1.9 2.5 5.5 ns
1
fall to Enable Bytes Invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns
1
fall to Load Burst Address Valid 2.07 2.79 6.73 2.0 2.7 6.5 ns
1
fall to Load Burst Address Invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns
1
rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns
1
rise to Burst Clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns
) Valid 1.35 2.79 6.52 1.3 2.7 6.3 ns
) Invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns
2.32 2.62 6.85 2.3 2.6 6.8 ns
7b Clock
7c Clock
7d Clock
1
rise to Burst Clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns
1
fall to Burst Clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns
1
fall to Burst Clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns
8a Read Data setup time 5.54 – – 5.5 – – ns
8b Read Data hold time 0 – – 0 – – ns
9a Clock
9b Clock
1
rise to Write Data Valid 1.81 2.72 6.85 1.8 2.7 6.8 ns
1
fall to Write Data Invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns
9c Clock1 rise to Write Data Invalid 1.63 – – 1.62 – – ns
10a DTACK
setup time 2.52 – – 2.5 – – ns
1. Clock refers to the system clock signal, HCLK, generated from the System PLL
MC9328MXL Advance Information, Rev. 5
20 Freescale Semiconductor
Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK
signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 13.
HCLK
CS5
3
RW
1
OE
5
EXT_DTACK
2
INT_DTACK
Ref
No.
1CS5
2 External DTACK
3CS5
4 External DTACK
5OE
asserted to OE asserted –T–Tns
asserted
pulse width 3T – 3T – ns
negated
negated after CS5 is negated 0 4.5 0 4 ns
4
Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0
Table 13. Access Cycle Timing Parameters
1.8V ± 0.10V 3.0V ± 0.30V
Characteristic
Min Max Min Max
input setup from CS5
input hold after CS5 is
0–0–ns
0 1.5T 0 1.5T ns
Unit
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK
Freescale Semiconductor 21
input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Advance Information, Rev. 5
Specifications
HCLK
CS5
RW
OE
EXT_DTACK (WAIT)
INT_DTACK
1
Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1
Table 14. Access Cycle Timing Parameters
Ref
No.
1 External DTACK
Characteristic
input setup from CS5
asserted
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
1.8V ± 0.10V 3.0V ± 0.30V
Min Max Min Max
0–0–ns
Unit
MC9328MXL Advance Information, Rev. 5
22 Freescale Semiconductor
3.9.3 EIM External Bus Timing
The timing diagrams in this section show the timing of accesses to memory or a peripheral.
hclk
hsel_weim_cs[0]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
weim_hready
weim_bclk
weim_addr
weim_cs
weim_r/w
weim_lba
Seq/Nonseq
Read
V1
Last Valid Data
Last Valid Address
V1
V1
Read
weim_oe
weim_eb (EBC=0)
weim_eb
(EBC=1)
weim_data_in
V1
Figure 8. WSC = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 23
Specifications
hsel_weim_cs[0]
hclk
htrans
hwrite
haddr
hready
hwdata
weim_hrdata
weim_hready
weim_bclk
weim_addr
weim_cs
[0]
weim_r/w
Nonseq
Write
V1
Last Valid Data
Last Valid Address
Write Data (V1) Unknown
Last Valid Data
V1
Write
weim_lba
weim_oe
weim_eb
weim_data_out
Last Valid Data Write Data (V1)
Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5
24 Freescale Semiconductor
hclk
hsel_weim_cs[0]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
weim_hready
weim_bclk
weim_addr
weim_cs
[0]
weim_r/w
weim_lba
Nonseq
Read
V1
Last Valid Data
Address V1
Read
V1 Word
Address V1 + 2Last Valid Addr
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word 2/2 Half Word
Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor 25
Specifications
hsel_weim_cs[0]
hclk
htrans
hwrite
haddr
hready
hwdata
weim_hrdata
weim_hready
weim_bclk
weim_addr
weim_cs
[0]
weim_r/w
Nonseq
Write
V1
Last Valid Data
Write Data (V1 Word)
Last Valid Data
Address V1
Address V1 + 2Last Valid Addr
Write
weim_lba
weim_oe
weim_eb
weim_data_out
1/2 Half Word 2/2 Half Word
Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5
26 Freescale Semiconductor
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