Freescale MC68Hc912D60A, MC68HC912D60C, MC68HC912D60P Technical Data
MC68Hc912D60A
MC68HC912D60C
MC68HC912D60P
Technical Data
HC12
Microcontrollers
MC68HC912D60A/D
Rev. 3.1
08/2005
freescale.com
MC68HC912D60A
MC68HC912D60C
MC68HC912D60P
Technical Data — Rev. 3.1
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Freescale data sheets
and/or specifications can and do vary in different applications and actual performance
may vary over time. All operating par ameters, including "Typicals" m ust be validated
for each customer application by customer's technical experts. Freescale does not
convey any license under its pa tent rig hts n or th e righ ts of ot hers . Fre esca le pro duc ts
are not designed, intended, or authorized for use as components in systems intended
for surgical implant into the body, or other applications intended to support or sustain
life, or for any other application in which the failure of the Freescale product could
create a situation where personal injury or death may occur. Should Buyer pur chase or
use Freescale products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintend ed or unauthorized use, even if such claim
alleges that Freescale was negligent regarding the design or manufacture of the part.
Freescale, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Freescale, Inc., 2005
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor 3
Technical Data MC68HC912D60A — Rev. 3.1
4 Freescale Semiconductor
Technical Data — MC68HC912D60A
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Section 1. General Description . . . . . . . . . . . . . . . . . . . .23
Section 2. Central Processing Unit . . . . . . . . . . . . . . . . .31
Section 3. Pinout and Signal Descriptions. . . . . . . . . . .37
Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 5. Operating Modes and Resource Mapping . .71
List of Paragraphs
Section 6. Bus Control and Input/Output . . . . . . . . . . . .85
Section 7. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . .97
Section 8. EEPROM Memory . . . . . . . . . . . . . . . . . . . . .105
Section 9. Resets and Interrupts . . . . . . . . . . . . . . . . . .119
Section 10. I/O Ports with Key Wake-up . . . . . . . . . . . .129
Section 11. Clock Functions . . . . . . . . . . . . . . . . . . . . .137
Section 12. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Section 13. Pulse Width Modulator . . . . . . . . . . . . . . . .207
Section 14. Enhanced Capture Timer . . . . . . . . . . . . . .223
Section 15. Multiple Serial Interface . . . . . . . . . . . . . . .263
Section 16. Freescale Interconnect Bus . . . . . . . . . . . .289
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Paragraphs 5
List of Paragraphs
Section 17. MSCAN Controller. . . . . . . . . . . . . . . . . . . .303
Section 18. Analog-to-Digital Converter . . . . . . . . . . . .349
Section 19. Development Support. . . . . . . . . . . . . . . . .377
Section 20. Electrical Specifications. . . . . . . . . . . . . . .405
Section 21. Appendix: CGM Practical Aspects . . . . . .427
Section 22. Appendix: Changes from MC68HC912D60437
Section 23. Appendix: Information on MC68HC912D60A
Mask Set Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
Technical Data MC68HC912D60A — Rev. 3.1
6 List of Paragraphs Freescale Semiconductor
Technical Data — MC68HC912D60A
Technical Data — List of Paragraphs
Technical Data — Table of Contents
Technical Data — List of Figures
Technical Data — List of Tables
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table of Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3 Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . .24
1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6 Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 2. Central Processing Unit
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.6 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.7 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Table of Contents 7
Table of Contents
Section 3. Pinout and Signal Descriptions
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 MC68HC912D60A Pin Assignments in 112-pin QFP. . . . . . . .38
3.3 MC68HC912D60A Pin Assignments in 80-pin QFP. . . . . . . . .40
3.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.5 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.6 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Section 4. Registers
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.2 Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 5. Operating Modes and Resource Mapping
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.5 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.6 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Section 6. Bus Control and Input/Output
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.3 Detecting Access Type from External Signals . . . . . . . . . . . . .85
6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Section 7. Flash Memory
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Technical Data MC68HC912D60A — Rev. 3.1
8 Table of Contents Freescale Semiconductor
Table of Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . .98
7.5 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.6 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.8 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .101
7.9 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .103
7.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.11 Flash protection bit FPOPEN . . . . . . . . . . . . . . . . . . . . . . . . .104
Section 8. EEPROM Memory
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.3 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . .106
8.4 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .107
8.5 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .108
8.6 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.7 Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.8 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . .116
Section 9. Resets and Interrupts
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.3 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.4 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
9.5 Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .123
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Table of Contents 9
Table of Contents
9.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.7 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.8 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.9 Customer Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Section 10. I/O Ports with Key Wake-up
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .130
10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Section 11. Clock Functions
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
11.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .141
11.6 Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . .143
11.7 System Clock Frequency formulas. . . . . . . . . . . . . . . . . . . . .162
11.8 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
11.9 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .166
11.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
11.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
11.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Section 12. Oscillator
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Technical Data MC68HC912D60A — Rev. 3.1
10 Table of Contents Freescale Semiconductor
Table of Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
12.3 MC68HC912D60A Oscillator Specification. . . . . . . . . . . . . . .176
12.4 MC68HC912D60C Colpitts Oscillator Specification . . . . . . . .179
12.5 MC68HC912D60P Pierce Oscillator Specification . . . . . . . . .194
Section 13. Pulse Width Modulator
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.3 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .210
13.4 PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Section 14. Enhanced Capture Timer
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
14.3 Enhanced Capture Timer Modes of Operation. . . . . . . . . . . .230
14.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
14.5 Timer and Modulus Counter Operation in Different Modes . .261
Section 15. Multiple Serial Interface
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
15.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
15.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .264
15.5 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . .276
15.6 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
Section 16. Freescale Interconnect Bus
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Table of Contents 11
Table of Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
16.3 Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
16.4 Biphase coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
16.5 Message validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
16.6 Interfacing to MI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
16.7 MI Bus clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
16.8 SCI0/MI Bus registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Section 17. MSCAN Controller
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
17.5 Identifier Acceptance Filter. . . . . . . . . . . . . . . . . . . . . . . . . . .310
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
17.7 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .316
17.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
17.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
17.12 Programmer’s Model of Message Storage. . . . . . . . . . . . . . .325
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .330
Section 18. Analog-to-Digital Converter
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
18.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
Technical Data MC68HC912D60A — Rev. 3.1
12 Table of Contents Freescale Semiconductor
Table of Contents
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
18.5 ATD Operational Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
18.6 ATD Operation In Different MCU Modes . . . . . . . . . . . . . . . .355
18.7 General Purpose Digital Input Port Operation . . . . . . . . . . . .357
18.8 Application Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . .358
18.9 ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
Section 19. Development Support
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
19.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
19.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .379
19.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
19.6 Instruction Tagging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
Section 20. Electrical Specifications
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
20.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Section 21. Appendix: CGM Practical Aspects
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
21.3 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .427
21.4 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .433
Section 22. Appendix: Changes from MC68HC912D60
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Table of Contents 13
Table of Contents
22.2 Significant changes from the MC68HC912D60
(non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
Section 23. Appendix: Information on MC68HC912D60A
Mask Set Changes
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
23.3 Flash Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
23.4 Clock Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444
23.5 Pseudo Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444
23.6 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444
23.7 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445
Technical Data — Glossary
Technical Data — Revision History
23.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
23.9 Changes from Rev 2.0 to Rev 3.0 . . . . . . . . . . . . . . . . . . . . .457
23.10 Major Changes From Rev 1.0 to Rev 2.0. . . . . . . . . . . . . . . .457
23.11 Major Changes From Rev 0.0 to Rev 1.0. . . . . . . . . . . . . . . .458
Technical Data MC68HC912D60A — Rev. 3.1
14 Table of Contents Freescale Semiconductor
Technical Data — MC68HC912D60A
Figure Title Page
1-1 MC68HC912D60A 112-pin QFP Block Diagram . . . . . . . . . . .29
1-2 MC68HC912D60A 80-pin QFP Block Diagram . . . . . . . . . . . .30
2-1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3-1 Pin Assignments in 112-pin TQFP for MC68HC912D60A . . . .38
3-2 112-pin TQFP Mechanical Dimensions (case no987) . . . . . . .39
3-3 Pin Assignments in 80-pin QFP for MC68HC912D60A . . . . . .40
3-4 80-pin QFP Mechanical Dimensions (case no841B) . . . . . . . .41
3-5 PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .43
3-6 External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .45
5-1 MC68HC912D60A Memory Map . . . . . . . . . . . . . . . . . . . . . . .83
6-1 Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .86
10-1 STOP Key Wake-up Filter (falling edge trigger) timing. . . . . .135
11-1 Internal Clock Relationships. . . . . . . . . . . . . . . . . . . . . . . . . .139
11-2 PLL Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .144
11-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .146
11-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .149
11-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .164
11-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
11-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .166
12-1 MC68HC912D60A Colpitts Oscillator Architecture. . . . . . . . .177
12-2 MC68HC912D60C Colpitts Oscillator Architecture. . . . . . . . .180
12-3 MC68HC912D60C Crystal with DC Blocking Capacitor. . . . .192
12-4 MC68HC912D60P Pierce Oscillator Architecture. . . . . . . . . .195
13-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .208
13-2 Block Diagram of PWM Center-Aligned Output Channel . . . .209
13-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
14-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .225
14-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .226
List of Figures
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Figures 15
List of Figures
14-3 8-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . . .227
14-4 16-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . .228
14-5 Block Diagram for Port7 with Output compare /
Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
14-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .229
15-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .264
15-2 Serial Communications Interface Block Diagram . . . . . . . . . .265
15-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .277
15-4 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .278
15-5 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .279
15-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .280
16-1 MI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
16-2 Biphase coding and error detection . . . . . . . . . . . . . . . . . . . .292
16-3 MI BUS Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
16-4 A typical MI Bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . .295
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . .308
17-3 32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .312
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .312
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .313
17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .319
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
17-8 Segments within the Bit Time. . . . . . . . . . . . . . . . . . . . . . . . .323
17-9 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
17-10 Message Buffer Organization. . . . . . . . . . . . . . . . . . . . . . . . .325
17-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
17-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
18-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .350
19-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .381
19-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .381
19-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .382
20-1 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
20-2 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .415
20-3 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .416
20-4 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .417
20-5 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
20-6 Port Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .419
20-7 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419
Technical Data MC68HC912D60A — Rev. 3.1
16 List of Figures Freescale Semiconductor
List of Figures
20-8 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . .421
20-9 SPI Timing Diagram (1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . .423
20-10 SPI Timing Diagram (2 of 2). . . . . . . . . . . . . . . . . . . . . . . . . .424
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Figures 17
List of Figures
Technical Data MC68HC912D60A — Rev. 3.1
18 List of Figures Freescale Semiconductor
Technical Data — MC68HC912D60A
Table Title Page
1-1 Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27
1-2 Development Tools Ordering Information. . . . . . . . . . . . . . . . .28
2-1 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .34
2-2 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .35
3-1 MC68HC912D60A Power and Ground Connection Summary.44
3-2 MC68HC912D60A Signal Description Summary . . . . . . . . . . .50
3-3 MC68HC912D60A Port Description Summary. . . . . . . . . . . . .59
3-4 Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .60
4-1 MC68HC912D60A Register Map . . . . . . . . . . . . . . . . . . . . . . .62
5-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5-2 Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
5-3 RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .82
5-4 EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .82
8-1 EEDIV Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8-2 1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .112
8-3 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8-4 Shadow word mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9-1 Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9-2 Stacking Order on Entry to Interrupts. . . . . . . . . . . . . . . . . . .128
11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .155
11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .155
11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .169
11-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .212
13-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . .222
13-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .222
14-1 Compare Result Output Action. . . . . . . . . . . . . . . . . . . . . . . .238
14-2 Edge Detector Circuit Configuration. . . . . . . . . . . . . . . . . . . .238
List of Tables
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Tables 19
List of Tables
14-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15-1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
15-2 Loop Mode Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
15-3 SS Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
15-4 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
16-1 MI Bus Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
17-1 msCAN12 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .315
17-2 msCAN12 vsCPU operating modes . . . . . . . . . . . . . . . . . . . .317
17-3 CAN Standard Compliant Bit Time Segment Settings . . . . . .323
17-4 Data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
17-5 Synchronization jump width . . . . . . . . . . . . . . . . . . . . . . . . . .333
17-6 Baud rate prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
17-7 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
17-8 Time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
17-9 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .341
17-10 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . .342
18-1 Result Data Formats Available. . . . . . . . . . . . . . . . . . . . . . . .361
18-2 Left Justified ATD Output Codes . . . . . . . . . . . . . . . . . . . . . .362
18-3 ATD Response to Background Debug Enable . . . . . . . . . . . .364
18-4 Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .365
18-5 Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
18-6 Conversion Sequence Length Coding . . . . . . . . . . . . . . . . . .367
18-7 Result Register Assignment for Different Conversion
Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
18-8 Special Channel Conversion Select Coding. . . . . . . . . . . . . .368
18-9 Analog Input Channel Select Coding . . . . . . . . . . . . . . . . . . .369
18-10 Multichannel Mode Result Register Assignment (MULT=1). .370
19-1 IPIPE Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
19-2 Hardware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
19-3 BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . .385
19-4 BDM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
19-5 TTAGO Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
19-6 TTAGO Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
19-7 Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
19-8 REGN Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
19-9 Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
19-10 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . .399
19-11 Breakpoint Read/Write Control. . . . . . . . . . . . . . . . . . . . . . . .401
Technical Data MC68HC912D60A — Rev. 3.1
20 List of Tables Freescale Semiconductor
List of Tables
19-12 Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
20-1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
20-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .408
20-4 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
20-5 ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .409
20-6 Analog Converter Characteristics (Operating) . . . . . . . . . . . .410
20-7 ATD AC Characteristics (Operating). . . . . . . . . . . . . . . . . . . .410
20-8 ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
20-9 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
20-10 Flash EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . .412
20-11 Pulse Width Modulator Characteristics. . . . . . . . . . . . . . . . . .412
20-12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
20-13 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
20-14 Multiplexed Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . .420
20-15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
20-16 CGM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
20-17 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
20-18 Key Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
20-19 msCAN12 Wake-up Time from Sleep Mode. . . . . . . . . . . . . .426
21-1 Suggested 8MHz Synthesis PLL Filter Elements
(Tracking Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
21-2 Suggested 8MHz Synthesis PLL Filter Elements
(Acquisition Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Tables 21
List of Tables
Technical Data MC68HC912D60A — Rev. 3.1
22 List of Tables Freescale Semiconductor
Technical Data — MC68HC912D60A
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3 Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . .24
1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6 Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.2 Introduction
The MC68HC912D60A microcontroller unit (MCU) is a 16-bit device
available in two package options, 80-pin QFP and 112-pin TQFP. Onchip peripherals include a 16-bit central processing unit (CPU12), 60K
bytes of flash EEPROM, 2K bytes of RAM, 1K bytes of EEPROM, two
asynchronous serial communication interfaces (SCI), a serial peripheral
interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP)
8-channel,10-bit analog-to-digital converters (ATD), a four-channel
pulse-width modulator (PWM), and a CAN 2.0 A, B software compatible
module (MSCAN12). System resource mapping, clock generation,
interrupt control and bus interfacing are managed by the lite integration
module (LIM). The MC68HC912D60A has full 16-bit data paths
throughout, however, the external bus can operate in an 8-bit narrow
mode so single 8-bit wide memory can be interfaced for lower cost
systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements. In addition
to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins
are available with Key-Wake-Up capability from STOP or WAIT mode.
Section 1. General Description
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor General Description 23
General Description
1.3 Devices Covered in this Document
The MC68HC912D60C and MC68HC912D60P are devices similar to
the MC68HC912D60A, but with different oscillator configurations. Refer
to Section 12. Oscillator for more details.
The generic term MC68HC912D60A is used throughout this document
to mean all derivatives mentioned above, except in Section 12.
Oscillator, where it refers only to the MC68HC912D60A device.
1.4 Features
• 16-bit CPU12
– U pward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to
M68HC11
– 20-bit ALU
– Instruction queue
– Enhanced indexed addressing
• Multiplexed bus
– S ingle chip or expanded
– 16 address/16 data wide or 16 address/8 data narrow mode
• Two 8-bit ports with key wake-up interrupt (2 pins only are
2
available on 80QFP) and one I
only)
•Memory
– 60K byte flash EEPROM, made of a 28K module and a 32K
module with 8K bytes protected BOOT section in each module
(MC68HC912D60A)
– 1K byte EEPROM
–2K byte RAM
C start bit detector (112TQFP
Technical Data MC68HC912D60A — Rev. 3.1
24 General Description Freescale Semiconductor
General Description
Features
• Analog-to-digital converters
– 2 x 8-channels, 10-bit resolution in 112TQFP
– 1 x 8-channels, 8-bit resolution in 80QFP
• 1M bit per second, CAN 2.0 A, B software compatible module
– Two receive and three transmit buffers
– F lexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8x8bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– In 80QFP, only TxCAN and RxCAN pins are available
– Loop-back for self test operation
– Programmable link to a timer input capture channel, for time-
stamping and network synchronization.
• Enhanced capture timer (ECT)
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels; 4
of the 8 input captures with buffer
– Input capture filters and buffers, three successive captures on
four channels, or two captures on four channels with a
capture/compare selectable on the remaining four
– Four 8-bit or two 16-bit pulse accumulators
– 16-bit modulus down-counter with 4-bit prescaler
– Four user-selectable delay counters for signal filtering
• 4 PWM channels with programmable period and duty cycle
– 8-bit 4-channel or 16-bit 2-channel
– Separate control for each pulse width and duty cycle
– Center- or left-aligned outputs
– Programmable clock select logic with a wide range of
frequencies
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor General Description 25
General Description
• Serial interfaces
– Two asynchronous serial communications interfaces (SCI)
– MI-Bus implemented on final devices
– Synchronous serial peripheral interface (SPI)
• LIM (light integration module)
– WCR (windowed COP watchdog, real time interrupt, clock
monitor)
– ROC (reset and clocks)
– MEBI (multiplexed external bus interface)
– MBI (internal bus interface and map)
– INT (interrupt control)
• Clock generation
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Slow mode divider
– Low power 0.5 to 16 MHz crystal oscillator reference clock
– Option of a Pierce or Colpitts oscillator
• 112-Pin TQFP package or 80-pin QFP package
– Up to 68 general-purpose I/O lines, plus up to 18 input-only
lines in 112TQFP
or
Up to 48 general-purpose I/O lines, plus up to 10 input-only
lines in 80QFP
• 8MHz operation at 5V
• Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
Technical Data MC68HC912D60A — Rev. 3.1
26 General Description Freescale Semiconductor
1.5 Ordering Information
Package
General Description
Ordering Information
Table 1-1. Device Ordering Information
Ambient Temperature
Order Number
Range Designator
112-Pin TQFP
Single Tray
60 Pcs
80-Pin TQFP
Single Tray
84 Pcs
112-Pin TQFP
Single Tray
60 Pcs
80-Pin TQFP
Single Tray
84 Pcs
112-Pin TQFP
Single Tray
60 Pcs
–40 to +85°C C MC912D60ACPV8
–40 to +105°C V MC912D60AVPV8
–40 to +125°C M* MC912D60AMPV8
–40 to +85°C C MC912D60ACFU8
–40 to +105°C V MC912D60AVFU8
–40 to +125°C M* MC912D60AMFU8
–40 to +85°C C MC912D60CCPV8
–40 to +105°C V MC912D60CVPV8
–40 to +125°C M* MC912D60CMPV8
–40 to +85°C C MC912D60CCFU8
–40 to +105°C V MC912D60CVFU8
–40 to +125°C M* MC912D60CMFU8
–40 to +85°C C MC912D60PCPV8
–40 to +105°C V MC912D60PVPV8
–40 to +125°C M* MC912D60PMPV8
80-Pin TQFP
Single Tray
84 Pcs
–40 to +85°C C MC912D60PCFU8
–40 to +105°C V MC912D60PVFU8
–40 to +125°C M* MC912D60PMFU8
* Important: M temperature operation is available only for single chip
modes
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor General Description 27
General Description
Table 1-2. Development Tools Ordering Information
Description Name Order Number
MCUez Free from World Wide Web
Serial Debug Interface SDI
Evaluation board EVB
M68SDIL (3–5V), M68DIL12 (SDIL + MCUez +
SDBUG12)
M68EVB912D60 (EVB only)
M68KIT912D60 (EVB + SDIL12)
NOTE: SDBUG12 is a P & E Micro Product. It can be obtained from P & E from
their web site (http://www.pemicro.com) for approximately $100.
Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.html
Technical Data MC68HC912D60A — Rev. 3.1
28 General Description Freescale Semiconductor
1.6 Block Diagrams
General Description
Block Diagrams
TxCAN
DDRG
PORTG
Figure 1-1. MC68HC912D60A 112-pin QFP Block Diagram
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor General Description 29
General Description
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
TxCAN
PG7
KWG6
KWG5
KWG4
KWG3
KWG2
KWG1
KWG0
DDRG
DDRH
PG4
PORTG
PORTH
Figure 1-2. MC68HC912D60A 80-pin QFP Block Diagram
Technical Data MC68HC912D60A — Rev. 3.1
30 General Description Freescale Semiconductor
Loading...