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The MC68HC908SR12 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
Features of the MC68HC908SR12 include the following:
•High-performance M68HC08 architecture
•Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
•Maximum internal bus frequency:
–8-MHz at 5V operating voltage
–4-MHz at 3V operating voltage
•Clock input options:
–RC-oscillator
–32kHz crystal-oscillator with 32MHz internal phase-lock-loop
•12k-bytes user program FLASH memory with security1 feature
•512 bytes of on-chip RAM
•Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, and PWM
capability on each channel
•Timebase module
•3-channel, 8-bit high speed PWM (125kHz) with independent
counters and automatic phase control
•Serial communications interface module (SCI)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
36General DescriptionFreescale Semiconductor
General Description
Features
•System Management Bus (SMBus), version 1.0/1.1
(Multi-master IIC bus)
•14-channel, 10-bit analog-to-digital converter (ADC), with
auto-scan mode for 4 channels
•Current sensor with programmable amplifier
•Temperature sensor (–20°C to +70°C)
•IRQ1 external interrupt pin with integrated pullup
•IRQ2 external interrupt pin with programmable pullup
•8-bit keyboard wakeup port with integrated pullup
•31 general-purpose input/output (I/O) pins and 2 dedicated pins:
–31 shared-function I/O pins
–Two dedicated analog input pins
•Low-power design (fully static with Stop and Wait modes)
•Master reset pin (with integrated pullup) and power-on reset
•System protection features
–Optional computer operating properly (COP) reset
–Low-voltage detection with optional reset
–Illegal opcode detection with reset
–Illegal address detection with reset
•Specific features of the MC68HC908SR12 in 42-pin SDIP are:
–29 general-purpose l/Os only
–11-channel ADC only
Features of the CPU08 include the following:
•Enhanced HC05 programming model
•Extensive loop control functions
•16 addressing modes (eight more than the HC05)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorGeneral Description37
General Description
•16-bit Index register and stack pointer
•Memory-to-memory data transfers
•Fast 8 × 8 multiply instruction
•Fast 16/8 divide instruction
•Binary-coded decimal (BCD) instructions
•Optimization for controller applications
•Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908SR12.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
38General DescriptionFreescale Semiconductor
Freescale SemiconductorGeneral Description39
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
CONTROL AND STATUS REGISTERS — 96 BYTES
2-CHANNEL TIMER INTERFACE
2-CHANNEL TIMER INTERFACE
MODULE 1
MODULE 2
DDRA
PORTA
PTA7/T1CH1
PTA6/T1CH0
PTA5/ATD7 – PTA0/ATD2
‡
USER FLASH — 12,288 BYTES
PTB6/IRQ2
PTB5/T2CH1
PTB4/T2CH0
PTB3//SCL1/RxD
PTB2/SDA1/TxD
PTB1/SCL0
PTB0/SDA0
PTC7/ATD12
PTC6/ATD11
PTC5/ATD10
PTC4/ATD9
PTC3/ATD8
†
†
‡ #
‡ #
‡
‡
‡
PTC2/PWM2
PTC1/PWM1
PTC0/PWM0/CD
†
†
USER RAM — 512 BYTES
MONITOR ROM — 368 BYTES
USER FLASH VECTORS — 38 BYTES
OSCILLATORS AND
CLOCK GENERATOR MODULE
INTERNAL OSCILLATOR
OSC1
OSC2
CGMXFC
RC OSCILLATOR
X-TAL OSCILLATOR
PHASE-LOCKED LOOP
TIMEBASE
MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
MULTI-MASTER IIC (SMBUS)
INTERFACE MODULE
PULSE WIDTH MODULATOR
MODULE
8-BIT KEYBOARD
INTERRUPT MODULE
DDRB
DDRC
PORTB
PORTC
* RST
* IRQ1
** IRQ2
OPIN1/ATD0
#
OPIN2/ATD1
V
V
V
SSAM
REFH
REFL
V
V
V
DDA
V
SSA
SYSTEM INTEGRATION
MODULE
EXTERNAL IRQ
MODULE
COMPUTER OPERATING
PROPERLY MODULE
LOW-VOLTAGE
INHIBIT MODULE
DDRD
PORTD
PTD7/KBI7 – PTD0/KBI0 ***
ANALOG
MODULE
POWER-ON RESET
MODULE
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
* Pin contains integrated pullup device.
MCU Block Diagram
General Description
** Pin contains configurable pullup device.
DD
SS
POWER
*** Pin contains integrated pullup device for KBI functions.
† Pin is open-drain when configured as output.
‡ High current drive pin (for LED).
# Pin not bonded on 42-pin SDIP.
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
MCU
must be grounded for proper MCU operation.
V
SS
1.6.2 Oscillator Pins (OSC1 and OSC2)
V
DD
C1
0.1 µF
+
C2
V
DD
NOTE: Component values shown
represent typical applications.
V
SS
Figure 1-4. Power Supply Bypassing
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Section 7. Oscillator (OSC) and Section 8. Clock
Generator Module (CGM).
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
42General DescriptionFreescale Semiconductor
1.6.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known start-up state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor. See Section 9. System Integration Module (SIM).
1.6.4 External Interrupt Pin (IRQ1)
IRQ1 is an asynchronous external interrupt pin. This pin contains an
internal pullup resistor. See Section 19. External Interrupt (IRQ).
General Description
Pin Functions
1.6.5 Analog Power Supply Pin (V
V
is the power supply pin for the analog circuits of the MCU.
DDA
1.6.6 Analog Ground Pin (V
V
SSA
)
SSA
is the power supply ground pin for the analog circuits of the MCU.
DDA
)
It should be decoupled as per the VSS digital ground pin.
1.6.7 ADC Voltage Low Reference Pin (V
V
is the voltage input pin for the ADC voltage low reference. See
REFL
Section 15. Analog-to-Digital Converter (ADC).
1.6.8 ADC Voltage High Reference Pin (V
V
is the voltage input pin for the ADC voltage high reference. See
REFH
Section 15. Analog-to-Digital Converter (ADC).
REFL
REFH
)
)
1.6.9 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See
Section 8. Clock Generator Module (CGM).
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorGeneral Description43
General Description
1.6.10 Analog Input Pins (OPIN1/ATD0, OPIN2/ATD1, V
OPIN1/ATD0 and OPIN2/ATD1 are input pins to the analog module and
ADC and V
is the negative reference input. See Section 14.
SSAM
Analog Module and Section 15. Analog-to-Digital Converter (ADC).
1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are special function, bidirectional port pins.
PTA7/T1CH1–PTA6/T1CH0 are shared with the TIM1, and
PTA5/ATD7–PTA0/ATD2 are shared with the ADC. See Section 18.
and Section 15. Analog-to-Digital Converter (ADC).
1.6.12 Port B I/O Pins (PTB6–PTB0)
PTB6–PTB0 are special function, bidirectional port pins. PTB6/IRQ2 is
shared with the IRQ2 input, PTB5/T2CH1–PTB4/T2CH0 are shared with
the TIM2, PTB3/SCL1/RxD–PTB2/SDA1/TxD are shared with the
MMIIC and SCI, and PTB1/SCL0–PTB0/SDA0 are shared with the
MMIIC. See Section 18. Input/Output (I/O) Ports, Section 19.
PTC7–PTC0 are special function, bidirectional port pins.
PTC7/ATD12–PTC3/ATD8 are shared with the ADC,
PTC2/PWM2–PTC1/PWM1 are shared with the PWM, and
PTC0/PWM0/CD is shared with the PWM and analog module. See
The CPU08 can address 64k-bytes of memory space. The memory
map, shown in Figure 2-1, includes:
•12,288 bytes of user FLASH memory
•512 bytes of random-access memory (RAM)
•38 bytes of user-defined vectors
•368 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address
reset. In the memory map (Figure 2-1) and in register figures in this
document, unimplemented locations are shaded.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorMemory Map45
Memory Map
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page
$0000–$005F. Additional I/O registers have the following addresses:
•$FE00; SIM break status register, SBSR
•$FE01; SIM reset status register, SRSR
•$FE03; SIM break flag control register, SBFCR
•$FE04; Interrupt status register 1, INT1
•$FE05; Interrupt status register 2, INT2
•$FE06; Interrupt status register 3, INT3
•$FE07; Reserved
•$FE08; FLASH control register, FLCR
•$FE09; FLASH block protect register, FLBPR
•$FE0A; Reserved
•$FE0B; Reserved
•$FE0C; break address register high, BRKH
•$FE0D; break address register low, BRKL
•$FE0E; break status and control register, BRKSCR
•$FE0F; LVI status register, LVISR
•$FF80; Mask option register, MOR
•$FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2, Table 2-1 is a list of vector
locations.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
46Memory MapFreescale Semiconductor
Memory Map
Input/Output (I/O) Section
$0000
↓
$005F
$0060
↓
$025F
$0260
↓
$BFFF
$C000
↓
$EFFF
$F000
↓
$FDFF
$FE00SIM Break Status Register (SBSR)
$FE01SIM Reset Status Register (SRSR)
$FE02Reserved
$FE03SIM Break Flag Control Register (SBFCR)
$FE04Interrupt Status Register 1 (INT1)
$FE05Interrupt Status Register 2 (INT2)
$FE06Interrupt Status Register 3 (INT3)
$FE07Reserved
$FE08FLASH Control Register (FLCR)
$FE09FLASH Block Protect Register (FLBPR)
$FE0AReserved
$FE0BReserved
$FE0CBreak Address Register High (BRKH)
$FE0DBreak Address Register Low (BRKL)
$FE0EBreak Status and Control Register (BRKSCR)
$FE0FLVI Status Register (LVISR)
$FE10
↓
$FF7F
$FF80Mask Option Register
$FF81
↓
$FFD9
$FFDA
↓
$FFFF
I/O Registers
96 Bytes
RAM
512 Bytes
Unimplemented
48,544 Bytes
FLASH Memory
12,288 Bytes
Unimplemented
3,584 Bytes
Monitor ROM
368 Bytes
Reserved
89 Bytes
FLASH Vectors
38 Bytes
Figure 2-1. Memory Map
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorMemory Map47
Memory Map
Addr.Register NameBit 7654321Bit 0
Read:
$0000
$0001
$0002
$0003
$0004
$0005
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Write:
Reset:UUUUUUUU
Read:0
Write:
Reset:0 UUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
Read:0
Write:
Reset:00000000
PTA7PTA6PTA5PTA4PTA3PTA2PTA1PTA0
PTB6PTB5PTB4PTB3PTB2PTB1PTB0
PTC7PTC6PTC5PTC4PTC3PTC2PTC1PTC0
PTD7PTD6PTD5PTD4PTD3PTD2PTD1PTD0
DDRA7DDRA6DDRA5DDRA4DDRA3DDRA2DDRA1DDRA0
DDRB6DDRB5DDRB4DDRB3DDRB2DDRB1DDRB0
Data Direction Register C
$0006
Data Direction Register D
$0007
$0008Unimplemented
$0009Unimplemented
(DDRC)
(DDRD)
U = UnaffectedX = Indeterminate
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
Write:
Reset:
DDRC7DDRC6DDRC5DDRC4DDRC3DDRC2DDRC1DDRC0
DDRD7DDRD6DDRD5DDRD4DDRD3DDRD2DDRD1DDRD0
= UnimplementedR= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
48Memory MapFreescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register NameBit 7654321Bit 0
Read:
$000AUnimplemented
$000BUnimplemented
Port-A LED Control
$000C
Port-C LED Control
$000D
Analog Module Control
$000E
Analog Module Gain
$000F
Register
(LEDA)
Register
(LEDC)
Register
(AMCR)
Control Register
(AMGCR)
Write:
Reset:
Read:
Write:
Reset:
Read:00
Write:
Reset:00000000
Read:
LEDC7LEDC6LEDC5LEDC4LEDC3
Write:
Reset:00000000
Read:
PWR1PWR0OPCH1OPCH0AMIENDO2DO1DO0
Write:
Reset:00000000
Read:
GAINB3GAINB2GAINB1GAINB0GAINA3GAINA2GAINA1GAINA0
Write:
Reset:00000000
LEDA5LEDA4LEDA3LEDA2LEDA1LEDA0
000
Analog Module Status and
$0010
$0011Unimplemented
$0012Unimplemented
$0013
Control Register
(AMSCR)
SCI Control Register 1
(SCC1)
U = UnaffectedX = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12)
Read:
AMCDIV1 AMCDIV0
Write:OPIFR
Reset:00U000U0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
LOOPSENSCITXINVMWAKEILTYPENPTY
Write:
Reset:00000000
0OPIF0DOF0CDIF
CDIFR
= UnimplementedR= Reserved
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorMemory Map49
Memory Map
Addr.Register NameBit 7654321Bit 0
Read:
$0014
$0015
$0016
$0017
$0018
$0019
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
SCI Baud Rate Register
(SCBR)
Write:
Reset:00000000
Read:R8
Write:
Reset:UU000000
Read:SCTETCSCRFIDLEORNFFEPE
Write:
Reset:11000000
Read:000000BKFRPF
Write:
Reset:00000000
Read:R7R6R5R4R3R2R1R0
Write:T7T6T5T4T3T2T1T0
Reset:UUUUUUUU
Read:00
Write:
Reset:0000000
SCTIETCIESCRIEILIETERERWUSBK
T8DMAREDMATEORIENEIEFEIEPEIE
SCP1SCP0RSCR2SCR1SCR0
Keyboard Status and
$001A
Keyboard Interrupt Enable
$001B
IRQ2 Status and Control
$001C
$001D
Configuration Register 2
Read:0000KEYF0
Control Register
(KBSCR)
Register
(KBIER)
Register
(INTSCR2)
(CONFIG2)
U = UnaffectedX = Indeterminate
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:0
Write:
Reset:00000000
Read:
Write:
†
Reset:00000000
KBIE7KBIE6KBIE5KBIE4KBIE3KBIE2KBIE1KBIE0
PTBPUE6
STOP_
ICLKEN
RCLKEN
STOP_
00IRQ2F0
STOP_
XCLKEN
OSCCLK1 OSCCLK0
= UnimplementedR= Reserved
ACKK
ACK2
0
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
IMASKKMODEK
IMASK2MODE2
CDOEN
SCIBDSRC
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
50Memory MapFreescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register NameBit 7654321Bit 0
IRQ1 Status and Control
$001E
$001F
† One-time writable register after each reset.
$0020
$0021
$0022
$0023
Configuration Register 1
Timer 1 Status and
Timer 1 Counter Modulo
Register
(INTSCR1)
(CONFIG1)
Control Register
(T1SC)
Timer 1 Counter
Register High
(T1CNTH)
Timer 1 Counter
Register Low
(T1CNTL)
Register High
(T1MODH)
Read:0000IRQ1F0
Write:ACK1
Reset:00000000
Read:
Write:
†
Reset:00000000
Read:TOF
Write:0TRST
Reset:00100000
Read:Bit 1514131211109Bit 8
Write:
Reset:00000000
Read:Bit 7654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
IMASK1MODE1
COPRSLVISTOP LVIRSTD LVIPWRD LVI5OR3SSRECSTOPCOPD
TOIETSTOP
Bit 1514131211109Bit 8
00
PS2PS1PS0
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read:CH0F
CH0IEMS0BMS0AELS0BELS0ATOV0CH0MAX
Write:0
Reset:00000000
Read:
Bit 1514131211109Bit 8
Write:
Reset:XXXXXXXX
= UnimplementedR= Reserved
$0024
$0025
$0026
Timer 1 Counter Modulo
Register Low
(T1MODL)
Timer 1 Channel 0 Status
and Control Register
(T1SC0)
Timer 1 Channel 0
Register High
(T1CH0H)
U = UnaffectedX = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorMemory Map51
Memory Map
Addr.Register NameBit 7654321Bit 0
Timer 1 Channel 0
$0027
Timer 1 Channel 1 Status
$0028
$0029
$002A
$002B
$002C
Register Low
(T1CH0L)
and Control Register
(T1SC1)
Timer 1 Channel 1
Register High
(T1CH1H)
Timer 1 Channel 1
Register Low
(T1CH1L)
Timer 2 Status and
Control Register
(T2SC)
Timer 2 Counter
Register High
(T2CNTH)
Read:
Write:
Reset:XXXXXXXX
Read:CH1F
Write:0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read:TOF
Write:0TRST
Reset:00100000
Read:Bit 1514131211109Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0
CH1IE
Bit 1514131211109Bit 8
Bit 7654321Bit 0
TOIETSTOP
0
MS1AELS1BELS1ATOV1CH1MAX
00
PS2PS1PS0
$002D
$002E
$002F
$0030
Timer 2 Counter
Register Low
(T2CNTL)
Timer 2 Counter Modulo
Register High
(T2MODH)
Timer 2 Counter Modulo
Register Low
(T2MODL)
Timer 2 Channel 0 Status
and Control Register
(T2SC0)
U = UnaffectedX = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 12)
Read:Bit 7654321Bit 0
Write:
Reset:00000000
Read:
Bit 1514131211109Bit 8
Write:
Reset:11111111
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read:CH0F
CH0IEMS0BMS0AELS0BELS0ATOV0CH0MAX
Write:0
Reset:00000000
= UnimplementedR= Reserved
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
52Memory MapFreescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register NameBit 7654321Bit 0
$0031
$0032
$0033
$0034
$0035
$0036
Timer 2 Channel 0
Register High
(T2CH0H)
Timer 2 Channel 0
Register Low
(T2CH0L)
Timer 2 Channel 1 Status
and Control Register
(T2SC1)
Timer 2 Channel 1
Register High
(T2CH1H)
Timer 2 Channel 1
Register Low
(T2CH1L)
PLL Control Register
(PTCL)
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read:CH1F
Write:0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:00100000
Bit 1514131211109Bit 8
Bit 7654321Bit 0
CH1IE
Bit 1514131211109Bit 8
Bit 7654321Bit 0
PLLF
PLLIE
0
MS1AELS1BELS1ATOV1CH1MAX
PLLONBCSPRE1PRE0VPR1VPR0
$0037
$0038
$0039
$003A
PLL Bandwidth Control
Register
(PBWC)
PLL Multiplier Select
Register High
(PMSH)
PLL Multiplier Select
Register Low
(PMSL)
PLL VCO Range Select
Register
(PMRS)
U = UnaffectedX = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12)
Read:
AUTO
Write:
Reset:0000000
Read:0000
Write:
Reset:00000000
Read:
MUL7MUL6MUL5MUL4MUL3MUL2MUL1MUL0
Write:
Reset:01000000
Read:
VRS7VRS6VRS5VRS4VRS3VRS2VRS1VRS0
Write:
Reset:01000000
LOCK
ACQ
0000
R
MUL11MUL10MUL9MUL8
= UnimplementedR= Reserved
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorMemory Map53
Memory Map
Addr.Register NameBit 7654321Bit 0
PLL Reference Divider
$003B
$003CUnimplemented
$003DUnimplemented
$003EUnimplemented
$003FUnimplemented
Select Register
$0040Unimplemented
(PMDS)
Read:0000
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
0
00
0
RDS3RDS2RDS1RDS0
0001
$0041Unimplemented
$0042Unimplemented
$0043Unimplemented
$0044Unimplemented
U = UnaffectedX = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
This section describes the 512 bytes of RAM (random-access memory).
3.3 Functional Description
Addresses $0060 through $025F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K-byte memory space.
NOTE:For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE:Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorFLASH Memory63
FLASH Memory
Addr.Register NameBit 7654321Bit 0
Read:0000
$FE08
$FE09
FLASH Control Register
(FLCR)
FLASH Block Protect
Register (FLBPR)
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 12,288 bytes for user
memory plus a block of 38 bytes for user interrupt vectors and one byte
for the mask option register. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory page size is
defined as 128 bytes, and is the minimum size that can be erased in a
page erase operation. Program and erase operations are facilitated
through control bits in FLASH control register (FLCR). The address
ranges for the FLASH memory are:
HVENMASSERASEPGM
BPR7BPR6BPR5BPR4BPR3BPR2BPR1BPR0
= Unimplemented
•$C000–$EFFF; user memory, 12,288 bytes
•$FFDA–$FFFF; user interrupt vectors, 38 bytes
•$FF80; mask option register
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE:A security feature prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
1
64FLASH MemoryFreescale Semiconductor
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address:$FE08
Bit 7654321Bit 0
FLASH Memory
FLASH Control Register
Read:0000
HVENMASSERASEPGM
Write:
Reset:00000000
Figure 4-2. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorFLASH Memory65
FLASH Memory
4.5 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page
consists of 128 consecutive bytes starting from addresses $xx00 or
$xx80. The 38-byte user interrupt vectors area also forms a page. The
38-byte user interrupt vectors cannot be erased by the page erase
operation because of security reasons. Mass erase is required to erase
this page.
1.Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2.Write any data to any FLASH address within the page address
range desired.
3.Wait for a time, t
(10µs).
nvs
4.Set the HVEN bit.
5.Wait for a time, t
Erase
(1ms).
6.Clear the ERASE bit.
7.Wait for a time, t
8.Clear the HVEN bit.
9.After time, t
rcv
mode.
NOTE:Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps.
(5µs).
nvh
(1µs), the memory can be accessed again in read
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
66FLASH MemoryFreescale Semiconductor
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read
as logic 1:
1.Set both the ERASE bit and the MASS bit in the FLASH control
register.
2.Write any data to any FLASH address within the FLASH memory
address range.
FLASH Memory
FLASH Mass Erase Operation
3.Wait for a time, t
(10µs).
nvs
4.Set the HVEN bit.
5.Wait for a time t
MErase
(4ms).
6.Clear the ERASE bit.
7.Wait for a time, t
nvhl
(100µs).
8.Clear the HVEN bit.
9.After time, t
(1µs), the memory can be accessed again in read
rcv
mode.
NOTE:Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorFLASH Memory67
FLASH Memory
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $xx00, $xx40,
$xx80, or $xxC0. The procedure for programming a row of the FLASH
memory is outlined below:
1.Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2.Write any data to any FLASH address within the row address
range desired.
3.Wait for a time, t
(10µs).
nvs
4.Set the HVEN bit.
5.Wait for a time, t
pgs
(5µs).
6.Write data to the FLASH address to be programmed.
7.Wait for time, t
Prog
(30µs).
8.Repeat step 6 and 7 until all the bytes within the row are
programmed.
9.Clear the PGM bit.
10.Wait for time, t
nvh
(5µs).
11.Clear the HVEN bit.
12.After time, t
(1µs), the memory can be accessed again in read
rcv
mode.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE:Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps. Do
not exceed t
Characteristics.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
68FLASH MemoryFreescale Semiconductor
maximum. See 24.18 FLASH Memory
Prog
FLASH Memory
FLASH Program Operation
Figure 4-3 shows a flowchart representation for programming the
FLASH memory.
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
Write any data to any FLASH address
Set PGM bit
within the row address range desired
3
4
5
6
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address
to be programmed
7
Wait for a time, t
nvs
pgs
Prog
Completed
programming
Y
this row?
N
NOTE:
9
Clear PGM bit
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
10
Wait for a time, t
nvh
must not exceed the maximum programming
Prog
max.
11
Clear HVEN bit
time, t
This row program algorithm assumes the row/s
to be programmed are initially erased.
12
Wait for a time, t
rcv
End of Programming
Figure 4-3. FLASH Programming Flowchart
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorFLASH Memory69
FLASH Memory
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
pages of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE:When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set,
the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register.
The content of this register determine the starting location of the
protected range within the FLASH memory.
Address:$FE09
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Register Bit7 to Bit 0
BPR[7:1] represent bits [13:7] of a 16-bit memory address. Bits
[15:14] are logic 1s and bits [6:0] are logic 0s.
Bit 7654321Bit 0
BPR7BPR6BPR5BPR4BPR3BPR2BPR1BPR0
Figure 4-4. FLASH Block Protect Register (FLBPR)
16-bit memory address
Start address of FLASH block protect 110000000
BPR[7:1]
Figure 4-5. FLASH Block Protect Start Address
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
70FLASH MemoryFreescale Semiconductor
FLASH Memory
FLASH Protection
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00 or XX80 (at
page boundaries) within the FLASH memory.
Examples of protect start address:
BPR[7:0]Start of Address of Protect Range
$00 or $01
$02 or $03$C080 (1100 0000 1000 0000)
$04 or $05$C100 (1100 0001 0000 0000)
$06 or $07$C180 (1100 0001 1000 0000)
$08 or $09$C200 (1100 0010 0000 0000)
and so on...
$F8 or $F9$FE00 (1111 1110 0000 0000)
$FA or $FB$FE80 (1111 1110 1000 0000)
$FC or $FD$FF00 (1111 1111 0000 0000)
$FE$FF80 (1111 1111 1000 0000)
$FFThe entire FLASH memory is not protected.
Note:
The end address of the protected range is always $FFFF.
$C000 (1100 0000 0000 0000)
The entire FLASH memory is protected.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorFLASH Memory71
FLASH Memory
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
72FLASH MemoryFreescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 5. Configuration and Mask Option Registers
This section describes the configuration registers, CONFIG1 and
CONFIG2; and the mask option register, MOR.
(CONFIG & MOR)
The configuration registers enable or disable these options:
•Computer operating properly module (COP)
•COP timeout period (218 – 24 or 213 – 24 ICLK cycles)
•Low-voltage inhibit (LVI) module power
•LVI module reset
•LVI module in stop mode
•LVI module voltage trip point selection
•STOP instruction
•Stop mode recovery time (32 ICLK cycles or 4096 ICLK cycles)
•Oscillator (internal, RC, and crystal) during stop mode
•Serial communications interface clock source (CGMXCLK or f
•Current detect output pin
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
BUS
)
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR)73
Configuration and Mask Option
The mask option register selects one of the following oscillator options
as the MCU reference clock:
•Internal oscillator
•RC oscillator
•Crystal oscillator
Addr.Register NameBit 7654321Bit 0
Read:
$001D
$001F
$FF80
* FLASH register.Reset:UUUUUUUU
† One-time writable register after each reset.
†† Reset by POR only.
Configuration Register 2
(CONFIG2)
Configuration Register 1
(CONFIG1)
Mask Option Register
(MOR)*
Write:
†
Reset:00000000
Read:
Write:
†
Reset:00000
Read:
Write:
Erased:11111111
STOP_
ICLKEN
COPRSLVISTOP LVIRSTD LVIPWRD LVI5OR3SSRECSTOPCOPD
OSCSEL1OSCSEL0RRRRRR
STOP_
RCLKEN
= UnimplementedR= Reserved
STOP_
XCLKEN
OSCCLK1 OSCCLK0
††
0
CDOEN
000
SCIBDSRC
Figure 5-1. CONFIG and MOR Register Summary
5.3 Functional Description
The configuration registers and the mask option register are used in the
initialization of various options. These two types of registers are
configured differently:
•Configuration registers — Write-once registers after reset
•Mask option register — FLASH register (write by programming)
The configuration registers can be written once after each reset. All of
the configuration register bits are cleared during reset. Since the various
options affect the operation of the MCU, it is recommended that these
registers be written immediately after reset. The configuration registers
are located at $001D and $001F. The configurations register may be
read at anytime.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
74Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
Configuration and Mask Option Registers (CONFIG & MOR)
NOTE:The options except LVI5OR3 are one-time writable by the user after
each reset. The LVI5OR3 bit is one-time writable by the user only after
each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in Figure 5-2 and Figure 5-3.
The mask option register (MOR) is used for selecting one of the three
clock options for the MCU. The MOR is a byte located in FLASH
memory, and is written to by a FLASH programming routine.
5.4 Configuration Register 1 (CONFIG1)
Address:$001F
Bit 7654321Bit 0
Configuration Register 1 (CONFIG1)
Read:
Write:
Reset:00000*000
COPRSLVISTOP LVIRSTD LVIPWRD LVI5OR3SSRECSTOPCOPD
* Reset by POR only.
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 21. Computer Operating Properly (COP).)
13
1 = COP time out period = 2
0 = COP time out period = 2
– 24 ICLK cycles
18
– 24 ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR)75
Configuration and Mask Option
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
LVIPWRD disables the LVI module. (See Section 22. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5V or 3V Operating Mode
LVI5OR3 selects the voltage operating mode of the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI).) The voltage mode selected
for the LVI should match the operating VDD. See Section 24.
Electrical Specifications for the LVI voltage trip points for each of
the modes.
1 = LVI operates in 5V mode
0 = LVI operates in 3V mode
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK
cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE:Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, and it is disabled during stop mode
(STOP_XCLKEN= 0), do not set the SSREC bit.
NOTE:When the LVI is disabled in stop mode (LVISTOP=0), the system
stabilization time for long stop recovery (4096 ICLK cycles) gives a delay
longer than the LVI’s turn-on time. There is no period where the MCU is
not protected from a low power condition. However, when using the
short stop recovery configuration option, the 32 ICLK delay is less than
the LVI’s turn-on time and there exists a period in start-up where the LVI
is not protecting the MCU.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
76Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
Configuration and Mask Option Registers (CONFIG & MOR)
STOP_ICLKEN disables the internal oscillator during stop mode.
Setting the STOP_ICLKEN bit disables the oscillator during stop
mode. (See 7.4 Internal Oscillator).
Reset clears this bit.
1 = Internal oscillator disabled during stop mode
0 = Internal oscillator enabled to operate during stop mode
STOP_RCLKEN — RC Oscillator Stop Mode Enable
STOP_RCLKEN enables the RC oscillator to continue operating
during stop mode. Setting the STOP_RCLKEN bit allows the
oscillator to operate continuously even during stop mode. This is
useful for driving the timebase module to allow it to generate periodic
wake up while in stop mode. (See Section 8. Clock Generator
Module (CGM) and subsection 8.8.2 Stop Mode.)
Reset clears this bit.
1 = RC oscillator enabled to operate during stop mode
0 = RC oscillator disabled during stop mode
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR)77
Configuration and Mask Option
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
STOP_XCLKEN enables the crystal (x-tal) oscillator to continue
operating during stop mode. Setting the STOP_XCLKEN bit allows
the x-tal oscillator to operate continuously even during stop mode.
This is useful for driving the timebase module to allow it to generate
periodic wake up while in stop mode. (See Section 8. Clock
Generator Module (CGM) and subsection 8.8.2 Stop Mode.)
Reset clears this bit.
1 = X-tal oscillator enabled to operate during stop mode
0 = X-tal oscillator disabled during stop mode
OSCCLK1, OSCCLK0 — Oscillator Output Control Bits
OSCCLK1 and OSCCLK0 select which oscillator output to be driven
out as OSCCLK to the timebase module (TBM). Reset clears these
two bits.
CDOEN enables the port pin PC0/PWM0/CD as the CD output pin for
the current detect flag (CDIF) from the analog module. Reset clears
the CDOEN bit.
1 = PCO/PWMO/CD pin enabled as CD output pin,
PTC0 and PWM0 functions are disabled.
0 = PTC0/PWM/CD pin disabled as CD output pin,
PTC0 or PWM0 functions are available; see 18.5.1 Port C
Data Register (PTC).
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
78Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
SCIBDSRC — SCI Baud Rate Clock Source
SCIBDSRC selects the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock, f
0 = Oscillator clock, CGMXCLK, is used as clock source for SCI
5.6 Mask Option Register (MOR)
The mask option register (MOR) is used for selecting one of the three
clock options for the MCU. The MOR is a byte located in FLASH
memory, and is written to by a FLASH programming routine.
Address:$FF80
Bit 7654321B
Configuration and Mask Option Registers (CONFIG & MOR)
Mask Option Register (MOR)
, is used as clock source for SCI
BUS
OSCSEL1, OSCSEL0 — Oscillator Selection Bits
OSCSEL1 and OSCSEL0 select which oscillator is used for the MCU
CGMXCLK clock. The erase state of these two bits is logic 1. These
bits are unaffected by reset. (See Table 5-1).
Bits 5–0 — Should be left as 1’s.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR)79
Configuration and Mask Option
Table 5-1. CGMXCLK Clock Selection
OSCSEL1OSCSEL0CGMXCLKOSC2 pinComments
00——Not used
01ICLKf
10RCCLKf
11X-TAL
BUS
BUS
Inverting
output of
XTAL
Internal oscillator generates the CGMXCLK.
RC oscillator generates the CGMXCLK.
Internal oscillator is available after each POR
or reset.
X-tal oscillator generates the CGMXCLK.
Internal oscillator is available after each POR
or reset.
NOTE:The internal oscillator is a free running oscillator and is available after
each POR or reset. It is turned-off in stop mode by clearing the
STOP_ICLKEN bit in CONFIG2.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
80Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)81
Central Processor Unit (CPU)
6.3 Features
•Object code fully upward-compatible with M68HC05 Family
•16-bit stack pointer with stack manipulation instructions
•16-bit index register with x-register manipulation instructions
•8-MHz CPU internal bus frequency
•64K-byte program/data memory space
•16 addressing modes
•Memory-to-memory data moves without using accumulator
•Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•Enhanced binary-coded decimal (BCD) data handling
•Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64K-bytes
6.4 CPU Registers
•Low-power stop and wait modes
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
82Central Processor Unit (CPU)Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
6.4.1 Accumulator
7
15
HX
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7654321Bit 0
Read:
Write:
Reset:Unaffected by reset
Figure 6-2. Accumulator (A)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)83
Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64K-byte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
Bit
1413121110987654321
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Bit
0
Figure 6-3. Index Register (H:X)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
84Central Processor Unit (CPU)Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
NOTE:The location of the stack is arbitrary and may be relocated anywhere in
6.4.4 Program Counter
Bit
1413121110987654321
15
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 6-4. Stack Pointer (SP)
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
1413121110987654321
15
Read:
Write:
Reset:Loaded with Vector from $FFFE and $FFFF
Bit
0
Figure 6-5. Program Counter (PC)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)85
Central Processor Unit (CPU)
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X11X1XXX
V11H I NZC
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
86Central Processor Unit (CPU)Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE:To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)87
Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
6.6.1 Wait Mode
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
The WAIT instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
88Central Processor Unit (CPU)Freescale Semiconductor
6.6.2 Stop Mode
The STOP instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Central Processor Unit (CPU)
CPU During Break Interrupts
•Loading the instruction register with the SWI instruction
•Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
6.9 Opcode Map
See Table 6-2.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)89
ee ff
AIS #oprAdd Immediate Value (Signed) to SPSP ← (SP) + (16 « M)––––––IMMA7 ii 2
AIX #oprAdd Immediate Value (Signed) to H:XH:X ← (H:X) + (16 « M)––––––IMMAF ii2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
TAPTransfer A to CCRCCR ← (A)RRRRRRINH842
TAXTransfer A to XX ← (A)––––––INH971
TPATransfer CCR to AA ← (CCR)– – – – – – INH851
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSXTransfer SP to H:XH:X ← (SP) + 1––––––INH952
TXATransfer X to AA ← (X)––––––INH9F1
TXSTransfer H:X to SP(SP) ← (H:X) – 1––––––INH942
Test for Negative or Zero(A) – $00 or (X) – $00 or (M) – $000 – –
RR–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)97
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
Source
Form
AAccumulatornAny bit
CCarry/borrow bitoprOperand (one or two bytes)
CCR Condition code registerPCProgram counter
ddDirect address of operandPCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instructionPCL Program counter low byte
DDDirect to direct addressing modeREL Relative addressing mode
DIRDirect addressing moderelRelative program counter offset byte
DIX+ Direct to indexed with post increment addressing moderrRelative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressingSP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing modeSP2 Stack pointer 16-bit offset addressing mode
ffOffset byte in indexed, 8-bit offset addressingSPStack pointer
HHalf-carry bitUUndefined
HIndex register high byteVOverflow bit
hh llHigh and low bytes of operand address in extended addressingXIndex register low byte
IInterrupt maskZZero bit
iiImmediate operand byte&Logical AND
IMDImmediate source to direct destination addressing mode|Logical OR
IMM Immediate addressing mode
INHInherent addressing mode( )Contents of
IXIndexed, no offset addressing mode–( ) Negation (two’s complement)
IX+Indexed, no offset, post increment addressing mode#Immediate value
IX+D Indexed with post increment to direct addressing mode
IX1Indexed, 8-bit offset addressing mode←Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode?If
IX2Indexed, 16-bit offset addressing mode:Concatenated with
MMemory locationRSet or cleared
NNegative bit—Not affected
OperationDescription
⊕Logical EXCLUSIVE OR
«Sign extend
CCR
VH I NZC
Address
Mode
Opcode
Operand
Cycles
Data SheetMC68HC908SR12•MC68HC08SR12 — Rev. 5.0
98Central Processor Unit (CPU)Freescale Semiconductor
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0Data Sheet
Freescale SemiconductorCentral Processor Unit (CPU)99
Table 6-2. Opcode Map
Bit Manipulation BranchRead-Modify-WriteControlRegister/Memory