MC68HC908SR12
MC68HC08SR12
Data Sheet
M68HC08
Microcontrollers
MC68HC908SR12
Rev. 5.0
07/2004
freescale.com
MC68HC908SR12
MC68HC08SR12
Data Sheet
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This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor 3
Revision History
Revision History
Date
July 2004 5
February,
2002
Revision
Level
4
Description
Table 24-2 . Operating Range and Table 24-11 . 3V ADC
Electrical Characteristics — changed minimum V
operation to 3V.
15.8.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3)
— Corrected ADRL–ADRL3 register bits.
PTB0/SDA0, PTB1/SCL0, PTB2/SDA1/TxD, and
PTB3/SCL1/RxD pins — clarified these open-drain pins
throughout this document.
8.4.6 Programming the PLL — deleted redundant step in
programming the PLL.
Figure 10-1 . Monitor Mode Circuit — corrected connections for
PTA1 and PTA2.
Table 10-1 . Monitor Mode Signal Requirements and Options
— clarified clock input requirements for monitor mode entry.
Section 11. Timer Interface Module (TIM) — timer
discrepancies corrected throughout this section.
18.5.1 Port C Data Register (PTC) and 18.5.2 Data Direction
Register C (DDRC)
for ADC
DD
Page
Number(s)
373, 381
248
323, 254, 293
120
167
169
181
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
4 Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 35
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 61
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Configuration and Mask Option Registers
(CONFIG & MOR). . . . . . . . . . . . . . . . . . . . . . 73
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 81
Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . .101
List of Sections
Section 8. Clock Generator Module (CGM). . . . . . . . . . 111
Section 9. System Integration Module (SIM) . . . . . . . .141
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 165
Section 11. Timer Interface Module (TIM) . . . . . . . . . . .181
Section 12. Timebase Module (TBM). . . . . . . . . . . . . . . 205
Section 13. Pulse Width Modulator (PWM) . . . . . . . . . . 211
Section 14. Analog Module . . . . . . . . . . . . . . . . . . . . . .221
Section 15. Analog-to-Digital Converter (ADC) . . . . . .231
Section 16. Serial Communications Interface (SCI). . . 251
Section 17. Multi-Master IIC Interface (MMIIC) . . . . . . .291
Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 317
Section 19. External Interrupt (IRQ) . . . . . . . . . . . . . . .335
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor List of Sections 5
List of Sections
Section 20. Keyboard Interrupt Module (KBI). . . . . . . . 343
Section 21. Computer Operating Properly (COP) . . . .351
Section 22. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 357
Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . .363
Section 24. Electrical Specifications. . . . . . . . . . . . . . . 371
Section 25. Mechanical Specifications . . . . . . . . . . . . .387
Section 26. Ordering Information . . . . . . . . . . . . . . . . . 391
Appendix A. MC68HC08SR12 . . . . . . . . . . . . . . . . . . . .393
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
6 List of Sections Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
1.6.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .42
1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .42
1.6.3 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.6.4 External Interrupt Pin (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . .43
1.6.5 Analog Power Supply Pin (V
1.6.6 Analog Ground Pin (V
1.6.7 ADC Voltage Low Reference Pin (V
1.6.8 ADC Voltage High Reference Pin (V
1.6.9 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .43
1.6.10 Analog Input Pins (OPIN1/ATD0, OPIN2/ATD1, V
1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .44
1.6.12 Port B I/O Pins (PTB6–PTB0) . . . . . . . . . . . . . . . . . . . . . . .44
1.6.13 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .44
1.6.14 Port D I/O Pins (PTD7/KBI7–PTD0/KBI0) . . . . . . . . . . . . . .44
) . . . . . . . . . . . . . . . . . . . . . . . . . .43
SSA
Table of Contents
). . . . . . . . . . . . . . . . . . . . .43
DDA
) . . . . . . . . . . . . . .43
REFL
). . . . . . . . . . . . . .43
REFH
SSAM
). . .44
Section 2. Memory Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .45
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Table of Contents 7
Table of Contents
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .46
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 4. FLASH Memory
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .66
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .67
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .70
Section 5. Configuration and Mask Option Registers
(CONFIG & MOR)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .75
5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .77
5.6 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . .79
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
8 Table of Contents Freescale Semiconductor
Table of Contents
Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Section 7. Oscillator (OSC)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.3 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.3.1 CGM Reference Clock Selection . . . . . . . . . . . . . . . . . . . .104
7.3.2 TBM Reference Clock Selection . . . . . . . . . . . . . . . . . . . .105
7.4 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.5 RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.6 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
7.7.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .108
7.7.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .109
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Table of Contents 9
Table of Contents
7.7.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .109
7.7.4 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . .109
7.7.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . .109
7.7.6 Oscillator Clock to Time Base Module (OSCCLK). . . . . . .109
7.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
7.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
7.9 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .110
Section 8. Clock Generator Module (CGM)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .116
8.4.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
8.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .118
8.4.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . .118
8.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
8.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . .124
8.4.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .124
8.4.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .125
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .126
8.5.2 PLL Analog Power Pin (V
8.5.3 PLL Analog Ground Pin (V
) . . . . . . . . . . . . . . . . . . . . . .126
DDA
) . . . . . . . . . . . . . . . . . . . . .126
SSA
8.5.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . .126
8.5.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . .126
8.5.6 CGM VCO Clock Output (CGMVCLK). . . . . . . . . . . . . . . .127
8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . .127
8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .127
8.6 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
10 Table of Contents Freescale Semiconductor
Table of Contents
8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .130
8.6.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . .132
8.6.4 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . .133
8.6.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . .134
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .136
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .137
8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .137
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .137
8.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Section 9. System Integration Module (SIM)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .144
9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.3.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . .145
9.3.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . .146
9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .146
9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .147
9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .149
9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.4.2.5 Low-Voltage Inhibit (LVI) Reset. . . . . . . . . . . . . . . . . . .150
9.4.2.6 Monitor Mode Entry Module Reset. . . . . . . . . . . . . . . . .150
9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .151
9.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . .151
9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .151
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Table of Contents 11
Table of Contents
9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9.6.1.1 Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .154
9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
9.6.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .155
9.6.1.4 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . .155
9.6.1.5 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . .157
9.6.1.6 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . .157
9.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
9.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .158
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
9.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .162
9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .163
9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .164
Section 10. Monitor ROM (MON)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
10.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .168
10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10.4.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
10.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
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Section 11. Timer Interface Module (TIM)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
11.5.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .188
11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .189
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .189
11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .190
11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .191
11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .194
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .196
11.10.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .198
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .199
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .200
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Section 12. Timebase Module (TBM)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
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12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .207
12.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
12.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Section 13. Pulse Width Modulator (PWM)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.4 PWM Period and Resolution. . . . . . . . . . . . . . . . . . . . . . . . . .214
13.5 PWM Automatic Phase Control . . . . . . . . . . . . . . . . . . . . . . .215
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
13.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
13.10.1 PWM Control Register (PWMCR) . . . . . . . . . . . . . . . . . . .217
13.10.2 PWM Clock Control Register (PWMCCR) . . . . . . . . . . . . .218
13.10.3 PWM Data Registers (PWMDR0–PWMDR2) . . . . . . . . . .219
13.10.4 PWM Phase Control Register . . . . . . . . . . . . . . . . . . . . . .220
Section 14. Analog Module
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
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14.4.1 On-Chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . .223
14.4.2 Two-Stage Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
14.4.3 Amplifier Response Time. . . . . . . . . . . . . . . . . . . . . . . . . .224
14.4.4 Current Flow Detection Amplifier . . . . . . . . . . . . . . . . . . . .225
14.4.5 Current Flow Detect Output . . . . . . . . . . . . . . . . . . . . . . . .225
14.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
14.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
14.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
14.7 Analog Module I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . .226
14.7.1 Analog Module Control Register (AMCR) . . . . . . . . . . . . .226
14.7.2 Analog Module Gain Control Register (AMGCR). . . . . . . .227
14.7.3 Analog Module Status and Control Register (AMSCR) . . .228
Section 15. Analog-to-Digital Converter (ADC)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
15.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
15.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
15.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
15.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.4.5 Auto-scan Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.4.6 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4.7 Data Register Interlocking . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.8 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.7.1 ADC Voltage In (V
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) . . . . . . . . . . . . . . . . . . . . . . . . . . .240
ADIN
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15.7.2 ADC Analog Power Pin (V
15.7.3 ADC Analog Ground Pin (V
15.7.4 ADC Voltage Reference High Pin (V
15.7.5 ADC Voltage Reference Low Pin (V
) . . . . . . . . . . . . . . . . . . . . .240
DDA
). . . . . . . . . . . . . . . . . . . . .240
SSA
). . . . . . . . . . . . .241
REFH
) . . . . . . . . . . . . .241
REFL
15.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .242
15.8.2 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . .244
15.8.3 ADC Data Register 0 (ADRH0 and ADRL0). . . . . . . . . . . .246
15.8.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3). .248
15.8.5 ADC Auto-Scan Control Register (ADASCR). . . . . . . . . . .248
Section 16. Serial Communications Interface (SCI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
16.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
16.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
16.5.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
16.5.2.1 Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
16.5.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .259
16.5.2.3 Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
16.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
16.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .261
16.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .261
16.5.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
16.5.3.1 Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
16.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .262
16.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
16.5.3.4 Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
16.5.3.5 Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .266
16.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
16.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
16.5.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
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16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
16.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .272
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
16.8.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
16.8.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
16.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
16.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
16.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .279
16.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
16.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
16.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
16.9.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .288
Section 17. Multi-Master IIC Interface (MMIIC)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
17.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
17.5 Multi-Master IIC System Configuration. . . . . . . . . . . . . . . . . .295
17.6 Multi-Master IIC Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . .295
17.6.1 START Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
17.6.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . .296
17.6.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
17.6.4 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . .297
17.6.5 STOP Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
17.6.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
17.6.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
17.6.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
17.6.9 Packet Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
17.7 MMIIC I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
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17.7.1 MMIIC Address Register (MMADR). . . . . . . . . . . . . . . . . .299
17.7.2 MMIIC Control Register 1 (MMCR1) . . . . . . . . . . . . . . . . .301
17.7.3 MMIIC Control Register 2 (MMCR2) . . . . . . . . . . . . . . . . .303
17.7.4 MMIIC Status Register (MMSR). . . . . . . . . . . . . . . . . . . . .305
17.7.5 MMIIC Data Transmit Register (MMDTR) . . . . . . . . . . . . .307
17.7.6 MMIIC Data Receive Register (MMDRR). . . . . . . . . . . . . .308
17.7.7 MMIIC CRC Data Register (MMCRCDR). . . . . . . . . . . . . .309
17.7.8 MMIIC Frequency Divider Register (MMFDR) . . . . . . . . . .310
17.8 Program Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
17.8.1 Data Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
17.9 SMBus Protocols with PEC and without PEC. . . . . . . . . . . . .313
17.9.1 Quick Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.9.2 Send Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.9.3 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.9.4 Write Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
17.9.5 Read Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
17.9.6 Process Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
17.9.7 Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
17.10 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . .316
Section 18. Input/Output (I/O) Ports
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
18.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
18.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .320
18.3.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . .321
18.3.3 Port A LED Control Register (LEDA) . . . . . . . . . . . . . . . . .323
18.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
18.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .324
18.4.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . .325
18.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
18.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .327
18.5.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .329
18.5.3 Port C LED Control Register (LEDC). . . . . . . . . . . . . . . . .330
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18.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
18.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .331
18.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .332
Section 19. External Interrupt (IRQ)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
19.5 IRQ1 and IRQ2 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
19.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .339
19.7 IRQ Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
19.7.1 IRQ1 Status and Control Register . . . . . . . . . . . . . . . . . . .340
19.7.2 IRQ2 Status and Control Register . . . . . . . . . . . . . . . . . . .341
Section 20. Keyboard Interrupt Module (KBI)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
20.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
20.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
20.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . .347
20.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .348
20.6.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .349
20.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
20.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
20.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
20.10 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .350
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Section 21. Computer Operating Properly (COP)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
21.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
21.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
21.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
21.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
21.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
21.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
21.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
21.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
21.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .354
21.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
21.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
21.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .356
Section 22. Low-Voltage Inhibit (LVI)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
22.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
22.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .360
22.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .360
22.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
22.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
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22.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
22.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
22.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
Section 23. Break Module (BRK)
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
23.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .366
23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .366
23.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .366
23.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .366
23.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
23.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
23.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .367
23.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .368
23.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .368
23.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .370
Section 24. Electrical Specifications
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
24.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .372
24.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .373
24.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
24.6 5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .374
24.7 3.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .376
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24.8 5.0V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
24.9 3.0V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
24.10 5.0V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . .378
24.11 3.0V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . .379
24.12 5.0V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .380
24.13 3.0V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .381
24.14 Analog Module Electrical Characteristics . . . . . . . . . . . . . . . .382
24.14.1 Temperature Sensor Electrical Characteristics . . . . . . . . .382
24.14.2 Current Detection Electrical Characteristics. . . . . . . . . . . .382
24.14.3 Two-Stage Amplifier Electrical Characteristics. . . . . . . . . .382
24.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .383
24.16 MMIIC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .383
24.17 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . .385
24.18 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .386
Section 25. Mechanical Specifications
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
25.3 48-Pin Plastic Low Quad Flat Pack (LQFP) . . . . . . . . . . . . . .388
25.4 42-Pin Shrink Dual In-Line Package (SDIP). . . . . . . . . . . . . .389
Section 26. Ordering Information
26.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
26.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
26.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
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Appendix A. MC68HC08SR12
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
A.3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
A.5 Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
A.6 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
A.7 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
A.8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
A.8.1 5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .398
A.8.2 3.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .399
A.8.3 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .401
A.9 ROM Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
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Data Sheet — MC68HC908SR12•MC68HC08SR12
Figure Title Page
1-1 MC68HC908SR12 Block Diagram . . . . . . . . . . . . . . . . . . . . . .39
1-2 48-Pin LQFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . .40
1-3 42-Pin SDIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .41
1-4 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .48
4-1 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .64
4-2 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .65
4-3 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .69
4-4 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .70
4-5 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .70
List of Figures
5-1 CONFIG and MOR Register Summary. . . . . . . . . . . . . . . . . . .74
5-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .75
5-3 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .77
5-4 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . .79
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
6-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .86
7-1 Oscillator Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .103
7-2 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . .104
7-3 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .105
7-4 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
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Figure Title Page
7-5 RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7-6 Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
8-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
8-2 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .115
8-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .125
8-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .128
8-5 PLL Bandwidth Control Register (PBWCR) . . . . . . . . . . . . . .131
8-6 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .132
8-7 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .132
8-8 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .133
8-9 PLL Reference Divider Select Register (PMDS) . . . . . . . . . .134
8-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .144
9-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9-8 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9-11 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . .154
9-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .155
9-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .157
9-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .157
9-15 Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
9-16 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . .160
9-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .160
9-18 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .161
9-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .162
9-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .163
9-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .164
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10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
10-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .171
10-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10-4 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
10-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
10-7 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .178
10-8 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .179
11-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .185
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .190
11-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .196
11-5 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . .198
11-6 TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . . . .198
11-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .199
11-8 TIM Counter Modulo Register Low (TMODL). . . . . . . . . . . . .199
11-9 TIM Channel 0 Status and Control Register (TSC0) . . . . . . .200
11-10TIM Channel 1 Status and Control Register (TSC1) . . . . . . .200
11-11CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
11-12TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . .204
11-13TIM Channel 0 Register Low (TCH0L). . . . . . . . . . . . . . . . . .204
11-14TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . .204
11-15TIM Channel 1 Register Low (TCH1L). . . . . . . . . . . . . . . . . .204
12-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . .207
13-1 PWM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .212
13-2 PWM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13-3 PWM Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13-4 PWM Automatic Phase Control . . . . . . . . . . . . . . . . . . . . . . .215
13-5 PWM Control Register (PWMCR). . . . . . . . . . . . . . . . . . . . . .217
13-6 PWM Clock Control Register (PWMCCR) . . . . . . . . . . . . . . .218
13-7 PWM Data Register 0 (PWMDR0) . . . . . . . . . . . . . . . . . . . . .219
13-8 PWM Data Register 1 (PWMDR1) . . . . . . . . . . . . . . . . . . . . .219
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor List of Figures 27
List of Figures
Figure Title Page
13-9 PWM Data Register 2 (PWMDR2) . . . . . . . . . . . . . . . . . . . . .219
13-10PWM Phase Control Register (PWMPCR). . . . . . . . . . . . . . .220
14-1 Analog Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .222
14-2 Analog Module I/O Register Summary. . . . . . . . . . . . . . . . . .223
14-3 Analog Module Control Register (AMCR). . . . . . . . . . . . . . . .226
14-4 Analog Module Gain Control Register (AMGCR) . . . . . . . . . .227
14-5 Analog Module Status and Control Register (AMSCR) . . . . .229
15-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .233
15-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
15-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .242
15-4 ADC Clock Control Register (ADICLK). . . . . . . . . . . . . . . . . .244
15-5 ADRH0 and ADRL0 in 8-Bit Truncated Mode. . . . . . . . . . . . .246
15-6 ADRH0 and ADRL0 in Right Justified Mode. . . . . . . . . . . . . .246
15-7 ADRH0 and ADRL0 in Left Justified Mode. . . . . . . . . . . . . . .247
15-8 ADRH0 and ADRL0 in Left Justified Sign Data Mode . . . . . .247
15-9 ADC Data Register Low 1 to 3 (ADRL1–ADRL3). . . . . . . . . .248
15-10ADC Scan Control Register (ADASCR) . . . . . . . . . . . . . . . . .248
16-1 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .255
16-2 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .256
16-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
16-4 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
16-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .263
16-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
16-7 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
16-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
16-9 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .274
16-10SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .277
16-11SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .279
16-12SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .282
16-13Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
16-14SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .286
16-15SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .287
16-16SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .288
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
28 List of Figures Freescale Semiconductor
List of Figures
Figure Title Page
17-1 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .294
17-2 Multi-Master IIC Bus Transmission Signal Diagram. . . . . . . .295
17-3 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
17-4 MMIIC Address Register (MMADR) . . . . . . . . . . . . . . . . . . . .299
17-5 MMIIC Control Register 1 (MMCR1). . . . . . . . . . . . . . . . . . . .301
17-6 MMIIC Control Register 2 (MMCR2). . . . . . . . . . . . . . . . . . . .303
17-7 MMIIC Status Register (MMSR). . . . . . . . . . . . . . . . . . . . . . .305
17-8 MMIIC Data Transmit Register (MMDTR) . . . . . . . . . . . . . . .307
17-9 MMIIC Data Receive Register (MMDRR). . . . . . . . . . . . . . . .308
17-10MMIIC CRC Data Register (MMCRCDR). . . . . . . . . . . . . . . .309
17-11MMIIC Frequency Divider Register (MMFDR) . . . . . . . . . . . .310
17-12Data Transfer Sequences for Master/Slave
Transmit/Receive Modes. . . . . . . . . . . . . . . . . . . . . . . . . .312
17-13Quick Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17-14Send Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17-15Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17-16Write Byte/Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
17-17Read Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
17-18Process Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
17-19Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
17-20SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . .316
18-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .318
18-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .320
18-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .321
18-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
18-5 Port A LED Control Register (LEDA) . . . . . . . . . . . . . . . . . . .323
18-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .324
18-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .325
18-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
18-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .327
18-10Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .329
18-11Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
18-12Port A LED Control Register (LEDA) . . . . . . . . . . . . . . . . . . .330
18-13Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .331
18-14Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .332
18-15Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor List of Figures 29
List of Figures
Figure Title Page
19-1 External Interrupt I/O Register Summary . . . . . . . . . . . . . . . .336
19-2 IRQ1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
19-3 IRQ2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
19-4 IRQ1 Status and Control Register (INTSCR1) . . . . . . . . . . . .340
19-5 IRQ2 Status and Control Register (INTSCR2) . . . . . . . . . . . .341
20-1 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .344
20-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .345
20-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .348
20-4 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . .349
21-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
21-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .354
21-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .355
22-1 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .358
22-2 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .358
22-3 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
23-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .365
23-2 Break Module I/O Register Summary. . . . . . . . . . . . . . . . . . .365
23-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .367
23-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .368
23-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .368
23-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .369
23-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .370
24-1 RC vs. Bus Frequency (5V @25°C). . . . . . . . . . . . . . . . . . . .378
24-2 RC vs. Bus Frequency (3V @25°C). . . . . . . . . . . . . . . . . . . .379
24-3 MMIIC Signal Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
25-1 48-Pin LQFP (Case #932-02). . . . . . . . . . . . . . . . . . . . . . . . .388
25-2 42-Pin SDIP (Case #858-01) . . . . . . . . . . . . . . . . . . . . . . . . .389
A-1 MC68HC08SR12 Block Diagram . . . . . . . . . . . . . . . . . . . . . 395
A-2 MC68HC08SR12 Memory Map . . . . . . . . . . . . . . . . . . . . . . 396
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
30 List of Figures Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Table Title Page
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5-1 CGMXCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7-1 CGMXCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . .104
7-2 Timebase Module Reference Clock Selection . . . . . . . . . . . .105
List of Tables
8-1 Numeric Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
8-3 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .130
8-2 PRE1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .130
9-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10-1 Monitor Mode Signal Requirements and Options. . . . . . . . . .169
10-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .173
10-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .175
10-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .175
10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .176
10-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .176
10-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .177
10-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .177
11-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor List of Tables 31
List of Tables
Table Title Page
11-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .202
12-1 Timebase Rate Selection for OSCCLK = 32.768 kHz . . . . . .207
13-1 PTC0 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
13-2 PWM Counter Clock Prescaler Selection. . . . . . . . . . . . . . . .219
14-1 Analog Module Power Control . . . . . . . . . . . . . . . . . . . . . . . .226
14-2 Amplifier Channel Select Control bits. . . . . . . . . . . . . . . . . . .227
14-3 Analog Module Gain Values. . . . . . . . . . . . . . . . . . . . . . . . . .228
14-4 Analog Module Clock Divider Select. . . . . . . . . . . . . . . . . . . .229
15-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
15-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
15-3 ADC Mode Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
15-4 Auto-scan Mode Channel Select . . . . . . . . . . . . . . . . . . . . . .248
16-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
16-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
16-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
16-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
16-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .276
16-6 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .288
16-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
16-8 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . . .290
17-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
17-2 MMIIC Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . .310
18-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .319
18-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
18-3 PTB2 and PTB3 Pin Configurations . . . . . . . . . . . . . . . . . . . .325
18-4 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
18-5 PTC0 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
18-6 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
18-7 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
32 List of Tables Freescale Semiconductor
List of Tables
Table Title Page
20-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
22-1 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
24-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .372
24-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
24-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
24-4 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .374
24-5 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .376
24-6 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
24-7 3V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
24-8 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .378
24-9 3V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .379
24-105V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .380
24-113V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .381
24-12Temperature Sensor Electrical Characteristics . . . . . . . . . . .382
24-13Current Detection Electrical Characteristics. . . . . . . . . . . . . .382
24-14Two-Stage Amplifier Electrical Characteristics. . . . . . . . . . . .382
24-15MMIIC DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .383
24-16MMIIC Interface Input/Output Signal Timing. . . . . . . . . . . . . .384
24-17FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . .386
26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
A-1 Summary of MC68HC08SR12 and
MC68HC908SR12 Differences . . . . . . . . . . . . . . . . . . . . .394
A-2 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .398
A-3 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .399
A-4 MC68HC08SR12 Order Numbers . . . . . . . . . . . . . . . . . . . . .401
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor List of Tables 33
List of Tables
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
34 List of Tables Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
1.6.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .42
1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .42
1.6.3 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.6.4 External Interrupt Pin (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . .43
1.6.5 Analog Power Supply Pin (V
1.6.6 Analog Ground Pin (V
1.6.7 ADC Voltage Low Reference Pin (V
1.6.8 ADC Voltage High Reference Pin (V
1.6.9 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .43
1.6.10 Analog Input Pins (OPIN1/ATD0, OPIN2/ATD1, V
1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .44
1.6.12 Port B I/O Pins (PTB6–PTB0) . . . . . . . . . . . . . . . . . . . . . . .44
1.6.13 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .44
1.6.14 Port D I/O Pins (PTD7/KBI7–PTD0/KBI0) . . . . . . . . . . . . . .44
SSA
). . . . . . . . . . . . . . . . . . . . .43
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . .43
) . . . . . . . . . . . . . .43
REFL
). . . . . . . . . . . . . .43
REFH
). . .44
SSAM
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor General Description 35
General Description
1.2 Introduction
1.3 Features
The MC68HC908SR12 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
Features of the MC68HC908SR12 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
• Maximum internal bus frequency:
– 8-MHz at 5V operating voltage
– 4-MHz at 3V operating voltage
• Clock input options:
– RC-oscillator
– 32kHz crystal-oscillator with 32MHz internal phase-lock-loop
• 12k-bytes user program FLASH memory with security1 feature
• 512 bytes of on-chip RAM
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, and PWM
capability on each channel
• Timebase module
• 3-channel, 8-bit high speed PWM (125kHz) with independent
counters and automatic phase control
• Serial communications interface module (SCI)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
36 General Description Freescale Semiconductor
General Description
Features
• System Management Bus (SMBus), version 1.0/1.1
(Multi-master IIC bus)
• 14-channel, 10-bit analog-to-digital converter (ADC), with
auto-scan mode for 4 channels
• Current sensor with programmable amplifier
• Temperature sensor (–20°C to +70°C)
•IRQ1 external interrupt pin with integrated pullup
•IRQ2 external interrupt pin with programmable pullup
• 8-bit keyboard wakeup port with integrated pullup
• 31 general-purpose input/output (I/O) pins and 2 dedicated pins:
– 31 shared-function I/O pins
– Two dedicated analog input pins
• Low-power design (fully static with Stop and Wait modes)
• Master reset pin (with integrated pullup) and power-on reset
• System protection features
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• 48-pin low quad flat pack (LQFP) and 42-pin shrink dual-in-line
package (SDIP)
• Specific features of the MC68HC908SR12 in 42-pin SDIP are:
– 29 general-purpose l/Os only
– 11-channel ADC only
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor General Description 37
General Description
• 16-bit Index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908SR12.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
38 General Description Freescale Semiconductor
Freescale Semiconductor General Description 39
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
CONTROL AND STATUS REGISTERS — 96 BYTES
2-CHANNEL TIMER INTERFACE
2-CHANNEL TIMER INTERFACE
MODULE 1
MODULE 2
DDRA
PORTA
PTA7/T1CH1
PTA6/T1CH0
PTA5/ATD7 – PTA0/ATD2
‡
USER FLASH — 12,288 BYTES
PTB6/IRQ2
PTB5/T2CH1
PTB4/T2CH0
PTB3//SCL1/RxD
PTB2/SDA1/TxD
PTB1/SCL0
PTB0/SDA0
PTC7/ATD12
PTC6/ATD11
PTC5/ATD10
PTC4/ATD9
PTC3/ATD8
†
†
‡ #
‡ #
‡
‡
‡
PTC2/PWM2
PTC1/PWM1
PTC0/PWM0/CD
†
†
USER RAM — 512 BYTES
MONITOR ROM — 368 BYTES
USER FLASH VECTORS — 38 BYTES
OSCILLATORS AND
CLOCK GENERATOR MODULE
INTERNAL OSCILLATOR
OSC1
OSC2
CGMXFC
RC OSCILLATOR
X-TAL OSCILLATOR
PHASE-LOCKED LOOP
TIMEBASE
MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
MULTI-MASTER IIC (SMBUS)
INTERFACE MODULE
PULSE WIDTH MODULATOR
MODULE
8-BIT KEYBOARD
INTERRUPT MODULE
DDRB
DDRC
PORTB
PORTC
* RST
* IRQ1
** IRQ2
OPIN1/ATD0
#
OPIN2/ATD1
V
V
V
SSAM
REFH
REFL
V
V
V
DDA
V
SSA
SYSTEM INTEGRATION
MODULE
EXTERNAL IRQ
MODULE
COMPUTER OPERATING
PROPERLY MODULE
LOW-VOLTAGE
INHIBIT MODULE
DDRD
PORTD
PTD7/KBI7 – PTD0/KBI0 ***
ANALOG
MODULE
POWER-ON RESET
MODULE
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
* Pin contains integrated pullup device.
MCU Block Diagram
General Description
** Pin contains configurable pullup device.
DD
SS
POWER
*** Pin contains integrated pullup device for KBI functions.
† Pin is open-drain when configured as output.
‡ High current drive pin (for LED).
# Pin not bonded on 42-pin SDIP.
Figure 1-1. MC68HC908SR12 Block Diagram
General Description
1.5 Pin Assignments
PTC3/ATD8
1
PTA5/ATD7
CGMXFC
48
47
PTC6/ATD11
PTC5/ATD10
PTC4/ATD9
46
45
44
VDDA
43
VSSA
42
NC
41
PTA4/ATD6
40
PTA3/ATD5
39
PTA2/ATD4
38
PTA1/ATD3
37
36
VREFH
12
2
3
4
5
6
7
8
9
10
11
13
PTB0/SDA0
14
15
16
PTB1/SCL0
PTB2/SDA1/TxD
PTB3/SCL1/RxD
17
18
19
PTD4/KBI4
PTD5/KBI5
PTD6/KBI6
20
21
22
23
PTC2/PWM2
PTC1/PWM1
PTC0/PWM0/CD
PTA7/T1CH1
NC
PTD0/KBI0
VDD
OSC1
OSC2
VSS
PTD1/KBI1
IRQ1
PTD2/KBI2
RST
PTD3/KBI3
35
34
33
32
31
30
29
28
27
26
25
24
NC
VREFL
OPIN2/ATD1
PTC7/ATD12
PTA0/ATD2
VSSAM
OPIN1/ATD0
PTB4/T2CH0
PTB5/T2CH1
PTB6/IRQ2
PTA6/T1CH0
PTD7/KBI7
NC: No connection
Figure 1-2. 48-Pin LQFP Pin Assignments
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
40 General Description Freescale Semiconductor
General Description
Pin Functions
VDDA
PTC5/ATD10
PTC4/ATD9
PTA5/ATD7
CGMXFC
PTC3/ATD8
PTD0/KBI0
VDD
OSC1
OSC2
VSS
PTD1/KBI1
IRQ1
PTD2/KBI2
RST
PTD3/KBI3
PTB0/SDA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSSA
PTA4/ATD6
PTA3/ATD5
PTA2/ATD4
PTA1/ATD3
VREFH
VREFL
PTA0/ATD2
VSSAM
OPIN1/ATD0
PTB4/T2CH0
PTB5/T2CH1
PTB6/IRQ2
PTA6/T1CH0
PTD7/KBI7
PTA7/T1CH1
PTC2/PWM2
1.6 Pin Functions
PTB1/SCL0
PTB2/SDA1/TxD
PTB3/SCL1/RxD
PTD4/KBI4
Pins not available on 42-pin package Internal connection
18
19
20 23
21 22
OPIN2/ATD1 Unconnected
PTC6/ATD11 Unconnected
PTC7/ATD12 Unconnected
Figure 1-3. 42-Pin SDIP Pin Assignment
Description of pin functions are provided here.
25
24
PTC1/PWM1
PTC0/PWM0/CD
PTD6/KBI6
PTD5/KBI5
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor General Description 41
General Description
1.6.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
MCU
must be grounded for proper MCU operation.
V
SS
1.6.2 Oscillator Pins (OSC1 and OSC2)
V
DD
C1
0.1 µF
+
C2
V
DD
NOTE: Component values shown
represent typical applications.
V
SS
Figure 1-4. Power Supply Bypassing
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Section 7. Oscillator (OSC) and Section 8. Clock
Generator Module (CGM).
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
42 General Description Freescale Semiconductor
1.6.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known start-up state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor. See Section 9. System Integration Module (SIM).
1.6.4 External Interrupt Pin (IRQ1)
IRQ1 is an asynchronous external interrupt pin. This pin contains an
internal pullup resistor. See Section 19. External Interrupt (IRQ).
General Description
Pin Functions
1.6.5 Analog Power Supply Pin (V
V
is the power supply pin for the analog circuits of the MCU.
DDA
1.6.6 Analog Ground Pin (V
V
SSA
)
SSA
is the power supply ground pin for the analog circuits of the MCU.
DDA
)
It should be decoupled as per the VSS digital ground pin.
1.6.7 ADC Voltage Low Reference Pin (V
V
is the voltage input pin for the ADC voltage low reference. See
REFL
Section 15. Analog-to-Digital Converter (ADC).
1.6.8 ADC Voltage High Reference Pin (V
V
is the voltage input pin for the ADC voltage high reference. See
REFH
Section 15. Analog-to-Digital Converter (ADC).
REFL
REFH
)
)
1.6.9 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See
Section 8. Clock Generator Module (CGM).
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor General Description 43
General Description
1.6.10 Analog Input Pins (OPIN1/ATD0, OPIN2/ATD1, V
OPIN1/ATD0 and OPIN2/ATD1 are input pins to the analog module and
ADC and V
is the negative reference input. See Section 14.
SSAM
Analog Module and Section 15. Analog-to-Digital Converter (ADC).
1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are special function, bidirectional port pins.
PTA7/T1CH1–PTA6/T1CH0 are shared with the TIM1, and
PTA5/ATD7–PTA0/ATD2 are shared with the ADC. See Section 18.
Input/Output (I/O) Ports, Section 11. Timer Interface Module (TIM),
and Section 15. Analog-to-Digital Converter (ADC).
1.6.12 Port B I/O Pins (PTB6–PTB0)
PTB6–PTB0 are special function, bidirectional port pins. PTB6/IRQ2 is
shared with the IRQ2 input, PTB5/T2CH1–PTB4/T2CH0 are shared with
the TIM2, PTB3/SCL1/RxD–PTB2/SDA1/TxD are shared with the
MMIIC and SCI, and PTB1/SCL0–PTB0/SDA0 are shared with the
MMIIC. See Section 18. Input/Output (I/O) Ports, Section 19.
External Interrupt (IRQ), Section 11. Timer Interface Module (TIM),
Section 16. Serial Communications Interface (SCI), and Section 17.
Multi-Master IIC Interface (MMIIC).
SSAM
)
1.6.13 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are special function, bidirectional port pins.
PTC7/ATD12–PTC3/ATD8 are shared with the ADC,
PTC2/PWM2–PTC1/PWM1 are shared with the PWM, and
PTC0/PWM0/CD is shared with the PWM and analog module. See
Section 18. Input/Output (I/O) Ports, Section 15. Analog-to-Digital
Converter (ADC), Section 13. Pulse Width Modulator (PWM), and
Section 14. Analog Module.
1.6.14 Port D I/O Pins (PTD7/KBI7–PTD0/KBI0)
PTD7–PTD0 are general-purpose bidirectional port pins with keyboard
wakeup function. See Section 18. Input/Output (I/O) Ports and
Section 20. Keyboard Interrupt Module (KBI).
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
44 General Description Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 2. Memory Map
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .45
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .46
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
2.2 Introduction
The CPU08 can address 64k-bytes of memory space. The memory
map, shown in Figure 2-1, includes:
• 12,288 bytes of user FLASH memory
• 512 bytes of random-access memory (RAM)
• 38 bytes of user-defined vectors
• 368 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address
reset. In the memory map (Figure 2-1) and in register figures in this
document, unimplemented locations are shaded.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 45
Memory Map
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page
$0000–$005F. Additional I/O registers have the following addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
• $FE03; SIM break flag control register, SBFCR
• $FE04; Interrupt status register 1, INT1
• $FE05; Interrupt status register 2, INT2
• $FE06; Interrupt status register 3, INT3
• $FE07; Reserved
• $FE08; FLASH control register, FLCR
• $FE09; FLASH block protect register, FLBPR
• $FE0A; Reserved
• $FE0B; Reserved
• $FE0C; break address register high, BRKH
• $FE0D; break address register low, BRKL
• $FE0E; break status and control register, BRKSCR
• $FE0F; LVI status register, LVISR
• $FF80; Mask option register, MOR
• $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2, Table 2-1 is a list of vector
locations.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
46 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
$0000
↓
$005F
$0060
↓
$025F
$0260
↓
$BFFF
$C000
↓
$EFFF
$F000
↓
$FDFF
$FE00 SIM Break Status Register (SBSR)
$FE01 SIM Reset Status Register (SRSR)
$FE02 Reserved
$FE03 SIM Break Flag Control Register (SBFCR)
$FE04 Interrupt Status Register 1 (INT1)
$FE05 Interrupt Status Register 2 (INT2)
$FE06 Interrupt Status Register 3 (INT3)
$FE07 Reserved
$FE08 FLASH Control Register (FLCR)
$FE09 FLASH Block Protect Register (FLBPR)
$FE0A Reserved
$FE0B Reserved
$FE0C Break Address Register High (BRKH)
$FE0D Break Address Register Low (BRKL)
$FE0E Break Status and Control Register (BRKSCR)
$FE0F LVI Status Register (LVISR)
$FE10
↓
$FF7F
$FF80 Mask Option Register
$FF81
↓
$FFD9
$FFDA
↓
$FFFF
I/O Registers
96 Bytes
RAM
512 Bytes
Unimplemented
48,544 Bytes
FLASH Memory
12,288 Bytes
Unimplemented
3,584 Bytes
Monitor ROM
368 Bytes
Reserved
89 Bytes
FLASH Vectors
38 Bytes
Figure 2-1. Memory Map
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 47
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0000
$0001
$0002
$0003
$0004
$0005
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Write:
Reset:UUUUUUUU
Read: 0
Write:
Reset:0 UUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
Read: 0
Write:
Reset:00000000
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register C
$0006
Data Direction Register D
$0007
$0008 Unimplemented
$0009 Unimplemented
(DDRC)
(DDRD)
U = Unaffected X = Indeterminate
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
Write:
Reset:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
48 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read:
$000A Unimplemented
$000B Unimplemented
Port-A LED Control
$000C
Port-C LED Control
$000D
Analog Module Control
$000E
Analog Module Gain
$000F
Register
(LEDA)
Register
(LEDC)
Register
(AMCR)
Control Register
(AMGCR)
Write:
Reset:
Read:
Write:
Reset:
Read: 0 0
Write:
Reset:00000000
Read:
LEDC7 LEDC6 LEDC5 LEDC4 LEDC3
Write:
Reset:00000000
Read:
PWR1 PWR0 OPCH1 OPCH0 AMIEN DO2 DO1 DO0
Write:
Reset:00000000
Read:
GAINB3 GAINB2 GAINB1 GAINB0 GAINA3 GAINA2 GAINA1 GAINA0
Write:
Reset:00000000
LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDA0
000
Analog Module Status and
$0010
$0011 Unimplemented
$0012 Unimplemented
$0013
Control Register
(AMSCR)
SCI Control Register 1
(SCC1)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12)
Read:
AMCDIV1 AMCDIV0
Write: OPIFR
Reset:00U000U0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset:00000000
0 OPIF 0 DOF 0 CDIF
CDIFR
= Unimplemented R = Reserved
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 49
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0014
$0015
$0016
$0017
$0018
$0019
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
SCI Baud Rate Register
(SCBR)
Write:
Reset:00000000
Read: R8
Write:
Reset:UU000000
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read: 000000BKFRPF
Write:
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:UUUUUUUU
Read: 0 0
Write:
Reset:0000 000
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
T8 DMARE DMATE ORIE NEIE FEIE PEIE
SCP1 SCP0 R SCR2 SCR1 SCR0
Keyboard Status and
$001A
Keyboard Interrupt Enable
$001B
IRQ2 Status and Control
$001C
$001D
Configuration Register 2
Read: 0000KEYF 0
Control Register
(KBSCR)
Register
(KBIER)
Register
(INTSCR2)
(CONFIG2)
U = Unaffected X = Indeterminate
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0
Write:
Reset:00000000
Read:
Write:
†
Reset:00000000
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
PTBPUE6
STOP_
ICLKEN
RCLKEN
STOP_
00IRQ2F0
STOP_
XCLKEN
OSCCLK1 OSCCLK0
= Unimplemented R = Reserved
ACKK
ACK2
0
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
IMASKK MODEK
IMASK2 MODE2
CDOEN
SCIBDSRC
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
50 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
IRQ1 Status and Control
$001E
$001F
† One-time writable register after each reset.
$0020
$0021
$0022
$0023
Configuration Register 1
Timer 1 Status and
Timer 1 Counter Modulo
Register
(INTSCR1)
(CONFIG1)
Control Register
(T1SC)
Timer 1 Counter
Register High
(T1CNTH)
Timer 1 Counter
Register Low
(T1CNTL)
Register High
(T1MODH)
Read: 0000IRQ1F0
Write: ACK1
Reset:00000000
Read:
Write:
†
Reset:00000000
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
IMASK1 MODE1
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
TOIE TSTOP
Bit 15 14 13 12 11 10 9 Bit 8
00
PS2 PS1 PS0
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:XXXXXXXX
= Unimplemented R = Reserved
$0024
$0025
$0026
Timer 1 Counter Modulo
Register Low
(T1MODL)
Timer 1 Channel 0 Status
and Control Register
(T1SC0)
Timer 1 Channel 0
Register High
(T1CH0H)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 51
Memory Map
Addr.Register Name Bit 7654321Bit 0
Timer 1 Channel 0
$0027
Timer 1 Channel 1 Status
$0028
$0029
$002A
$002B
$002C
Register Low
(T1CH0L)
and Control Register
(T1SC1)
Timer 1 Channel 1
Register High
(T1CH1H)
Timer 1 Channel 1
Register Low
(T1CH1L)
Timer 2 Status and
Control Register
(T2SC)
Timer 2 Counter
Register High
(T2CNTH)
Read:
Write:
Reset:XXXXXXXX
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TOIE TSTOP
0
MS1A ELS1B ELS1A TOV1 CH1MAX
00
PS2 PS1 PS0
$002D
$002E
$002F
$0030
Timer 2 Counter
Register Low
(T2CNTL)
Timer 2 Counter Modulo
Register High
(T2MODH)
Timer 2 Counter Modulo
Register Low
(T2MODL)
Timer 2 Channel 0 Status
and Control Register
(T2SC0)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 12)
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
= Unimplemented R = Reserved
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
52 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
$0031
$0032
$0033
$0034
$0035
$0036
Timer 2 Channel 0
Register High
(T2CH0H)
Timer 2 Channel 0
Register Low
(T2CH0L)
Timer 2 Channel 1 Status
and Control Register
(T2SC1)
Timer 2 Channel 1
Register High
(T2CH1H)
Timer 2 Channel 1
Register Low
(T2CH1L)
PLL Control Register
(PTCL)
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:00100000
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
PLLF
PLLIE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
PLLON BCS PRE1 PRE0 VPR1 VPR0
$0037
$0038
$0039
$003A
PLL Bandwidth Control
Register
(PBWC)
PLL Multiplier Select
Register High
(PMSH)
PLL Multiplier Select
Register Low
(PMSL)
PLL VCO Range Select
Register
(PMRS)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12)
Read:
AUTO
Write:
Reset:0000000
Read: 0000
Write:
Reset:00000000
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
LOCK
ACQ
0000
R
MUL11 MUL10 MUL9 MUL8
= Unimplemented R = Reserved
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 53
Memory Map
Addr.Register Name Bit 7654321Bit 0
PLL Reference Divider
$003B
$003C Unimplemented
$003D Unimplemented
$003E Unimplemented
$003F Unimplemented
Select Register
$0040 Unimplemented
(PMDS)
Read: 0000
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
0
00
0
RDS3 RDS2 RDS1 RDS0
0001
$0041 Unimplemented
$0042 Unimplemented
$0043 Unimplemented
$0044 Unimplemented
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
= Unimplemented R = Reserved
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
54 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read:
$0045 Unimplemented
Timebase Control
$0046
Register
(TBCR)
$0047 Unimplemented
$0048
$0049
$004A
MMIIC Address Register
(MMADR)
MMIIC Control Register 1
(MMCR1)
MMIIC Control Register 2
(MMCR2)
Write:
Reset:
Read: TBIF
TBR2 TBR1 TBR0
Write:
0
TBIE TBON R
TA CK
Reset:0000000
Read:
Write:
Reset:
Read:
MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1
MMEXTAD
Write:
Reset:10100000
Read:
MMEN MMIEN
Write:
00
MMCLRBB
MMTXAK REPSEN
MMCRCBYTE
SDASCL1
Reset:00000000
Read: MMALIF MMNAKIF MMBB
MMAST MMRW
00
MMCRCEF
Write: 0 0
Reset:0000000
Unaffected
$004B
MMIIC Status Register
MMIIC Data Transmit
$004C
MMIIC Data Receive
$004D
MMIIC CRC Data Register
$004E
MMCRCBF
(MMSR)
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK
Write: 0 0
Reset:00001010
Read:
MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0
Register
(MMDTR)
Write:
Reset:00000000
Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0
Register
(MDDRR)
(MMCRDR)
Write:
Reset:00000000
MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
Read:
Write:
Reset:00000000
U = Unaffected X = Indeterminate
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12)
MMTXBE MMRXBF
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 55
Memory Map
Addr.Register Name Bit 7654321Bit 0
MMIIC Frequency Divider
$004F
$0050 Reserved
$0051
$0052
$0053
$0054
PWM Control Register
PWM Clock Control
PWM Data Register 0
PWM Data Register 1
Register
(MMFDR)
(PWMCR)
Register
(PWMCCR)
(PWMDR0)
(PWMDR1)
Read: 00000
Write:
Reset:00000100
Read:
Write:
Reset:
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
RRRRRRRR
00
PWMEN2 PWMEN1 PWMEN0
00000
PCLKSEL
0PWMD7 0PWMD6 0PWMD5 0PWMD4 0PWMD3 0PWMD2 0PWMD1 0PWMD0
1PWMD7 1PWMD6 1PWMD5 1PWMD4 1PWMD3 1PWMD2 1PWMD1 1PWMD0
MMBR2 MMBR1 MMBR0
PCH2 PCH1 PCH0
PCLK1 PCLK0
$0055
$0056
$0057
$0058
PWM Data Register 2
(PWMDR2)
PWM Phase Control
Register
(PWMPCR)
ADC Status and Control
Register
(ADSCR)
ADC Clock Control
Register
(ADICLK)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 12)
Read:
2PWMD7 2PWMD6 2PWMD5 2PWMD4 2PWMD3 2PWMD2 2PWMD1 2PWMD0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: COCO
Write:
Reset:00011111
Read:
Write:
Reset:00000100
PHEN PHD6 PHD5 PHD4 PHD3 PHD2 PHD1 PHD0
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
00
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
R
= Unimplemented R = Reserved
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
56 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read: ADx ADx ADx ADx ADx ADx ADx ADx
ADC Data Register High 0
$0059
$005A
$005B
$005C
$005D
(ADRH0)
ADC Data Register Low 0
(ADRL0)
ADC Data Register Low 1
(ADRL1)
ADC Data Register Low 2
(ADRL3)
ADC Data Register Low 3
(ADRL3)
Write:RRRRRRRR
Reset:00000000
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset:00000000
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset:00000000
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset:00000000
ADC Auto-scan Control
$005E
$005F Unimplemented
SIM Break Status Register
$FE00
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
$FE01
Register
(ADASCR)
(SBSR)
(SRSR)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12)
Read: 00000
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
RRRRRR
Write: Note
Reset: 0
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
= Unimplemented R = Reserved
AUTO1 AUTO0 ASCAN
SBSW
R
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 57
Memory Map
Addr.Register Name Bit 7654321Bit 0
$FE02 Reserved
SIM Break Flag Control
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
Interrupt Status Register 3
$FE06
$FE07 Reserved
Register
(SBFCR)
(INT1)
(INT2)
(INT3)
Read:
RRRRRRRR
Write:
Reset:
Read:
BCFERRRRRRR
Write:
Reset: 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
Read: 00000IF17IF16IF15
Write:RRRRRRRR
Reset:00000000
Read:
RRRRRRRR
Write:
$FE08
$FE09
$FE0A Reserved
$FE0B Reserved
FLASH Control Register
(FLCR)
FLASH Block Protect
Register (FLBPR)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 12)
Reset:
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
Read:
RRRRRRRR
Write:
Reset:
Read:
RRRRRRRR
Write:
Reset:
= Unimplemented R = Reserved
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
58 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Break Address Register
$FE0C
Break Address Register
$FE0D
Break Status and Control
$FE0E
Low-Voltage Inhibit Status
$FE0F
Mask Option Register
$FF80
High
(BRKH)
Low
(BRKL)
Register
(BRKSCR)
Register
(LVISR)
(MOR)*
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: LVIOUT 0000000
Write:
Reset:00000000
Read:
Write:
Erased:11111111
Reset:UUUUUUUU
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
000000
BRKE BRKA
OSCSEL1OSCSEL0RRRRRR
* MOR is a non-volatile FLASH register; write by programming.
Read: Low byte of reset vector
$FFFF
COP Control Register
(COPCTL)
U = Unaffected X = Indeterminate
Write: Writing clears COP counter (any value)
Reset:UUUUUUUU
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12)
= Unimplemented R = Reserved
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Memory Map 59
Memory Map
Table 2-1. Vector Addresses
.
Vector Priority Vector Address Vector
Lowest
Highest $FFFF Reset Vector (Low)
IF17
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
—
$FFDA Timebase Module Interrupt Vector (High)
$FFDB Timebase Module Interrupt Vector (Low)
$FFDC Analog Module Interrupt Vector (High)
$FFDD Analog Module Interrupt Vector (Low)
$FFDE ADC Conversion Complete Vector (High)
$FFDF ADC Conversion Complete Vector (Low)
$FFE0 Keyboard Vector (High)
$FFE1 Keyboard Vector (Low)
$FFE2 SCI Transmit Vector (High)
$FFE3 SCI Transmit Vector (Low)
$FFE4 SCI Receive Vector (High)
$FFE5 SCI Receive Vector (Low)
$FFE6 SCI Error Vector (High)
$FFE7 SCI Error Vector (Low)
$FFE8 MMIIC Interrupt Vector (High)
$FFE9 MMIIC Interrupt Vector (Low)
$FFEA TIM2 Overflow Vector (High)
$FFEB TIM2 Overflow Vector (Low)
$FFEC TIM2 Channel 1 Vector (High)
$FFED TIM2 Channel 1 Vector (Low)
$FFEE TIM2 Channel 0 Vector (High)
$FFEF TIM2 Channel 0 Vector (Low)
$FFF0 TIM1 Overflow Vector (High)
$FFF1 TIM1 Overflow Vector (Low)
$FFF2 TIM1 Channel 1 Vector (High)
$FFF3 TIM1 Channel 1 Vector (Low)
$FFF4 TIM1 Channel 0 Vector (High)
$FFF5 TIM1 Channel 0 Vector (Low)
$FFF6 PLL Vector (High)
$FFF7 PLL Vector (Low)
$FFF8 IRQ2
$FFF9 IRQ2
$FFFA IRQ1
$FFFB IRQ1
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
Vector (High)
Vector (Low)
Vector (High)
Vector (Low)
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
60 Memory Map Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.2 Introduction
This section describes the 512 bytes of RAM (random-access memory).
3.3 Functional Description
Addresses $0060 through $025F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K-byte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Random-Access Memory (RAM) 61
Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
62 Random-Access Memory (RAM) Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 4. FLASH Memory
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .66
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .67
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .70
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor FLASH Memory 63
FLASH Memory
Addr.Register Name Bit 7654321Bit 0
Read: 0000
$FE08
$FE09
FLASH Control Register
(FLCR)
FLASH Block Protect
Register (FLBPR)
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 12,288 bytes for user
memory plus a block of 38 bytes for user interrupt vectors and one byte
for the mask option register. An erased bit reads as logic 1 and a
programmed bit reads as a logic 0. The FLASH memory page size is
defined as 128 bytes, and is the minimum size that can be erased in a
page erase operation. Program and erase operations are facilitated
through control bits in FLASH control register (FLCR). The address
ranges for the FLASH memory are:
HVEN MASS ERASE PGM
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
= Unimplemented
• $C000–$EFFF; user memory, 12,288 bytes
• $FFDA–$FFFF; user interrupt vectors, 38 bytes
• $FF80; mask option register
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
1
64 FLASH Memory Freescale Semiconductor
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address: $FE08
Bit 7654321Bit 0
FLASH Memory
FLASH Control Register
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Figure 4-2. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
1 = Mass Erase operation selected
0 = Block Erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor FLASH Memory 65
FLASH Memory
4.5 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page
consists of 128 consecutive bytes starting from addresses $xx00 or
$xx80. The 38-byte user interrupt vectors area also forms a page. The
38-byte user interrupt vectors cannot be erased by the page erase
operation because of security reasons. Mass erase is required to erase
this page.
1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Write any data to any FLASH address within the page address
range desired.
3. Wait for a time, t
(10µs).
nvs
4. Set the HVEN bit.
5. Wait for a time, t
Erase
(1ms).
6. Clear the ERASE bit.
7. Wait for a time, t
8. Clear the HVEN bit.
9. After time, t
rcv
mode.
NOTE: Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps.
(5µs).
nvh
(1µs), the memory can be accessed again in read
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
66 FLASH Memory Freescale Semiconductor
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read
as logic 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Write any data to any FLASH address within the FLASH memory
address range.
FLASH Memory
FLASH Mass Erase Operation
3. Wait for a time, t
(10µs).
nvs
4. Set the HVEN bit.
5. Wait for a time t
MErase
(4ms).
6. Clear the ERASE bit.
7. Wait for a time, t
nvhl
(100µs).
8. Clear the HVEN bit.
9. After time, t
(1µs), the memory can be accessed again in read
rcv
mode.
NOTE: Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor FLASH Memory 67
FLASH Memory
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $xx00, $xx40,
$xx80, or $xxC0. The procedure for programming a row of the FLASH
memory is outlined below:
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Write any data to any FLASH address within the row address
range desired.
3. Wait for a time, t
(10µs).
nvs
4. Set the HVEN bit.
5. Wait for a time, t
pgs
(5µs).
6. Write data to the FLASH address to be programmed.
7. Wait for time, t
Prog
(30µs).
8. Repeat step 6 and 7 until all the bytes within the row are
programmed.
9. Clear the PGM bit.
10. Wait for time, t
nvh
(5µs).
11. Clear the HVEN bit.
12. After time, t
(1µs), the memory can be accessed again in read
rcv
mode.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE: Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps. Do
not exceed t
Characteristics.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
68 FLASH Memory Freescale Semiconductor
maximum. See 24.18 FLASH Memory
Prog
FLASH Memory
FLASH Program Operation
Figure 4-3 shows a flowchart representation for programming the
FLASH memory.
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
Write any data to any FLASH address
Set PGM bit
within the row address range desired
3
4
5
6
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address
to be programmed
7
Wait for a time, t
nvs
pgs
Prog
Completed
programming
Y
this row?
N
NOTE:
9
Clear PGM bit
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
10
Wait for a time, t
nvh
must not exceed the maximum programming
Prog
max.
11
Clear HVEN bit
time, t
This row program algorithm assumes the row/s
to be programmed are initially erased.
12
Wait for a time, t
rcv
End of Programming
Figure 4-3. FLASH Programming Flowchart
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor FLASH Memory 69
FLASH Memory
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
pages of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE: When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set,
the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register.
The content of this register determine the starting location of the
protected range within the FLASH memory.
Address: $FE09
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Register Bit7 to Bit 0
BPR[7:1] represent bits [13:7] of a 16-bit memory address. Bits
[15:14] are logic 1s and bits [6:0] are logic 0s.
Bit 7654321Bit 0
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 4-4. FLASH Block Protect Register (FLBPR)
16-bit memory address
Start address of FLASH block protect 11 0000000
BPR[7:1]
Figure 4-5. FLASH Block Protect Start Address
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
70 FLASH Memory Freescale Semiconductor
FLASH Memory
FLASH Protection
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00 or XX80 (at
page boundaries) within the FLASH memory.
Examples of protect start address:
BPR[7:0] Start of Address of Protect Range
$00 or $01
$02 or $03 $C080 (1100 0000 1000 0000)
$04 or $05 $C100 (1100 0001 0000 0000)
$06 or $07 $C180 (1100 0001 1000 0000)
$08 or $09 $C200 (1100 0010 0000 0000)
and so on...
$F8 or $F9 $FE00 (1111 1110 0000 0000)
$FA or $FB $FE80 (1111 1110 1000 0000)
$FC or $FD $FF00 (1111 1111 0000 0000)
$FE $FF80 (1111 1111 1000 0000)
$FF The entire FLASH memory is not protected.
Note:
The end address of the protected range is always $FFFF.
$C000 (1100 0000 0000 0000)
The entire FLASH memory is protected.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor FLASH Memory 71
FLASH Memory
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
72 FLASH Memory Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 5. Configuration and Mask Option Registers
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .75
5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .77
5.6 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.2 Introduction
This section describes the configuration registers, CONFIG1 and
CONFIG2; and the mask option register, MOR.
(CONFIG & MOR)
The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (218 – 24 or 213 – 24 ICLK cycles)
• Low-voltage inhibit (LVI) module power
• LVI module reset
• LVI module in stop mode
• LVI module voltage trip point selection
• STOP instruction
• Stop mode recovery time (32 ICLK cycles or 4096 ICLK cycles)
• Oscillator (internal, RC, and crystal) during stop mode
• Serial communications interface clock source (CGMXCLK or f
• Current detect output pin
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
BUS
)
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) 73
Configuration and Mask Option
The mask option register selects one of the following oscillator options
as the MCU reference clock:
• Internal oscillator
• RC oscillator
• Crystal oscillator
Addr.Register Name Bit 7654321Bit 0
Read:
$001D
$001F
$FF80
* FLASH register. Reset:UUUUUUUU
† One-time writable register after each reset.
†† Reset by POR only.
Configuration Register 2
(CONFIG2)
Configuration Register 1
(CONFIG1)
Mask Option Register
(MOR)*
Write:
†
Reset:00000000
Read:
Write:
†
Reset:00000
Read:
Write:
Erased:11111111
STOP_
ICLKEN
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
OSCSEL1OSCSEL0RRRRRR
STOP_
RCLKEN
= Unimplemented R = Reserved
STOP_
XCLKEN
OSCCLK1 OSCCLK0
††
0
CDOEN
000
SCIBDSRC
Figure 5-1. CONFIG and MOR Register Summary
5.3 Functional Description
The configuration registers and the mask option register are used in the
initialization of various options. These two types of registers are
configured differently:
• Configuration registers — Write-once registers after reset
• Mask option register — FLASH register (write by programming)
The configuration registers can be written once after each reset. All of
the configuration register bits are cleared during reset. Since the various
options affect the operation of the MCU, it is recommended that these
registers be written immediately after reset. The configuration registers
are located at $001D and $001F. The configurations register may be
read at anytime.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
74 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
Configuration and Mask Option Registers (CONFIG & MOR)
NOTE: The options except LVI5OR3 are one-time writable by the user after
each reset. The LVI5OR3 bit is one-time writable by the user only after
each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in Figure 5-2 and Figure 5-3.
The mask option register (MOR) is used for selecting one of the three
clock options for the MCU. The MOR is a byte located in FLASH
memory, and is written to by a FLASH programming routine.
5.4 Configuration Register 1 (CONFIG1)
Address: $001F
Bit 7654321Bit 0
Configuration Register 1 (CONFIG1)
Read:
Write:
Reset:00000*000
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
* Reset by POR only.
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 21. Computer Operating Properly (COP).)
13
1 = COP time out period = 2
0 = COP time out period = 2
– 24 ICLK cycles
18
– 24 ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) 75
Configuration and Mask Option
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 22. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5V or 3V Operating Mode
LVI5OR3 selects the voltage operating mode of the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI).) The voltage mode selected
for the LVI should match the operating VDD. See Section 24.
Electrical Specifications for the LVI voltage trip points for each of
the modes.
1 = LVI operates in 5V mode
0 = LVI operates in 3V mode
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK
cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, and it is disabled during stop mode
(STOP_XCLKEN= 0), do not set the SSREC bit.
NOTE: When the LVI is disabled in stop mode (LVISTOP=0), the system
stabilization time for long stop recovery (4096 ICLK cycles) gives a delay
longer than the LVI’s turn-on time. There is no period where the MCU is
not protected from a low power condition. However, when using the
short stop recovery configuration option, the 32 ICLK delay is less than
the LVI’s turn-on time and there exists a period in start-up where the LVI
is not protecting the MCU.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
76 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
Configuration and Mask Option Registers (CONFIG & MOR)
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 21. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
5.5 Configuration Register 2 (CONFIG2)
Address: $001D
Bit 7654321Bit 0
Configuration Register 2 (CONFIG2)
Read:
Write:
Reset:00000000
STOP_
ICLKEN
STOP_
RCLKEN
STOP_
XCLKEN
OSCCLK1 OSCCLK0
0
CDOEN
SCIBDSRC
Figure 5-3. Configuration Register 2 (CONFIG2)
STOP_ICLKEN — Internal Oscillator Stop Mode Disable
STOP_ICLKEN disables the internal oscillator during stop mode.
Setting the STOP_ICLKEN bit disables the oscillator during stop
mode. (See 7.4 Internal Oscillator).
Reset clears this bit.
1 = Internal oscillator disabled during stop mode
0 = Internal oscillator enabled to operate during stop mode
STOP_RCLKEN — RC Oscillator Stop Mode Enable
STOP_RCLKEN enables the RC oscillator to continue operating
during stop mode. Setting the STOP_RCLKEN bit allows the
oscillator to operate continuously even during stop mode. This is
useful for driving the timebase module to allow it to generate periodic
wake up while in stop mode. (See Section 8. Clock Generator
Module (CGM) and subsection 8.8.2 Stop Mode.)
Reset clears this bit.
1 = RC oscillator enabled to operate during stop mode
0 = RC oscillator disabled during stop mode
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) 77
Configuration and Mask Option
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
STOP_XCLKEN enables the crystal (x-tal) oscillator to continue
operating during stop mode. Setting the STOP_XCLKEN bit allows
the x-tal oscillator to operate continuously even during stop mode.
This is useful for driving the timebase module to allow it to generate
periodic wake up while in stop mode. (See Section 8. Clock
Generator Module (CGM) and subsection 8.8.2 Stop Mode.)
Reset clears this bit.
1 = X-tal oscillator enabled to operate during stop mode
0 = X-tal oscillator disabled during stop mode
OSCCLK1, OSCCLK0 — Oscillator Output Control Bits
OSCCLK1 and OSCCLK0 select which oscillator output to be driven
out as OSCCLK to the timebase module (TBM). Reset clears these
two bits.
OSCCLK1 OSCCLK0 Timebase Clock Source
0 0 Internal oscillator (ICLK)
0 1 RC oscillator (RCCLK)
1 0 X-tal oscillator (XTAL)
1 1 Not used
CDOEN — Current-Flow Detect Output Enable
CDOEN enables the port pin PC0/PWM0/CD as the CD output pin for
the current detect flag (CDIF) from the analog module. Reset clears
the CDOEN bit.
1 = PCO/PWMO/CD pin enabled as CD output pin,
PTC0 and PWM0 functions are disabled.
0 = PTC0/PWM/CD pin disabled as CD output pin,
PTC0 or PWM0 functions are available; see 18.5.1 Port C
Data Register (PTC).
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
78 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
SCIBDSRC — SCI Baud Rate Clock Source
SCIBDSRC selects the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock, f
0 = Oscillator clock, CGMXCLK, is used as clock source for SCI
5.6 Mask Option Register (MOR)
The mask option register (MOR) is used for selecting one of the three
clock options for the MCU. The MOR is a byte located in FLASH
memory, and is written to by a FLASH programming routine.
Address: $FF80
Bit 7654321B
Configuration and Mask Option Registers (CONFIG & MOR)
Mask Option Register (MOR)
, is used as clock source for SCI
BUS
OSCSEL1, OSCSEL0 — Oscillator Selection Bits
OSCSEL1 and OSCSEL0 select which oscillator is used for the MCU
CGMXCLK clock. The erase state of these two bits is logic 1. These
bits are unaffected by reset. (See Table 5-1).
Bits 5–0 — Should be left as 1’s.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) 79
Configuration and Mask Option
Table 5-1. CGMXCLK Clock Selection
OSCSEL1 OSCSEL0 CGMXCLK OSC2 pin Comments
0 0 — — Not used
01ICLKf
1 0 RCCLK f
11X-TAL
BUS
BUS
Inverting
output of
XTAL
Internal oscillator generates the CGMXCLK.
RC oscillator generates the CGMXCLK.
Internal oscillator is available after each POR
or reset.
X-tal oscillator generates the CGMXCLK.
Internal oscillator is available after each POR
or reset.
NOTE: The internal oscillator is a free running oscillator and is available after
each POR or reset. It is turned-off in stop mode by clearing the
STOP_ICLKEN bit in CONFIG2.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
80 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
Data Sheet — MC68HC908SR12•MC68HC08SR12
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.2 Introduction
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 81
Central Processor Unit (CPU)
6.3 Features
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64K-byte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64K-bytes
6.4 CPU Registers
• Low-power stop and wait modes
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
82 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
6.4.1 Accumulator
7
15
H X
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 83
Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64K-byte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
Bit
1413121110987654321
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Bit
0
Figure 6-3. Index Register (H:X)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
84 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
6.4.4 Program Counter
Bit
1413121110987654321
15
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 6-4. Stack Pointer (SP)
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
1413121110987654321
15
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Bit
0
Figure 6-5. Program Counter (PC)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 85
Central Processor Unit (CPU)
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X11X1XXX
V11H I NZC
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
86 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 87
Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
6.6.1 Wait Mode
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
88 Central Processor Unit (CPU) Freescale Semiconductor
6.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Central Processor Unit (CPU)
CPU During Break Interrupts
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
6.9 Opcode Map
See Table 6-2.
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 89
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary
Source
Form
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add with Carry A ← (A) + (M) + (C) RR– RRR
Add without Carry A ← (A) + (M) RR– RRR
Operation Description
Effect on
CCR
VH I NZC
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
A9
B9
C9
D9
E9
F9
9EE9
9ED9
AB
BB
CB
DB
EB
FB
9EEB
9EDB
Opcode
Operand
Cycles
2
ii
3
dd
4
hh ll
4
ee ff
3
ff
2
4
ff
5
ee ff
2
ii
3
dd
4
hh ll
4
ee ff
3
ff
2
4
ff
5
ee ff
AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
Logical AND A ← (A) & (M) 0 – – RR–
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right
C
b7
b7
0
b0
b0
C
R ––RRR
R ––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
A4
B4
C4
D4
E4
F4
9EE4
9ED4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
11
13
15
17
19
1B
1D
1F
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd
dd
dd
dd
dd
dd
dd
dd
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
4
4
4
4
4
4
4
4
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
90 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Opcode Map
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3
BHS rel
BIH rel Branch if IRQ
BIL rel Branch if IRQ
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
BLE opr
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Branch if Higher or Same
(Same as BCC)
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
Bit Test (A) & (M) 0 – – RR–
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3
PC ← (PC) + 2 +rel ? (Z) | (N ⊕ V) = 0––––––REL 92 rr 3
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
2
ii
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
PC ← (PC) + 2 +rel ? (Z)
A5
B5
C5
D5
E5
F5
9EE5
9ED5
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 91
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
Source
Form
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––R
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 –––––R
Operation Description
CCR
VH I NZC
Address
Mode
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
00
02
04
06
08
0A
0C
0E
Opcode
Operand
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
Cycles
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
DIR (b0)
DIR (b1)
BSET n,opr Set Bit n in M Mn ← 1 ––––––
PC ← (PC) + 2; push (PCL)
BSR rel Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Compare and Branch if Equal
Clear
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
––––––REL AD rr 4
––––––
0––01–
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
10
12
14
16
18
1A
1C
1E
31
41
51
61
71
9E61
3F
4F
5F
8C
6F
7F
9E6F
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
4
4
4
4
4
4
4
4
5
4
4
5
4
6
3
1
1
1
3
2
4
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
92 Central Processor Unit (CPU) Freescale Semiconductor
Source
Form
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
Operation Description
Compare A with M (A) – (M) R ––RRR
CCR
VH I NZC
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
Opcode Map
Opcode
Operand
ii
A1
dd
B1
hh ll
C1
ee ff
D1
ff
E1
F1
ff
9EE1
ee ff
9ED1
Cycles
2
3
4
4
3
2
4
5
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA Decimal Adjust A (A)
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Complement (One’s Complement)
Compare H:X with M (H:X) – (M:M + 1) R ––RRR
Compare X with M (X) – (M) R ––RRR
Decrement and Branch if Not Zero
Decrement
M ← (M
) = $FF – (M)
A ← (A
) = $FF – (M)
X ← (X
) = $FF – (M)
M ← (M
) = $FF – (M)
M ← (M
) = $FF – (M)
M ← (M
) = $FF – (M)
A ← (A) –1 or M ← (M) –1 or X← (X) –1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ←
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
10
(M) – 1
dd
DIR
INH
0––RR1
U––RRRINH 72 2
––––––
R ––RR–
INH
IX1
IX
SP1
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
33
43
53
ff
63
73
9E63
ff
6575ii ii+1dd3
ii
A3
dd
B3
hh ll
C3
ee ff
D3
ff
E3
F3
ff
9EE3
ee ff
9ED3
dd rr
3B
rr
4B
rr
5B
ff rr
6B
rr
7B
ff rr
9E6B
dd
3A
4A
5A
ff
6A
7A
9E6A
ff
4
1
1
4
3
5
4
2
3
4
4
3
2
4
5
5
3
3
5
4
6
4
1
1
4
3
5
DIV Divide
A ← (H:A)/(X)
H ← Remainder
––––RRINH 52 7
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 93
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Source
Form
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Exclusive OR M with A A ← (A ⊕ M) 0––RR–
Increment
Jump PC ← Jump Address ––––––
Operation Description
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
Effect on
CCR
VH I NZC
R ––RR–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
Address
Mode
A8
B8
C8
D8
E8
F8
9EE8
9ED8
3C
4C
5C
6C
7C
9E6C
BC
CC
DC
EC
FC
Opcode
Operand
Cycles
2
ii
3
dd
4
hh ll
4
ee ff
3
ff
2
4
ff
5
ee ff
dd
4
1
1
ff
4
3
ff
5
2
dd
3
hh ll
4
ee ff
3
ff
2
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr
,X
LSL ,X
LSL opr,SP
PC ← (PC) + n (n = 1, 2, or 3)
Jump to Subroutine
Load A from M A ← (M) 0––RR–
Load H:X from M H:X ← (M:M + 1) 0––RR–
Load X from M X ← (M) 0––RR–
Logical Shift Left
(Same as ASL)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
C
b7
0
b0
––––––
R ––RRR
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
dd
BD
hh ll
CD
ee ff
DD
ff
ED
FD
ii
A6
dd
B6
hh ll
C6
ee ff
D6
ff
E6
F6
ff
9EE6
ee ff
9ED6
4555ii jjdd3
ii
AE
dd
BE
hh ll
CE
ee ff
DE
ff
EE
FE
ff
9EEE
ee ff
9EDE
dd
38
48
58
ff
68
78
9E68
ff
4
5
6
5
4
2
3
4
4
3
2
4
5
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
94 Central Processor Unit (CPU) Freescale Semiconductor
Source
Form
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
Operation Description
Logical Shift Right R ––0RR
b7
C0
b0
CCR
VH I NZC
DIR
INH
INH
IX1
IX
SP1
Address
Mode
Opcode Map
Opcode
Operand
dd
34
44
54
ff
64
74
9E64
ff
Cycles
4
1
1
4
3
5
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP No Operation None – – – – – – INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2
Move
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – RR–
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
← (M)
Source
0––RR–
R ––RRR
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
4E
5E
6E
7E
30
40
50
60
70
9E60
AA
BA
CA
DA
EA
FA
9EEA
9EDA
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
5
4
4
4
4
1
1
4
3
5
2
3
4
4
3
2
4
5
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2
dd
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry R ––RRR
C
b7
b0
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
4
1
1
4
ff
3
5
ff
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 95
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
Source
Form
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
Rotate Right through Carry R ––RRR
Operation Description
b7
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
b0
C
CCR
VH I NZC
RRRRRRINH 80 7
DIR
INH
INH
IX1
IX
SP1
Address
Mode
36
46
56
66
76
9E66
Opcode
Operand
dd
ff
ff
Cycles
4
1
1
4
3
5
RTS Return from Subroutine
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – RR– DIR 35 dd 4
STOP Enable IRQ
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Subtract with Carry A ← (A) – (M) – (C) R ––RRR
Store A in M M ← (A) 0––RR–
Pin; Stop Oscillator I ← 0; Stop Oscillator – – 0 – – – INH 8E 1
Store X in M M ← (X) 0––RR–
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
––––––INH 81 4
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
B7
C7
D7
E7
F7
9EE7
9ED7
BF
CF
DF
EF
FF
9EEF
9EDF
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
3
4
4
3
2
4
5
3
4
4
3
2
4
5
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
96 Central Processor Unit (CPU) Freescale Semiconductor
Table 6-1. Instruction Set Summary (Continued)
Source
Form
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI Software Interrupt
Subtract A ← (A) – (M) R ––RRR
Operation Description
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Central Processor Unit (CPU)
Opcode Map
Effect on
CCR
VH I NZC
––1–––INH 83 9
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
A0
B0
C0
D0
E0
F0
9EE0
9ED0
Opcode
Operand
2
ii
3
dd
4
hh ll
4
ee ff
3
ff
2
4
ff
5
ee ff
Cycles
TAP Transfer A to CCR CCR ← (A) RRRRRRINH 84 2
TAX Transfer A to X X ← (A) ––––––INH 97 1
TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A ← (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – –
RR–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 97
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
Source
Form
A Accumulator n Any bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location R Set or cleared
N Negative bit — Not affected
Operation Description
⊕ Logical EXCLUSIVE OR
« Sign extend
CCR
VH I NZC
Address
Mode
Opcode
Operand
Cycles
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
98 Central Processor Unit (CPU) Freescale Semiconductor
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 99
Table 6-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
MSB
LSB
05BRSET0
15BRCLR0
25BRSET1
35BRCLR1
45BRSET2
55BRCLR2
65BRSET3
75BRCLR3
85BRSET4
95BRCLR4
A5BRSET5
B5BRCLR5
C5BRSET6
D5BRCLR6
E5BRSET7
F5BRCLR7
01234569E6789ABCD9EDE9EEF
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
4
BSET0
2DIR
4
BCLR0
2DIR
4
BSET1
2DIR
4
BCLR1
2DIR
4
BSET2
2DIR
4
BCLR2
2DIR
4
BSET3
2DIR
4
BCLR3
2DIR
4
BSET4
2DIR
4
BCLR4
2DIR
4
BSET5
2DIR
4
BCLR5
2DIR
4
BSET6
2DIR
4
BCLR6
2DIR
4
BSET7
2DIR
4
BCLR7
2DIR
3
BRA
2REL
3
BRN
2REL
3
BHI
2REL
3
BLS
2REL
3
BCC
2REL
3
BCS
2REL
3
BNE
2REL
3
BEQ
2REL
3
BHCC
2REL
3
BHCS
2REL
3
BPL
2REL
3
BMI
2REL
3
BMC
2REL
3
BMS
2REL
3
BIL
2REL
3
BIH
2REL
4
NEG
2DIR
5
CBEQ
3DIR
4
COM
2DIR
4
LSR
2DIR
4
STHX
2DIR
4
ROR
2DIR
4
ASR
2DIR
4
LSL
2DIR
4
ROL
2DIR
4
DEC
2DIR
5
DBNZ
3DIR
4
INC
2DIR
3
TST
2DIR
3
CLR
2DIR
1
NEGA
1INH
4
CBEQA
3IMM
5
MUL
1INH
1
COMA
1INH
1
LSRA
1INH
3
LDHX
3IMM
1
RORA
1INH
1
ASRA
1INH
1
LSLA
1INH
1
ROLA
1INH
1
DECA
1INH
3
DBNZA
2INH
1
INCA
1INH
1
TSTA
1INH
5
MOV
3DD
1
CLRA
1INH
1
NEGX
1INH
4
CBEQX
3IMM
7
DIV
1INH
1
COMX
1INH
1
LSRX
1INH
4
LDHX
2DIR
1
RORX
1INH
1
ASRX
1INH
1
LSLX
1INH
1
ROLX
1INH
1
DECX
1INH
3
DBNZX
2INH
1
INCX
1INH
1
TSTX
1INH
4
MOV
2DIX+
1
CLRX
1INH
4
NEG
2IX1
3IX1+
1INH
2IX1
2IX1
3IMM
2IX1
2IX1
2IX1
2IX1
2IX1
3IX1
2IX1
2IX1
3IMD
2IX1
5
CBEQ
3
NSA
4
COM
4
LSR
3
CPHX
4
ROR
4
ASR
4
LSL
4
ROL
4
DEC
5
DBNZ
4
INC
3
TST
4
MOV
3
CLR
3SP1
4SP1
3SP1
3SP1
3SP1
3SP1
3SP1
3SP1
3SP1
4SP1
3SP1
3SP1
3SP1
5
NEG
6
CBEQ
5
COM
5
LSR
ROR
5
ASR
5
LSL
5
ROL
5
DEC
6
DBNZ
5
INC
4
TST
4
CLR
NEG
1IX
CBEQ
2IX+
DAA
1INH
COM
1IX
LSR
1IX
CPHX
2DIR
5
ROR
1IX
ASR
1IX
LSL
1IX
ROL
1IX
DEC
1IX
DBNZ
2IX
INC
1IX
TST
1IX
MOV
2IX+D
CLR
1IX
3
4
2
3
3
4
3
3
3
3
3
4
3
2
4
2
7
RTI
1INH
4
RTS
1INH
9
SWI
1INH
2
TA P
1INH
1
TPA
1INH
2
PULA
1INH
2
PSHA
1INH
2
PULX
1INH
2
PSHX
1INH
2
PULH
1INH
2
PSHH
1INH
1
CLRH
1INH
1
STOP
1INH
1
WAIT
1INH
3
BGE
2REL
3
BLT
2REL
3
BGT
2REL
3
BLE
2REL
2
TXS
1INH
2
TSX
1INH
1
TA X
1INH
1
CLC
1INH
1
SEC
1INH
2
CLI
1INH
2
SEI
1INH
1
RSP
1INH
1
NOP
1INH
*
1
TXA
1INH
2
SUB
2IMM
2
CMP
2IMM
2
SBC
2IMM
2
CPX
2IMM
2
AND
2IMM
2
BIT
2IMM
2
LDA
2IMM
2
AIS
2IMM
2
EOR
2IMM
2
ADC
2IMM
2
ORA
2IMM
2
ADD
2IMM
4
BSR
2REL
2
LDX
2IMM
2
AIX
2IMM
3
SUB
2DIR
3
CMP
2DIR
3
SBC
2DIR
3
CPX
2DIR
3
AND
2DIR
3
BIT
2DIR
3
LDA
2DIR
3
STA
2DIR
3
EOR
2DIR
3
ADC
2DIR
3
ORA
2DIR
3
ADD
2DIR
2
JMP
2DIR
4
JSR
2DIR
3
LDX
2DIR
3
STX
2DIR
4
SUB
3EXT
4
CMP
3EXT
4
SBC
3EXT
4
CPX
3EXT
4
AND
3EXT
4
BIT
3EXT
4
LDA
3EXT
4
STA
3EXT
4
EOR
3EXT
4
ADC
3EXT
4
ORA
3EXT
4
ADD
3EXT
3
JMP
3EXT
5
JSR
3EXT
4
LDX
3EXT
4
STX
3EXT
4
SUB
3IX2
4
CMP
3IX2
4
SBC
3IX2
4
CPX
3IX2
4
AND
3IX2
4
BIT
3IX2
4
LDA
3IX2
4
STA
3IX2
4
EOR
3IX2
4
ADC
3IX2
4
ORA
3IX2
4
ADD
3IX2
4
JMP
3IX2
6
JSR
3IX2
4
LDX
3IX2
4
STX
3IX2
5
SUB
4SP2
5
CMP
4SP2
5
SBC
4SP2
5
CPX
4SP2
5
AND
4SP2
5
BIT
4SP2
5
LDA
4SP2
5
STA
4SP2
5
EOR
4SP2
5
ADC
4SP2
5
ORA
4SP2
5
ADD
4SP2
5
LDX
4SP2
5
STX
4SP2
3
SUB
2IX1
3
CMP
2IX1
3
SBC
2IX1
3
CPX
2IX1
3
AND
2IX1
3
BIT
2IX1
3
LDA
2IX1
3
STA
2IX1
3
EOR
2IX1
3
ADC
2IX1
3
ORA
2IX1
3
ADD
2IX1
3
JMP
2IX1
5
JSR
2IX1
3
LDX
2IX1
3
STX
2IX1
4
SUB
3SP1
4
CMP
3SP1
4
SBC
3SP1
4
CPX
3SP1
4
AND
3SP1
4
BIT
3SP1
4
LDA
3SP1
4
STA
3SP1
4
EOR
3SP1
4
ADC
3SP1
4
ORA
3SP1
4
ADD
3SP1
4
LDX
3SP1
4
STX
3SP1
SUB
1IX
CMP
1IX
SBC
1IX
CPX
1IX
AND
1IX
BIT
1IX
LDA
1IX
STA
1IX
EOR
1IX
ADC
1IX
ORA
1IX
ADD
1IX
JMP
1IX
JSR
1IX
LDX
1IX
STX
1IX
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
Central Processor Unit (CPU)
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
MSB
LSB
Low Byte of Opcode in Hexadecimal 05BRSET0
0 High Byte of Opcode in Hexadecimal
3DIR
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
Opcode Map
Central Processor Unit (CPU)
Data Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
100 Central Processor Unit (CPU) Freescale Semiconductor
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