Freescale MC68HC908QY4, MC68HC908QY2, MC68HC908QT2, MC68HC908QY1, MC68HC908QT1 DATA SHEET
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MC68HC908QY4
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Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4/D
Rev. 5
07/2005
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MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
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MC68HC908QT1
Data Sheet
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MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 3)
Date
September,
2002
December,
2002
January,
2003
Revision
Level
N/A Initial release N/A
1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list. 19
Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages. 21
Figure 2-1. Memory Map — Clarified illegal address and unimplemented
memory.
Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for
Port A Data Register (PTA) and Data Direction Register A (DDRA).
Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard
interrupt and ADC conversion complete interrupt.
Chapter 13 System Integration Module (SIM) — Removed reference to break
status register as it is duplicated in break module.
11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified
oscillator trim option ordering information and what to expect with untrimmed
device.
Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected. 98
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) —
0.1
0.2 4.2 Features — Corrected third bulleted item. 49
Diagram updated for clarity.
Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7,
DDRA7, and DDRA6.
Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7. 100
Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for
DDRA7 and DDRA6.
Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1 103
Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion
of auto wakeup for clarity.
Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity. 49
Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation. 87
Chapter 16 Electrical Specifications — Extensive changes made to electrical
specifications.
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case
outline drawing for DFN package.
Chapter 17 Ordering Information and Mechanical Specifications — Added
ordering information for DFN package.
Description
Page
Number(s)
27
27
118
113
92
150
99
101
83
169
177
185
MC68HC908QY/QT Family Data Sheet, Rev. 5
4 Freescale Semiconductor
Revision History (Sheet 2 of 3)
Date
August,
2003
October,
2003
January,
2004
Revision
Level
1.0
2.0
3.0
Description
Reformatted to meet latest M68HC08 documentation standards N/A
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt
module and TCLK pin designator.
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator. 21
Table 1-2. Pin Functions — Added TCLK pin description. 22
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to
add TCLK.
Figure 2-1. Memory Map — Corrected names for the IRQ status and control
register (INTSCR) bits 3–0.
3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock
prescaler bits.
4.3 Functional Description — Updated periodic wakeup request values. 51
Figure 6-1. COP Block Diagram — Reworked for clarity 59
Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF,
ACK, and IMASK
Chapter 14 Timer Interface Module (TIM) — Added TCLK function. 131–139
15.3 Monitor Module (MON) — Updated with additional data. 147
Chapter 16 Electrical Specifications — Updated with additional data. 169–173
Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented
areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available.
Also corrected $FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity 59
6.3.2 STOP Instruction — Added subsection 60
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity. 111
Table 13-2. Reset Recovery Timing — Replaced previous table with new
information.
Chapter 14 Timer Interface Module (TIM) — Updated with additional data. 131
Figure 15-3. Break I/O Register Summary — Corrected bit designators for the
BRKAR register
15.3 Monitor Module (MON) — Clarified seventh bullet. 147
Table 17-1. MC Order Numbers — Corrected temperature and package
designators.
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
Oscillator Trim Value at $FFC0.
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
Page
Number(s)
20
23
26
47
77–79
27
112
143
175
32
38
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 5
Revision History
Revision History (Sheet 3 of 3)
Date
November,
2004
July,
2005
Revision
Level
4.0
5.0
Description
Reformatted to meet current documentation standards Throughout
6.3.1 BUSCLKX4 — Clarified description of BUSCLKX4 58
Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary:
Reworked definitions for STOP instruction
Added WAIT instruction
13.8.1 SIM Reset Status Register — Clarified SRSR flag setting 117
14.9.1 TIM Status and Control Register — Added information to TSTOP note 127
16.8 5-V Oscillator Characteristics — Added values for deviation from trimmed
inernal oscillator
16.12 3-V Oscillator Characteristics — Added values for deviation from trimmed
inernal oscillator
Figure 5-2. Configuration Register 1 (CONFIG1) — Clarified bit definitions for
COPRS.
Chapter 8 External Interrupt (IRQ) — Reworked for clarification. 73
11.3.4 RC Oscillator — Improved RC oscillator wording. 93
12.1 Introduction — Added note pertaining to non-bonded port pins. 97
17.3 Package Dimensions — Updated package information. 165
Page
Number(s)
70
71
155
158
54
MC68HC908QY/QT Family Data Sheet, Rev. 5
6 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Chapter 8 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 13 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Chapter 14 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .165
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 7
List of Chapters
MC68HC908QY/QT Family Data Sheet, Rev. 5
8 Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6 Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6 FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.2 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6.3 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6.4 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6.5 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.6.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 9
Table of Contents
3.6 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.7.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.6 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6.1 Port A I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.1 BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MC68HC908QY/QT Family Data Sheet, Rev. 5
10 Freescale Semiconductor
Chapter 7
Central Processor Unit (CPU)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 8
External Interrupt (IRQ)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3.1 MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.3.2 MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.7.1 IRQ Input Pins (IRQ
8.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.1 Keyboard Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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9.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.7.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.3.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.3.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.3.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 11
Oscillator Module (OSC)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.3.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3.1.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3.2 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3.3 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.3.4 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.4 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.4.4 XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.4.6 Internal Oscillator Clock (INTCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.4.7 Oscillator Out 2 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.4.8 Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.8 Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.8.1 Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 13
System Integration Module (SIM)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.2 RST
13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.3.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
13.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chapter 14
Timer Interface Module (TIM)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.8 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.8.1 TIM Clock Pin (PTA2/TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.9 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Chapter 15
Development Support
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
15.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
15.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
15.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
MC68HC908QY/QT Family Data Sheet, Rev. 5
14 Freescale Semiconductor
15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Chapter 16
Electrical Specifications
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.5 5-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.6 Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
16.7 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
16.8 5-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
16.9 3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16.10 Typical 3.0-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
16.11 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16.12 3-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
16.13 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.14 Analog-to-Digital Converter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.16 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Chapter 17
Ordering Information and Mechanical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
17.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
17.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 15
Table of Contents
MC68HC908QY/QT Family Data Sheet, Rev. 5
16 Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with
a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
0.4
Table 1-1. Summary of Device Variations
Device
MC68HC908QT1 1536 bytes — 8 pins
MC68HC908QT2 1536 bytes 4 ch, 8 bit 8 pins
MC68HC908QT4 4096 bytes 4 ch, 8 bit 8 pins
MC68HC908QY1 1536 bytes — 16 pins
MC68HC908QY2 1536 bytes 4 ch, 8 bit 16 pins
MC68HC908QY4 4096 bytes 4 ch, 8 bit 16 pins
FLASH
Memory Size
Analog-to-Digital
Converter
1.2 Features
Features include:
• High-performance M68HC08 CPU core
• Fully upward-compatible object code with M68HC05 Family
• 5-V and 3-V operating voltages (V
• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V
• Trimmable internal oscillator
– 3.2 MHz internal bus operation
– 8-bit trim capability allows 0.4% accuracy
– ± 25% untrimmed
• Auto wakeup from STOP capability
• Configuration (CONFIG) register for MCU configuration options, including:
– Low-voltage inhibit (LVI) trip point
• In-system FLASH programming
• FLASH security
(2)
DD
)
(1)
Pin
Count
1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming.
2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 17
General Description
• On-chip in-application programmable FLASH memory (with internal program/erase voltage
generation)
– MC68HC908QY4 and MC68HC908QT4 — 4096 bytes
– MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes
• 128 bytes of on-chip random-access memory (RAM)
• 2-channel, 16-bit timer interface module (TIM)
• 4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2, MC68HC908QY4,
MC68HC908QT2, and MC68HC908QT4
• 5 or 13 bidirectional input/output (I/O) lines and one input only:
– Six shared with keyboard interrupt function and ADC
– Two shared with timer channels
– One shared with external interrupt (IRQ)
– Eight extra I/O lines on 16-pin package only
– High current sink/source capability on all port pins
– Selectable pullups on all ports, selectable on an individual bit basis
– Three-state ability on all port pins
• 6-bit keyboard interrupt with wakeup feature (KBI)
• Low-voltage inhibit (LVI) module features:
– Software selectable trip point in CONFIG register
• System protection features:
– Computer operating properly (COP) watchdog
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• External asynchronous interrupt pin with internal pullup (IRQ
) shared with general-purpose input
pin
• Master asynchronous reset pin (RST
) shared with general-purpose input/output (I/O) pin
• Power-on reset
• Internal pullups on IRQ
and RST to reduce external components
• Memory mapped I/O registers
• Power saving stop and wait modes
• MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are available in these packages:
– 16-pin plastic dual in-line package (PDIP)
– 16-pin small outline integrated circuit (SOIC) package
– 16-pin thin shrink small outline package (TSSOP)
• MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages:
– 8-pin PDIP
– 8-pin SOIC
– 8-pin dual flat no lead (DFN) package
MC68HC908QY/QT Family Data Sheet, Rev. 5
18 Freescale Semiconductor
MCU Block Diagram
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QY4.
1.4 Pin Assignments
The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in 8-pin packages and the
MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 in 16-pin packages. Figure 1-2 shows the pin
assignment for these packages.
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 19
General Description
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA3/RST
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
/KBI3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER SUPPLY
PTA
PTB
8-BIT ADC
128 BYTES RAM
DDRA
DDRB
V
DD
V
SS
M68HC08 CPU
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
SINGLE INTERRUPT
MODULE
BREAK
MODULE
POWER-ON RESET
MODULE
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 1-1. Block Diagram
MC68HC908QY/QT Family Data Sheet, Rev. 5
20 Freescale Semiconductor
Pin Assignments
V
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
PTA3/RST
/KBI3
V
PTB7
PTB6
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
PTB5
PTB4
PTA3/RST
/KBI3
DD
1
2
3
4
8
7
6
5
8-PIN ASSIGNMENT
MC68HC908QT1 PDIP/SOIC
1
DD
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16-PIN ASSIGNMENT
MC68HC908QY1 PDIP/SOIC
V
SS
PTA0/TCH0/KBI0
PTA1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
V
SS
PTB0
PTB1
PTA0/TCH0/KBI0
PTA1/TCH1/KBI1
PTB2
PTB3
PTA2/IRQ
/KBI2/TCLK
V
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTA3/RST
/KBI3
1
DD
2
3
4
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC
V
PTB7
PTB6
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTB5
PTB4
PTA3/RST
/KBI3
1
DD
2
3
4
5
6
7
8
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC
V
SS
8
PTA0/AD0/TCH0/KBI0
7
6
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
5
V
16
SS
15
PTB0
14
PTB1
PTA0/AD0/TCH0/KBI0
13
PTA1/AD1/TCH1/KBI1
12
11
PTB2
10
PTB3
PTA2/IRQ
9
/KBI2/TCLK
PTA0/TCH0/KBI0
PTB1
PTB0
V
V
PTB7
PTB6
PTA5/OSC1/KBI5
PTA0/TCH0/KBI0
PTA5/OSC1/KB15
1
2
3
4
SS
5
DD
6
7
8
16-PIN ASSIGNMENT
MC68HC908QY1 TSSOP
1
2
V
SS
V
3
DD
4
8-PIN ASSIGNMENT
MC68HC908QT1 DFN
PTA1/TCH1/KBI1
16
PTB2
15
PTB3
14
PTA2/IRQ
13
PTA3/RST
12
11
PTB4
10
PTB5
9
PTA4/OSC2/KBI4
8
PTA1/TCH1/KBI1
7
PTA2/IRQ/KBI2/TCLK
6
PTA3/RST
PTA4/OSC2/KBI4
5
/KBI2/TCLK
/KBI3
/KBI3
PTA0/AD0/TCH0/KBI0
PTA5/OSC1/AD3/KBI5
PTA0/AD0/TCH0/KBI0
PTA5//OSC1/AD3/KB15
Figure 1-2. MCU Pin Assignments
PTB1
PTB0
V
V
PTB7
PTB6
1
2
3
4
SS
5
DD
6
7
8
PTA1/AD1/TCH1/KBI1
16
PTB2
15
PTB3
14
PTA2/IRQ
13
PTA3/RST
12
11
PTB4
10
PTB5
9
PTA4/OSC2/AD2/KBI4
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 TSSOP
1
V
2
SS
V
3
DD
4
8
PTA1/AD1/TCH1/KBI1
7
PTA2/IRQ/KBI2/TCLK
6
PTA3/RST
PTA4/OSC2/AD2/KBI4
5
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 DFN
/KBI2/TCLK
/KBI3
/KBI3
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 21
General Description
1.5 Pin Functions
Table 1-2 provides a description of the pin functions.
Table 1-2. Pin Functions
Pin
Name
V
DD
V
SS
PTA0
PTA1
PTA2
PTA3
Description Input/Output
Power supply Power
Power supply ground Power
PTA0 — General purpose I/O port Input/Output
AD0 — A/D channel 0 input Input
TCH0 — Timer Channel 0 I/O Input/Output
KBI0 — Keyboard interrupt input 0 Input
PTA1 — General purpose I/O port Input/Output
AD1 — A/D channel 1 input Input
TCH1 — Timer Channel 1 I/O Input/Output
KBI1 — Keyboard interrupt input 1 Input
PTA2 — General purpose input-only port Input
— External interrupt with programmable pullup and Schmitt trigger input Input
IRQ
KBI2 — Keyboard interrupt input 2 Input
TCLK — Timer clock input Input
PTA3 — General purpose I/O port Input/Output
RST — Reset input, active low with internal pullup and Schmitt trigger Input
KBI3 — Keyboard interrupt input 3 Input
PTA4 — General purpose I/O port Input/Output
OSC2 —XTAL oscillator output (XTAL option only)
PTA4
PTA5
PTB[0:7]
1. The PTB pins are not available on the 8-pin packages (see note in 12.1 Introduction).
22 Freescale Semiconductor
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
AD2 — A/D channel 2 input Input
KBI4 — Keyboard interrupt input 4 Input
PTA5 — General purpose I/O port Input/Output
OSC1 — XTAL, RC, or external oscillator input Input
AD3 — A/D channel 3 input Input
KBI5 — Keyboard interrupt input 5 Input
(1)
8 general-purpose I/O ports Input/Output
MC68HC908QY/QT Family Data Sheet, Rev. 5
Output
Output
Pin Function Priority
1.6 Pin Function Priority
Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin.
NOTE
Upon reset all pins come up as input ports regardless of the priority table.
Table 1-3. Function Priority in Shared Pins
Pin Name Highest-to-Lowest Priority Sequence
PTA0 AD0 → TCH0 → KBI0 → PTA0
PTA1 AD1 →TCH1 → KBI1 → PTA1
PTA2 IRQ
PTA3 RST
PTA4 OSC2 → AD2 → KBI4 → PTA4
PTA5 OSC1 → AD3 → KBI5 → PTA5
→ KBI2 → TCLK → PTA2
→ KBI3 → PTA3
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 23
General Description
MC68HC908QY/QT Family Data Sheet, Rev. 5
24 Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown
in Figure 2-1, includes:
• 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4
• 1536 bytes of user FLASH for MC68HC908QT2, MC68HC908QT1, MC68HC908QY2, and
MC68HC908QY1
• 128 bytes of random access memory (RAM)
• 48 bytes of user-defined vectors, located in FLASH
• 416 bytes of monitor read-only memory (ROM)
• 1536 bytes of FLASH program and erase routines, located in ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-1
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in
register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 25
Memory
$0000
↓
$003F
$0040
↓
$007F
$0080
↓
$00FF
$0100
↓
$27FF
$2800
↓
$2DFF
$2E00
↓
$EDFF
$EE00
↓
$FDFF
$FE00 BREAK STATUS REGISTER (BSR)
$FE01 RESET STATUS REGISTER (SRSR)
$FE02 BREAK AUXILIARY REGISTER (BRKAR)
$FE03 BREAK FLAG CONTROL REGISTER (BFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE05 INTERRUPT STATUS REGISTER 2 (INT2)
$FE06 INTERRUPT STATUS REGISTER 3 (INT3)
$FE07
$FE08
$FE09 BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0A BREAK ADDRESS LOW REGISTER (BRKL)
$FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0C LVISR
$FE0D
↓
$FE0F
$FE10
↓
$FFAF
$FFB0
↓
$FFBD
$FFBE FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFBF
$FFC0 INTERNAL OSCILLATOR TRIM VALUE
$FFC1
$FFC2
↓
$FFCF
$FFD0
↓
$FFFF
RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)
MC68HC908QT4 AND MC68HC908QY4
FLASH CONTROL REGISTER (FLCR)
I/O REGISTERS
64 BYTES
RESERVED
64 BYTES
128 BYTES
UNIMPLEMENTED
9984 BYTES
AUXILIARY ROM
1536 BYTES
UNIMPLEMENTED
49152 BYTES
FLASH MEMORY
4096 BYTES
RESERVED FOR FLASH TEST
MONITOR ROM 416 BYTES
14 BYTES
RESERVED FLASH
RESERVED FLASH
14 BYTES
USER VECTORS
48 BYTES
(1)
RAM
(1)
(1)
3 BYTES
FLASH
FLASH
Note 1.
Attempts to execute code from addresses in this
range will generate an illegal address reset.
UNIMPLEMENTED
51712 BYTES
FLASH MEMORY
1536 BYTES
MC68HC908QT1, MC68HC908QT2,
MC68HC908QY1, and MC68HC908QY2
Memory Map
$2E00
↓
$F7FF
$F800
↓
$FDFF
Figure 2-1. Memory Map
MC68HC908QY/QT Family Data Sheet, Rev. 5
26 Freescale Semiconductor
Input/Output (I/O) Section
2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
•$FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
•$FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value — Optional
• $FFFF — COP control register, COPCTL
Addr.Register Name Bit 7654321Bit 0
Port A Data Register
$0000
Port B Data Register
$0001
$0002 Unimplemented
$0003 Unimplemented
Data Direction Register A
$0004
Data Direction Register B
$0005
(PTA)
See page 98.
(PTB)
See page 100.
(DDRA)
See page 98.
(DDRB)
See page 101.
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
R
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
R R DDRA5 DDRA4 DDRA3
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
AWUL
= Unimplemented R = Reserved U = Unaffected
PTA5 PTA4 PTA3
PTA2
0
DDRA1 DDRA0
PTA1 PTA0
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 27
Memory
Addr.Register Name Bit 7654321Bit 0
$0006
Unimplemented
↓
$000A
Unimplemented
Port A Input Pullup Enable
$000B
Register (PTAPUE)
See page 99.
Port B Input Pullup Enable
$000C
Register (PTBPUE)
See page 102.
$000D
↓
Unimplemented
$0019
Keyboard Status and
$001A
Control Register (KBSCR)
See page 83.
Keyboard Interrupt
$001B
Enable Register (KBIER)
See page 84.
$001C Unimplemented
IRQ Status and Control
$001D
Register (INTSCR)
See page 77.
Configuration Register 2
$001E
(CONFIG2)
See page 53.
Read:
Write:
OSC2EN
0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Reset:00000000
Read:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
Write:
Reset:00000000
Read: 0 0 0 0 KEYF 0
Write: ACKK
IMASKK MODEK
Reset:00000000
Read: 0
Write:
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Reset:00000000
Read: 0 0 0 0 IRQF 0
Write: ACK
IMASK MODE
Reset:00000000
Read:
(1)
Reset:00000000
IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN
Write:
(2)
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
Read:
(1)
Write:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
Reset:00000
(2)
000
$001F
Configuration Register 1
(CONFIG1)
See page 54.
1. One-time writable register after each reset.
2. LVI5OR3 reset to 0 by a power-on reset (POR) only.
$0020
$0021
TIM Status and Control
Register (TSC)
See page 127.
TIM Counter Register High
(TCNTH)
See page 128.
Read: TOF
Write: 0 TRST
TOIE TSTOP
Reset:00100000
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
00
PS2 PS1 PS0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 5
28 Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Read: CH0F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CH1IE
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
↓
$0035
TIM Counter Register Low
(TCNTL)
See page 128.
TIM Counter Modulo
Register High (TMODH)
See page 129.
TIM Counter Modulo
Register Low (TMODL)
See page 129.
TIM Channel 0 Status and
Control Register (TSC0)
See page 130.
TIM Channel 0
Register High (TCH0H)
See page 132.
TIM Channel 0
Register Low (TCH0L)
See page 132.
TIM Channel 1 Status and
Control Register (TSC1)
See page 130.
TIM Channel 1
Register High (TCH1H)
See page 132.
TIM Channel 1
Register Low (TCH1L)
See page 132.
Unimplemented
Oscillator Status Register
$0036
$0037 Unimplemented Read:
Oscillator Trim Register
$0038
(OSCSTAT)
See page 96.
(OSCTRIM)
See page 96.
Read:
Write:
Reset:00000000
Read:
Write:
Reset:10000000
RRRRRRECGON
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
= Unimplemented R = Reserved U = Unaffected
ECGST
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor 29
Memory
Addr.Register Name Bit 7654321Bit 0
$0039
↓
$003B
Unimplemented
ADC Status and Control
$003C
$003D Unimplemented
$003E
$003F
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07 Reserved RRRRRRRR
Register (ADSCR)
See page 45.
ADC Data Register
(ADR)
See page 47.
ADC Input Clock Register
(ADICLK)
See page 47.
Break Status Register
(BSR)
See page 137.
SIM Reset Status Register
(SRSR)
See page 117.
Break Auxiliary
Register (BRKAR)
See page 137.
Break Flag Control
Register (BFCR)
See page 138.
Interrupt Status Register 1
(INT1)
See page 77.
Interrupt Status Register 2
(INT2)
See page 77.
Interrupt Status Register 3
(INT3)
See page 77.
Read: COCO
Write: R
Reset:00011111
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset:00000000
Read:
Write: See note 1
Reset: 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
Read:0000000
Write:
Reset:00000000
Read:
Write:
Reset: 0
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Read:IF140000000
Write:RRRRRRRR
Reset:00000000
Read:0000000IF15
Write:RRRRRRRR
Reset:00000000
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADIV2 ADIV1 ADIV0
RRRRRR
1. Writing a 0 clears SBSW.
BCFERRRRRRR
AIEN ADCO CH4 CH3 CH2 CH1 CH0
00000
SBSW
R
BDCOP
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 5
30 Freescale Semiconductor
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