查询MC908QF4CFJ供应商
..
.
Freescale Semiconductor, Inc.
MC68HC908QF4
nc
Freescale Semiconductor, I
M68HC08
Microcontrollers
Data Sheet
MC68HC908QF4
Rev. 1.0
6/2004
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC68HC908QF4
Data Sheet
To provide the most up-to-date information, the revision of our documents on the
World Wide Web will be the most current. Your printed copy may be an earlier
nc...
I
revision. To verify you have the latest information available, refer to:
http://motorola.com/semiconductors/
cale Semiconductor,
Frees
The following revision history table summarizes changes contained in this
document. For your convenience, the page number designators have been linked
to the appropriate location.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA 3
For More Information On This Product,
Go to: www.freescale.com
Revision History
Freescale Semiconductor, Inc.
Revision History
Date
October,
2003
June,
2004
nc...
I
Revision
Level
N/A Initial release N/A
Removed references to MC68HC908QF3, MC68HC908QF2, and
MC68HC908QF1
1.0
17.4 Thermal Characteristics — Updated 32-pin TQFP value 176
18.2 MC Order Numbers — Updated table entries for MC order numbers 193
Description
cale Semiconductor,
Page
Number(s)
Throughout
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
4 Revision History MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908QF4
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Section 3. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . .37
Section 4. Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . .45
List of Sections
nc...
I
cale Semiconductor,
Frees
Section 5. Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . .51
Section 6. Computer Operating Properly (COP) . . . . . . . . . . . . . . . . .55
Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . .59
Section 8. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Section 9. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . .79
Section 10. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . .87
Section 11. Oscillator Module (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . .91
Section 12. PLL Tuned UHF Transmitter Module. . . . . . . . . . . . . . . .101
Section 13. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . .111
Section 14. System Integration Module (SIM) . . . . . . . . . . . . . . . . . .119
Section 15. Timer Interface Module (TIM). . . . . . . . . . . . . . . . . . . . . .137
Section 16. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Section 17. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .175
Section 18. Ordering Information and Mechanical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA List of Sections 5
For More Information On This Product,
Go to: www.freescale.com
List of Sections
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
6 List of Sections MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908QF4
Table of Contents
Section 1. General Description
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
nc...
I
Section 2. Memory
cale Semiconductor,
Frees
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6 FLASH Memory (FLASH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6.2 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6.3 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.4 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.5 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Section 3. Analog-to-Digital Converter (ADC)
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.1 ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.3 Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 7
For More Information On This Product,
Go to: www.freescale.com
Table of Contents
Freescale Semiconductor, Inc.
3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.6 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.7.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.7.3 ADC Input Clock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Section 4. Auto Wakeup Module (AWU)
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
nc...
I
cale Semiconductor,
Frees
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6.1 Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.6.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . 48
4.6.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 5. Configuration Register (CONFIG)
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Section 6. Computer Operating Properly (COP)
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.1 BUSCLKX4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.4 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Sheet MC68HC908QF4 — Rev. 1.0
8 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.8 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table of Contents
Section 7. Central Processor Unit (CPU)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
nc...
I
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
cale Semiconductor,
Frees
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.8 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Section 8. External Interrupt (IRQ)
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.4 IRQ
8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Section 9. Keyboard Interrupt Module (KBI)
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.3.2 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 9
For More Information On This Product,
Go to: www.freescale.com
Table of Contents
nc...
I
Freescale Semiconductor, Inc.
9.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 83
9.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . 84
9.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 85
Section 10. Low-Voltage Inhibit (LVI)
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.3.1 Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.3.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.3.3 Voltage Hysteresis Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.3.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.4 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
cale Semiconductor,
Frees
10.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Section 11. Oscillator Module (OSC)
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.1.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.2 External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3.3 XTAL Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3.4 RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.4 Oscillator Module Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4). . . . . . . . . . 96
11.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . 96
11.4.4 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.4.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.4.6 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.7 Oscillator Out 2 (BUSCLKX4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.8 Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data Sheet MC68HC908QF4 — Rev. 1.0
10 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
11.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.8 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.8.1 Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . 99
Table of Contents
Section 12. PLL Tuned UHF Transmitter Module
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.2 Transmitter Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3 Phase-Lock Loop (PLL) and Local Oscillator. . . . . . . . . . . . . . . . . . . . 103
12.4 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
nc...
I
cale Semiconductor,
Frees
12.5 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.6 Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.7 State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.9 Data Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.10 Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.10.1 Application Schematics in OOK and FSK Modulation . . . . . . . . . . 107
12.10.2 Complete Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Section 13. Input/Output (I/O) Ports
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.2.1 Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.2.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.2.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 114
13.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.3.1 Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.3.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.3.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 116
Section 14. System Integration Module (SIM)
14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.2 RST
14.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 121
14.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . 122
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 11
and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
For More Information On This Product,
Go to: www.freescale.com
Table of Contents
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
14.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . 123
14.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . 124
14.4.2.3 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . 126
14.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 126
14.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . 132
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
14.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.8.1 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.8.2 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Section 15. Timer Interface Module (TIM)
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.3 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.4.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.4.3.2 Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.4.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 143
15.4.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . 144
15.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Data Sheet MC68HC908QF4 — Rev. 1.0
12 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
15.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.8 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.8.1 TIM Clock Pin (PTA2/TCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1). . . . . . . . . . 146
15.9 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.9.3 TIM Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . 150
15.9.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table of Contents
nc...
I
cale Semiconductor,
Frees
Section 16. Development Support
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16.2 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . 158
16.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
16.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
16.2.2 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 159
16.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.3 Monitor Module (MON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
16.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16.3.1.3 Monitor Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
16.3.2 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Section 17. Electrical Specifications
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
17.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
17.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 13
For More Information On This Product,
Go to: www.freescale.com
Table of Contents
nc...
I
Freescale Semiconductor, Inc.
17.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
17.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
17.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
17.7 Typical 3.0-V Output Drive Characteristics. . . . . . . . . . . . . . . . . . . . . . 179
17.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
17.9 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
17.10 Analog-to-Digital (ADC) Converter Characteristics. . . . . . . . . . . . . . . . 183
17.10.1 ADC Electrical Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 183
17.10.2 ADC Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 183
17.11 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 184
17.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
17.13 UHF Transmitter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
17.13.1 UHF Module Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . 186
17.13.2 UHF Module Output Power Measurement . . . . . . . . . . . . . . . . . . . 190
cale Semiconductor,
Frees
Section 18. Ordering Information
and Mechanical Specifications
18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
18.3 32-Pin Plastic Low-Profile Quad Flat Pack
(Case No. 873A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Data Sheet MC68HC908QF4 — Rev. 1.0
14 Table of Contents MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
1.1 Introduction
nc...
I
Freescale Semiconductor, Inc.
Section 1. General Description
The MC68HC908QF4 MCU is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). Optimized for low-power
operation and available in a small 32-pin low-profile quad flat pack (LQFP), this
MCU is well suited for remote keyless entry (RKE) transmitter designs, tire
pressure monitoring (TPM), or other remote sensing and wireless RF data
transmission applications.
All MCUs in the M68HC908 Family use the enhanced M68HC08 central processor
unit (CPU08) and are available with a variety of modules, me mory sizes and types,
and package types.
1.2 Features
cale Semiconductor,
Frees
Features of the MC68HC908QF4 MCU include:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6 805, M146805, and M68HC05
Families
• Operating voltage range of 2.2 to 3.6 V
• Maximum internal bus frequency of 2 MHz
• Trimmable internal oscillator
– 4-MHz operating frequency for a 1-MHz bus frequency
– 8-bit trim capability allows 0.4% accuracy
– ±25 percent accuracy untrimmed
• Auto wakeup from STOP capability
• 4096 bytes of on-chip FLASH memory
• FLASH program memory security
• 128 bytes of on-chip RAM
• 16-bit, 2-channel timer interface module (TIM)
• 4 channel, 8-bit analog-to-digital converter (ADC)
(2)
(1)
1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming.
2. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA General Description 15
For More Information On This Product,
Go to: www.freescale.com
General Description
Freescale Semiconductor, Inc.
• 13 general-purpose input/output (I/O) ports:
– Six shared with keyboard wakeup function
– Three shared with the timer module, IRQ
– Port A pins have 3-mA sink capabilities
• Low-voltage inhibit (LVI) module with selectable trip points:
– 2.12 V detection forces MCU into reset
– 2.32 V detection sets indicator flag
• 6-bit keyboard interrupt with wakeup feature (KBI)
• External asynchronous interrupt pin with internal pullup (IRQ
• Ultra high frequency (UHF) RF transmitter:
– Ultra low sleep mode current
nc...
I
Features of the CPU08 include:
cale Semiconductor,
– ASK and FSK modulation selectable
• System protection features:
– Computer operating properly (COP) reset
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• 32-pin plastic LQFP package
• Power saving stop and wait modes
• Master reset pin (RST
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
) shared with general-purpose I/O pin
)
Frees
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Third party C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QF4 MCU.
Data Sheet MC68HC908QF4 — Rev. 1.0
16 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
General Description
Pin Assignments
nc...
I
cale Semiconductor,
Frees
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA
PTB
V
MODE
PLLEN
DATA
BS
OP1
GND
REXT
XTAL1
XTAL0
UPCLK
PFD
DDRA
M68HC08 CPU
DDRB
MC68HC908QF4
4096 BYTES
USER FLASH
CC
PTA3/RST
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
TRANSMITTER
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
/KBI3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
8-BIT ADC
128 BYTES RAM
UHF
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
SINGLE INTERRUPT
MODULE
BREAK
MODULE
POWER-ON RESET
MODULE
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
MONITOR ROM
POWER SUPPLY
V
DD
V
SS
Figure 1-1. Block Diagram
1.4 Pin Assignments
The MC68HC908QF4 is available in a 32-pin plastic low-profile quad flat pack
(LQFP). Figure 1-2 shows the pin assignment for this package.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA General Description 17
For More Information On This Product,
Go to: www.freescale.com
General Description
1.5 Pin Functions
nc...
I
Freescale Semiconductor, Inc.
Table 1-1 provides a description of the pin functions other than those dedicated to
the UHF module which are shown in Table 1-2.
PTA5/OSC1/KBI5
PTB6
PTB7
26
25
V
24
DD
V
23
SS
PTB0
22
PTB1
21
PTA3/RST/KBI3
PTA2/IRQ/KBI2
PTB3
PTB2
PTB4
32
1
2
3
4
PTA4/OSC2/KBI4
PTB5
31
30
NC
29
NC
28
27
cale Semiconductor,
Frees
Pin
Name
V
DD
V
SS
PTA0
PTA1/TCH1/KBI1
GND
XTAL1
XTAL0
5
6
7
8
9
10
11
12
13
14
15
16
REXT
CFSK
CC
V
RFOUT
GNDRF
CC
V
ENABLE
20
19
18
17
MODE
PTA0/TCH0/KBI0
DATA CLK
DATA
BAND
Figure 1-2. MC68HC908QF4 Pin Assignments
Table 1-1. Pin Functions
Description Input/Output
Pow er supply Pow er
Powe r supply ground Power
PTA0 — General purpose I/O port Input/Output
TCH0 — Timer Channel 0 I/O Input/Output
KBI0 — Keyboard interrupt input 0 Input
PTA1 — General purpose I/O port Input/Output
PTA1
Data Sheet MC68HC908QF4 — Rev. 1.0
18 General Description MOTOROLA
TCH1 — Timer Channel 1 I/O Input/Output
KBI1 — Keyboard interrupt input 1 Input
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 1-1. Pin Functions (Continued)
General Description
Pin Functions
nc...
I
cale Semiconductor,
Frees
Pin
Name
PTA2 — General purpose input-only port Input
— External interrupt with programmable pullup
PTA2
PTA3
PTA4
PTA5
PTB[0:7] 8 general-purpose I/O ports Input/Output
IRQ
and Schmitt trigger input
KBI2 — Keyboard interrupt input 2 Input
PTA3 — General purpose I/O port Input/Output
— Reset input, active low with internal pullup and Schmitt trigger Input
RST
KBI3 — Keyboard interrupt input 3 Input
PTA4 — General purpose I/O port Input/Output
OSC2 —XTAL oscillator output (XTAL option only)
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
KBI4 — Keyboard interrupt input 4 Input
PTA5 — General purpose I/O port Input/Output
OSC1 —XTAL, RC, or external oscillator input Input
KBI5 — Keyboard interrupt input 5 Input
Description Input/Output
Input
Output
Output
Table 1-2. UHF Transmitter Pins
Pin Function Description
6 GND Ground
7 XTAL1 Reference oscillator input
8 XTAL0 Reference oscillator output
9 REXT Output amplifier current setting resistor
10 CFSK FSK switch output
11
12 RFOUT Power amplifier output
13 GNDRF Power amplifier ground
14
15 ENABLE Enable input
16 MODE Modulation type selection input
V
CC
V
CC
Power supply
Power supply
17 BAND Frequency band selection
18 DATA Data input
19 DATACLK Clock output to the microcontroller
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA General Description 19
For More Information On This Product,
Go to: www.freescale.com
General Description
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
20 General Description MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
2.1 Introduction
nc...
I
Freescale Semiconductor, Inc.
Section 2. Memory
The central processor unit (CPU08) can address 64 Kbytes of memory space. The
memory map, shown in Figure 2-1, includes:
• 4096 bytes of user FLASH
• 128 bytes of random access memory (RAM)
• 48 bytes of user-defined vectors, located in FLASH
• 416 bytes of monitor read-only memory (ROM)
• 1536 bytes of FLASH program and erase routines, located in ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can have unpredictable effects on MCU
operation. In Figure 2-1 and in register figures in this document, unimplemented
locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation.
In Figure 2-1 and in register figures in this document, reserved locations are
marked with the word Reserved or with the letter R.
cale Semiconductor,
Frees
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 21
For More Information On This Product,
Go to: www.freescale.com
Memory
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
$0000
↓
$003F
$0040
↓
$007F
$0080
↓
$00FF
$0100
↓
$27FF
$2800
↓
$2DFF
$2E00
↓
$EDFF
$EE00
↓
$FDFF
$FE00
↓
$FE0F
$FE10
↓
$FFAF
$FFB0
↓
$FFBD
$FFBE FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFBF
$FFC0 INTERNAL OSCILLATOR TRIM VALUE
$FFC1 RESERVED FLASH
$FFC2
↓
$FFCF
$FFD0
↓
$FFFF
I/O REGISTERS
64 BYTES
RESERVED
64 BYTES
RAM
128 BYTES
UNIMPLEMENTED
9984 BYTES
AUXILIARY ROM
1536 BYTES
UNIMPLEMENTED
49152 BYTES
FLASH MEMORY
4096 BYTES
SYSTEM REGISTERS
MONITOR ROM 416 BYTES
FLASH
14 BYTES
RESERVED FLASH
FLASH
14 BYTES
USER VECTORS
48 BYTES
Figure 2-1. Memory Map
Data Sheet MC68HC908QF4 — Rev. 1.0
22 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status,
and data registers. Additional I/O registers have these addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
Memory
Input/Output (I/O) Section
nc...
I
cale Semiconductor,
Frees
• $FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
•$FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value — Optional
• $FFFF — COP control register, COPCTL
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 23
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
$0000
$0001
$0002
↓
$0003
Port A Data Register
(PTA)
See page 112.
Port B Data Register
(PTB)
See page 115.
Unimplemented
Read:
Write:
Reset: UNAFFECTED BY RESET
Read:
Write:
Reset: Unaffected by reset
R
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
AWUL
PTA5 PTA4 PTA3
PTA2
PTA1 PTA0
nc...
I
cale Semiconductor,
Frees
Data Direction Register A
$0004
Data Direction Register B
$0005
$0006
↓
$000A
Port A Input Pullup Enable
$000B
$000C
$000D
↓
$0019
$001A
$001B
$001C Unimplemented
Register (PTAPUE)
Port B Input Pullup Enable
Register (PTBPUE)
Keyboard Status and
Control Register (KBSCR)
Keyboard Interrupt
Enable Register (KBIER)
(DDRA)
See page 113.
(DDRB)
See page 115.
Unimplemented
See page 114.
See page 116.
Unimplemented
See page 84.
See page 85.
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:0000KEYF0
Write:
Reset:00000000
Read: 0
Write:
Reset:00000000
R R DDRA5 DDRA4 DDRA3
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
OSC2EN
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
0
ACKK
DDRA1 DDRA0
IMASKK MODEK
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
Data Sheet MC68HC908QF4 — Rev. 1.0
24 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Read:0000IRQF10
Write:
Reset:00000000
Read:
(1)
Write:
Reset:00000000
$001D
$001E
IRQ Status and Control
Register (INTSCR)
See page 77.
Configuration Register 2
(CONFIG2)
See page 51.
IRQPUD IRQEN R OSCOPT1 OSCOPT0
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
Memory
Input/Output (I/O) Section
ACK1
R
IMASK1 MODE1
R RSTEN
(2)
nc...
I
cale Semiconductor,
Frees
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
Configuration Register 1
(CONFIG1)
See page 52.
TIM Status and Control
Register (TSC)
See page 147.
TIM Counter Register High
(TCNTH)
See page 149.
TIM Counter Register Low
(TCNTL)
See page 149.
TIM Counter Modulo
Register High (TMODH)
See page 149.
TIM Counter Modulo
Register Low (TMODL)
See page 149.
TIM Channel 0 Status and
Control Register (TSC0)
See page 150.
TIM Channel 0
Register High (TCH0H)
See page 153.
Read:
(1)
Write:
Reset:00000
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Read:Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Read: CH0F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
COPRS LVISTOP LVIRSTD LVIPWRD LVDLVR SSREC STOP COPD
(2)
1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits.
2. LVDLVR reset to 0 by a power-on reset (POR) only.
TOIE TSTOP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
= Unimplemented R = Reserved U = Unaffected
00
000
PS2 PS1 PS0
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 25
For More Information On This Product,
Go to: www.freescale.com
nc...
I
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CH1IE
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$0027
$0028
$0029
$002A
$002B
↓
$0035
TIM Channel 0
Register Low (TCH0L)
See page 153.
TIM Channel 1 Status and
Control Register (TSC1)
See page 150.
TIM Channel 1
Register High (TCH1H)
See page 153.
TIM Channel 1
Register Low (TCH1L)
See page 153.
Unimplemented
cale Semiconductor,
Frees
Oscillator Status Register
$0036
$0037 Unimplemented Read:
Oscillator Trim Register
$0038
$0039
↓
$003F
Break Status Register
$FE00
SIM Reset Status Register
$FE01
(OSCSTAT)
See page 98.
(OSCTRIM)
See page 99.
Unimplemented
See page 161.
(SRSR)
See page 135.
Read:
Write:
Reset:00000000
Read:
Write:
Reset:10000000
Read:
Write: See note 1
(BSR)
Reset: 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
RRRRRRECGON
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
RRRRRR
1. Writing a 0 clears SBSW.
= Unimplemented R = Reserved U = Unaffected
SBSW
ECGST
R
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
Data Sheet MC68HC908QF4 — Rev. 1.0
26 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Addr.Register Name Bit 7654321Bit 0
Break Auxiliary
$FE02
$FE03
$FE04
$FE05
nc...
I
$FE06
$FE07 Reserved RRRRRRRR
Register (BRKAR)
See page 160.
Break Flag Control
Register (BFCR)
See page 161.
Interrupt Status Register 1
See page 77.
Interrupt Status Register 2
See page 77.
Interrupt Status Register 3
See page 77.
Read:0000000
Write:
Reset:00000000
Read:
Write:
Reset: 0
Read: 0 IF5 IF4 IF3 0 IF1 0 0
(INT1)
Write:RRRRRRRR
Reset:00000000
Read:IF140000000
(INT2)
Write:RRRRRRRR
Reset:00000000
Read:0000000IF15
(INT3)
Write:RRRRRRRR
Reset:00000000
Memory
Input/Output (I/O) Section
BDCOP
BCFERRRRRRR
cale Semiconductor,
Frees
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
↓
$FE0F
FLASH Control Register
(FLCR)
See page 30.
Break Address High
Register (BRKH)
See page 160.
Break Address low
Register (BRKL)
See page 160.
Break Status and Control
Register (BRKSCR)
See page 159.
LVI Status Register
(LVISR)
See page 89.
Reserved for FLASH Test RRRRRRRR
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:LVIOUT000000R
Write:
Reset:00000000
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
BRKE BRKA
= Unimplemented R = Reserved U = Unaffected
000000
HVEN MASS ERASE PGM
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 27
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Memory
Addr.Register Name Bit 7654321Bit 0
$FFB0
↓
$FFBD
Unimplemented
FLASH Block Protect
$FFBE
$FFBF Unimplemented
Internal Oscillator Trim Value
$FFC0
nc...
I
$FFC1 Reserved RRRRRRRR
$FFC2
↓
$FFCF
$FFFF
Register (FLBPR)
See page 35.
(Optional)
Unimplemented
COP Control Register
(COPCTL)
See page 57.
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
Read:
Write:
Reset:00000000
Read:
Write:
Reset:10000000
Read: LOW BYTE OF RESET VECTOR
Write: WRITING CLEARS COP COUNTER (ANY VALUE)
Reset: Unaffected by reset
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
= Unimplemented R = Reserved U = Unaffected
cale Semiconductor,
0
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
28 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 2-1 shows the MC68HC908QF4 reset and interrupt vectors.
.
Vector Priority Vector Address Vector
Lowest
Table 2-1. Vector Addresses
IF14
IF13
↓
IF6
IF5
$FFE0 Keyboard vector (high)
$FFE1 Keyboard vector (low)
— Not used
$FFF2 TIM overflow vector (high)
$FFF3 TIM overflow vector (low)
Random-Access Memory (RAM)
Memory
nc...
I
2.5 Random-Access Memory (RAM)
cale Semiconductor,
NOTE: For correct operation, the stack pointer must point only to RAM locations.
Frees
Addresses $0080–$00FF are RAM locations. The location of the stack RAM is
programmable. The 16-bit stack pointer allows the stack to be anywhere in the
64-Kbyte memory space.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of
the stack to save the contents of the CPU registers.
Highest
IF4
IF3
IF2 — Not used
IF1
—
—
$FFF4 TIM channel 1 vector (high)
$FFF5 TIM channel 1 vector (low)
$FFF6 TIM channel 0 vector (high)
$FFF7 TIM channel 0 vector (low)
$FFF A IRQ
$FFFB IRQ
$FFFC SWI vector (high)
$FFFD SWI vector (low)
$FFFE Reset vector (high)
$FFFF Reset vector (low)
vector (high)
vector (low)
NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return
address. The stack pointer decrements during pushes and increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the
RAM during a subroutine or during the interrupt stacking operation.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 29
For More Information On This Product,
Go to: www.freescale.com
Memory
2.6 FLASH Memory (FLASH)
nc...
I
Freescale Semiconductor, Inc.
This subsection describes the operation of the embedded FLASH memory. The
FLASH memory can be read, programmed, and erased from a single external
supply. The program and erase operations are enabled through the use of an
internal charge pump.
The FLASH memory consists of an array of 4096 bytes with an additional 48 bytes
for user vectors. The minimum size of FLASH memory that can be erased is 64
bytes; and the maximum size of FLASH memory that can be programmed in a
program cycle is 32 bytes (a row). Program and erase operations are facilitated
through control bits in the FLASH control register (FLCR). Details for these
operations appear later in this section. The address ranges for the user memory
and vectors are:
• $EE00 – $FDFF; user memory, 4096 bytes
• $FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE: An erased bit reads as 1 and a programmed bit reads as 0. A security feature
2.6.1 FLASH Control Register
cale Semiconductor,
Frees
prevents viewing of the FLASH contents.
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address: $FE08
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory
for either program or erase operation. It can only be set if either PGM =1 or
ERASE =1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
(1)
HVEN MASS ERASE PGM
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908QF4 — Rev. 1.0
30 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
ERASE — Erase Control Bit
PGM — Program Control Bit
2.6.2 FLASH Page Erase Operation
nc...
I
cale Semiconductor,
NOTE: Programming and erasing of FLASH locations cannot be performed by code being
Frees
Use the following procedure to erase a page of FLASH memory. A page consists
of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0.
The 48-byte user interrupt vectors area also forms a page. Any FLASH memory
page can be erased alone.
10. After time, t
executed from the FLASH memory. While these operations must be performed in
the order as shown, but other unrelated operations may occur between the steps.
Freescale Semiconductor, Inc.
This read/write bit configures the memory for erase operation. ERASE is
interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1
at the same time.
1 = Erase operation selected
0 = Erase operation unselected
This read/write bit configures the memory for program operation. PGM is
interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to
1 at the same time.
1 = Program operation selected
0 = Program operation unselected
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block
to be erased.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE bit.
8. Wait for a time, t
9. Clear the HVEN bit.
again.
FLASH Memory (FLASH)
(minimum 10 µs).
NVS
(minimum 1 ms or 4 ms).
Erase
(minimum 5 µs).
NVH
(typical 1 µs), the memory can be accessed in read mode
RCV
Memory
In applications that need up to 10,000 program/erase cycles, use the 4 ms page
erase specification to get improved long-term reliability. Any application can use
this 4 ms page erase specification. However, in applications where a FLASH
location will be erased and reprogrammed less than 1000 times, and speed is
important, use the 1 ms page erase specification to get a lower minimum erase
time.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 31
For More Information On This Product,
Go to: www.freescale.com
Memory
2.6.3 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as 1:
NOTE: Mass erase is disabled whenever any block is protected (FLBPR does not equal
$FF).
nc...
I
10. After time, t
Freescale Semiconductor, Inc.
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address
range.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE and MASS bits.
8. Wait for a time, t
9. Clear the HVEN bit.
again.
(1)
within the FLASH memory address
(minimum 10 µs).
NVS
(minimum 4 ms).
Erase
(minimum 100 µs).
NVH1
(typical 1 µs), the memory can be accessed in read mode
RCV
NOTE: Programming and erasing of FLASH locations cannot be performed by code being
2.6.4 FLASH Program Operation
cale Semiconductor,
NOTE: Only bytes which are currently $FF may be programmed.
Frees
executed from the FLASH memory. While these operations must be performed in
the order as shown, but other unrelated operations may occur between the steps.
Programming of the FLASH memory is done on a row basis. A row consists of 32
consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80,
$XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a
row of FLASH memory
Figure 2-4 shows a flowchart of the programming algorithm.
1. Set the PGM bit. This configures the memory for program operation and
enables the latching of address and data for programming.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH location within the address range desired.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
(minimum 10 µs).
NVS
(minimum 5 µs).
PGS
1. When in monitor mode, with security sequence failed (see 16.3.2 Security), write to the FLASH
block protect register instead of any FLASH address.
Data Sheet MC68HC908QF4 — Rev. 1.0
32 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Memory
FLASH Memory (FLASH)
NOTE: The COP register at location $FFFF should not be written between steps 5-12,
nc...
I
NOTE: Programming and erasing of FLASH locations cannot be performed by code being
2.6.5 FLASH Protection
cale Semiconductor,
NOTE: In performing a program or erase operation, the FLASH block protect register must
Frees
7. Write data to the FLASH address being programmed
8. Wait for time, t
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit
11. Wait for time, t
12. Clear the HVEN bit.
13. After time, t
again.
when the HVEN bit is set. Since this register is located at a valid FLASH address,
unpredictable behavior may occur if this location is written while HVEN is set.
This program sequence is repeated throughout the memory until all data is
programmed.
executed from the FLASH memory. While these operations must be performed in
the order shown, other unrelated operations may occur between the steps. Do not
exceed t
Due to the ability of the on-board charge pump to erase and program the FLASH
memory in the target application, provision is made to protect blocks of memory
from unintentional erase or program operations due to system malfunction. This
protection is done by use of a FLASH block protect register (FLBPR). The FLBPR
determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends to the
bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
be read after setting the PGM or ERASE bit and before asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from
being programmed and erased. When all the bits are erased (all 1’s), the entire
memory is accessible for program and erase.
PROG
RCV
maximum, see 17.12 Memory Characteristics.
(minimum 30 µs).
PROG
(1)
.
(minimum 5 µs).
NVH
(typical 1 µs), the memory can be accessed in read mode
(1)
.
1. The time between each FLASH address change, or the time between the last FLASH address
programmed to clearing PGM bit, must not exceed the maximum programming time, t
maximum.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 33
For More Information On This Product,
Go to: www.freescale.com
PROG
Memory
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
Algorithm for Programming
a Row (32 Bytes) of FLASH Memory
1
2
READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
5
6
7
WRITE DATA TO THE FLASH ADDRESS
8
9
SET PGM BIT
WAIT FOR A TIME, t
SET HVEN BIT
WAIT FOR A TIME, t
TO BE PROGRAMMED
WAIT FOR A TIME, t
COMPLETED
PROGRAMMING
THIS ROW?
N
nvs
pgs
PROG
Y
10
11
CLEAR PGM BIT
WAIT FOR A TIME, t
nvh
Notes:
The time between each FLASH address change (step 6 to step 9), or the
time between the last FLASH address programmed to clearing PGM bit
(step 6 to step 9) must not exceed the maximum programming time, t
maximum. This row program algorithm assumes the row/s to be
programmed are initially erased.
PROG
12
13
,
CLEAR HVEN BIT
WAIT FOR A TIME, t
END OF PROGRAMMING
rcv
Figure 2-4. FLASH Programming Flowchart
Data Sheet MC68HC908QF4 — Rev. 1.0
34 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
When bits within the FLBPR are programmed, they lock a block of memory. The
address ranges are shown in 2.6.6 FLASH Block Protect Register. Once the
FLBPR is programmed with a value other than $FF, any erase or program of the
FLBPR or the protected block of FLASH memory is prohibited. Mass erase is
disabled whenever any block is protected (FLBPR does not equal $FF). The
FLBPR itself can be erased or programmed only with an external voltage, V
present on the IRQ
mode.
2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH
memory, and therefore can only be written during a programming sequence of the
FLASH memory. The value in this register determines the starting address of the
nc...
I
protected range within the FLASH memory.
Freescale Semiconductor, Inc.
Address: $FFBE
pin. This voltage also allows entry from reset into the monitor
Memory
FLASH Memory (FLASH)
,
TST
cale Semiconductor,
Frees
Bit 7654321Bit 0
Read:
Write:
Reset:UUUUUUUU
U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
BPR[7:0] — FLASH Protection Register Bits [7:0]
These eight bits in FLBPR represent bits [13:6] of a 16-bit memory a ddress. Bits
[15:14] are 1s and bits [5:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the
FLASH memory for block protection. The FLASH is protected from this start
address to the end of FLASH memory, at $FFFF. With this mechanism, the
protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH
memory. See Figure 2-6 and Table 2-2.
START ADDRESS OF
FLASH BLOCK PROTECT
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-5. FLASH Block Protect Register (FLBPR)
16-BIT MEMORY ADDRESS
11
FLBPR VALUE
0
0
000
0
Figure 2-6. FLASH Block Protect Start Address
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Memory 35
For More Information On This Product,
Go to: www.freescale.com
nc...
I
Memory
Freescale Semiconductor, Inc.
BPR[7:0] Start of Address of Protect Range
$00–$B8 The entire FLASH memory is protected.
$B9 (1011 1001)$EE40 (1110 1110 0100 0000)
$BA (1011 1010)$EE80 (1110 1110 1000 0000)
$BB (1011 1011) $EEC0 (1110 1110 1100 0000)
$BC (1011 1100)$EF00 (1110 1111 0000 0000)
$DE (1101 1110) $F780 (1111 0111 1000 0000)
$DF (1101 1111)$F7C0 (1111 0111 1100 0000)
$FE (1111 1110)
Table 2-2. Examples of Protect Start Address
and so on...
$FF80 (1111 1111 1000 0000)
FLBPR, OSCTRIM, and vectors are protected
$FF The entire FLASH memory is not protecte d.
2.6.7 Wait Mode
2.6.8 Stop Mode
cale Semiconductor,
Frees
Putting the MCU into wait mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly, but there will not be any memory
activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase
operation on the FLASH, or the operation will discontinue and the FLASH will be
on standby mode.
Putting the MCU into stop mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly, but there will not be any memory
activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase
operation on the FLASH, or the operation will discontinue and the FLASH will be
on standby mode
NOTE: Standby mode is the power-saving mode of the FLASH module in which all internal
control signals to the FLASH are inactive and the current consumption of the
FLASH is at a minimum.
Data Sheet MC68HC908QF4 — Rev. 1.0
36 Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
3.1 Introduction
3.2 Features
nc...
I
Freescale Semiconductor, Inc.
Section 3. Analog-to-Digital Converter (ADC)
This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit,
4-channel analog-to-digital converter.
Features of the ADC module include:
• 4 channels with multiplexed input
• Linear successive approximation with monotonicity
cale Semiconductor,
Frees
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock frequency
Figure 3-1 provides a summary of the input/output (I/O) registers.
Addr.Register Name Bit 7654321Bit 0
ADC Status and Control
$003C
$003D Unimplemented
$003E
$003F
Register (ADSCR)
See page 42.
ADC Data Register
(ADR)
See page 43.
ADC Input Clock Register
(ADICLK)
See page 44.
Read: COCO
Write:
Reset:00011111
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset:00000000
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
ADIV2 ADIV1 ADIV0
AIEN ADCO CH4 CH3 CH2 CH1 CH0
00000
= Unimplemented
Figure 3-1. ADC I/O Register Summary
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 37
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
nc...
I
cale Semiconductor,
Frees
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA
PTB
V
MODE
PLLEN
DATA
BS
OP1
GND
REXT
XTAL1
XTAL0
UPCLK
PFD
DDRA
M68HC08 CPU
DDRB
MC68HC908QF4
4096 BYTES
USER FLASH
CC
PTA3/RST
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
TRANSMITTER
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
/KBI3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
8-BIT ADC
128 BYTES RAM
UHF
Figure 3-2. Block Diagram Highlighting ADC Block and Pins
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
SINGLE INTERRUPT
MODULE
BREAK
MODULE
POWER-ON RESET
MODULE
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
MONITOR ROM
POWER SUPPLY
V
DD
V
SS
Data Sheet MC68HC908QF4 — Rev. 1.0
38 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
3.3 Functional Description
INTERNAL
DATA BUS
READ DDRA
nc...
I
WRITE DDRA
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Functional Description
Four ADC channels are available for sampling external sources at pins PTA0,
PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to
select one of the four ADC channels as an ADC voltage input (ADCVIN). ADCVIN
is converted by the successive approximation register-based counters. The ADC
resolution is eight bits. When the conversion is completed, ADC puts the result in
the ADC data register and sets a flag or generates an interrupt.
Figure 3-3 shows a block diagram of the ADC.
DISABLE
RESET
DDRAx
cale Semiconductor,
Frees
WRITE PTA
READ PTA
INTERRUPT
LOGIC
AIEN COCO
BUS CLOCK
CONVERSION
COMPLETE
ADC DATA REGISTER
ADC
ADC CLOCK
CLOCK
GENERATOR
PTAx
ADC VOLTAGE IN
ADCVIN
DISABLE
ADC CHANNEL x
CHANNEL
SELECT
(1 OF 4 CHANNELS)
ADCx
CH[4:0]
ADIV[2:0]
Figure 3-3. ADC Block Diagram
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 39
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.3.1 ADC Port I/O Pins
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with
the ADC channels. The channel select bits (ADC status and control register
(ADSCR), $003C), define which ADC channel/port pin will be used as the input
signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O logic and can
be used as general-purpose I/O. Writes to the port register or data direction register
(DDR) will not have any affect on the port pin that is selected by the ADC. Read of
a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is
at 0. If the DDR bit is 1, the value in the port data latch is read.
3.3.2 Voltage Conversion
nc...
I
NOTE: Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time
cale Semiconductor,
3.3.4 Continuous Conversion
Frees
When the input voltage to the ADC equals V
(full scale). If the input voltage equals V
voltages between V
voltages will result in $FF if greater than V
Sixteen ADC internal clocks are required to perform one conversion. The ADC
starts a conversion on the first rising edge of the ADC internal clock immediately
following a write to the ADSCR. If the ADC internal clock is selected to run at
1 MHz, then one conversion will take 16 µs to complete. With a 1-MHz ADC
internal clock the maximum sample rate is 62.5 kHz.
Conversion Time =
Number of Bus Cycles = Conversion Time × Bus Frequency
In the continuous conversion mode (ADCO = 1), the ADC continuously converts
the selected channel filling the ADC data register (ADR) with new data after each
conversion. Data from the previous conversion will be overwritten whether that
data has been read or not. Conversions will continue until the ADCO bit is cleared.
The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until
the next read of the ADC data register.
DD
and V
are a straight-line linear conversion. All other input
SS
16 ADC Clock Cycles
ADC Clock Frequency
SS,
, the ADC converts the signal to $FF
DD
the ADC converts it to $00. Input
and $00 if less than VSS.
DD
When a conversion is in process and the ADSCR is written, the current conversion
data should be discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
Data Sheet MC68HC908QF4 — Rev. 1.0
40 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
3.4 Interrupts
3.5 Low-Power Modes
3.5.1 Wait Mode
nc...
I
Freescale Semiconductor, Inc.
When the AIEN bit is set, the ADC module is capable of generating a central
processor unit (CPU) interrupt after each ADC conversion. A CPU interrupt is
generated if the COCO bit is at 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
The following subsections describe the ADC in low-power modes.
The ADC continues normal operation during wait mode. Any enabled CPU interrupt
request from the ADC can bring the microcontroller unit (MCU) out of wait mode. If
the ADC is not required to bring the MCU out of wait mode, power down the ADC
by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT instruction.
Analog-to-Digital Converter (ADC)
Interrupts
3.5.2 Stop Mode
3.6 Input/Output Signals
cale Semiconductor,
3.7 Input/Output Registers
Frees
The ADC module is inactive after the execution of a STOP instruction. Any pending
conversion is aborted. ADC conversions resume when the MCU exits stop mode.
Allow one conversion cycle to stabilize the analog circuitry before using ADC data
after exiting stop mode.
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC
channels to the ADC module.
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 41
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control
register (ADSCR). When a conversion is in process and the ADSCR is written, the
current conversion data should be discarded to prevent an incorrect reading.
Address: $003C
Bit 7654321Bit 0
nc...
I
cale Semiconductor,
Frees
Read: COCO
AIEN ADCO CH4 CH3 CH2 CH1 CH0
Write:
Reset:00011111
= Unimplemented
Figure 3-4. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end
of each conversion. COCO will stay set until cleared by a read of the ADC data
register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end
of a conversion. It always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled
(AIEN = 1)
NOTE: The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion.
The interrupt signal is cleared when ADR is read or ADSCR is written. Reset
clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update ADR at the
end of each conversion. Only one conversion is allo wed when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of
the four ADC channels. The five select bits are detailed in Table 3-1. Care
Data Sheet MC68HC908QF4 — Rev. 1.0
42 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Input/Output Registers
should be taken when using a port pin as both an analog and a digital input
simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1.
This feature allows for reduced power consumption for the MCU when the ADC
is not used. Reset sets all of these bits to a 1.
NOTE: Recovery from the disabled state requires one conversion cycle to stabilize.
Table 3-1. MUX Channel Select
nc...
I
cale Semiconductor,
3.7.2 ADC Data Register
Frees
CH4 CH3 CH2 CH1 CH0
00000 AD0 PTA0
00001 AD1 PTA1
00010 AD2 PTA4
00011 AD3 PTA5
00100 —
↓↓↓↓↓ —
11010 —
11011 — Reserved
11
11
11
111 1 1—ADC power off
1. If any unused channels are selected, the resulting ADC conversi on will be
unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the
table, are used to verify the operation of the ADC converter both in production test and for user applications.
1 0 0 — Unused
1 0 1—
1 1 0—
ADC
Channel
Input Select
V
V
DDA
SSA
(1)
(2)
(2)
Unused
One 8-bit result register is provided. This register is updated each time an ADC
conversion completes.
Address: $003E
Bit 7654321Bit 0
Read:
Write:
Reset: Indeterminate after reset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 3-5. ADC Data Register (ADR)
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Analog-to-Digital Converter (ADC) 43
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003F
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
nc...
I
ADIV2–ADIV0 — ADC Clock Prescaler Bits
cale Semiconductor,
ADIV2 ADIV1 ADIV0
= Unimplemented
Figure 3-6. ADC Input Clock Register (ADICLK)
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used
by the ADC to generate the internal ADC clock. Table 3-2 shows the available
clock configurations. The ADC clock should be set according to the MCU
operating voltage. Lower operating voltages will require lower ADC clock
frequencies for best accuracy. The analog input level should remain stable for
the entire conversion time (maximum = 17 ADC clock cycles).
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 Bus clock ÷ 1
0 0 1 Bus clock ÷ 2
0 1 0 Bus clock ÷ 4
0 1 1 Bus clock ÷ 8
1 X X Bus clock ÷ 16
X = don’t care
00000
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
44 Analog-to-Digital Converter (ADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908QF4
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a
periodic interrupt during stop mode to wake the part up without requiring an
external signal. Figure 4-2 is a block diagram of the AWU.
4.2 Features
Section 4. Auto Wakeup Module (AWU)
nc...
I
cale Semiconductor,
Frees
Features of the auto wakeup module include:
• One internal interrupt with separate interrupt enable bit, sharing the same
keyboard interrupt vector and keyboard interrupt mask bit
• Exit from low-power stop mode without external signals
• Selectable timeout periods
• Dedicated low power internal oscillator separate from the main system clock
sources
Figure 4-1 provides a summary of the input/output (I/O) registers used in
conjuction with the AWU.
Addr.Register Name Bit 7654321Bit 0
$0000
$001A
$001B
Port A Data Register
(PTA)
See page 48.
Keyboard Status
and Control Register
(KBSCR)
See page 48.
Keyboard Interrupt Enable
Register (KBIER)
See page 49.
Read: 0 AWUL
PTA5 PTA4 PTA3
Write:
Reset: Unaffected by reset
Read:0000KEYF0
Write:
Reset:00000000
Read: 0
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
= Unimplemented
PTA2
PTA1 PTA0
IMASKK MODEK
ACKK
Figure 4-1. AWU Register Summary
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Auto Wakeup Module (AWU) 45
For More Information On This Product,
Go to: www.freescale.com
Auto Wakeup Module (AWU)
4.3 Functional Description
nc...
I
Freescale Semiconductor, Inc.
The function of the auto wakeup logic is to generate periodic wakeup requests to
bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are
treated as regular keyboard interrupt requests, with the differe nce that instead of a
pin, the interrupt signal is generated by an internal logic.
Writing the AWUIE bit in the keyboard interrupt enable register enables or disables
the auto wakeup interrupt input (see Figure 4-2). A logic 1 applied to the
AWUIREQ input with auto wakeup interrupt request enabled, latches an auto
wakeup interrupt request.
Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data
register (PTA). This is a read-only bit which is occupying an empty bit position on
PTA. No PTA associated registers, such as PTA6 data direction or PTA6 pullup
exist for this bit.
Entering stop mode will enable the auto wakeup generation logic. An internal RC
oscillator (exclusive for the auto wakeup feature) drives the wakeup request
generator. Once the overflow count is reached in the generator counter, a wakeup
request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1.
cale Semiconductor,
Frees
(CGMXCLK)
BUSCLKX4
Wakeup interrupt requests will only be serviced if the associated interrupt enable
bit, AWUIE, in KBIER is set. The AWU shares the keyboard interrupt vector.
COPRS (FROM CONFIG1)
INT RC OSC
EN 32 kHz
CLRLOGIC
CLEAR
CLK
RST
RESET
AUTOWUGE N
SHORT
OVERFLOW
CLK
RST
ISTOP
1 = DIV 2
0 = DIV 2
9
14
RESET
ACKK
V
DD
D
Q
E
R
TO PTA READ, BIT 6
TO KBI INTERRUPT LOGIC (SEE
Figure 9-3. Keyboard Interrupt
Block Diagram)
AWUL
AWUIREQ
RESET
AWUIE
Figure 4-2. Auto Wakeup Interrupt Request Generation Logic
Data Sheet MC68HC908QF4 — Rev. 1.0
46 Auto Wakeup Module (AWU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
The overflow count can be selected from two options d efined by the COPRS bit in
CONFIG1. This bit was “borrowed” from the computer operating properly (COP)
using the fact that the COP feature is idle (no MCU clock available) in stop mode.
The typical values of the periodic wakeup request are (at room temperature):
• COPRS = 0: 875 ms @ 3.0 V, 1.1 s @ 2.3 V
• COPRS = 1: 22 ms @ 3.0 V, 27 ms @ 2.3 V
The auto wakeup RC oscillator is highly dependent on operating voltage and
temperature. This feature is not recommended for use as a time-keeping function.
The wakeup request is latched to allow the interrupt source identification. The
latched value, AWUL, can be read directly from the bit 6 position of PTA data
register. This is a read-only bit which is occupying an empty bit position on PTA.
No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6 pullup
nc...
I
exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR
register. Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see
Figure 4-2) has no effect on AWUL reading.
Auto Wakeup Module (AWU)
Wait Mode
4.4 Wait Mode
4.5 Stop Mode
cale Semiconductor,
4.6 Input/Output Registers
Frees
The AWU oscillator and counters are inactive in normal operating mode and
become active only upon entering stop mode.
The AWU module remains inactive in wait mode.
When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable
register) it is activated automatically upon entering stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard interrupt
requests to bring the MCU out of stop mode. The AWU counters start from ‘0’ each
time stop mode is entered.
The AWU shares registers with the keyboard interrupt (KBI) module and the port A
I/O module. The following I/O registers control and monitor operation of the AWU:
• Port A data register (PTA)
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Auto Wakeup Module (AWU) 47
For More Information On This Product,
Go to: www.freescale.com
Auto Wakeup Module (AWU)
4.6.1 Port A I/O Register
nc...
I
Freescale Semiconductor, Inc.
The port A data register (PTA) contains a data latch for the state of the AWU
interrupt request, in addition to the data latches for port A.
Address: $0000
Read: 0 AWUL
Write:
Reset: 0 0 Unaffected by reset
AWUL — Auto Wakeup Latch
This is a read-only bit which has the value of the auto wakeup interrupt request
latch. The wakeup request signal is generated internally. There is no PTA6 port
or any of the associated bits such as PTA6 data direction or pullup bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
Bit 7654321Bit 0
PTA5 PTA4 PTA3
= Unimplemented
Figure 4-3. Port A Data Register (PTA)
PTA2
PTA1 PTA0
NOTE: PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see
a description of these bits, see 13.2.1 Port A Data Register.
4.6.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard/auto wakeup interrupt requests
• Acknowledges keyboard/auto wakeup interrupt requests
• Masks keyboard/auto wakeup interrupt requests
Address:
$001A
cale Semiconductor,
Read:0000KEYF0
Write:
Frees
Reset:00000000
Figure 4-4. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto
wakeup. Reset clears the KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending
Bit 7654321Bit 0
ACKK
= Unimplemented
IMASKK MODEK
Data Sheet MC68HC908QF4 — Rev. 1.0
48 Auto Wakeup Module (AWU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt
request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears
ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt
mask from generating interrupt requests on port A or auto wakeup. Reset clears
the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE: MODEK is not used in conjuction with the auto wakeup feature. To see a
description of this bit, see 9.7.1 Keyboard Status and Control Register.
4.6.3 Keyboard Interrupt Enable Register
nc...
I
The keyboard interrupt enable register (KBIER) enables or disables the auto
wakeup to operate as a keyboard/auto wakeup interrupt input.
Auto Wakeup Module (AWU)
Input/Output Registers
cale Semiconductor,
Frees
Address:
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt
requests. Reset clears AWUIE.
NOTE: KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see
a description of these bits, see 9.7.2 Keyboard Interrupt Enable Register.
$001B
Bit 7654321Bit 0
Read: 0
Write:
Reset:00000000
Figure 4-5. Keyboard Interrupt Enable Register (KBIER)
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
= Unimplemented
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Auto Wakeup Module (AWU) 49
For More Information On This Product,
Go to: www.freescale.com
Auto Wakeup Module (AWU)
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
50 Auto Wakeup Module (AWU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908QF4
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The
configuration registers enable or disable the following options:
• Stop mode recovery time (32 × BUSCLKX4 cycles or
4096 × BUSCLKX4 cycles)
•STOP instruction
Section 5. Configuration Register (CONFIG)
nc...
I
5.2 Functional Description
cale Semiconductor,
Frees
• Computer operating properly module (COP)
• COP reset period (COPRS): (2
18–24
(2
• Low-voltage inhibit (LVI) enable and trip voltage selection
• OSC option selection
•IRQ
•RST
• Auto wakeup timeout period
The configuration registers are used in the initialization of various options. The
configuration registers can be written once after each reset. Exceptions are bits
LVDLVR and LVIRSTD which may be written at any time. Most of the configuration
register bits are cleared during reset. Since the various options a ffect the operation
of the microcontroller unit (MCU) it is recommended that this register be written
immediately after reset. The configuration registers are located at $001E and
$001F, and may be read at anytime.
Address:
Read:
Write:
Reset:000 0 0 00U
POR:0000 0 000
) × BUSCLKX4
pin
pin
$001E
Bit 7654 321Bit 0
IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN
= Reserved U = Unaffected
R
13–24
) × BUSCLKX4 or
Figure 5-1. Configuration Register 2 (CONFIG2)
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Configuration Register (CONFIG) 51
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Configuration Register (CONFIG)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option
(0, 0) Internal oscillator
(0, 1) External oscillator
(1, 0) External RC oscillator
(1, 1) External XTAL oscillator
pin and V
DD
nc...
I
cale Semiconductor,
Frees
RSTEN — RST
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE: The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave
this bit unaffected.
Address:
COPRS (Out of STOP Mode) — COP Reset Period Selection Bit
COPRS (In STOP Mode) — Auto Wakeup Period Selection Bit
$001F
Read:
Write:
Reset:0000U000
POR:
U = Unaffected
1 = COP reset short cycle = (2
0 = COP reset long cycle = (2
1 = Auto wakeup short cycle = (2
0 = Auto wakeup long cycle = (2
Pin Function Selection
Bit 7 6 5 4 3 2 1 Bit 0
COPRS LVISTOP
00000000
Figure 5-2. Configuration Register 1 (CONFIG1)
LVIRSTD
LVIPWRD LVDLVR SSREC STOP COPD
13
– 24) × BUSCLKX4
18
– 24) × BUSCLKX4
9
) × INTRCOSC
14
) × INTRCOSC
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to
operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
Data Sheet MC68HC908QF4 — Rev. 1.0
52 Configuration Register (CONFIG) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. Unlike other
configuration bits, the LVIRSTD can be written at any time.
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVDLVR — Low Voltage Detect or Low Voltage Reset Mode Bit
LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used
as a low voltage warning, while LVR will commonly be used as a re set condition.
Unlike other CONFIG bits, LVDLVR can be written multiple times after reset.
nc...
I
NOTE: The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets will leave
1 = LVI trip voltage level set to LVD trip voltage
0 = LVI trip voltage level set to LVR trip voltage
this bit unaffected.
Configuration Register (CONFIG)
Functional Description
cale Semiconductor,
Frees
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4
cycles instead of a 4096 BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.
When using the LVI during normal operation but disabling du ring stop mode, the
LVI will have an enable time of t
reset and long stop recovery (both 4096 BUSCLKX4 cycles) gives a delay
longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when
using the short stop recovery configuration option, the 32 BUSCLKX4 delay
must be greater than the LVI’s turn on time to avoid a period in startup where
the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
. The system stabilization time for power-on
EN
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Configuration Register (CONFIG) 53
For More Information On This Product,
Go to: www.freescale.com
Configuration Register (CONFIG)
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
54 Configuration Register (CONFIG) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
6.1 Introduction
nc...
6.2 Functional Description
I
Freescale Semiconductor, Inc.
Section 6. Computer Operating Properly (COP)
The computer operating properly (COP) module contains a free-running counter
that generates a reset if allowed to overflow. The COP module helps software
recover from runaway code. Prevent a COP reset by clearing the COP counter
periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.
cale Semiconductor,
Frees
BUSCLKX4
STOP INSTRUCTION
INTERNAL RESET SOURCES
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE (FROM CONFIG1)
RESET
COPCTL WRITE
COP RATE SELECT
(COPRS FROM CONFIG1)
12-BIT SIM COUNTER
CLEAR ALL STAGES
COP CLOCK
Figure 6-1. COP Block Diagram
CLEAR STAGES 5–12
COP TIMEOUT
6-BIT COP COUNTER
CLEAR
COP COUNTER
RESET CIRCUIT
RESET STATUS REGISTER
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Computer Operating Properly (COP) 55
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system
integration module (SIM) counter. If not cleared by software, the COP counter
overflows and generates an asynchronous reset after 2
BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 2
internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms. Writing any
value to location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12–5 of the SIM counter.
NOTE: Service the COP immediately after reset and before entering or after exiting stop
mode to guarantee the maximum time before the first COP counter overflow.
18–24
18–24
BUSCLKX4 cycle overflow option, the
or 213–24
nc...
I
6.3 I/O Signals
6.3.1 BUSCLKX4
6.3.2 STOP Instruction
cale Semiconductor,
6.3.3 COPCTL Write
Frees
A COP reset pulls the RST
for 32 × BUSCLKX4 cycles and sets the COP bit in the reset status register (RSR).
See 14.8.1 SIM Reset Status Register.
NOTE: Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from generating a
reset even while the main program is not working properly.
The following paragraphs describe the signals shown in Figure 6-1.
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the
crystal frequency or the RC-oscillator frequency.
The STOP instruction clears the SIM counter.
Writing any value to the COP control register (COPCTL) (see 6.4 COP Control
Register) clears the COP counter and clears stages 12–5 of the SIM counter.
Reading the COP control register returns the low byte of the reset vector.
pin low (if the RSTEN bit is set in the CONFIG1 register)
6.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter
4096 × BUSCLKX4 cycles after power up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
Data Sheet MC68HC908QF4 — Rev. 1.0
56 Computer Operating Properly (COP) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG). See Section 5. Configuration Register
(CONFIG).
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the
configuration register 1 (CONFIG1). See Section 5. Configuration Register
(CONFIG).
6.4 COP Control Register
Computer Operating Properly (COP)
COP Control Register
nc...
I
6.5 Interrupts
6.6 Monitor Mode
cale Semiconductor,
6.7 Low-Power Modes
Frees
The COP control register (COPCTL) is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and sta rts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF
Bit 7654321Bit 0
Read: LOW BYTE OF RESET VECTOR
Write: CLEAR COP COUNTER
Reset: Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
is present on the IRQ pin.
TST
6.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Computer Operating Properly (COP) 57
For More Information On This Product,
Go to: www.freescale.com
Computer Operating Properly (COP)
6.7.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter.
Service the COP immediately before entering or after exiting stop mode to ensure
a full COP timeout period after entering or exiting stop mode.
6.8 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit
is set in break auxiliary register (BRKAR).
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
58 Computer Operating Properly (COP) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
7.1 Introduction
7.2 Features
nc...
I
Freescale Semiconductor, Inc.
Section 7. Central Processor Unit (CPU)
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08 Reference
Manual (Motorola document order number CPU08RM/AD) contains a description
of the CPU instruction set, addressing modes, and architecture.
Features of the CPU include:
cale Semiconductor,
Frees
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension
of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 59
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory
map.
nc...
I
7.3.1 Accumulator
cale Semiconductor,
7
15
H X
15
15
70
V11HINZC
Figure 7-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
60 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Figure 7-2. Accumulator (A)
7.3.2 Index Register
Freescale Semiconductor, Inc.
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space.
H is the upper byte of the index register, and X is the lower byte. H:X is the
concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register
to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Central Processor Unit (CPU)
CPU Registers
nc...
I
7.3.3 Stack Pointer
cale Semiconductor,
Frees
Bit
151413121110987654321
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 7-3. Index Register (H:X)
The stack pointer is a 16-bit register that contains the address of the next locatio n
on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack
pointer (RSP) instruction sets the least significant byte to $FF and does not affect
the most significant byte. The stack pointer decrements as data is pushed onto the
stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack
pointer can function as an index register to access data on the stack. The CPU
uses the contents of the stack pointer to determine the conditional address of the
operand.
Bit
151413121110987654321
Read:
Write:
Reset:0000000011111111
Bit
0
Bit
0
Figure 7-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF)
frees direct address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 61
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next
instruction or operand to be fetched.
Normally, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
During reset, the program counter is loaded with the reset vector address located
at $FFFE and $FFFF. The vector address is the address of the first instruction to
be executed after exiting the reset state.
nc...
I
7.3.5 Condition Code Register
cale Semiconductor,
Frees
Bit
151413121110987654321
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Figure 7-5. Program Counter (PC)
The 8-bit condition code register contains the interrupt mask and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set
permanently to 1. The following paragraphs describe the functions o f the condition
code register.
Bit 7654321Bit 0
Read:
V11H I NZC
Write:
Reset:X11X1XXX
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
Bit
0
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The
signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
Data Sheet MC68HC908QF4 — Rev. 1.0
62 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits
3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation.
The half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags to
determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU
interrupts are enabled when the interrupt mask is cleared. When a CPU
interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the
interrupt vector is fetched.
nc...
I
1 = Interrupts disabled
0 = Interrupts enabled
Central Processor Unit (CPU)
CPU Registers
cale Semiconductor,
Frees
NOTE: To maintain M6805 Family compatibility, the upper byte o f the index register (H) is
not stacked automatically. If the interrupt service routine modifies H, then th e user
must stack and unstack H using the PSHH and PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack
and restores the interrupt mask from the stack. After any reset, the interrupt
mask is set and can be cleared only by the clear interrupt mask software
instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation,
or data manipulation produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or
data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a
carry out of bit 7 of the accumulator or when a subtraction operation requires a
borrow. Some instructions — such as bit test and branch, shift, and rotate —
also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 63
For More Information On This Product,
Go to: www.freescale.com
Central Processor Unit (CPU)
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction
set.
Refer to the CPU08 Reference Manual (Motorola document order number
CPU08RM/AD) for a description of the instructions and addressing modes and
more detail about the architecture of the CPU.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
7.5.1 Wait Mode
nc...
I
The WAIT instruction:
Freescale Semiconductor, Inc.
7.5.2 Stop Mode
The STOP instruction:
After exiting stop mode, the CPU clock begins running after the oscillator
cale Semiconductor,
stabilization delay.
7.6 CPU During Break Interrupts
Frees
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Clears the interrupt mask (I bit) in the condition code register, enabling
interrupts. After exit from wait mode by interrupt, the I bit remains clear. After
exit by reset, the I bit is set.
• Disables the CPU clock
• Clears the interrupt mask (I bit) in the condition code register, enabling
external interrupts. After exit from stop mode by external interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in
monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If
the break address register match occurs on the last cycle of a CPU instruction, the
break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break
interrupt and returns the MCU to normal operation if the break interrupt has been
deasserted.
Data Sheet MC68HC908QF4 — Rev. 1.0
64 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 7)
Central Processor Unit (CPU)
Instruction Set Summary
nc...
I
cale Semiconductor,
Frees
Source
Form
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AIS #opr Add Immediate V alue (Signed) to SP
AIX #opr Add Immediate Value (Signed) to H:X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
Add with Carry A ← (A) + (M) + (C) –
Add without Carry A ← (A) + (M) –
Logical AND A ← (A) & (M) 0 – – –
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right ––
Operation Description
SP ← (SP) + (16
H:X ← (H:X) + (16
C
b7
b7
« M)
« M)
0
b0
C
b0
on CCR
VHI NZC
––––––IMM A7 ii 2
––––––IMM AF ii 2
––
Address
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Mode
A9
B9
C9
D9
E9
F9
9EE9
9ED9
AB
BB
CB
DB
EB
FB
9EEB
9EDB
A4
B4
C4
D4
E4
F4
9EE4
9ED4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
11
13
15
17
19
1B
1D
1F
Opcode
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd
dd
dd
dd
dd
dd
dd
dd
Operand
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
4
4
4
4
4
4
4
4
Effect
Cycles
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 65
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 2 of 7)
nc...
I
cale Semiconductor,
Frees
Source
Form
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3
BHS rel
BIH rel Branch if IRQ
BIL rel Branch if IRQ
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
BLE opr
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands)
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Branch if Higher or Same
(Same as BCC)
Bit Test (A) & (M) 0 – – –
Branch if Less Than or Equal To
(Signed Operands)
Operation Description
PC ← (PC) + 2 + rel ? (N
PC ← (PC) + 2 + rel ? (Z) | (N
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
PC ← (PC) + 2 + rel ? (Z) | (N
PC ← (PC) + 2 + rel ? (N
⊕ V) = 0
⊕ V) = 0
⊕ V) = 1
⊕ V) =1
on CCR
VHI NZC
––––––REL 90 rr 3
––––––REL 92 rr 3
––––––REL 93 rr 3
––––––REL 91 rr 3
Address
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Mode
A5
B5
C5
D5
E5
F5
9EE5
9ED5
01
03
05
07
09
0B
0D
0F
Opcode
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
Operand
2
3
4
4
3
2
4
5
5
5
5
5
5
5
5
5
Effect
Cycles
Data Sheet MC68HC908QF4 — Rev. 1.0
66 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 7-1. Instruction Set Summary (Sheet 3 of 7)
Central Processor Unit (CPU)
Instruction Set Summary
nc...
I
cale Semiconductor,
Frees
Source
Form
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 –––––
BSET n,opr Set Bit n in M Mn ← 1 ––––––
BSR rel Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPHX #opr
CPHX opr
Compare and Branch if Equal
Clear
Compare A with M (A) – (M) ––
Complement (One’s Complement)
Compare H:X with M (H:X) – (M:M + 1) ––
Operation Description
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
M ← (M
) = $FF – (M)
A ← (A) = $FF – (M)
) = $FF – (M)
X ← (X
M ← (M
) = $FF – (M)
M ← (M) = $FF – (M)
) = $FF – (M)
M ← (M
on CCR
VHI NZC
––––––REL AD rr 4
––––––
0––01–
0––1
Address
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
Mode
Opcode
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
31
41
51
61
71
9E61
3F
4F
5F
8C
6F
7F
9E6F
A1
B1
C1
D1
E1
F1
9EE1
9ED1
33
43
53
63
73
9E63
6575ii ii+1dd3
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
Operand
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
5
4
4
5
4
6
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
Effect
Cycles
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 67
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 4 of 7)
nc...
I
cale Semiconductor,
Frees
Source
Form
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA Decimal Adjust A
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
DIV Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Compare X with M (X) – (M) ––
Decrement and Branch if Not Zero
Decrement
Exclusive OR M with A
Increment
Jump PC ← Jump Address ––––––
Jump to Subroutine
Load A from M A ← (M) 0–––
Operation Description
(A)
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
A ← (A
⊕ M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Effect
on CCR
VHI NZC
U––INH 72 2
––––––
–––
––––INH 52 7
0–––
–––
––––––
Address
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Mode
A3
B3
C3
D3
E3
F3
9EE3
9ED3
3B
4B
5B
6B
7B
9E6B
3A
4A
5A
6A
7A
9E6A
A8
B8
C8
D8
E8
F8
9EE8
9ED8
3C
4C
5C
6C
7C
9E6C
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
9EE6
9ED6
Opcode
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd rr
rr
rr
ff rr
rr
ff rr
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
Operand
Cycles
2
3
4
4
3
2
4
5
5
3
3
5
4
6
4
1
1
4
3
5
2
3
4
4
3
2
4
5
4
1
1
4
3
5
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
Data Sheet MC68HC908QF4 — Rev. 1.0
68 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 7-1. Instruction Set Summary (Sheet 5 of 7)
Central Processor Unit (CPU)
Instruction Set Summary
nc...
I
cale Semiconductor,
Frees
Source
Form
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP No Operation None ––––––INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2
Load H:X from M H:X ← (M:M + 1) 0–––
Load X from M X ← (M) 0–––
Logical Shift Left
(Same as ASL)
Logical Shift Right ––0
Move
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – –
Operation Description
C
b7
b7
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
b0
← (M)
0
b0
C0
Source
on CCR
VHI NZC
––
0–––
––
Address
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Mode
Opcode
4555ii jjdd3
AE
BE
CE
DE
EE
FE
9EEE
9EDE
38
48
58
68
78
9E68
34
44
54
64
74
9E64
4E
5E
6E
7E
30
40
50
60
70
9E60
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
Operand
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
5
4
4
4
4
1
1
4
3
5
2
3
4
4
3
2
4
5
Effect
Cycles
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 69
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 6 of 7)
nc...
I
cale Semiconductor,
Frees
Source
Form
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
RTS Return from Subroutine
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – – DIR 35 dd 4
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Rotate Left through Carry ––
Rotate Right through Carry ––
Subtract with Carry A ← (A) – (M) – (C) ––
Store A in M M ← (A) 0–––
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
Store X in M M ← (X) 0–––
Subtract A ← (A) – (M) ––
Operation Description
C
b7
b7
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
I ← 0; Stop Processing ––0–––INH 8E 1
b0
b0
C
on CCR
VHI NZC
INH 80 7
––––––INH 81 4
Address
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Mode
39
49
59
69
79
9E69
36
46
56
66
76
9E66
A2
B2
C2
D2
E2
F2
9EE2
9ED2
B7
C7
D7
E7
F7
9EE7
9ED7
BF
CF
DF
EF
FF
9EEF
9EDF
A0
B0
C0
D0
E0
F0
9EE0
9ED0
Opcode
dd
ff
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
Operand
4
1
1
4
3
5
4
1
1
4
3
5
2
3
4
4
3
2
4
5
3
4
4
3
2
4
5
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
Effect
Cycles
Data Sheet MC68HC908QF4 — Rev. 1.0
70 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 7-1. Instruction Set Summary (Sheet 7 of 7)
Central Processor Unit (CPU)
Opcode Map
nc...
I
cale Semiconductor,
Frees
Source
Form
SWI Software Interrupt
TAP Transfer A to CCR CCR ← (A) INH 84 2
TAX Transfer A to X X ← (A) ––––––INH 97 1
TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A ← (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
WAIT Enable Interrupts; Wait for Interrupt
A Accumulator n Any bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location Set or cleared
N Negative bit — Not affected
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – –
Operation Description
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
I bit ← 0; Inhibit CPU clocking
until interrupted
⊕ Logical EXCLUSIVE OR
« Sign extend
on CCR
VHI NZC
––1–––INH 83 9
––0–––INH 8F 1
Address
DIR
INH
INH
IX1
IX
SP1
Mode
3D
4D
5D
6D
7D
9E6D
Opcode
dd
ff
ff
Operand
3
1
1
3
2
4
Effect
Cycles
7.8 Opcode Map
See Table 7-2.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Central Processor Unit (CPU) 71
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
nc...
I
cale Semiconductor,
Frees
2
2
SUB
CMP
1IX
1IX
4
4
SUB
CMP
3 SP1
3 SP1
3
3
SUB
CMP
2IX1
2IX1
5
5
SUB
CMP
4 SP2
4 SP2
4
4
SUB
CMP
3IX2
3IX2
4
4
SUB
CMP
3EXT
3EXT
3
3
SUB
CMP
2DIR
2DIR
2
2
SUB
CMP
2IMM
2IMM
3
3
BLT
BGE
2REL
2REL
4
7
RTI
RTS
1INH
1INH
4
3
NEG
CBEQ
2IX+
1IX
6
5
NEG
CBEQ
4 SP1
4
1
1
4
3
4
3 SP1
NEG
2IX1
NEGX
1INH
NEGA
1INH
NEG
2DIR
BRA
2REL
BSET0
2DIR
5
CBEQ
4
CBEQX
4
CBEQA
5
CBEQ
3
BRN
4
BCLR0
3IX1+
3IMM
3IMM
3DIR
2REL
2DIR
Table 7-2. Opcode Map
2
4
3
5
4
4
3
2
3
2
3
7
5
3
4
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
BGT
DAA
NSA
DIV
MUL
BHI
BSET1
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
2REL
1INH
1INH
1INH
1INH
2REL
2DIR
2
CPX
4
CPX
3
CPX
5
CPX
4
CPX
4
CPX
3
CPX
2
CPX
3
BLE
9
SWI
3
COM
5
COM
4
COM
1
COMX
1
COMA
4
COM
3
BLS
4
BCLR1
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
2REL
1INH
1IX
3 SP1
2IX1
1INH
1INH
2DIR
2REL
2DIR
2
4
3
5
4
4
3
2
2
2
3
5
4
1
1
4
3
4
AND
1IX
AND
3 SP1
AND
2IX1
AND
4 SP2
AND
3IX2
AND
3EXT
AND
2DIR
AND
2IMM
TXS
1INH
TAP
1INH
LSR
1IX
LSR
3 SP1
LSR
2IX1
LSRX
1INH
LSRA
1INH
LSR
2DIR
BCC
2REL
BSET2
2DIR
2
BIT
4
BIT
3
BIT
5
BIT
4
BIT
4
BIT
3
BIT
2
BIT
2
TSX
1
TPA
4
CPHX
3
CPHX
4
LDHX
3
LDHX
4
STHX
3
BCS
4
BCLR2
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
2DIR
3IMM
2DIR
3IMM
2DIR
2REL
2DIR
2
4
3
5
4
4
3
2
2
3
5
4
1
1
4
3
4
LDA
1IX
LDA
3 SP1
LDA
2IX1
LDA
4 SP2
LDA
3IX2
LDA
3EXT
LDA
2DIR
LDA
2IMM
PULA
1INH
ROR
1IX
ROR
3 SP1
ROR
2IX1
RORX
1INH
RORA
1INH
ROR
2DIR
BNE
2REL
BSET3
2DIR
2
4
3
5
4
4
3
2
1
2
3
5
4
1
1
4
3
4
STA
1IX
STA
3 SP1
STA
2IX1
STA
4 SP2
STA
3IX2
STA
3EXT
STA
2DIR
AIS
2IMM
TAX
1INH
PSHA
1INH
ASR
1IX
ASR
3 SP1
ASR
2IX1
ASRX
1INH
ASRA
1INH
ASR
2DIR
BEQ
2REL
BCLR3
2DIR
2
4
3
5
4
4
3
2
1
2
3
5
4
1
1
4
3
4
EOR
1IX
EOR
3 SP1
EOR
2IX1
EOR
4 SP2
EOR
3IX2
EOR
3EXT
EOR
2DIR
EOR
2IMM
CLC
1INH
PULX
1INH
LSL
1IX
LSL
3 SP1
LSL
2IX1
LSLX
1INH
LSLA
1INH
LSL
2DIR
BHCC
2REL
BSET4
2DIR
2
ADC
4
ADC
3
ADC
5
ADC
4
ADC
4
ADC
3
ADC
2
ADC
1
SEC
2
PSHX
3
ROL
5
ROL
4
ROL
1
ROLX
1
ROLA
4
ROL
3
BHCS
4
BCLR4
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
1IX
3 SP1
2IX1
1INH
1INH
2DIR
2REL
2DIR
2
4
3
5
4
4
3
2
2
2
3
5
4
1
1
4
3
4
ORA
1IX
ORA
3 SP1
ORA
2IX1
ORA
4 SP2
ORA
3IX2
ORA
3EXT
ORA
2DIR
ORA
2IMM
CLI
1INH
PULH
1INH
DEC
1IX
DEC
3 SP1
DEC
2IX1
DECX
1INH
DECA
1INH
DEC
2DIR
BPL
2REL
BSET5
2DIR
2
ADD
4
ADD
3
ADD
5
ADD
4
ADD
4
ADD
3
ADD
2
ADD
2
SEI
2
PSHH
4
DBNZ
6
DBNZ
5
DBNZ
3
DBNZX
3
DBNZA
5
DBNZ
3
BMI
4
BCLR5
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
2IX
4 SP1
3IX1
2INH
2INH
3DIR
2REL
2DIR
2
3
4
3
2
1
1
3
5
4
1
1
4
3
4
JMP
1IX
JMP
2IX1
JMP
3IX2
JMP
3EXT
JMP
2DIR
RSP
1INH
CLRH
1INH
INC
1IX
INC
3 SP1
INC
2IX1
INCX
1INH
INCA
1INH
INC
2DIR
BMC
2REL
BSET6
2DIR
4
5
6
5
4
4
1
2
4
3
1
1
3
3
4
JSR
1IX
JSR
2IX1
JSR
3IX2
JSR
3EXT
JSR
2DIR
BSR
2REL
NOP
1INH
TST
1IX
TST
3 SP1
TST
2IX1
TSTX
1INH
TSTA
1INH
TST
2DIR
BMS
2REL
BCLR6
2DIR
2
2
4
3
5
4
4
3
2
1
4
4
4
5
3
4
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
*
STOP
MOV
MOV
MOV
MOV
BIL
BSET7
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
2IX+D
3IMD
2DIX+
3DD
2REL
2DIR
STX
4
STX
3
STX
5
STX
4
STX
4
STX
3
STX
2
AIX
1
TXA
1
WAIT
2
CLR
4
CLR
3
CLR
1
CLRX
1
CLRA
3
CLR
3
BIH
4
BCLR7
1IX
3 SP1
2IX1
4 SP2
3IX2
3EXT
2DIR
2IMM
1INH
1INH
1IX
3 SP1
2IX1
1INH
1INH
2DIR
2REL
2DIR
MSB
0 High Byte of Opcode in Hexadecimal
LSB
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
5
BRSET0
3DIR
Low Byte of Opcode in Hexadecimal 0
5
5
5
0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
MSB
BRSET0
BRCLR0
3DIR
3DIR
1
0
LSB
BRSET1
2
3DIR
5
BRCLR1
3DIR
3
5
5
BRSET2
3DIR
4
5
BRSET3
BRCLR2
3DIR
3DIR
5
6
5
5
BRSET4
3DIR
3DIR
8
BRCLR3
7
5
5
BRSET5
3DIR
BRCLR4
3DIR
9
A
5
5
BRCLR5
3DIR
B
BRSET6
C
3DIR
5
BRCLR6
3DIR
D
5
5
BRSET7
BRCLR7
3DIR
3DIR
F
E
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
Data Sheet MC68HC908QF4 — Rev. 1.0
72 Central Processor Unit (CPU) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
8.1 Introduction
8.2 Features
nc...
I
Freescale Semiconductor, Inc.
Section 8. External Interrupt (IRQ)
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and
keyboard interrupt (KBI), provides a maskable interrupt input.
Features of the IRQ module include the following:
• External interrupt pin, IRQ
•IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Selectable internal pullup resistor
8.3 Functional Description
cale Semiconductor,
Frees
IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2)
IRQEN bit accordingly. A zero disables the IRQ function and IRQ
other shared functionalities. A one enables the IRQ function.
A falling edge on the external interrupt pin can latch a central processor unit (CPU)
interrupt request. Figure 8-2 shows the structure of the IRQ module.
Interrupt signals on the IRQ
remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
• Software clear — Software can clear the interrupt latch by writing to the
acknowledge bit in the interrupt status and control register (INTSCR).
Writing a 1 to the ACK bit clears the IRQ latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered out of reset and is
software-configurable to be either falling-edge or falling-edge and low-level
triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ
pin.
pin are latched into the IRQ latch. An interrupt latch
will assume the
When the interrupt pin is edge-triggered only (MODE = 0), the CPU interrupt
request remains set until a vector fetch, software clear, or reset occurs.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA External Interrupt (IRQ) 73
For More Information On This Product,
Go to: www.freescale.com
External Interrupt (IRQ)
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
/KBI2/TCLK
PTA3/RST
TRANSMITTER
/KBI3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
UHF
PTA
PTB
8-BIT ADC
128 BYTES RAM
V
MODE
PLLEN
DATA
BS
OP1
GND
REXT
XTAL1
XTAL0
UPCLK
PFD
DDRA
M68HC08 CPU
DDRB
MC68HC908QF4
4096 BYTES
USER FLASH
CC
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
SINGLE INTERRUPT
MODULE
BREAK
MODULE
POWER-ON RESET
MODULE
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
MONITOR ROM
POWER SUPPLY
V
DD
V
SS
Data Sheet MC68HC908QF4 — Rev. 1.0
74 External Interrupt (IRQ) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
ACK
RESET
VECTOR
FETCH
DECODER
V
DD
IRQPUD
INTERNAL ADDRESS BUS
IRQ
nc...
I
INTERNAL
PULLUP
DEVICE
V
DD
MODE
CLR
DQ
CK
IRQ
FF
IMASK
SYNCHRO-
NIZER
HIGH
VOLTAGE
DETECT
External Interrupt (IRQ)
Functional Description
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
cale Semiconductor,
Frees
Figure 8-2. IRQ Module Block Diagram
When the interrupt pin is both falling-edge and low-level triggered (MODE = 1), the
CPU interrupt request remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending. A reset
will clear the latch and the MODE control bit, thereby clearing the interrupt even if
the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A
latched interrupt request is not presented to the interrupt priority logic unless the
IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests. See 14.6 Exception Control.
Figure 8-3 provides a summary of the IRQ I/O register.
Addr.Register Name Bit 7654321Bit 0
Read:0000IRQF0
Write:
Reset:00000000
= Unimplemented
ACK
IMASK MODE
$001D
IRQ Status and Control
Register (INTSCR)
See page 77.
Figure 8-3. IRQ I/O Register Summary
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA External Interrupt (IRQ) 75
For More Information On This Product,
Go to: www.freescale.com
External Interrupt (IRQ)
8.4 IRQ Pin
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A
vector fetch, software clear, or reset clears the IRQ latch.
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
If the MODE bit is set, the IRQ
sensitive. With MODE set, both of the following actions must occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software may generate the interrupt
acknowledge signal by writing a 1 to the ACK bit in the interrupt statu s and
control register (INTSCR). The ACK bit is useful in applications that poll the
pin and require software to clear the IRQ latch. Writing to the ACK bit
IRQ
prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions
on the IRQ
another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU
loads the program counter with the vector address at locations $FFFA and
$FFFB.
• Return of the IRQ
remains active.
The vector fetch or software clear and the return of the IRQ
in any order. The interrupt request remains pending as long as the IRQ
logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the
interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ
clear, a vector fetch or software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts.
The IRQF bit is not affected by the IMASK bit, which makes it useful in applications
where polling is preferred.
NOTE: When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL
instructions can be used to read the logic level on the IRQ
is disabled, these instructions will behave as if the IRQ
of the actual level on the pin. Conversely, when the IRQ
of the port A data register will always read a 0.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking
interrupt requests in the interrupt routine. An internal pullup resistor to V
connected to the IRQ
CONFIG2 register ($001E).
pin. A falling edge that occurs after writing to the ACK bit latches
pin; this can be disabled by setting the IRQPUD bit in the
pin is both falling-edge sensitive and low-level
pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ
pin to logic 1 may occur
pin is at
pin is falling-edge sensitive only. With MODE
pin. If the IRQ function
pin is a logic 1, regardless
function is enabled, bit 2
is
DD
8.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be
cleared during the break state. The BCFE bit in the break flag control register
(BFCR) enables software to clear the latches during the break state. See
Section 14. System Integration Module (SIM).
Data Sheet MC68HC908QF4 — Rev. 1.0
76 External Interrupt (IRQ) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the
BCFE bit. If a latch is cleared during the break state, it remains cleared when the
MCU exits the break state.
To protect the latches during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), writing to the ACK bit in the IRQ status and control register
during the break state has no effect on the IRQ latch.
8.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the
IRQ module, see Section 5. Configuration Register (CONFIG).
The ISCR has the following functions:
• Shows the state of the IRQ flag
nc...
I
• Clears the IRQ latch
• Masks IRQ and interrupt request
• Controls triggering sensitivity of the IRQ
Freescale Semiconductor, Inc.
IRQ Status and Control Register
interrupt pin
External Interrupt (IRQ)
cale Semiconductor,
Frees
Address: $001D
Bit 7654321Bit 0
Read:0000IRQF
Write:
Reset:00000000
= Unimplemented
Figure 8-4. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ
0 = IRQ
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears
IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
MODE.
1 = IRQ
0 = IRQ
interrupt pending
interrupt not pending
interrupt requests on falling edges and low levels
interrupt requests on falling edges only
ACK
IMASK MODE
pin. Reset clears
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA External Interrupt (IRQ) 77
For More Information On This Product,
Go to: www.freescale.com
External Interrupt (IRQ)
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
78 External Interrupt (IRQ) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
9.1 Introduction
9.2 Features
nc...
I
Freescale Semiconductor, Inc.
Section 9. Keyboard Interrupt Module (KBI)
The keyboard interrupt module (KBI) provides six independently maskable external
interrupts, which are accessible via the PTA0–PTA5 pins.
Features of the keyboard interrupt module include:
• Six keyboard interrupt pins with separate keyboard interrupt enable bits and
one keyboard interrupt mask
cale Semiconductor,
Frees
• Software configurable pullup device if input pin is configured as input port bit
• Programmable edge-only or edge and level interrupt sensitivity
• Exit from low-power modes
Figure 9-1 provides a summary of the input/output (I/O) registers
Addr.Register Name Bit 7654321Bit 0
Keyboard Status and Control
$001A
Keyboard Interrupt Enable
$001B
Register (KBSCR)
See page 84.
Register (KBIER)
See page 85.
Read:0000KEYF0
Write:
Reset:00000000
Read: 0
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
= Unimplemented
Figure 9-1. KBI I/O Register Summary
ACKK
IMASKK MODEK
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Keyboard Interrupt Module (KBI) 79
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Keyboard Interrupt Module (KBI)
nc...
I
cale Semiconductor,
Frees
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
/KBI2/TCLK
PTA3/RST
TRANSMITTER
/KBI3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
UHF
PTA
PTB
8-BIT ADC
128 BYTES RAM
V
MODE
PLLEN
DATA
BS
OP1
GND
REXT
XTAL1
XTAL0
UPCLK
PFD
DDRA
M68HC08 CPU
DDRB
MC68HC908QF4
4096 BYTES
USER FLASH
CC
Figure 9-2. Block Diagram Highlighting KBI Block and Pins
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
SINGLE INTERRUPT
MODULE
BREAK
MODULE
POWER-ON RESET
MODULE
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
MONITOR ROM
POWER SUPPLY
V
DD
V
SS
Data Sheet MC68HC908QF4 — Rev. 1.0
80 Keyboard Interrupt Module (KBI) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
KBI0
KBIE0
TO PULLUP ENABLE
KBI5
Freescale Semiconductor, Inc.
.
.
.
V
DD
CLR
DQ
CK
KEYBOARD
INTERRUPT FF
ACKK
RESET
Keyboard Interrupt Module (KBI)
Functional Description
INTERNAL BUS
VECTOR FETCH
DECODER
KEYF
SYNCHRONIZER
IMASKK
KEYBOARD
INTERRUPT
REQUEST
nc...
I
TO PULLUP ENABLE
AWUIREQ
KBIE5
(1)
9.3 Functional Description
9.3.1 Keyboard Operation
cale Semiconductor,
Frees
MODEK
1. For AWUGEN logic refer to Figure 4-2. Auto Wakeup Interrupt
Request Generation Logic.
Figure 9-3. Keyboard Interrupt Block Diagram
The keyboard interrupt module controls the enabling/disabling of interrupt
functions on the six port A pins. These six pins can be enabled/disabled
independently of each other.
Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register (KBIER)
independently enables or disables each port A pin as a keyboard interrupt pin.
Enabling a keyboard interrupt pin in port A also enables its internal pullup device
irrespective of PTAPUEx bits in the port A input pullup enable register (see
13.2.3 Port A Input Pullup Enable Register). A logic 0 applied to an enabled
keyboard interrupt pin latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard interrupt inputs goes
low after all were high. The MODEK bit in the keyboard status and control register
controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard
interrupt input does not latch an interrupt request if another keyboard pin is
already low. To prevent losing an interrupt request on one input because
another input is still low, software can disable the latter input while it is low.
• If the keyboard interrupt is falling edge and low-level sensitive, an interrupt
request is present as long as any keyboard interrupt input is low.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Keyboard Interrupt Module (KBI) 81
For More Information On This Product,
Go to: www.freescale.com
Keyboard Interrupt Module (KBI)
If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and
low-level sensitive, and both of the following actions must occur to clear a keyboard
interrupt request:
nc...
I
Freescale Semiconductor, Inc.
• Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the interrupt request. Software may generate
the interrupt acknowledge signal by writing a 1 to the ACKK bit in the
keyboard status and control register (KBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt inputs and require software to
clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to
noise. Setting ACKK does not affect subsequent transitions on the keyb oard
interrupt inputs. A falling edge that occurs after writing to the ACKK bit
latches another interrupt request. If the keyboard interrupt mask bit,
IMASKK, is clear, the central processor unit (CPU) loads the program
counter with the vector address at locations $FFE0 and $FFE1.
• Return of all enabled keyboard interrupt inputs to logic 1 — As long as any
enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains
set. The auto wakeup interrupt input, AWUIREQ, will be cleared only by
writing to ACKK bit in KBSCR or reset.
cale Semiconductor,
Frees
The vector fetch or software clear and the return of all enabled keyboard interrupt
pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only.
With MODEK clear, a vector fetch or software clear immediately clears the
keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the
interrupt request even if a keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be
used to see if a pending interrupt exists. The KEYF bit is not affected by the
keyboard interrupt mask bit (IMASKK) which makes it useful in applications where
polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction
register to configure the pin as an input and then read the data register.
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard
interrupt pin to be an input, overriding the data direction register. However, the data
direction register bit must be a 0 for software to read the pin.
Data Sheet MC68HC908QF4 — Rev. 1.0
82 Keyboard Interrupt Module (KBI) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to
reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard
3. Write to the ACKK bit in the keyboard status and control register to clear any
4. Clear the IMASKK bit.
Freescale Semiconductor, Inc.
and control register.
interrupt enable register.
false interrupts.
Keyboard Interrupt Module (KBI)
Wait Mode
nc...
I
9.4 Wait Mode
cale Semiconductor,
9.5 Stop Mode
Frees
An interrupt signal on an edge-triggered pin can be acknowledged immediately
after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt
pin must be acknowledged after a delay that depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA
bits in the data direction register A.
2. Write 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard
interrupt enable register.
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the
keyboard status and control register enables keyboard interrupt requests to bring
the MCU out of wait mode.
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the
keyboard status and control register enables keyboard interrupt requests to bring
the MCU out of stop mode.
9.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch
can be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear status bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt,
write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains
cleared when the MCU exits the break state.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Keyboard Interrupt Module (KBI) 83
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Keyboard Interrupt Module (KBI)
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the
keyboard status and control register during the break state has no effect.
9.7 Input/Output Registers
The following I/O registers control and monitor operation of the keyboard interrupt
module:
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
9.7.1 Keyboard Status and Control Register
nc...
I
cale Semiconductor,
Frees
The keyboard status and control register (KBSCR):
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7654321Bit 0
Read:0000KEYF0
Write: ACKK
Reset:00000000
= Unimplemented
Figure 9-4. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto
wakeup. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
IMASKK MODEK
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard interrupt request on port A
and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK.
Data Sheet MC68HC908QF4 — Rev. 1.0
84 Keyboard Interrupt Module (KBI) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt
mask from generating interrupt requests on port A or auto wakeup. Reset clears
the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt
pins on port A and auto wakeup. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
9.7.2 Keyboard Interrupt Enable Register
Keyboard Interrupt Module (KBI)
Input/Output Registers
nc...
I
cale Semiconductor,
Frees
The port A keyboard interrupt enable register (KBIER) enables or disables each
port A pin or auto wakeup to operate as a keyboard interrupt input.
Address: $001B
Bit 7654321Bit 0
Read: 0
Write:
Reset:00000000
Figure 9-5. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Port A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin
on port A to latch interrupt requests. Reset clears the keyboard interrupt enable
register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
NOTE: AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a
description of this bit, see Section 4. Auto Wakeup Module (AWU).
AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
= Unimplemented
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Keyboard Interrupt Module (KBI) 85
For More Information On This Product,
Go to: www.freescale.com
Keyboard Interrupt Module (KBI)
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
86 Keyboard Interrupt Module (KBI) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Data Sheet — MC68HC908QF4
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the
voltage on the V
LVI trip falling voltage, V
10.2 Features
Section 10. Low-Voltage Inhibit (LVI)
pin and can force a reset when the V
DD
.
TRIPF
voltage falls below the
DD
nc...
I
10.3 Functional Description
cale Semiconductor,
Frees
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Selectable LVI trip voltage
• Programmable stop mode operation
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD,
LVDLVR, and LVIRSTD are user selectable options found in the configuration
register (CONFIG1). See Section 5. Configuration Register (CONFIG).
V
DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
> LVITRIP = 0
V
LOW V
DD
DETECTOR
LVDLVR
FROM CONFIG
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Low-Voltage Inhibit (LVI) 87
For More Information On This Product,
Go to: www.freescale.com
DD
≤ LVITRIP = 1
V
DD
LVIOUT
Figure 10-1. LVI Module Block Diagram
LVI RESET
Low-Voltage Inhibit (LVI)
NOTE: After a power-on reset, the LVI’s default mode of operation is LVR trip voltage. If a
nc...
I
Freescale Semiconductor, Inc.
The LVI is enabled out of reset. The LVI module contains a bandgap reference
circuit and comparator. Clearing the LVI power disable bit (LVIPWRD) enables the
LVI to monitor V
the LVI module to generate a reset when V
V
DTRIPF
operate in stop mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the
LVD trip point voltage. The actual trip thresholds are specified in 17.5 DC
Electrical Characteristics. Either trip level can be used as a detect or reset.
higher trip voltage is desired, the user must set the LVDLVR bit to raise the trip
point to the LVD voltage.
If the user requires the higher trip voltage and sets the LVDLVR bit after power-on
reset while the VDD supply is not above the V
microcontroller unit (MCU) will immediately go into reset. The next time the LVI
releases the reset, the supply will be above the V
. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to
voltage. Clearing the LVI reset disable bit (LVIRSTD) enables
DD
falls below a voltage, V
DD
for LVD mode, the
TRIPR
for LVD mode.
TRIPR
TRIPF
or
Once an LVI reset occurs, the MCU remains in reset until VDD rises above a
voltage, V
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR) and can be used for polling LVI operation when the LVI reset is
disabled.
10.3.1 Polled LVI Operation
In applications that can operate at V
monitor V
bit must be cleared to enable the LVI module, and the LVIRSTD bit must be set to
disable LVI resets.
cale Semiconductor,
10.3.2 Forced Reset Operation
In applications that require V
resets allows the LVI module to reset the MCU when V
Frees
10.3.3 Voltage Hysteresis Protection
level. In the configuration register, the LVIPWRD and LVIRSTD bits must be
cleared to enable the LVI module and to enable LVI resets.
, which causes the MCU to exit reset. See Section 14. System
TRIPR
levels below the V
DD
by polling the LVIOUT bit. In the configuration register, the LVIPWRD
DD
to remain above the V
DD
TRIPF
DD
level, software can
TRIPF
level, enabling LVI
falls below the V
TRIPF
Once the LVI has triggered (by having V
a reset condition until V
prevents a condition in which the MCU is continually entering and exiting reset if
V
is approximately equal to V
DD
hysteresis voltage, V
Data Sheet MC68HC908QF4 — Rev. 1.0
88 Low-Voltage Inhibit (LVI) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
rises above the rising trip point voltage, V
DD
TRIPF
.
HYS
fall below V
DD
. V
TRIPR
), the LVI will maintain
TRIPF
is greater than V
TRIPF
TRIPR
by the
. This
10.3.4 LVI Trip Selection
nc...
I
Freescale Semiconductor, Inc.
The LVDLVR bit in the configuration register selects whether the LVI is configured
for LVD (low voltage detect) or LVR (low voltage reset) protection. The LVD trip
voltage can be used as a low voltage warning. The LVR trip voltage will commonly
be configured as a reset condition since it is very close to the minimum operating
voltage of the device. The LVDLVR bit can be written to anytime so that battery
applications can make use of the LVI as both a warning indicator and to generate
a system reset.
Polling and forced reset operation modes can be combined to take full advantage
of LVD and LVR trip voltages selection. LVD (LVDLVR = 1) in polling mode
(LVIRSTD = 1) can be used as a low voltage warning in a slowly and continuously
falling V
identified, the part can be set to LVR (LVDLVR = 0) and reset enabled
(LVIRSTD = 0). So, as V
voltage is reached. Unlike other bits in CONFIG registers, LVIRSTD and LVDLVR
bits are allowed to be written multiple times after reset.
DD
Low-Voltage Inhibit (LVI)
LVI Status Register
application (for example, battery applications). Once LVD has been
continues to fall the part will reset when LVR trip
DD
NOTE: The microcontroller is guaranteed to operate a t a minimum supply voltage. The trip
10.4 LVI Status Register
cale Semiconductor,
Frees
point (V
Electrical Characteristics for the actual trip point voltages.
The LVI status register (LVISR) indicates if the VDD voltage was detected below
the V
TRIPF
Address: $FE0C
Read:LVIOUT000000R
Write:
Reset:00000000
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
trip voltage and is cleared when V
in these threshold levels results in a hysteresis that prevents oscillation into and
out of reset (see Table 10-1). Reset clears the LVIOUT bit.
[LVD] or V
TRIPF
level while LVI resets have been disabled.
Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 10-2. LVI Status Register (LVISR)
[LVR]) may be lower than this. See 17.5 DC
TRIPF
voltage falls below the V
DD
voltage rises above V
DD
TRIPR
TRIPF
. The difference
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Low-Voltage Inhibit (LVI) 89
For More Information On This Product,
Go to: www.freescale.com
Low-Voltage Inhibit (LVI)
Freescale Semiconductor, Inc.
Table 10-1. LVIOUT Bit Indication
10.5 LVI Interrupts
10.6 Low-Power Modes
nc...
I
10.6.1 Wait Mode
10.6.2 Stop Mode
cale Semiconductor,
V
DD
VDD > V
V
V
TRIPF
The LVI module does not generate interrupt requests.
The STOP and WAIT instructions put the MCU in low power-consumption standby
modes.
If enabled, the LVI module remains active in wait mode. If enabled to generate
resets, the LVI module can generate a reset and bring the MCU out of wait mode.
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP
bit in the configuration register is set, the LVI module remains active in stop mode.
If enabled to generate resets, the LVI module can generate a reset and bring the
MCU out of stop mode.
TRIPR
< V
DD
TRIPF
< VDD < V
TRIPR
LVIOUT
0
1
Previous value
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
90 Low-Voltage Inhibit (LVI) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Data Sheet — MC68HC908QF4
11.1 Introduction
nc...
I
Freescale Semiconductor, Inc.
Section 11. Oscillator Module (OSC)
The oscillator module is used to provide a stable clock source for the
microcontroller system and bus. The oscillator module generates two output
clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by the system
integration module (SIM) and the computer operating properly module (COP). The
BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the
microcontroller. Therefore the bus frequency will be one forth of the BUSCLKX4
frequency.
11.2 Features
11.3 Functional Description
cale Semiconductor,
Frees
The oscillator has these four clock source options available:
1. Internal oscillator: An internally generated, fixed frequency clock, trimmable
to ±5%. This is the default option out of reset.
2. External oscillator: An external clock that can be driven directly into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that requires an
external R connection only. The capacitor is internal to the chip.
4. External crystal: A built-in oscillator module (XTAL oscillator) that requires
an external crystal or ceramic-resonator.
The oscillator contains these major subsystems:
• Internal oscillator circuit
• Internal or external clock switch control
• External clock circuit
• External crystal circuit
• External RC clock circuit
11.3.1 Internal Oscillator
The internal oscillator circuit is designed for use with no external components to
provide a clock source with tolerance less than ±25% untrimmed. An 8-bit trimming
register allows adjustment to a tolerance of less than ±5%.
The internal oscillator will generate a clock of 4.0 MHz typical (INTCLK) resulting
in a bus speed (internal clock ÷ 4) of 1.0 MHz.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Oscillator Module (OSC) 91
For More Information On This Product,
Go to: www.freescale.com
Oscillator Module (OSC)
Freescale Semiconductor, Inc.
nc...
I
cale Semiconductor,
Frees
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ
/KBI2/TCLK
PTA
PTB
V
MODE
PLLEN
DATA
BS
OP1
GND
REXT
XTAL1
XTAL0
UPCLK
PFD
DDRA
M68HC08 CPU
DDRB
MC68HC908QF4
4096 BYTES
USER FLASH
CC
PTA3/RST
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
TRANSMITTER
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
/KBI3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
8-BIT ADC
128 BYTES RAM
UHF
Figure 11-1. Block Diagram Highlighting OSC Block and Pins
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
SINGLE INTERRUPT
MODULE
BREAK
MODULE
POWER-ON RESET
MODULE
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
MONITOR ROM
POWER SUPPLY
V
DD
V
SS
Data Sheet MC68HC908QF4 — Rev. 1.0
92 Oscillator Module (OSC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC
oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in PTAPUE register.
See Section 13. Input/Output (I/O) Ports.
11.3.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and
–128 steps. Increasing OSCTRIM value increases the clock period. Trimming
allows the internal clock frequency to be set to 4.0 MHz ±5%.
All devices are programmed with a trim value in a reserved FLASH location,
$FFC0. This value can be copied from the FLASH to the OSCTRIM register
($0038) during reset initialization.
Reset loads OSCTRIM with a default value of $80.
nc...
I
WARNING: Bulk FLASH erasure will set location $FFC0 to $FF and the factory
programmed value will be lost.
Freescale Semiconductor, Inc.
Oscillator Module (OSC)
Functional Description
11.3.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must
perform the following steps:
1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an
external crystal oscillator, set PTA4 (OSC2) as an output and drive high for
several cycles. This may help the crystal circuit start more robustly.
2. Set CONFIG2 bits OSCOPT[1:0] according to 11.7 CONFIG2 Options. The
oscillator module control logic will then set OSC1 as an external clock input
and, if the external crystal option is selected, OSC2 will also be set as the
clock output.
3. Create a software delay to wait the stabilization time needed for the selected
cale Semiconductor,
Frees
clock source (crystal, resonator, RC) as recommended by the component
manufacturer. A good rule of thumb for crystal oscillators is to wait 4096
cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait approximately
1 msec.
4. After the manufacturer’s recommended delay has elapsed, th e ECGON bit
in the OSC status register (OSCSTAT) needs to be set by the user software.
5. After ECGON set is detected, the OSC module checks for oscillator activity
by waiting two external clock rising edges.
6. The OSC module then switches to the external clock. Logic provides a glitch
free transition.
7. The OSC module first sets the ECGST bit in the OSCSTAT register and then
stops the internal oscillator.
NOTE: Once transition to the external clock is done, the internal oscillator will only be
reactivated with reset. No post-switch clock monitor feature is implemented (clock
does not switch back to internal if external clock dies).
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Oscillator Module (OSC) 93
For More Information On This Product,
Go to: www.freescale.com
Oscillator Module (OSC)
11.3.2 External Oscillator
11.3.3 XTAL Oscillator
nc...
I
Freescale Semiconductor, Inc.
The external clock option is designed for use when a clock signal is available in the
application to provide a clock source to the microcontroller. The OSC1 pin is
enabled as an input by the oscillator module. The clock signal is used directly to
create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit
in the port A pullup enable register will be clear to enable PTA4 I/O functions on the
pin.
The XTAL oscillator circuit is designed for use with an external low-frequency
crystal or ceramic resonator to provide an accurate clock source. In this
configuration, the OSC2 pin is dedicated to the external crystal circuit. The
OSC2EN bit in the port A pullup enable register has no effect when this clock mode
is selected.
cale Semiconductor,
Frees
In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator
configuration, as shown in Figure 11-2. This figure shows only the logical
representation of the internal components and may not represent actual circuitry.
The oscillator configuration uses five components:
•Crystal, X
• Fixed capacitor, C
1
1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, R
• Series resistor, R
FROM SIM
SIMOSCEN
MCU
B
S
TO SIMTO SIM
BUSCLKX2BUSCLKX4
XTALCLK
OSC2OSC1
R
R
B
X
1
S
÷ 2
C
1
C
2
Figure 11-2. XTAL Oscillator External Connections
Data Sheet MC68HC908QF4 — Rev. 1.0
94 Oscillator Module (OSC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
11.3.4 RC Oscillator
Freescale Semiconductor, Inc.
Oscillator Module (OSC)
Oscillator Module Signals
The RC oscillator circuit is designed for use with external R to provide a clock
source with tolerance less than 25%.
In its typical configuration, the RC oscillator requires two external components, one
R and one C. In the MC68HLC908QF4, the capacitor is internal to the chip. The R
value should have a tolerance of 1% or less, to obtain a clock source with less than
25% tolerance. The oscillator configuration uses one component, R
EXT
.
In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the
OSC2EN bit in the port A pullup enable register can be set to enable the OSC2
output function on the pin. Enabling the OSC2 output slightly increases the external
RC oscillator frequency, f
RCCLK
.
nc...
I
cale Semiconductor,
Frees
11.4 Oscillator Module Signals
SIMOSCEN
MCU
OSCRCOPT
INTCLK
EXTERNAL RC
EN
OSCILLATOR
OSC1
V
DD
R
EXT
RCCLK
PTA4/BUSCLKX4 (OSC2)
See Section 17. Electrical Specifications
for component value requirements.
0
1
1
0
TO SIM
PTA4
I/O
Figure 11-3. RC Oscillator External Connections
÷ 2
TO SIMFROM SIM
BUSCLKX2BUSCLKX4
PTA4
OSC2EN
The following paragraphs describe the signals that are inputs to and outputs from
the oscillator module.
11.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC
oscillator circuit, or an external clock source.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Oscillator Module (OSC) 95
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Oscillator Module (OSC)
For the internal oscillator configuration, the OSC1 pin can assume other functions
according to Table 1-1. Pin Functions.
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)
For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting
amplifier output.
For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function.
The OSC2EN bit has no effect.
For the internal oscillator or RC oscillator options, the OSC2 pin can assume other
functions according to Table 1-1. Pin Functions, or the output of the oscillator
clock (BUSCLKX4).
nc...
I
Option OSC2 Pin Function
XTAL oscillator Inverting OSC1
External clock PTA4 I/O
Table 11-1. OSC2 Pin Function
Internal oscillator
11.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and
enables/disables either the XTAL oscillator circuit, the RC oscillator, or the internal
oscillator.
11.4.4 XTAL Oscillator Clock (XTALCLK)
cale Semiconductor,
Frees
11.4.5 RC Oscillator Clock (RCCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal
) and comes directly from the crystal oscillator circuit. Figure 11-2 shows
(f
XCLK
only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent
the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on
the crystal and other external factors. Also, the frequency and amplitude of
XTALCLK can be unstable at start up.
RCCLK is the RC oscillator output signal. Its frequency is directly proportional to
the time constant of external R and internal C. Figure 11-3 shows only the logical
relation of RCCLK to OSC1 and may not represent the actual circuitry.
or
RC oscillator
Controlled by OSC2EN bit in PTAPUE register
OSC2EN = 0: PTA4 I/O
OSC2EN = 1: BUSCLKX4 output
Data Sheet MC68HC908QF4 — Rev. 1.0
96 Oscillator Module (OSC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
11.4.6 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to 4.0
MHz, but it can be also trimmed using the oscillator trimming feature of the
OSCTRIM register (see 11.3.1.1 Internal Oscillator Trimming).
11.4.7 Oscillator Out 2 (BUSCLKX4)
BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This
signal is driven to the SIM module and is used to determine the COP cycles.
11.4.8 Oscillator Out (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4, this signal is driven
to the SIM for generation of the bus clocks used by the CPU and other modules on
nc...
I
the MCU. BUSCLKX2 will be divided again in the SIM and results in the internal
bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK
frequency.
Oscillator Module (OSC)
Low Power Modes
11.5 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby
modes.
11.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and
BUSCLKX4 continue to drive to the SIM module.
11.5.2 Stop Mode
The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK
cale Semiconductor,
output, hence BUSCLKX2 and BUSCLKX4.
11.6 Oscillator During Break Mode
Frees
The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device
enters the break state.
11.7 CONFIG2 Options
Two CONFIG2 register options affect the operation of the oscillator module:
OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have a default
configuration. Refer to Section 5. Configuration Register (CONFIG) for more
information on how the CONFIG2 register is used.
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Oscillator Module (OSC) 97
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Oscillator Module (OSC)
Table 11-2 shows how the OSCOPT bits are used to select the oscillator clock
source.
OSCOPT1 OSCOPT0 Oscillator Modes
11.8 Input/Output (I/O) Registers
Table 11-2. Oscillator Modes
0 0 Internal Oscillator
0 1 External Oscillator
10External RC
1 1 External Crystal
nc...
I
11.8.1 Oscillator Status Register
cale Semiconductor,
Frees
The oscillator module contains these two registers:
1. Oscillator status register (OSCSTAT)
2. Oscillator trim register (OSCTRIM)
The oscillator status register (OSCSTAT) contains the bits for switching from
internal to external clock sources.
Address:
ECGON — External Clock Generator On Bit
This read/write bit enables external clock generator, so that the switching
process can be initiated. This bit is forced low during reset. This bit is ignored in
monitor mode with the internal oscillator bypassed.
$0036
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
1 = External clock generator enabled
0 = External clock generator disabled
RRRRRRECGON
=Reserved
R
Figure 11-4. Oscillator Status Register (OSCSTAT)
= Unimplemented
ECGST
ECGST — External Clock Status Bit
This read-only bit indicates whether or not an external clock source is engaged
to drive the system clock.
1 = An external clock source engaged
0 = An external clock source disengaged
Data Sheet MC68HC908QF4 — Rev. 1.0
98 Oscillator Module (OSC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
11.8.2 Oscillator Trim Register (OSCTRIM)
Oscillator Module (OSC)
Input/Output (I/O) Registers
Address:
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the
internal oscillator. By measuring the period of the internal clock and adjusting
this factor accordingly, the frequency of the internal clock can be fine tuned.
nc...
I
Increasing (decreasing) this factor by one increases (decreases) the period by
approximately 0.2% of the untrimmed period (the period for TRIM = $80). The
trimmed frequency is guaranteed not to vary by more than ±5% over the full
specified range of temperature and voltage. The reset value is $80, which sets
the frequency to 4.0 MHz (1.0 MHz bus speed) ±25%.
cale Semiconductor,
$0038
Bit 7654321Bit 0
Read:
Write:
Reset:10000000
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
Figure 11-5. Oscillator Trim Register (OSCTRIM)
Frees
MC68HC908QF4 — Rev. 1.0 Data Sheet
MOTOROLA Oscillator Module (OSC) 99
For More Information On This Product,
Go to: www.freescale.com
Oscillator Module (OSC)
nc...
I
Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet MC68HC908QF4 — Rev. 1.0
100 Oscillator Module (OSC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Loading...