Freescale MC68HC908JL8, MC68HC908JK8, MC68HC908KL8, MC68HC08JL8, MC68HC08JK8 User Manual

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MC68HC908JL8 MC68HC908JK8 MC68HC908KL8 MC68HC08JL8 MC68HC08JK8

Data Sheet

M68HC08 Microcontrollers

MC68HC908JL8 Rev. 3.1 3/2005

freescale.com

MC68HC908JL8 MC68HC908JK8 MC68HC908KL8 MC68HC08JL8 MC68HC08JK8

Data Sheet

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://www.freescale.com

The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 3

Revision History

Date

Mar 2005 3.1

Nov 2004 3

Nov 2002 2 First general release. —

Revision

Level

Description

Added IRQ timing to Table 17-5 . Control Timing (5V) and Table 17-8 .

Control Timing (3V)

Chapter 9 Serial Communications Interface (SCI) — Corrected SCI

module clock source from OSCCLK to Bus Clock throughout.

Figure 13-2 . Keyboard Interrupt Block Diagram —

Removed incorrect Schmitt trigger in block diagram.

14.7.2 Stop Mode — STOP_ICLKDIS bit does not affect stop mode

conditions for COP. Replaced section with new text.

Added Appendix A MC68HC08JL8 — ROM parts. 201

Added Appendix B MC68HC908KL8. 207

Page

Number(s)

188, 190

121–206

168

176

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4 Freescale Semiconductor

List of Chapters

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR) . . . . . . . . . . . . . .41

Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Chapter 5 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Chapter 6 Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Chapter 9 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Chapter 10 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Chapter 11 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Chapter 12 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Chapter 13 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Chapter 14 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Chapter 15 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

Chapter 16 Break Module (BREAK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Chapter 18 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Chapter 19 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Appendix A MC68HC08JL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Appendix B MC68HC908KL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

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List of Chapters

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

6 Freescale Semiconductor

Chapter 1

General Description

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 2

Memory

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.4 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.7 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.8 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.9 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.10 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.11 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.12 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 3

Configuration and Mask Option Registers (CONFIG & MOR)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.3 Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.4 Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.5 Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 4

Central Processor Unit (CPU)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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Freescale Semiconductor 7

Table of Contents

4.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 5

System Integration Module (SIM)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.2.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.7.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.7.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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8 Freescale Semiconductor

Chapter 6

Oscillator (OSC)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2.1 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.2.2 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.4 XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.4.8 Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Chapter 7

Monitor ROM (MON)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.3.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.3.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.3.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.3.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.3.5 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.3.6 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.5 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.5.1 PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.5.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.5.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.5.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.5.5 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.5.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.5.7 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.5.8 EE_READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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Chapter 8

Timer Interface Module (TIM)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.4.4.3 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

8.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

8.8.1 TIM Clock Pin (ADC12/T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

8.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1) . . . . . 113

8.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

8.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

8.9.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

8.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

8.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

8.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Chapter 9

Serial Communications Interface (SCI)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

9.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

9.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.4.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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9.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

9.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

9.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

9.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

9.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.7.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

9.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

9.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.8.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Chapter 10

Analog-to-Digital Converter (ADC)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

10.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

10.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

10.6.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

10.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

10.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

10.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

10.7.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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Chapter 11

Input/Output (I/O) Ports

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

11.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

11.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

11.2.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

11.2.3 Port A Input Pull-Up Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

11.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.3.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.4.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.5 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.5.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.5.2 Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Chapter 12

External Interrupt (IRQ)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

12.3.1 IRQ

12.4 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

12.5 IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Chapter 13

Keyboard Interrupt Module (KBI)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

13.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13.5 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13.5.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

13.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Chapter 14

Computer Operating Properly (COP)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

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14.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

14.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

14.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Chapter 15

Low Voltage Inhibit (LVI)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

15.4 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Chapter 16

Break Module (BREAK)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

16.3.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

16.3.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

16.3.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

16.3.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

16.4 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

16.4.1 Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

16.4.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

16.4.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

16.4.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

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Chapter 17

Electrical Specifications

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

17.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

17.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

17.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

17.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

17.6 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

17.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

17.8 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

17.9 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

17.10 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

17.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

17.12 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

17.13 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

17.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 18

Mechanical Specifications

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

18.2 20-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

18.3 20-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

18.4 28-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

18.5 28-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

18.6 32-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

18.7 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Chapter 19

Ordering Information

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

19.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Appendix A

MC68HC08JL8

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

A.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

A.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

A.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

A.5 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

A.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

A.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

A.7.1 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

A.8 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

A.9 MC68HC08JL8 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

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Appendix B

MC68HC908KL8

B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

B.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

B.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

B.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

B.5 Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

B.6 MC68HC908KL8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

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Table of Contents

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Chapter 1 General Description

1.1 Introduction

The MC68HC908JL8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

Table 1-1. Summary of Devices

Generic Part Description Pin Count

MC68HC908JL8 FLASH part 28 or 32

MC68HC908JK8 FLASH part 20

MC68HC08JL8 ROM part for MC68HC908JL8 28 or 32

MC68HC08JK8 ROM part for MC68HC908JK8 20

MC68HC908KL8 ADC-less MC68HC908JL8 28 or 32

1.2 Features

Features of the MC68HC908JL8 include the following:

• High-performance M68HC08 architecture

• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

• Low-power design; fully static with stop and wait modes

• Maximum internal bus frequency: – 8-MHz at 5V operating voltage – 4-MHz at 3V operating voltage

• Oscillator options: – Crystal or resonator – RC oscillator

• 8,192 bytes user program FLASH memory with security

(1)

feature

• 256 bytes of on-chip RAM

• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel; external clock input option on TIM2

• 13-channel, 8-bit analog-to-digital converter (ADC)

• Serial communications interface module (SCI)

• 26 general-purpose input/output (I/O) ports: – 8 keyboard interrupt with internal pull-up

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

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General Description

– 11 LED drivers (sink) –2 × 25mA open-drain I/O with pull-up

• Resident routines for in-circuit programming and EEPROM emulation

• System protection features: – Optional computer operating properly (COP) reset, driven by internal RC oscillator – Optional low-voltage detection with reset and selectable trip points for 3V and 5 V operation – Illegal opcode detection with reset – Illegal address detection with reset

• Master reset pin with internal pull-up and power-on reset

•IRQ

with schmitt-trigger input and programmable pull-up

• 20-pin dual in-line package (PDIP), 20-pin small outline integrated package (SOIC), 28-pin PDIP, 28-pin SOIC, 32-pin shrink dual in-line package (SDIP), and 32-pin low-profile quad flat pack (LQFP)

• Specific features of the MC68HC908JL8 in 28-pin packages are: – 23 general-purpose I/Os only – 7 keyboard interrupt with internal pull-up – 10 LED drivers (sink) – 12-channel ADC – Timer I/O pins on TIM1 only

• Specific features of the MC68HC908JL8 in 20-pin packages are: – 15 general-purpose I/Os only – 1 keyboard interrupt with internal pull-up – 4 LED drivers (sink) – 10-channel ADC – Timer I/O pins on TIM1 only

Features of the CPU08 include the following:

• Enhanced HC05 programming model

• Extensive loop control functions

• 16 addressing modes (eight more than the HC05)

• 16-bit index register and stack pointer

• Memory-to-memory data transfers

• Fast 8 × 8 multiply instruction

• Fast 16/8 divide instruction

• Binary-coded decimal (BCD) instructions

• Optimization for controller applications

• Efficient C language support

1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908JL8.

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18 Freescale Semiconductor

INTERNAL BUS

MCU Block Diagram

M68HC08 CPU

CPU

REGISTERS

ARITHMETIC/LOGIC

UNIT (ALU)

CONTROL AND STATUS REGISTERS — 64 BYTES

USER FLASH — 8,192 BYTES

USER RAM — 256 BYTES

MONITOR ROM — 959 BYTES

USER FLASH VECTORS — 36 BYTES

OSC1

OSC2/RCCLK

CRYSTAL OSCILLATOR

RC OSCILLATOR

INTERNAL OSCILLATOR

* RST

SYSTEM INTEGRATION

MODULE

KEYBOARD INTERRUPT

MODULE

8-BIT ANALOG-TO-DIGITAL

CONVERTER MODULE

2-CHANNEL TIMER INTERFACE

MODULE 1

2-CHANNEL TIMER INTERFACE

MODULE 2

BREAK

MODULE

SERIAL COMMUNICATIONS

INTERFACE MODULE

POWER-ON RESET

MODULE

LOW-VOLTAGE INHIBIT

MODULE

DDRA

DDRB

DDRD

PORTA

PORTB

PORTD

PTA7/KBI7**

PTA6/KBI6**

PTA5/KBI5**

PTA4/KBI4**

PTA3/KBI3**

PTA2/KBI2**

PTA1/KBI1**

PTA0/KBI0**

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

PTB4/ADC4

PTB3/ADC3

PTB2/ADC2

PTB1/ADC1

PTB0/ADC0

ADC12/T2CLK

PTD7/RxD** PTD6/TxD**

PTD5/T1CH1

PTD4/T1CH0

PTD3/ADC8

PTD2/ADC9

PTD1/ADC10

PTD0/ADC11

‡

†‡

‡

* IRQ

VDD

VSS

EXTERNAL INTERRUPT

MODULE

POWER

ADC REFERENCE

Figure 1-1. MC68HC908JL8 Block Diagram

COMPUTER OPERATING

PROPERLY MODULE

* Pin contains integrated pull-up device.

** Pin contains programmable pull-up device.

† 25mA open-drain if output pin. ‡ LED direct sink pin.

¥ Shared pin: OSC2/RCCLK/PTA6/KBI6.

# Pins available on 32-pin packages only.

## Pins available on 28-pin and 32-pin packages only.

DDRE

PTE

PTE1/T2CH1

PTE0/T2CH0

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General Description

1.4 Pin Assignments

OSC2/RCCLK/PTA6/KBI6

OSC1

PTA1/KBI1

VDD

PTA2/KBI2

PTA3/KBI3

PTB7/ADC7

PTB6/ADC6

PTA0/KBI0

VSS

IRQ

ADC12/T2CLK

PTA7/KBI7

RST

PTA5/KBI5

PTD4/T1CH0

PTD5/T1CH1

PTD2/ADC9

PTA4/KBI4

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTD1/ADC10

PTB2/ADC2

PTB5/ADC5

PTE0/T2CH0

PTB4/ADC4

PTE1/T2CH1

PTD0/ADC11

PTB3/ADC3

PTD6/TxD

PTD7/RxD

Figure 1-2. 32-Pin LQFP Pin Assignment

IRQ

PTA0/KBI0

VSS

OSC1

OSC2/RCCLK/PTA6/KBI6

PTA1/KBI1

VDD

PTA2/KBI2

PTA3/KBI3

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

PTD7/RxD

PTD6/TxD

PTE0/T2CH0

PTE1/T2CH1

ADC12/T2CLK

PTA7/KBI7

RST

PTA5/KBI5

PTD4/T1CH0

PTD5/T1CH1

PTD2/ADC9

PTA4/KBI4

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTD1/ADC10

PTB2/ADC2

PTB3/ADC3

PTD0/ADC11

PTB4/ADC4

Figure 1-3. 32-Pin SDIP Pin Assignment

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

20 Freescale Semiconductor

IRQ

PTA0/KBI0

VSS

OSC1

OSC2/RCCLK/PTA6/KBI6

PTA1/KBI1

VDD

PTA2/KBI2

PTA3/KBI3

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

PTD7/RxD

PTD6/TxD

RST

PTA5/KBI5

PTD4/T1CH0

PTD5/T1CH1

PTD2/ADC9

PTA4/KBI4

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTD1/ADC10

PTB2/ADC2

PTB3/ADC3

PTD0/ADC11

PTB4/ADC4

Pins not available on 28-pin packages

PTE0/T2CH0

PTE1/T2CH1

ADC12/T2CLK

PTA7/KBI7

Internal pads are unconnected. Set these unused port I/Os to output low.

Pin Functions

OSC2/RCCLK/PTA6/KBI6

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

The 20-pin MC68HC908JL8 is designated MC68HC908JK8.

1.5 Pin Functions

Figure 1-4. 28-Pin PDIP/SOIC Pin Assignment

IRQ

VSS

OSC1

VDD

PTD7/RxD

PTD6/TxD

RST

PTD4/T1CH0

PTD5/T1CH1

PTD2/ADC9

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTB2/ADC2

PTB3/ADC3

PTB4/ADC4

Pins not available on 20-pin packages

PTA0/KBI0 PTD0/ADC11

PTA1/KBI1 PTD1/ADC10

PTA2/KBI2

PTA3/KBI3 PTE0/T2CH0

PTA4/KBI4 PTE1/T2CH1

PTA5/KBI5

PTA7/KBI7

Internal pads are unconnected. Set these unused port I/Os to output low.

Figure 1-5. 20-Pin PDIP/SOIC Pin Assignment

ADC12/T2CLK

Description of the pin functions are provided in Table 1-2.

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 21

General Description

Table 1-2. Pin Functions

PIN NAME PIN DESCRIPTION IN/OUT

VDD Power supply. In 5V or 3V

VSS Power supply ground. Out 0V

RST

IRQ

OSC1 Crystal or RC oscillator input. In VDD

OSC2/RCCLK

ADC12/T2CLK

PTA0–PTA7

Reset input, active low; with internal pull-up and schmitt trigger input.

External IRQ pin; with programmable internal pull-up and schmitt trigger input.

Used for monitor mode entry. In

OSC2: crystal oscillator output; inverted OSC1 signal. Out VDD

RCCLK: RC oscillator clock output. Out VDD

Pin as PTA6/KBI6 (see PTA0–PTA7). In/Out VDD

ADC12: channel-12 input of ADC. In VSS to VDD

T2CLK: external input clock for TIM2. In VDD

8-bit general purpose I/O port. In/Out VDD

Each pin has programmable internal pull-up when configured as input.

Pins as keyboard interrupts, KBI0–KBI7. In VDD

In/Out VDD

In VDD

VOLTAGE

LEVEL

VDD to V

TST

PTB0–PTB7

PTD0–PTD7

PTA0–PTA5 and PTA7 have LED direct sink capability. Out VSS

PTA6 as OSC2/RCCLK. Out VDD

8-bit general purpose I/O port. In/Out VDD

Pins as ADC input channels, ADC0–ADC7. In VSS to VDD

8-bit general purpose I/O port; with programmable internal pull-ups on PTD6–PTD7.

PTD0–PTD3 as ADC input channels, ADC11–ADC8. Input VSS to VDD

PTD2–PTD3 and PTD6–PTD7 have LED direct sink capability Out VSS

PTD4 as T1CH0 of TIM1. In/Out VDD

PTD5 as T1CH1 of TIM1. In/Out VDD

PTD6–PTD7 have configurable 25mA open-drain output. Out VSS

PTD6 as TxD of SCI. Out VDD

PTD7 as RxD of SCI. In VDD

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

In/Out VDD

22 Freescale Semiconductor

Table 1-2. Pin Functions (Continued)

Pin Functions

PIN NAME PIN DESCRIPTION IN/OUT

2-bit general purpose I/O port. In/Out VDD

PTE0–PTE1

PTE0 as T2CH0 of TIM2. In/Out VDD

PTE1 as T2CH1 of TIM2. In/Out VDD

NOTE

Devices in 28-pin packages, the following pins are not available:

PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.

Devices in 20-pin packages, the following pins are not available:

PTA0/KBI0–PTA5/KBI5, PTD0/ADC11, PTD1/ADC10,

PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.

VOLTAGE

LEVEL

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 23

General Description

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

24 Freescale Semiconductor

Chapter 2 Memory

2.1 Introduction

The CPU08 can address 64-kbytes of memory space. The memory map, shown in Figure 2-1, includes:

• 8,192 bytes of user FLASH memory

• 36 bytes of user-defined vectors

• 959 bytes of monitor ROM

2.2 I/O Section

Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses:

• $FE00; Break Status Register, BSR

• $FE01; Reset Status Register, RSR

•$FE02; Reserved

• $FE03; Break Flag Control Register, BFCR

• $FE04; Interrupt Status Register 1, INT1

• $FE05; Interrupt Status Register 2, INT2

• $FE06; Interrupt Status Register 3, INT3

•$FE07; Reserved

• $FE08; FLASH Control Register, FLCR

•$FE09; Reserved

•$FE0A; Reserved

•$FE0B; Reserved

• $FE0C; Break Address Register High, BRKH

• $FE0D; Break Address Register Low, BRKL

• $FE0E; Break Status and Control Register, BRKSCR

•$FE0F; Reserved

• $FFCF; FLASH Block Protect Register, FLBPR (FLASH register)

• $FFD0; Mask Option Register, MOR (FLASH register)

• $FFFF; COP Control Register, COPCTL

2.3 Monitor ROM

The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 25

Monitor ROM

Addr.Register Name Bit 7654321Bit 0

$0000 Port A Data Register (PTA)

$0001 Port B Data Register (PTB)

$0002 Unimplemented

Read:

Write:

Reset: Unaffected by reset

Read:

Write:

Reset: Unaffected by reset

Read:

Write:

PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

$0003 Port D Data Register (PTD)

$0004

$0005

$0006 Unimplemented

$0007

$0008

$0009 Unimplemented

$000A

$000B Unimplemented

Data Direction Register A

(DDRA)

Data Direction Register B

(DDRB)

Data Direction Register D

(DDRD)

Port E Data Register

(PTE)

Port D Control Register

(PDCR)

Read:

Write:

Reset: Unaffected by reset

Read:

Write:

Reset:00000000

Read:

Write:

Reset:00000000

Read:

Write:

Read:

Write:

Reset:00000000

Read:

Write:

Reset: Unaffected by reset

Read:

Write:

Write:

Reset:

Read:

Write:

PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

PTE1 PTE0

SLOWD7 SLOWD6 PTDPU7 PTDPU6

00000000

$000C

Data Direction Register E

(DDRE)

Port A Input Pull-up

$000D

Enable Register

(PTAPUE)

PTA7 Input Pull-up

$000E

Enable Register

(PTA7PUE)

$000F

↓

$0012

U = Unaffected X = Indeterminate

Unimplemented

Read:

Write:

Reset:00000000

Read:

PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset:

Read:

PTAPUE7

Write:

Reset:

Read:

Write:

00000000

= Unimplemented R = Reserved

DDRE1 DDRE0

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 27

Memory

Addr.Register Name Bit 7654321Bit 0

$0013

$0014

$0015

$0016 SCI Status Register 1 (SCS1)

$0017 SCI Status Register 2 (SCS2)

$0018

$0019

SCI Control Register 1

(SCC1)

SCI Control Register 2

(SCC2)

SCI Control Register 3

(SCC3)

SCI Data Register

(SCDR)

SCI Baud Rate Register

(SCBR)

Keyboard Status and

$001A

Control Register

(KBSCR)

Keyboard Interrupt

$001B

Enable Register

(KBIER)

$001C

Unimplemented

Read:

Write:

Reset:00000000

Read:

Write:

Reset:00000000

Read: R8

Write:

Reset:UU000000

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset:11000000

Read:

Write:

Reset:00000000

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

Read:

Write:

Reset:00000000

Read: 0000KEYF 0

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

SCTIE TCIE SCRIE ILIE TE RE RWU SBK

T8 DMARE DMATE ORIE NEIE FEIE PEIE

BKF RPF

SCP1 SCP0 R SCR2 SCR1 SCR0

ACKK

00000000

IMASKK MODEK

KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

00000000

IRQ Status and Control

$001D

$001E

$001F

† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.

Configuration Register 2

Configuration Register 1

(INTSCR)

(CONFIG2)

(CONFIG1)

TIM1 Status and Control

$0020

(T1SC)

TIM1 Counter Register

$0021

(T1CNTH)

U = Unaffected X = Indeterminate

Read:0000IRQF0

Write:

Reset:00000000

Read:

IRQPUDRRLVIT1LVIT0RR

Write:

†

Reset:0000*0*000

Read:

Write:

†

Reset:00000000

Read: TOF

Write: 0 TRST

Reset:

COPRS R R LVID R SSREC STOP COPD

TOIE TSTOP

00100000

Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

High

Write:

Reset:

00000000

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

ACK

IMASK MODE

STOP_

ICLKDIS

PS2 PS1 PS0

28 Freescale Semiconductor

Monitor ROM

Addr.Register Name Bit 7654321Bit 0

TIM1 Counter Register

$0022

(T1CNTL)

TIM Counter Modulo

$0023

(TMODH)

TIM1 Counter Modulo

$0024

(T1MODL)

TIM1 Channel 0 Status

$0025

and Control Register

(T1SC0)

TIM1 Channel 0

$0026

(T1CH0H)

TIM1 Channel 0

$0027

(T1CH0L)

TIM1 Channel 1 Status

$0028

and Control Register

(T1SC1)

TIM1 Channel 1

$0029

(T1CH1H)

TIM1 Channel 1

$002A

(T1CH1L)

$002B

↓

$002F

Unimplemented

TIM2 Status and Control

$0030

(T2SC)

TIM2 Counter Register

$0031

(T2CNTH)

TIM2 Counter Register

$0032

(T2CNTL)

TIM2 Counter Modulo

$0033

(T2MODH)

TIM2 Counter Modulo

$0034

(T2MODL)

U = Unaffected X = Indeterminate

Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Write:

Low

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read: CH0F

Write: 0

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read: CH1F

Write: 0

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Read: TOF

Write: 0 TRST

Reset:

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11111111

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Indeterminate after reset

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Indeterminate after reset

CH1IE

00000000

MS1A ELS1B ELS1A TOV1 CH1MAX

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Indeterminate after reset

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Indeterminate after reset

TOIE TSTOP

00100000

PS2 PS1 PS0

Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

High

Write:

Reset:

00000000

Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Low

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11111111

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 29

Memory

Addr.Register Name Bit 7654321Bit 0

Read: CH0F

Write: 0

Reset:

Read:

Write:

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Reset:

Read:

Write:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reset:

Read: CH1F

Write: 0

Reset:

Read:

Write:

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Reset:

Read:

Write:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reset:

Read:

Write:

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Indeterminate after reset

CH1IE

MS1A ELS1B ELS1A TOV1 CH1MAX

Indeterminate after reset

$0035

$0036

$0037

$0038

$0039

$003A

$003B

TIM2 Channel 0 Status

and Control Register

(T2SC0)

TIM2 Channel 0

(T2CH0H)

TIM2 Channel 0

(T2CH0L)

TIM2 Channel 1 Status

and Control Register

(T2SC1)

TIM2 Channel 1

(T2CH1H)

TIM2 Channel 1

(T2CH1L)

Unimplemented

ADC Status and Control

$003C

$003D

$003E

$003F

$FE00 Break Status Register (BSR)

$FE01 Reset Status Register (RSR)

$FE02 Reserved

$FE03

U = Unaffected X = Indeterminate

ADC Data Register

ADC Input Clock Register

Note: Writing a logic 0 clears SBSW.

Break Flag Control

(ADSCR)

(ADICLK)

Unimplemented

(BFCR)

Read: COCO

Write:

Reset:00011111

Read:AD7AD6AD5AD4AD3AD2AD1AD0

Write:

(ADR)

Reset: Indeterminate after reset

Read:

Write:

Reset:00000000

Read:

Write:

Read:

Write: See note

Reset: 0

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

Read:

Write:

Read:

Write:

Reset: 0

ADIV2 ADIV1 ADIV0

BCFERRRRRRR

AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

00000

RRRRRR

RRRRRRRR

= Unimplemented R = Reserved

SBSW

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

30 Freescale Semiconductor

Monitor ROM

Addr.Register Name Bit 7654321Bit 0

$FE04

$FE05

$FE06

Interrupt Status Register 1

Interrupt Status Register 2

Interrupt Status Register 3

$FE07 Reserved

Read: IF6 IF5 IF4 IF3 0 IF1 0 0

Write:RRRRRRRR

(INT1)

Reset:00000000

Read: IF14 IF13 IF12 IF11 0 0 IF8 IF7

Write:RRRRRRRR

(INT2)

Reset:00000000

Read:0000000IF15

Write:RRRRRRRR

(INT3)

Reset:00000000

Read:

Write:

RRRRRRRR

Write:

Reset:00000000

Read:

Write:

$FE08

$FE09

FLASH Control Register

↓

(FLCR)

Reserved

$FE0B

Read:

Write:

Reset:00000000

Read:

Write:

Reset:00000000

Read:

Write:

BRKE BRKA

Reset:00000000

Read:

Write:

Reset: Unaffected by reset; $FF when blank

Read:

Write:

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

OSCSELRRRRRRR

Reset: Unaffected by reset; $FF when blank

$FE0C

$FE0D

$FE0E

$FFCF

$FFD0

Break Address High

(BRKH)

Break Address low

(BRKL)

Break Status and Control

(BRKSCR)

FLASH Block Protect

(FLBPR)

Mask Option Register

(MOR)

# Non-volatile FLASH registers; write by programming.

Read: Low byte of reset vector

Write: Writing clears COP counter (any value)

Reset: Unaffected by reset

$FFFF

COP Control Register

(COPCTL)

U = Unaffected X = Indeterminate

HVEN MASS ERASE PGM

RRRRRRRR

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

000000

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 31

Memory

Table 2-1. Vector Addresses

Vector Priority INT Flag Address Vector

Lowest

—

$FFD0

↓

Not Used

$FFDD

$FFDE ADC Conversion Complete Vector (High)

IF15

IF14

IF13

$FFDF ADC Conversion Complete Vector (Low)

$FFE0 Keyboard Interrupt Vector (High)

$FFE1 Keyboard Interrupt Vector (Low)

$FFE2 SCI Transmit Vector (High)

$FFE3 SCI Transmit Vector (Low)

$FFE4 SCI Receive Vector (High)

IF12

IF11

$FFE5 SCI Receive Vector (Low)

$FFE6 SCI Error Vector (High)

$FFE7 SCI Error Vector (Low)

IF10

↓

— Not Used

IF9

$FFEC TIM2 Overflow Vector (High)

IF8

IF7

IF6

$FFED TIM2 Overflow Vector (Low)

$FFEE TIM2 Channel 1 Vector (High)

$FFEF TIM2 Channel 1 Vector (Low)

$FFF0 TIM2 Channel 0 Vector (High)

$FFF1 TIM2 Channel 0 Vector (Low)

$FFF2 TIM1 Overflow Vector (High)

IF5

IF4

IF3

$FFF3 TIM1 Overflow Vector (Low)

$FFF4 TIM1 Channel 1 Vector (High)

$FFF5 TIM1 Channel 1 Vector (Low)

$FFF6 TIM1 Channel 0 Vector (High)

$FFF7 TIM1 Channel 0 Vector (Low)

IF2 — Not Used

IF1

$FFFA IRQ

Vector (High)

$FFFB IRQ Vector (Low)

$FFFC SWI Vector (High)

—

$FFFD SWI Vector (Low)

$FFFE Reset Vector (High)

—

$FFFF Reset Vector (Low)

Highest

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

32 Freescale Semiconductor

Random-Access Memory (RAM)

2.4 Random-Access Memory (RAM)

Addresses $0060 through $015F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.

NOTE

For correct operation, the stack pointer must point only to RAM locations.

Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.

NOTE

For M6805 compatibility, the H register is not stacked.

During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.

NOTE

Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.

2.5 FLASH Memory

This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.

2.6 Functional Description

The FLASH memory consists of an array of 8,192 bytes for user memory plus a block of 36 bytes for user interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory page size is defined as 64 bytes, and is the minimum size that can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR).

The address ranges for the FLASH memory are:

• $DC00–$FBFF; user memory; 12,288 bytes

• $FFDC–$FFFF; user interrupt vectors; 36 bytes

Programming tools are available from Motorola. Contact your local Motorola representative for more information.

NOTE

A security feature prevents viewing of the FLASH contents.

(1)

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 33

Memory

2.7 FLASH Control Register

The FLASH control register (FCLR) controls FLASH program and erase operations.

Address: $FE08

Bit 7654321Bit 0

Write:

Reset:00000000

Figure 2-3. FLASH Control Register (FLCR)

HVEN — High Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed.

1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control Bit

This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set.

1 = Mass erase operation selected 0 = Page erase operation selected

HVEN MASS ERASE PGM

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time.

1 = Erase operation selected 0 = Erase operation not selected

PGM — Program Control Bit

This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.

1 = Program operation selected 0 = Program operation not selected

2.8 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 36-byte user interrupt vectors area also forms a page. Any page within the 8,192 bytes user memory area ($DC00–$FBFF) can be erased alone.

The 36-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page.

1. Set the ERASE bit and clear the MASS bit in the FLASH control register.

2. Read the FLASH block protect register.

3. Write any data to any FLASH address within the page address range desired.

4. Wait for a time, t

5. Set the HVEN bit.

6. Wait for a time t

nvs

erase

(10µs).

(4ms).

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34 Freescale Semiconductor

FLASH Mass Erase Operation

7. Clear the ERASE bit.

8. Wait for a time, t

nvh

(5µs).

9. Clear the HVEN bit.

10. After time, t

(1µs), the memory can be accessed in read mode again.

rcv

NOTE

Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.

2.9 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory:

1. Set both the ERASE bit and the MASS bit in the FLASH control register.

2. Read the FLASH block protect register.

3. Write any data to any FLASH location within the FLASH memory address range.

4. Wait for a time, t

5. Set the HVEN bit.

6. Wait for a time t

7. Clear the ERASE bit.

8. Wait for a time, t

9. Clear the HVEN bit.

10. After time, t

rcv

(10µs).

nvs

(4ms).

merase

(100µs).

nvh1

(1µs), the memory can be accessed in read mode again.

NOTE

2.10 FLASH Program Operation

Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of FLASH memory: (Figure 2-4 shows a flowchart of the programming algorithm.)

1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming.

2. Read the FLASH block protect register.

3. Write any data to any FLASH location within the address range of the row to be programmed.

4. Wait for a time, t

5. Set the HVEN bit.

6. Wait for a time, t

7. Write data to the FLASH address to be programmed.

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Freescale Semiconductor 35

(10µs).

nvs

(5µs).

pgs

Memory

8. Wait for time, t

prog

(30µs).

9. Repeat steps 7 and 8 until all bytes within the row are programmed.

10. Clear the PGM bit.

11. Wait for time, t

nvh

(5µs).

12. Clear the HVEN bit.

13. After time, t

(1µs), the memory can be accessed in read mode again.

rcv

This program sequence is repeated throughout the memory until all data is programmed.

NOTE

The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 7 to step 10), must not exceed the maximum programming time, t

max.

prog

NOTE

Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.

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36 Freescale Semiconductor

FLASH Program Operation

Algorithm for programming a row (32 bytes) of FLASH memory

Read the FLASH block protect register

Write any data to any FLASH location

Set PGM bit

within the address range of the row to be programmed

Wait for a time, t

Set HVEN bit

Wait for a time, t

Write data to the FLASH address

to be programmed

nvs

pgs

Wait for a time, t

Completed

programming

this row?

NOTE: The time between each FLASH address change (step 7 to step 7), or

the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, t

prog

max.

This row program algorithm assumes the row/s to be programmed are initially erased.

prog

Clear PGM bit

Wait for a time, t

Clear HVEN bit

Wait for a time, t

nvh

rcv

End of programming

Figure 2-4. FLASH Programming Flowchart

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Memory

2.11 FLASH Block Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations.

NOTE

In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit

When the FLBPR is program with all 0’s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.

When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in

2.12 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any

erase or program of the FLBPR or the protected block of FLASH memory is prohibited. The FLBPR itself can be erased or programmed only with an external voltage, V also allows entry from reset into the monitor mode.

, present on the IRQ pin. This voltage

TST

2.12 FLASH Block Protect Register

The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory.

Address: $FFCF

Bit 7654321Bit 0

Read:

Write:

Reset: Unaffected by reset; $FF when blank

Non-volatile FLASH register; write by programming.

BPR[7:0] — FLASH Block Protect Bits

BPR[7:0] represent bits [13:6] of a 16-bit memory address. Bits [15:14] are logic 1’s and bits [5:0] are logic 0’s.

Start address of FLASH block protect 1 1 000000

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Figure 2-5. FLASH Block Protect Register (FLBPR)

16-bit memory address

BPR[7:0]

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FLASH Block Protect Register

The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries — 64 bytes) within the FLASH memory.

Examples of protect start address:

BPR[7:0]

$00–$70 The entire FLASH memory is protected.

$71

(0111 0001)

$72

(0111 0010)

$73

(0111 0011)

and so on...

$FD

(1111 1101)

$FE

(1111 1110)

$FF The entire FLASH memory is not protected.

1. The end address of the protected range is always $FFFF.

Start of Address of Protect Range

$DC40 (1101 1100 0100 0000)

$DC80 (1101 1100 1000 0000)

$DCC0 (1101 1100 1100 0000)

$FF40 (1111 1111 0100 0000)

$FF80 (1111 1111 1000 0000)

(1)

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Freescale Semiconductor 39

Memory

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40 Freescale Semiconductor

Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR)

3.1 Introduction

This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register (MOR).

The configuration registers enable or disable these options:

• Computer operating properly module (COP)

• COP timeout period (2

• Internal oscillator during stop mode

• Low voltage inhibit (LVI) module

• LVI module voltage trip point selection

•STOP instruction

• Stop mode recovery time (32 or 4096 ICLK cycles)

• Pull-up on IRQ

The mask option register selects the oscillator option:

• Crystal or RC

13–24

or 218–24 ICLK cycles)

3.2 Functional Description

The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001E and $001F. The configuration registers may be read at anytime.

NOTE

The options except LVIT[1:0] are one-time writable by the user after each reset. The LVIT[1:0] bits are one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-1 and Figure 3-2.

The mask option register (MOR) is used to select the oscillator option for the MCU: crystal oscillator or RC oscillator. The MOR is implemented as a byte in FLASH memory. Hence, writing to the MOR requires programming the byte.

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Configuration and Mask Option Registers (CONFIG & MOR)

3.3 Configuration Register 1 (CONFIG1)

Address: $001F

Bit 7654321Bit 0

Read:

Write:

Reset:00000000

COPRS — COP Rate Select Bit

COPRS selects the COP time-out period. Reset clears COPRS. (See Chapter 14 Computer Operating Properly (COP).)

1 = COP timeout period is (2 0 = COP timeout period is (2

LVID — Low Voltage Inhibit Disable Bit

LVID disables the LVI module. Reset clears LVID. (See Chapter 15 Low Voltage Inhibit (LVI).)

1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled

COPRS R R LVID R SSREC STOP COPD

R=Reserved

Figure 3-1. Configuration Register 1 (CONFIG1)

– 24) ICLK cycles

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay.

1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles

NOTE

Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit.

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. Reset clears COPD. (See Chapter 14 Computer Operating Properly (COP).)

1 = COP module disabled 0 = COP module enabled

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42 Freescale Semiconductor

Configuration Register 2 (CONFIG2)

3.4 Configuration Register 2 (CONFIG2)

Address: $001E

Bit 7654321Bit 0

Read:

IRQPUD R R LVIT1 LVIT0 R R

Write:

Reset:000

POR:00000000

R=Reserved

One-time writable register after each reset. LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.

Not affected Not affected

000

Figure 3-2. Configuration Register 2 (CONFIG2)

IRQPUD — IRQ Pin Pull-Up Disable Bit

IRQPUD disconnects the internal pull-up on the IRQ

pin. 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ

pin and V

LVIT1, LVIT0 — LVI Trip Voltage Selection Bits

Detail description of trip voltage selection is given in Chapter 15 Low Voltage Inhibit (LVI).

STOP_ICLKDIS — Internal Oscillator Stop Mode Disable Bit

Setting STOP_ICLKDIS disables the internal oscillator during stop mode. When this bit is cleared, the internal oscillator continues to operate in stop mode. Reset clears this bit.

1 = Internal oscillator disabled during stop mode 0 = Internal oscillator enabled during stop mode

STOP_

ICLKDIS

3.5 Mask Option Register (MOR)

The mask option register (MOR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. This register is read after a power-on reset to determine the type of oscillator selected. (See Chapter 6 Oscillator (OSC).)

Address: $FFD0

Bit 7654321Bit 0

Read:

OSCSELRRRRRRR

Write:

Erased:11111111

Reset: Unaffected by reset

Non-volatile FLASH register; write by programming.

R=Reserved

Figure 3-3. Mask Option Register (MOR)

OSCSEL — Oscillator Select Bit

OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. This bit is unaffected by reset.

1 = Crystal oscillator 0 = RC oscillator

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Freescale Semiconductor 43

Configuration and Mask Option Registers (CONFIG & MOR)

Bits 6–0 — Should be left as logic 1’s.

NOTE

When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available.

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44 Freescale Semiconductor

Chapter 4 Central Processor Unit (CPU)

4.1 Introduction

The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

4.2 Features

• Object code fully upward-compatible with M68HC05 Family

• 16-bit stack pointer with stack manipulation instructions

• 16-Bit Index Register with X-Register Manipulation Instructions

• 8-MHz CPU Internal Bus Frequency

• 64-Kbyte Program/Data Memory Space

• 16 Addressing Modes

• Memory-to-Memory Data Moves without Using Accumulator

• Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions

• Enhanced Binary-Coded Decimal (BCD) Data Handling

• Modular Architecture with Expandable Internal Bus Definition for Extension of Addressing Range beyond 64 Kbytes

• Low-Power Stop and Wait Modes

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Freescale Semiconductor 45

Central Processor Unit (CPU)

4.3 CPU Registers

Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.

H X

V11H I NZC

ACCUMULATOR (A)

INDEX REGISTER (H:X)

STACK POINTER (SP)

PROGRAM COUNTER (PC)

CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG

ZERO FLAG

NEGATIVE FLAG

INTERRUPT MASK

HALF-CARRY FLAG

TWO’S COMPLEMENT OVERFLOW FLAG

Figure 4-1. CPU Registers

4.3.1 Accumulator

The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.

Bit 7654321Bit 0

Read:

Write:

Reset: Unaffected by reset

Figure 4-2. Accumulator (A)

4.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.

In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.

The index register can serve also as a temporary data storage location.

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CPU Registers

Bit

1413121110987654321Bit 0

Read:

Write:

Reset:00000000XXXXXXXX

X = Indeterminate

Figure 4-3. Index Register (H:X)

4.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.

Bit

1413121110987654321Bit 0

Read:

Write:

Reset:0000000011111111

Figure 4-4. Stack Pointer (SP)

NOTE

The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.

4.3.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.

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Freescale Semiconductor 47

Central Processor Unit (CPU)

Bit

1413121110987654321Bit 0

Read:

Write:

Reset: Loaded with Vector from $FFFE and $FFFF

Figure 4-5. Program Counter (PC)

4.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.

Bit 7654321Bit 0

Read:

Write:

Reset:X1 1X1XXX

V11H I NZC

X = Indeterminate

Figure 4-6. Condition Code Register (CCR)

V — Overflow Flag

The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.

1 = Overflow 0 = No overflow

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor.

1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4

I — Interrupt Mask

When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.

1 = Interrupts disabled 0 = Interrupts enabled

NOTE

To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions.

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Arithmetic/Logic Unit (ALU)

After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI).

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result.

1 = Negative result 0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00.

1 = Zero result 0 = Non-zero result

C — Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.

1 = Carry out of bit 7 0 = No carry out of bit 7

4.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set.

Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.

4.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

4.5.1 Wait Mode

The WAIT instruction:

• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

4.5.2 Stop Mode

The STOP instruction:

• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

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Central Processor Unit (CPU)

4.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:

• Loading the instruction register with the SWI instruction

• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode

The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.

A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.

4.7 Instruction Set Summary

Table 4-1 provides a summary of the M68HC08 instruction set.

4.8 Opcode Map

The opcode map is provided in Table 4-2.

Table 4-1. Instruction Set Summary

Source

Form

ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP

ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP

AIS #

opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2

AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2

Add with Carry A ← (A) + (M) + (C) RR– RRR

Add without Carry A ← (A) + (M) RR– RRR

Operation Description

CCR

VH I NZC

IMM DIR EXT IX2 IX1 IX SP1 SP2

Address

Mode

Opcode

B9 C9 D9

9EE9 9ED9

AB BB CB DB EB FB

9EEB 9EDB

ii dd hh ll ee ff ff

ff ee ff

ii dd hh ll ee ff ff

ff ee ff

Operand

2 3 4 4 3 2 4 5

Effect on

Cycles

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50 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP

ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP

ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP

BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

Logical AND A ← (A) & (M) 0 – – RR–

Arithmetic Shift Left (Same as LSL)

Arithmetic Shift Right R ––RRR

Operation Description

CCR

VH I NZC

R ––RRR

IMM DIR EXT IX2 IX1 IX SP1 SP2

DIR INH INH IX1 IX SP1

Address

Mode

B4 C4 D4

9EE4 9ED4

9E68

9E67

Opcode

Operand

ii dd hh ll ee ff ff

ff ee ff

2 3 4 4 3 2 4 5

4 1 1 4 3 5

Effect on

Cycles

DIR (b0) DIR (b1) DIR (b2)

BCLR n, opr Clear Bit n in M Mn ← 0 ––––––

BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3

BGE opr

BGT opr

BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3

BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3

BHI rel Branch if Higher PC

BHS rel

BIH rel Branch if IRQ

BIL rel Branch if IRQ

Branch if Greater Than or Equal To (Signed Operands)

Branch if Greater Than (Signed Operands)

Branch if Higher or Same (Same as BCC)

Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3

Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3

PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3

PC ← (PC) + 2 +rel ? (Z) | (N ⊕ V)=0––––––REL 92 rr 3

← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3

PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

1B 1D

dd dd dd dd dd dd dd

4 4 4 4 4 4 4

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Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP

BLE opr

BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3

BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 1 ––––––REL 91 rr 3

BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3

BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3

BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +

BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3

Bit Test (A) & (M) 0 – – RR–

Branch if Less Than or Equal To (Signed Operands)

Operation Description

PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V)=1––––––REL 93 rr 3

rel ? (I) = 1 ––––––REL 2D rr 3

CCR

VH I NZC

IMM DIR EXT IX2 IX1 IX SP1 SP2

Address

Mode

B5 C5 D5

9EE5 9ED5

Opcode

Operand

ii dd hh ll ee ff ff

ff ee ff

2 3 4 4 3 2 4 5

Effect on

Cycles

BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3

BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3

dd rr

DIR (b0) DIR (b1) DIR (b2)

BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – – R

BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3

BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 – – – – – R

BSET n,opr Set Bit n in M Mn ← 1 ––––––

DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

0B 0D

0A 0C

1A 1C

dd rr dd rr dd rr dd rr dd rr dd rr dd rr

dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr

dd dd dd dd dd dd dd dd

5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

4 4 4 4 4 4 4 4

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

52 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

BSR rel Branch to Subroutine

CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel

CLC Clear Carry Bit C ← 0 –––––0INH 98 1

CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2

CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP

CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP

Compare and Branch if Equal

Clear

Compare A with M (A) – (M) R ––RRR

Operation Description

PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

PC ← (PC) + rel

PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00

M ← $00 A ← $00 X ←

$00

H ← $00 M ← $00 M ← $00 M ← $00

CCR

Mode

9E61

5F 8C

9E6F

B1 C1 D1

9EE1 9ED1

Opcode

Operand

dd rr ii rr ii rr ff rr rr ff rr

ii dd hh ll ee ff ff

ff ee ff

5 4 4 5 4 6

3 1 1 1 3 2 4

2 3 4 4 3 2 4 5

VH I NZC

––––––REL AD rr 4

––––––

0––01–

Address

DIR IMM IMM IX1+ IX+ SP1

DIR INH INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP1 SP2

Effect on

Cycles

COM opr COMA COMX COM opr,X COM ,X COM opr,SP

CPHX #opr CPHX opr

CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP

DAA Decimal Adjust A (A)

Complement (One’s Complement)

Compare H:X with M (H:X) – (M:M + 1) R ––RRR

Compare X with M (X) – (M) R ––RRR

M ← (M

A ← (A

X ← (X M ← (M M ← (M M ← (M

) = $FF – (M) ) = $FF – (M) ) = $FF – (M)

) = $FF – (M)

DIR INH

0––RR1

U–– RRRINH 72 2

INH IX1 IX SP1

IMM DIR

IMM DIR EXT IX2 IX1 IX SP1 SP2

33 43 53

63 73

9E63

6575ii ii+1dd3

hh ll

ee ff

E3 F3

9EE3

ee ff

9ED3

4 1 1 4 3 5

2 3 4 4 3 2 4 5

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 53

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel

DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP

DIV Divide

EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP

Decrement and Branch if Not Zero

Decrement

Exclusive OR M with A A ← (A ⊕ M) 0 – – RR–

Operation Description

A ← (A)–1 or M ← (M) –1 or X ← (X)–1

PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 4 + rel ? (result) ≠ 0

M ← (M) – 1

A ←

(A) – 1

X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1

A ← (H:A)/(X)

H ← Remainder

Effect on

CCR

Mode

3B 4B 5B 6B 7B

9E6B

3A 4A 5A 6A 7A

9E6A

B8 C8 D8

9EE8 9ED8

Opcode

Operand

dd rr rr rr ff rr rr ff rr

ii dd hh ll ee ff ff

ff ee ff

VH I NZC

––––––

R ––RR–

––––RRINH 52 7

Address

DIR INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP1 SP2

Cycles

5 3 3 5 4 6

4 1 1 4 3 5

2 3 4 4 3 2 4 5

INC opr INCA INCX INC opr,X INC ,X INC opr,SP

JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X

JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X

LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP

LDHX #opr LDHX opr

M ← (M) + 1

A ← (A) + 1

Increment

Jump PC ← Jump Address ––––––

PC ← (PC) + n (n = 1, 2, or 3)

Jump to Subroutine

PC ← Unconditional Address

Load A from M A ← (M) 0 – – RR–

Load H:X from M H:X ← (M:M + 1) 0 – – RR–

X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1

Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1

R ––RR–

––––––

DIR INH INH IX1 IX SP1

DIR EXT IX2 IX1 IX

IMM DIR EXT IX2 IX1 IX SP1 SP2

IMM DIR

3C 4C 5C

6C 7C

9E6C

hh ll

ee ff

EC FC

hh ll

ee ff

ED FD

hh ll

ee ff

E6 F6

9EE6

ee ff

9ED6

4555ii jjdd3

4 1 1 4 3 5

2 3 4 3 2

4 5 6 5 4

2 3 4 4 3 2 4 5

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

54 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP

LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP

LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP

MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr

Effect on

Operation Description

CCR

VH I NZC

Load X from M X ← (M) 0 – – RR–

Logical Shift Left (Same as ASL)

Logical Shift Right R ––0RR

Move

(M)

Destination

H:X ← (H:X) + 1 (IX+D, DIX+)

← (M)

Source

R ––RRR

0––RR–

IMM DIR EXT IX2 IX1 IX SP1 SP2

DIR INH INH IX1 IX SP1

DD DIX+ IMD IX+D

Address

Mode

Opcode

AE BE CE DE EE

FE 9EEE 9EDE

38 48 58 68 78

9E68

34 44 54 64 74

9E64

4E 5E 6E 7E

Operand

ii dd hh ll ee ff ff

ff ee ff

dd dd dd ii dd dd

Cycles

2 3 4 4 3 2 4 5

4 1 1 4 3 5

5 4 4 4

MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5

ii dd hh ll ee ff ff

ff ee ff

4 1 1 4 3 5

2 3 4 4 3 2 4 5

NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP

NOP No Operation None ––––––INH 9D 1

NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3

ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP

PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2

PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2

PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2

PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2

Negate (Two’s Complement)

Inclusive OR A and M A ← (A) | (M) 0 – – RR–

M ← –(M) = $00 – (M)

A ← –(A) = $00 – (A)

X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M)

R ––RRR

DIR INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP1 SP2

30 40 50 60 70

9E60

AA BA CA DA EA

FA 9EEA 9EDA

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 55

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2

PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2

ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP

ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP

RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1

RTI Return from Interrupt

Rotate Left through Carry R ––RRR

Rotate Right through Carry R ––RRR

Operation Description

SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X)

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

CCR

Mode

79 9E69

76 9E66

Opcode

Operand

VH I NZC

RRRRRRINH 80 7

Address

DIR INH INH IX1 IX SP1

4 1 1 4 3 5

Effect on

Cycles

RTS Return from Subroutine

SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP

SEC Set Carry Bit C ← 1 –––––1INH 99 1

SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2

STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP

STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – RR– DIR 35 dd 4

STOP Enable IRQ

Subtract with Carry A ← (A) – (M) – (C) R ––RRR

Store A in M M ← (A) 0 – – RR–

Pin; Stop Oscillator I ← 0; Stop Oscillator ––0–––INH 8E 1

SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL)

––––––INH 81 4

IMM DIR EXT IX2 IX1 IX SP1 SP2

DIR EXT IX2 IX1 IX SP1 SP2

C2 D2

F2 9EE2 9ED2

C7 D7

F7 9EE7 9ED7

dd hh ll ee ff ff

ff ee ff

dd hh ll ee ff ff

ff ee ff

3 4 4 3 2 4 5

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

56 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP

SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP

SWI Software Interrupt

Store X in M M ← (X) 0 – – RR–

Subtract A ← (A) – (M) R ––RRR

Operation Description

PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH)

← (SP) – 1; Push (X)

SP ← (SP) – 1; Push (A)

SP ← (SP) – 1; Push (CCR)

SP ← (SP) – 1; I ← 1

PCH ← Interrupt Vector High Byte

PCL ← Interrupt Vector Low Byte

Effect on

CCR

Mode

VH I NZC

––1–––INH 83 9

Address

DIR EXT IX2 IX1 IX SP1 SP2

IMM DIR EXT IX2 IX1 IX SP1 SP2

Opcode

BF CF DF EF

FF 9EEF 9EDF

C0 D0

F0 9EE0 9ED0

Operand

dd hh ll ee ff ff

ff ee ff

ii dd hh ll ee ff ff

ff ee ff

3 4 4 3 2 4 5

2 3 4 4 3 2 4 5

Cycles

TAP Transfer A to CCR CCR ← (A) RRRRRRINH 84 2

TAX Transfer A to X X ← (A) ––––––INH 97 1

TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1

TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP

TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2

TXA Transfer X to A A ← (X) ––––––INH 9F 1

TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2

Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – RR–

DIR INH INH IX1 IX SP1

3D 4D 5D 6D 7D

9E6D

3 1 1 3

2 4

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 57

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR IMM Immediate addressing mode INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location R Set or cleared N Negative bit — Not affected

Operation Description

⊕ Logical EXCLUSIVE OR

« Sign extend

CCR

VH I NZC

Address

Mode

Opcode

Effect on

Cycles

Operand

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

58 Freescale Semiconductor

Freescale Semiconductor 59

Bit Manipulation Branch Read-Modify-Write Control Register/Memory

DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX

01234569E6789ABCD9EDE9EEF

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

05BRSET0

3DIR

15BRCLR0

3DIR

25BRSET1

3DIR

35BRCLR1

3DIR

45BRSET2

3DIR

55BRCLR2

3DIR

65BRSET3

3DIR

75BRCLR3

3DIR

85BRSET4

3DIR

95BRCLR4

3DIR

A5BRSET5

3DIR

B5BRCLR5

3DIR

C5BRSET6

3DIR

D5BRCLR6

3DIR

E5BRSET7

3DIR

F5BRCLR7

3DIR

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment

BSET0

2DIR

BCLR0

2DIR

BSET1

2DIR

BCLR1

2DIR

BSET2

2DIR

BCLR2

2DIR

BSET3

2DIR

BCLR3

2DIR

BSET4

2DIR

BCLR4

2DIR

BSET5

2DIR

BCLR5

2DIR

BSET6

2DIR

BCLR6

2DIR

BSET7

2DIR

BCLR7

2DIR

BRA

2REL

BRN

2REL

BHI

2REL

BLS

2REL

BCC

2REL

BCS

2REL

BNE

2REL

BEQ

2REL

BHCC

2REL

BHCS

2REL

BPL

2REL

BMI

2REL

BMC

2REL

BMS

2REL

BIL

2REL

BIH

2REL

NEG

2DIR

CBEQ

3DIR

COM

2DIR

LSR

2DIR

STHX

2DIR

ROR

2DIR

ASR

2DIR

LSL

2DIR

ROL

2DIR

DEC

2DIR

DBNZ

3DIR

INC

2DIR

TST

2DIR

CLR

2DIR

NEGA

1INH

CBEQA

3IMM

MUL

1INH

COMA

1INH

LSRA

1INH

LDHX

3IMM

RORA

1INH

ASRA

1INH

LSLA

1INH

ROLA

1INH

DECA

1INH

DBNZA

2INH

INCA

1INH

TSTA

1INH

MOV

3DD

CLRA

1INH

NEGX

1INH

CBEQX

3IMM

DIV

1INH

COMX

1INH

LSRX

1INH

LDHX

2DIR

RORX

1INH

ASRX

1INH

LSLX

1INH

ROLX

1INH

DECX

1INH

DBNZX

2INH

INCX

1INH

TSTX

1INH

MOV

2DIX+

CLRX

1INH

*Pre-byte for stack pointer indexed instructions

NEG

2IX1

3IX1+

1INH

2IX1

3IMM

2IX1

3IX1

2IX1

3IMD

2IX1

CBEQ

NSA

COM

LSR

CPHX

ROR

ASR

LSL

ROL

DEC

DBNZ

INC

TST

MOV

CLR

3SP1

4SP1

3SP1

4SP1

3SP1

Table 4-2. Opcode Map

NEG

CBEQ

COM

LSR

ROR

ASR

LSL

ROL

DEC

DBNZ

INC

TST

CLR

NEG

1IX

CBEQ

2IX+

DAA

1INH

COM

1IX

LSR

1IX

CPHX

2DIR

ROR

1IX

ASR

1IX

LSL

1IX

ROL

1IX

DEC

1IX

DBNZ

2IX

INC

1IX

TST

1IX

MOV

2IX+D

CLR

1IX

Low Byte of Opcode in Hexadecimal 05BRSET0

RTI

1INH

RTS

1INH

SWI

1INH

TA P

1INH

TPA

1INH

PULA

1INH

PSHA

1INH

PULX

1INH

PSHX

1INH

PULH

1INH

PSHH

1INH

CLRH

1INH

STOP

1INH

WAIT

1INH

BGE

2REL

BLT

2REL

BGT

2REL

BLE

2REL

TXS

1INH

TSX

1INH

TA X

1INH

CLC

1INH

SEC

1INH

CLI

1INH

SEI

1INH

RSP

1INH

NOP

1INH

TXA

1INH

SUB

2IMM

CMP

2IMM

SBC

2IMM

CPX

2IMM

AND

2IMM

BIT

2IMM

LDA

2IMM

AIS

2IMM

EOR

2IMM

ADC

2IMM

ORA

2IMM

ADD

2IMM

BSR

2REL

LDX

2IMM

AIX

2IMM

SUB

2DIR

CMP

2DIR

SBC

2DIR

CPX

2DIR

AND

2DIR

BIT

2DIR

LDA

2DIR

STA

2DIR

EOR

2DIR

ADC

2DIR

ORA

2DIR

ADD

2DIR

JMP

2DIR

JSR

2DIR

LDX

2DIR

STX

2DIR

SUB

3EXT

CMP

3EXT

SBC

3EXT

CPX

3EXT

AND

3EXT

BIT

3EXT

LDA

3EXT

STA

3EXT

EOR

3EXT

ADC

3EXT

ORA

3EXT

ADD

3EXT

JMP

3EXT

JSR

3EXT

LDX

3EXT

STX

3EXT

0 High Byte of Opcode in Hexadecimal

3DIR

SUB

3IX2

CMP

3IX2

SBC

3IX2

CPX

3IX2

AND

3IX2

BIT

3IX2

LDA

3IX2

STA

3IX2

EOR

3IX2

ADC

3IX2

ORA

3IX2

ADD

3IX2

JMP

3IX2

JSR

3IX2

LDX

3IX2

STX

3IX2

Cycles

SUB

4SP2

CMP

4SP2

SBC

4SP2

CPX

4SP2

AND

4SP2

BIT

4SP2

LDA

4SP2

STA

4SP2

EOR

4SP2

ADC

4SP2

ORA

4SP2

ADD

4SP2

LDX

4SP2

STX

4SP2

SUB

2IX1

CMP

2IX1

SBC

2IX1

CPX

2IX1

AND

2IX1

BIT

2IX1

LDA

2IX1

STA

2IX1

EOR

2IX1

ADC

2IX1

ORA

2IX1

ADD

2IX1

JMP

2IX1

JSR

2IX1

LDX

2IX1

STX

2IX1

SUB

3SP1

CMP

3SP1

SBC

3SP1

CPX

3SP1

AND

3SP1

BIT

3SP1

LDA

3SP1

STA

3SP1

EOR

3SP1

ADC

3SP1

ORA

3SP1

ADD

3SP1

LDX

3SP1

STX

3SP1

SUB

1IX

CMP

1IX

SBC

1IX

CPX

1IX

AND

1IX

BIT

1IX

LDA

1IX

STA

1IX

EOR

1IX

ADC

1IX

ORA

1IX

ADD

1IX

JMP

1IX

JSR

1IX

LDX

1IX

STX

1IX

Opcode Map

Central Processor Unit (CPU)

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60 Freescale Semiconductor

Chapter 5 System Integration Module (SIM)

5.1 Introduction

This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing.

The SIM is responsible for:

• Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control

• Master reset control, including power-on reset (POR) and COP timeout

• Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation

• CPU enable/disable timing

• Modular architecture expandable to 128 interrupt sources

Table 5-1 shows the internal signal names used in this section.

Table 5-1. Signal Name Conventions

Signal Name Description

ICLK Internal oscillator clock

OSCOUT

IAB Internal address bus

IDB Internal data bus

PORRST Signal from the power-on reset module to the SIM

IRST Internal reset signal

R/W

The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)

Read/write signal

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Freescale Semiconductor 61

System Integration Module (SIM)

STOP/WAIT

CONTROL

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

SIMOSCEN (TO OSCILLATOR)

INTERNAL

PULL-UP

RESET

PIN LOGIC

VDD

CLOCK

CONTROL

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROL

AND PRIORITY DECODE

SIM

COUNTER

÷2

CLOCK GENERATORS

MASTER

RESET

CONTROL

RESET

COP CLOCK

ICLK (FROM OSCILLATOR)

OSCOUT (FROM OSCILLATOR)

INTERNAL CLOCKS

ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

COP TIMEOUT (FROM COP MODULE)

USB RESET (FROM USB MODULE)

INTERRUPT SOURCES

CPU INTERFACE

Figure 5-1. SIM Block Diagram

Addr.Register Name Bit 7654321Bit 0

$FE00 Break Status Register (BSR)

Read:

Write: NOTE

RRRRRR

SBSW

Reset:00000000

Note: Writing a logic 0 clears SBSW.

Read: POR PIN COP ILOP ILAD MODRST LVI 0

$FE01 Reset Status Register (RSR)

Write:

POR:10000000

$FE02 Reserved

Read:

Write:

RRRRRRRR

Reset:

Read:

Write:

BCFERRRRRRR

Reset: 0

$FE03

Break Flag Control

(BFCR)

Figure 5-2. SIM I/O Register Summary

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62 Freescale Semiconductor

SIM Bus Clock Control and Generation

Read: IF6 IF5 IF4 IF3 0 IF1 0 0

Write:RRRRRRRR

(INT1)

Reset:00000000

Read: IF14 IF13 IF12 IF11 0 0 IF8 IF7

Write:RRRRRRRR

(INT2)

Reset:00000000

Read:0000000IF15

Write:RRRRRRRR

(INT3)

Reset:00000000

= Unimplemented R = Reserved

$FE04

$FE05

$FE06

Interrupt Status Register 1

Interrupt Status Register 2

Interrupt Status Register 3

Figure 5-2. SIM I/O Register Summary

5.2 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 5-3.

From

OSCILLATOR

From

OSCILLATOR

ICLK

OSCOUT

SIM COUNTER

÷ 2

GENERATORS

BUS CLOCK

OSCOUT is OSC frequency divided by 2

SIM

Figure 5-3. SIM Clock Signals

5.2.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency divided by four.

5.2.2 Clock Start-Up from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeout has completed. The RST

pin is driven low by the SIM during this entire period. The IBUS clocks

start upon completion of the timeout.

5.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 ICLK cycles. (See 5.6.2 Stop Mode.)

In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

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Freescale Semiconductor 63

System Integration Module (SIM)

5.3 Reset and System Initialization

The MCU has these reset sources:

• Power-on reset module (POR)

• External reset pin (RST

• Computer operating properly module (COP)

• Low-voltage inhibit module (LVI)

• Illegal opcode

• Illegal address

All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in Monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states.

An internal reset clears the SIM counter (see 5.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 5.7 SIM Registers.)

5.3.1 External Pin Reset

The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST of 67 ICLK cycles, assuming that the POR was not the source of the reset. See Table 5-2 for details.

Figure 5-4 shows the relative timing.

)

is held low for a minimum

Table 5-2. PIN Bit Set Timing

Reset Type Number of Cycles Required to Set PIN

POR 4163 (4096 + 64 + 3)

All others 67 (64 + 3)

RST

IAB

VECT H VECT L

Figure 5-4. External Reset Timing

5.3.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (Figure 5-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR. (See Figure 5-6 . Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096 ICLK cycles during which the SIM forces the RST from the falling edge of RST

shown in Figure 5-5.

pin low. The internal reset signal then follows the sequence

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64 Freescale Semiconductor

IRST

Reset and System Initialization

RST

ICLK

IAB

RST PULLED LOW BY MCU

32 CYCLES 32 CYCLES

VECTOR HIGH

Figure 5-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

COPRST

POR

LVI

INTERNAL RESET

Figure 5-6. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.

5.3.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST

) is held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.

At power-on, the following events occur:

• A POR pulse is generated.

• The internal reset signal is asserted.

• The SIM enables OSCOUT.

• Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization of the oscillator.

•The RST

pin is driven low during the oscillator stabilization time.

• The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.

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Freescale Semiconductor 65

System Integration Module (SIM)

OSC1

PORRST

4096

CYCLES

ICLK

OSCOUT

RST

IAB

CYCLES

$FFFE $FFFF

Figure 5-7. POR Recovery

5.3.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST

pin for all internal reset sources.

To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every (2

– 24) ICLK cycles, drives the COP counter. The COP should be serviced as soon as

possible out of reset to guarantee the maximum amount of time before the first time-out.

The COP module is disabled if the RST

pin or the IRQ pin is held at V

while the MCU is in monitor

TST

mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST external noise. During a break state, V

or the IRQ pin. This prevents the COP from becoming disabled as a result of

on the RST pin disables the COP module.

TST

5.3.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset.

If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST

pin for all

internal reset sources.

5.3.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST

pin for all internal reset sources.

5.3.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when the V trip voltage V

66 Freescale Semiconductor

. The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is

TRIP

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

voltage falls to the LVI

SIM Counter

held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST

pin for all internal reset sources.

5.4 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of ICLK.

5.4.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.

5.4.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32 ICLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1).

5.4.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See 5.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 5.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)

5.5 Exception Control

Normal, sequential program execution can be changed in three different ways:

• Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI)

• Reset

• Break interrupts

5.5.1 Interrupts

An interrupt temporarily changes the sequence of program execution to respond to a particular event.

Figure 5-8 flow charts the handling of system interrupts.

Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared).

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Freescale Semiconductor 67

System Integration Module (SIM)

FROM RESET

BREAK INTERRUPT?

YES

INTERRUPT?

(As many interrupts as exist on chip)

I BIT SET?

IRQ

TIMER 1

YES

STACK CPU REGISTERS.

LOAD PC WITH INTERRUPT VECTOR.

SET I BIT.

FETCH NEXT

INSTRUCTION

SWI

INSTRUCTION?

RTI

INSTRUCTION?

YES

UNSTACK CPU REGISTERS.

EXECUTE INSTRUCTION.

Figure 5-8. Interrupt Processing

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68 Freescale Semiconductor

Exception Control

At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows interrupt entry timing.

Figure 5-10 shows interrupt recovery timing.

MODULE

INTERRUPT

I BIT

IAB

IDB

R/W

MODULE

INTERRUPT

I BIT

IAB

IDB

R/W

DUMMY

SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR

DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE

Figure 5-9

SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1

CCR A X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND

. Interrupt Entry

Figure 5-10. Interrupt Recovery

5.5.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 5-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.

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Freescale Semiconductor 69

System Integration Module (SIM)

CLI

BACKGROUND ROUTINE#$FF

INT1

INT2

LDA

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

PULH

RTI

Figure 5-11. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.

NOTE

To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.

5.5.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.

NOTE

A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does.

5.5.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 5-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.

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70 Freescale Semiconductor

Table 5-3. Interrupt Sources

Exception Control

Priority Source Flag

Highest Reset — — — $FFFE–$FFFF

SWI Instruction — — — $FFFC–$FFFD

Pin IRQF IMASK IF1 $FFFA–$FFFB

IRQ

Timer 1 Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7

Timer 1 Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5

Timer 1 Overflow Interrupt TOF TOIE IF5 $FFF2–$FFF3

Timer 2 Channel 0 Interrupt CH0F CH0IE IF6 $FFF0–$FFF1

Timer 2 Channel 1 Interrupt CH1F CH1IE IF7 $FFEE–$FFEF

Timer 2 Overflow Interrupt TOF TOIE IF8 $FFEC–$FFED

SCI Error

SCI Receive

SCI Transmit

Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1

Lowest ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF

NF FE PE

SCRF

IDLE

SCTE

Mask

ORIE NEIE

FEIE

PEIE

SCRIE

ILIE

SCTIE

TCIE

(1)

INT Flag Vector Address

IF11 $FFE6–$FFE7

IF12 $FFE4–$FFE5

IF13 $FFE2–$FFE3

1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.

5.5.2.1 Interrupt Status Register 1

Address: $FE04

Bit 7654321Bit 0

Read: IF6 IF5 IF4 IF3 0 IF1 0 0

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 5-12. Interrupt Status Register 1 (INT1)

IF1, IF3 to IF6 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present 0 = No interrupt request present

Bit 0, 1, and 3 — Always read 0

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 71

System Integration Module (SIM)

5.5.2.2 Interrupt Status Register 2

Address: $FE05

Bit 7654321Bit 0

Read: IF14 IF13 IF12 IF11 0 0 IF8 IF7

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 5-13. Interrupt Status Register 2 (INT2)

IF7, IF8, IF11 to F14 — Interrupt Flags

This flag indicates the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present 0 = No interrupt request present

Bit 2 and 3 — Always read 0

5.5.2.3 Interrupt Status Register 3

Address: $FE06

Bit 7654321Bit 0

Read:0000000IF15

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 5-14. Interrupt Status Register 3 (INT3)

IF15 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present 0 = No interrupt request present

Bit 1 to 7 — Always read 0

5.5.3 Reset

All reset sources always have equal and highest priority and cannot be arbitrated.

5.5.4 Break Interrupts

The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 16 Break Module (BREAK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.

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72 Freescale Semiconductor

Low-Power Modes

5.5.5 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR).

Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.

5.6 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.

5.6.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 5-15 shows the timing for wait mode entry.

A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option register is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode.

WAIT ADDR

IDB

R/W

NOTE: Previous data can be operand data or the WAIT opcode, depending on the

PREVIOUS DATA NEXT OPCODE SAME

last instruction.

Figure 5-15. Wait Mode Entry Timing

WAIT ADDR + 1 SAME SAMEIAB

SAME

Figure 5-16 and Figure 5-17 show the timing for WAIT recovery.

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Freescale Semiconductor 73

System Integration Module (SIM)

IAB

IDB

EXITSTOPWAIT

NOTE: EXITSTOPWAIT =

Figure 5-16. Wait Recovery from Interrupt or Break

IAB

IDB

RST

ICLK

$A6

$6E0B

$A6 $A6

Figure 5-17. Wait Recovery from Internal Reset

$6E0C$6E0B $00FF $00FE $00FD $00FC

$A6 $A6 $01 $0B $6E$A6

RST pin OR CPU interrupt OR break interrupt

Cycles

RST VCT H RST VCT L

5.6.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the oscillator signals (OSCOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode.

NOTE

External crystal applications should use the full stop recovery time by clearing the SSREC bit.

A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR).

The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 5-18 shows stop mode entry timing.

NOTE

To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.

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74 Freescale Semiconductor

CPUSTOP

SIM Registers

ICLK

INT/BREAK

IAB

STOP ADDR

IDB

R/W

NOTE: Previous data can be operand data or the STOP opcode, depending on the last

instruction.

PREVIOUS DATA NEXT OPCODE SAME

STOP ADDR + 1 SAME SAMEIAB

SAME

Figure 5-18. Stop Mode Entry Timing

STOP RECOVERY PERIOD

STOP +1

STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3

Figure 5-19. Stop Mode Recovery from Interrupt or Break

5.7 SIM Registers

The SIM has three memory mapped registers.

• Break Status Register (BSR)

• Reset Status Register (RSR)

• Break Flag Control Register (BFCR)

5.7.1 Break Status Register (BSR)

The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.

Address: $FE00

Bit 7654321Bit 0

Read:

Write: Note

Reset:00000000

RRRRRR

R = Reserved 1. Writing a logic zero clears SBSW.

Figure 5-20. Break Status Register (BSR)

SBSW

(1)

MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1

Freescale Semiconductor 75

System Integration Module (SIM)

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt

SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit clears it.

;

This code works if the H register has been pushed onto the stack in the break

;

service routine software. This code should be executed at the end of the

;

break service routine software. HIBYTE EQU 5 LOBYTE EQU 6

; If not SBSW, do RTI

BRCLR SBSW,BSR, RETURN ;;See if wait mode or stop mode was exited

by break. TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too.

DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH

RTI

; Restore H register.

5.7.2 Reset Status Register (RSR)

This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.

Address: $FE01

Bit 7654321Bit 0

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

= Unimplemented

Figure 5-21. Reset Status Register (RSR)

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit 0 = Read of RSR

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76 Freescale Semiconductor

PIN — External Reset Bit

1 = Last reset caused by external reset pin (RST

)

0 = POR or read of RSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter 0 = POR or read of RSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode 0 = POR or read of RSR

ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of RSR

MODRST — Monitor Mode Entry Module Reset bit

1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after

POR while IRQ

= V

0 = POR or read of RSR

LVI — Low Voltage Inhibit Reset bit

1 = Last reset caused by LVI circuit 0 = POR or read of RSR

SIM Registers

5.7.3 Break Flag Control Register (BFCR)

The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.

Address: $FE03

Bit 7654321Bit 0

Read:

Write:

Reset: 0

BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set.

1 = Status bits clearable during break 0 = Status bits not clearable during break

BCFERRRRRRR

R= Reserved

Figure 5-22. Break Flag Control Register (BFCR)

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Freescale Semiconductor 77

System Integration Module (SIM)

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78 Freescale Semiconductor

Chapter 6 Oscillator (OSC)

6.1 Introduction

The oscillator module provides the reference clocks for the MCU system and bus. Two oscillators are running on the device:

Selectable oscillator — for bus clock

• Crystal oscillator (XTAL) — built-in oscillator that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1.

• RC oscillator (RC) — built-in oscillator that requires an external resistor-capacitor connection only.

The selected oscillator is used to drive the bus clock, the SIM, and other modules on the MCU. The oscillator type is selected by programming a bit FLASH memory. The RC and crystal oscillator cannot run concurrently; one is disabled while the other is selected; because the RC and XTAL circuits share the same OSC1 pin.

Non-selectable oscillator — for COP

• Internal oscillator — built-in RC oscillator that requires no external components.

This internal oscillator is used to drive the computer operating properly (COP) module and the SIM. The internal oscillator runs continuously after a POR or reset, and is always available.

6.2 Oscillator Selection

The oscillator type is selected by programming a bit in a FLASH memory location; the mask option register (MOR), at $FFD0. (See 3.5 Mask Option Register (MOR).)

NOTE

On the ROM device, the oscillator is selected by a ROM-mask layer at factory.

Address: $FFD0

Bit 7654321Bit 0

Read:

OSCSELRRRRRRR

Write:

Erased:11111111

Reset: Unaffected by reset

Non-volatile FLASH register; write by programming.

R=Reserved

Figure 6-1. Mask Option Register (MOR)

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Freescale Semiconductor 79

Oscillator (OSC)

OSCSEL — Oscillator Select Bit

OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. This bit is unaffected by reset.

1 = Crystal oscillator 0 = RC oscillator

Bits 6–0 — Should be left as logic 1’s.

NOTE

When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available.

6.2.1 XTAL Oscillator

The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source.

In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 6-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components:

•Crystal, X

• Fixed capacitor, C

• Tuning capacitor, C2 (can also be a fixed capacitor)

• Feedback resistor, R

• Series resistor, RS (optional)

From SIM

XTALCLK

SIMOSCEN

To SIMTo SIM

OSCOUT2OSCOUT

÷ 2

MCU

OSC2OSC1

RS*

*RS can be zero (shorted) when used with higher-frequency crystals.

Refer to manufacturer’s data.

See Chapter 17 for component value requirements.

Figure 6-2. XTAL Oscillator External Connections

The series resistor (R

) is included in the diagram to follow strict Pierce oscillator guidelines and may not

be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information.

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80 Freescale Semiconductor

Internal Oscillator

6.2.2 RC Oscillator

The RC oscillator circuit is designed for use with external resistor and capacitor to provide a clock source with tolerance less than 10%.

In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components:

•C

EXT

•R

EXT

To SIM

To SIMFrom SIM

OSCOUT2OSCOUT

SIMOSCEN

MCU

OSCILLATOR

OSC1

EXT

EXT-RC

RCCLK

EXT

÷ 2

RCCLK/PTA6 (OSC2)

See Chapter 17 for component value requirements.

PTA6

I/O

PTA6

PTA6EN

Figure 6-3. RC Oscillator External Connections

6.3 Internal Oscillator

The internal oscillator clock (ICLK) is a free running 50-kHz clock that requires no external components. It is used as the reference clock input to the computer operating properly (COP) module and the SIM.

The internal oscillator by default is always available and is free running after POR or reset. It can be stopped in stop mode by setting the STOP_ICLKDIS bit before executing the STOP instruction.

Figure 6-4 shows the logical representation of components of the internal oscillator circuitry.

INTERNAL

Figure 6-4. Internal Oscillator

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Freescale Semiconductor 81

Oscillator (OSC)

NOTE

The internal oscillator is a free running oscillator and is available after each POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2 (see 3.4 Configuration Register 2 (CONFIG2)).

6.4 I/O Signals

The following paragraphs describe the oscillator I/O signals.

6.4.1 Crystal Amplifier Input Pin (OSC1)

OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.

6.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6)

For the XTAL oscillator, OSC2 pin is the output of the crystal oscillator inverting amplifier.

For the RC oscillator, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of the RC oscillator, RCCLK.

Oscillator OSC2 pin function

XTAL Inverting OSC1

Controlled by PTA6EN bit in PTAPUE ($000D)

PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6/KBI6

6.4.3 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the XTAL oscillator circuit or the RC-oscillator.

6.4.4 XTAL Oscillator Clock (XTALCLK)

XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (f directly from the crystal oscillator circuit. Figure 6-2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start-up.

) and comes

XCLK

6.4.5 RC Oscillator Clock (RCCLK)

RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. Figure 6-3 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry.

6.4.6 Oscillator Out 2 (2OSCOUT)

2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module.

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82 Freescale Semiconductor

Low Power Modes

6.4.7 Oscillator Out (OSCOUT)

The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency.

6.4.8 Internal Oscillator Clock (ICLK)

ICLK is the internal oscillator output signal (typically 50-kHz), for the COP module and the SIM. Its frequency depends on the V

voltage. (See Chapter 17 Electrical Specifications for ICLK parameters.)

6.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.

6.5.1 Wait Mode

The WAIT instruction has no effect on the oscillator logic. OSCOUT, 2OSCOUT, and ICLK continues to drive to the SIM module.

6.5.2 Stop Mode

The STOP instruction disables the XTALCLK or the RCCLK output, hence, OSCOUT and 2OSCOUT are disabled.

The STOP instruction also turns off the ICLK input to the COP module if the STOP_ICLKDIS bit is set in configuration register 2 (CONFIG2). After reset, the STOP_ICLKDIS bit is clear by default and ICLK is enabled during stop mode.

6.6 Oscillator During Break Mode

The OSCOUT, 2OSCOUT, and ICLK clocks continue to be driven out when the device enters the break state.

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Freescale Semiconductor 83

Oscillator (OSC)

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84 Freescale Semiconductor

Chapter 7 Monitor ROM (MON)

7.1 Introduction

This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be achieved without use of the higher test voltage, V blank, thus reducing the hardware requirements for in-circuit programming.

7.2 Features

Features of the monitor ROM include the following:

• Normal user-mode pin functionality

• One pin dedicated to serial communication between monitor ROM and host computer

• Standard mark/space non-return-to-zero (NRZ) communication with host computer

• Execution of code in RAM or FLASH

• FLASH memory security feature

• FLASH memory programming interface

• 959 bytes monitor ROM code size

• Monitor mode entry without high voltage, V $FF)

• Standard monitor mode entry if high voltage, V

• Resident routines for FLASH programming and EEPROM emulation

(1)

, as long as vector addresses $FFFE and $FFFF are

TST

, if reset vector is blank ($FFFE and $FFFF contain

TST

, is applied to IRQ

TST

7.3 Functional Description

The monitor ROM receives and executes commands from a host computer. Figure 7-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface.

Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

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Freescale Semiconductor 85

Monitor ROM (MON)

EXT OSC (50% DUTY)

EXT OSC CONNECTION TO OSC1, WITH OSC2 UNCONNECTED, CAN REPLACE XTAL CIRCUIT.

OSC1

0.1 µF

RST

HC908JL8

1 µF

DB9

MAX232

C1+

C1–

C2+

C2–

GND

V+

V–

1 µF

TST

1 µF

74HC125

NOTES:

1. Monitor mode entry method: SW1: Position A — High voltage entry (V

Bus clock depends on SW2.

TST

)

SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)

Bus clock = OSC1 ÷ 4.

2. Affects high voltage entry to monitor mode only (SW1 at position A): SW2: Position C — Bus clock = OSC1 ÷ 4 SW2: Position D — Bus clock = OSC1 ÷ 2

5. See Table 17-4 for V

voltage level requirements.

TST

9.8304MHz

20 pF

XTAL CIRCUIT

1 k

10 k

8.5 V

(SEE NOTE 2)

20 pF

10 k

OSC1

10M

OSC2

SW1

(SEE NOTE 1)

IRQ

10 k

PTB0

10 k

SW2

PTB1

PTB3

PTB2

10 k

Figure 7-1. Monitor Mode Circuit

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86 Freescale Semiconductor

Functional Description

7.3.1 Entering Monitor Mode

Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode

may be entered after a POR.

Communication at 9600 baud will be established provided one of the following sets of conditions is met:

1. If IRQ

= V

TST

– Clock on OSC1 is 4.9125MHz –PTB3 = low

2. If IRQ

= V

TST

– Clock on OSC1 is 9.8304MHz – PTB3 = high

3. If $FFFE and $FFFF are blank (contain $FF): – Clock on OSC1 is 9.8304MHz

–IRQ

= V

Table 7-1. Monitor Mode Entry Requirements and Options

$FFFE

IRQ

TST

(2)

(1)

and

$FFFF

X 0011 4.9152MHz 2.4576MHz

X 1011 9.8304MHz 2.4576MHz

BLANK

(contain

$FF)

NOT

BLANK

PTB3

PTB2

PTB1

X X X 1 9.8304MHz 2.4576 MHz

XXXX X OSC1 ÷ 4 Enters User mode.

PTB0

OSC1 Clock

(1)

Bus Frequency Comments

High voltage entry to monitor mode. 9600 baud communication on PTB0. COP disabled.

Blank reset vector (low-voltage) entry to monitor mode. 9600 baud communication on PTB0. COP disabled.

1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit.

2. See Table 17-4 for V

If V

is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus

TST

frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with V

voltage level requirements.

TST

applied to IRQ upon

TST

monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V

is applied to IRQ. In this event, the OSCOUT frequency is equal to the

TST

2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.

Entering monitor mode with V

. (See Chapter 5 System Integration Module (SIM) for more information on modes of operation.)

RST

If entering monitor mode without high voltage on IRQ (Table 7-1 condition set 3, where applied voltage is V

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Freescale Semiconductor 87

on IRQ, the COP is disabled as long as V

TST

and reset vector being blank ($FFFE and $FFFF)

), then all port B pin requirements and conditions,

is applied to either IRQ or

TST

Monitor ROM (MON)

including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming.

Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ

or the RST.

Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ

= V

. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.

POR RESET

IS VECTOR

BLANK?

YES

MONITOR MODE

EXECUTE MONITOR

CODE

POR

TRIGGERED?

YES

NORMAL USER

MODE

Figure 7-2. Low-Voltage Monitor Mode Entry Flowchart

Enter monitor mode with the pin configuration shown above by pulling RST edge of RST

latches monitor mode. Once monitor mode is latched, the values on the specified pins can

low and then high. The rising

change.

Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate.

In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code.

Table 7-2 is a summary of the vector differences between user mode and monitor mode.

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88 Freescale Semiconductor

Table 7-2. Monitor Mode Vector Differences

Functions

Functional Description

Modes

COP

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD

Monitor Disabled

(1)

$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD

Notes:

1. If the high voltage (V its COP enable output. The COP is a mask option enabled or disabled by the COPD bit

) is removed from the IRQ pin or the RST pin, the SIM asserts

TST

in the configuration register.

When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends control to the address on the stack pointer.

7.3.2 Baud Rate

The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ

pin is at logic zero upon entry into monitor mode, the divide by ratio is 512.

Table 7-3. Monitor Baud Rate Selection

Monitor Mode

Entry By:

. When PTB3 is high, the divide by ratio is 1024. If the PTB3

TST

OSC1 Clock

Frequency

PTB3 Baud Rate

4.9152 MHz 0 9600 bps

IRQ

= V

TST

9.8304 MHz 1 9600 bps

4.9152 MHz 1 4800 bps

Blank reset vector,

= V

IRQ

9.8304 MHz X 9600 bps

4.9152 MHz X 4800 bps

7.3.3 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 7-3 and Figure 7-4.)

STOP

BIT

STOP

BIT

STOP

BIT

START

BIT

START

BIT

$A5

BREAK

START

BIT

BIT 0 BIT 1

START

BIT

START

BIT

BIT 2 BIT 3 BIT 4 BIT 6 BIT 7

BIT 5

Figure 7-3. Monitor Data Format

BIT 0 BIT 1

BIT 2 BIT 3 BIT 4 BIT 6 BIT 7

BIT 2

BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

BIT 5

Figure 7-4. Sample Monitor Waveforms

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Freescale Semiconductor 89

Monitor ROM (MON)

The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive baud rates must be identical.

7.3.4 Echoing

As shown in Figure 7-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin for error checking.

SENT TO MONITOR

ADDR. HIGHREADREAD ADDR. HIGH ADDR. LOW ADDR. LOW DATA

ECHO

RESULT

Figure 7-5. Read Transaction

Any result of a command appears after the echo of the last byte of the command.

7.3.5 Break Signal

A start bit followed by nine low bits is a break signal. (See Figure 7-6.) When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal.

MISSING STOP BIT

0 1 2 3 4 5 6 7

TWO-STOP-BIT DELAY BEFORE ZERO ECHO

0 1 2 3 4 5 6 7

Figure 7-6. Break Transaction

7.3.6 Commands

The monitor ROM uses the following commands:

• READ (read memory)

• WRITE (write memory)

• IREAD (indexed read)

• IWRITE (indexed write)

• READSP (read stack pointer)

• RUN (run user program)

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90 Freescale Semiconductor

Table 7-4. READ (Read Memory) Command

Description Read byte from memory

Operand Specifies 2-byte address in high byte:low byte order

Data Returned Returns contents of specified address

Opcode $4A

Command Sequence

SENT TO MONITOR

ADDR. HIGHREADREAD ADDR. HIGH ADDR. LOW ADDR. LOW DATA

Functional Description

ECHO

RESULT

Table 7-5. WRITE (Write Memory) Command

Description Write byte to memory

Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte

Data Returned None

Opcode $49

Command Sequence

SENT TO MONITOR

ADDR. HIGHWRITEWRITE ADDR. HIGH ADDR. LOW ADDR. LOW DATA

ECHO

DATA

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Freescale Semiconductor 91

Monitor ROM (MON)

Table 7-6. IREAD (Indexed Read) Command

Description Read next 2 bytes in memory from last address accessed

Operand Specifies 2-byte address in high byte:low byte order

Data Returned Returns contents of next two addresses

Opcode $1A

Command Sequence

SENT TO MONITOR

DATAIREADIREAD DATA

ECHO

Table 7-7. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1

Operand Specifies single data byte

Data Returned None

Opcode $19

Command Sequence

SENT TO MONITOR

DATAIWRITEIWRITE DATA

ECHO

A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map.

RESULT

NOTE

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92 Freescale Semiconductor

Table 7-8. READSP (Read Stack Pointer) Command

Description Reads stack pointer

Operand None

Data Returned Returns stack pointer in high byte:low byte order

Opcode $0C

Command Sequence

SENT TO MONITOR

SP HIGHREADSPREADSP SP LOW

Security

ECHO

Table 7-9. RUN (Run User Program) Command

Description Executes RTI instruction

Operand None

Data Returned None

Opcode $28

Command Sequence

SENT TO MONITOR

RUNRUN

ECHO

7.4 Security

RESULT

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.

NOTE

Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.

During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTB0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 7-7.)

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Freescale Semiconductor 93

Monitor ROM (MON)

Figure 7-7. Monitor Mode Entry Timing

Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an

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94 Freescale Semiconductor

Table 7-10. Summary of ROM-Resident Routines

ROM-Resident Routines

Routine Name Routine Description Call Address

PRGRNGE Program a range of locations $FC06 15

ERARNGE Erase a page or the entire array $FCBE 9

LDRNGE Loads data from a range of locations $FF30 9

MON_PRGRNGE

MON_ERARNGE

MON_LDRNGE

EE_WRITE

EE_READ

1. The listed stack size excludes the 2 bytes used by the calling instruction, JSR.

Program a range of locations in monitor mode

Erase a page or the entire array in monitor mode

Loads data from a range of locations in monitor mode

Emulated EEPROM write. Data size ranges from 2 to 15 bytes at a time.

Emulated EEPROM read. Data size ranges from 2 to 15 bytes at a time.

$FF28 17

$FF2C 11

$FF24 11

$FD3F 24

$FDD0 16

Stack Used

(bytes)

(1)

The routines are designed to be called as stand-alone subroutines in the user program or monitor mode. The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM. The index register (H:X) is loaded with the address of the first byte of the data block (acting as a pointer), and the subroutine is called (JSR). Using the start address as a pointer, multiple data blocks can be used, any area of RAM be used. A data block has the control and data bytes in a defined order, as shown in

Figure 7-8.

During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected.

FILE_PTR

$XXXX

ADDRESS AS POINTER

START ADDRESS HIGH (ADDRH)

START ADDRESS LOW (ADDRL)

DATA

ARRAY

RAM

BUS SPEED (BUS_SPD)

DATA SIZE (DATASIZE)

DATA 0

DATA 1

DATA N

DATA

BLOCK

Figure 7-8. Data Block Format for ROM-Resident Routines

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Freescale Semiconductor 95

Monitor ROM (MON)

The control and data bytes are described below.

• Bus speed — This one byte indicates the operating bus speed of the MCU. The value of this byte should be equal to 4 times the bus speed, and should not be set to less than 4 (i.e. minimum bus speed is 1MHz).

• Data size — This one byte indicates the number of bytes in the data array that are to be manipulated. The maximum data array size is 128. Routines EE_WRITE and EE_READ are restricted to manipulate a data array between 2 to 15 bytes. Whereas routines ERARNGE and MON_ERARNGE do not manipulate a data array, thus, this data size byte has no meaning.

• Start address — These two bytes, high byte followed by low byte, indicate the start address of the FLASH memory to be manipulated.

• Data array — This data array contains data that are to be manipulated. Data in this array are programmed to FLASH memory by the programming routines: PRGRNGE, MON_PRGRNGE, EE_WRITE. For the read routines: LDRNGE, MON_LDRNGE, and EE_READ, data is read from FLASH and stored in this array.

7.5.1 PRGRNGE

PRGRNGE is used to program a range of FLASH locations with data loaded into the data array.

Table 7-11. PRGRNGE Routine

Routine Name PRGRNGE

Routine Description Program a range of locations

Calling Address $FC06

Stack Used 15 bytes

Data Block Format Bus speed (BUS_SPD)

Data size (DATASIZE) Start address high (ADDRH) Start address (ADDRL) Data 1 (DATA1)

Data N (DATAN)

The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be programmed in one routine call is 128 bytes (max. DATASIZE is 128).

ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment during programming. A check to see that all bytes in the specified range are erased is not performed by this routine prior programming. Nor does this routine do a verification after programming, so there is no return confirmation that programming was successful. User must assure that the range specified is first erased.

The coding example below is to program 32 bytes of data starting at FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block.

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ORG RAM

: FILE_PTR: BUS_SPD DS.B 1; Indicates 4x bus frequency DATASIZE DS.B 1; Data size to be programmed START_ADDR DS.W 1; FLASH start address DATAARRAY DS.B 32; Reserved data array

PRGRNGE EQU $FC06 FLASH_START EQU $EF00

ORG FLASH

INITIALISATION:

MOV #20, BUS_SPD

MOV #32, DATASIZE

LDHX #FLASH_START

STHX START_ADDR

RTS MAIN:

BSR INITIALISATION

LDHX #FILE_PTR

JSR PRGRNGE

ROM-Resident Routines

7.5.2 ERARNGE

ERARNGE is used to erase a range of locations in FLASH.

Table 7-12. ERARNGE Routine

Routine Name ERARNGE

Routine Description Erase a page or the entire array

Calling Address $FCBE

Stack Used 9 bytes

Data Block Format Bus speed (BUS_SPD)

Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL)

There are two sizes of erase ranges: a page or the entire array. The ERARNGE will erase the page (64 consecutive bytes) in FLASH specified by the address ADDRH:ADDRL. This address can be any address within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH array (mass erase). Therefore, care must be taken when calling this routine to prevent an accidental mass erase. To avoid undesirable routine return addresses after a mass erase, the ERARNGE routine should not be called from code executed from FLASH memory. Load the code into an area of RAM before calling the ERARNGE routine.

The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not used.

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Monitor ROM (MON)

The coding example below is to perform a page erase, from $EF00–$EF3F. The Initialization subroutine is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).

ERARNGE EQU $FCBE MAIN:

BSR INITIALISATION

LDHX #FILE_PTR

JSR ERARNGE

7.5.3 LDRNGE

LDRNGE is used to load the data array in RAM with data from a range of FLASH locations.

Table 7-13. LDRNGE Routine

Routine Name LDRNGE

Routine Description Loads data from a range of locations

Calling Address $FF30

Stack Used 9 bytes

Data Block Format Bus speed (BUS_SPD)

Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1

Data N

The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be retrieved in one routine call is 128 bytes. The data retrieved from FLASH is loaded into the data array in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from FLASH that was previously programmed.

The coding example below is to retrieve 32 bytes of data starting from $EF00 in FLASH. The Initialization subroutine is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).

LDRNGE EQU $FF30 MAIN:

BSR INITIALIZATION

LDHX #FILE_PTR

JSR LDRNGE

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ROM-Resident Routines

7.5.4 MON_PRGRNGE

In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into the data array.

Table 7-14. MON_PRGRNGE Routine

Routine Name MON_PRGRNGE

Routine Description Program a range of locations, in monitor mode

Calling Address $FC28

Stack Used 17 bytes

Data Block Format Bus speed

Data size Starting address (high byte) Starting address (low byte) Data 1

Data N

The MON_PRGRNGE routine is designed to be used in monitor mode. It performs the same function as the PRGRNGE routine (see 7.5.1 PRGRNGE), except that MON_PRGRNGE returns to the main program via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to the monitor code.

7.5.5 MON_ERARNGE

In monitor mode, ERARNGE is used to erase a range of locations in FLASH.

Table 7-15. MON_ERARNGE Routine

Routine Name MON_ERARNGE

Routine Description Erase a page or the entire array, in monitor mode

Calling Address $FF2C

Stack Used 11 bytes

Data Block Format Bus speed

Data size Starting address (high byte) Starting address (low byte)

The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as the ERARNGE routine (see 7.5.2 ERARNGE), except that MON_ERARNGE returns to the main program via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the monitor code.

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Monitor ROM (MON)

7.5.6 MON_LDRNGE

In monitor mode, LDRNGE is used to load the data array in RAM with data from a range of FLASH locations.

Table 7-16. ICP_LDRNGE Routine

Routine Name MON_LDRNGE

Routine Description Loads data from a range of locations, in monitor mode

Calling Address $FF24

Stack Used 11 bytes

Data Block Format Bus speed

Data size Starting address (high byte) Starting address (low byte) Data 1

Data N

The MON_LDRNGE routine is designed to be used in monitor mode. It performs the same function as the LDRNGE routine (see 7.5.3 LDRNGE), except that MON_LDRNGE returns to the main program via an SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor code.

7.5.7 EE_WRITE

EE_WRITE is used to write a set of data from the data array to FLASH.

Table 7-17. EE_WRITE Routine

Routine Name EE_WRITE

Routine Description

Calling Address $FD3F

Stack Used 24 bytes

Data Block Format Bus speed (BUS_SPD)

1. The minimum data size is 2 bytes. The maximum data size is 15 bytes.

2. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.

The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes in the data array is specified by DATASIZE. The minimum number of bytes that can be

Emulated EEPROM write. Data size ranges from 2 to 15 bytes at a time.

Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL)

Data 1

Data N

(1)

(2)

(1)

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Freescale MC68HC908JL8, MC68HC908JK8, MC68HC908KL8, MC68HC08JL8, MC68HC08JK8 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

List of Chapters

Table of Contents

Chapter 1 General Description

1.1 Introduction

1.2 Features

1.3 MCU Block Diagram

1.4 Pin Assignments

1.5 Pin Functions

Chapter 2 Memory

2.1 Introduction

2.2 I/O Section

2.3 Monitor ROM

2.4 Random-Access Memory (RAM)

2.5 FLASH Memory

2.6 Functional Description

2.7 FLASH Control Register

2.8 FLASH Page Erase Operation

2.9 FLASH Mass Erase Operation

2.10 FLASH Program Operation

2.11 FLASH Block Protection

2.12 FLASH Block Protect Register

Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR)

3.1 Introduction

3.2 Functional Description

3.3 Configuration Register 1 (CONFIG1)

3.4 Configuration Register 2 (CONFIG2)

3.5 Mask Option Register (MOR)

Chapter 4 Central Processor Unit (CPU)

4.1 Introduction

4.2 Features

4.3 CPU Registers

4.3.1 Accumulator

4.3.2 Index Register

4.3.3 Stack Pointer

4.3.4 Program Counter

4.3.5 Condition Code Register

4.4 Arithmetic/Logic Unit (ALU)

4.5 Low-Power Modes

4.5.1 Wait Mode

4.5.2 Stop Mode

4.6 CPU During Break Interrupts

4.7 Instruction Set Summary

4.8 Opcode Map

Chapter 5 System Integration Module (SIM)

5.1 Introduction

5.2 SIM Bus Clock Control and Generation

5.2.1 Bus Timing

5.2.2 Clock Start-Up from POR or LVI Reset

5.2.3 Clocks in Stop Mode and Wait Mode

5.3 Reset and System Initialization

5.3.1 External Pin Reset

5.3.2 Active Resets from Internal Sources

5.3.2.1 Power-On Reset

5.3.2.2 Computer Operating Properly (COP) Reset

5.3.2.3 Illegal Opcode Reset

5.3.2.4 Illegal Address Reset

5.3.2.5 Low-Voltage Inhibit (LVI) Reset

5.4 SIM Counter

5.4.1 SIM Counter During Power-On Reset

5.4.2 SIM Counter During Stop Mode Recovery

5.4.3 SIM Counter and Reset States

5.5 Exception Control

5.5.1 Interrupts

5.5.1.1 Hardware Interrupts

5.5.1.2 SWI Instruction

5.5.2 Interrupt Status Registers

5.5.2.1 Interrupt Status Register 1

5.5.2.2 Interrupt Status Register 2

5.5.2.3 Interrupt Status Register 3

5.5.3 Reset

5.5.4 Break Interrupts

5.5.5 Status Flag Protection in Break Mode

5.6 Low-Power Modes

5.6.1 Wait Mode

5.6.2 Stop Mode