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Freescale and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
The MC68HC908JB8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
Freescale SemiconductorGeneral Description27
Page 28
General Description
1.3 Features
Features of the MC68HC908JB8 include:
•High-performance M68HC08 architecture
•Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
•3-MHz internal bus frequency
•8,192 bytes of on-chip FLASH memory
•256 bytes of on-chip random-access memory (RAM)
•FLASH program memory security
1
•On-chip programming firmware for use with host PC computer
•Up to 37 general-purpose 3.3V input/output (I/O) pins, including:
–13 or 10 shared-function I/O pins, depending on package
–24, 8, or 2 dedicated I/O pins, depending on package
–8 keyboard interrupts on port A, on all packages
–10mA sink capability for normal LED on 4 pins
–25mA sink capability for infrared LED on 2 pins
–10mA sink capability for PS/2 connection on 2 pins
(with USB module disabled)
•16-bit, 2-channel timer interface module (TIM) with selectable
input capture, output compare, PWM capability on each channel,
and external clock input option (TCLK)
•Full Universal Serial Bus Specification 1.1 low-speed functions:
–1.5 Mbps data rate
–On-chip 3.3V regulator
–Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer
–Endpoint 1 with 8-byte transmit buffer
–Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
CPU
REGISTERS
M68HC08 CPU
ARITHMETIC/LOGIC
UNIT (ALU)
INTERNAL BUS
KEYBOARD INTERRUPT
MODULE
DDRA
PTA
PTA7/KBA7
:
PTA0/KBA0
(3)
(3)
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH MEMORY — 8,192 BYTES
USER RAM — 256 BYTES
MONITOR ROM — 976 BYTES
USER FLASH VECTORS — 16 BYTES
(1), (2)
(1), (3)
OSC1
OSC2
RST
IRQ
V
V
V
REG
(3.3 V)
DD
SS
INTERNAL VOLTAGE REGULATOR
OSCILLATOR
SYSTEM INTEGRATION
MODULE
IRQ
MODULE
POWER
TIMER INTERFACE
MODULE
BREAK
MODULE
LOW VOLTAGE INHIBIT
MODULE
POWER-ON RESET
MODULE
COMPUTER OPERATING PROPERLY
MODULE
USB
MODULE
USB ENDPOINT 0, 1, 2
LS USB
TRANSCEIVER
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pullup device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
NOTE:In 20-pin package, the PTD0 and PTD1 internal pads are bonded
together to PTD0/1 pin.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
Freescale SemiconductorGeneral Description33
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General Description
1.5.1 Power Supply Pins (VDD, VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the bypass capacitors as close to the MCU power pins as
possible. Use high-frequency-response ceramic capacitors for C
C
that require the port pins to source high current levels.
are optional bulk current bypass capacitors for use in applications
BULK
MCU
BYPASS
.
1.5.2 Voltage Regulator Out (V
V
internally for the MCU operation and the USB data driver. It is also used
to supply the voltage for the external pullup resistor required on the
USB’s D– line. The V
or larger and a 0.1 µF ceramic bypass capacitor as Figure 1-6 shows.
Place the bypass capacitors as close to the V
V
DD
C
BYPASS
0.1 µF
+
C
BULK
V
DD
NOTE: Values shown are typical values.
V
SS
Figure 1-5. Power Supply Bypassing
)
REG
is the 3.3 V output of the on-chip voltage regulator. V
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit.
V
REG
V
REG
MCU
C
REGBYPASS
0.1 µF
+
C
REGBULK
> 4.7 µF
V
SS
1.5.4 External Reset Pin (RST)
A logic zero on the RST pin forces the MCU to a known start-up state.
RST is bidirectional, allowing a reset of the entire system. It is driven low
when any internal reset source is asserted. The RST pin contains an
internal pullup device to VDD. (See Section 8. System Integration
Module (SIM).)
1.5.5 External Interrupt Pins (IRQ
IRQ is an asynchronous external interrupt pin. IRQ is also the pin to
enter monitor mode. The IRQ pin contains a software configurable pullup
device to V
(See Section 13. External Interrupt (IRQ).)
, PTE4/D–)
. PTE4/D– can be programmed to trigger the IRQ interrupt.
DD
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
Freescale SemiconductorGeneral Description35
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General Description
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0)
PTA7/KBA7–PTA0/KBA0 are general-purpose bidirectional I/O port
pins. (See Section 12. Input/Output Ports (I/O).) Each pin contains a
software configurable pullup device to V
as an input. (See 12.8 Port Options.) Each pin can also be programmed
as an external keyboard interrupt pin. (See Section 14. Keyboard
Interrupt Module (KBI).)
1.5.7 Port B (I/O) Pins (PTB7–PTB0)
PTB7–PTB0 are general-purpose bidirectional I/O port pins. Each pin
contains a software configurable pullup device to V
configured as an input. (See 12.8 Port Options.)
REG
when the pin is configured
when the pin is
REG
1.5.8 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are general-purpose bidirectional I/O port pins. (See
Section 12. Input/Output Ports (I/O).) Each pin contains a software
configurable pullup device to V
when the pin is configured as an
REG
input. (See 12.8 Port Options.)
1.5.9 Port D I/O Pins (PTD7–PTD0)
PTD7–PTD0 are general-purpose bidirectional I/O port pins; open-drain
when configured as output. (See Section 12. Input/Output Ports (I/O).)
PTD5–PTD2 are software configurable to be 10mA sink pins for direct
LED connections. PTD1–PTD0 are software configurable to be 25mA
sink pins for direct infrared LED connections. (See 12.8 Port Options.)
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1, PTE1/TCH0, PTE0/TCLK)
Port E is a 5-bit special function port that shares two of its pins with the
USB module and three of its pins with the timer interface module.
Each PTE2–PTE0 pin contains a software configurable pullup device to
When the USB module is disabled, the PTE4 and PTE3 pins are
general-purpose bidirectional I/O port pins with 10mA sink capability.
Each pin is open-drain when configured as an output; and each pin
contains a software configurable 5kΩ pullup to V
when configured as
DD
an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt.
When the USB module is enabled, the PTE4/D– and PTE3/D+ pins
become the USB module D– and D+ pins. The D– pin contains a
software configurable 1.5kΩ pullup to V
. (See Section 11. Timer
REG
Interface Module (TIM), Section 9. Universal Serial Bus Module
(USB) and Section 12. Input/Output Ports (I/O).)
Summary of the pin functions are provided in Table 1-1.
Table 1-1. Summary of Pin Functions
PIN NAMEPIN DESCRIPTIONIN/OUTVOLTAGE LEVEL
V
DD
V
SS
V
REG
RST
Power supply.IN4.0 to 5.5V
Power supply ground.OUT0V
Regulated 3.3V output from MCU.OUT
Reset input; active low.
With internal pullup to V
and schmitt trigger input.
DD
External IRQ pin; with programmable internal pullup to VDD
IRQ
and schmitt trigger input.
Used for mode entry selection.IN
OSC1Crystal oscillator input.IN
OSC2Crystal oscillator output; inverting of OSC1 signal.OUT
8-bit general-purpose I/O port.IN/OUT
PTA0/KBA0
:
PTA7/KBA7
Pins as keyboard interrupts, KBA0–KBA7.IN
Each pin has programmable internal pullup to V
REG
when
configured as input.
8-bit general-purpose I/O port.IN/OUT
PTB0–PTB7
Each pin has programmable internal pullup to V
REG
when
configured as input.
IN/OUT
IN
IN
IN
V
V
REG
(3.3V)
REG
V
DD
V
DD
to VDD+V
V
REG
V
REG
V
REG
V
REG
V
REG
V
REG
V
REG
HI
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
Freescale SemiconductorGeneral Description37
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General Description
Table 1-1. Summary of Pin Functions
PIN NAMEPIN DESCRIPTIONIN/OUTVOLTAGE LEVEL
PTC0–PTC7
PTD0–PTD7
PTE0/TCLK
PTE1/TCH0
PTE2/TCH1
8-bit general-purpose I/O port.IN/OUT
Each pin has programmable internal pullup to V
configured as input.
8-bit general-purpose I/O port;
open-drain when configured as output.
REG
when
IN
IN
OUT
PTD0–PTD1 have configurable 25mA sink for infrared LED.OUT
PTD2–PTD5 have configurable 10mA sink for LED.OUT
PTE0–PTE2 are general-purpose I/O pins.IN/OUT
PTE0–PTE2 have programmable internal pullup to V
when configured as input or output.
REG
IN/OUT
PTE0 as TCLK of timer interface module.IN
PTE1 as TCH0 of timer interface module.IN/OUT
PTE2 as TCH1 of timer interface module.IN/OUT
PTE3–PTE4 are general-purpose I/O pins;
open-drain when configured as output.
IN
OUT
V
V
V
V
REG
REG
REG
REG
V
V
V
V
V
V
V
V
V
REG
REG
REG
or V
or V
or V
REG
REG
REG
REG
REG
DD
or V
DD
DD
DD
DD
PTE3/D+
PTE4/D–
PTE3–PTE4 have programmable internal pullup to VDD
when configured as input.
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
•$FE00; break status register, BSR
•$FE01; reset status register, RSR
•$FE02; reserved
•$FE03; break flag control register, BFCR
•$FE04; interrupt status register 1, INT1
•$FE05; reserved
•$FE06; reserved
2.4 Monitor ROM
•$FE07; reserved
•$FE08; FLASH control register, FLCR
•$FE09; FLASH block protect register, FLBPR
•$FE0A; reserved
•$FE0B; reserved
•$FE0C; break Address Register High, BRKH
•$FE0D; break Address Register Low, BRKL
•$FE0E; break status and control register, BRKSCR
•$FFFF; COP control register, COPCTL
The 512 bytes at addresses $FC00–$FDFF and 464 bytes at addresses
$FE10–$FFDF are reserved ROM addresses that contain the
instructions for the monitor functions. (See Section 10. Monitor ROM
(MON).)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
Freescale SemiconductorMemory Map41
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Memory Map
Addr.Register NameBit 7654321Bit 0
$0000
$0001
$0002
$0003
$0004
* DDRA7 bit is reset by POR or LVI reset only.
$0005
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Read:
PTA7PTA6PTA5PTA4PTA3PTA2PTA1PTA0
Write:
Reset:Unaffected by reset
Read:
PTB7PTB6PTB5PTB4PTB3PTB2PTB1PTB0
Write:
Reset:Unaffected by reset
Read:
PTC7PTC6PTC5PTC4PTC3PTC2PTC1PTC0
Write:
Reset:Unaffected by reset
Read:
PTD7PTD6PTD5PTD4PTD3PTD2PTD1PTD0
Write:
Reset:Unaffected by reset
Read:
DDRA7DDRA6DDRA5DDRA4DDRA3DDRA2DDRA1DDRA0
Write:
Reset:0*0000000
Read:
DDRB7DDRB6DDRB5DDRB4DDRB3DDRB2DDRB1DDRB0
Write:
Reset:00000000
Data Direction Register C
$0006
Data Direction Register D
$0007
$0008
$0009
Port E Data Register
Data Direction Register E
(DDRC)
(DDRD)
(PTE)
(DDRE)
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:000
Write:
Reset:Unaffected by reset
Read:000
Write:
Reset:00000000
DDRC7DDRC6DDRC5DDRC4DDRC3DDRC2DDRC1DDRC0
DDRD7DDRD6DDRD5DDRD4DDRD3DDRD2DDRD1DDRD0
PTE4PTE3PTE2PTE1PTE0
DDRE4DDRE3DDRE2DDRE1DDRE0
= UnimplementedR= ReservedU = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Addresses $0040–$013F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE:For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:For M6805 Family compatibility, the H register is not stacked.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE:Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
Freescale SemiconductorFLASH Memory53
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FLASH Memory
Addr.Register NameBit 7654321Bit 0
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
$FE08
$FE09
FLASH Control Register
(FLCR)
FLASH Block Protect
Register
(FLBPR)
Figure 4-1. FLASH Memory Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 8,192 bytes for user memory
plus a small block of 16 bytes for user interrupt vectors. An erased bit
reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory is block erasable. The minimum erase block size is 512 bytes.
Program and erase operation operations are facilitated through control
bits in FLASH control register (FLCR).The address ranges for the
FLASH memory are shown as follows:
HVENMASSERASEPGM
BPR7BPR6BPR5BPR4BPR3BPR2BPR1BPR0
•$DC00–$FBFF (user memory; 8,192 bytes)
•$FFF0–$FFFF (user interrupt vectors; 16 bytes)
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE:A security feature prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address:$FE08
Bit 7654321Bit 0
FLASH Memory
FLASH Control Register
Read:0000
HVENMASSERASEPGM
Write:
Reset:00000000
Figure 4-2. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the
memory for either program or erase operation. It can only be set if
either PGM or ERASE is high and the sequence for erase or
program/verify is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
This read/write bit configures the memory for program operation. This
bit and the ERASE bit should not be set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
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FLASH Memory
4.5 FLASH Block Erase Operation
Use the following procedure to erase a block of FLASH memory. A block
consists of 512 consecutive bytes starting from addresses $X000,
$X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. Any block
within the 8,192 bytes user memory area ($DC00–$FBFF) can be
erased alone.
NOTE:The 16-byte user vectors, $FFF0–$FFFF, cannot be erased by the block
erase operation because of security reasons. Mass erase is required to
erase this block.
1.Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2.Write any data to any FLASH address within the address range of
the block to be erased.
3.Wait for a time, t
(5 µs).
nvs
4.Set the HVEN bit.
5.Wait for a time t
6.Clear the ERASE bit.
7.Wait for a time, t
8.Clear the HVEN bit.
9.After time, t
(1 µs), the memory can be accessed in read mode
rcv
again.
NOTE:Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
Use the following procedure to erase the entire FLASH memory:
1.Set both the ERASE bit and the MASS bit in the FLASH control
register.
2.Write any data to any FLASH address within the address range
$FFE0–$FFFF.
FLASH Memory
FLASH Mass Erase Operation
3.Wait for a time, t
(5 µs).
nvs
4.Set the HVEN bit.
5.Wait for a time t
me
(2 ms).
6.Clear the ERASE bit.
7.Wait for a time, t
nvh1
(100 µs).
8.Clear the HVEN bit.
9.After time, t
(1 µs), the memory can be accessed in read mode
rcv
again.
NOTE:Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
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FLASH Memory
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80 or $XXC0. The procedure for programming a row of the
FLASH memory is outlined below:
1.Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2.Write any data to any FLASH address within the address range of
the row to be programmed.
3.Wait for a time, t
(5 µs).
nvs
4.Set the HVEN bit.
5.Wait for a time, t
(10 µs).
pgs
6.Write data to the byte being programmed.
7.Wait for time, t
PROG
(20 µs).
8.Repeat step 6 and 7 until all the bytes within the row are
programmed.
9.Clear the PGM bit.
10.Wait for time, t
nvh
(5 µs).
11.Clear the HVEN bit.
12.After time, t
(1 µs), the memory can be accessed in read mode
rcv
again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE:Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t
Memory Characteristics).
Figure 4-3 shows a flowchart representation for programming the
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
Write any data to any FLASH address
Set PGM bit
within the row address range desired
3
4
5
6
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address
to be programmed
7
Wait for a time, t
nvs
pgs
PROG
Completed
programming
this row?
NOTE:
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
must not exceed the maximum programming
PROG
max.
time, t
This row program algorithm assumes the row/s
to be programmed are initially erased.
Figure 4-3. FLASH Programming Flowchart
Y
N
9
10
11
12
Clear PGM bit
Wait for a time, t
nvh
Clear HVEN bit
Wait for a time, t
rcv
End of Programming
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
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FLASH Memory
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE:When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set,
the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register.
The content of this register determine the starting location of the
protected range within the FLASH memory.
Address:$FE09
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0
BPR[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0]
are logic 0’s.
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be X000, X200, X400,
X600, X800, XA00, XC00, or XE00 within the FLASH memory.
Examples of protect start address:
BPR[7:0]Start of Address of Protect Range
$00 to $DCThe entire FLASH memory is protected.
$DE (1101 1110)$DE00 (1101 1110 0000 0000)
$E0 (1110 0000)$E000 (1110 0000 0000 0000)
$E2 (1110 0010)$E200 (1110 0010 0000 0000)
$E4 (1110 0100)$E400 (1110 0100 0000 0000)
and so on...
Note:
The end address of the protected range is always $FFFF.
4.9 ROM-Resident Routines
ROM-resident routines can be called by a program running in user mode
or in monitor mode (see Section 10. Monitor ROM (MON)) for FLASH
programming, erasing, and verifying. The range of the FLASH memory
must be unprotected (see 4.8 FLASH Protection) before calling the
erase or programming routine.
Routine
Name
$FE$FFE0–$FFFF (User vectors)
$FFThe entire FLASH memory is not protected.
Table 4-1. ROM-Resident Routines
Call AddressRoutine Function
VERIFY$FC03FLASH verify routine
ERASE$FC06FLASH mass erase routine
PROGRAM$FC09FLASH program routine
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FLASH Memory
4.9.1 Variables
The ROM-resident routines use three variables: CTRLBYT, CPUSPD
and LADDR; and one data buffer. The minimum size of the data buffer
is one byte and the maximum size is 64 bytes.
CPUSPD must be set before calling the ERASE or PROGRAM routine,
and should be set to four times the value of the CPU internal bus speed
in MHz. For example: for CPU speed of 3MHz, CPUSPD should be set
to 12.
Table 4-2. ROM-Resident Routine Variables
VariableAddressDescription
CTRLBYT$0048Control byte for setting mass erase.
4.9.2 ERASE Routine
CPUSPD$0049
LADDR$004A–$004BLast FLASH address to be programmed.
DATABUF$004C–$008BData buffer for programming and verifying.
Timing adjustment for different CPU
speeds.
The ERASE routine erases the entire FLASH memory. The routine does
not check for a blank range before or after erase.
Table 4-3. ERASE Routine
RoutineERASE
Calling Address$FC06
Stack Use5 Bytes
CPUSPD — CPU speed
HX —Contains any address in the range to be
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. Bit-5 and
bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared
during any reset. Since the various options affect the operation of the
MCU, it is recommended that this register be written immediately after
reset. The configuration register is located at $001F. The configuration
register may be read at any time.
Address:$001F
Bit 7654321Bit 0
Read:00
Write:
Reset:000*0*0000
URSTDLVIDSSRECCOPRSSTOPCOPD
= Unimplemented
* URSTD and LVID bits are reset by POR or LVI reset only.
Figure 5-1. Configuration Register (CONFIG)
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU.
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI circuit
1 = Disable LVI circuit
0 = Enable LVI circuit
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
2048×OSCXCLK cycles instead of a 4096 ×OSCXCLK cycle delay.
1 = Stop mode recovery after 2048×OSCXCLK cycles
0 = Stop mode recovery after 4096×OSCXCLK cycles
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Central Processor Unit (CPU)
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
6.3 Features
•Object code fully upward-compatible with M68HC05 Family
•16-bit stack pointer with stack manipulation instructions
•16-bit index register with x-register manipulation instructions
•3-MHz CPU internal bus frequency
•64-Kbyte program/data memory space
•16 addressing modes
•Memory-to-memory data moves without using accumulator
•Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•Enhanced binary-coded decimal (BCD) data handling
•Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64-Kbytes
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6.4 CPU Registers
Central Processor Unit (CPU)
CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
6.4.1 Accumulator
7
15
HX
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7654321Bit 0
Read:
Write:
Reset:Unaffected by reset
Figure 6-2. Accumulator (A)
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Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
Bit
1413121110987654321
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Bit
0
Figure 6-3. Index Register (H:X)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
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NOTE:The location of the stack is arbitrary and may be relocated anywhere in
6.4.4 Program Counter
Central Processor Unit (CPU)
CPU Registers
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
1413121110987654321
15
Read:
Write:
Reset:Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit
0
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Central Processor Unit (CPU)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X1 1X1XXX
V11H I NZC
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
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Central Processor Unit (CPU)
CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE:To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
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Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
6.6.1 Wait Mode
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
The WAIT instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
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6.6.2 Stop Mode
The STOP instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Central Processor Unit (CPU)
CPU During Break Interrupts
•Loading the instruction register with the SWI instruction
•Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
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Test for Negative or Zero(A) – $00 or (X) – $00 or (M) – $000 – –
RR–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
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Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 9 of 9)
Effect on
Source
Form
AAccumulatornAny bit
CCarry/borrow bitoprOperand (one or two bytes)
CCRCondition code registerPCProgram counter
ddDirect address of operandPCH Program counter high byte
dd rrDirect address of operand and relative offset of branch instructionPCL Program counter low byte
DDDirect to direct addressing modeREL Relative addressing mode
DIRDirect addressing moderelRelative program counter offset byte
DIX+Direct to indexed with post increment addressing moderrRelative program counter offset byte
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 Stack pointer, 8-bit offset addressing mode
EXTExtended addressing modeSP2 Stack pointer 16-bit offset addressing mode
ffOffset byte in indexed, 8-bit offset addressingSPStack pointer
HHalf-carry bitUUndefined
HIndex register high byteVOverflow bit
hh llHigh and low bytes of operand address in extended addressingXIndex register low byte
IInterrupt maskZZero bit
iiImmediate operand byte&Logical AND
IMDImmediate source to direct destination addressing mode|Logical OR
IMMImmediate addressing mode
INHInherent addressing mode( )Contents of
IXIndexed, no offset addressing mode–( ) Negation (two’s complement)
IX+Indexed, no offset, post increment addressing mode#Immediate value
IX+DIndexed with post increment to direct addressing mode
IX1Indexed, 8-bit offset addressing mode←Loaded with
IX1+Indexed, 8-bit offset, post increment addressing mode?If
IX2Indexed, 16-bit offset addressing mode:Concatenated with
MMemory locationRSet or cleared
NNegative bit—Not affected
The oscillator circuit is designed for use with crystals or ceramic
resonators. The oscillator circuit generates the crystal clock signal. The
crystal oscillator output signal passes through the clock doubler.
OSCXCLK is the output signal of the clock doubler. OSCXCLK is divided
by two before being passed on to the system integration module (SIM)
for bus clock generation.
Figure 7-1 shows the structure of the oscillator. The oscillator requires
various external components.
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Oscillator (OSC)
7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external
components. The crystal oscillator is normally connected in a Pierce
oscillator configuration, as shown in Figure 7-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
•Crystal, X
•Fixed capacitor, C
1
1
•Tuning capacitor, C2 (can also be a fixed capacitor)
•Feedback resistor, R
B
•Series resistor, RS (optional)
FROM SIM
SIMOSCEN
MCU
OSC1OSC2
TO USBTO SIM
CLOCK
DOUBLER
R
B
OSCXCLK
TO SIM
÷ 2
OSCOUT
RS*
X1
C1C2
* RS can be 0 (shorted) when used with
higher frequency crystals.
Refer to manufacturer’s data.
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
7.4 I/O Signals
The following paragraphs describe the oscillator input/output (I/O)
signals.
7.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
Oscillator (OSC)
I/O Signals
7.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator.
7.4.4 External Clock Source (OSCXCLK)
The crystal oscillator output signal passes through the clock doubler and
OSCXCLK is the output signal of the clock doubler. OSCXCLK runs at
twice the speed of the crystal (f
relation of OSCXCLK to OSC1 and OSC2 and may not represent the
actual circuitry. The duty cycle of OSCXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and
amplitude of OSCXCLK can be unstable at startup.
). Figure 7-1 shows only the logical
XCLK
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Oscillator (OSC)
7.4.5 Oscillator Out (OSCOUT)
The clock driven to the SIM is OSCXCLK. This signal is driven to the SIM
for generation of the bus clocks used by the CPU and other modules on
the MCU. OSCOUT will be divided again in the SIM and results in the
internal bus frequency being one forth of the OSCXCLK frequency or
one half of the crystal frequency.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
7.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. OSCXCLK
continues to drive to the SIM module.
7.5.2 Stop Mode
The STOP instruction disables the OSCXCLK output.
7.6 Oscillator During Break Mode
The oscillator continues to drive OSCXCLK when the chip enters the
break state.
This section describes the system integration module (SIM), which
supports up to 8 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. The SIM is a system state
controller that coordinates CPU and exception timing. A block diagram
of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM
I/O registers. The SIM is responsible for:
•Bus clock generation and control for CPU and peripherals
–Stop/wait/reset/break entry and recovery
–Internal clock control
•Master reset control, including power-on reset (POR) and COP
timeout
•Interrupt control:
–Acknowledge timing
–Arbitration control timing
–Vector address generation
•CPU enable/disable timing
•Modular architecture expandable to 128 interrupt sources
SIM to generate the internal bus clocks.
(Bus clock = OSCXCLK ÷ 4 = f
OSC
÷ 2)
Read/write signal
Page 96
System Integration Module (SIM)
Addr.Register NameBit 7654321Bit 0
$FE00Break Status Register
Note: Writing a logic 0 clears SBSW.
$FE01Reset Status Register
$FE02Reserved Read:
$FE03Break Flag Control
Register
(BFCR)
$FE04 Interrupt Status Register 1
Read:
(BSR)
Write:See note
Reset:0
Read:PORPINCOPILOPILADUSBLVI0
(RSR)
Write:
POR:10000000
Write:
Read:
Write:
Reset:0
Read:IF6IF5IF4IF3IF2IF100
(INT1)
Write:RRRRRRRR
Reset:00000000
RRRRRR
RRRRRRRR
BCFERRRRRRR
SBSW
Figure 8-2. SIM I/O Register Summary
R
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 8-3.
In user mode, the internal bus frequency is the oscillator frequency
divided by two.
8.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 OSCXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
8.3.3 Clocks in Stop Mode and Wait Mode
System Integration Module (SIM)
Reset and System Initialization
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 2048 OSCXCLK cycles. (See 8.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
8.4 Reset and System Initialization
The MCU has these reset sources:
•Power-on reset module (POR)
•External reset pin (RST
•Computer operating properly module (COP)
•Illegal opcode
)
•Illegal address
•Universal serial bus module (USB)
•Low-voltage inhibit module (LVI)
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All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 8.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 8.8 SIM Registers.)
8.4.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 OSCXCLK cycles, assuming that neither the POR nor the LVI was the
source of the reset. See Table 8-2 for details. Figure 8-4 shows the
relative timing.
All internal reset sources actively pull the RST pin low for 32 OSCXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. (See Figure
8-5.) An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, the USB module or POR. (See Figure 8-6 .
Sources of Internal Reset.)
NOTE:For LVI or POR resets, the SIM cycles through 4096 OSCXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST
Figure 8-5.
IRST
System Integration Module (SIM)
Reset and System Initialization
shown in
RST
OSCXCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES32 CYCLES
VECTOR HIGH
Figure 8-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
USB
INTERNAL RESET
Figure 8-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3Technical Data
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
•A POR pulse is generated.
•The internal reset signal is asserted.
•The SIM enables the oscillator to drive OSCXCLK.
•Internal clocks to the CPU and modules are held inactive for 4096
OSCXCLK cycles to allow stabilization of the oscillator.
•The RST pin is driven low during the oscillator stabilization time.
•The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.