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The MC68HC908JB16 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorGeneral Description29
General Description
1.3 Features
Features of the MC68HC908JB16 MCU include the following:
•High-performance M68HC08 architecture
•Fully upward-compatible object code with M6805, M146805, and
M68HC05 families
•Low-power design; fully static with stop and wait modes
•6-MHz internal bus frequency
•16,384 bytes of on-chip FLASH memory with security1 feature
•384 bytes of on-chip random access memory (RAM)
•Up to 21 general-purpose input/output (I/O) pins, including:
–15 shared-function I/O pins
–8-bit keyboard interrupt port
–1 0mA high current drive for PS/2 connection on 2 pins
(with USB module disabled)
–1 dedicated I/O pin, with 25mA direct drive for infrared LED
(32-pin package)
–6 dedicated I/O pins, with 25mA direct drive for infrared LED
on 2 pins and 10mA direct drive for normal LED on 4 pins
(28-pin package)
•Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, PWM capability on
each channel, and external clock input option (TCLK)
•Universal Serial Bus specification 2.0 low-speed functions:
–1.5Mbps data rate
–On-chip 3.3V regulator
–Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer
–Endpoint 1 with 8-byte transmit buffer
–Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
•In-circuit programming capability using USB communication or
standard serial link on PTA0 pin
•System protection features:
–Optional computer operating properly (COP) reset
–Optional Low-voltage detection with reset
–Illegal opcode detection with reset
–Illegal address detection with reset
•Master reset pin with internal pull-up and power-on reset
•IRQ interrupt pin with internal pull-up and schmitt-trigger input
•32-pin low-profile quad flat pack (LQFP) and 28-pin small outline
integrated circuit package (SOIC)
Features of the CPU08 include the following:
•Enhanced HC05 programming model
•Extensive loop control functions
•16 addressing modes (eight more than the HC05)
•16-bit index register and stack pointer
•Memory-to-memory data transfers
•Fast 8 × 8 multiply instruction
•Fast 16/8 divide instruction
•Binary-coded decimal (BCD) instructions
•Optimization for controller applications
•Third party C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908JB16.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorGeneral Description31
32General DescriptionFreescale Semiconductor
Technical DataMC68HC908JB16 — Rev. 1.1
General Description
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
CONTROL AND STATUS REGISTERS — 64 BYTES
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
BREAK
DDRA
PTA
PTA7/KBA7
:
PTA0/KBA0
(3)
MODULE
(5)
(1), (5)
(5)
(1), (5)
(1)
OSC1
(1)
OSC2
CGMXFC1
CGMOUT1
CGMXFC2
CGMOUT2
(2)
RST
(3)
IRQ
USER FLASH MEMORY — 16,384 BYTES
USER RAM — 384 BYTES
MONITOR ROM — 1,472 BYTES
USER FLASH VECTORS — 48 BYTES
OSCILLATOR
DUAL CLOCK
GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
IRQ
MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
LOW VOLTAGE INHIBIT
MODULE
POWER-ON RESET
MODULE
COMPUTER OPERATING
PROPERLY MODULE
2-CHANNEL TIMER INTERFACE
MODULE 1
2-CHANNEL TIMER INTERFACE
MODULE 2
USB MODULE
USB ENDPOINT 0, 1, 2
LS USB
TRANSCEIVER
DDRC
DDRD
DDRE
PTC
PTD
PTE
PTC1/RxD
PTC0/TxD
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
PTE4/D–
PTE3/D+
(3)
(3)
(4), (6)
(4), (6)
(4), (6)
(4), (6)
(4), (6)
(4)
(3), (4)
(3), (4)
PTE2/T2CH01
PTE1/T1CH01
PTE0/TCLK
(3)
(3)
(3)
V
DD
V
SS
V
(3.3V)
REG
(5)
V
DDA
(5)
V
SSA0
(5)
V
REGA0
REGA1
SSA1
(3.3V)
(3.3V)
(5)
V
(5)
V
POWER AND INTERNAL
VOLTAGE REGULATORS
(1) Pins have 3V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pull-up device.
(4) Pins are open-drain when configured as output.
(5) Pins available on 32-pin package only.
(6) Pins available on 28-pin package only.
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the bypass capacitors as close to the MCU power pins as
possible. Use high-frequency-response ceramic capacitors for C
C
that require the port pins to source high current levels.
are optional bulk current bypass capacitors for use in applications
BULK
BYPASS
.
1.6.2 Voltage Regulator Output Pin (V
V
is the 3.3V output of the on-chip voltage regulator. V
REG
internally for the MCU operation and the USB data driver. It is also used
to supply the voltage for the external pullup resistor required on the
USB’s D– line. The V
or larger and a 0.1µF ceramic bypass capacitor as Figure 1-5 shows.
Place the bypass capacitors as close to the V
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit.
1.6.4 External Reset Pin (RST)
V
REG
V
REG
MCU
C
REGBYPASS
0.1 µF
+
C
REGBULK
> 4.7 µF
V
SS
A logic zero on the RST pin forces the MCU to a known start-up state.
RST is bidirectional, allowing a reset of the entire system. It is driven low
when any internal reset source is asserted. The RST pin contains an
internal pullup device to VDD. (See Section 8. System Integration
Module (SIM).)
1.6.5 External Interrupt Pins (IRQ, PTE4/D–)
is an asynchronous external interrupt pin. IRQ is also the pin to
IRQ
enter Monitor mode. The IRQ pin contains a software configurable pullup
device to VDD. PTE4/D– can be programmed to trigger the IRQ interrupt.
(See Section 15. External Interrupt (IRQ).)
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorGeneral Description35
General Description
1.6.6 CGM Power Supply Pins (V
V
is the power supply pin, V
DDA
the analog portion of the clock generator modules (CGMs). Connect
V
to the same voltage potential as VDD. Connect V
DDA
pins to the same voltage potential as VSS. Decoupling of these pins
should be as per the digital supply.
1.6.7 CGM Voltage Regulator Out (V
V
REGA0
V
REGA0
is the 3.3V output of the second on-chip voltage regulator.
is used for CGM1 and CGM2 operation. Decoupling of this pin
should be as per the digital V
1.6.8 CGM Voltage Regulator In (V
V
REGA1
V
REGA0
is the 3.3V input pin for CGM2. Connect V
. Decoupling of V
CGMXFC1 and CGMXFC2 are external capacitor connections for the
respective CGMs.
1.6.10 CGM Clock Output Pins (CGMOUT1, CGMOUT2)
CGMOUT1 and CGMOUT2 are buffered VCO outputs of the respective
CGMs.
1.6.11 Port A Input/Output (I/O) Pins (PTA7/KBA7
PTA7/KBA7
–PTA0/KBA0 are general-purpose bidirectional I/O port
–PTA0/KBA0)
pins. (See Section 14. Input/Output (I/O) Ports.) Each pin contains a
software configurable pullup device to V
an input. (See 14.7 Port Options.) Each pin can also be programmed
as an external keyboard interrupt pin. (See Section 16. Keyboard
Interrupt Module (KBI).)
when the pin is configured as
DD
Technical DataMC68HC908JB16 — Rev. 1.1
36General DescriptionFreescale Semiconductor
1.6.12 Port C I/O Pins (PTC1/RxD, PTC0/TxD)
Port C is a 2-bit special function port that shares its pins with the SCI
module. (See Section 14. Input/Output (I/O) Ports.) Each pin contains
a software configurable pullup device to VDD when the pin is configured
as an input. (See 14.7 Port Options.)
1.6.13 Port D I/O Pins (PTD5–PTD0)
PTD5–PTD0 are general-purpose bidirectional I/O port pins; open-drain
when configured as output. (See Section 14. Input/Output (I/O) Ports.)
PTD5–PTC2 are software configurable to be 10mA sink pins for direct
LED connections. PTD1–PTD0 are software configurable to be 25mA
sink pins for direct infrared LED connections. (See 14.7 Port Options.)
General Description
1.6.14 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/T2CH01, PTE1/T1CH01, PTE0/TCLK)
Port E is a 5-bit special function port that shares two of its pins with the
USB module and three of its pins with the two timer interface modules.
Each PTE2–PTE0 pin contains a software configurable pullup device to
VDD when the pin is configured as an input or output.
When the USB module is disabled, the PTE4 and PTE3 pins are
general-purpose bidirectional I/O port pins with 10mA sink capability.
Each pin is open-drain when configured as an output; and each pin
contains a software configurable 5kΩ pullup to VDD when configured as
an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt.
When the USB module is enabled, the PTE4/D– and PTE3/D+ pins
become the USB module D– and D+ pins. The USB D– pin contains a
1.5kΩ software configurable pullup device to V
. (See Section 10.
REG
Timer Interface Module (TIM), Section 11. Universal Serial Bus
Module (USB) and Section 14. Input/Output (I/O) Ports.)
NOTE:Any unused inputs and I/O ports should be tied to an appropriate logic
level (either V
do not require termination, termination is recommended to reduce the
possibility of static damage.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorGeneral Description37
or VSS). Although the I/O ports of the MC68HC908JB16
DD
General Description
Summary of the pin functions are provided in Table 1-1.
Table 1-1. Summary of Pin Functions
PIN NAMEPIN DESCRIPTIONIN/OUT
V
DD
V
SS
V
REG
RST
IRQ
Power supply.IN4.0 to 5.5V
Power supply ground.OUT0V
3.3V regulated output from MCU.OUT
Reset input, active low.
With internal pull-up and schmitt trigger input.
External IRQ pin; with programmable internal pull-up and
schmitt trigger input.
IN/OUT
IN
Used for mode entry selection.IN
OSC1Crystal oscillator input.IN
OSC2Crystal oscillator output; inverting of OSC1 signal.OUT
(1)
V
DDA
V
SSA0
V
SSA1
V
REGA0
(1)
(1)
(1)
Analog power supply.IN4.0 to 5.5V
Analog power supply ground.OUT0V
3.3V regulated output from MCU.OUT
VOLTAGE
LEVEL
V
(3.3V)
REG
V
DD
V
DD
V
to V
REG
V
REG
V
REG
V
REGA0
TST
(3.3V)
REGA1
(1)
V
CGMXFC1
CGMXFC2
CGMOUT1
CGMOUT2
PTA0/KBA0
:
PTA7/KBA7
3.3V input for CGM2.IN
(1)
CGM1 external filter capacitor connection.OUT
(1)
CGM2 external filter capacitor connection.OUT
(1)
CGM1 clock output .OUT
(1)
CGM2 clock output .OUT
8-bit general purpose I/O port.IN/OUT
Pins as keyboard interrupts, KBA0–KBA7.IN
Each pin has programmable int ernal pullup when configured
as input.
IN
V
REGA0
V
REGA0
V
REGA0
V
REGA0
V
REGA0
V
V
V
DD
DD
DD
Technical DataMC68HC908JB16 — Rev. 1.1
38General DescriptionFreescale Semiconductor
Table 1-1. Summary of Pin Functions
General Description
PIN NAMEPIN DESCRIPTIONIN/OUT
2-bit general purpose I/O port.IN/OUT
PTC0/TxD
PTC1/RxD
Each pin has programmable internal pull-up device.IN
PTC0 as TxD of SCI module.OUT
PTC1 as RxD of SCI module.IN
6-bit general purpose I/O port;
PTD0–PTD5
open-drain when configured as output.
(2)
PTD0–PTD1 have conf igurable 25mA sink for infrared LED.OUT
OUT
PTD2–PTD5 have conf igurable 10mA sink for LED.OUT
PTE0–PTE2 are general purpose I/O lines.IN/OUT
PTE0/TCLK
PTE1/T1CH01
PTE0–PTE2 have programmable internal pullup when
configured as input or output.
PTE0 as TCLK of TIM1 and TIM2.IN
IN/OUT
PTE2/T2CH01
PTE1 as T1CH01 of TIM1.IN/OUT
IN
VOLTAGE
LEVEL
V
DD
V
DD
V
DD
V
DD
V
DD
V
or V
REG
V
or V
REG
V
or V
REG
V
DD
V
DD
V
DD
V
DD
DD
DD
DD
PTE2 as T2CH01 of TIM2.IN/OUT
PTE3–PTE4 general purpose I/O lines;
open-drain when configured as output.
PTE3–PTE4 have programmable internal pullup when
PTE3/D+
PTE4/D–
configured as input.
PTE3 as D+ of USB module.IN/OUT
PTE4 as D– of USB module.IN/OUT
PTE4 as additional IRQ interrupt.IN
Notes:
1. Pin available on 32-pin package only.
2. PTD[5:1] pins available on 28-pin package only.
The CPU08 can address 64k-bytes of memory space. The memory map,
shown in Figure 2-1, includes:
Section 2. Memory Map
•16,384 bytes of FLASH memory
•384 bytes of random-access memory (RAM)
•48 bytes of user-defined vectors
•1,024 + 448 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map
(Figure 2-1) and in register figures in this document, unimplemented
locations are shaded.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorMemory Map41
Memory Map
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area
of $0000–$007F. Additional I/O registers have these addresses:
•$FE00; SIM break status register, SBSR
•$FE01; SIM reset status register, SRSR
•$FE02; Reserved
•$FE03; SIM break flag control register, SBFCR
•$FE04; Interrupt status register 1, INT1
•$FE05; Interrupt status register 2, INT2
•$FE06; Reserved
•$FE07; Reserved
•$FE08; FLASH control register, FLCR
•$FE09; FLASH block protect register, FLBPR
•$FE0A; Reserved
•$FE0B; Reserved
•$FE0C; Break address register high, BRKH
•$FE0D; Break address register low, BRKL
•$FE0E; Break status and control register, BRKSCR
•$FE0F; Reserved
•$FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector
locations.
Technical DataMC68HC908JB16 — Rev. 1.1
42Memory MapFreescale Semiconductor
Memory Map
$0000
↓
$007F
$0080
↓
$01FF
$0200
↓
$B9FF
$BA00
↓
$F9FF
$FA00
↓
$FDFF
$FE00SIM Break Status Register (SBSR)
$FE01SIM Reset Status Register (SRSR)
$FE02Reserved
$FE03SIM Break Flag Control Register (SBFCR)
$FE04Interrupt Status Register 1 (INT1)
$FE05Interrupt Status Register 2 (INT2)
I/O Registers
128 Bytes
RAM
384 Bytes
Unimplemented
47,104 Bytes
FLASH Memory
16,384 Bytes
Monitor ROM 1
1,024 Bytes
$FE06Reserved
$FE07Reserved
$FE08FLASH Control Register (FLCR)
$FE09FLASH Block Protect Register (FLBPR)
$FE0AReserved
$FE0BReserved
$FE0CBreak Address Register High (BRKH)
$FE0DBreak Address Register Low (BRKL)
$FE0EBreak Status and Control Register (BRKSCR)
$FE0FReserved
$FE10
↓
$FFCF
$FFD0
↓
$FFFF
Monitor ROM 2
448 Bytes
FLASH Vectors
48 Bytes
Figure 2-1. Memory Map
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorMemory Map43
Memory Map
Addr.Register NameBit 7654321Bit 0
$0000
$0001Reserved
$0002
$0003
$0004
* DDRA7 bit is reset by POR or LVI reset only.
Port A Data Register
(PTA)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
$0005Reserved
$0006
Data Direction Register C
(DDRC)
Read:
Write:
Reset:Unaffected by reset
Read:
Write:
Reset:
Read:000000
Write:
Reset:Unaffected by reset
Read:00
Write:
Reset:Unaffected by reset
Read:
Write:
Reset:0*0000000
Read:
Write:
Reset:
Read:000000
Write:
Reset:00000000
PTA7PTA6PTA5PTA4PTA3PTA2PTA1PTA0
RRRRRRRR
PTC1PTC0
PTD5PTD4PTD3PTD2PTD1PTD0
DDRA7DDRA6DDRA5DDRA4DDRA3DDRA2DDRA1DDRA0
RRRRRRRR
DDRC1DDRC0
$0007
$0008
$0009
Data Direction Register D
Port E Data Register
Data Direction Register E
(DDRD)
(PTE)
(DDRE)
U = Unaffected
Read:00
Write:
Reset:00000000
Read:000
Write:
Reset:Unaffected by reset
Read:000
Write:
Reset:00000000
X = Indeterminate
DDRD5DDRD4DDRD3DDRD2DDRD1DDRD0
PTE4PTE3PTE2PTE1PTE0
DDRE4DDRE3DDRE2DDRE1DDRE0
= UnimplementedR= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
Technical DataMC68HC908JB16 — Rev. 1.1
44Memory MapFreescale Semiconductor
Memory Map
Addr.Register NameBit 7654321Bit 0
Timer 1 Status and Control
$000A
$000BReserved
$000C
$000D
Timer 1 Counter Modulo
$000E
Timer 1 Counter Modulo
$000F
Timer 1 Channel 0
$0010
$0011
Status and Control
Timer 1 Channel 0
Register
(T1SC)
Timer 1 Counter
Register High
(T1CNTH)
Timer 1 Counter
Register Low
(T1CNTL)
Register High
(T1MODH)
Register Low
(T1MODL)
Register
(T1SC0)
Register High
(T1CH0H)
Read:TOF
TOIETSTOP
Write:0TRST
Reset:00100000
Read:
RRRRRRRR
Write:
Reset:
Read:Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8
Write:
Reset:00000000
Read:Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Write:
Reset:00000000
Read:
Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8
Write:
Reset:11111111
Read:
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Write:
Reset:11111111
Read:CH0F
CH0IEMS0BMS0AELS0BELS0ATOV0CH0MAX
Write:0
Reset:00000000
Read:
Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8
Write:
Reset:Indeterminate after reset
00
PS2PS1PS0
Read:
Write:
Reset:Indeterminate after reset
Read:CH1F
Write:0
Reset:00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
CH1IECH01IEMS1AELS1BELS1ATOV1CH1MAX
X = Indeterminate
= UnimplementedR= Reserved
$0012
$0013
Timer 1 Channel 0
Register Low
(T1CH0L)
Timer 1 Channel 1
Status and Control
Register
(T1SC1)
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12)
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorMemory Map45
Memory Map
Addr.Register NameBit 7654321Bit 0
Timer 1 Channel 1
$0014
$0015
$0016
Keyboard Interrupt Enable
$0017
$0018
$0019
$001A
* PULLEN bit is reset by POR or LVI reset only.
USB Interrupt Register 2
USB Control Register 2
USB Control Register 3
Register High
(T1CH1H)
Timer 1 Channel 1
Register Low
(T1CH1L)
Keyboard Status and
Control Register
(KBSCR)
Register
(KBIER)
(UIR2)
(UCR2)
(UCR3)
Read:
Write:
Reset:Indeterminate after reset
Read:
Write:
Reset:Indeterminate after reset
Read:0000KEYF0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:00000000
Write: EOPFRRSTFRTXD2FRRXD2FRTDX1FR
Reset:00000000
Read:
Write:
Reset:00000000
Read:TX1ST0
Write:
Reset:000000*00
Bit15Bit14Bit13Bit12Bit11Bit10Bit9Bit8
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
ACKK
KBIE7KBIE6KBIE5KBIE4KBIE3KBIE2KBIE1KBIE0
RESUMFR
T2SEQSTALL2TX2ERX2ETP2SIZ3TP2SIZ2TP2SIZ1TP2SIZ0
TX1STR
OSTALL0 ISTALL0
0
PULLEN ENABLE2 ENABLE1
IMASKKMODEK
TXD0FRRXD0FR
$001B
$001C
$001D
USB Control Register 4
(UCR4)
IRQ Option Control
Register
(IOCR)
Port Option Control
Register
(POCR)
U = Unaffected
Read:00000
Write:
Reset:00000000
Read:00000PTE4IF
Write:
Reset:00000000
Read:
PTE20PPTDLDD PTDILDDPTE4PPTE3PPCPRPAP
Write:
Reset:00000000
X = Indeterminate
= UnimplementedR= Reserved
FUSBOFDPFDM
PTE4IEIRQPD
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
Technical DataMC68HC908JB16 — Rev. 1.1
46Memory MapFreescale Semiconductor
Memory Map
Addr.Register NameBit 7654321Bit 0
IRQ Status and Control
$001E
$001F
† One-time writable register after each reset.
* LVIDR, LVI5OR3, URSTD, and LVID, are reset by POR or LVI reset only.
This section describes the 384 bytes of RAM (random-access memory).
3.3 Functional Description
Addresses $0080 through $01FF are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K-byte memory space.
NOTE:For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 128 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE:Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorFLASH Memory59
FLASH Memory
Addr.Register NameBit 7654321Bit 0
Read:0000
$FE08
FLASH Control Register
(FLCR)
Write:
Reset:00000000
HVENMASSERASEPGM
FLASH Block Protect
$FE09
Register
(FLBPR)
Reset:00000000
4.3 Functional Description
The FLASH memory consists of an array of 16,384 bytes for user
memory plus a block of 48 bytes for user interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory is block erasable. The minimum erase block size is 512 bytes.
Program and erase operation operations are facilitated through control
bits in FLASH Control Register (FLCR).The address ranges for the
FLASH memory are shown as follows:
Read:
BPR7BPR6BPR5BPR4BPR3BPR2BPR1BPR0
Write:
= Unimplemented
Figure 4-1. FLASH I/O Register Summary
•$BA00–$F9FF (user memory, 16,384 bytes)
•$FFD0–$FFFF (user interrupt vectors, 48 bytes)
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE:A security feature prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical DataMC68HC908JB16 — Rev. 1.1
60FLASH MemoryFreescale Semiconductor
1
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operation.
Address:$FE08
Read:0000
Write:
Reset:00000000
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the
memory for either program or erase operation. It can only be set if
either PGM=1 or ERASE=1 and the sequence for erase or
program/verify is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
FLASH Memory
Bit 7654321Bit 0
HVENMASSERASEPGM
= Unimplemented
Figure 4-2. FLASH Control Register (FLCR)
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
This read/write bit configures the memory for program operation. This
bit and the ERASE bit should not be set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorFLASH Memory61
FLASH Memory
4.5 FLASH Block Erase Operation
Use the following procedure to erase a block of FLASH memory. A block
consists of 512 consecutive bytes starting from addresses $X000,
$X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. The 48-byte
user interrupt vectors area also forms a block. Any block within the 16K
bytes user memory area ($BA00–$F9FF) can be erased alone.
NOTE:The 48-byte user interrupt vectors, $FFD0–$FFFF, cannot be erased by
the block erase operation because of security reasons. Mass erase is
required to erase this block.
1.Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2.Write any data to any FLASH address within the address range of
the block to be erased.
3.Wait for a time, t
nvs
(5µs).
4.Set the HVEN bit.
5.Wait for a time t
6.Clear the ERASE bit.
7.Wait for a time, t
8.Clear the HVEN bit.
9.After time, t
(1µs), the memory can be accessed in read mode
rcv
again.
NOTE:Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
Erase
nvh
(10ms).
(5µs).
Technical DataMC68HC908JB16 — Rev. 1.1
62FLASH MemoryFreescale Semiconductor
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1.Set both the ERASE bit and the MASS bit in the FLASH control
register.
2.Write any data to any FLASH address within the address range
$FFD0–$FFFF.
FLASH Memory
3.Wait for a time, t
nvs
(5µs).
4.Set the HVEN bit.
5.Wait for a time t
MErase
(200ms).
6.Clear the ERASE bit.
7.Wait for a time, t
nvhl
(100µs).
8.Clear the HVEN bit.
9.After time, t
(1µs), the memory can be accessed in read mode
rcv
again.
NOTE:Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorFLASH Memory63
FLASH Memory
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80 or $XXC0. The procedure for programming a row of the
FLASH memory is outlined below:
1.Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2.Write any data to any FLASH address within the address range of
the row to be programmed.
3.Wait for a time, t
nvs
(5µs).
4.Set the HVEN bit.
5.Wait for a time, t
(10µs).
pgs
6.Write data to the byte being programmed.
7.Wait for time, t
Prog
(30µs).
8.Repeat steps 6 and 7 until all the bytes within the row are
programmed.
9.Clear the PGM bit.
10.Wait for time, t
11.Clear the HVEN bit.
12.After time, t
rcv
again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE:Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed
from RAM. While these operations must be performed in the order as
shown, but other unrelated operations may occur between the steps. Do
not exceed t
Characteristics.
maximum. See 20.14 FLASH Memory
Prog
(5µs).
nvh
(1µs), the memory can be accessed in read mode
Figure 4-3 shows a flowchart representation for programming the
FLASH memory.
Technical DataMC68HC908JB16 — Rev. 1.1
64FLASH MemoryFreescale Semiconductor
FLASH Memory
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
Write any data to any FLASH address
Set PGM bit
within the row address range desired
3
4
5
6
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address
to be programmed
7
Wait for a time, t
nvs
pgs
Prog
Completed
programming
this row?
NOTE:
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
must not exceed the maximum programming
Prog
max.
time, t
This row program algorithm assumes the row/s
to be programmed are initially erased.
Figure 4-3. FLASH Programming Flowchart
Y
N
9
10
11
12
Clear PGM bit
Wait for a time, t
nvh
Clear HVEN bit
Wait for a time, t
rcv
End of Programming
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorFLASH Memory65
FLASH Memory
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH Block
Protect Register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE:When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set,
the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register.
The 7 bits of the 8-bit content of this register determine the starting
location of the protected range within the FLASH memory.
Address:$FE09
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0
BPR[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0]
are logic 0’s.
Bit 7654321Bit 0
BPR7BPR6BPR5BPR4BPR3BPR2BPR1BPR0
Figure 4-4. FLASH Block Protect Register (FLBPR)
16-bit memory address
Start address of FLASH block protect000000000
BPR[7:1]
Figure 4-5. FLASH Block Protect Start Address
Technical DataMC68HC908JB16 — Rev. 1.1
66FLASH MemoryFreescale Semiconductor
FLASH Memory
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be X000, X200, X400,
X600, X800, XA00, XC00, or XE00 within the FLASH memory.
Note:
The end address of the protected range is always $FFFF.
4.9 ROM-Resident Routines
ROM-resident routines can be called by a program running in user mode
or in monitor mode (see Section 9. Monitor ROM (MON)) for FLASH
programming, erasing, and verifying. The range of the FLASH memory
must be unprotected (see 4.8 FLASH Protection) before calling the
erase or programming routine.
Routine NameCall AddressDescription
VERIFY$FC03FLASH verify routine
$FE$FFD0–$FFFF (User vectors)
$FFThe entire FLASH memory is not protected.
Ta ble 4-1. ROM-Resident Routines
ERASE$FC06FLASH mass or block erase routine
PROGRAM$FC09FLASH program routine
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorFLASH Memory67
FLASH Memory
4.9.1 Variables
The ROM-resident routines use three variables: CTRLBYT, CPUSPD
and LADDR; and one data buffer. The minimum size of the data buffer
is one byte and the maximum size is 64 bytes.
CPUSPD must be set before calling the erase or programming routines,
and should be set to four times the value of the CPU internal bus speed
in MHz. For example: for CPU speed of 6MHz, CPUSPD should be set
to 24.
Table 4-2. Summary of FLASH Routine Variables
VariableAddressDescription
CTRLBYT$0088Control byte for sett ing mass or block erase.
CPUSPD$0089Timing adjustment for different CPU speeds.
LADDR$008A–$008BLast FLASH address to be programmed.
4.9.2 ERASE Routine
NOTE:A block erase cannot be performed on the last block of FLASH memory
DATABUF$0100–$013FData buffer for programming and verifying.
The ERASE routine erases the entire or a block of FLASH memory. The
routine does not check for a blank range before or after erase.
This section describes the configuration register, CONFIG. The
configuration register enables or disables these options:
•Low voltage inhibit (LVI) module control and voltage trip point
selection
•USB reset
•Stop mode recovery time (2048 or 4096 OSCDCLK cycles)
•COP timeout period (218 – 24 or 213 – 24 OSCDCLK cycles)
•STOP instruction
•Computer operating properly module (COP)
5.3 Functional Description
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. All of the
configuration register bits are cleared during reset. Since the various
options affect the operation of the MCU, it is recommended that this
register be written immediately after reset. The configuration register is
located at $001F. The configuration register may be read at anytime.
* LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
Figure 5-1. Configuration Register (CONFIG)
LVIDR — LVI Disable Bit for V
LVIDR disables the LVI circuit for V
REG
. (See Section 18. Low-
REG
Voltage Inhibit (LVI).)
1 = LVI circuit for V
0 = LVI circuit for V
NOTE:There is no LVI circuit for V
REG
REG
REGA
disabled
enabled
.
LVI5OR3 — LVI Trip Point Voltage Select Bit for V
LVI5OR3 selects the trip point voltage of the LVI circuit for VDD.
(See Section 18. Low-Voltage Inhibit (LVI).)
1 = LVI trips at 3.3V
0 = LVI trips at 2.4V
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU. (See Section 11. Universal Serial Bus Module
(USB).)
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
DD
LVID — LVI Disable Bit for V
DD
LVID disables the LVI circuit for VDD. (See Section 18. Low-Voltage
Freescale SemiconductorCentral Processor Unit (CPU)75
Central Processor Unit (CPU)
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
6.3 Features
Feature of the CPU include:
•Object code fully upward-compatible with M68HC05 Family
•16-bit stack pointer with stack manipulation instructions
•16-Bit index register with X-register manipulation instructions
•6-MHz CPU internal bus frequency
•64-Kbyte program/data memory space
•16 addressing modes
•Memory-to-memory data moves without using accumulator
•Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•Enhanced binary-coded decimal (BCD) data handling
•Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64-Kbytes
•Low-power stop and wait modes
Technical DataMC68HC908JB16 — Rev. 1.1
76Central Processor Unit (CPU)Freescale Semiconductor
6.4 CPU Registers
Central Processor Unit (CPU)
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
6.4.1 Accumulator
7
15
HX
15
15
70
V11HINZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7654321Bit 0
Read:
Write:
Reset:Unaffected by reset
Figure 6-2. Accumulator (A)
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorCentral Processor Unit (CPU)77
Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64K-byte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
Bit
1413121110987654321
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Bit
0
Figure 6-3. Index Register (H:X)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
1413121110987654321
15
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 6-4. Stack Pointer (SP)
Technical DataMC68HC908JB16 — Rev. 1.1
78Central Processor Unit (CPU)Freescale Semiconductor
NOTE:The location of the stack is arbitrary and may be relocated anywhere in
6.4.4 Program Counter
Central Processor Unit (CPU)
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
1413121110987654321
15
Read:
Write:
Reset:Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit
0
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorCentral Processor Unit (CPU)79
Central Processor Unit (CPU)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:
V11HI NZC
X1 1X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction
uses the states of the H and C flags to determine the appropriate
correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Technical DataMC68HC908JB16 — Rev. 1.1
80Central Processor Unit (CPU)Freescale Semiconductor
Central Processor Unit (CPU)
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE:To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorCentral Processor Unit (CPU)81
Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
6.6.1 Wait Mode
The WAIT and STOP ins tr uc ti on s put the MCU in l o w p o w e r- c o ns u m p ti o n
standby modes.
The WAIT instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock.
Technical DataMC68HC908JB16 — Rev. 1.1
82Central Processor Unit (CPU)Freescale Semiconductor
6.6.2 Stop Mode
The STOP instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock.
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See Section 19. Break Module (BRK).) The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
Central Processor Unit (CPU)
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorCentral Processor Unit (CPU)83
90Central Processor Unit (CPU)Freescale Semiconductor
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 8 of 8)
Effect on
Source
Form
SWISoftware Interrupt
TAPTransfer A to CCRCCR ← (A)↕↕↕↕↕↕INH842
TAXTransfer A to XX ← (A)––––––INH971
TPATransfer CCR to AA ← (CCR)– – – – – – INH851
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSXTransfer SP to H:XH:X ← (SP) + 1––––––INH952
TXATransfer X to AA ← (X)––––––INH9F1
TXSTransfer H:X to SP(SP) ← (H:X) – 1––––––INH942
AAccumulatornAny bit
CCarry/borrow bitoprOperand (one or two bytes)
CCR Condition code registerPCProgram counter
ddDirect address of operandPCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instructionPCL Program counter low byte
DDDirect to direct addressing modeREL Relative addressing mode
DIRDirect addressing moderelRelative program counter offset byte
DIX+ Direct to indexed with post increment addressing moderrRelative program counter offset byte
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 Stack pointer, 8-bit offset addressing mode
EXTExtended addressing modeSP2 Stack pointer 16-bit offset addressing mode
ffOffset byte in indexed, 8-bit offset addressingSPStack pointer
HHalf-carry bitUUndefined
HIndex register high byteVOverflow bit
hh llHigh and low bytes of operand address in extended addressingXIndex register low byte
IInterrupt maskZZero bit
iiImmediate operand byte&Logical AND
IMDImmediate source to direct destination addressing mode|Logical OR
IMMImmediate addressing mode
INHInherent addressing mode( )Contents of
IXIndexed, no offset addressing mode–( ) Negation (two’s complement)
IX+Indexed, no offset, post increment addressing mode#Immediate value
IX+D Indexed with post increment to direct addressing mode
IX1Indexed, 8-bit offset addressing mode←Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode?If
IX2Indexed, 16-bit offset addressing mode:Concatenated with
MMemory location↕Set or cleared
NNegative bit—Not affected
Test for Negative or Zero(A) – $00 or (X) – $00 or (M) – $000 – – ↕↕–
The oscillator circuit is designed for use with crystals or ceramic
resonators. The oscillator circuit generates the crystal clock signal,
OSCXCLK, and passes through a clock doubler to produce OSCDCLK.
This clock doubler clock is further divided by two before being passed on
to the system integration module (SIM) for bus clock generation.
Figure 7-1 shows the structure of the oscillator. The oscillator requires
various external components.
The MC68HC908JB16 operates from a nominal 12MHz crystal,
providing a 6MHz internal bus clock. The 12MHz clock is required for
various modules, such as the CGMs and USB. The clock doubler clock,
OSCDCLK, is used as the base clock for the COP module.
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorOscillator (OSC)93
Oscillator (OSC)
7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external
components. The crystal oscillator is normally connected in a Pierce
oscillator configuration, as shown in Figure 7-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
•Crystal, X1 (nominally 12MHz)
•Fixed capacitor, C
1
•Tuning capacitor, C2 (can also be a fixed capacitor)
•Feedback resistor, R
B
•Series resistor, RS (not required for 12MHz)
FROM SIM
SIMOSCEN
MCU
OSC1OSC2
R
B
X1
TO CGMTO SIM
OSCXCLK
CLOCK
DOUBLER
÷ 2
RS*
TO COP, SCI
OSCDCLK
TO USB
÷ 2
OSCOUT
12 MHz
C1C2
* RS can be 0 (shorted) when used with
higher frequency crystals.
Refer to manufacturer’s data.
Figure 7-1. Oscillator External Connections
The series resistor (R
) is included in the diagram to follow strict Pierce
S
oscillator guidelines and may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Technical DataMC68HC908JB16 — Rev. 1.1
94Oscillator (OSC)Freescale Semiconductor
7.4 I/O Signals
The following paragraphs describe the oscillator input/output (I/O)
signals.
7.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.4.2 Crystal Amplifier Output Pin (OSC1)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN)
Oscillator (OSC)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator.
7.4.4 Crystal Output Frequency Signal (OSCXCLK)
OSCXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f
) and comes directly from the crystal oscillator circuit.
XCLK
Figure 7-1 shows only the logical relation of OSCXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
OSCXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of OSCXCLK can be
unstable at startup.
7.4.5 Clock Doubler Out (OSCDCLK)
OSCDCLK is the clock doubler output signal. It runs at twice the speed
of the crystal (f
) and comes from the clock doubler circuit.
XCLK
MC68HC908JB16 — Rev. 1.1Technical Data
Freescale SemiconductorOscillator (OSC)95
Oscillator (OSC)
7.4.6 Oscillator Out (OSCOUT)
OSCOUT is the divide-by-two signal after the clock doubler circuit. It
runs at the same speed as OSCXCLK, at crystal frequency (f
signal goes to the SIM, which generates the MCU clocks. OSCOUT will
be divided-by-two again in the SIM and results in the internal bus
frequency being one half of the crystal frequency.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
7.5.1 Wait Mode
XCLK
). This
The WAIT instruction has no effect on the oscillator logic. OSCXCLK
continues to drive to the MCU.
7.5.2 Stop Mode
The STOP instruction disables the OSCXCLK output.
7.6 Oscillator During Break Mode
The oscillator continues to drive OSCXCLK when the chip enters the
break state.
8.8.3SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .120
8.2 Introduction
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. The SIM is a system
state controller that coordinates CPU and exception timing. A block
diagram of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of
the SIM I/O registers. The SIM is responsible for:
•Bus clock generation and control for CPU and peripherals
–Stop/wait/reset/break entry and recovery
–Internal clock control
•Master reset control, including power-on reset (POR) and COP
timeout
•Interrupt control:
–Acknowledge timing
–Arbitration control timing
–Vector address generation
•CPU enable/disable timing
•Modular architecture expandable to 128 interrupt sources
Table 8-1 shows the internal signal names used in this section.
SIM to generate the internal bus clocks.
(Bus clock = OSCDCLK ÷ 4 = OSCXCLK ÷ 2)
Read/write signal
System Integration Module (SIM)
Addr.Register NameBit 7654321Bit 0
SIM Break Status Register
$FE00
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
$FE01
SIM Break Flag Control
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
(SBSR)
(SRSR)
Register
(SBFCR)
(INT1)
(INT2)
Read:
RRRRRR
Write:See note
Reset:0
Read:PORPINCOPILOPILADUSBLVI0
Write:
POR:10000000
Read:
BCFERRRRRRR
Write:
Reset:0
Read:IF6IF5IF4IF3IF2IF100
Write:RRRRRRRR
Reset:00000000
Read:IF14IF13IF12IF11IF10IF9IF8IF7
Write:RRRRRRRR
Reset:00000000
SBSW
R
Figure 8-2. SIM I/O Register Summary
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 8-3.