Freescale MC68HC908GZ60 DATA SHEET
查询MC68HC908GZ32供应商
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Freescale Semiconductor, Inc.
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
cale Semiconductor,
Frees
M68HC08
Microcontrollers
MOTOROLA.COM/SEMICONDUCTORS
MC68HC908GZ60/D
Rev. 1.0
5/2004
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Freescale Semiconductor, Inc.
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For More Information On This Product,
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Freescale Semiconductor, Inc.
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
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To provide the most up-to-date information, the revision of our documents on the
World Wide Web will be the most current. Your printed copy may be an earlier
revision. To verify you have the latest information available, refer to:
http://motorola.com/semiconductors
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The following revision history table summarizes changes contained in this
document. For your convenience, the page number designators have been linked
to the appropriate location.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA 3
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Revision History
Freescale Semiconductor, Inc.
Revision History
Date
April,
2004
May,
2004
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Revision
Level
N/A Initial release N/A
9.7.3 Keyboard Interrupt Polarity Register — Corrected the bit description
of the KBIP7–KBIP0 bits.
14.8.8 ESCI Prescaler Register — Reworked note under PDS2–PDS0
description for clarity.
Table 22-1. MC Order Numbers — Corrected order numbers. 367
Figure 22-1. Device Numbering System — Reworked diagram to reflect
1.0
correct order numbers.
Table A-1. MC Order Numbers — Corrected order numbers. 374
Figure A-3. Device Numbering System — Reworked diagr am to reflect
correct order numbers.
B.4 Ordering Information — Corrected order numbers. 378
Figure B-3. Device Numbering System — Reworked diagr am to reflect
correct order numbers.
Description
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Page
Number(s)
132
234
367
374
378
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Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
4 Revision History MOTOROLA
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Freescale Semiconductor, Inc.
Data Sheet — MC68HC908GZ60
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Section 3. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . .65
Section 4. Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . .79
List of Sections
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Section 5. Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . .99
Section 6. Computer Operating Properly (COP) Module. . . . . . . . . .103
Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . .107
Section 8. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Section 9. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . .125
Section 10. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Section 11. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . .141
Section 12. MSCAN08 Controller (MSCAN08) . . . . . . . . . . . . . . . . . .145
Section 13. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . .183
Section 14. Enhanced Serial Communications
Interface (ESCI) Module . . . . . . . . . . . . . . . . . . . . . . . . .205
Section 15. System Integration Module (SIM) . . . . . . . . . . . . . . . . . .241
Section 16. Serial Peripheral Interface (SPI) Module. . . . . . . . . . . . .261
Section 17. Timebase Module (TBM). . . . . . . . . . . . . . . . . . . . . . . . . .285
Section 18. Timer Interface Module (TIM1). . . . . . . . . . . . . . . . . . . . .291
Section 19. Timer Interface Module (TIM2). . . . . . . . . . . . . . . . . . . . .309
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA List of Sections 5
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List of Sections
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Section 20. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Section 21. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .351
Section 22. Ordering Information
Appendix A. MC68HC908GZ48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
Appendix B. MC68HC908GZ32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
and Mechanical Specifications . . . . . . . . . . . . . . . . . . .367
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Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
6 List of Sections MOTOROLA
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Data Sheet — MC68HC908GZ60
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2.2 Features of the CPU08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1 Power Supply Pins (V
1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.3 External Reset Pin (RST
1.5.4 External Interrupt Pin (IRQ
1.5.5 CGM Power Supply Pins (V
1.5.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . 30
1.5.7 ADC Power Supply/Reference Pins
1.5.8 Port A Input/Output (I/O) Pins
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0). . . . . . . . . . . . . . . . . . . . . . 30
1.5.10 Port C I/O Pins (PTC6–PTC0/CANTX). . . . . . . . . . . . . . . . . . . . . . . 30
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS
1.5.12 Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . . 31
1.5.13 Port F I/O Pins (PTF7/T2CH5–PTF0). . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.14 Port G I/O Pins (PTG7/AD23–PTBG0/AD16). . . . . . . . . . . . . . . . . . 31
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.6 FLASH-1 Memory (FLASH-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.2 FLASH-1 Control and Block Protect Registers. . . . . . . . . . . . . . . . . 49
2.6.2.1 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.6.2.2 FLASH-1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.6.3 FLASH-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Section 1. General Description
and VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
and V
DDA
(V
DDAD/VREFH
(PTA7/KBD7/AD15–PTA0/KBD0/AD8) . . . . . . . . . . . . . . . . . . . . 30
and V
SSAD/VREFL
) . . . . . . . . . . . . . . . . . . . 29
SSA
) . . . . . . . . . . . . . . . . . . . . . . . . 30
) . . . . . . . . . . . . . . . . . . . . 31
Section 2. Memory
Table of Contents
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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Table of Contents
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2.6.4 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.5 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.6 FLASH-1 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7 FLASH-2 Memory (FLASH-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.2 FLASH-2 Control and Block Protect Registers. . . . . . . . . . . . . . . . . 57
2.7.2.1 FLASH-2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.7.2.2 FLASH-2 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.3 FLASH-2 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.7.4 FLASH-2 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.7.5 FLASH-2 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.7.6 FLASH-2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.7.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.7.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Section 3. Analog-to-Digital Converter (ADC)
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.1 ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.3 Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.6 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.4 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7.1 ADC Analog Power Pin (V
3.7.2 ADC Analog Ground Pin (V
3.7.3 ADC Voltage Reference High Pin (V
3.7.4 ADC Voltage Reference Low Pin (V
3.7.5 ADC Voltage In (V
3.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADIN
). . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SSAD
). . . . . . . . . . . . . . . . . . . . 71
REFH
) . . . . . . . . . . . . . . . . . . . . 71
REFL
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
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3.8.2 ADC Data Register High and Data Register Low. . . . . . . . . . . . . . . 74
3.8.2.1 Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.8.2.2 Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.8.2.3 Left Justified Signed Data Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8.2.4 Eight Bit Truncation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table of Contents
Section 4. Clock Generator Module (CGM)
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.2 Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.4 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.3.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . . . . . . . . 82
4.3.6 Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.7 Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . 88
4.4.4 PLL Analog Power Pin (V
4.4.5 PLL Analog Ground Pin (V
4.4.6 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . 88
4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP) . . . . . . . . . . . 88
4.4.8 Crystal Output Frequency Signal (CGMXCLK). . . . . . . . . . . . . . . . . 89
4.4.9 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . . . . . . . . 89
4.4.10 CGM CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.5.3 PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.5.4 PLL Multiplier Select Register Low. . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.5.5 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . 97
4.8.3 Choosing a Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SSA
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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Table of Contents
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Section 5. Configuration Register (CONFIG)
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 6. Computer Operating Properly (COP) Module
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.4 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.8 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Section 7. Central Processor Unit (CPU)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.8 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Section 8. External Interrupt (IRQ)
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.4 IRQ
8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Section 9. Keyboard Interrupt Module (KBI)
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . 130
9.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . 130
9.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 131
9.7.3 Keyboard Interrupt Polarity Register. . . . . . . . . . . . . . . . . . . . . . . . 132
Section 10. Low-Power Modes
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.1.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.3 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6 Computer Operating Properly Module (COP). . . . . . . . . . . . . . . . . . . . 135
10.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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10.7 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.8 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.10 Enhanced Serial Communications Interface Module (ESCI) . . . . . . . . 136
10.10.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . 137
10.11.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.12 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . . . . . . . . 137
10.12.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.13.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.14 Motorola Scalable Controller Area Network Module (MSCAN) . . . . . . 138
10.14.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.16 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Section 11. Low-Voltage Inhibit (LVI)
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.3.1 Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.3.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.3.3 Voltage Hysteresis Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.3.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.4 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
11.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
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Section 12. MSCAN08 Controller (MSCAN08)
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.3 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4.1 Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4.2 Receive Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.5 Identifier Acceptance Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.2 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.8.1 MSCAN08 Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.8.2 MSCAN08 Soft Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.3 MSCAN08 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.4 CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.5 Programmable Wakeup Function. . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.12 Programmer’s Model of Message Storage. . . . . . . . . . . . . . . . . . . . . . 164
12.12.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.12.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.12.3 Data Length Register (DLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.12.4 Data Segment Registers (DSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.12.5 Transmit Buffer Priority Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . . . . 168
12.13.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . . . . . . . 169
12.13.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . . 171
12.13.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.13.4 MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.13.5 MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . 174
12.13.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . 176
12.13.7 MSCAN08 Transmitter Flag Register. . . . . . . . . . . . . . . . . . . . . . . 177
12.13.8 MSCAN08 Transmitter Control Register. . . . . . . . . . . . . . . . . . . . . 178
12.13.9 MSCAN08 Identifier Acceptance Control Register. . . . . . . . . . . . . 179
12.13.10 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.13.11 MSCAN08 Transmit Error Counter. . . . . . . . . . . . . . . . . . . . . . . . . 180
12.13.12 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . . . . . . . . 181
12.13.13 MSCAN08 Identifier Mask Registers (CIDMR0–CIDMR3). . . . . . . 182
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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Section 13. Input/Output (I/O) Ports
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
13.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
13.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.2.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 189
13.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.3.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.4.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.4.3 Port C Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 194
13.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.5.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.5.3 Port D Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . 197
13.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
13.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
13.6.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
13.7 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.7.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.7.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.8 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
13.8.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
13.8.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Section 14. Enhanced Serial Communications
Interface (ESCI) Module
14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
14.3 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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14.4.3.3 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.6 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 221
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.7.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.8.1 ESCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
14.8.2 ESCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
14.8.3 ESCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.8.4 ESCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.8.5 ESCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.8.7 ESCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.8.8 ESCI Prescaler Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.9.1 ESCI Arbiter Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.9.2 ESCI Arbiter Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
14.9.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
14.9.4 Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
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Section 15. System Integration Module (SIM)
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 244
15.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
15.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . 244
15.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . 244
15.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . 246
15.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . 248
15.3.2.3 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2.6 Monitor Mode Entry Module Reset (MODRST). . . . . . . . . . . . . . 248
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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15.4 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . 249
15.4.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 249
15.4.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.5 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.5.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.5.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
15.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
15.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . 255
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
15.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
15.7 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
15.7.1 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
15.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
15.7.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
cale Semiconductor,
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Section 16. Serial Peripheral Interface (SPI) Module
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
16.3.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
16.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
16.4.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . 266
16.4.2 Transmission Format When CPHA = 0. . . . . . . . . . . . . . . . . . . . . . 266
16.4.3 Transmission Format When CPHA = 1. . . . . . . . . . . . . . . . . . . . . . 267
16.4.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.5 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16.6.1 Overflow Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16.6.2 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
16.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
16.8 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
16.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.9.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.10 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
16.11.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
16.11.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
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16.11.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
16.11.4 SS
16.12 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
16.12.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
16.12.2 SPI Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 280
16.12.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table of Contents
(Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Section 17. Timebase Module (TBM)
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
17.5 TBM Interrupt Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
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17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
17.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
17.7 Timebase Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
cale Semiconductor,
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Section 18. Timer Interface Module (TIM1)
18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
18.3.1 TIM1 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
18.3.3.2 Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
18.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
18.3.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 297
18.3.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . 298
18.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
18.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
18.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
18.6 TIM1 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.7 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.8.1 TIM1 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 300
18.8.2 TIM1 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
18.8.3 TIM1 Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 303
18.8.4 TIM1 Channel Status and Control Registers . . . . . . . . . . . . . . . . . 303
18.8.5 TIM1 Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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Section 19. Timer Interface Module (TIM2)
19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
19.3.1 TIM2 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
19.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
19.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
19.3.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
19.3.3.2 Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
19.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
19.3.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 318
19.3.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . 318
19.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
19.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.6 TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
19.7.1 TIM2 Clock Pin (T2CH0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
19.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0) . . . . 322
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
19.8.1 TIM2 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 323
19.8.2 TIM2 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
19.8.3 TIM2 Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 325
19.8.4 TIM2 Channel Status and Control Registers . . . . . . . . . . . . . . . . . 326
19.8.5 TIM2 Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Section 20. Development Support
20.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.2 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . 336
20.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
20.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
20.2.2 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
20.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 337
20.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20.2.2.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20.2.2.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
20.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
20.3 Monitor Module (MON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
20.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
20.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
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20.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
20.3.1.3 Monitor Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
20.3.1.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
20.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
20.3.2 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table of Contents
Section 21. Electrical Specifications
21.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
21.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
21.5 5.0-Vdc Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
21.6 3.3-Vdc Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
21.7 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
21.8 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
21.9 Clock Generation Module (CGM) Characteristics. . . . . . . . . . . . . . . . . 358
21.9.1 CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.9.2 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.10 5.0-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
21.11 3.3-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
21.12 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
21.13 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
21.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 365
21.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Section 22. Ordering Information
and Mechanical Specifications
22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
22.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
22.3 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . 368
22.4 48-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . 369
22.5 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Appendix A. MC68HC908GZ48
A.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
A.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
A.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA Table of Contents 19
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Table of Contents
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B.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Appendix B. MC68HC908GZ32
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Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
20 Table of Contents MOTOROLA
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Data Sheet — MC68HC908GZ60
1.1 Introduction
The MC68HC908GZ60, MC68HC908GZ48, and MC68HC908GZ32 are members
of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units
(MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and
package types.
Section 1. General Description
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1.2 Features
1.2.1 Standard Features
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The information contained in this document pertains to all three devices with the
exceptions noted in Appendix A. MC68HC908GZ48 and Appendix B.
MC68HC908GZ32.
For convenience, features have been organized to reflect:
• Standard features
• Features of the CPU08
Features of the MC68HC908GZ60 include:
• High-performance M68HC08 architecture optimized for C-compilers
• Fully upward-compatible object code with M6 805, M146805, and M68HC05
Families
• 8-MHz internal bus frequency
• Clock generation module supporting 1-MHz to 8-MHz crystals
• MSCAN08 (Motorola scalable controller area network) controller
(implementing 2.0b protocol as defined in BOSCH specification dated
September 1991)
• FLASH program memory security
• On-chip programming firmware for use with host personal computer which
does not require high voltage for entry
• In-system programming (ISP)
(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 21
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General Description
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• System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip points for
– Illegal opcode detection with reset
– Illegal address detection with reset
• Low-power design; fully static with stop and wait modes
• Standard low-power modes of operation:
– Wait mode
– Stop mode
• Master reset pin and power-on reset (POR)
• On-chip FLASH memory:
– MC68HC908GZ60 — 60 Kbytes
– MC68HC908GZ48 — 48 Kbytes
– MC68HC908GZ32 — 32 Kbytes
• Random-access memory (RAM):
– MC68HC908GZ60 — 2048 bytes
– MC68HC908GZ48 — 1536 bytes
– MC68HC908GZ32 — 1536 bytes
• Serial peripheral interface (SPI) module
• Enhanced serial communications interface (ESCI) module
• One 16-bit, 2-channel timer interface module (TIM1) with selectable input
capture, output compare, and pulse-width modulation (PWM) capability on
each channel
• One 16-bit, 6-channel timer interface module (TIM2) with selectable input
capture, output compare, and pulse-width modulation (PWM) capability on
each channel
• Timebase module with clock prescaler circuitry for eight user selectable
periodic real-time interrupts with optional active clock source during stop
mode for periodic wakeup from stop using an external crystal
• 24-channel, 10-bit successive approximation analog-to-digital converter
(ADC)
• 8-bit keyboard wakeup port with software selectable rising or falling edge
detect, as well as high or low level detection
• Up to 53 general-purpose input/output (I/O) pins, including:
– 40 shared-function I/O pins, depending on package choice
– Up to 13 dedicated I/O pins, depending on package choice
• Selectable pullups on inputs only on ports A, C, and D. Selection is on an
individual port bit basis. During output mode, pullups are disengaged.
• Internal pullups on IRQ
• High current 10-mA sink/source capability on all port pins
3.3-V and 5.0-V operation
and RST to reduce customer system cost
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
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• Higher current 20-mA sink/source capability on PTC0–PTC4 and
PTF0–PTF3
• User selectable clockout feature with divide by 1, 2, and 4 of the bus or
crystal frequency
• User selection of having the o scillator enabled or disabled during stop mode
• BREAK module (BRK) to allow single breakpoint setting during
in-circuit debugging
• Available packages:
– 32-pin low-profile quad flat pack (LQFP)
– 48-pin low-profile quad flat pack (LQFP)
– 64-pin quad flat pack (QFP)
• Specific features in 32-pin LQFP are:
– Port A is only 4 bits: PTA0–PTA3; shared with ADC and KBI modules
– Port B is only 6 bits: PTB0–PTB5; shared with ADC module
– Port C is only 2 bits: PTC0–PTC1; shared with MSCAN module
– Port D is only 7 bits: PTD0–PTD6; shared with SPI, TIM1 and TIM2
– Port E is only 2 bits: PTE0–PTE1; shared with ESCI module
• Specific features in 48-pin LQFP are:
– Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules
– Port B is 8 bits: PTB0–PTB7; shared with ADC module
– Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module
– Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules
– Port E is only 6 bits: PTE0–PTE5; shared with ESCI module
• Specific features in 64-pin QFP are:
– Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules
– Port B is 8 bits: PTB0–PTB7; shared with ADC module
– Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module
– Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, andTIM2 modules
– Port E is only 6 bits: PTE0–PTE5; shared with ESCI module
– Port F is 8 bits: PTF0–PTF7; shared with TIM2 module
– Port G is 8 bits; PTG0–PTG7; shared with ADC module
General Description
Features
modules
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 23
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General Description
1.2.2 Features of the CPU08
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1.3 MCU Block Diagram
Freescale Semiconductor, Inc.
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
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Figure 1-1 shows the structure of the MC68HC908GZ60. Refer to Appendix A.
MC68HC908GZ48 and Appendix B. MC68HC908GZ32.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
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General Description
MCU Block Diagram
(2)
(2)
PTD3/SPSCK
PTD2/MOSI
PORTD
DDRD
COMPUTER OPERATING
(2)
(2)
PTD1/MISO
PTD0/SS/MCLK
PROPERLY MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
PTE5–PTE2
PTE1/RxD
DDRE
MONITOR MODE ENTRY
PTE0/TxD
PORTE
MODULE
PTF6/T2CH4
PTF7/T2CH5
MODULE
SECURITY
PTF5/T2CH3
PTF4/T2CH2
PORTF
DDRF
MODULE
MEMORY MAP
(3)
PTF3–PFT0
MODULE
CONFIGURATION REGISTER 1–2
PTG7/AD23–PTG0/AD16
PORTG
DDRG
MSCAN
MODULE
Figure 1-1. MC68HC908GZ60 Block Diagram
(2)
TX
PTD7/T2CH1
PTC0/CAN
MODULE
6-CHANNEL TIMER INTERFACE
(2)
(2, 3)
(2, 3)
(2, 3)
PTC3
(2, 3)
PTC2
PORTC
DDRC
2-CHANNEL TIMER INTERFACE
RX
PTC1/CAN
MODULE
(2)
(2)
(2, 3)
PTC6
PTC5
PTA7/KBD7/AD15–PTA0/KBD0/AD8
PORTA
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INTERNAL BUS
DDRA
MODULE
PROGRAMMABLE TIMEBASE
PTB7/AD7–PTB0/AD0
PORTB
DDRB
MODULE
DUAL VOLTAGE
SINGLE BREAKPOINT BREAK
PTC4
8-BIT KEYBOARD
INTERRUPT MODULE
LOW-VOLTAGE INHIBIT MODULE
(2)
(2)
(2)
PTD6/T2CH0
PTD5/T1CH1
PTD4/T1CH0
COMMUNICATIONS
ENHANCED SERIAL
INTERFACE MODULE
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UNIT (ALU)
ARITHMETIC/LOGIC
M68HC08 CPU
CPU
REGISTERS
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 62,078 BYTES
USER RAM — 2048 BYTES
MONITOR ROM
USER FLASH VECTOR SPACE — 52 BYTES
1–8 MHz OSCILLATOR
CLOCK GENERATOR MODULE
OSC1
OSC2
PHASE LOCKED LOOP
CGMXFC
SYSTEM INTEGRATION
(1)
MODULE
RST
SINGLE EXTERNAL
INTERRUPT MODULE
(1)
IRQ
CONVERTER MODULE
10-BIT ANALOG-TO-DIGITAL
REFL
REFH
/V
/V
SSAD
DDAD
V
V
MODULE
POWER-ON RESET
V
DD
POWER
SS
DDA
V
V
V
SSA
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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1. Pin contains integrated pullup device.
2. Ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input.
3. Higher current drive port pins
General Description
1.4 Pin Assignments
Figure 1-2, Figure 1-3, and Figure 1-4 illustrate the pin assignments for the 32-pin
LQFP, 48-pin LQFP, and 64-pin QFP respectively.
Freescale Semiconductor, Inc.
TX
OSC1
OSC2
32
RST
1
PTE0/TxD
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PTE1/RxD
IRQ
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
31
2
3
4
5
6
7
8
9
10
SS
DD
V
V
SSAVDDA
CGMXFC
V
29
30
11
12
PTD4/T1CH0
PTD5/T1CH1
PTC1/CANRXPTC0/CAN
27
28
13
14
PTB0/AD0
PTD6/T2CH0
Figure 1-2. 32-Pin LQFP Pin Assignments
cale Semiconductor,
26
15
PTB1/AD1
PTA3/KBD3/AD11
25
24
23
22
21
20
19
18
17
16
PTB2/AD2
PTA2/KBD2/AD10
PTA1/KBD1/AD9
PTA0/KBD0/AD8
V
SSAD/VREFL
V
DDAD/VREFH
PTB5/AD5
PTB4/AD4
PTB3/AD3
Frees
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
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RX
TX
General Description
Pin Assignments
PTD4/T1CH0
SSAVDDA
CGMXFC
V
46
45
15
16
PTD5/T1CH1
PTD6/T2CH0
PTC1/CAN
44
43
17
18
PTD7/T2CH1
PTC0/CAN
42
19
PTC2
PTA7/KBD7/AD15
41
20
PTC3
PTA5/KBD5/AD13
PTA6/KBD6/AD14
40
39
21
22
PTC4
PTB0/AD0
PTA3/KBD3/AD11
PTA4/KBD4/AD12
37
38
36
35
34
33
32
31
30
29
28
27
26
23
PTB1/AD1
25
24
PTB2/AD2
PTA2/KBD2/AD10
PTA1/KBD1/AD9
PTA0/KBD0/AD8
PTC6
PTC5
V
SSAD/VREFL
V
DDAD/VREFH
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
OSC1
OSC2
48
RST
1
PTE0/TxD
PTE1/RxD
PTE2
PTE3
PTE4
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PTE5
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
IRQ
2
3
4
5
6
7
8
9
10
12
47
11
14
13
SS
DD
V
V
Figure 1-3. 48-Pin LQFP Pin Assignments
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MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
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General Description
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RST
PTE0/TxD
PTE1/RxD
PTE2
PTE3
PTE4
PTE5
PTF0
PTF1
Freescale Semiconductor, Inc.
OSC1
OSC2
CGMXFC
64
63 62 61 60
1
2
3
4
5
6
7
8
9
V
SSA
V
DDA
PTC1/CAN
TX
RX
PTC0/CAN
PTG6/AD22
PTG7/AD23
56575859
PTG4/AD20
PTG5/AD21
PTA5/KBD5/AD13
PTA4/KBD4/AD12
PTA6/KBD6/AD14
PTA7/KBD7/AD15
PTA3/KBD3/AD11
49
505152535455
PTA2/KBD2/AD10
48
PTA1/KBD1/AD9
47
46
PTA0/KBD0/AD8
45
PTC6
44
PTC5
43
PTG3/AD19
42
PTG2/AD18
41
PTG1/AD17
40
PTG0/AD16
PTF2
PTF3
IRQ
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
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1.5 Pin Functions
1.5.1 Power Supply Pins (V
10
11
12
13
14
15
16
27
PTC2
PTF7/T2CH5
28 29 30 31
PTC4
PTC3
23
PTD7/T2CH1
24 25 26
PTF5/T2CH3
PTF4/T2CH2
PTF6/T2CH4
18
19
20 21 22
17 32
SS
DD
V
V
PTD5/T1CH1
PTD4/T1CH0
PTD6/T2CH0
Figure 1-4. 64-Pin QFP Pin Assignments
Descriptions of the pin functions are provided here.
and VSS)
DD
PTB0/AD0
PTB1/AD1
39
38
37
36
35
34
PTB2/AD2
33
V
SSAD/VREFL
V
DDAD/VREFH
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
and VSS are the power supply and ground pins. The MCU operates from a
V
DD
single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on
the power supply. To prevent noise problems, take special care to provide power
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
28 General Description MOTOROLA
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supply bypassing at the MCU as Figure 1-5 shows. Place the C1 bypass capacitor
as close to the MCU as possible. Use a high-frequency-response ceramic
capacitor for C1. C2 is an optional bulk current bypass capacitor for use in
applications that require the port pins to source high current levels.
General Description
Pin Functions
MCU
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I
1.5.2 Oscillator Pins (OSC1 and OSC2)
OSC1 and OSC2 are the connections for an external crystal, resonator, or clock
circuit. See Section 4. Clock Generator Module (CGM).
1.5.3 External Reset Pin (RST
cale Semiconductor,
A low on the RST
allowing a reset of the entire system. It is driven low when any internal reset source
is asserted. This pin contains an internal pullup resistor. See Section 15. System
Integration Module (SIM).
V
DD
C1
0.1 µF
+
C2
V
DD
Note: Component values shown represent typical applications.
Figure 1-5. Power Supply Bypassing
)
pin forces the MCU to a known startup state. RST is bidirectional,
V
SS
Frees
1.5.4 External Interrupt Pin (IRQ
is an asynchronous external interrupt pin. This pin contains an internal pullup
IRQ
resistor. See Section 8. External Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (V
and V
V
DDA
generator module (CGM). Decoupling of these pins should be as per the digital
supply. See Section 4. Clock Generator Module (CGM).
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0 Data Sheet
MOTOROLA General Description 29
)
and V
DDA
are the power supply pins for the analog portion of the clock
SSA
SSA
)
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General Description
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Section 4.
Clock Generator Module (CGM).
1.5.7 ADC Power Supply/Reference Pins (V
DDAD
and V
REFH
SSAD
and V
V
(ADC). V
high reference supply for the ADC, and by default the V
externally filtered and connected to the same voltage potential as V
low reference supply for the ADC, and by default the V
connected to the same voltage potential as V
Converter (ADC).
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1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8)
I
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port
A pins can be programmed to serve as keyboard interrupt pins or used as
analog-to-digital inputs. PTA7–PTA4 are only available on the 48-pin LQFP and
64-pin QFP packages. See Section 13. Input/Output (I/O) Ports, Section 9.
Keyboard Interrupt Module (KBI), and Section 3. Analog-to-Digital Converter
(ADC).
These port pins also have selectable pullups when configured for input mode. The
pullups are disengaged when configured for output mode. The pullups are
selectable on an individual port bit basis.
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used
for analog-to-digital converter (ADC) inputs. PTB7–PTB6 are only available on the
cale Semiconductor,
1.5.10 Port C I/O Pins (PTC6–PTC0/CAN
Frees
48-pin LQFP and 64-pin QFP packages. See Section 13. Input/Output (I/O)
Ports and Section 3. Analog-to-Digital Converter (ADC).
PTC6 and PTC5 are general-purpose, bidirectional I/O port pins.
DDAD/VREFH
are the power supply pins to the analog-to-digital converter
are the reference voltage pins for the ADC. V
REFL
)
TX
and V
SSAD/VREFL
. See Section 3. Analog-to-Digital
SS
)
DDAD/VREFH
DD
SSAD/VREFL
REFH
pin should be
. V
REFL
pin should be
is the
is the
PTC4–PTC0 are general-purpose, bidirectional I/O port pins that contain higher
current sink/source capability. PTC6–PTC2 are only available on the 48-pin LQFP
and 64-pin QFP packages. See Section 13. Input/Output (I/O) Ports.
PTC1 and PTC0 can be programmed to be MSCAN08 pins.
These port pins also have selectable pullups when configured for input mode. The
pullups are disengaged when configured for output mode. The pullups are
selectable on an individual port bit basis.
Data Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 — Rev. 1.0
30 General Description MOTOROLA
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