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MC68HC908GZ32
DATA SHEET
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Freescale MC68HC908GZ60, MC68HC908GZ48, MC68HC908GZ32 DATA SHEET

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MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32
Data Sheet
MC68HC908GZ60 Rev. 6.0 04/2007
MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 3
Revision History
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
April, 2004
May, 2004
June,
2005
March,
2006
July,
2006
Revision
Level
N/A Initial release N/A
9.7.3 Keyboard Interrupt Polarity Register — Corrected the bit description of the KBIP7–KBIP0 bits.
14.8.8 ESCI Prescaler Register — Reworked note under PDS2–PDS0 description for clarity.
Table 22-1. MC Order Numbers — Corrected order numbers. 329
Figure 22-1. Device Numbering System — Reworked diagram to reflect
1.0
2.0
3.0
4.0
correct order numbers.
Table A-1. MC Order Numbers — Corrected order numbers. 342
Figure A-3. Device Numbering System — Reworked diagram to reflect correct order numbers.
B.4 Ordering Information — Corrected order numbers. 346
Figure B-3. Device Numbering System — Reworked diagram to reflect correct order numbers.
Reformatted to Freescale publication standards Throughout
Table 14-6. ESCI LIN Control Bits — Corrected Functionality entries 211
14.9.1 ESCI Arbiter Control Register — Corrected bit ACLK bit description 215
14.9.3 Bit Time Measurement — Corrected definition for ACLK bit 216
10.5 Clock Generator Module (CGM) — Updated description to remove erroneous information.
Added section 1.5.15 Unused Pin Termination 31
Chapter 13 Input/Output (I/O) Ports — Replaced note 169
Table 14-6. ESCI LIN Control Bits — Updated functionality column. 213
18.6 TIM1 During Break Interrupts — Updated first paragraph for clarity. 270
19.6 TIM2 During Break Interrupts — Updated first paragraph for clarity. 290
20.2.1.2 TIM During Break Interrupts — Updated first paragraph for clarity. 302
Figure 20-10. Normal Monitor Mode Circuit and Figure 20-11. Forced Monitor Mode — Changed capacitor values
21.5 5.0-Vdc Electrical Characteristics — Updated minimum value for low-voltage inhibit, trip rising voltage (VTRIPR).
21.9.2 CGM Component Information — Updated values for feedback bias resistor
Description
Page
Number(s)
119
212
329
342
346
122
307
317
322
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
4 Freescale Semiconductor
Revision History (Continued)
Date
October,
2006
April,
2007
Revision
Level
5.0
6.0
Description
12.2 Features — Corrected timer link connection from TIM2 channel 0 to TIM1 channel 0.
12.9 Timer Link — Corrected timer link connection from TIM2 channel 0 to TIM1 channel 0.
21.5 5.0-Vdc Electrical Characteristics and
21.6 3.3-Vdc Electrical Characteristics — Updated DC injection current specification.
Figure 2-2. Control, Status, and Data Registers — Changed TBMCLKSEL to
TMBCLKSEL to be compatible with development tool nomenclature
Chapter 5 Configuration Register (CONFIG) — Changed COPCLK to
CGMXCLK and TBMCLKSEL to TMBCLKSEL to be compatible with development tool nomenclature
10.6.2 Stop Mode — Changed COPCLK to CGMXCLK 125
Figure 14-3. ESCI Module Block Diagram — Changed BUS_CLK to BUS
CLOCK and removed reference to 4xBUSCLK
14.4.2 Transmitter — Changed ESCIBDSRC to SCIBDSRC 194
14.9.1 ESCI Arbiter Control Register and 14.9.3 Bit Time Measurement —
Replaced one quarter with one half in the definition for ACLK = 1
Figure 17-1. Timebase Block Diagram, 17.5 TBM Interrupt Rate, and Table 17-1. Timebase Divider Selection — Changed TBMCLKSEL to TMBCLKSEL
to be compatible with development tool nomenclature
21.9 Clock Generation Module (CGM) Characteristics — Updated section to
include the following:
21.9.1 CGM Operating Conditions
21.9.2 CGM Component Information
21.9.3 CGM Acquisition/Lock Time Information
Page
Number(s)
135
147
317 319
37
91 92 93
192
217 218
260 261
322 322 323
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 5
Revision History
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
6 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Chapter 6 Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Chapter 8 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Chapter 10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Chapter 11 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Chapter 12 MSCAN08 Controller (MSCAN08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Chapter 13 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . 189
Chapter 15 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
Chapter 17 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Chapter 18 Timer Interface Module (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Chapter 19 Timer Interface Module (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Chapter 20 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
Chapter 21 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
Chapter 22 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .333
Appendix A MC68HC908GZ48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
Appendix B MC68HC908GZ32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 7
List of Chapters
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
8 Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.2 Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1 Power Supply Pins (V
1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.3 External Reset Pin (RST
1.5.4 External Interrupt Pin (IRQ
1.5.5 CGM Power Supply Pins (V
1.5.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.7 ADC Power Supply/Reference Pins (V
1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8) . . . . . . . . . . . . . . . . 30
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.10 Port C I/O Pins (PTC6–PTC0/CANTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS
1.5.12 Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.13 Port F I/O Pins (PTF7/T2CH5–PTF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.14 Port G I/O Pins (PTG7/AD23–PTBG0/AD16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.15 Unused Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DDA
and V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SSA
DDAD/VREFH
and V
SSAD/VREFL
). . . . . . . . . . . . . . . . 29
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.6 FLASH-1 Memory (FLASH-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.6.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.6.2 FLASH-1 Control and Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.6.2.1 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.6.2.2 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.6.3 FLASH-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.4 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.5 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 9
Table of Contents
2.6.6 FLASH-1 Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.7 FLASH-2 Memory (FLASH-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.7.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.7.2 FLASH-2 Control and Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.7.2.1 FLASH-2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.7.2.2 FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.7.3 FLASH-2 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.7.4 FLASH-2 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.7.5 FLASH-2 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.6 FLASH-2 Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.6 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.7.1 ADC Analog Power Pin (V
3.7.2 ADC Analog Ground Pin (V
3.7.3 ADC Voltage Reference High Pin (V
3.7.4 ADC Voltage Reference Low Pin (V
3.7.5 ADC Voltage In (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADIN
3.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.8.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.8.2 ADC Data Register High and Data Register Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.8.2.1 Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.8.2.2 Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.8.2.3 Left Justified Signed Data Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.8.2.4 Eight Bit Truncation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DDAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SSAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
REFL
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
10 Freescale Semiconductor
Chapter 4
Clock Generator Module (CGM)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.1 Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.5 Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.4 PLL Analog Power Pin (V
4.4.5 PLL Analog Ground Pin (V
4.4.6 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4.8 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.4.9 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.4.10 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.5.3 PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5.4 PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5.5 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.8 Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SSA
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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Chapter 6
Computer Operating Properly (COP) Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Chapter 7
Central Processor Unit (CPU)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 8
External Interrupt (IRQ)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.4 IRQ
8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.7.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.7.3 Keyboard Interrupt Polarity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Chapter 10
Low-Power Modes
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.1.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.2 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.3 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.4 Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.5 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.6 Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7 External Interrupt Module (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.8 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.9 Low-Voltage Inhibit Module (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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10.10 Enhanced Serial Communications Interface Module (ESCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.12 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.14 Scalable Controller Area Network Module (MSCAN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.14.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.15 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.16 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 11
Low-Voltage Inhibit (LVI)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.3.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.3.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.3.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Chapter 12
MSCAN08 Controller (MSCAN08)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.3 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4 Message Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4.2 Receive Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.4.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.6.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.6.2 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
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12.7 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.8.1 MSCAN08 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.8.2 MSCAN08 Soft Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.8.3 MSCAN08 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.8.4 CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.8.5 Programmable Wakeup Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.9 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.12.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.12.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.12.3 Data Length Register (DLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.12.4 Data Segment Registers (DSRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.12.5 Transmit Buffer Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.13 Programmer’s Model of Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.13.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.13.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.13.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.13.4 MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.13.5 MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.13.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.13.7 MSCAN08 Transmitter Flag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.13.8 MSCAN08 Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.13.9 MSCAN08 Identifier Acceptance Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.13.10 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.13.11 MSCAN08 Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.13.12 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.13.13 MSCAN08 Identifier Mask Registers (CIDMR0–CIDMR3). . . . . . . . . . . . . . . . . . . . . . . . . 167
Chapter 13
Input/Output (I/O) Ports
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.2 Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.3.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.5 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.5.3 Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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13.6 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
13.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
13.6.2 Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.6.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
13.8.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
13.8.2 Data Direction Register F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
13.9 Port G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13.9.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13.9.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Chapter 14
Enhanced Serial Communications Interface (ESCI) Module
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
14.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.6 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.7.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.8.1 ESCI Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
14.8.2 ESCI Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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14.8.3 ESCI Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.8.4 ESCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
14.8.5 ESCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
14.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.8.7 ESCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.8.8 ESCI Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
14.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14.9.1 ESCI Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14.9.2 ESCI Arbiter Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
14.9.3 Bit Time Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
14.9.4 Arbitration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Chapter 15
System Integration Module (SIM)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
15.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
15.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
15.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
15.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
15.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
15.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
15.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
15.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
15.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
15.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
15.3.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
15.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
15.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
15.5.1.3 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
15.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
15.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.7.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.7.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
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Table of Contents
Chapter 16
Serial Peripheral Interface (SPI) Module
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.4.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.4.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.4.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
16.4.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
16.5 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
16.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
16.6.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
16.6.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
16.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.8 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
16.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
16.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
16.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.10 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.11.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.11.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.11.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
16.11.4 SS
16.12 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
16.12.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
16.12.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
16.12.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
(Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Chapter 17
Timebase Module (TBM)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
17.5 TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
17.7 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
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Chapter 18
Timer Interface Module (TIM1)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
18.3.1 TIM1 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
18.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
18.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
18.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
18.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
18.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
18.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
18.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
18.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
18.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
18.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
18.6 TIM1 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
18.7 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
18.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
18.8.1 TIM1 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
18.8.2 TIM1 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
18.8.3 TIM1 Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
18.8.4 TIM1 Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
18.8.5 TIM1 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Chapter 19
Timer Interface Module (TIM2)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
19.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
19.3.1 TIM2 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
19.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
19.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
19.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
19.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
19.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
19.6 TIM2 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 19
Table of Contents
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
19.7.1 TIM2 Clock Pin (T2CH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
19.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0) . . . . . . . . . . . . . . . . . . . . . . 290
19.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
19.8.1 TIM2 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
19.8.2 TIM2 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
19.8.3 TIM2 Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
19.8.4 TIM2 Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
19.8.5 TIM2 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Chapter 20
Development Support
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
20.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
20.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
20.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
20.2.2.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
20.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
20.2.2.3 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
20.2.2.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
20.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
20.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
20.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
20.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
20.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
20.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
20.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
20.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Chapter 21
Electrical Specifications
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
21.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
21.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
21.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
21.5 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
21.6 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
21.7 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
21.8 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
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20 Freescale Semiconductor
21.9 Clock Generation Module (CGM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
21.9.1 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
21.9.2 CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
21.9.3 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
21.10 5.0-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
21.11 3.3-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
21.12 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
21.13 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
21.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
21.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Chapter 22
Ordering Information and Mechanical Specifications
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
22.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
22.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Appendix A
MC68HC908GZ48
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
A.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
A.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Appendix B
MC68HC908GZ32
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
B.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
B.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
B.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 21
Table of Contents
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
22 Freescale Semiconductor
Chapter 1 General Description
1.1 Introduction
The MC68HC908GZ60, MC68HC908GZ48, and MC68HC908GZ32 are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
The information contained in this document pertains to all three devices with the exceptions noted in
Appendix A MC68HC908GZ48 and Appendix B MC68HC908GZ32.
1.2 Features
For convenience, features have been organized to reflect:
• Standard features
• Features of the CPU08
1.2.1 Standard Features
Features of the MC68HC908GZ60 include:
• High-performance M68HC08 architecture optimized for C-compilers
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• 8-MHz internal bus frequency
• Clock generation module supporting 1-MHz to 8-MHz crystals
• MSCAN08 (scalable controller area network) controller (implementing 2.0b protocol as defined in BOSCH specification dated September 1991)
• FLASH program memory security
• On-chip programming firmware for use with host personal computer which does not require high voltage for entry
• In-system programming (ISP)
• System protection features: – Optional computer operating properly (COP) reset – Low-voltage detection with optional reset and selectable trip points for 3.3-V and 5.0-V
operation – Illegal opcode detection with reset – Illegal address detection with reset
• Low-power design; fully static with stop and wait modes
(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 23
General Description
• Standard low-power modes of operation: – Wait mode – Stop mode
• Master reset pin and power-on reset (POR)
•On-chip FLASH memory: – MC68HC908GZ60 — 60 Kbytes – MC68HC908GZ48 — 48 Kbytes – MC68HC908GZ32 — 32 Kbytes
• Random-access memory (RAM): – MC68HC908GZ60 — 2048 bytes – MC68HC908GZ48 — 1536 bytes – MC68HC908GZ32 — 1536 bytes
• Serial peripheral interface (SPI) module
• Enhanced serial communications interface (ESCI) module
• One 16-bit, 2-channel timer interface module (TIM1) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel
• One 16-bit, 6-channel timer interface module (TIM2) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel
• Timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external crystal
• 24-channel, 10-bit successive approximation analog-to-digital converter (ADC)
• 8-bit keyboard wakeup port with software selectable rising or falling edge detect, as well as high or low level detection
• Up to 53 general-purpose input/output (I/O) pins, including: – 40 shared-function I/O pins, depending on package choice – Up to 13 dedicated I/O pins, depending on package choice
• Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis. During output mode, pullups are disengaged.
• Internal pullups on IRQ
and RST to reduce customer system cost
• High current 10-mA sink/source capability on all port pins
• Higher current 20-mA sink/source capability on PTC0–PTC4 and PTF0–PTF3
• User selectable clockout feature with divide by 1, 2, and 4 of the bus or crystal frequency
• User selection of having the oscillator enabled or disabled during stop mode
• BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging
• Available packages: – 32-pin low-profile quad flat pack (LQFP) – 48-pin low-profile quad flat pack (LQFP) – 64-pin quad flat pack (QFP)
• Specific features in 32-pin LQFP are: – Port A is only 4 bits: PTA0–PTA3; shared with ADC and KBI modules – Port B is only 6 bits: PTB0–PTB5; shared with ADC module – Port C is only 2 bits: PTC0–PTC1; shared with MSCAN module – Port D is only 7 bits: PTD0–PTD6; shared with SPI, TIM1 and TIM2 modules – Port E is only 2 bits: PTE0–PTE1; shared with ESCI module
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
24 Freescale Semiconductor
• Specific features in 48-pin LQFP are: – Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules – Port B is 8 bits: PTB0–PTB7; shared with ADC module – Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module – Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules – Port E is only 6 bits: PTE0–PTE5; shared with ESCI module
• Specific features in 64-pin QFP are: – Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules – Port B is 8 bits: PTB0–PTB7; shared with ADC module – Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module – Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, andTIM2 modules – Port E is only 6 bits: PTE0–PTE5; shared with ESCI module – Port F is 8 bits: PTF0–PTF7; shared with TIM2 module – Port G is 8 bits; PTG0–PTG7; shared with ADC module
1.2.2 Features of the CPU08
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
MCU Block Diagram
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GZ60. Refer to Appendix A MC68HC908GZ48 and Appendix B MC68HC908GZ32.
1.4 Pin Assignments
Figure 1-2, Figure 1-3, and Figure 1-4 illustrate the pin assignments for the 32-pin LQFP, 48-pin LQFP,
and 64-pin QFP respectively.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 25
General Description
SINGLE BREAKPOINT BREAK
MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODE ENTRY
SERIAL PERIPHERAL
6-CHANNEL TIMER INTERFACE
MODULE
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 62,078 BYTES
USER RAM — 2048 BYTES
MONITOR ROM
USER FLASH VECTOR SPACE — 52 BYTES
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1 OSC2
RST
(1)
IRQ
(1)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7/AD15–
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6
(2)
PTC5
(2)
PTC4
(2, 3)
PTC3
(2, 3)
PTC2
(2, 3)
PTC1/CAN
RX
(2, 3)
PTC0/CAN
TX
(2, 3)
PTD7/T2CH1
(2)
PTD6/T2CH0
(2)
PTD5/T1CH1
(2)
PTD4/T1CH0
(2)
PTD3/SPSCK
(2)
PTD2/MOSI
(2)
PTD1/MISO
(2)
PTD0/SS/MCLK
(2)
PTE1/RxD PTE0/TxD
2-CHANNEL TIMER INTERFACE
MODULE
ENHANCED SERIAL
INTERFACE MODULE
SECURITY
MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
CONFIGURATION REGISTER 1–2
MODULE
POWER
V
SS
V
DD
V
SSA
V
DDA
1. Pin contains integrated pullup device.
2. Ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input.
3. Higher current drive port pins
V
DDAD/VREFH
V
SSAD/VREFL
PTE5–PTE2
COMMUNICATIONS
CLOCK GENERATOR MODULE
CGMXFC
PHASE LOCKED LOOP
1–8 MHz OSCILLATOR
PORTB
DDRB
PTB7/AD7–
PORTF
DDRF
PTF7/T2CH5
MODULE
PORTG
DDRG
PTG7/AD23–
PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2
PTF3–PFT0
(3)
MSCAN
MODULE
PTA0/KBD0/AD8
(2)
PTB0/AD0
PTG0/AD16
Figure 1-1. MC68HC908GZ60 Block Diagram
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
26 Freescale Semiconductor
Figure 1-2. 32-Pin LQFP Pin Assignments
PTD3/SPSCK
PTA3/KBD3/AD1
PTD2/MOSI
PTD1/MISO
PTD0/SS/MCLK
IRQ
PTE1/RxD
PTE0/TxD
RST
PTA2/KBD2/AD10
PTA1/KBD1/AD9
PTA0/KBD0/AD8
V
SSAD/VREFL
V
DDAD/VREFH
PTB5/AD5
PTB4/AD4
PTB3/AD3
OSC1
OSC2
CGMXFC
V
SSAVDDA
PTC1/CANRXPTC0/CAN
TX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
PTB2/AD2
V
SS
V
DD
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
PTB0/AD0
PTB1/AD1
36
37
13
RST
PTD0/SS/MCLK
PTD1/MISO
PTD2/MOSI
PTE0/TxD
PTE1/RxD
PTE2
PTE3
PTE4
PTE5
IRQ
PTC3
PTC2
PTD7/T2CH1
PTD6/T2CH0
PTD5/T1CH1
PTD4/T1CH0
V
DD
V
SS
PTC4
PTB0/AD0
PTB1/AD1
PTA5/KBD5/AD13
PTA6/KBD6/AD14
PTC1/CAN
RX
CGMXFC
V
SSAVDDA
PTA7/KBD7/AD15
PTC0/CAN
TX
PTA4/KBD4/AD12
PTA3/KBD3/AD11
OSC2
12
24
25
V
DDAD/VREFH
V
SSAD/VREFL
PTC5
PTC6
PTA0/KBD0/AD8
PTB4/AD4
PTB5/AD5
PTB3/AD3
PTB6/AD6
PTB7/AD7
PTA1/KBD1/AD9
PTA2/KBD2/AD10
PTB2/AD2
PTD3/SPSCK
48
OSC1
46
45
44
43
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
14
15
16
17
18
19
20
21
22
11
23
35
34
33
32
31
30
29
28
27
26
47
Pin Assignments
Freescale Semiconductor 27
Figure 1-3. 48-Pin LQFP Pin Assignments
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
General Description
PTE4
1
PTE1/RxD
PTE2
PTE5
PTF0
PTF1
PTF2
PTF6/T2CH4
PTF5/T2CH3
PTF4/T2CH2
PTD7/T2CH1
PTD6/T2CH0
PTD5/T1CH1
PTD4/T1CH0
PTG1/AD17
PTG2/AD18
PTG3/AD19
PTC5
PTC6
PTB5/AD5
PTG0/AD16
PTA5/KBD5/AD13
PTG4/AD20
OSC1
PTG7/AD23
PTG6/AD22
PTG5/AD21
PTA2/KBD2/AD10
PTA6/KBD6/AD14
PTA7/KBD7/AD15
17 32
33
49
48
64
PTF3
IRQ
PTD0/SS/MCLK
16
PTD3/SPSCK
PTF7/T2CH5
PTC2
PTC3
PTC4
V
SSAD/VREFL
V
DDAD/VREFH
PTB7/AD7
PTB6/AD6
PTC0/CAN
TX
PTC1/CAN
RX
V
DDA
V
SSA
PTE3
PTD1/MISO
PTD2/MOSI
PTB0/AD0
PTA0/KBD0/AD8
PTA1/KBD1/AD9
OSC2
CGMXFC
RST
PTE0/TxD
V
SS
V
DD
PTB1/AD1
PTB2/AD2
PTB4/AD4
PTB3/AD3
PTA4/KBD4/AD12
PTA3/KBD3/AD11
2
3
4
5
6
7
8
43
42
41
40
39
38
18
19
20 21 22
23
505152535455
9
10
11
24 25 26
27
37
36
35
34
56575859
12
13
14
15
28 29 30 31
44
45
46
47
63 62 61 60
1.5 Pin Functions
Descriptions of the pin functions are provided here.
1.5.1 Power Supply Pins (VDD and VSS)
Figure 1-4. 64-Pin QFP Pin Assignments
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
28 Freescale Semiconductor
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Pin Functions
MCU
V
DD
C2
C1
0.1 μF
V
SS
V
DD
+
Note: Component values shown represent typical applications.
Figure 1-5. Power Supply Bypassing
1.5.2 Oscillator Pins (OSC1 and OSC2)
OSC1 and OSC2 are the connections for an external crystal, resonator, or clock circuit. See Chapter 4
Clock Generator Module (CGM).
1.5.3 External Reset Pin (RST)
A low on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Chapter 15 System Integration Module (SIM).
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See
Chapter 8 External Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (V
V
DDA
and V
are the power supply pins for the analog portion of the clock generator module (CGM).
SSA
DDA
and V
SSA
)
Decoupling of these pins should be as per the digital supply. See Chapter 4 Clock Generator Module
(CGM).
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module
(CGM).
1.5.7 ADC Power Supply/Reference Pins (V
V
DDAD
and V
are the power supply pins to the analog-to-digital converter (ADC). V
SSAD
are the reference voltage pins for the ADC. V the V
DDAD/VREFH
pin should be externally filtered and connected to the same voltage potential as VDD.
DDAD/VREFH
is the high reference supply for the ADC, and by default
REFH
and V
SSAD/VREFL
)
REFH
and V
REFL
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 29
General Description
V
is the low reference supply for the ADC, and by default the V
REFL
to the same voltage potential as V
. See Chapter 3 Analog-to-Digital Converter (ADC).
SS
SSAD/VREFL
pin should be connected
1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8)
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins or used as analog-to-digital inputs. PTA7–PTA4 are only available on the 48-pin LQFP and 64-pin QFP packages. See Chapter 13 Input/Output (I/O) Ports,
Chapter 9 Keyboard Interrupt Module (KBI), and Chapter 3 Analog-to-Digital Converter (ADC).
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs. PTB7–PTB6 are only available on the 48-pin LQFP and 64-pin QFP packages. See Chapter 13 Input/Output (I/O) Ports and Chapter 3 Analog-to-Digital Converter (ADC).
1.5.10 Port C I/O Pins (PTC6–PTC0/CANTX)
PTC6 and PTC5 are general-purpose, bidirectional I/O port pins.
PTC4–PTC0 are general-purpose, bidirectional I/O port pins that contain higher current sink/source capability. PTC6–PTC2 are only available on the 48-pin LQFP and 64-pin QFP packages. See Chapter
13 Input/Output (I/O) Ports.
PTC1 and PTC0 can be programmed to be MSCAN08 pins.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS)
PTD7–PTD0 are special-function, bidirectional I/O port pins. PTD3–PTD0 can be programmed to be serial peripheral interface (SPI) pins, while PTD7–PTD4 can be individually programmed to be timer interface module (TIM1 and TIM2) pins. PTD0 can be used to output a clock, MCLK. PTD7 is only available on the 48-pin LQFP and 64-pin QFP packages. See Chapter 18 Timer Interface Module (TIM1),
Chapter 19 Timer Interface Module (TIM2), Chapter 16 Serial Peripheral Interface (SPI) Module, Chapter 13 Input/Output (I/O) Ports. and Chapter 5 Configuration Register (CONFIG).
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.12 Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD)
PTE5–PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can also be programmed to be enhanced serial communications interface (ESCI) pins. PTE5–PTE2 are only available on the 48-pin LQFP and 64-pin QFP packages. See Chapter 14 Enhanced Serial Communications Interface
(ESCI) Module and Chapter 13 Input/Output (I/O) Ports.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
30 Freescale Semiconductor
Pin Functions
1.5.13 Port F I/O Pins (PTF7/T2CH5–PTF0)
PTF7–PTF4 are special-function, bidirectional I/O port pins that can be individually programmed to be timer interface module (TIM2) pins.
PTF3–PTF0 are general-purpose, bidirectional I/O port pins that contain higher current sink/source capability.
PTF7–PTF0 are only available on the 64-pin QFP package. See Chapter 18 Timer Interface Module
(TIM1), Chapter 19 Timer Interface Module (TIM2), and Chapter 13 Input/Output (I/O) Ports.
1.5.14 Port G I/O Pins (PTG7/AD23–PTBG0/AD16)
PTG7–PTG0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs. PTG7–PTG0 are only available on the 64-pin QFP package. See Chapter 13
Input/Output (I/O) Ports and Chapter 3 Analog-to-Digital Converter (ADC).
1.5.15 Unused Pin Termination
Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess current caused by floating inputs, and enhances immunity during noise or transient events. Termination methods include:
1. Configuring unused pins as outputs and driving high or low;
2. Configuring unused pins as inputs and enabling internal pull-ups;
3. Configuring unused pins as inputs and using external pull-up or pull-down resistors.
Never connect unused pins directly to V
or VSS.
DD
Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method 1 or 2 above are appropriate.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 31
General Description
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
32 Freescale Semiconductor
Chapter 2 Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
• 62,078 bytes of user FLASH memory
• 2048 bytes of random-access memory (RAM)
• 52 bytes of user-defined vectors
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on microcontroller (MCU) operation. In the
Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved
or with the letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$003F, or at $0440–$0461. Additional I/O registers have these addresses:
• $FE00; SIM break status register, BSR
• $FE01; SIM reset status register, SRSR
• $FE02; reserved
• $FE03; SIM break flag control register, BFCR
• $FE04; interrupt status register 1, INT1
• $FE05; interrupt status register 2, INT2
• $FE06; interrupt status register 3, INT3
• $FE07; interrupt status register 4, INT4
• $FE08; FLASH-2 control register, FL2CR
• $FE09; break address register high, BRKH
• $FE0A; break address register low, BRKL
• $FE0B; break status and control register, BRKSCR
• $FE0C; LVI status register, LVISR
• $FE0D; FLASH-2 test control register, FLTCR2
• $FE0E; FLASH-1 test control register, FLTCR1
• $FF80; FLASH-1 block protect register, FL1BPR
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 33
Memory
• $FF81; FLASH-2 block protect register, FL2BPR
• $FF88; FLASH-1 control register, FL1CR
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
$0000
↓
$003F
$0040
↓
$043F
$0440
↓
$0461
$0462
↓
$04FF
$0500
↓
$057F
$0580
↓
$097F
$0980
↓
$1B7F
$1B80
↓
$1DFF
$1E00
↓
$1E0F
$1E10
↓
$1E1F
I/O REGISTERS
64 BYTES
RAM-1
1024 BYTES
I/O REGISTERS
34 BYTES
FLASH-2
158 BYTES
MSCAN CONTROL AND MESSAGE BUFFER
128 BYTES
RAM-2
1024 BYTES
FLASH-2
4608 BYTES $FE20
RESERVED
640 BYTES
MONITOR ROM
16 BYTES
RESERVED
16 BYTES
$FE00 SIM BREAK STATUS REGISTER (BSR)
$FE01 SIM RESET STATUS REGISTER (SRSR)
$FE02 RESERVED
$FE03 SIM BREAK FLAG CONTROL REGISTER (BFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE05 INTERRUPT STATUS REGISTER 2 (INT2)
$FE06 INTERRUPT STATUS REGISTER 3 (INT3)
$FE07 INTERRUPT STATUS REGISTER 4 (INT4)
$FE08 FLASH-2 CONTROL REGISTER (FL2CR)
$FE09 BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0A BREAK ADDRESS REGISTER LOW (BRKL)
$FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0C LVI STATUS REGISTER (LVISR)
$FE0D FLASH-2 TEST CONTROL REGISTER (FLTCR2)
$FE0E FLASH-1 TEST CONTROL REGISTER (FLTCR1)
$FE0F
$FE10
↓
$FE1F
$FF7F
$FF80 FLASH-1 BLOCK PROTECT REGISTER (FL1BPR)
$FF81 FLASH-2 BLOCK PROTECT REGISTER (FL2BPR)
$FF82
$FF87
$FF88 FLASH-1 CONTROL REGISTER (FL1CR)
RESERVED FOR COMPATIBILITY WITH MONITOR CODE
↓
↓
UNIMPLEMENTED
UNIMPLEMENTED
16 BYTES
FOR A-FAMILY PART
MONITOR ROM
352 BYTES
RESERVED
6 BYTES
$1E20
↓
$7FFF
$8000
↓
$FDFF
FLASH-2
25,056 BYTES
FLASH-1
32,256 BYTES
$FF89
↓
$FFCB
$FFCC
↓
$FFFF
RESERVED
67 BYTES
FLASH-1 VECTORS
(1)
1. $FFF6–$FFFD used for eight security bytes
52 BYTES
Figure 2-1. MC68HC908GZ60 Memory Map
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
34 Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
(PTA)
Reset: Unaffected by reset
Read:
(PTB)
Write:
Reset: Unaffected by reset
Read: 1
(PTC)
Write:
Reset: Unaffected by reset
Read:
(PTD)
Write:
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0 0
(PTE)
Write:
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0
Write:
Reset:00000000
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
PDS2 PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0
AM1
ALOST
= Unimplemented R = Reserved U = Unaffected
AM0 ACLK
AFIN ARUN AROVFL ARD8
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Port A Data Register
See page 173.
Port B Data Register
See page 176.
Port C Data Register
See page 178.
Port D Data Register
See page 180.
Data Direction Register A
(DDRA)
See page 174.
Data Direction Register B
(DDRB)
See page 176.
Data Direction Register C
(DDRC)
See page 178.
Data Direction Register D
(DDRD)
See page 181.
Port E Data Register
See page 183.
ESCI Prescaler Register
(SCPSC)
See page 214.
ESCI Arbiter Control Register (SCIACTL)
See page 217.
ESCI Arbiter Data
Register (SCIADAT)
See page 218.
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 35
Memory
Addr.Register Name Bit 7654321Bit 0
Read: 0 0
Write:
Reset:00000000
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
Read: 0
Write:
Reset:00000000
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:00000000
Read:
Write:
Reset:00101000
Read: SPRF
Write:
Reset:00001000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: R8
Write:
Reset:U0000000
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read: 000000BKFRPF
Write:
Reset:00000000
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
ERRIE
T8 R R ORIE NEIE FEIE PEIE
= Unimplemented R = Reserved U = Unaffected
DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
OVRF MODF SPTE
MODFEN SPR1 SPR0
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
Data Direction Register E
(DDRE)
See page 184.
Port A Input Pullup Enable
Register (PTAPUE)
See page 175.
Port C Input Pullup Enable
Register (PTCPUE)
See page 180.
Port D Input Pullup Enable
Register (PTDPUE)
See page 182.
SPI Control Register
(SPCR)
See page 255.
SPI Status and Control
Register (SPSCR)
See page 256.
SPI Data Register
(SPDR)
See page 258.
ESCI Control Register 1
(SCC1)
See page 204.
ESCI Control Register 2
(SCC2)
See page 206.
ESCI Control Register 3
(SCC3)
See page 208.
ESCI Status Register 1
(SCS1)
See page 209.
ESCI Status Register 2
(SCS2)
See page 211.
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
36 Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Read:
Write:
LINT LINR SCP1 SCP0 R SCR2 SCR1 SCR0
Reset:00000000
Read: 0000KEYF 0
Write:
ACKK
IMASKK MODEK
Reset:00000000
Read:
Write:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Reset:00000000
Read: TBIF
Write:
TBR2 TBR1 TBR0
0
TACK
TBIE TBON R
Reset:00000000
Read: 0000IRQF0
Write:
ACK
IMASK MODE
Reset:00000000
Read: 0
(1)
Write:
MCLKSEL MCLK1 MCLK0
MSCAN-
(1)
EN
TMBCLK-
SEL
OSCENIN-
STOP
SCIBDSRC
$0018
ESCI Baud Rate Register
$0019
Keyboard Status and Control
$001A
Register (INTKBSCR)
Keyboard Interrupt Enable
$001B
Register (INTKBIER)
Timebase Module Control
$001C
IRQ Status and Control
$001D
Configuration Register 2
$001E
ESCI Data Register
(SCDR)
See page 212.
(SCBR)
See page 212.
See page 120.
See page 121.
Register (TBCR)
See page 262.
Register (INTSCR)
See page 114.
(CONFIG2)
See page 92.
Reset:00000001
$001F
Configuration Register 1
(CONFIG1)
See page 93.
Read:
(1)
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3
Write:
Reset:00000000
(1)
SSREC STOP COPD
1. One-time writable register after each reset, except MSCANEN and LVI5OR3 bits. MSCANEN andLVI5OR3 bits are only reset via POR (power-on reset).
$0020
$0021
$0022
$0023
TIM1 Status and Control
Register (T1SC)
See page 271.
TIM1 Counter
Register High (T1CNTH)
See page 273.
TIM1 Counter
Register Low (T1CNTL)
See page 273.
TIM1 Counter Modulo
Register High (T1MODH)
See page 273.
Read: TOF
Write: 0 TRST
TOIE TSTOP
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
Reset:11111111
00
PS2 PS1 PS0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 37
Memory
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset:11111111
Read: CH0F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Bit 7654321Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TOIE TSTOP
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
0
MS1A ELS1B ELS1A TOV1 CH1MAX
00
PS2 PS1 PS0
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
TIM1 Counter Modulo
Register Low (T1MODL)
See page 273.
TIM1 Channel 0 Status and
Control Register (T1SC0)
See page 274.
TIM1 Channel 0
Register High (T1CH0H)
See page 277.
TIM1 Channel 0
Register Low (T1CH0L)
See page 277.
TIM1 Channel 1 Status and
Control Register (T1SC1)
See page 274.
TIM1 Channel 1
Register High (T1CH1H)
See page 277.
TIM1 Channel 1
Register Low (T1CH1L)
See page 277.
TIM2 Status and Control
Register (T2SC)
See page 291.
TIM2 Counter
Register High (T2CNTH)
See page 292.
TIM2 Counter
Register Low (T2CNTL)
See page 292.
TIM2 Counter Modulo
Register High (T2MODH)
See page 293.
TIM2 Counter Modulo
Register Low (T2MODL)
See page 293.
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
38 Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
TIM2 Channel 0 Status and
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B Reserved
Control Register (T2SC0)
See page 293.
TIM2 Channel 0
Register High (T2CH0H)
See page 297.
TIM2 Channel 0
Register Low (T2CH0L)
See page 297.
TIM2 Channel 1 Status and
Control Register (T2SC1)
See page 293.
TIM2 Channel 1
Register High (T2CH1H)
See page 297.
TIM2 Channel 1
Register Low (T2CH1L)
See page 297.
PLL Control Register
(PCTL)
See page 83.
PLL Bandwidth Control
Register (PBWC)
See page 85.
PLL Multiplier Select High
Register (PMSH)
See page 86.
PLL Multiplier Select Low
Register (PMSL)
See page 86.
PLL VCO Select Range
Register (PMRS)
See page 87.
Read: CH0F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset:00100000
Read:
Write:
Reset:00000000
Read: 0000
Write:
Reset:00000000
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read: 0000
Write:
Reset:00000001
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
PLLIE
AUTO
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
CH1IE
PLLF
LOCK
= Unimplemented R = Reserved U = Unaffected
0
PLLON BCS R R VPR1 VPR0
ACQ
MS1A ELS1B ELS1A TOV1 CH1MAX
0000
MUL11 MUL10 MUL9 MUL8
RRRR
R
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 39
Memory
Addr.Register Name Bit 7654321Bit 0
Read: COCO
Write: R
Reset:00011111
Read: 000000AD9AD8
Write:
Reset: Unaffected by reset
Read: AD7 AD6 AD5 AD4 A3 AD2 AD1 AD0
Write:
Reset: Unaffected by reset
Read:
Write:
Reset:00000100
Read:
Write:
(PTF)
Reset: Unaffected by reset
Read:
Write:
(PTG)
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: CH2F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R
PTF7 PTF6 PTF5 PTF4 PTAF3 PTF2 PTF1 PTF0
PTG7 PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0
KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
= Unimplemented R = Reserved U = Unaffected
0
$003C
$003D
$003E
$003F
$0440
$0441
$0444
$0445
$0448
$0456
$0457
$0458
ADC Status and Control
Register (ADSCR)
See page 68.
ADC Data High Register
(ADRH)
See page 70.
ADC Data Low Register
(ADRL)
See page 70.
ADC Clock Register
(ADCLK)
See page 72.
Port F Data Register
See page 185.
Port G Data Register
See page 186.
Data Direction Register F
(DDRF)
See page 185.
Data Direction Register G
(DDRG)
See page 187.
Keyboard Interrupt
Polarity Register
(INTKBIPR)
See page 121.
TIM2 Channel 2 Status and
Control Register (T2SC2)
See page 297.
TIM2 Channel 2
Register High (T2CH2H)
See page 297.
TIM2 Channel 2
Register Low (T2CH2L)
See page 297.
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
40 Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
TIM2 Channel 3 Status and
$0459
$045A
$045B
$045C
$045D
$045E
$045F
$0460
$0461
$FE00
1. Writing a 0 clears SBSW.
Control Register (T2SC3)
See page 293.
TIM2 Channel 3
Register High (T2CH3H)
See page 297.
TIM2 Channel 3
Register Low (T2CH3L)
See page 297.
TIM2 Channel 4 Status and
Control Register (T2SC4)
See page 293.
TIM2 Channel 4
Register High (T2CH4H)
See page 297.
TIM2 Channel 4
Register Low (T2CH4L)
See page 297.
TIM2 Channel 5 Status and
Control Register (T2SC5)
See page 293.
TIM2 Channel 5
Register High (T2CH5H)
See page 297.
TIM2 Channel 5
Register Low (T2CH5L)
See page 297.
Break Status Register
See page 237.
Read: CH3F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH4F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH5F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write: NOTE 1
(BSR)
Reset:00000000
Bit 15 14 13 12 11 10 9 Bit 8
Bit 765432 1Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321 Bit 0
RRRRRR
CH3IE
CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX
CH5IE
0
0
MS3A ELS3B ELS3A TOV3 CH3MAX
MS5A ELS5B ELS5A TOV 5 CH5MAX
SBSW
R
SIM Reset Status Register
$FE01
$FE02 Reserved
(SRSR)
See page 237.
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
Read:
Write:
Reset:00000000
RRRRRRRR
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 41
Memory
Addr.Register Name Bit 7654321Bit 0
Break Flag Control Register
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
Interrupt Status Register 3
$FE06
Interrupt Status Register 4
$FE07
FLASH-2 Control Register
$FE08
Break Address Register High
$FE09
Break Address Register Low
$FE0A
Break Status and Control
$FE0B
$FE0C
$FE0D
$FE0E
FLASH-2 Test Control
FLASH-1 Test Control
(BFCR)
See page 238.
See page 231.
See page 233.
See page 233.
See page 233.
(FL2CR)
See page 53.
(BRKH)
See page 303.
(BRKL)
See page 303.
Register (BRKSCR)
See page 303.
LVI Status Register
(LVISR)
See page 133.
Register (FLTCR2)
Register (FLTCR1)
Read:
Write:
Reset:00000000
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
(INT1)
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
(INT2)
Write:RRRRRRRR
Reset:00000000
Read: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15
(INT3)
Write:RRRRRRRR
Reset:00000000
Read: 000000IF24IF23
(INT4)
Write:RRRRRRRR
Reset:00000000
Read: 0000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: LVIOUT 0000000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
BCFERRRRRRR
HVEN MASS ERASE PGM
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
BRKE BRKA
RRRRRRRR
RRRRRRRR
= Unimplemented R = Reserved U = Unaffected
000000
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
42 Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
$FF80
$FF81
FLASH-1 Block Protect
Register (FL1BPR)
See page 47.
FLASH-2 Block Protect
Register (FL2BPR)
See page 54.
(1)
Read:
Write:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Reset: Unaffected by reset
(1)
Read:
Write:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Reset: Unaffected by reset
1. Non-volatile FLASH register
Read: 0000
Write:
HVEN MASS ERASE PGM
Reset:00000000
$FF88
FLASH-1 Control Register
(FL1CR)
See page 46.
$FFFF
COP Control Register
(COPCTL)
See page 97.
Read: Low byte of reset vector
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
Table 2-1. Vector Addresses
.
Vector Priority Vector Address Vector
Lowest
IF24
IF23
IF22
IF21
IF20
IF19
IF18
IF17
IF16
$FFCC TIM2 Channel 5 Vector (High)
$FFCD TIM2 Channel 5 Vector (Low)
$FFCE TIM2 Channel 4 Vector (High)
$FFCF TIM2 Channel 4 Vector (Low)
$FFD0 TIM2 Channel 3 Vector (High)
$FFD1 TIM2 Channel 3 Vector (Low)
$FFD2 TIM2 Channel 2 Vector (High)
$FFD3 TIM2 Channel 2 Vector (Low)
$FFD4 MSCAN08 Transmit Vector (High)
$FFD5 MSCAN08 Transmit Vector (Low)
$FFD6 MSCAN08 Receive Vector (High)
$FFD7 MSCAN08 Receive Vector (Low)
$FFD8 MSCAN08 Error Vector (High)
$FFD9 MSCAN08 Error Vector (Low)
$FFDA MSCAN08 Wakeup Vector (High)
$FFDB MSCAN08 Wakeup Vector (Low)
$FFDC Timebase Vector (High)
$FFDD Timebase Vector (Low)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 43
Memory
Table 2-1. Vector Addresses (Continued)
Vector Priority Vector Address Vector
$FFDE ADC Conversion Complete Vector (High)
$FFDF ADC Conversion Complete Vector (Low)
$FFE0 Keyboard Vector (High)
$FFE1 Keyboard Vector (Low)
$FFE2 ESCI Transmit Vector (High)
$FFE3 ESCI Transmit Vector (Low)
$FFE4 ESCI Receive Vector (High)
$FFE5 ESCI Receive Vector (Low)
$FFE6 ESCI Error Vector (High)
$FFE7 ESCI Error Vector (Low)
$FFE8 SPI Transmit Vector (High)
$FFE9 SPI Transmit Vector (Low)
$FFEA SPI Receive Vector (High)
$FFEB SPI Receive Vector (Low)
$FFEC TIM2 Overflow Vector (High)
$FFED TIM2 Overflow Vector (Low)
$FFEE TIM2 Channel 1 Vector (High)
$FFEF TIM2 Channel 1 Vector (Low)
$FFF0 TIM2 Channel 0 Vector (High)
$FFF1 TIM2 Channel 0 Vector (Low)
$FFF2 TIM1 Overflow Vector (High)
$FFF3 TIM1 Overflow Vector (Low)
$FFF4 TIM1 Channel 1 Vector (High)
$FFF5 TIM1 Channel 1 Vector (Low)
$FFF6 TIM1 Channel 0 Vector (High)
$FFF7 TIM1 Channel 0 Vector (Low)
$FFF8 PLL Vector (High)
$FFF9 PLL Vector (Low)
$FFFA IRQ
$FFFB IRQ
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
$FFFF Reset Vector (Low)
Vector (High)
Vector (Low)
Highest
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
—
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
44 Freescale Semiconductor
Random-Access Memory (RAM)
2.5 Random-Access Memory (RAM)
The RAM locations are broken into two non-continuous memory blocks. The RAM addresses locations are $0040–$043F and $0580–$097F. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
2.6 FLASH-1 Memory (FLASH-1)
This subsection describes the operation of the embedded FLASH-1 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
2.6.1 Functional Description
The FLASH-1 memory is an array of 32,256 bytes with two bytes of block protection (one byte for protecting areas within FLASH-1 array and one byte for protecting areas within FLASH-2 array) and an additional 52 bytes of user vectors. An erased bit reads as a 1 and a programmed bit reads as a 0.
Memory in the FLASH-1 array is organized into rows within pages. There are two rows of memory per page with 64 bytes per row. The minimum erase block size is a single page,128 bytes. Programming is performed on a per-row basis, 64 bytes at a time. Program and erase operations are facilitated through control bits in the FLASH-1 control register (FL1CR). Details for these operations appear later in this subsection.
The FLASH-1 memory map consists of:
• $8000–$FDFF: user memory (32,256 bytes)
• $FF80: FLASH-1 block protect register (FL1BPR)
• $FF81: FLASH-2 block protect register (FL2BPR)
• $FF88: FLASH-1 control register (FL1CR)
• $FFCC–$FFFF: these locations are reserved for user-defined interrupt and reset vectors (see
Table 2-1 for details)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 45
Memory
Programming tools are available from Freescale. Contact your local Freescale representative for more information.
NOTE
A security feature prevents viewing of the FLASH contents.
(1)
2.6.2 FLASH-1 Control and Block Protect Registers
The FLASH-1 array has two registers that control its operation, the FLASH-1 control register (FL1CR) and the FLASH-1 block protect register (FL1BPR).
2.6.2.1 FLASH-1 Control Register
The FLASH-1 control register (FL1CR) controls FLASH program and erase operations.
Address: $FF88
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
Figure 2-3. FLASH-1 Control Register (FL1CR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off
HVEN MASS ERASE PGM
MASS — Mass Erase Control Bit
Setting this read/write bit configures the FLASH-1 array for mass erase operation.
1 = MASS erase operation selected 0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected 0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected 0 = Program operation unselected
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
46 Freescale Semiconductor
FLASH-1 Memory (FLASH-1)
1
FLBPR VALUE
16-BIT MEMORY ADDRESS
0000000
START ADDRESS OF FLASH
BLOCK PROTECT
2.6.2.2 FLASH-1 Block Protect Register
The FLASH-1 block protect register (FL1BPR) is implemented as a byte within the FLASH-1 memory; therefore, it can only be written during a FLASH programming sequence. The value in this register determines the starting location of the protected range within the FLASH-1 memory.
Address: $FF80
Bit 7654321Bit 0
Read:
Write:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Unaffected by reset
Figure 2-4. FLASH-1 Block Protect Register (FL1BPR)
FL1BPR[7:0] — Block Protect Register Bits 7 to 0
These eight bits represent bits [14:7] of a 16-bit memory address. Bit 15 is a 1 and bits [6:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH-1 memory for block
protection. FLASH-1 is protected from this start address to the end of FLASH-1 memory at $FFFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-1 array.
Figure 2-5. FLASH-1 Block Protect Start Address
Table 2-2. FLASH-1 Protected Ranges
FL1BPR[7:0] Protected Range
$FF No protection
$FE $FF00–$FFFF
$FD
↓
$0B
$0A $8500–$FFFF
$09 $8480–$FFFF
$08
↓
$04
$03 $8180–$FFFF
$02 $8100–$FFFF
$01 $8080–$FFFF
$00 $8000–$FFFF
$FE80–$FFFF
↓
$8580–$FFFF
$8400–$FFFF
↓
$8200–$FFFF
Decreasing the value in FL1BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $FF00–$FFFF are protected in FLASH-1.
The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range. Refer to Figure 2-1 and make sure that the desired locations are protected.
Freescale Semiconductor 47
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Memory
2.6.3 FLASH-1 Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by using the FLASH-1 block protection register (FL1BPR). FL1BPR determines the range of the FLASH-1 memory which is to be protected. The range of the protected area starts from a location defined by FL1BPR and ends at the bottom of the FLASH-1 memory ($FFFF). When the memory is protected, the HVEN bit can not be set in either ERASE or PROGRAM operations.
NOTE
In performing a program or erase operation, the FLASH-1 block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit.
When the FLASH-1 block protect register is programmed with all 0’s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within FL1BPR are programmed (0), they lock a block of memory address ranges as shown in
Figure 2-4. If FL1BPR is programmed with any value other than $FF, the protected block of FLASH
memory can not be erased or programmed.
NOTE
The vector locations and the FLASH block protect registers are located in the same page. FL1BPR and FL2BPR are not protected with special hardware or software. Therefore, if this page is not protected by FL1BPR and the vector locations are erased by either a page or a mass erase operation, then both FL1BPR and FL2BPR will also get erased.
2.6.4 FLASH-1 Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH-1 memory:
1. Set both the ERASE bit and the MASS bit in the FLASH-1 control register (FL1CR).
2. Read the FLASH-1 block protect register (FL1BPR).
NOTE
Mass erase is disabled whenever any block is protected (FL1BPR does not equal $FF).
3. Write to any FLASH-1 address within the FLASH-1 array with any data.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE and MASS bits.
8. Wait for a time, t
9. Clear the HVEN bit.
10. Wait for a time, t
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
same FLASH array.
(minimum 10 μs).
NVS
MERASE
NVHL
RCV
(minimum 4 ms).
(minimum 100 μs).
, (typically 1 μs) after which the memory can be accessed in normal read mode.
NOTES
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
48 Freescale Semiconductor
FLASH-1 Memory (FLASH-1)
B. While these operations must be performed in the order shown, other unrelated operations may occur
between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase operations.
2.6.5 FLASH-1 Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH-1 memory:
1. Set the ERASE bit and clear the MASS bit in the FLASH-1 control register (FL1CR).
2. Read the FLASH-1 block protect register (FL1BPR).
3. Write any data to any FLASH-1 address within the address range of the page (128 byte block) to be erased.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Clear the ERASE bit.
8. Wait for time, t
9. Clear the HVEN bit.
10. Wait for a time, t
(minimum 10 μs).
NVS
(minimum 1 ms or 4 ms).
ERASE
(minimum 5 μs).
NVH
, (typically 1 μs) after which the memory can be accessed in normal read mode.
RCV
NOTES
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
same FLASH array.
B. While these operations must be performed in the order shown, other unrelated operations may occur
between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase operations.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.
2.6.6 FLASH-1 Program Operation
Programming of the FLASH-1 memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows:
• $XX00 to $XX3F
• $XX40 to $XX7F
• $XX80 to $XXBF
• $XXC0 to $XXFF
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 49
Memory
During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail.
Use this step-by-step procedure to program a row of FLASH-1 memory.
NOTE
Only bytes which are currently $FF may be programmed.
1. Set the PGM bit in the FLASH-1 control register (FL1CR). This configures the memory for program operation and enables the latching of address and data programming.
2. Read the FLASH-1 block protect register (FL1BPR).
3. Write to any FLASH-1 address within the row address range desired with any data.
4. Wait for time, t
(minimum 10 μs).
NVS
5. Set the HVEN bit.
6. Wait for time, t
(minimum 5 μs).
PGS
7. Write data byte to the FLASH-1 address to be programmed.
8. Wait for time, t
(minimum 30 μs).
PROG
9. Repeat steps 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, t
(minimum 5 μs)
NVH
12. Clear the HVEN bit.
13. Wait for a time, t
, (typically 1 μs) after which the memory can be accessed in normal read mode.
RCV
The FLASH programming algorithm flowchart is shown in Figure 2-6.
NOTES
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
same FLASH array.
B. While these operations must be performed in the order shown, other unrelated operations may occur
between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase operations.
D. Do not exceed t
programming time to the same row before next erase. t
t
NVS
+ t
NVH
+ t
maximum or t
PROG
+ (t
PGS
PROG
X
64) ≤ t
maximum. t
HV
HV
HV
maximum
is defined as the cumulative high voltage
must satisfy this condition:
HV
E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH
address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, t
PROG
maximum.
F. Be cautious when programming the FLASH-1 array to ensure that non-FLASH locations are not used
as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
50 Freescale Semiconductor
FLASH-1 Memory (FLASH-1)
SET HVEN BIT
READ THE FLASH BLOCK
WAIT FOR A TIME, t
NVS
SET PGM BIT
WAIT FOR A TIME, t
PGS
WAIT FOR A TIME, t
PROG
CLEAR PGM BIT
CLEAR HVEN BIT
COMPLETED
PROGRAMMING
THIS ROW?
YES
NO
END OF PROGRAMMING
1
2
3
4
5
6
7
8
10
11
12
13
Algorithm for programming a row (64 bytes) of FLASH memory
PROTECT REGISTER
WRITE ANY DATA TO ANY FLASH
ADDRESS WITHIN THE ROW
ADDRESS RANGE DESIRED
WRITE DATA TO THE FLASH
ADDRESS TO BE PROGRAMMED
WAIT FOR A TIME, t
NVH
WAIT FOR A TIME, t
RCV
NOTES:
The time between each FLASH address change (step 7 to step 7) or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step10) must not exceed the maximum programming time, t
PROG
, maximum.
This row program algorithm assumes the row/s to be programmed are initially erased.
Figure 2-6. FLASH-1 Programming Algorithm Flowchart
Freescale Semiconductor 51
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Memory
2.6.7 Low-Power Modes
The WAIT and STOP instructions will place the MCU in low power-consumption standby modes.
2.6.7.1 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. Wait mode will suspend any FLASH program/erase operations and leave the memory in a standby mode.
2.6.7.2 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a standby mode.
NOTE
Standby mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum.
2.7 FLASH-2 Memory (FLASH-2)
This subsection describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
2.7.1 Functional Description
The FLASH-2 memory is a non-continuous array consisting of a total of 29,822 bytes. An erased bit reads as a 1 and a programmed bit reads as a 0.
Memory in the FLASH-2 array is organized into rows within pages. There are two rows of memory per page with 64 bytes per row. The minimum erase block size is a single page,128 bytes. Programming is performed on a per-row basis, 64 bytes at a time. Program and erase operations are facilitated through control bits in the FLASH-2 control register (FL2CR). Details for these operations appear later in this subsection.
The FLASH-2 memory map consists of:
• $0462–$04FF: user memory (158 bytes)
• $0980–$1B7F: user memory (4608 bytes)
• $1E20–$7FFF: user memory (25056 bytes)
• $FF81: FLASH-2 block protect register (FL2BPR)
NOTE
FL2BPR physically resides within FLASH-1 memory addressing space
• $FE08: FLASH-2 control register (FL2CR)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
52 Freescale Semiconductor
FLASH-2 Memory (FLASH-2)
Programming tools are available from Freescale. Contact your local Freescale representative for more information.
NOTE
A security feature prevents viewing of the FLASH contents.
(1)
2.7.2 FLASH-2 Control and Block Protect Registers
The FLASH-2 array has two registers that control its operation, the FLASH-2 control register (FL2CR) and the FLASH-2 block protect register (FL2BPR).
2.7.2.1 FLASH-2 Control Register
The FLASH-2 control register (FL2CR) controls FLASH-2 program and erase operations.
Address: $FE08
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
Figure 2-7. FLASH-2 Control Register (FL2CR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off
HVEN MASS ERASE PGM
MASS — Mass Erase Control Bit
Setting this read/write bit configures the FLASH-2 array for mass or page erase operation.
1 = Mass erase operation selected 0 = Page erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time.
1 = Erase operation selected 0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected 0 = Program operation unselected
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 53
Memory
0
FLBPR VALUE
16-BIT MEMORY ADDRESS
0000000
START ADDRESS OF FLASH
BLOCK PROTECT
2.7.2.2 FLASH-2 Block Protect Register
The FLASH-2 block protect register (FL2BPR) is implemented as a byte within the FLASH-1 memory; therefore, can only be written during a FLASH-1 programming sequence. The value in this register determines the starting location of the protected range within the FLASH-2 memory.
Address: $FF81
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-8. FLASH-2 Block Protect Register (FL2BPR)
NOTE
The FLASH-2 block protect register (FL2BPR) controls the block protection for the FLASH-2 array. However, FL2BPR is implemented within the FLASH-1 memory array and therefore, the FLASH-1 control register (FL1CR) must be used to program/erase FL2BPR.
FL2BPR[7:0] — Block Protect Register Bits 7 to 0
These eight bits represent bits [14:7] of a 16-bit memory address. Bit 15 is a 0 and bits [6:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH-2 memory for block
protection. FLASH-2 is protected from this start address to the end of FLASH-2 memory at $7FFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-2 array.
Figure 2-9. FLASH-2 Block Protect Start Address
Table 2-3. FLASH-2 Protected Ranges
FL2BPR[7:0] Protected Range
$FF No Protection
$FE $7F00–$7FFF
$FD
↓
$0B
$0A $0500–$7FFF
$09 $0480–$7FFF
$08
↓
$04
$03 $0462–$7FFF
$02 $0462–$7FFF
$01 $0462–$7FFF
$00 $0462–$7FFF
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
$7E80–$7FFF
↓
$0580–$7FFF
$0462–$7FFF
↓
$0462–$7FFF
54 Freescale Semiconductor
FLASH-2 Memory (FLASH-2)
Decreasing the value in FL2BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $7F00–$7FFF are protected in FLASH-2.
The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range. Refer to Figure 2-1 and make sure that the desired locations are protected.
2.7.3 FLASH-2 Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by using the FLASH-2 block protection register (FL2BPR). FL2BPR determines the range of the FLASH-2 memory which is to be protected. The range of the protected area starts from a location defined by FL2BPR and ends at the bottom of the FLASH-2 memory ($7FFF). When the memory is protected, the HVEN bit can not be set in either ERASE or PROGRAM operations.
NOTE
In performing a program or erase operation, the FLASH-2 block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit.
When the FLASH-2 block protect register is programmed with all 0’s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within FL2BPR are programmed (0), they lock a block of memory address ranges as shown in
2.7.2.2 FLASH-2 Block Protect Register. If FL2BPR is programmed with any value other than $FF, the
protected block of FLASH memory can not be erased or programmed.
NOTE
The vector locations and the FLASH block protect registers are located in the same page. FL1BPR and FL2BPR are not protected with special hardware or software. Therefore, if this page is not protected by FL1BPR and the vector locations are erased by either a page or a mass erase operation, both FL1BPR and FL2BPR will also get erased.
2.7.4 FLASH-2 Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH-2 memory:
1. Set both the ERASE bit and the MASS bit in the FLASH-2 control register (FL2CR).
2. Read the FLASH-2 block protect register (FL2BPR).
NOTE
Mass erase is disabled whenever any block is protected (FL2BPR does not equal $FF).
3. Write to any FLASH-2 address within the FLASH-2 array with any data.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE and MASS bits.
(minimum 10 μs).
NVS
MERASE
(minimum 4 ms).
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 55
Memory
8. Wait for a time, t
(minimum 100 μs).
NVHL
9. Clear the HVEN bit.
10. Wait for a time, t
, (typically 1 μs) after which the memory can be accessed in normal read mode.
RCV
NOTES
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
same FLASH array.
B. While these operations must be performed in the order shown, other unrelated operations may occur
between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase operations.
2.7.5 FLASH-2 Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH-2 memory:
1. Set the ERASE bit and clear the MASS bit in the FLASH-2 control register (FL2CR).
2. Read the FLASH-2 block protect register (FL2BPR).
3. Write any data to any FLASH-2 address within the address range of the page (128 byte block) to be erased.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Clear the ERASE bit.
8. Wait for time, t
9. Clear the HVEN bit.
10. Wait for a time, t
(minimum 10 μs).
NVS
(minimum 1 ms or 4 ms).
ERASE
(minimum 5 μs).
NVH
, (typically 1 μs) after which the memory can be accessed in normal read mode.
RCV
NOTES
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
same FLASH array.
B. While these operations must be performed in the order shown, other unrelated operations may occur
between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase operations.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
56 Freescale Semiconductor
FLASH-2 Memory (FLASH-2)
2.7.6 FLASH-2 Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows:
• $XX00 to $XX3F
• $XX40 to $XX7F
• $XX80 to $XXBF
• $XXC0 to $XXFF
During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail.
NOTE
Only bytes which are currently $FF may be programmed.
Use this step-by-step procedure to program a row of FLASH-2 memory:
1. Set the PGM bit in the FLASH-2 control register (FL2CR). This configures the memory for program operation and enables the latching of address and data programming.
2. Read the FLASH-2 block protect register (FL2BPR).
3. Write to any FLASH-2 address within the row address range desired with any data.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Write data byte to the FLASH-2 address to be programmed.
8. Wait for time, t
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, t
12. Clear the HVEN bit.
13. Wait for a time, t
The FLASH programming algorithm flowchart is shown in Figure 2-10.
(minimum 10 μs).
NVS
(minimum 5 μs).
PGS
PROG
NVH
(minimum 30 μs).
(minimum 5 μs).
, (typically 1 μs) after which the memory can be accessed in normal read mode.
RCV
NOTES
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
same FLASH array.
B. While these operations must be performed in the order shown, other unrelated operations may occur
between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase operations.
D. Do not exceed t
PROG
maximum or t
programming time to the same row before next erase. t
t
+ t
NVS
Freescale Semiconductor 57
+ t
NVH
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
PGS
+ (t
PROG
X
64) ≤ t
maximum. t
HV
maximum
HV
is defined as the cumulative high voltage
HV
must satisfy this condition:
HV
Memory
E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH
address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, t
PROG
maximum.
F. Be cautious when programming the FLASH-2 array to ensure that non-FLASH locations are not used
as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm.
2.7.7 Low-Power Modes
The WAIT and STOP instructions will place the MCU in low power-consumption standby modes.
2.7.7.1 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. Wait mode will suspend any FLASH program/erase operations and leave the memory in a standby mode.
2.7.7.2 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a standby mode.
NOTE
Standby mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
58 Freescale Semiconductor
FLASH-2 Memory (FLASH-2)
SET HVEN BIT
READ THE FLASH BLOCK
WAIT FOR A TIME, t
NVS
SET PGM BIT
WAIT FOR A TIME, t
PGS
WAIT FOR A TIME, t
PROG
CLEAR PGM BIT
CLEAR HVEN BIT
COMPLETED
PROGRAMMING
THIS ROW?
YES
NO
END OF PROGRAMMING
1
2
3
4
5
6
7
8
10
11
12
13
Algorithm for programming a row (64 bytes) of FLASH memory
PROTECT REGISTER
WRITE ANY DATA TO ANY FLASH
ADDRESS WITHIN THE ROW
ADDRESS RANGE DESIRED
WRITE DATA TO THE FLASH
ADDRESS TO BE PROGRAMMED
WAIT FOR A TIME, t
NVH
WAIT FOR A TIME, t
RCV
NOTES:
The time between each FLASH address change (step 7 to step 7) or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step10) must not exceed the maximum programming time, t
PROG
, maximum.
This row program algorithm assumes the row/s to be programmed are initially erased.
Figure 2-10. FLASH-2 Programming Algorithm Flowchart
Freescale Semiconductor 59
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Memory
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
60 Freescale Semiconductor
Chapter 3 Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the 10-bit analog-to-digital converter (ADC).
3.2 Features
Features of the ADC module include:
• 24 channels with multiplexed input
• Linear successive approximation with monotonicity
• 10-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
• Left or right justified result
• Left justified sign data mode
3.3 Functional Description
The ADC provides 24 pins for sampling external sources at pins PTG7/AD23–PTG0/AD16, PTA7/KBD7/AD15–PTA0/KBD0/AD8, and PTB7/AD7–PTB0/AD0. An analog multiplexer allows the single ADC converter to select one of 24 ADC channels as ADC voltage in (V the successive approximation register-based analog-to-digital converter. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See
Figure 3-2.
3.3.1 ADC Port I/O Pins
PTG7/AD23–PTG0/AD16, PTA7/KBD7/AD15–PTA0/KBD0/AD8, and PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. A read of a port pin in use by the ADC will return a 0.
ADIN
). V
is converted by
ADIN
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 61
Analog-to-Digital Converter (ADC)
SINGLE BREAKPOINT BREAK
MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODE ENTRY
SERIAL PERIPHERAL
6-CHANNEL TIMER INTERFACE
MODULE
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH — 62,078 BYTES
USER RAM — 2048 BYTES
MONITOR ROM
USER FLASH VECTOR SPACE — 52 BYTES
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1 OSC2
RST
(1)
IRQ
(1)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7/AD15–
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6
(2)
PTC5
(2)
PTC4
(2, 3)
PTC3
(2, 3)
PTC2
(2, 3)
PTC1/CAN
RX
(2, 3)
PTC0/CAN
TX
(2, 3)
PTD7/T2CH1
(2)
PTD6/T2CH0
(2)
PTD5/T1CH1
(2)
PTD4/T1CH0
(2)
PTD3/SPSCK
(2)
PTD2/MOSI
(2)
PTD1/MISO
(2)
PTD0/SS/MCLK
(2)
PTE1/RxD PTE0/TxD
2-CHANNEL TIMER INTERFACE
MODULE
ENHANCED SERIAL
INTERFACE MODULE
SECURITY
MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
CONFIGURATION REGISTER 1–2
MODULE
POWER
V
SS
V
DD
V
SSA
V
DDA
1. Pin contains integrated pullup device.
2. Ports are software configurable with pullup device if input port or pullup/pulldown device for keyboard input.
3. Higher current drive port pins
V
DDAD/VREFH
V
SSAD/VREFL
PTE5–PTE2
COMMUNICATIONS
CLOCK GENERATOR MODULE
CGMXFC
PHASE LOCKED LOOP
1–8 MHz OSCILLATOR
PORTB
DDRB
PTB7/AD7–
PORTF
DDRF
PTF7/T2CH5
MODULE
PORTG
DDRG
PTG7/AD23–
PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2
PTF3–PFT0
(3)
MSCAN
MODULE
PTA0/KBD0/AD8
(2)
PTB0/AD0
PTG0/AD16
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
62 Freescale Semiconductor
Functional Description
INTERNAL DATA BUS
READ DDRx
WRITE DDRx
RESET
WRITE PTx
READ PTx
PTx
DDRx
PTx
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
CLOCK
GENERATOR
CONVERSION
COMPLETE
ADC
(V
ADIN
)
ADC CLOCK
CGMXCLK
BUS CLOCK
ADCH4–ADCH0
ADC DATA REGISTER
AIEN COCO
DISABLE
DISABLE
ADC CHANNEL x
ADIV2–ADIV0 ADICLK
VOLTAGE IN
3.3.2 Voltage Conversion
When the input voltage to the ADC equals V input voltage equals V
REFL
, the ADC converts it to $000. Input voltages between V
Figure 3-2. ADC Block Diagram
straight-line linear conversion.
The ADC input voltage must always be greater than V V
Connect the V connect the V
The V
.
DDAD
DDAD
SSAD
pin should be routed carefully for maximum noise immunity.
pin to the same voltage potential as the VDD pin, and
DDAD
pin to the same voltage potential as the VSS pin.
, the ADC converts the signal to $3FF (full scale). If the
REFH
REFH
and V
NOTE
and less than
SSAD
REFL
are a
Freescale Semiconductor 63
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Analog-to-Digital Converter (ADC)
16 to 17 ADC cycles
ADC frequency
Conversion time =
Number of bus cycles = conversion time × bus frequency
3.3.3 Conversion Time
Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency.
3.3.4 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after each conversion and will stay set until the next read of the ADC data register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs between writes to the ADSCR.
When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
3.3.6 Result Justification
The conversion result may be formatted in four different ways:
1. Left justified
2. Right justified
3. Left Justified sign data mode
4. 8-bit truncation mode
All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock register (ADCLK).
Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register high, ADRH. This may be useful if the result is to be treated as an 8-bit result where the two least significant bits (LSB), located in the ADC data register low, ADRL, can be ignored. However, ADRL must be read after ADRH or else the interlocking will prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC data register high, ADRH, and the eight LSBs in ADC data register low, ADRL. This mode of operation typically is used when a 10-bit unsigned result is desired.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
64 Freescale Semiconductor
Monotonicity
IDEAL 10-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2
IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2
10-BIT TRUNCATED TO 8-BIT RESULT
WHEN TRUNCATION IS USED, ERROR FROM IDEAL 8-BIT = 3/8 LSB DUE TO NON-IDEAL QUANTIZATION.
000
001
002
003
004
005
006
007
008
009
00A
00B
000
001
002
003
8-BIT
RESULT
10-BIT
RESULT
INPUT VOLTAGE REPRESENTED AS 10-BIT
INPUT VOLTAGE REPRESENTED AS 8-BIT
1/2 2 1/2 4 1/2 6 1/2 8 1/2
1 1/2 3 1/2 5 1/2 7 1/2 9 1/2
1/2 2 1/21 1/2
Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. Finally, 8-bit truncation mode will place the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present.
NOTE
Quantization error is affected when only the most significant eight bits are used as a result. See Figure 3-3.
3.4 Monotonicity
The conversion process is monotonic and has no missing codes.
3.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit is a 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
Freescale Semiconductor 65
Figure 3-3. Bit Truncation Mode Error
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Analog-to-Digital Converter (ADC)
3.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power- consumption standby modes.
3.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction.
3.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry.
3.7 I/O Signals
The ADC module has eight pins shared with port A and the KBI module:
PTA7/KBD7/AD15–PTA0/KBD0/AD8
The ADC module has eight pins shared with port B:
PTB7/AD7–PTB0/AD0
The ADC module has eight pins shared with port G:
PTG7/AD23–PTG0/AD16
3.7.1 ADC Analog Power Pin (V
The ADC analog portion uses V potential as V
. External filtering may be necessary to ensure clean V
DD
DDAD
)
DDAD
as its power pin. Connect the V
NOTE
For maximum noise immunity, route V capacitors as close as possible to the package.
V
3.7.2 ADC Analog Ground Pin (V
The ADC analog portion uses V potential as V
DDAD
and V
are bonded internally.
REFH
.
SS
)
SSAD
as its ground pin. Connect the V
SSAD
NOTE
V
SSAD
and V
Route V
are bonded internally.
REFL
cleanly to avoid any offset errors.
SSAD
DDAD
DDAD
carefully and place bypass
DDAD
SSAD
pin to the same voltage
for good results.
pin to the same voltage
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
66 Freescale Semiconductor
I/O Registers
3.7.3 ADC Voltage Reference High Pin (V
The ADC analog portion uses V pin to the same voltage potential as V
as its upper voltage reference pin. By default, connect the V
REFH
. External filtering is often necessary to ensure a clean V
DD
REFH
)
REFH
for
REFH
good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
NOTE
For maximum noise immunity, route V capacitors as close as possible to the package. Routing V
V
DDAD
and V
parallel to V
are bonded internally.
REFH
may improve common mode noise rejection.
REFL
3.7.4 ADC Voltage Reference Low Pin (V
The ADC analog portion uses V to the same voltage potential as V
as its lower voltage reference pin. By default, connect the V
REFL
. External filtering is often necessary to ensure a clean V
SS
REFL
carefully and place bypass
REFH
REFH
)
close and
REFL
pin
REFL
for good
results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
NOTE
For maximum noise immunity, route V to V Routing V
, place bypass capacitors as close as possible to the package.
SS
close and parallel to V
REFH
carefully and, if not connected
REFL
may improve common mode
REFL
noise rejection.
SSAD
and V
V
3.7.5 ADC Voltage In (V
V
is the input voltage signal from one of the 24 ADC channels to the ADC module.
ADIN
are bonded internally.
REFL
ADIN
)
3.8 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADRH and ADRL)
• ADC clock register (ADCLK)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 67
Analog-to-Digital Converter (ADC)
3.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address: $003C
Bit 7654321Bit 0
Read: COCO
Write: R
Reset:00011111
R= Reserved
Figure 3-4. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads as a 0.
1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
The write function of the COCO bit is reserved. When writing to the ADSCR register, always have a 0 in the COCO bit position.
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
NOTE
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled 0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion 0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 32 ADC channels. Only 24 channels, AD23–AD0, are available on this MCU. The channels are detailed in Table 3-1. Care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. See Table 3-1.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
68 Freescale Semiconductor
I/O Registers
The voltage levels supplied from internal reference nodes, as specified in Table 3-1, are used to verify the operation of the ADC converter both in production test and for user applications.
Table 3-1. Mux Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select
00000 PTB0/AD0
00001 PTB1/AD1
00010 PTB2/AD2
00011 PTB3/AD3
00100 PTB4/AD4
00101 PTB5/AD5
00110 PTB6/AD6
00111 PTB7/AD7
0 1 0 0 0 PTA0/KBD0/AD8
0 1 0 0 1 PTA1/KBD1/AD9
0 1 0 1 0 PTA2/KBD2/AD10
0 1 0 1 1 PTA3/KBD3/AD11
0 1 1 0 0 PTA4/KBD4/AD12
0 1 1 0 1 PTA5/KBD5/AD13
0 1 1 1 0 PTA6/KBD6/AD14
0 1 1 1 1 PTA7/KBD7/AD15
1 0 0 0 0 PTG0/AD16
1 0 0 0 1 PTG1/AD17
1 0 0 1 0 PTG2/AD18
1 0 0 1 1 PTG3/AD19
1 0 1 0 0 PTG4/AD20
1 0 1 0 1 PTG5/AD21
1 0 1 1 0 PTG6/AD22
1 0 1 1 1 PTG7/AD23
1
↓
1
11101
11110
1 1 1 1 1 ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown or re­served.
1
↓
1
0
↓
1
0
↓
0
(1)
0
↓
0
Unused
V
REFH
V
REFL
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 69
Analog-to-Digital Converter (ADC)
3.8.2 ADC Data Register High and Data Register Low
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D ADRH
Bit 7654321Bit 0
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read:AD1AD0000000
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
3.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the 10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the 10-bit result. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D ADRH
Bit 7654321Bit 0
Read:000000AD9AD8
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
70 Freescale Semiconductor
I/O Registers
3.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D
Bit 7654321Bit 0
Read: AD9
Write:
Reset: Unaffected by reset
Address: $003E
Read:AD1AD0000000
Write:
Reset: Unaffected by reset
AD8 AD7 AD6 AD5 AD4 AD3 AD2
= Unimplemented
Figure 3-7. ADC Data Register High (ADRH) and Low (ADRL)
3.8.2.4 Eight Bit Truncation Mode
In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit result. The ADRH register is unused and reads as 0. The ADRL register is updated each time an ADC single channel conversion completes. In 8-bit mode, the ADRL register contains no interlocking with ADRH.
Address: $003D ADRH
Bit 7654321Bit 0
Read:00000000
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 71
Analog-to-Digital Converter (ADC)
f
ADIC
=
f
CGMXCLK
or bus frequency
ADIV[2:0]
≅ 1 MHz
3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003F
Bit 7654321Bit 0
Read:
Write:
Reset:00000100
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R
= Unimplemented R = Reserved
Figure 3-9. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz.
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1 0 0 1 ADC input clock ÷ 2 0 1 0 ADC input clock ÷ 4 0 1 1 ADC input clock ÷ 8
1
1. X = Don’t care
(1)
X
(1)
X
ADC input clock ÷ 16
0
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
1 = Internal bus clock 0 = Oscillator output clock (CGMXCLK)
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See 21.10 5.0-Volt ADC Characteristics.
MODE1 and MODE0 — Modes of Result Justification Bits
MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode.
00 = 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified signed data mode
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
72 Freescale Semiconductor
Chapter 4 Clock Generator Module (CGM)
4.1 Introduction
This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the system clocks, including the bus clock, which is at a frequency of CGMOUT/2. The PLL is a fully functional frequency generator designed for use with crystals or ceramic resonators. The PLL can generate a maximum bus frequency of 8 MHz using a 1-8MHz crystal or external clock source.
4.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference
• High-frequency crystal operation with low-power operation and high-output frequency resolution
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop mode
4.3 Functional Description
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock, CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK.
Figure 4-1 shows the structure of the CGM.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 73
Clock Generator Module (CGM)
BCS
PHASE
DETECTOR
LOOP
FILTER
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
CLOCK
CGMXCLK
CGMOUT
CGMVDV
CGMVCLK
SIMOSCEN (FROM SIM)
OSCILLATOR (OSC)
INTERRUPT
CONTROL
CGMINT
PLL ANALOG
÷
2
CGMRCLK
OSC2
OSC1
SELECT
CIRCUIT
V
DDA
CGMXFC V
SSA
LOCK AUTO ACQ
VPR1–VPR0
PLLIE PLLF
MUL11–MUL0
VRS7–VRS0
OSCENINSTOP
(FROM CONFIG)
(TO: SIM, TBM, ADC, MSCAN)
PHASE-LOCKED LOOP (PLL)
A
B
S
*
*
WHEN S = 1, CGMOUT = B
SIMDIV2 (FROM SIM)
(TO SIM)
(TO SIM)
Figure 4-1. CGM Block Diagram
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
74 Freescale Semiconductor
Functional Description
4.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCENINSTOP bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
4.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually.
4.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f CGMXFC pin changes the frequency within this range. By design, f center-of-range frequency, f
E
(L × 2
)f
NOM
.
, (71.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
NOM
. Modulating the voltage on the
VRS
is equal to the nominal
VRS
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, f
. The VCO’s output clock, CGMVCLK, running at a frequency, f
RCLK
, is fed back through a
VCLK
programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The dividers output is the VCO feedback clock, CGMVDV, running at a frequency, f
VDV=fVCLK
/(N). (For more
information, see 4.3.6 Programming the PLL.)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 4.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 75
Clock Generator Module (CGM)
frequency, f
. The circuit determines the mode of the PLL and the lock condition based on this
RCLK
comparison.
4.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
• Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ
bit is clear in
the PLL bandwidth control register. (See 4.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. (See 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ
bit is set.
4.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 4.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (for example, during PLL start up) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. (See 4.3.8 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate action, depending on the application. (See 4.6 Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control mode:
•The ACQ
bit (See 4.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of
the filter. (See 4.3.4 Acquisition and Tracking Modes.)
•The ACQ
bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 4.8 Acquisition/Lock Time Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 4.8 Acquisition/Lock Time Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. (See 4.5.1 PLL Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below f
BUSMAX
76 Freescale Semiconductor
.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Functional Description
The following conditions apply when in manual mode:
•ACQ
• Before entering tracking mode (ACQ
is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ
bit must be clear.
= 1), software must wait a given time, t
(See 4.8
ACQ
Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, t
, after entering tracking mode before selecting the PLL as the
AL
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
4.3.6 Programming the PLL
Use the following procedure to program the PLL. For reference, the variables used and their meaning are shown in Table 4-1.
Table 4-1. Variable Definitions
Variable Definition
f
BUSDES
f
VCLKDES
f
RCLK
f
VCLK
f
BUS
f
NOM
f
VRS
Desired bus clock frequency
Desired VCO clock frequency
Chosen reference crystal frequency
Calculated VCO clock frequency
Calculated bus clock frequency
Nominal VCO center frequency
Programmed VCO center frequency
NOTE
The round function in the following equations means that the real number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
BUSDES
.
2. Calculate the desired VCO frequency (four times the desired bus frequency). f
VCLKDES
3. Choose a practical PLL (crystal) reference frequency, f
= 4 x f
BUSDES
RCLK
. Typically, the reference crystal is 1–8
MHz. Frequency errors to the PLL are corrected at a rate of f
RCLK
. For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate. The relationship between the VCO frequency, f reference frequency, f
RCLK,
is:
f
VCLK
= (N) (f
RCLK
)
VCLK
, and the
N, the range multiplier, must be an integer.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 77
Clock Generator Module (CGM)
N round
f
VCLKDES
f
RCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
= f
VCLK
N() f
RCLK
×=
f
BUS
f
VCLK
()4⁄=
L = Round
f
VCLK
2E x f
NOM
f
VRSfVCLK
–
f
NOM
2E×
2
-------------------------- -
≤
In cases where desired bus frequency has some tolerance, choose f
to a value determined
RCLK
either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Chapter 21 Electrical
Specifications. After choosing N, the actual bus frequency can be determined using equation in 2
above.
4. Select a VCO frequency multiplier, N.
5. Calculate and verify the adequacy of the VCO and bus frequencies f
VCLK
and f
BUS
.
6. Select the VCO’s power-of-two range multiplier E, according to Table 4-2.
Table 4-2. Power-of-Two Range Selectors
Frequency Range E
VCLK
VCLK
VCLK
≤ 8 MHz
≤ 16 MHz
≤ 32 MHz
0
1
(1)
2
0 < f
8 MHz< f
16 MHz< f
1. Do not program E to a value of 3.
7. Select a VCO linear range multiplier, L, where f
= 71.4 kHz
NOM
8. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, f center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL.
= (L x 2E) f
f
VRS
NOM
9. For proper operation,
10. Verify the choice of N, E, and L by comparing f must be within the application’s tolerance of f
f
VCLK
VCLK
.
to f
VCLK
VCLKDES
to f
VRS
and f
, and f
VCLKDES
VRS
. For proper operation,
must be as close as possible
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU.
VRS
. The
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
78 Freescale Semiconductor
11. Program the PLL registers accordingly:
a. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
b. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N. If using a 1–8 MHz reference, the PMSL register must be reprogrammed from the reset value before enabling the PLL.
c. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
Table 4-3 provides numeric examples (register values are in hexadecimal notation):
Table 4-3. Numeric Example
Functional Description
f
BUS
500 kHz 1 MHz 002 0 1B
1.25 MHz 1 MHz 005 0 45
2.0 MHz 1 MHz 008 0 70
2.5 MHz 1 MHz 00A 1 45
3.0 MHz 1 MHz 00C 1 53
4.0 MHz 1 MHz 010 1 70
5.0 MHz 1 MHz 014 2 46
7.0 MHz 1 MHz 01C 2 62
8.0 MHz 1 MHz 020 2 70
f
RCLK
NEL
4.3.7 Special Programming Exceptions
The programming method described in 4.3.6 Programming the PLL does not account for two possible exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these exceptions:
• A 0 value for N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
See 4.3.8 Base Clock Selector Circuit.
4.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 79
Clock Generator Module (CGM)
OSC1
C
1
C
2
SIMOSCEN
CGMXCLK
R
B
X1
R
S
C
BYP
OSC2
CGMXFC
V
DDA
Note: Filter network in box can be replaced with a single capacitor, but will degrade stability.
V
DD
OSCENINSTOP
(FROM CONFIG)
R
F1
V
SSA
CF1
C
F2
4.3.9 CGM External Connections
In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-2.
Figure 4-2 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•Crystal, X
• Fixed capacitor, C
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, R
• Series resistor, RS
1
1
B
The series resistor (R
) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the
S
crystal manufacturer’s data for more information regarding values for C1 and C2.
Figure 4-2 also shows the external components for the PLL:
• Bypass capacitor, C
BYP
• Filter network
Routing should be done with great care to minimize signal cross talk and noise.
Figure 4-2. CGM External Connections
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
80 Freescale Semiconductor
I/O Signals
4.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
4.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
4.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
4.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 4-2.)
NOTE
To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network.
4.4.4 PLL Analog Power Pin (V
V
is a power pin used by the analog portions of the PLL. Connect the V
DDA
potential as the V
DD
pin.
DDA
)
pin to the same voltage
DDA
NOTE
Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.
4.4.5 PLL Analog Ground Pin (V
V
is a ground pin used by the analog portions of the PLL. Connect the V
SSA
potential as the V
SS
pin.
SSA
)
pin to the same voltage
SSA
NOTE
Route V
carefully for maximum noise immunity and place bypass
SSA
capacitors as close as possible to the package.
4.4.6 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL.
4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP)
OSCENINSTOP is a bit in the CONFIG2 register that enables the oscillator to continue operating during stop mode. If this bit is set, the oscillator continues running during stop mode. If this bit is not set (default), the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 81
Clock Generator Module (CGM)
4.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f
) and comes
XCLK
directly from the crystal oscillator circuit. Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) (See 4.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC) (See 4.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH) (See 4.5.3 PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL) (See 4.5.4 PLL Multiplier Select Register Low.)
• PLL VCO range select register (PMRS) (See 4.5.5 PLL VCO Range Select Register.)
Figure 4-3 is a summary of the CGM registers.
Addr.Register Name Bit 7654321Bit 0
$0036
$0037
$0038
PLL Control Register
(PCTL)
See page 83.
PLL Bandwidth Control
Register (PBWC)
See page 85.
PLL Multiplier Select High
Register (PMSH)
See page 86.
Read:
Write:
Reset:00100000
Read:
Write:
Reset:00000000
Read:0000
Write:
Reset:00000000
PLLIE
AUTO
PLLF
LOCK
= Unimplemented R = Reserved
PLLON BCS R R VPR1 VPR0
ACQ
0000
MUL11 MUL10 MUL9 MUL8
R
Figure 4-3. CGM I/O Register Summary
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
82 Freescale Semiconductor
CGM Registers
Addr.Register Name Bit 7654321Bit 0
PLL Multiplier Select Low
$0039
$003A
$003B Reserved Register
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Register (PMSL)
See page 86.
PLL VCO Select Range
Register (PMRS)
See page 87.
is read-only.
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read:0000
Write:
Reset:00000001
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
RRRR
= Unimplemented R = Reserved
Figure 4-3. CGM I/O Register Summary (Continued)
4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, and the VCO power-of-two range selector bits.
Address: $0036
Bit 76543 2 1Bit 0
Read:
PLLIE
Write:
Reset:00100 0 00
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled 0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition 0 = No change in lock condition
PLLF
PLLON BCS R R VPR1 VPR0
= Unimplemented R = Reserved
Figure 4-4. PLL Control Register (PCTL)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 83
Clock Generator Module (CGM)
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 4.3.8 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on 0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 4.3.8 Base Clock
Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See
4.3.8 Base Clock Selector Circuit.).
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L controls the hardware center-of-range frequency, f
. VPR1:VPR0 cannot be written when the
VRS
PLLON bit is set. Reset clears these bits. (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and
4.5.5 PLL VCO Range Select Register.)
Table 4-4. VPR1 and VPR0 Programming
VPR1 and VPR0 E
00 0 1
01 1 2
10
1. Do not program E to a value of 3.
(1)
2
VCO Power-of-Two
Range Multiplier
4
NOTE
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are appropriate for the given reference and VCO clock frequencies before enabling the PLL. See 4.3.6 Programming the PLL for detailed instructions on selecting the proper value for these control bits.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
84 Freescale Semiconductor
CGM Registers
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address: $0037
Bit 7654321Bit 0
Read:
AUTO
Write:
Reset:00000000
LOCK
ACQ
= Unimplemented R= Reserved
Figure 4-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ
bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control
0000
R
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit.
1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked
ACQ
— Acquisition Mode Bit
When the AUTO bit is set, ACQ or tracking mode. When the AUTO bit is clear, ACQ
is a read-only bit that indicates whether the PLL is in acquisition mode
is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode.
1 = Tracking mode 0 = Acquisition mode
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 85
Clock Generator Module (CGM)
4.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider.
Address: $0038
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
MUL11 MUL10 MUL9 MUL8
Figure 4-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that selects the VCO frequency multiplier N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as 0s.
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider.
Address: $0038
Bit 7654321Bit 0
Read:
Write:
Reset:01000000
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
NOTE
For applications using 1–8 MHz reference frequencies this register must be reprogrammed before enabling the PLL. The reset value of this register will cause applications using 1–8 MHz reference frequencies to become unstable if the PLL is enabled without programming an appropriate value. The programmed value must not allow the VCO clock to exceed 32 MHz. See 4.3.6 Programming the PLL for detailed instructions on choosing the proper value for PMSL.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
86 Freescale Semiconductor
CGM Registers
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier, N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) MUL7–MUL0 cannot be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to $40 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1).
4.5.5 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO.
Address: $003A
Bit 7654321Bit 0
Read:
Write:
Reset:01000000
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Figure 4-8. PLL VCO Range Select Register (PMRS)
NOTE
Verify that the value of the PMRS register is appropriate for the given reference and VCO clock frequencies before enabling the PLL. See 4.3.6
Programming the PLL for detailed instructions on selecting the proper value
for these control bits.
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.1 PLL Control Register.), controls the hardware center-of-range frequency, f
. VRS7–VRS0 cannot be written when the PLLON bit in the
VRS
PCTL is set. (See 4.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 4.3.8 Base
Clock Selector Circuit and 4.3.7 Special Programming Exceptions.). Reset initializes the register to $40
for a default range multiply value of 64.
NOTE
The VCO range select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear.
The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 87
Clock Generator Module (CGM)
4.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.
4.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
4.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power. Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
4.7.2 Stop Mode
If the OSCENINSTOP bit in the CONFIG2 register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT).
If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked loop is shut off but the oscillator will continue to operate in stop mode.
4.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 15.7.3 Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
88 Freescale Semiconductor
Acquisition/Lock Time Specifications
4.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times.
4.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error.
4.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, f This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is under user control via the choice of crystal frequency f
XCLK
4.3.3 PLL Circuits and 4.3.6 Programming the PLL.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. (See 4.8.3 Choosing a Filter.)
Also important is the operating voltage potential applied to V
. The power supply potential alters the
DDA
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL.
RCLK
. (See
.
Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 89
Clock Generator Module (CGM)
CGMXFC
R
F1
C
F2
C
F1
V
SSA
CGMXFC
C
F
V
SSA
(A) (B)
External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination.
4.8.3 Choosing a Filter
As described in 4.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage.
Figure 4-9 shows two types of filter circuits. In low-cost applications, where stability and reaction time of
the PLL are not critical, the three component filter network shown in Figure 4-9 (B) can be replaced by a single capacitor, C components at various reference frequencies. For reference frequencies between the values listed in the table, extrapolate to the nearest common capacitor value. In general, a slightly larger capacitor provides more stability at the expense of increased lock time.
, as shown in shown in Figure 4-9 (A). Refer to Table 4-5 for recommended filter
F
Figure 4-9. PLL Filter
Table 4-5. Example Filter Component Values
f
RCLK
1 MHz 8.2 nF 820 pF 2k 18 nF
2 MHz 4.7 nF 470 pF 2k 6.8 nF
3 MHz 3.3 nF 330 pF 2k 5.6 nF
4 MHz 2.2 nF 220 pF 2k 4.7 nF
5 MHz 1.8 nF 180 pF 2k 3.9 nF
6 MHz 1.5 nF 150 pF 2k 3.3 nF
7 MHz 1.2 nF 120 pF 2k 2.7 nF
8 MHz 1 nF 100 pF 2k 2.2 nF
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
90 Freescale Semiconductor
C
F1
C
F2
R
F1
C
F
Chapter 5 Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options:
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• COP timeout period (262,128 or 8176 CGMXCLK cycles)
•STOP instruction
• Computer operating properly module (COP)
• Low-voltage inhibit (LVI) module control and voltage trip point selection
• Enable/disable the oscillator (OSC) during stop mode
• Enable/disable an extra divide by 128 prescaler in timebase module
• Enable for scalable controller area network (MSCAN)
• Selectable clockout (MCLK) feature with divide by 1, 2, and 4 of the bus or crystal frequency
• Timebase clock select
5.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU), it is recommended that these registers be written immediately after reset. The configuration registers are located at $001E and $001F and may be read at anytime.
NOTE
On a FLASH device, the options except MSCANEN and LVI5OR3 are one-time writable by the user after each reset. These bits are one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 and
Figure 5-2.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 91
Configuration Register (CONFIG)
Address: $001E
Bit 76543 2 1Bit 0
Read: 0
Write:
Reset:0000See note0 0 1
Note: MSCANEN is only reset via POR (power-on reset).
MCLKSEL MCLK1 MCLK0 MSCANEN TMBCLKSEL OSCENINSTOP SCIBDSRC
= Unimplemented
Figure 5-1. Configuration Register 2 (CONFIG2)
MCLKSEL — MCLK Source Select Bit
1 = Crystal frequency 0 = Bus frequency
MCLK1 and MCLK0 — MCLK Output Select Bits
Setting the MCLK1 and MCLK0 bits enables the PTD0/SS
pin to be used as a MCLK output clock. Once configured for MCLK, the PTD data direction register for PTD0 is used to enable and disable the MCLK output.
See Table 5-1 for M CLK options.
Table 5-1. MCLK Output Select
MCLK1 MCLK0 MCLK Frequency
0 0 MCLK not enabled
0 1 Clock
1 0 Clock divided by 2
1 1 Clock divided by 4
MSCANEN— MSCAN08 Enable Bit
Setting the MSCANEN
See Chapter 12 MSCAN08 Controller (MSCAN08) for a more detailed description of the
pins.
enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1
MSCAN08 operation.
1 = Enables MSCAN08 module 0 = Disables the MSCAN08 module
NOTE
The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected.
TMBCLKSEL— Timebase Clock Select Bit
TMBCLKSEL the extra prescaler and clearing this bit disables it.
enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
See Chapter 17 Timebase Module (TBM) for a more
detailed description of the external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module 0 = Disables extra divide-by-128 prescaler in timebase module
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
92 Freescale Semiconductor
Functional Description
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module (CGM). This function is used to keep the timebase running while
the rest of the MCU stops. See Chapter 17 Timebase Module (TBM). When clear, the oscillator will cease to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator in stop mode.
1 = Oscillator enabled during stop mode 0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting of this bit affects the frequency at which the SCI operates.See Chapter 14 Enhanced Serial
Communications Interface (ESCI) Module.
1 = Internal data bus clock used as clock source for SCI (default) 0 = External oscillator used as clock source for SCI
Address: $001F
Bit 7654321Bit 0
Read:
Reset:0000See note000
Note: LVI5OR3 is only reset via POR (power-on reset).
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
Write:
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See Chapter 6 Computer Operating
Properly (COP) Module
1 = COP timeout period = 8176 CGMXCLK cycles 0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode 0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled 0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI module power disabled 0 = LVI module power enabled
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 93
Configuration Register (CONFIG)
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module (see Chapter 11 Low-Voltage Inhibit
(LVI)). The voltage mode selected for the LVI should match the operating V
(see Chapter 21
DD
Electrical Specifications) for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode 0 = LVI operates in 3-V mode
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
Exiting stop mode by any reset will result in the long stop recovery.
The short stop recovery delay can be enabled when using a crystal or resonator and the OSCENINSTOP bit is set. The short stop recovery delay can be enabled when an external oscillator is used, regardless of the OSCENINSTOP setting.
The short stop recovery delay must be disabled when the OSCENINSTOP bit is clear and a crystal or resonator is used.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 6 Computer Operating Properly (COP) Module.
1 = COP module disabled 0 = COP module enabled
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
94 Freescale Semiconductor
Chapter 6
COPCTL WRITE
CGMXCLK
RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
12-BIT SIM COUNTER
CLEAR ALL STAGES
6-BIT COP COUNTER
COP DISABLE
RESET
COPCTL WRITE
CLEAR
COP MODULE
COPEN (FROM SIM)
COP COUNTER
COP CLOCK
COP TIMEOUT
STOP INSTRUCTION
(FROM CONFIG)
COP RATE SEL
(FROM CONFIG)
CLEAR STAGES 5–12
Computer Operating Properly (COP) Module
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
6.2 Functional Description
Figure 6-1 shows the structure of the COP module.
Freescale Semiconductor 95
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Figure 6-1. COP Block Diagram
Computer Operating Properly (COP) Module
The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 262,128 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow.
A COP reset pulls the RST
pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST
on the RST pin disables the COP.
V
TST
pin or the IRQ is held at V
. During the break state,
TST
NOTE
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) clears the COP counter and clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector. See 6.4
COP Control Register.
6.3.4 Power-On Reset
The power-on reset (POR) circuit clears the SIM counter 4096 CGMXCLK cycles after power-up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
96 Freescale Semiconductor
COP Control Register
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 5 Configuration Register (CONFIG).
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See
Chapter 5 Configuration Register (CONFIG).
6.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate central processor unit (CPU) interrupt requests.
6.6 Monitor Mode
When monitor mode is entered with V on the IRQ having V
pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
on the IRQ pin, the COP is automatically disabled until a POR occurs.
TST
on the IRQ pin, the COP is disabled as long as V
TST
remains
TST
6.7 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes.
6.7.1 Wait Mode
The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.
6.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 97
Computer Operating Properly (COP) Module
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset.
6.8 COP Module During Break Mode
The COP is disabled during a break interrupt when V
is present on the RST pin.
TST
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
98 Freescale Semiconductor
Chapter 7 Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 99
Central Processor Unit (CPU)
ACCUMULATOR (A)
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG
V11HINZC
H X
0
0
0
0
7
15
15
15
70
7.3.1 Accumulator
Figure 7-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 7-2. Accumulator (A)
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit 151413121110987654321
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 7-3. Index Register (H:X)
Bit
0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
100 Freescale Semiconductor
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