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the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
The MC68HC908GR8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
This document also describes the MC68HC908GR4. The MC68HC908GR4 is a device identical to the
MC68HC908GR8 except that it has less Flash memory. Only when there are differences from the
MC68HC908GR8 is the MC68HC908GR4 specifically mentioned in the text.
1.2 Features
For convenience, features have been organized to reflect:
•Standard features of the MC68HC908GR8
•Features of the CPU08
1.2.1 Standard Features of the MC68HC908GR8
•High-performance M68HC08 architecture optimized for C-compilers
•Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
•8-MHz internal bus frequency
•FLASH program memory security
•On-chip programming firmware for use with host personal computer which does not require high
voltage for entry
•In-system programming
•System protection features:
–Optional computer operating properly (COP) reset
–Low-voltage detection with optional reset and selectable trip points for 3.0 V and 5.0 V
operation
–Illegal opcode detection with reset
–Illegal address detection with reset
•Low-power design; fully static with stop and wait modes
•Standard low-power modes of operation:
–Wait mode
–Stop mode
•Master reset pin and power-on reset (POR)
(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor19
General Description
•7680 bytes of on-chip FLASH memory on the MC68HC908GR8 and 4096 bytes of on-chip FLASH
memory on the MC68HC908GR4 with in-circuit programming capabilities of FLASH program
memory
•384 bytes of on-chip random-access memory (RAM)
•Serial peripheral interface module (SPI)
•Serial communications interface module (SCI)
•One 16-bit, 2-channel timer (TIM1) and one 16-bit, 1-channel timer (TIM2) interface modules with
selectable input capture, output compare, and PWM capability on each channel
•Up to 21 general-purpose input/output (I/O) pins, including:
–19 shared-function I/O pins
–Up to two dedicated I/O pins, depending on package choice
•Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
•High current 10-mA sink/10-mA source capability on all port pins
•Higher current 15-mA sink/source capability on PTC0–PTC1
•Timebase module with clock prescaler circuitry for eight user selectable periodic real-time
interrupts with optional active clock source during stop mode for periodic wakeup from stop using
an external 32-kHz crystal
•Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG register to allow user selection of
having the oscillator enabled or disabled during stop mode
•4-bit keyboard wakeup port
•32-pin quad flat pack (QFP) or 28-pin plastic dual-in-line package (DIP) or 28-pin small outline
integrated circuit (SOIC)
•Specific features of the MC68HC908GR8 in 28-pin DIP and 28-pin SOIC are:
–Port B is only 4 bits: PTB0–PTB3; 4-channel ADC module
–No Port C bits
1.2.2 Features of the CPU08
Features of the CPU08 include:
•Enhanced HC05 programming model
•Extensive loop control functions
•16 addressing modes (eight more than the HC05)
•16-bit index register and stack pointer
•Memory-to-memory data transfers
•Fast 8 × 8 multiply instruction
•Fast 16/8 divide instruction
•Binary-coded decimal (BCD) instructions
•Optimization for controller applications
•Efficient C language support
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
20Freescale Semiconductor
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GR8.
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
Figure 1-1. MCU Block Diagram
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor21
General Description
1.4 Pin Assignments
OSC1
OSC2
SSAVDDA
CGMXFC
V
PTC1
PTC0
PTA3/KBD3
32
RST
PTE0/TxD
PTE1/RxD
IRQ
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
1
31
2
3
4
5
6
7
8
9
10
11
12
13
14
SS
DD
V
V
PTB0/AD0
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
15
PTB1/AD1
PTB2/AD2
24
PTA2/KBD2
23
PTA1/KBD1
22
PTA0/KBD0
V
21
20
19
18
17
16
SSAD/VREFL
V
DDAD/VREFH
PTB5/AD5
PTB4/AD4
PTB3/AD3
25
26
27
28
29
30
NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.
Figure 1-2. QFP Pin Assignments
CGMXFC
OSC2
OSC1
RST
PTE0/TxD
PTE1/RxD
IRQ
PTD0/SS
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
V
V
PTD4/T1CH0
1
2
3
4
5
6
7
8
9
10
11
12
SS
13
DD
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SSA
V
DDA
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
V
SSAD/VREFL
V
DDAD/VREFH
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
PTD6/T2CH0
PTD5/T1CH1
TE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.
Figure 1-3. DIP And SOIC Pin Assignments
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
22Freescale Semiconductor
Pin Functions
1.5 Pin Functions
Descriptions of the pin functions are provided here.
1.5.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To
prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response
ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that
require the port pins to source high current levels.
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Chapter 7 Clock
Generator Module (CGMC).
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset
of the entire system. It is driven low when any internal reset source is asserted. This pin contains an
internal pullup resistor that is always activated, even when the reset pin is pulled low. See Chapter 4
Resets and Interrupts.
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor that is always
activated, even when the reset pin is pulled low. See Chapter 12 External Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (V
V
and V
DDA
Decoupling of these pins should be as per the digital supply. See Chapter 7 Clock Generator Module
(CGMC).
are the power supply pins for the analog portion of the clock generator module (CGM).
SSA
DDA
and V
SSA
)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor23
General Description
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Chapter 7 Clock Generator Module
(CGMC).
1.5.7 Analog Power Supply/Reference Pins (V
V
DDAD
and V
are the power supply pins for the analog-to-digital converter. Decoupling of these pins
SSAD
DDAD/VREFH
and V
SSAD/VREFL
)
should be as per the digital supply.
NOTE
V
internally connected with V
V
V
connected with V
be tied to the same potential as V
is the high reference supply for the ADC. The V
REFH
and have the same potential as V
DDAD
should be tied to the same potential as VDD via separate traces.
DDAD
is the low reference supply for the ADC. The V
REFL
and has the same potential as V
SSAD
via separate traces.
SS
REFH
pin is internally
REFL
SSAD. VSSAD
signal is
DDAD.
should
See Chapter 5 Analog-to-Digital Converter (ADC).
1.5.8 Port A Input/Output (I/O) Pins (PTA3/KBD3–PTA0/KBD0)
PTA3–PTA0 are special-function, bidirectional I/O port pins. Any or all of the port A pins can be
programmed to serve as keyboard interrupt pins. See Chapter 16 Input/Output Ports (I/O) and See
Chapter 12 External Interrupt (IRQ).
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
When the port pins are configured for special-function mode (KBI), pullups will be automatically engaged.
As long as the port pins are in special-function mode, the pullups will always be on.
1.5.9 Port B I/O Pins (PTB5/AD5–PTB0/AD0)
PTB5–PTB0 are special-function, bidirectional I/O port pins that can also be used for analog-to-digital
converter (ADC) inputs. See Chapter 16 Input/Output Ports (I/O) and See Chapter 5 Analog-to-Digital
Converter (ADC).
There are no pullups associated with this port.
1.5.10 Port C I/O Pins (PTC1–PTC0)
PTC1–PTC0 are general-purpose, bidirectional I/O port pins. See Chapter 16 Input/Output Ports (I/O).
PTC0 and PTC1 are only available on 32-pin QFP packages.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.11 Port D I/O Pins (PTD6/T2CH0–PTD0/SS)
PTD6–PTD0 are special-function, bidirectional I/O port pins. PTD3–PTD0 can be programmed to be
serial peripheral interface (SPI) pins, while PTD6–PTD4 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Chapter 22 Timer Interface Module (TIM), Chapter 20 Serial
Peripheral Interface (SPI), and See Chapter 16 Input/Output Ports (I/O).
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
24Freescale Semiconductor
Pin Functions
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
When the port pins are configured for special-function mode (SPI, TIM1, TIM2), pullups can be selectable
on an individual port pin basis.
1.5.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD)
PTE1–PTE0 are special-function, bidirectional I/O port pins. These pins can also be programmed to be
serial communications interface (SCI) pins. See Chapter 18 Serial Communications Interface (SCI) and
See Chapter 16 Input/Output Ports (I/O).
NOTE
Any unused inputs and I/O ports should be tied to an appropriate logic level
(either V
require termination, termination is recommended to reduce the possibility
of electro-static discharge damage.
or VSS). Although the I/O ports of the MC68HC908GR8 do not
DD
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor25
General Description
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
26Freescale Semiconductor
Chapter 2
Memory Map
2.1 Introduction
The CPU08 can address 64K bytes of memory space. The memory map, shown in Figure 2-1, includes:
•8K bytes of FLASH memory, 7680 bytes of user space on the MC68HC908GR8 or
4K bytes of FLASH memory, 4096 bytes of user space on the MC68HC908GR4
•384 bytes of random-access memory (RAM)
•36 bytes of user-defined vectors
•310 bytes of monitor routines in read-only memory (ROM)
•544 bytes of integrated FLASH burn-in routines in ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset if illegal address resets are
enabled. In the memory map (Figure 2-1) and in register figures in this document, unimplemented
locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and
in register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$003F. Additional I/O
registers have these addresses:
•$FE00; SIM break status register, SBSR
•$FE01; SIM reset status register, SRSR
•$FE03; SIM break flag control register, SBFCR
•$FE04; interrupt status register 1, INT1
•$FE05; interrupt status register 2, INT2
•$FE06; interrupt status register 3, INT3
•$FE07; reserved FLASH test control register, FLTCR
•$FE08; FLASH control register, FLCR
•$FE09; break address register high, BRKH
•$FE0A; break address register low, BRKL
•$FE0B; break status and control register, BRKSCR
•$FE0C; LVI status register, LVISR
•$FF7E; FLASH block protect register, FLBPR
Data registers are shown in Figure 2-2, and Table 2-1 is a list of vector locations.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor27
Memory Map
$0000
↓
$003F
$0040
↓
$01BF
$01C0
↓
$1BFF
$1C00
↓
$1E1F
$1E20
↓
$DFFF
$E000
↓
$EDFF
$EE00
↓
$FDFF
$FE00SIM Break Status Register (SBSR)
$FE01SIM Reset Status Register (SRSR)
Reserved for Integrated FLASH Burn-in Routines
MC68HC908GR8
FLASH Memory
7680 Bytes
I/O Registers
64 Bytes
RAM
384 Bytes
Unimplemented
6720 Bytes
544 Bytes
Unimplemented
49,632 Bytes
MC68HC908GR4
Unimplemented
MC68HC908GR4
FLASH Memory
3584 Bytes
4096 Bytes
$FE02
$FE03SIM Break Flag Control Register (SBFCR)
$FE04Interrupt Status Register 1 (INT1)
$FE05Interrupt Status Register 2 (INT2)
$FE06Interrupt Status Register 3 (INT3)
$FE07
$FE08FLASH Control Register (FLCR)
$FE09Break Address Register High (BRKH)
$FE0ABreak Address Register Low (BRKL)
$FE0BBreak Status and Control Register (BRKSCR)
$FE0CLVI Status Register (LVISR)
Reserved for FLASH Test Control Register (FLTCR)
Reserved
Continued on next page
Figure 2-1. Memory Map
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
28Freescale Semiconductor
$FE0D
↓
$FE0F
$FE10
↓
$FE1F
$FE20
↓
$FF55
$FF56
↓
$FF7D
$FF7EFLASH Block Protect Register (FLBPR)
$FF7F
↓
$FFDB
Reserved for Compatibility with Monitor Code
Reserved
3 Bytes
Unimplemented
16 Bytes
for A-Family Parts
Monitor ROM
310 Bytes
Unimplemented
40 Bytes
Unimplemented
93 Bytes
Input/Output (I/O) Section
Note: $FFF6–$FFFD
contains
8 security bytes
$FFDC
↓
$FFFE
$FFFF
FLASH Vectors
(36 Bytes inluding $FFFF)
Low byte of reset vector when read
COP Control Register (COPCTL)
Figure 2-1. Memory Map (Continued)
Addr.Register NameBit 7654321Bit 0
$0000
$0001
$0002
$0003
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Read:0000
Write:
Reset:Unaffected by reset
Read:00
Write:
Reset:Unaffected by reset
Read:000000
Write:
Reset:Unaffected by reset
Read:0
Write:
Reset:Unaffected by reset
PTD6PTD5PTD4PTD3PTD2PTD1PTD0
= UnimplementedR = ReservedU = Unaffected
PTB5PTB4PTB3PTB2PTB1PTB0
PTA3PTA2PTA1PTA0
PTC1PTC0
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
30Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register NameBit 7654321Bit 0
Read:R7R6R5R4R3R2R1R0
Write:T7T6T5T4T3T2T1T0
Reset:Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:R8
Write:
Reset:UU000000
Read:SCTETCSCRFIDLEORNFFEPE
Write:
Reset:11000000
Read:
Write:
Reset:00000000
Read:R7R6R5R4R3R2R1R0
Write:T7T6T5T4T3T2T1T0
Reset:Unaffected by reset
Read:
Write:
Reset:00000000
Read:0000KEYF0
Write:
Reset:00000000
Read:
Write:
Reset:0000
Read:TBIF
Write:
Reset:00000000
Read:0000IRQF10
Write:ACK1
Reset:00000000
LOOPSENSCITXINVMWAKEILTYPENPTY
SCTIETCIESCRIEILIETERERWUSBK
T8DMAREDMATEORIENEIEFEIEPEIE
BKFRPF
SCP1SCP0RSCR2SCR1SCR0
ACKK
KBIE3KBIE2KBIE1KBIE0
TBR2TBR1TBR0
= UnimplementedR = ReservedU = Unaffected
0
TACK
TBIETBONR
IMASKKMODEK
IMASK1MODE1
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
SPI Data Register
(SPDR)
SCI Control Register 1
(SCC1)
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
SCI Baud Rate Register
(SCBR)
Keyboard Status
and Control Register
(INTKBSCR)
Keyboard Interrupt Enable
Register (INTKBIER)
Time Base Module Control
Register (TBCR)
IRQ Status and Control
Register (INTSCR)
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor31
Memory Map
Addr.Register NameBit 7654321Bit 0
$001E
Configuration Register 2
(CONFIG2)†
Read:000000
Write:
OSC-
STOPENB
SCIBDSRC
Reset:00000000
$001F
Configuration Register 1
(CONFIG1)
Read:
Write:
†
COPRSLVISTOPLVIRSTDLVIPWRD LVI5OR3
†
SSRECSTOPCOPD
Reset:00000000
$0020
Timer 1 Status and Control
Register (T1SC)
Read:TOF
Write:0TRST
TOIETSTOP
00
PS2PS1PS0
Reset:00100000
Read:Bit 1514131211109Bit 8
$0021
Timer 1 Counter Register
High (T1CNTH)
Write:
Reset:00000000
Read:Bit 7654321Bit 0
$0022
Timer 1 Counter Register
Low (T1CNTL)
Write:
Reset:00000000
$0023
Timer 1 Counter Modulo
Register High (T1MODH)
Read:
Write:
Bit 1514131211109Bit 8
Reset:11111111
$0024
Timer 1 Counter Modulo
Register Low (T1MODL)
Read:
Write:
Bit 7654321Bit 0
Reset:11111111
Read:CH0F
Write:0
CH0IEMS0BMS0AELS0BELS0ATOV0CH0MAX
Reset:00000000
Read:
Write:
Bit 1514131211109Bit 8
$0025
$0026
Timer 1 Channel 0 Status
and Control Register
(T1SC0)
Timer 1 Channel 0
Register High (T1CH0H)
Reset:Indeterminate after reset
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
Read:
Write:
Bit 7654321Bit 0
Reset:Indeterminate after reset
† One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Timer 1 Channel 1 Status and
$0028
Control Register (T1SC1)
Read:CH1F
Write:0
CH1IE
0
MS1AELS1BELS1ATOV1CH1MAX
Reset:00000000
$0029
Timer 1 Channel 1
Register High (T1CH1H)
Read:
Write:
Bit 1514131211109Bit 8
Reset:Indeterminate after reset
= UnimplementedR = ReservedU = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
32Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register NameBit 7654321Bit 0
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
↓
$0035
$0036
$0037
Timer 1 Channel 1
Register Low (T1CH1L)
Timer 2 Status and Control
Register (T2SC)
Timer 2 Counter Register
High (T2CNTH)
Timer 2 Counter Register
Low (T2CNTL)
Timer 2 Counter Modulo
Register High (T2MODH)
Timer 2 Counter Modulo
Register Low (T2MODL)
Timer 2 Channel 0 Status
and Control Register
(T2SC0)
Timer 2 Channel 0
Register High (T2CH0H)
Timer 2 Channel 0
Register Low (T2CH0L)
Unimplemented
PLL Control Register
(PCTL)
PLL Bandwidth Control
Register (PBWC)
Read:
Write:
Reset:Indeterminate after reset
Read:TOF
Write:0TRST
Reset:00100000
Read:Bit 1514131211109Bit 8
Write:
Reset:00000000
Read:Bit 7654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Read:CH0F
Write:0
Reset:00000000
Read:
Write:
Reset:Indeterminate after reset
Read:
Write:
Reset:Indeterminate after reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00100000
Read:
Write:
Reset:00000000
Bit 7654321Bit 0
TOIETSTOP
Bit 1514131211109Bit 8
Bit 7654321Bit 0
CH0IEMS0BMS0AELS0BELS0ATOV0CH0MAX
Bit 1514131211109Bit 8
Bit 7654321Bit 0
PLLIE
AUTO
PLLF
LOCK
= UnimplementedR = ReservedU = Unaffected
PLLONBCSPRE1PRE0VPR1VPR0
ACQ
00
0000
PS2PS1PS0
R
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor33
Memory Map
Addr.Register NameBit 7654321Bit 0
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003FUnimplemented
$FE00
$FE01
$FE02Unimplemented
$FE03
PLL Multiplier Select High
Register (PMSH)
PLL Multiplier Select Low
Register (PMSL)
PLL VCO Select Range
Register (PMRS)
PLL Reference Divider
Select Register (PMDS)
Analog-to-Digital Status and
Control Register
(ADSCR)
Analog-to-Digital Data
Register (ADR)
Analog-to-Digital Input Clock
Register (ADCLK)
SIM Break Status Register
(SBSR)
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
(SRSR)
SIM Break Flag Control
Register (SBFCR)
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read:0000
Write:
Reset:00000001
Read:COCO
Write:R
Reset:00011111
Read:AD7AD6AD5AD4AD3AD2AD1AD0
Write:RRRRRRRR
Reset:Indeterminate after reset
Read:
Write:RRRR
Reset:00000000
Read:
Write:
Reset:
Read:
Write:NOTE
Reset:00000000
Read:PORPINCOPILOPILADMODRSTLVI0
Write:
POR:10000000
Read:
Write:
Reset:
Read:
Write:
Reset:0
MUL7MUL6MUL5MUL4MUL3MUL2MUL1MUL0
VRS7VRS6VRS5VRS4VRS3VRS2VRS1VRS0
AIENADCOADCH4ADCH3ADCH2ADCH1ADCH0
ADIV2ADIV1ADIV0ADICLK
RRRRRR
BCFERRRRRRR
= UnimplementedR = ReservedU = Unaffected
MUL11MUL10MUL9MUL8
RDS3RDS2RDS1RDS0
0000
SBSW
R
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
34Freescale Semiconductor
Input/Output (I/O) Section
Addr.Register NameBit 7654321Bit 0
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0CLVI Status Register (LVISR)
$FF7E
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
FLASH Test Control
Register (FLTCR)
FLASH Control Register
(FLCR)
Break Address Register High
(BRKH)
Break Address Register Low
(BRKL)
Break Status and Control
Register (BRKSCR)
FLASH Block Protect
Register (FLBPR)
Read:IF6IF5IF4IF3IF2IF100
Write:RRRRRRRR
(INT1)
Reset:00000000
Read:IF14IF13IF12IF11IF10IF9IF8IF7
Write:RRRRRRRR
(INT2)
Reset:00000000
Read:000000IF16IF15
Write:RRRRRRRR
(INT3)
Reset:00000000
Read:
Write:
Reset:00000000
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:LVIOUT0000000
Write:
Reset:00000000
Read:
Write:
†
Reset:UUUUUUUU
RRRRRRRR
HVENMASSERASEPGM
Bit 1514131211109Bit 8
Bit 7654321Bit 0
BRKEBRKA
BPR7BPR6BPR5BPR4BPR3BPR2BPR1BPR0
000000
Read:Low byte of reset vector
Write:Writing clears COP counter (any value)
Reset:Unaffected by reset
= UnimplementedR = ReservedU = Unaffected
$FFFF
COP Control Register
(COPCTL)
† Non-volatile FLASH register
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor35
Memory Map
.
Table 2-1. Vector Addresses
Vector PriorityVectorAddressVector
Lowest
Highest$FFFFReset Vector (Low)
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
—
$FFDCTimebase Vector (High)
$FFDDTimebase Vector (Low)
$FFDEADC Conversion Complete Vector (High)
$FFDFADC Conversion Complete Vector (Low)
$FFE0Keyboard Vector (High)
$FFE1Keyboard Vector (Low)
$FFE2SCI Transmit Vector (High)
$FFE3SCI Transmit Vector (Low)
$FFE4SCI Receive Vector (High)
$FFE5SCI Receive Vector (Low)
$FFE6SCI Error Vector (High)
$FFE7SCI Error Vector (Low)
$FFE8SPI Transmit Vector (High)
$FFE9SPI Transmit Vector (Low)
$FFEASPI Receive Vector (High)
$FFEBSPI Receive Vector (Low)
$FFECTIM2 Overflow Vector (High)
$FFEDTIM2 Overflow Vector (Low)
$FFEE
$FFEF
$FFF0TIM2 Channel 0 Vector (High)
$FFF1TIM2 Channel 0 Vector (Low)
$FFF2TIM1 Overflow Vector (High)
$FFF3TIM1 Overflow Vector (Low)
$FFF4TIM1 Channel 1 Vector (High)
$FFF5TIM1 Channel 1 Vector (Low)
$FFF6TIM1 Channel 0 Vector (High)
$FFF7TIM1 Channel 0 Vector (Low)
$FFF8PLL Vector (High)
$FFF9PLL Vector (Low)
$FFFAIRQ
$FFFBIRQ
$FFFCSWI Vector (High)
$FFFDSWI Vector (Low)
$FFFEReset Vector (High)
Reserved
Reserved
Vector (High)
Vector (Low)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
36Freescale Semiconductor
Chapter 3
Low-Power Modes
3.1 Introduction
The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08
MCUs and are entered through instruction execution. This section describes how each module acts in the
low-power modes.
3.1.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but
the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See Chapter 8 Configuration Register
(CONFIG).)
3.1.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock
is disabled if the OSCSTOPENB bit in the CONFIG register is at a logic 0. (See Chapter 8 Configuration
Register (CONFIG).)
3.2 Analog-to-Digital Converter (ADC)
3.2.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
3.2.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
3.3 Break Module (BRK)
3.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if the BW bit in the break status register is set.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor37
Low-Power Modes
3.3.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the BW
bit in the break status register. The STOP instruction does not affect break module register states.
3.4 Central Processor Unit (CPU)
3.4.1 Wait Mode
The WAIT instruction:
•Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
3.4.2 Stop Mode
The STOP instruction:
•Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
3.5 Clock Generator Module (CGM)
3.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
3.5.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the
PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal
clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the
crystal clock divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off, but the
oscillator will continue to operate in stop mode.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
38Freescale Semiconductor
Computer Operating Properly Module (COP)
3.6 Computer Operating Properly Module (COP)
3.6.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine or a DMA service routine.
3.6.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent
inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the
STOP bit.
3.7 External Interrupt Module (IRQ)
3.7.1 Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK1 bit in the IRQ status and control
register enables IRQ
CPU interrupt requests to bring the MCU out of wait mode.
3.7.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 bit in the IRQ status and control
register enables IRQ
CPU interrupt requests to bring the MCU out of stop mode.
3.8 Keyboard Interrupt Module (KBI)
3.8.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
3.8.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
3.9 Low-Voltage Inhibit Module (LVI)
3.9.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor39
Low-Power Modes
3.9.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
3.10 Serial Communications Interface Module (SCI)
3.10.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
3.10.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI
module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
3.11 Serial Peripheral Interface Module (SPI)
3.11.1 Wait Mode
The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module
can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
3.11.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI
operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
3.12 Timer Interface Module (TIM1 and TIM2)
3.12.1 Wait Mode
The TIM remains active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU
out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
40Freescale Semiconductor
Timebase Module (TBM)
3.12.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the
TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
3.13 Timebase Module (TBM)
3.13.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
3.13.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
3.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt
vector:
•External reset — A logic 0 on the RST
contents of locations $FFFE and $FFFF.
•External interrupt — A high-to-low transition on an external interrupt pin (IRQ
program counter with the contents of locations: $FFFA and $FFFB; IRQ
•Break interrupt — A break interrupt loads the program counter with the contents of $FFFC and
$FFFD.
•Computer operating properly module (COP) reset — A timeout of the COP counter resets the MCU
and loads the program counter with the contents of $FFFE and $FFFF.
•Low-voltage inhibit module (LVI) reset — A power supply voltage below the V
MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
•Clock generator module (CGM) interrupt — A CPU interrupt request from the phase-locked loop
(PLL) loads the program counter with the contents of $FFF8 and $FFF9.
•Keyboard module (KBI) interrupt — A CPU interrupt request from the KBI module loads the
program counter with the contents of $FFDE and $FFDF.
•Timer 1 interface module (TIM1) interrupt — A CPU interrupt request from the TIM1 loads the
program counter with the contents of:
–$FFF2 and $FFF3; TIM1 overflow
–$FFF4 and $FFF5; TIM1 channel 1
–$FFF6 and $FFF7; TIM1 channel 0
pin resets the MCU and loads the program counter with the
pin) loads the
pin.
voltage resets the
tripf
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor41
Low-Power Modes
•Timer 2 interface module (TIM2) interrupt — A CPU interrupt request from the TIM2 loads the
program counter with the contents of:
–$FFEC and $FFED; TIM2 overflow
–$FFF0 and $FFF1; TIM2 channel 0
•Serial peripheral interface module (SPI) interrupt — A CPU interrupt request from the SPI loads
the program counter with the contents of:
–$FFE8 and $FFE9; SPI transmitter
–$FFEA and $FFEB; SPI receiver
•Serial communications interface module (SCI) interrupt — A CPU interrupt request from the SCI
loads the program counter with the contents of:
–$FFE2 and $FFE3; SCI transmitter
–$FFE4 and $FFE5; SCI receiver
–$FFE6 and $FFE7; SCI receiver error
•Analog-to-digital converter module (ADC) interrupt — A CPU interrupt request from the ADC loads
the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete.
•Timebase module (TBM) interrupt — A CPU interrupt request from the TBM loads the program
counter with the contents of: $FFDC and $FFDD; TBM interrupt.
3.15 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset vector or with an
interrupt vector:
•External reset — A logic 0 on the RST
pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
•External interrupt — A high-to-low transition on an external interrupt pin loads the program counter
with the contents of locations:
–$FFFA and $FFFB; IRQ
pin
–$FFDE and $FFDF; keyboard interrupt pins
•Low-voltage inhibit (LVI) reset — A power supply voltage below the LVI
voltage resets the MCU
tripf
and loads the program counter with the contents of locations $FFFE and $FFFF.
•Break interrupt — A break interrupt loads the program counter with the contents of locations $FFFC
and $FFFD.
•Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents
of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit
stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register controls the oscillator stabilization delay
during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
NOTE
Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
42Freescale Semiconductor
Chapter 4
Resets and Interrupts
4.1 Introduction
Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes
the MCU to its startup condition. An interrupt vectors the program counter to a service routine.
4.2 Resets
A reset immediately returns the MCU to a known startup condition and begins program execution from a
user-defined memory location.
4.2.1 Effects
A reset:
•Immediately stops the operation of the instruction being executed
•Initializes certain control and status bits
•Loads the program counter with a user-defined reset vector address from locations $FFFE and
$FFFF
•Selects CGMXCLK divided by four as the bus clock
4.2.2 External Reset
A logic 0 applied to the RST pin for a time, t
PIN bit in the SIM reset status register.
, generates an external reset. An external reset sets the
IRL
4.2.3 Internal Reset
Sources:
•Power-on reset (POR)
•Computer operating properly (COP)
•Low-power reset circuits
•Illegal opcode
•Illegal address
All internal reset sources pull the RST
devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST
RST PIN
CGMXCLK
INTERNAL
RESET
pin low for 32 CGMXCLK cycles to allow resetting of external
PULLED LOW BY MCU
32 CYCLES32 CYCLES
Figure 4-1. Internal Reset Timing
pin.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor43
Resets and Interrupts
4.2.3.1 Power-On Reset
A power-on reset is an internal reset caused by a positive transition on the V
pin. VDD at the POR must
DD
go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The POR is not a
brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
•Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
•Drives the RST
pin low during the oscillator stabilization delay
•Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
•Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
•Sets the POR bit in the SIM reset status register and clears all other bits in the register
OSC1
PORRST
CGMXCLK
(1)
4096
CYCLES32CYCLES32CYCLES
CGMOUT
RST
PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 4-2. Power-On Reset Recovery
4.2.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
4.2.3.3 Low-Voltage Inhibit Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
LVI trip voltage, V
TRIPF
.
An LVI reset:
•Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles after the power supply voltage rises to V
•Drives the RST pin low for as long as VDD is below V
TRIPF
and during the oscillator stabilization
TRIPF
delay
•Releases the RST
pin 32 CGMXCLK cycles after the oscillator stabilization delay
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
44Freescale Semiconductor
Resets
•Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
•Sets the LVI bit in the SIM reset status register
4.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP instruction causes an illegal
opcode reset.
4.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
4.2.4 SIM Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are automatically cleared
following a read of the register. Reset service can read the SIM reset status register to clear the register
after power-on reset and to determine the source of any subsequent reset.
The register is initialized on powerup as shown with the POR bit set and all other bits cleared. During a
POR or any other internal reset, the RST
XCLK cycles later. If the pin is not above a V
pin is pulled low. After the pin is released, it will be sampled 32
at that time, then the PIN bit in the SRSR may be set in
IH
addition to whatever other bits are set.
NOTE
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register, multiple
flags remain set.
Address:$FE01
Bit 7654321Bit 0
Read:PORPINCOPILOPILAD0LVI0
Write:
POR:10000000
= Unimplemented
Figure 4-3. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST
pin since last read of SRSR
0 = POR or read of SRSR since last external reset
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor45
Resets and Interrupts
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
4.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
STACKING
ORDER
•
•
•
CONDITION CODE REGISTER
5
4
3
PROGRAM COUNTER (HIGH BYTE)
2
PROGRAM COUNTER (LOW BYTE)
1
*High byte of index register is not stacked.
ACCUMULATOR
INDEX REGISTER (LOW BYTE)*
•
•
•
Figure 4-4. Interrupt Stacking Order
1
2
3
UNSTACKING
ORDER
4
5
$00FF DEFAULT ADDRESS ON RESET
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
46Freescale Semiconductor
Interrupts
4.3.1 Effects
An interrupt:
•Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
•Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
•Loads the program counter with a user-defined vector address
After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one
interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the
example shown in Figure 4-5, if an interrupt is pending upon exit from the interrupt service routine, the
pending interrupt is serviced before the LDA instruction is executed.
CLI
BACKGROUND
ROUTINE
INT1
INT2
Figure 4-5
#$FF
LDA
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor47
Resets and Interrupts
FROM RESET
YES
BREAK
INTERRUPT
?
NO
I BIT SET?
I BIT SET?
NO
IRQ
INTERRUPT
?
NO
CGM
INTERRUPT
?
NO
OTHER
INTERRUPTS
?
NO
YES
YES
YES
YES
STACK CPU REGISTERS
LOAD PC WITH INTERRUPT VECTOR
SET I BIT
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
NO
RTI
INSTRUCTION
?
NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 4-6. Interrupt Processing
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
48Freescale Semiconductor
4.3.2 Sources
Interrupts
The sources in Table 4-1 can generate CPU interrupt requests.
Table 4-1. Interrupt Sources
SourceFlag
ResetNoneNoneNone0
SWI instructionNoneNoneNone0
pinIRQFIMASK1IF11
IRQ
CGM (PLL)PLLFPLLIEIF22$FFF8–$FFF9
TIM1 channel 0CH0FCH0IEIF33$FFF6–$FFF7
TIM1 channel 1CH1FCH1IEIF44$FFF4–$FFF5
TIM1 overflowTOFTOIEIF55$FFF2–$FFF3
TIM2 channel 0CH0FCH0IEIF66$FFF0–$FFF1
TIM2 overflowTOFTOIEIF88$FFEC–$FFED
SPI receiver fullSPRFSPRIE
SPI mode faultMODFERRIE
SPI transmitter emptySPTESPTIEIF1010$FFE8–$FFE9
Mask
(1)
INT Register
Flag
IF99$FFEA–$FFEBSPI overflowOVRFERRIE
Priority
(2)
Vector
Address
$FFFE
–$FFFF
$FFFC–$FFFD
$FFFA
–$FFFB
SCI receiver overrunORORIE
SCI noise fagNFNEIE
SCI framing errorFEFEIE
SCI parity errorPEPEIE
SCI receiver fullSCRFSCRIE
SCI input idleIDLEILIE
SCI transmitter emptySCTESCTIE
SCI transmission completeTCTCIE
Keyboard pinKEYFIMASKKIF1414$FFDE–$FFDF
ADC conversion completeCOCOAIENIF1515$FFDE–$FFDF
TimebaseTBIFTBIEIF1616$FFDC–$FFDD
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
IF1111$FFE6–$FFE7
IF1212$FFE4–$FFE5
IF1313$FFE2–$FFE3
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor49
Resets and Interrupts
4.3.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable interrupt.
NOTE
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
4.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
4.3.2.3 IRQ
A logic 0 on the IRQ1
Pin
pin latches an external interrupt request.
4.3.2.4 CGM (Clock Generator Module)
The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or
leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register.
PLLF is in the PLL control register.
4.3.2.5 TIM1 (Timer Interface Module 1)
TIM1 CPU interrupt sources:
•TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter value rolls over to $0000
after matching the value in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable
bit, TOIE, enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status
and control register.
•TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register.
4.3.2.6 TIM2 (Timer Interface Module 2)
TIM2 CPU interrupt sources:
•TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000
after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable
bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status
and control register.
•TIM2 channel flag (CH0F) — The CH0F bit is set when an input capture or output compare occurs
on channel 0. The channel 0 interrupt enable bit, CH0IE, enables channel 0 TIM2 CPU interrupt
requests. CH0F and CH0IE are in the TIM2 channel 0 status and control register.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
50Freescale Semiconductor
Interrupts
4.3.2.7 SPI (Serial Peripheral Interface)
SPI CPU interrupt sources:
•SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register
to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control
register.
•SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte transfers from the transmit
data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control
register.
•Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS
pin goes high during a
transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if
the SS
pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE,
enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
•Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data
register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control
register.
4.3.2.8 SCI (Serial Communications Interface)
SCI CPU interrupt sources:
•SCI transmitter empty bit (SCTE) — SCTE is set when the SCI data register transfers a character
to the transmit shift register. The SCI transmit interrupt enable bit, SCTIE, enables transmitter CPU
interrupt requests. SCTE is in SCI status register 1. SCTIE is in SCI control register 2.
•Transmission complete bit (TC) — TC is set when the transmit shift register and the SCI data
register are empty and no break or idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt requests. TC is in SCI status register
1. TCIE is in SCI control register 2.
•SCI receiver full bit (SCRF) — SCRF is set when the receive shift register transfers a character to
the SCI data register. The SCI receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI control register 2.
•Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic 1s shift in from the RxD pin.
The idle line interrupt enable bit, ILIE, enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.
•Receiver overrun bit (OR) — OR is set when the receive shift register shifts in a new character
before the previous character was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1.
ORIE is in SCI control register 3.
•Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters,
including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control
register 3.
•Framing error bit (FE) — FE is set when a logic 0 occurs where the receiver expects a stop bit. The
framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor51
Resets and Interrupts
•Parity error bit (PE) — PE is set when the SCI detects a parity error in incoming data. The parity
error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
4.3.2.9 KBD0
–KBD4 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt request.
4.3.2.10 ADC (Analog-to-Digital Converter)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled.
4.3.2.11 TBM (Timebase Module)
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
4.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 4-2. Interrupt Source Flags
Interrupt SourceInterrupt Status Register Flag
Reset—
SWI instruction—
pinIF1
IRQ
CGM (PLL)IF2
TIM1 channel 0IF3
TIM1 channel 1IF4
TIM1 overflowIF5
TIM2 channel 0IF6
ReservedIF7
TIM2 overflowIF8
SPI receiveIF9
SPI transmitIF10
SCI errorIF11
SCI receiveIF12
SCI transmitIF13
KeyboardIF14
ADC conversion completeIF15
TimebaseIF16
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
52Freescale Semiconductor
Interrupts
4.3.3.1 Interrupt Status Register 1
Address:$FE04
Bit 7654321Bit 0
Read:IF6IF5IF4IF3IF2IF100
Write:RRRRRRRR
Reset:00000000
R = Reserved
Figure 4-7. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the sources shown in Table 4-2.
This section describes the 8-bit analog-to-digital converter (ADC).
For further information regarding analog-to-digital converters on Freescale microcontrollers, please
consult the HC08 ADC Reference Manual, ADCRM/AD.
5.2 Features
Features of the ADC module include:
•Six channels with multiplexed input
•Linear successive approximation with monotonicity
•8-bit resolution
•Single or continuous conversion
•Conversion complete flag or conversion complete interrupt
•Selectable ADC clock
5.3 Functional Description
The ADC provides six pins for sampling external sources at pins PTB5/ATD5–PTB0/ATD0. An analog
multiplexer allows the single ADC converter to select one of six ADC channels as ADC voltage in (V
V
is converted by the successive approximation register-based analog-to-digital converter. When the
ADIN
conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an
interrupt. See Figure 5-1.
NOTE
References to DMA (direct-memory access) and associated functions are
only valid if the MCU has a DMA module. If the MCU has no DMA, any
DMA-related register bits should be left in their reset state for expected
MCU operation.
ADIN
).
5.3.1 ADC Port I/O Pins
PTB5/ATD5–PTB0/ATD0 are general-purpose I/O (input/output) pins that share with the ADC channels.
The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins
are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the
ADC will return a logic 0.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor55
Analog-to-Digital Converter (ADC)
INTERNAL DATA BUS
READ DDRBx
WRITE DDRBx
WRITE PTBx
READ PTBx
INTERRUPT
LOGIC
AIENCOCO
RESET
CONVERSION
COMPLETE
CGMXCLK
BUS CLOCK
Figure 5-1. ADC Block Diagram
DDRBx
PTBx
ADC DATA REGISTER
ADC
ADC CLOCK
CLOCK
GENERATOR
ADIV2–ADIV0ADICLK
DISABLE
ADC
VOLTAGE IN
)
(V
ADIN
DISABLE
CHANNEL
SELECT
PTBx
ADC CHANNEL x
ADCH4–ADCH0
5.3.2 Voltage Conversion
When the input voltage to the ADC equals V
input voltage equals V
, the ADC converts it to $00. Input voltages between V
REFL
straight-line linear conversion. All other input voltages will result in $FF, if greater than V
Inside the ADC module, the reference voltage, V
ADC analog power V
ground V
. Therefore, the ADC input voltage should not exceed the
DDAD
DDAD
; and V
analog supply voltages
For operation, V
should be tied to the same potential as V
DDAD
separate traces
, the ADC converts the signal to $FF (full scale). If the
REFH
and V
REFH
REFH
NOTE
is connected to the
REFH
is connected to the ADC analog
REFL
via
DD
REFL
.
are a
5.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles. The ADIVx and ADICLK bits should be set to provide a 1 MHz ADC clock frequency.
Conversion time =
Number of bus cycles = conversion time x bus frequency
16 to17 ADC cycles
ADC frequency
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
56Freescale Semiconductor
Interrupts
5.3.4 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit is cleared. The COCO/IDMAS bit is set after the first
conversion and will stay set until the next write of the ADC status and control register or the next read of
the ADC data register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs
between writes to the ADSCR.
5.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
5.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC
conversion. A CPU interrupt is generated if the COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set,
a DMA interrupt is generated. The COCO/IDMAS bit is not used as a conversion complete flag when
interrupts are enabled.
5.5 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power-consumption standby modes.
5.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
5.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
5.6 I/O Signals
The ADC module has six pins shared with port B, PTB5/AD5–PTB0/ATD0.
5.6.1 ADC Analog Power Pin (V
The ADC analog portion uses V
potential as V
. External filtering may be necessary to ensure clean V
DD
For maximum noise immunity, route V
capacitors as close as possible to the package.
DDAD
)/ADC Voltage Reference High Pin (V
DDAD
as its power pin. Connect the V
DDAD
DDAD
NOTE
carefully and place bypass
DDAD
)
REFH
pin to the same voltage
for good results.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor57
Analog-to-Digital Converter (ADC)
5.6.2 ADC Analog Ground Pin (V
The ADC analog portion uses V
potential as V
SS
.
as its ground pin. Connect the V
SSAD
)/ADC Voltage Reference Low Pin (V
SSAD
SSAD
NOTE
Route V
5.6.3 ADC Voltage In (V
V
is the input voltage signal from one of the six ADC channels to the ADC module.
ADIN
cleanly to avoid any offset errors.
SSAD
)
ADIN
5.7 I/O Registers
These I/O registers control and monitor ADC operation:
•ADC status and control register (ADSCR)
•ADC data register (ADR)
•ADC clock register (ADCLK)
5.7.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address:$0003C
Bit 7654321Bit 0
Read:
Write:
Reset:00011111
COCO/
IDMAS
AIENADCOADCH4ADCH3ADCH2ADCH1ADCH0
)
REFL
pin to the same voltage
Figure 5-2. ADC Status and Control Register (ADSCR)
COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit
When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit which is set each time a conversion
is completed except in the continuous conversion mode where it is set after the first conversion. This
bit is cleared whenever the ADSCR is written or whenever the ADR is read.
If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which selects either CPU or DMA to
service the ADC interrupt request. Reset clears this bit.
Because the MC68HC908GR8 does NOT have a DMA module, the IDMAS
bit should NEVER be set when AIEN is set. Doing so will mask ADC
interrupts and cause unwanted results.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
When this bit is set, the ADC will convert samples continuously and update the ADR register at the end
of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is
cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only six channels,
AD5–AD0, are available on this MCU. The channels are detailed in Table 5-1. Care should be taken
when using a port pin as both an analog and digital input simultaneously to prevent switching noise
from corrupting the analog signal. See Table 5-1.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in Table 5-1, are used to verify the
operation of the ADC converter both in production test and for user applications.
Table 5-1. Mux Channel Select
ADCH4ADCH3ADCH2ADCH1ADCH0Input Select
00000 PTB0/ATD0
00001 PTB1/ATD1
00010 PTB2/ATD2
00011 PTB3/ATD3
00100 PTB4/ATD4
00101 PTB5/ATD5
00110Reserved
00111Reserved
↓↓↓↓↓Reserved
11011Reserved
11100Reserved
11101
11110
11111ADC power off
NOTE: If an unknown channel is selected it should be made clear what value the user will read
from the ADC Data Register, unknown or reserved is not specific enough.
V
V
REFH
REFL
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor59
Analog-to-Digital Converter (ADC)
5.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
Address:$0003D
Bit 7654321Bit 0
Read:AD7AD6AD5AD4AD3AD2AD1AD0
Write:
Reset:00000000
= Unimplemented
Figure 5-3. ADC Data Register (ADR)
5.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address:$0003E
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
ADIV2ADIV1ADIV0ADICLK
= Unimplemented
0000
Figure 5-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 5-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal
ADC clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADC input clock frequency
------------------------- --------------------------------------- -------1 M H z=
ADIV2 ADIV0–
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
60Freescale Semiconductor
Chapter 6
Break Module (BRK)
6.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
6.2 Features
Features of the break module include:
•Accessible input/output (I/O) registers during the break interrupt
•CPU-generated break interrupts
•Software-generated break interrupts
•COP disabling during break interrupts
6.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
•Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation. Figure 6-1 shows the
structure of the break module.
6.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor61
Break Module (BRK)
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB15–IAB0
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
BREAK
Figure 6-1. Break Module Block Diagram
Addr.Register NameBit 7654321Bit 0
$FE00
$FE03
$FE09
$FE0A
$FE0B
Note: Writing a logic 0 clears BW.
SIM Break Status Register
SIM Break Flag Control
Register (SBFCR)
Break Address Register High
Break Address Register Low
Break Status and Control
Register (BRKSCR)
(SBSR)
(BRKH)
(BRKL)
Read:000100BW0
Write:RRRRRRNOTER
Reset:00010000
Read:
Write:
Reset:0
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
BCFERRRRRRR
Bit 1514131211109Bit 8
Bit 7654321Bit 0
BRKEBRKA
= UnimplementedR= Reserved
000000
Figure 6-2. I/O Register Summary
6.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•Loading the instruction register with the SWI instruction
•Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
62Freescale Semiconductor
6.3.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
6.3.4 COP During Break Interrupts
Low-Power Modes
The COP is disabled during a break interrupt when V
is present on the RST pin.
TST
6.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set. See Chapter 3 Low-Power Modes. Clear the BW bit by
writing logic 0 to it.
6.4.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
6.5 Break Module Registers
These registers control and monitor operation of the break module:
•Break status and control register (BRKSCR)
•Break address register high (BRKH)
•Break address register low (BRKL)
•SIM break status register (SBSR)
•SIM break flag control register (SBFCR)
6.5.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address:$FE0E
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
BRKEBRKA
= Unimplemented
Figure 6-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0
to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor63
000000
Break Module (BRK)
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
6.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address:$FE09
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
Address:$FE0A
Read:
Write:
Reset:00000000
Bit 1514131211109Bit 8
Figure 6-4. Break Address Register High (BRKH)
Bit 7654321Bit 0
Bit 7654321Bit 0
Figure 6-5. Break Address Register Low (BRKL)
6.5.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode.
The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.
Address:$FE00
Bit 7654321Bit 0
Read:000100BW0
Write:RRRRRRNOTER
Reset:00010000
Note: Writing a logic 0 clears BW.R= Reserved
Figure 6-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from wait mode. Clear BW by writing a
logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify the return address on the stack
by subtracting 1 from it. The following code is an example.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
64Freescale Semiconductor
Break Module Registers
This code works if the H register was stacked in the break interrupt routine. Execute this code at the end
of the break interrupt routine.
HIBYTEEQU5
LOBYTEEQU6
;If not BW, do RTI
BRCLRBW,BSR, RETURN;;See if wait mode or stop mode
was exited by break.
TSTLOBYTE,SP; If RETURNLO is not 0,
BNEDOLO; then just decrement low byte.
DECHIBYTE,SP; Else deal with high byte also.
DOLODECLOBYTE,SP; Point to WAIT/STOP opcode.
RETURNPULH
RTI
; Restore H register.
6.5.4 Break Flag Control Register
The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the
MCU is in a break state.
Address:$FE03
Bit 7654321Bit 0
Read:
Write:
Reset:0
BCFERRRRRRR
R= Reserved
Figure 6-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor65
Break Module (BRK)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
66Freescale Semiconductor
Chapter 7
Clock Generator Module (CGMC)
7.1 Introduction
This section describes the clock generator module. The CGMC generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of CGMOUT/2. In monitor mode, PTC3
determines the bus clock. The PLL is a fully functional frequency generator designed for use with crystals
or ceramic resonators. The PLL can generate an 8-MHz bus frequency using a 32-kHz crystal.
7.2 Features
Features of the CGMC include:
•Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
•Low-frequency crystal operation with low-power operation and high-output frequency resolution
•Programmable prescaler for power-of-two increases in frequency
•Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
•Automatic bandwidth control mode for low-jitter operation
•Automatic frequency lock detector
•CPU interrupt on entry or exit from locked condition
•Configuration register bit to allow oscillator operation during stop mode
7.3 Functional Description
The CGMC consists of three major submodules:
•Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
•Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
•Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from either CGMOUT or CGMXCLK.
Figure 7-1 shows the structure of the CGMC.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor67
Clock Generator Module (CGMC)
OSC2
OSC1
SIMOSCEN (FROM SIM)
OSCSTOPENB
(FROM CONFIG)
OSCILLATOR (OSC)
CGMXCLK
(TO: SIM, TIMTB15A, ADC)
PHASE-LOCKED LOOP (PLL)
CGMRDV
REFERENCE
DIVIDER
RDS3–RDS0
PHASE
DETECTOR
LOCK
DETECTOR
LOCKAUTOACQ
MUL11–MUL0
V
DDA
CGMRCLK
CGMXFCV
LOOP
FILTER
AUTOMATIC
MODE
CONTROL
SSA
VRS7–VRS0
PLL ANALOG
PRE1–PRE0
BCS
VPR1–VPR0
VOLTAGE
CONTROLLED
OSCILLATOR
INTERRUPT
CONTROL
PLLIEPLLF
CLOCK
SELECT
CIRCUIT
CGMVCLK
³ 2
CGMOUT
(TO SIM)
PLLIREQ
(TO SIM)
CGMVDV
FREQUENCY
DIVIDER
FREQUENCY
DIVIDER
Figure 7-1. CGMC Block Diagram
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
68Freescale Semiconductor
Functional Description
7.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
7.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
7.3.3 PLL Circuits
The PLL consists of these circuits:
•Voltage-controlled oscillator (VCO)
•Reference divider
•Frequency prescaler
•Modulo VCO frequency divider
•Phase detector
•Loop filter
•Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a
range from roughly one-half to twice the center-of-range frequency, f
CGM/XFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
E
(L × 2
)f
NOM
.
, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
NOM
. Modulating the voltage on the
VRS
is equal to the nominal
VRS
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
, and is fed to the PLL through a programmable modulo reference divider, which divides f
f
RCLK
RCLK
by a
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
RDV=fRCLK
/R. With an external crystal
(30 kHz–100 kHz), always set R = 1 for specified performance. With an external high-frequency clock
source, use R to divide the external frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
, is fed back through a programmable
VCLK
prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a
power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’
output is the VCO feedback clock, CGMVDV, running at a frequency, f
VDV=fVCLK
/(N × 2P). (See
7.3.6 Programming the PLL for more information.)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor69
Clock Generator Module (CGMC)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 7.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the
reference frequency determine the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
. The circuit determines the mode of the PLL and the lock condition based on
RDV
this comparison.
7.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
•Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ
the PLL bandwidth control register. (See 7.5.2 PLL Bandwidth Control Register.)
•Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 7.3.8 Base Clock Selector Circuit.) The PLL is automatically in
tracking mode when not in acquisition mode or when the ACQ
bit is set.
bit is clear in
7.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 7.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. (See 7.3.8 Base Clock Selector Circuit.) If
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See
Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control mode:
•The ACQ
filter. (See 7.3.4 Acquisition and Tracking Modes.)
•The ACQ
VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for
more information.)
•The LOCK bit is a read-only indicator of the locked state of the PLL.
bit (see 7.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the
bit is set when the VCO frequency is within a certain tolerance and is cleared when the
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
70Freescale Semiconductor
Functional Description
•The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for
more information.)
•CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 7.5.1 PLL Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f
BUSMAX
.
The following conditions apply when in manual mode:
•ACQ
•Before entering tracking mode (ACQ
is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ
bit must be clear.
= 1), software must wait a given time, t
ACQ
(see
7.8 Acquisition/Lock Time Specifications), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
•Software must wait a given time, t
, after entering tracking mode before selecting the PLL as the
AL
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor71
Clock Generator Module (CGMC)
When the tolerance on the bus frequency is tight, choose f
and R = 1. If f
practical choices of f
cannot meet this requirement, use the following equation to solve for R with
RCLK
, and choose the f
RCLK
Rround R
f
⎛⎞
⎧⎫
VCLKDES
--------------------------
×=
⎜⎟
⎨⎬
MAX
f
⎝⎠
RCLK
⎩⎭
that gives the lowest R.
RCLK
4.Select a VCO frequency multiplier, N.
×
Rf
⎛⎞
VCLKDES
=
Nround
-------------------------------------
⎜⎟
f
⎝⎠
RCLK
Reduce N/R to the lowest possible R.
5.If N is < N
, use P = 0. If N > N
max
, choose P using this table:
max
Current N ValueP
0N<N
≤
max
N
N
N
max
max
max
2×N<N
4×N<N
N<N
max
max
max
2×≤
integer
–
4×≤
8×≤
to an integer divisor of f
RCLK
f
⎛⎞
VCLKDES
--------------------------
⎜⎟
f
⎝⎠
RCLK
0
1
2
3
BUSDES
,
Then recalculate N:
×
Rf
⎛⎞
VCLKDES
Nround
=
6.Calculate and verify the adequacy of the VCO and bus frequencies f
f
VCLK
f
BUS
-------------------------------------
⎜⎟
⎝⎠
f
RCLK
2PNR⁄×()f
f
()4⁄=
VCLK
×=
2P×
RCLK
VCLK
7.Select the VCO’s power-of-two range multiplier E, according to this table:
Frequency RangeE
0 < f
9,830,400 ≤ f
19,660,800 ≤ f
NOTE: Do not program E to a value of 3.
8.Select a VCO linear range multiplier, L, where f
< 9,830,4000
VCLK
< 19,660,8001
VCLK
< 39,321,6002
VCLK
= 38.4 kHz
NOM
f
⎛⎞
VCLK
Lround
=
--------------------------
⎜⎟
⎝⎠
2Ef
×
NOM
and f
BUS
.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
72Freescale Semiconductor
Functional Description
9.Calculate and verify the adequacy of the VCO programmed center-of-range frequency, f
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
f
VRS
=
E
L2
×()f
NOM
For proper operation,
f
NOM
f
–
VRSfVCLK
--------------------------
≤
10.Verify the choice of P, R, N, E, and L by comparing f
operation, f
as possible to f
must be within the application’s tolerance of f
VCLK
.
VCLK
2E×
2
VCLK
to f
and f
VRS
VCLKDES
VCLKDES
, and f
VRS
. For proper
must be as close
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
11.Program the PLL registers accordingly:
a.In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b.In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
VRS
. The
c.In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
d.In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
e.In the PLL reference divider select register (PMDS), program the binary coded equivalent
of R.
Table 7-1 provides numeric examples (numbers are in hexadecimal notation):
Table 7-1. Numeric Example
f
BUS
2.0 MHz32.768 kHz1F500D1
2.4576 MHz32.768 kHz112C0180
2.5 MHz32.768 kHz11320183
4.0 MHz32.768 kHz11E901D1
4.9152 MHz32.768 kHz12580280
5.0 MHz32.768 kHz12630282
7.3728 MHz32.768 kHz138402C0
8.0 MHz32.768 kHz13D102D0
f
RCLK
RNPEL
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor73
Clock Generator Module (CGMC)
7.3.7 Special Programming Exceptions
The programming method described in 7.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
•A 0 value for R or N is interpreted exactly the same as a value of 1.
•A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
(See 7.3.8 Base Clock Selector Circuit.)
7.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
7.3.9 CGMC External Connections
In its typical configuration, the CGMC requires up to nine external components. Five of these are for the
crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-2.
Figure 7-2 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•Crystal, X
•Fixed capacitor, C
•Tuning capacitor, C2 (can also be a fixed capacitor)
•Feedback resistor, R
•Series resistor, RS
The series resistor (R
crystal manufacturer’s data for more information regarding values for C1 and C2.
Figure 7-2 also shows the external components for the PLL:
•Bypass capacitor, C
•Filter network
Routing should be done with great care to minimize signal cross talk and noise.
See 23.15.1 CGM Component Specifications for capacitor and resistor values.
1
1
B
) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the
S
BYP
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
74Freescale Semiconductor
SIMOSCEN
OSCSTOPENB
(FROM CONFIG)
I/O Signals
CGMXCLK
OSC1
RB
X1
C1C2
Note: Filter network in box can be replaced with a 0.47 µF capacitor, but will degrade stability.
OSC2
RS
0.033 µF
CGMXFC
10 k
Figure 7-2. CGMC External Connections
7.4 I/O Signals
The following paragraphs describe the CGMC I/O signals.
7.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
0.01 µF
V
SSA
V
DDA
CBYP
0.1 µF
V
DD
7.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 7-2.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor75
Clock Generator Module (CGMC)
7.4.4 PLL Analog Power Pin (V
V
is a power pin used by the analog portions of the PLL. Connect the V
DDA
potential as the V
DD
pin.
DDA
)
NOTE
Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.
7.4.5 PLL Analog Ground Pin (V
SSA
pin to the same voltage
DDA
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
76Freescale Semiconductor
CGMC Registers
7.5 CGMC Registers
These registers control and monitor operation of the CGMC:
•PLL control register (PCTL)
(See 7.5.1 PLL Control Register.)
•PLL bandwidth control register (PBWC)
(See 7.5.2 PLL Bandwidth Control Register.)
•PLL multiplier select register high (PMSH)
(See 7.5.3 PLL Multiplier Select Register High.)
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Control Register
(PCTL)
PLL Bandwidth Control
Register (PBWC)
PLL Multiplier Select High
Register (PMSH)
PLL Multiplier Select Low
Register (PMSL)
PLL VCO Select Range
Register (PMRS)
PLL Reference Divider
Select Register (PMDS)
is read-only.
Read:
Write:
Reset:00100000
Read:
Write:
Reset:00000000
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read:0000
Write:
Reset:00000001
PLLIE
AUTO
MUL7MUL6MUL5MUL4MUL3MUL2MUL1MUL0
VRS7VRS6VRS5VRS4VRS3VRS2VRS1VRS0
PLLF
LOCK
= UnimplementedR= Reserved
PLLONBCSPRE1PRE0VPR1VPR0
ACQ
0000
MUL11MUL10MUL9MUL8
RDS3RDS2RDS1RDS0
R
Figure 7-3. CGMC I/O Register Summary
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor77
Clock Generator Module (CGMC)
7.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
Address:$0036
Bit 7654321Bit 0
Read:
Write:
Reset:00100000
PLLIE
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = Change in lock condition
0 = No change in lock condition
PLLF
= Unimplemented
PLLONBCSPRE1PRE0VPR1VPR0
Figure 7-4. PLL Control Register (PCTL)
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 7.3.8 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGMC output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See 7.3.8 Base Clock
Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
78Freescale Semiconductor
CGMC Registers
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
7.3.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
NOTE
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
Table 7-2. PRE 1 and PRE0 Programming
PRE1 and PRE0PPrescaler Multiplier
0001
0112
1024
1138
VPR1 and 0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.5 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, f
. VPR1:VPR0 cannot be written when
VRS
the PLLON bit is set. Reset clears these bits.
Table 7-3. VPR1 and VPR0 Programming
VPR1 and VPR0E
0001
0112
1024
11
1. Do not program E to a value of 3.
(1)
3
VCO Power-of-Two
Range Multiplier
8
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor79
Clock Generator Module (CGMC)
7.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
•Selects automatic or manual (software-controlled) bandwidth control mode
•Indicates when the PLL is locked
•In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
•In manual operation, forces the PLL into acquisition or tracking mode
Address:$0037
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
AUTO
LOCK
= UnimplementedR= Reserved
ACQ
Figure 7-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ
bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
0000
R
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ
— Acquisition Mode Bit
When the AUTO bit is set, ACQ
or tracking mode. When the AUTO bit is clear, ACQ
is a read-only bit that indicates whether the PLL is in acquisition mode
is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
80Freescale Semiconductor
CGMC Registers
7.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
Address:$0038
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
Figure 7-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) A value of $0000 in
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
MUL11MUL10MUL9MUL8
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as logic 0s.
7.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
Address:$0038
Bit 7654321Bit 0
Read:
Write:
Reset:01000000
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) MUL7–MUL0 cannot
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address:$003A
Bit 7654321Bit 0
Read:
Write:
Reset:01000000
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (see 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.1 PLL Control Register), controls the
hardware center-of-range frequency, f
PCTL is set. (See 7.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 7.3.8 Base
Clock Selector Circuit and 7.3.7 Special Programming Exceptions.). Reset initializes the register to $40
for a default range multiply value of 64.
VRS7VRS6VRS5VRS4VRS3VRS2VRS1VRS0
Figure 7-8. PLL VCO Range Select Register (PMRS)
. VRS7–VRS0 cannot be written when the PLLON bit in the
VRS
NOTE
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
7.5.6 PLL Reference Divider Select Register
NOTE
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See 7.3.7 Special Programming Exceptions.) Reset
initializes the register to $01 for a default divide value of 1.
NOTE
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
7.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
7.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
7.7.1 Wait Mode
The WAIT instruction does not affect the CGMC. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor83
Clock Generator Module (CGMC)
7.7.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGMC (oscillator and phase locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the
PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal
clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the
crystal clock divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
7.7.3 CGMC During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 19.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
7.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
7.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percentage of the step input or when
the output settles to the desired value plus or minus a percentage of the frequency change. Therefore,
the reaction time is constant in this definition, regardless of the size of the step input. For example,
consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to
change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach
1MHz±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers
a –100-kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5kHz.
Five kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
84Freescale Semiconductor
Acquisition/Lock Time Specifications
7.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, f
RDV
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency f
XCLK
and the
R value programmed in the reference divider. (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and
7.5.6 PLL Reference Divider Select Register.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by
adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size
of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make
small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL
may not be able to adjust the voltage in a reasonable time. (See 7.8.3 Choosing a Filter.)
Also important is the operating voltage potential applied to V
. The power supply potential alters the
DDA
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
.
7.8.3 Choosing a Filter
As described in 7.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the
stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage.
Either of the filter networks in Figure 7-10 is recommended when using a 32.768-kHz reference crystal.
In low-cost applications, where stability and reaction time of the PLL is not critical, this filter network can
be replaced by a single capacitor.
CGMXFC
10 k
0.033 µF
Figure 7-10. PLL Filter
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor85
0.01 µF
V
SSA
Clock Generator Module (CGMC)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
86Freescale Semiconductor
Chapter 8
Configuration Register (CONFIG)
8.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers
enable or disable these options:
•Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
•COP timeout period (262,128 or 8176 CGMXCLK cycles)
•STOP instruction
•Computer operating properly module (COP)
•Low-voltage inhibit (LVI) module control and voltage trip point selection
•Enable/disable the oscillator (OSC) during stop mode
8.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. The configuration
register may be read at anytime.
NOTE
To ensure correct operation of the MCU under all operating conditions, the user must write data $1C to
address $0033 immediately after reset. This is to ensure proper termination of an unused module within
the MCU.
NOTE
On a FLASH device, the options except LVI5OR3 are one-time writeable by
the user after each reset. The LVI5OR3 bit is one-time writeable by the user
only after each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writeable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in Figure 8-1 and Figure 8-2.
Address:$001E
Bit 7654321Bit 0
Read:000000
Write:
Reset:00000000
= Unimplemented
OSC-
STOPENB
SCIBD-
SRC
Figure 8-1. Configuration Register 2 (CONFIG2)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor87
Configuration Register (CONFIG)
Address:$001F
Bit 7654321Bit 0
Read:
Write:
Reset:0000See Note000
Note: LVI5OR3 bit is only reset via POR (power-on reset)
COPRSLVISTOPLVIRSTDLVIPWRDLVI5OR3SSRECSTOPCOPD
Figure 8-2. Configuration Register 1 (CONFIG1)
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See Clock
Generator Module (CGM) subsection Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See Chapter 9 Computer Operating
Properly (COP).
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP. See Stop Mode.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).
LVIPWRD disables the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5V or 3V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See Chapter 14 Low-Voltage Inhibit
(LVI). The voltage mode selected for the LVI should match the operating V
. See Chapter 23
DD
Electrical Specifications for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5V mode.
0 = LVI operates in 3V mode.
SSREC — Short Stop Recovery Bit
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
88Freescale Semiconductor
Functional Description
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
When the LVISTOP is enabled, the system stabilization time for power on
reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the MCU
is not protected from a low power condition. However, when using the short
stop recovery configuration option, the 32-CGMXCLK delay is less than the
LVI’s turn-on time and there exists a period in startup where the LVI is not
protecting the MCU.
COPD disables the COP module. See Chapter 9 Computer Operating Properly (COP)
1 = COP module disabled
0 = COP module enabled
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor89
Configuration Register (CONFIG)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
90Freescale Semiconductor
Chapter 9
Computer Operating Properly (COP)
9.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG register.
9.2 Functional Description
Figure 9-1 shows the structure of the COP module.
CGMXCLK
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE
(FROM CONFIG)
RESET
COPCTL WRITE
COP RATE SEL
(FROM CONFIG)
12-BIT COP PRESCALER
CLEAR ALL STAGES
COP CLOCK
COP MODULE
CLEAR STAGES 5–12
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 9-1. COP Block Diagram
RESET CIRCUIT
RESET STATUS REGISTER
COP TIMEOUT
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor91
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration
register. With a 8176 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period
of 250 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12 through 5 of the prescaler.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST
pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST
on the RST pin disables the COP.
V
TST
pin or the IRQ1 is held at V
. During the break state,
TST
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
9.3 I/O Signals
The following paragraphs describe the signals shown in Figure 9-1.
9.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
9.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
9.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see COP Control Register) clears the COP
counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low
byte of the reset vector.
9.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
9.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
9.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
92Freescale Semiconductor
COP Control Register
9.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 8 Configuration Register (CONFIG).
9.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See
Chapter 8 Configuration Register (CONFIG).
9.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7654321Bit 0
Read:Low byte of reset vector
Write:Clear COP counter
Reset:Unaffected by reset
Figure 9-2. COP Control Register (COPCTL)
9.5 Interrupts
The COP does not generate CPU interrupt requests.
9.6 Monitor Mode
When monitor mode is entered with V
on the IRQ
having V
pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
on the IRQ pin, the COP is automatically disabled until a POR occurs.
TST
on the IRQ pin, the COP is disabled as long as V
TST
remains
TST
9.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
9.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear
the COP counter in a CPU interrupt routine.
9.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor93
Computer Operating Properly (COP)
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available
that disables the STOP instruction. When the STOP bit in the configuration register has the STOP
instruction disabled, execution of a STOP instruction results in an illegal opcode reset.
9.8 COP Module During Break Mode
The COP is disabled during a break interrupt when V
is present on the RST pin.
TST
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
94Freescale Semiconductor
Chapter 10
Central Processing Unit (CPU)
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
10.1 Features
Features of the CPU include:
•Object code fully upward-compatible with M68HC05 Family
•16-bit stack pointer with stack manipulation instructions
•16-bit index register with x-register manipulation instructions
•8-MHz CPU internal bus frequency
•64-Kbyte program/data memory space
•16 addressing modes
•Memory-to-memory data moves without using accumulator
•Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•Enhanced binary-coded decimal (BCD) data handling
•Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
•Low-power stop and wait modes
10.2 CPU Registers
Figure 10-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor95
Central Processing Unit (CPU)
7
15
HX
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 10-1. CPU Registers
10.2.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset:Unaffected by reset
Figure 10-2. Accumulator (A)
10.2.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
151413121110987654321
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 10-3. Index Register (H:X)
Bit
0
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
96Freescale Semiconductor
CPU Registers
10.2.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
151413121110987654321
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 10-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
10.2.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
151413121110987654321
Read:
Write:
Reset:Loaded with vector from $FFFE and $FFFF
Bit
0
Figure 10-5. Program Counter (PC)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor97
Central Processing Unit (CPU)
10.2.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X1 1X1XXX
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
V11H I NZC
X = Indeterminate
Figure 10-6. Condition Code Register (CCR)
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
98Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
10.3 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
10.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
10.4.1 Wait Mode
The WAIT instruction:
•Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
10.4.2 Stop Mode
The STOP instruction:
•Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
10.5 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
•Loading the instruction register with the SWI instruction
•Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 5
Freescale Semiconductor99
Central Processing Unit (CPU)
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
10.6 Instruction Set Summary
Table 10-1 provides a summary of the M68HC08 instruction set.
Table 10-1. Instruction Set Summary (Sheet 1 of 6)