MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
MC68HC908AP8
Data Sheet
M68HC08
Microcontrollers
MC68HC908AP64
Rev. 3
8/2005
freescale.com
MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
MC68HC908AP8
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 3
Revision History
Date
Revision
Level
August 2005 3
October 2003 2.5
August 2003 2.4
July 2003 2.3
Description
Table 22-4 . DC Electrical Characteristics (5V) — Updated V
values.
OL
Page
Number(s)
299
Table 22-6 . Oscillator Specifications (5V) and Table 22-10 . Oscillator
Specifications (3V) — Corrected internal oscillator clock frequency,
. Updated crystal oscillator component values CL, C1, C2, RB, and
f
ICLK
.
R
S
301, 305
Added MC68HC908AP16/AP8 information throughout. —
Section 10. Monitor ROM (MON) — Corrected RAM address to $60. 167
Section 24. Electrical Specifications — Added run and wait I
8MHz at 3V.
Section 24. Electrical Specifications — Updated stop I
DD
DD
data.
data for
421
417, 421
Removed MC68HC908AP16 references throughout. —
Table 1-2 . Pin Functions — Added footnote for V
5.3 Configuration Register 1 (CONFIG1) — Clarified LVIPWRD and
LVIREGD bits.
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode — Updated
BSC bit behavior.
REG
.
30
67
125
May 2003 2.2
10.5 ROM-Resident Routines — Corrected data size limits and control
byte size for EE_READ and EE_WRITE.
Figure 12-2 . Timebase Control Register (TBCR) — Corrected register
address.
168–193
207
Section 24. Electrical Specifications — Updated. 415
Updated for f
in CGM section.
= 125kHz and filter components
NOM
101
Updated electricals. 415
MC68HC908AP Family Data Sheet, Rev. 3
4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR) . . . . . . . . . . . . . . . .49
Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Chapter 5 Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 6 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Chapter 7 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 8 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Chapter 9 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Chapter 10 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Chapter 11 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .155
Chapter 12 Infrared Serial Communications Interface Module (IRSCI) . . . . . . . . . . . . . . 181
Chapter 13 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Chapter 14 Multi-Master IIC Interface (MMIIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Chapter 15 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Chapter 16 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Chapter 17 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Chapter 18 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
Chapter 19 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Chapter 20 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Chapter 21 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
Chapter 22 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Chapter 23 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
Chapter 24 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
MC68HC908AP Family Data Sheet, Rev. 3
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List of Chapters
MC68HC908AP Family Data Sheet, Rev. 3
6 Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.4 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6 Power Supply Bypassing (VDD, VDDA, VSS, VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7 Regulator Power Supply Configuration (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.2 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5.3 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5.4 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.5.5 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.5.6 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.5.7 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3 Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4 Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5 Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 4
Central Processor Unit (CPU)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Table of Contents
4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 5
Oscillator (OSC)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2.1 CGM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2.2 TBM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.4 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.5 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6.4 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.6.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.6.6 Oscillator Clock to Time Base Module (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.7 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.8 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 6
Clock Generator Module (CGM)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.5 Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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6.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.4.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.4.2 PLL Analog Power Pin (V
6.4.3 PLL Analog Ground Pin (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SSA
6.4.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.6 CGM VCO Clock Output (CGMVCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.7 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.5 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.5.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.5.4 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.5.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.7 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.8 Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 7
System Integration Module (SIM)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2.2 Clock Start-up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3.2.6 Monitor Mode Entry Module Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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7.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.7.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 8
Monitor ROM (MON)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.3.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.3.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.3.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.3.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.5 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.5.1 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.5.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.5.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.5.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.5.5 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.5.6 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.5.7 EE_READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Chapter 9
Timer Interface Module (TIM)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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9.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.9.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Chapter 10
Timebase Module (TBM)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.4 Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Chapter 11
Serial Communications Interface Module (SCI)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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11.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
11.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
11.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
11.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.8.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Chapter 12
Infrared Serial Communications Interface Module (IRSCI)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
12.2 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.3 IRSCI Module Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.4 Infrared Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.4.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12.4.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12.5 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.5.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.5.2.5 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
12.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.5.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.5.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.5.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
MC68HC908AP Family Data Sheet, Rev. 3
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12.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.7 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.8.1 PTC6/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.8.2 PTC7/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
12.9.1 IRSCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
12.9.2 IRSCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
12.9.3 IRSCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
12.9.4 IRSCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.9.5 IRSCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.9.6 IRSCI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
12.9.7 IRSCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
12.9.8 IRSCI Infrared Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Chapter 13
Serial Peripheral Interface Module (SPI)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.3 Pin Name Conventions and I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
13.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
13.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
13.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
13.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
13.6 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
13.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
13.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
13.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
13.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.12.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.12.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.12.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.12.4 SS
(Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
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13.12.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
13.13.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Chapter 14
Multi-Master IIC Interface (MMIIC)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
14.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
14.4 Multi-Master IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
14.5 Multi-Master IIC Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.5.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.5.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.5.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.5.4 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.5.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.5.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.5.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.5.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.5.9 Packet Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.6 MMIIC I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.6.1 MMIIC Address Register (MMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
14.6.2 MMIIC Control Register 1 (MMCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
14.6.3 MMIIC Control Register 2 (MMCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
14.6.4 MMIIC Status Register (MMSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.6.5 MMIIC Data Transmit Register (MMDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
14.6.6 MMIIC Data Receive Register (MMDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
14.6.7 MMIIC CRC Data Register (MMCRCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
14.6.8 MMIIC Frequency Divider Register (MMFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
14.7 Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
14.7.1 Data Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
14.8 SMBus Protocols with PEC and without PEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
14.8.1 Quick Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
14.8.2 Send Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
14.8.3 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
14.8.4 Write Byte/Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
14.8.5 Read Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
14.8.6 Process Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
14.8.7 Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
14.9 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Chapter 15
Analog-to-Digital Converter (ADC)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
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15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.3.5 Auto-Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.3.6 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
15.3.7 Data Register Interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
15.3.8 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
15.6.1 ADC Voltage In (V
15.6.2 ADC Analog Power Pin (V
15.6.3 ADC Analog Ground Pin (V
15.6.4 ADC Voltage Reference High Pin (V
15.6.5 ADC Voltage Reference Low Pin (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
ADIN
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
DDA
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
SSA
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
REFL
15.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.7.2 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
15.7.3 ADC Data Register 0 (ADRH0 and ADRL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
15.7.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3) . . . . . . . . . . . . . . . . . . . . . . . . . 257
15.7.5 ADC Auto-Scan Control Register (ADASCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Chapter 16
Input/Output (I/O) Ports
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
16.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.2.2 Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.2.3 Port-A LED Control Register (LEDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
16.4 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
16.4.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
16.4.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
16.5 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
16.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
16.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Chapter 17
External Interrupt (IRQ)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
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17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
17.4 IRQ1
17.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
17.6 IRQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
17.6.1 IRQ1 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
17.6.2 IRQ2 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
and IRQ2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Chapter 18
Keyboard Interrupt Module (KBI)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
18.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
18.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
18.5 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
18.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
18.5.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
18.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Chapter 19
Computer Operating Properly (COP)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
19.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
19.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.6 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19.3.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
19.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
19.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
19.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Chapter 20
Low-Voltage Inhibit (LVI)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
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20.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
20.3.1 Low V
20.3.2 Low V
Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
DD
Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
REG
20.3.3 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
20.3.4 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
20.3.5 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
20.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
20.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
20.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
20.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
20.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Chapter 21
Break Module (BRK)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
21.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
21.3.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
21.3.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
21.3.3 TIMI and TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
21.3.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
21.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
21.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.5 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.5.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
21.5.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
21.5.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Chapter 22
Electrical Specifications
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
22.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
22.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
22.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
22.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
22.6 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
22.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
22.8 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
22.9 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
22.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
22.11 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
22.12 3V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
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22.13 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
22.14 CGM Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
22.15 5V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
22.16 3V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
22.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Chapter 23
Mechanical Specifications
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
23.2 48-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
23.3 44-Pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
23.4 42-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Chapter 24
Ordering Information
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
24.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
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Chapter 1 General Description
1.1 Introduction
The MC68HC908AP64 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Table 1-1. Summary of Device Variations
Device
MC68HC908AP64 2,048 62,368
MC68HC908AP32 2,048 32,768
MC68HC908AP16 1,024 16,384
MC68HC908AP8 1,024 8,192
RAM Size
(bytes)
FLASH Memory Size
(bytes)
1.2 Features
Features of the MC68HC908AP64 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• Maximum internal bus frequency:
– 8-MHz at 5V or 3V operating voltage
• Clock input options:
– RC-oscillator
– 32-kHz crystal-oscillator with 32MHz internal PLL
• User program FLASH memory with security
– 62,368 bytes for MC68HC908AP64
– 32,768 bytes for MC68HC908AP32
– 16,384 bytes for MC68HC908AP16
– 8,192 bytes for MC68HC908AP8
•On-chip RAM
– 2,048 bytes for MC68HC908AP64 and MC68HC908AP32
– 1,024 bytes for MC68HC908AP16 and MC68HC908AP8
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture,
output compare, and PWM capability on each channel
(1)
feature
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 19
General Description
• Timebase module
• Serial communications interface module 1 (SCI)
• Serial communications interface module 2 (SCI) with infrared (IR) encoder/decoder
• Serial peripheral interface module (SPI)
• System management bus (SMBus), version 1.0/1.1 (multi-master IIC bus)
• 8-channel, 10-bit analog-to-digital converter (ADC)
•IRQ1
•IRQ2
external interrupt pin with integrated pullup
external interrupt pin with programmable pullup
• 8-bit keyboard wakeup port with integrated pullup
• 32 general-purpose input/output (I/O) pins:
– 31 shared-function I/O pins
– 8 LED drivers (sink)
–6 × 25mA open-drain I/O with pullup
• Low-power design (fully static with stop and wait modes)
• Master reset pin (with integrated pullup) and power-on reset
• System protection features
– Optional computer operating properly (COP) reset, driven by internal RC oscillator
– Low-voltage detection with optional reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
• 48-pin low quad flat pack (LQFP), 44-pin quad flat pack (QFP), and 42-pin shrink dual-in-line
package (SDIP)
• Specific features of the MC68HC908AP64 in 42-pin SDIP are:
– 30 general-purpose l/Os only
– External interrupt on IRQ1
only
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit Index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908AP64.
MC68HC908AP Family Data Sheet, Rev. 3
20 Freescale Semiconductor
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
CONTROL AND STATUS REGISTERS — 96 BYTES
USER FLASH — (SEE TABLE)
INTERNAL BUS
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
TIMEBASE
MODULE
MCU Block Diagram
PTA7/ADC7
PTA6/ADC6
PTA5/ADC5
PTA4/ADC4
DDRA
PORTA
PTA3/ADC3
PTA2/ADC2
PTA1/ADC1
PTA0/ADC0
‡
‡
‡
‡
‡
‡
‡
‡
USER RAM — (SEE TABLE)
MONITOR ROM — 959 BYTES
USER FLASH VECTOR SPACE — 48 BYTES
OSCILLATORS AND
CLOCK GENERATOR MODULE
INTERNAL OSCILLATOR
OSC1
OSC2
CGMXFC
* RST
* IRQ1
** IRQ2
RC OSCILLATOR
X-TAL OSCILLATOR
PHASE-LOCKED LOOP
SYSTEM INTEGRATION
MODULE
EXTERNAL INTERRUPT
MODULE
COMPUTER OPERATING
PROPERLY MODULE
POWER-ON RESET
MODULE
2-CHANNEL TIMER INTERFACE
MODULE 1
2-CHANNEL TIMER INTERFACE
MODULE 2
SERIAL COMMUNICATIONS
INTERFACE MODULE 1
MULTI-MASTER IIC (SMBUS)
INTERFACE MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE 2
(WITH INFRARED
MODULATOR/DEMODULATOR)
SERIAL PERIPHERAL
INTERFACE MODULE
KEYBOARD INTERRUPT
MODULE
LOW-VOLTAGE INHIBIT
MODULE
DDRB
DDRC
DDRD
PORTB
PORTC
PORTD
PTB7/T2CH1
PTB6/T2CH0
PTB5/T1CH1
PTB4/T1CH0
PTB3/RxD
PTB2/TxD
PTB1/SCL
PTB0/SDA
†
†
†
†
PTC7/SCRxD
PTC6/SCTxD
PTC5/SPSCK
PTC4/SS
PTC3/MOSI
PTC2/MISO
#
PTC1
PTC0/IRQ2 **
PTD7/KBI7 ***
PTD6/KBI6 ***
PTD5/KBI5 ***
PTD4/KBI4 ***
PTD3/KBI3 ***
PTD2/KBI2 ***
PTD1/KBI1 ***
PTD0/KBI0 ***
†
†
#
VDD
VDDA
VSS
VSSA
VREG
VREFH
VREFL
POWER
ADC REFERENCE
* Pin contains integrated pullup device.
** Pin contains configurable pullup device.
*** Pin contains integrated pullup device when configured as KBI.
†
Pin is open-drain when configured as output.
‡
LED direct sink pin.
#
Pin not bonded on 42-pin SDIP.
.
DEVICE
USER RAM
(bytes)
USER FLASH
(bytes)
MC68HC908AP64 2,048 62,368
MC68HC908AP32 2,048 32,768
MC68HC908AP16 1,024 16,384
MC68HC908AP8 1,024 8,192
Figure 1-1. MC68HC908AP64 Block Diagram
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 21
General Description
1.4 Pin Assignment
PTB6/T2CH0
PTD0/KBI0
PTB7/T2CH1
CGMXFC
48
47
46
45
44
1
43
PTD3/KBI3
42
41
PTD5/KBI5
PTD4/KBI4
40
39
PTD7/KBI7
PTD6/KBI6
37
38
36
VREFH
VSSA
VDDA
PTD2/KBI2
PTD1/KBI1
VREG
PTB5/T1CH1
VDD
OSC1
OSC2
VSS
PTB4/T1CH0
IRQ1
PTB3/RxD
RST
PTB2/TxD
12
2
3
4
5
6
7
8
9
10
11
13
PTB1/SCL
14
15
PTB0/SDA
PTC7/SCRxD
16
17
PTC6/SCTxD
PTC5/SPSCK
18
19
PTC4/SS
PTC3/MOSI
20
21
22
PTC1
PTC2/MISO
PTC0/IRQ2
35
34
33
32
31
30
29
28
27
26
23
25
24
NC
PTA7/ADC7
VREFL
NC
NC
PTA0/ADC0
NC
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
PTA6/ADC6
NC: No connection
Figure 1-2. 48-Pin LQFP Pin Assignments
MC68HC908AP Family Data Sheet, Rev. 3
22 Freescale Semiconductor
PTB6/T2CH0
Pin Assignment
VDDA
PTD2/KBI2
PTD1/KBI1
PTD0/KBI0
PTB7/T2CH1
CGMXFC
44
43
42
41
1
40
39
VSSA
PTD3/KBI3
38
37
PTD5/KBI5
PTD4/KBI4
36
35
PTD6/KBI6
34
33
PTD7/KBI7
VREG
PTB5/T1CH1
VDD
OSC1
OSC2
VSS
PTB4/T1CH0
IRQ1
PTB3/RxD
RST
2
3
4
5
6
7
8
9
10
11
13
12
PTB2/TxD
PTB1/SCL
14
15
PTB0/SDA
PTC7/SCRxD
16
PTC6/SCTxD
17
PTC5/SPSCK
18
PTC4/SS
20
19
PTC2/MISO
PTC3/MOSI
Figure 1-3. 44-Pin QFP Pin Assignments
21
PTC1
32
31
30
29
28
27
26
25
24
22
PTC0/IRQ2
VREFH
VREFL
PTA0/ADC0
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
PTA6/ADC6
PTA7/ADC7
23
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 23
General Description
PTD2/KBI2
PTD1/KBI1
PTD0/KBI0
PTB7/T2CH1
CGMXFC
PTB6/T2CH0
VREG
PTB5/T1CH1
VDD
OSC1
OSC2
VSS
PTB4/T1CH0
IRQ1
PTB3/RxD
RST
PTB2/TxD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDDA
VSSA
PTD3/KBI3
PTD4/KBI4
PTD5/KBI5
PTD6/KBI6
PTD7/KBI7
VREFH
VREFL
PTA0/ADC0
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
PTA6/ADC6
PTA7/ADC7
PTB1/SCL
PTB0/SDA
PTC7/SCRxD
PTC6/SCTxD
Pins not available on 42-pin package Internal connection
18
19
20
21 22
PTC0/IRQ2 Unconnected
PTC1 Unconnected
25
24
23
Figure 1-4. 42-Pin SDIP Pin Assignment
PTC2/MISO
PTC3/MOSI
PTC4/SS
PTC5/SPSCK
MC68HC908AP Family Data Sheet, Rev. 3
24 Freescale Semiconductor
1.5 Pin Functions
Description of the pin functions are provided in Table 1-2.
Table 1-2. Pin Functions
Pin Functions
PIN NAME PIN DESCRIPTION IN/OUT
V
DD
V
SS
V
DDA
V
SSA
V
REFH
V
REFL
V
REG
RST
IRQ1
Power supply.
Power supply ground.
Power supply for analog circuits.
Power supply ground for analog circuits.
ADC input reference high.
ADC input reference low.
Internal (2.5 V) regulator output.
Require external capacitors for decoupling.
Reset input, active low; with internal pullup and schmitt
trigger input.
External IRQ1 pin; with internal pullup and schmitt trigger
input.
Used for mode entry selection.
In
Out 0 V
In
Out
In
Out
Out
In
In
In
VOLTAGE
LEVEL
4.5 to 5.5
or
2.7 to 3.3
V
DD
V
SS
V
DDA
V
SSA
(1)
2.5V
V
DD
V
DD
to V
V
DD
TST
OSC1
OSC2
CGMXFC
PTA0/ADC0
:
PTA7/ADC7
Crystal or RC oscillator input.
Crystal OSC option: crystal oscillator output; inverted
OSC1.
RC OSC option: bus clock output.
Internal OSC option: bus clock output.
CGM external filter capacitor connection.
8-bit general purpose I/O port.
Pins as ADC inputs, ADC0–ADC7.
Each pin has high current sink for LED.
In
Out
Out
Out
V
V
V
V
REG
REG
REG
REG
In/Out Analog
In/Out
In
Out
V
V
V
DD
REFH
DD
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 25
General Description
Table 1-2. Pin Functions
PIN NAME PIN DESCRIPTION IN/OUT
8-bit general purpose I/O port; PTB0–PTB3 are open drain when
configured as output. PTB4–PTB7 have schmitt trigger inputs.
In/Out
PTB0 as SDA of MMIIC. In/Out
PTB0/SDA
PTB1 as SCL of MMIIC. In/Out
PTB1/SCL
PTB2/TxD
PTB2 as TxD of SCI; open drain output. Out
PTB3/RxD
PTB4/T1CH0
PTB3 as RxD of SCI. In
PTB5/T1CH1
PTB6/T2CH0
PTB7/T2CH1
PTB4 as T1CH0 of TIM1. In/Out
PTB5 as T1CH1 of TIM1. In/Out
PTB6 as T2CH0 of TIM2. In/Out
PTB7 as T2CH1 of TIM2. In/Out
8-bit general purpose I/O port; PTC6 and PTC7 are open drain
when configured as output.
In/Out
PTC0 is shared with IRQ2 and has schmitt trigger input. In
PTC0/IRQ2
PTC1
PTC2 as MISO of SPI. In
PTC2/MISO
PTC3/MOSI
PTC3 as MOSI of SPI. Out
PTC4/SS
PTC5/SPSCK
PTC4 as SS of SPI. In
PTC6/SCTxD
PTC7/SCRxD
PTC5 as SPSCK of SPI. In/Out
PTC6 as SCTxD of IRSCI; open drain output. Out
VOLTAGE
LEVEL
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
PTD0/KBI0
PTC7 as SCRxD of IRSCI. In
8-bit general purpose I/O port with schmitt trigger inputs. In/Out
:
PTD7/KBI7
Pins as keyboard interrupts (with pullup), KBI0–KBI7. In
1. See Chapter 22 Electrical Specifications for V
tolerance.
REG
V
DD
1.6 Power Supply Bypassing (VDD, VDDA, VSS, VSSA)
VDD and VSS are the power supply and ground pins, the MCU operates from a single power supply
together with an on chip voltage regulator.
Fast signal transitions on MCU pins place high. short-duration current demands on the power supply. To
prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the bypass capacitors as close to the MCU power pins as possible. Use
high-frequency-response ceramic capacitor for C
BYPASS
capacitors for use in applications that require the port pins to source high current level.
MC68HC908AP Family Data Sheet, Rev. 3
26 Freescale Semiconductor
, C
are optional bulk current bypass
BULK
V
DDA
and V
are the power supply and ground pins for the analog circuits of the MCU. These pins
SSA
should be decoupled as per the digital power supply pins.
MCU
Regulator Power Supply Configuration (VREG)
V
DD
C1(a)
0.1 µF
+
C2(a)
V
DD
V
SS
V
DDA
C1(b)
0.1 µF
+
C2(b)
V
DD
V
SSA
NOTE: Component values shown represent typical applications.
Figure 1-5. Power Supply Bypassing
1.7 Regulator Power Supply Configuration (VREG)
V
is the output from the on-chip regulator. All internal logics, except for the I/O pads, are powered by
REG
V
output. V
REG
the bypass capacitor as close to the V
requires an external ceramic bypass capacitor of 100 nF as Figure 1-6 shows. Place
REG
pin as possible.
REG
MCU
V
REG
C
VREGBYPASS
100 nF
Figure 1-6. Regulator Power Supply Bypassing
MC68HC908AP Family Data Sheet, Rev. 3
V
SS
Freescale Semiconductor 27
General Description
MC68HC908AP Family Data Sheet, Rev. 3
28 Freescale Semiconductor
Chapter 2 Memory
2.1 Introduction
The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes:
• 62,368 bytes of user FLASH — MC68HC908AP64
32,768 bytes of user FLASH — MC68HC908AP32
16,384 bytes of user FLASH — MC68HC908AP16
8,192 bytes of user FLASH — MC68HC908AP8
• 2,048 bytes of RAM — MC68HC908AP64 and MC68HC908AP32
1,024 bytes of RAM — MC68HC908AP16 and MC68HC908AP8
• 48 bytes of user-defined vectors
• 959 bytes of monitor ROM
2.2 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$005F. Additional I/O
registers have these addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
•$FE02; Reserved
• $FE03; SIM break flag control register, SBFCR
• $FE04; interrupt status register 1, INT1
• $FE05; interrupt status register 2, INT2
• $FE06; interrupt status register 3, INT3
•$FE07; Reserved
• $FE08; FLASH control register, FLCR
• $FE09; FLASH block protect register, FLBPR
•$FE0A; Reserved
•$FE0B; Reserved
• $FE0C; Break address register high, BRKH
• $FE0D; Break address register low, BRKL
• $FE0E; Break status and control register, BRKSCR
• $FE0F; LVI Status register, LVISR
• $FFCF; Mask option register, MOR (FLASH register)
• $FFFF; COP control register, COPCTL
2.3 Monitor ROM
The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that
contain the instructions for the monitor functions. (See Chapter 8 Monitor ROM (MON).)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 29
Memory
$0000
↓
$005F
$0060
↓
$085F
I/O Registers
96 Bytes
RAM
2,048 Bytes
(MC68HC908AP64)
$0860
FLASH Memory
↓
62,368 Bytes
(MC68HC908AP64)
$FBFF
$FC00
↓
$FDFF
Monitor ROM 2
512 Bytes
$FE00 SIM Break Status Register
$FE01 SIM Reset Status Register
$FE02 Reserved
$FE03 SIM Break Flag Control Register
$FE04 Interrupt Status Register 1
$FE05 Interrupt Status Register 2
$FE06 Interrupt Status Register 3
$FE07 Reserved
$FE08 FLASH Control Register
$FE09 FLASH Block Protect Register
$FE0A Reserved
$FE0B Reserved
$FE0C Break Address Register High
$FE0D Break Address Register Low
$FE0E Break Status and Control Register
$FE0F LVI Status Register
$FE10
↓
$FFCE
Monitor ROM 1
447 Bytes
$FFCF Mask Option Register
$FFD0
↓
$FFFF
FLASH Vectors
48 Bytes
MC68HC908AP32 MC68HC908AP16 MC68HC908AP8
RAM
2,048 Bytes
FLASH Memory
32,768 Bytes
$0060
↓
$085F
$0860
↓
RAM
1,024 Bytes
Unimplemented
1,024 Bytes
FLASH Memory
16,384 Bytes
$0060
$045F
$0860
↓
$485F
$4860
RAM
1,024 Bytes
Unimplemented
1,024 Bytes
FLASH Memory
8,192 Bytes
$885F
Unimplemented
29,600 Bytes
$8860
↓
$FBFF
Unimplemented
45,984 Bytes
↓
$FBFF
Unimplemented
54,176 Bytes
Figure 2-1. Memory Map
$0060
$045F
$0860
$285F
$2860
↓
$FBFF
MC68HC908AP Family Data Sheet, Rev. 3
30 Freescale Semiconductor
Monitor ROM
Addr.Register Name Bit 7654321Bit 0
$0000
$0001
$0002 Port C Data Register (PTC)
$0003 Port D Data Register (PTD)
$0004
$0005
$0006
$0007
$0008
$0009 Unimplemented
$000A Unimplemented
$000B Unimplemented
$000C
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Data Direction Register C
(DDRC)
Data Direction Register D
(DDRD)
Unimplemented
Port-A LED Control
Register
(LEDA)
U = Unaffected X = Indeterminate
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:00000000
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDA0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 31
Memory
Addr.Register Name Bit 7654321Bit 0
Read:
$000D Unimplemented
$000E Unimplemented
$000F Unimplemented
$0010
$0011
$0012
$0013
$0014
$0015
$0016 SCI Status Register 1 (SCS1)
$0017 SCI Status Register 2 (SCS2)
$0018
$0019
SPI Control Register
(SPCR)
SPI Status and Control
Register
(SPSCR)
SPI Data Register
(SPDR)
SCI Control Register 1
(SCC1)
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Data Register
(SCDR)
SCI Baud Rate Register
(SCBR)
U = Unaffected X = Indeterminate
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:00101000
Read: SPRF
Write:
Reset:00001000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: R8
Write:
Reset:UU000000
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read:000000BKFRPF
Write:
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Read: 0 0
Write:
Reset:00000000
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
ERRIE
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
T8 DMARE DMATE ORIE NEIE FEIE PEIE
OVRF MODF SPTE
SCP1 SCP0 R SCR2 SCR1 SCR0
= Unimplemented R = Reserved
MODFEN SPR1 SPR0
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
32 Freescale Semiconductor
Monitor ROM
Addr.Register Name Bit 7654321Bit 0
Keyboard Status and Control
$001A
$001B
IRQ2 Status and Control Reg-
$001C
$001D
Configuration Register 2
Register
(KBSCR)
Keyboard Interrupt
Enable Register
(KBIER)
(INTSCR2)
(CONFIG2)
Read:0000KEYF0
Write:
ACK
IMASK MODE
Reset:00000000
Read:
Write:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Reset:00000000
ister
Read: 0
Write:
PUC0ENB
00IRQ2F0
ACK2
IMASK2 MODE2
Reset:00000000
00
SCIBDSRC
†
Read:
Write:
STOP_
ICLKDIS
STOP_
RCLKEN
STOP_
XCLKEN
OSCCLK1 OSCCLK0
Reset:00000000
† One-time writable register after each reset.
IRQ1 Status and Control Reg-
$001E
$001F
Configuration Register 1
(INTSCR1)
(CONFIG1)
Read:0000IRQ1F0
ister
Write:
ACK1
IMASK1 MODE1
Reset:00000000
†
Read:
Write:
COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD
Reset:00000000
† One-time writable register after each reset.
$0020
$0021
$0022
Timer 1 Counter Modulo Reg-
$0023
Timer 1 Counter Modulo
$0024
Timer 1 Channel 0 Status and
$0025
Control Register (T1SC0)
Timer 1 Status and
Control Register
(T1SC)
Timer 1 Counter
Register High
(T1CNTH)
Timer 1 Counter
Register Low
(T1CNTL)
ister High
(T1MODH)
Register Low
(T1MODL)
Read: TOF
Write: 0 TRST
TOIE TSTOP
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read:Bit 7654321Bit 0
Write:
Reset:00000000
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
Reset:11111111
Read:
Write:
Bit 7654321Bit 0
Reset:11111111
Read: CH0F
Write: 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
00
PS2 PS1 PS0
Reset:00000000
U = Unaffected X = Indeterminate
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 33
Memory
Addr.Register Name Bit 7654321Bit 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read:Bit 7654321Bit 0
Write:
Reset:00000000
Read:
Write:
Reset:11111111
Read:
Write:
Reset:11111111
Read: CH0F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TOIE TSTOP
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
0
MS1A ELS1B ELS1A TOV1 CH1MAX
00
= Unimplemented R = Reserved
PS2 PS1 PS0
$0026
$0027
Timer 1 Channel 1 Status and
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
Control Register (T1SC1)
Timer 2 Counter Modulo Reg-
Timer 2 Counter Modulo
Timer 2 Channel 0 Status and
Control Register (T2SC0)
Timer 1 Channel 0
Register High
(T1CH0H)
Timer 1 Channel 0
Register Low
(T1CH0L)
Timer 1 Channel 1
Register High
(T1CH1H)
Timer 1 Channel 1
Register Low
(T1CH1L)
Timer 2 Status and
Control Register
(T2SC)
Timer 2 Counter
Register High
(T2CNTH)
Timer 2 Counter
Register Low
(T2CNTL)
ister High
(T2MODH)
Register Low
(T2MODL)
Timer 2 Channel 0
Register High
(T2CH0H)
Timer 2 Channel 0
Register Low
(T2CH0L)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
34 Freescale Semiconductor
Monitor ROM
Addr.Register Name Bit 7654321Bit 0
Timer 2 Channel 1 Status and
$0033
$0034
$0035
$0036 PLL Control Register (PCTL)
$0037
$0038
$0039
$003A
$003B
$003C Unimplemented
$003D Unimplemented
$003E Unimplemented
$003F Unimplemented
Control Register (T2SC1)
Timer 2 Channel 1
Register High
(T2CH1H)
Timer 2 Channel 1
Register Low
(T2CH1L)
PLL Bandwidth Control Reg-
ister
(PBWC)
PLL Multiplier Select
Register High
(PMSH)
PLL Multiplier Select
Register Low
(PMSL)
PLL VCO Range Select
Register
(PMRS)
PLL Reference Divider
Select Register
(PMDS)
U = Unaffected X = Indeterminate
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset:00100000
Read:
Write:
Reset:00000000
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read:0000
Write:
Reset:00000001
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
PLLIE
AUTO
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
CH1IE
PLLF
LOCK
0
PLLON BCS PRE1 PRE0 VPR1 VPR0
ACQ
MS1A ELS1B ELS1A TOV1 CH1MAX
0000
MUL11 MUL10 MUL9 MUL8
RDS3 RDS2 RDS1 RDS0
= Unimplemented R = Reserved
R
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 35
Memory
Addr.Register Name Bit 7654321Bit 0
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
$004C
IRSCI Control Register 1
(IRSCC1)
IRSCI Control Register 2
(IRSCC2)
IRSCI Control Register 3
(IRSCC3)
IRSCI Status Register 1
(IRSCS1)
IRSCI Status Register 2
(IRSCS2)
IRSCI Data Register
(IRSCDR)
IRSCI Baud Rate Register
(IRSCBR)
IRSCI Infrared Control
Register
(IRSCIRCR)
MMIIC Address Register
(MMADR)
MMIIC Control Register 1
(MMCR1)
MMIIC Control Register 2
(MMCR2)
MMIIC Status Register
(MMSR)
MMIIC Data Transmit
Register
(MMDTR)
U = Unaffected X = Indeterminate
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: R8
Write:
Reset:UU000000
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read:
Write:
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:10100000
Read:
Write: MMCLRBB
Reset:00000000
Read: MMALIF MMNAKIF MMBB
Write: 0 0
Reset:00 0 0000Unaffected
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF
Write: 0 0
Reset:00 0 01010
Read:
Write:
Reset:00000000
LOOPS ENSCI
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
T8 DMARE DMATE ORIE NEIE FEIE PEIE
CKS
R
MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD
MMEN MMIEN
MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0
0
0 0 0
0
SCP1 SCP0 R SCR2 SCR1 SCR0
0 0
M WAKE ILTY PEN PTY
BKF RPF
R TNP1 TNP0 IREN
MMTXAK REPSEN
MMAST MMRW
= Unimplemented R = Reserved
MMCRCBY
TE
0 0
0
MMCRCEF
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
36 Freescale Semiconductor
Monitor ROM
Addr.Register Name Bit 7654321Bit 0
MMIIC Data Receive Register
$004D
MMIIC CRC Data Register
$004E
MMIIC Frequency Divider
$004F
$0050 Reserved
Timebase Control Register
$0051
$0052 Unimplemented
$0053 Unimplemented
$0054 Unimplemented
$0055 Unimplemented
$0056 Unimplemented
ADC Status and Control
$0057
$0058
$0059
ADC Clock Control Register
ADC Data Register High 0
(MMDRR)
(MMCRDR)
Register
(MMFDR)
(TBCR)
Register
(ADSCR)
(ADICLK)
(ADRH0)
U = Unaffected X = Indeterminate
Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0
Write:
Reset:00000000
Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
Write:
Reset:00000000
Read: 0 0 0 0 0
Write:
Reset:00000100
Read:
Write:
Reset:
Read: TBIF
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read: COCO
Write:
Reset:00011111
Read:
Write:
Reset:00000000
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
RRRRRRRR
TBR2 TBR1 TBR0
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
= Unimplemented R = Reserved
0
TACK
MMBR2 MMBR1 MMBR0
TBIE TBON R
0 0
R
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 37
Memory
Addr.Register Name Bit 7654321Bit 0
$005A
$005B
$005C ADC Data Register Low 2
$005D
$005E
$005F Unimplemented
ADC Data Register Low 0
(ADRL0)
ADC Data Register Low 1
(ADRL1)
(ADRL2)
ADC Data Register Low 3
(ADRL3)
ADC Auto-scan Control
Register
(ADASCR)
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
Read:AD9AD8AD7AD6AD5AD4AD3AD2
Write:RRRRRRRR
Reset:00000000
Read:AD9AD8AD7AD6AD5AD4AD3AD2
Write:RRRRRRRR
Reset:00000000
Read:AD9AD8AD7AD6AD5AD4AD3AD2
Write:RRRRRRRR
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:
AUTO1 AUTO0 ASCA N
$FE00
Note: Writing a logic 0 clears SBSW.
$FE01
$FE02 Reserved
$FE03
$FE04
$FE05
SIM Break Status Register
(SBSR)
SIM Reset Status Register
(SRSR)
SIM Break Flag Control Reg-
(SBFCR)
Interrupt Status Register 1
(INT1)
Interrupt Status Register 2
(INT2)
U = Unaffected X = Indeterminate = Unimplemented R = Reserved
Read:
Write: Note
Reset: 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
Reset:10000000
Read:
Write:
Reset:
Read:
ister
Write:
Reset: 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
RRRRRR
RRRRRRRR
BCFERRRRRRR
SBSW
R
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
38 Freescale Semiconductor
Monitor ROM
Addr.Register Name Bit 7654321Bit 0
Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15
$FE06
Interrupt Status Register 3
(INT3)
Write:RRRRRRRR
Reset:00000000
$FE07 Reserved
Read:
Write:
RRRRRRRR
Reset:
$FE08
FLASH Control Register
(FLCR)
Read:0000
Write:
HVEN MASS ERASE PGM
Reset:00000000
FLASH Block Protect
$FE09
Register
(FLBPR)
$FE0A Reserved
Read:
Write:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Reset:00000000
Read:
Write:
RRRRRRRR
Reset:
$FE0B Reserved
Read:
Write:
RRRRRRRR
Reset:
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
Reset:00000000
Read:
Write:
Bit 7654321Bit 0
Reset:00000000
Reset:
Read:
BRKE BRKA
000000
Write:00000000
$FE0C
$FE0D
$FE0E
Break Address
Register High
(BRKH)
Break Address
Register Low
(BRKL)
Break Status and Control
Register
(BRKSCR)
Reset:LVIOUT 0000000
$FE0F LVI Status Register (LVISR)
Read:
Write:00000000
Read:
$FFCF
Mask Option Register
(MOR)
#
OSCSEL1OSCSEL0RRRRRR
Write:
Erased:11111111
Reset:UUUUUUUU
Read: Low byte of reset vector
$FFFF
COP Control Register
(COPCTL)
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
#
MOR is a non-volatile FLASH register; write by programming.
U = Unaffected X = Indeterminate
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 39
Memory
Table 2-1. Vector Addresses
Priority INT Flag Address Vector
Lowest
—
$FFD0 Reserved
$FFD1 Reserved
$FFD2 TBM Vector (High)
IF21
$FFD3 TBM Vector (Low)
$FFD4 SCI2 (IRSCI) Transmit Vector (High)
IF20
$FFD5 SCI2 (IRSCI) Transmit Vector (Low)
$FFD6 SCI2 (IRSCI) Receive Vector (High)
IF19
$FFD7 SCI2 (IRSCI) Receive Vector (Low)
$FFD8 SCI2 (IRSCI) Error Vector (High)
IF18
$FFD9 SCI2 (IRSCI) Error Vector (Low)
$FFDA SPI Transmit Vector (High)
IF17
$FFDB SPI Transmit Vector (Low)
$FFDC SPI Receive Vector (High)
IF16
$FFDD SPI Receive Vector (Low)
$FFDE ADC Conversion Complete Vector (High)
IF15
$FFDF ADC Conversion Complete Vector (Low)
IF14
IF13
IF12
IF11
IF10
IF9
$FFE0 Keyboard Vector (High)
$FFE1 Keyboard Vector (Low)
$FFE2 SCI Transmit Vector (High)
$FFE3 SCI Transmit Vector (Low)
$FFE4 SCI Receive Vector (High)
$FFE5 SCI Receive Vector (Low)
$FFE6 SCI Error Vector (High)
$FFE7 SCI Error Vector (Low)
$FFE8 MMIIC Interrupt Vector (High)
$FFE9 MMIIC Interrupt Vector (Low)
$FFEA TIM2 Overflow Vector (High)
$FFEB TIM2 Overflow Vector (Low)
MC68HC908AP Family Data Sheet, Rev. 3
40 Freescale Semiconductor
Table 2-1. Vector Addresses (Continued)
Priority INT Flag Address Vector
Random-Access Memory (RAM)
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
$FFEC TIM2 Channel 1 Vector (High)
$FFED TIM2 Channel 1 Vector (Low)
$FFEE TIM2 Channel 0 Vector (High)
$FFEF TIM2 Channel 0 Vector (Low)
$FFF0 TIM1 Overflow Vector (High)
$FFF1 TIM1 Overflow Vector (Low)
$FFF2 TIM1 Channel 1 Vector (High)
$FFF3 TIM1 Channel 1 Vector (Low)
$FFF4 TIM1 Channel 0 Vector (High)
$FFF5 TIM1 Channel 0 Vector (Low)
$FFF6 PLL Vector (High)
$FFF7 PLL Vector (Low)
$FFF8 IRQ2
$FFF9 IRQ2
$FFFA IRQ1
$FFFB IRQ1
Vector (High)
Vector (Low)
Vector (High)
Vector (Low)
—
—
Highest $FFFF Reset Vector (Low)
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
2.4 Random-Access Memory (RAM)
The following table shows the RAM size and address range:
Device RAM Size (Bytes) Memory Address Range
MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
MC68HC908AP8
The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere
in the 64k-byte memory space.
2,048 $0060–$085F
1,024 $0060–$045F
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 41
Memory
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero
RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.5 FLASH Memory
This sub-section describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply. The program and erase operations are enabled
through the use of an internal charge pump. The following table shows the FLASH memory size and
address range:
Device FLASH Size (Bytes) Memory Address Range
MC68HC908AP64 62,368 $0860–$FBFF
MC68HC908AP32 32,768 $0860–$885F
MC68HC908AP16 16,384 $0860–$485F
MC68HC908AP8 8,192 $0860–$285F
2.5.1 Functional Description
The FLASH memory consists of an array for user memory plus a block of 48 bytes for user interrupt
vectors and one byte for the mask option register. An erased bit reads as logic 1 and a programmed bit
reads as a logic 0. The FLASH memory page size is defined as 512 bytes, and is the minimum size that
can be erased in a page erase operation. Program and erase operations are facilitated through control
bits in FLASH control register (FLCR). The address ranges for the FLASH memory are:
• $0860–$FBFF; user memory, 62,368 / 32,768 / 16,384 / 8,192 bytes
• $FFD0–$FFFF; user interrupt vectors, 48 bytes
• $FFCF; mask option register
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.
MC68HC908AP Family Data Sheet, Rev. 3
42 Freescale Semiconductor
(1)
FLASH Memory
2.5.2 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operation.
Address: $FE08
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or page erase operation when the
ERASE bit is set.
1 = Mass erase operation selected
0 = Page erase operation selected
HVEN MASS ERASE PGM
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
2.5.3 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 512 consecutive bytes
starting from addresses $X000, $X200, $X400, $X600, $X800, $XA00, $XC00, or $XE00. The 48-byte
user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass
erase is required to erase this page.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Write any data to any FLASH location within the page address range desired.
3. Wait for a time, t
4. Set the HVEN bit.
5. Wait for a time t
nvs
erase
(5 µs).
(20 ms).
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 43
Memory
6. Clear the ERASE bit.
7. Wait for a time, t
nvh
(5 µs).
8. Clear the HVEN bit.
9. After time, t
(1 µs), the memory can be accessed in read mode again.
rcv
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
2.5.4 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Write any data to any FLASH location within the FLASH memory address range.
3. Wait for a time, t
4. Set the HVEN bit.
5. Wait for a time t
6. Clear the ERASE bit.
7. Wait for a time, t
8. Clear the HVEN bit.
9. After time, t
rcv
Due to the relatively long mass erase time, user should take care in the
code to prevent a COP reset from happening while the HVEN bit is set.
(5 µs).
nvs
(200 ms). (See NOTE below.)
me
(100 µs).
nvh1
(1 µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
2.5.5 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80 or $XXC0. Use the following procedure to program a row
of FLASH memory. (Figure 2-4 shows a flowchart of the programming algorithm.)
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Write any data to any FLASH location within the address range of the row to be programmed.
3. Wait for a time, t
4. Set the HVEN bit.
5. Wait for a time, t
6. Write data to the FLASH location to be programmed.
7. Wait for time, t
8. Repeat steps 6 and 7 until all bytes within the row are programmed.
9. Clear the PGM bit.
(5 µs).
nvs
(10 µs).
pgs
(20 µs to 40 µs).
prog
MC68HC908AP Family Data Sheet, Rev. 3
44 Freescale Semiconductor
FLASH Memory
10. Wait for time, t
nvh
(5 µs).
11. Clear the HVEN bit.
12. After time, t
(1 µs), the memory can be accessed in read mode again.
rcv
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
The time between each FLASH address change (step 6 to step 6), or the
time between the last FLASH addressed programmed to clearing the PGM
bit (step 6 to step 9), must not exceed the maximum programming time,
t
max.
prog
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
2.5.6 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect pages of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program
operations.
NOTE
The mask option register ($FFCF) and the 48 bytes of user interrupt vectors
($FFD0–$FFFF) are always protected, regardless of the value in the
FLASH block protect register. A mass erase is required to erase these
locations.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 45
Memory
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
Write any data to any FLASH address
Set PGM bit
within the row address range desired
3
4
5
6
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address
to be programmed
7
Wait for a time, t
nvs
pgs
prog
Completed
programming
this row?
NOTE:
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
must not exceed the maximum programming
time, t
PROG
max.
This row program algorithm assumes the row/s
to be programmed are initially erased.
Figure 2-4. FLASH Programming Flowchart
Y
N
9
10
11
12
Clear PGM bit
Wait for a time, t
Clear HVEN bit
Wait for a time, t
nvh
rcv
End of Programming
MC68HC908AP Family Data Sheet, Rev. 3
46 Freescale Semiconductor
FLASH Memory
2.5.7 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register. The value in this register
determines the starting address of the protected range within the FLASH memory.
Address: $FE09
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Bits
BPR[7:1] represent bits [15:9] of a 16-bit memory address. Bits [8:0] are logic 0’s.
Start address of FLASH block protect 000000000
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be X000, X200, X400, X0600, X800, XA00, XC00,
or XE00 (at page boundaries — 512 bytes) within the FLASH memory.
Examples of protect start address:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-5. FLASH Block Protect Register (FLBPR)
16-bit memory address
BPR[7:1]
Table 2-2 FLASH Block Protect Range
BPR[7:0] Protected Range
$00 to $09 The entire FLASH memory is protected.
$0A or $0B
(0000 101x)
$0C or $0D
(0000 110x)
and so on...
$FA or $FB
(1111 1101x)
$FC or $FD or $FE $FFCF to $FFFF
$FF
1. Except for the mask option register ($FFCF) and the 48-byte user vectors
($FFD0–$FFFF). These FLASH locations are always protected.
The entire FLASH memory is NOT protected.
$0A00 to $FFFF
$0C00 to $FFFF
$FA00 to $FFFF
(1)
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 47
Memory
MC68HC908AP Family Data Sheet, Rev. 3
48 Freescale Semiconductor
Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option
register, MOR.
The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (2
• Low-voltage inhibit (LVI) on V
•LVI on V
REG
• LVI module reset
• LVI module in stop mode
•STOP instruction
• Stop mode recovery time (32 ICLK or 4096 ICLK cycles)
• Oscillator (internal, RC, and crystal) during stop mode
• Serial communications interface clock source (CGMXCLK or f
18
– 24 or 213 – 24 ICLK cycles)
DD
BUS
)
The mask option register selects one of the following oscillator options:
• Internal oscillator
• RC oscillator
• Crystal oscillator
Addr.Register Name Bit 7654321Bit 0
Configuration Register 2
$001D
$001F
$FFCF
† One-time writable register after each reset.
#
MOR is a non-volatile FLASH register; write by programming.
Configuration Register 1
Mask-Option-Register
(CONFIG2)
(CONFIG1)
(MOR)
Read:
†
Write:
Reset:00000000
Read:
Write:
†
Reset:00000000
Read:
#
Write:
Erased:11111111
STOP_
ICLKDIS
COPRS LVISTOP LVIRSTD LVIPWRD
OSCSEL1OSCSEL0RRRRRR
STOP_
RCLKEN
= Unimplemented R = Reserved
STOP_
XCLKEN
OSCCLK1 OSCCLK0
LVIREGD SSREC STOP COPD
00
SCIBDSRC
Figure 3-1. CONFIG and MOR Registers Summary
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 49
Configuration & Mask Option Registers (CONFIG & MOR)
3.2 Functional Description
The configuration registers and the mask option register are used in the initialization of various options.
These two types of registers are configured differently:
• Configuration registers — Write-once registers after reset
• Mask option register — FLASH register (write by programming)
The configuration registers can be written once after each reset. All of the configuration register bits are
cleared during reset. Since the various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration registers are located at $001D and
$001F. The configuration registers may be read at anytime.
NOTE
The CONFIG registers are not in the FLASH memory but are special
registers containing one-time writable latches after each reset. Upon a
reset, the CONFIG registers default to predetermined settings as shown in
Figure 3-2 and Figure 3-3.
The mask option register (MOR) is used for selecting one of the three clock options for the MCU. The
MOR is a byte located in FLASH memory, and is written to by a FLASH programming routine.
3.3 Configuration Register 1 (CONFIG1)
Address: $001F
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD
Figure 3-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP time out period. Reset clears COPRS. (See Chapter 19 Computer Operating
Properly (COP).)
13
1 = COP time out period = 2
0 = COP time out period = 2
– 24 ICLK cycles
18
– 24 ICLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD or LVIREGD bit is clear, setting the LVISTOP bit enables the LVI to operate
during stop mode. Reset clears LVISTOP. (See Chapter 20 Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE
If LVISTOP=0, set LVIRSTD =1 before entering stop mode.
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See Chapter 20 Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HC908AP Family Data Sheet, Rev. 3
50 Freescale Semiconductor
Configuration Register 1 (CONFIG1)
LVIPWRD — V
LVIPWRD disables the V
1 = V
DD
0 = V
DD
LVIREGD — V
LVIREGD disables the V
1 = V
REG
0 = V
REG
LVI Circuit Disable Bit
DD
LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).)
DD
LVI circuit disabled
LVI circuit enabled
LVI Circuit Disable Bit
REG
LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).)
REG
LVI circuit disabled
LVI circuit enabled
NOTE
If LVIPWRD=1 and LVIREGD=1, set LVIRSTD =1 before entering stop
mode.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle
delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
When the LVI is disabled in stop mode (LVISTOP=0), the system
stabilization time for long stop recovery (4096 ICLK cycles) gives a delay
longer than the LVI’s turn-on time. There is no period where the MCU is not
protected from a low power condition. However, when using the short stop
recovery configuration option, the 32 ICLK delay is less than the LVI’s
turn-on time and there exists a period in start-up where the LVI is not
protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 19 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 51
Configuration & Mask Option Registers (CONFIG & MOR)
3.4 Configuration Register 2 (CONFIG2)
Address: $001D
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
STOP_
ICLKDIS
STOP_
RCLKEN
STOP_
XCLKEN
OSCCLK1 OSCCLK0
Figure 3-3. Configuration Register 2 (CONFIG2)
STOP_ICLKDIS — Internal Oscillator Stop Mode Disable
STOP_ICLKDIS disables the internal oscillator during stop mode. Setting the STOP_ICLKDIS bit
disables the oscillator during stop mode. (See Chapter 5 Oscillator (OSC).)
Reset clears this bit.
1 = Internal oscillator disabled during stop mode
0 = Internal oscillator enabled to operate during stop mode
STOP_RCLKEN — RC Oscillator Stop Mode Enable Bit
STOP_RCLKEN enables the RC oscillator to continue operating during stop mode. Setting the
STOP_RCLKEN bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wake up while in stop mode. (See
Chapter 5 Oscillator (OSC).)
Reset clears this bit.
1 = RC oscillator enabled to operate during stop mode
0 = RC oscillator disabled during stop mode
00
SCIBD-
SRC
STOP_XCLKEN — X-tal Oscillator Stop Mode Enable Bit
STOP_XCLKEN enables the crystal (x-tal) oscillator to continue operating during stop mode. Setting
the STOP_XCLKEN bit allows the x-tal oscillator to operate continuously even during stop mode. This
is useful for driving the timebase module to allow it to generate periodic wake up while in stop mode.
(See Chapter 5 Oscillator (OSC).) Reset clears this bit.
1 = X-tal oscillator enabled to operate during stop mode
0 = X-tal oscillator disabled during stop mode
OSCCLK1, OSCCLK0 — Oscillator Output Control Bits
OSCCLK1 and OSCCLK0 select which oscillator output to be driven out as OSCCLK to the timebase
module (TBM). Reset clears these two bits.
OSCCLK1 OSCCLK0 Timebase Clock Source
0 0 Internal oscillator (ICLK)
0 1 RC oscillator (RCCLK)
1 0 X-tal oscillator (XTAL)
1 1 Not used
MC68HC908AP Family Data Sheet, Rev. 3
52 Freescale Semiconductor
Mask Option Register (MOR)
SCIBDSRC — SCI Baud Rate Clock Source
SCIBDSRC selects the clock source used for the standard SCI module (non-infrared SCI). The setting
of this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock, f
, is used as clock source for SCI
BUS
0 = Oscillator clock, CGMXCLK, is used as clock source for SCI
3.5 Mask Option Register (MOR)
The mask option register (MOR) is used for selecting one of the three clock options for the MCU. The
MOR is a byte located in FLASH memory, and is written to by a FLASH programming routine.
Address: $FFCF
Bit 7654321Bit 0
Read:
OSCSEL1OSCSEL0RRRRRR
Write:
Reset: Unaffected by reset
Erased:11111111
R=Reserved
Figure 3-4. Mask Option Register (MOR)
OSCSEL1, OSCSEL0 — Oscillator Selection Bits
OSCSEL1 and OSCSEL0 select which oscillator is used for the MCU CGMXCLK clock. The erase
state of these two bits is logic 1. These bits are unaffected by reset. (See Table 3-1).
Bits 5–0 — Should be left as 1’s
Table 3-1. CGMXCLK Clock Selection
OSCSEL1 OSCSEL0 CGMXCLK OSC2 pin Comments
00——
01ICLK
1 0 RCCLK
11X-TAL
f
BUS
f
BUS
Inverting
output of XTAL
NOTE
The internal oscillator is a free running oscillator and is available after each
POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS
bit in CONFIG2.
Not used
Internal oscillator generates the CGMXCLK.
RC oscillator generates the CGMXCLK.
Internal oscillator is available after each POR
or reset.
X-tal oscillator generates the CGMXCLK.
Internal oscillator is available after each POR
or reset.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 53
Configuration & Mask Option Registers (CONFIG & MOR)
MC68HC908AP Family Data Sheet, Rev. 3
54 Freescale Semiconductor
Chapter 4 Central Processor Unit (CPU)
4.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes, and architecture.
4.2 Features
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-Bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 55
Central Processor Unit (CPU)
4.3 CPU Registers
Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.
7
15
H X
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 4-1. CPU Registers
4.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 4-2. Accumulator (A)
4.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
MC68HC908AP Family Data Sheet, Rev. 3
56 Freescale Semiconductor
CPU Registers
Bit
1413121110987654321Bit 0
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 4-3. Index Register (H:X)
4.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
1413121110987654321Bit 0
15
Read:
Write:
Reset:0000000011111111
Figure 4-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address
(page 0) space. For correct operation, the stack pointer must point only to
RAM locations.
4.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 57
Central Processor Unit (CPU)
Bit
1413121110987654321Bit 0
15
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Figure 4-5. Program Counter (PC)
4.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe
the functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X11X1XXX
V11H I NZC
X = Indeterminate
Figure 4-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
MC68HC908AP Family Data Sheet, Rev. 3
58 Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
4.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a
description of the instructions and addressing modes and more detail about the architecture of the CPU.
4.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
4.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 59
Central Processor Unit (CPU)
4.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary
Table 4-1 provides a summary of the M68HC08 instruction set.
4.8 Opcode Map
The opcode map is provided in Table 4-2.
Table 4-1. Instruction Set Summary
Source
Form
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AIS #
opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2
Add with Carry A ← (A) + (M) + (C) RR– RRR
Add without Carry A ← (A) + (M) RR – RRR
Operation Description
CCR
VH I NZC
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
Opcode
A9
B9
C9
D9
E9
F9
9EE9
9ED9
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
Operand
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
Effect on
Cycles
MC68HC908AP Family Data Sheet, Rev. 3
60 Freescale Semiconductor
Table 4-1. Instruction Set Summary
Opcode Map
Source
Form
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
Logical AND A ← (A) & (M) 0 – – RR–
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right R ––RRR
Operation Description
C
b7
b7
0
b0
C
b0
CCR
VH I NZC
R ––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
Address
Mode
A4
B4
C4
D4
E4
F4
9EE4
9ED4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
Opcode
Operand
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
Effect on
Cycles
DIR (b0)
DIR (b1)
DIR (b2)
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC
BHS rel
BIH rel Branch if IRQ
BIL rel Branch if IRQ
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Branch if Higher or Same
(Same as BCC)
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3
PC ← (PC) + 2 +rel ? (Z) | (N ⊕ V)=0––––––REL 92 rr 3
← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
dd
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 61
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Source
Form
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
BLE opr
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 1 ––––––REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
Bit Test (A) & (M) 0 – – RR–
Branch if Less Than or Equal To
(Signed Operands)
Operation Description
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V)=1––––––REL 93 rr 3
rel ? (I) = 1 ––––––REL 2D rr 3
CCR
VH I NZC
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
A5
B5
C5
D5
E5
F5
9EE5
9ED5
Opcode
Operand
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
Effect on
Cycles
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
5
dd rr
DIR (b0)
DIR (b1)
DIR (b2)
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – – R
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 – – – – – R
BSET n,opr Set Bit n in M Mn ← 1 ––––––
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
MC68HC908AP Family Data Sheet, Rev. 3
62 Freescale Semiconductor
Table 4-1. Instruction Set Summary
Opcode Map
Source
Form
BSR rel Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare and Branch if Equal
Clear
Compare A with M (A) – (M) R ––RRR
Operation Description
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
M ← $00
A ← $00
X ←
$00
H ← $00
M ← $00
M ← $00
M ← $00
CCR
Mode
31
41
51
61
71
9E61
3F
4F
5F
8C
6F
7F
9E6F
A1
B1
C1
D1
E1
F1
9EE1
9ED1
Opcode
Operand
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
5
4
4
5
4
6
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
VH I NZC
––––––REL AD rr 4
––––––
0––01–
Address
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Effect on
Cycles
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA Decimal Adjust A (A)
Complement (One’s Complement)
Compare H:X with M (H:X) – (M:M + 1) R ––RRR
Compare X with M (X) – (M) R ––RRR
M ← (M
A ← (A
X ← (X
M ← (M
M ← (M
M ← (M
) = $FF – (M)
) = $FF – (M)
) = $FF – (M)
) = $FF – (M)
) = $FF – (M)
) = $FF – (M)
10
dd
DIR
INH
0––RR1
U–– RRRINH 72 2
INH
IX1
IX
SP1
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
33
43
53
ff
63
73
9E63
ff
6575ii ii+1dd3
ii
A3
dd
B3
hh ll
C3
ee ff
D3
ff
E3
F3
ff
9EE3
ee ff
9ED3
4
1
1
4
3
5
4
2
3
4
4
3
2
4
5
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 63
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Source
Form
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
DIV Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Decrement and Branch if Not Zero
Decrement
Exclusive OR M with A A ← (A ⊕ M) 0 – – RR–
Operation Description
A ← (A)–1 or M ← (M) –1 or X ← (X)–1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) – 1
A ←
(A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
Effect on
CCR
Mode
3B
4B
5B
6B
7B
9E6B
3A
4A
5A
6A
7A
9E6A
A8
B8
C8
D8
E8
F8
9EE8
9ED8
Opcode
Operand
dd rr
rr
rr
ff rr
rr
ff rr
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
VH I NZC
––––––
R ––RR–
––––RRINH 52 7
Address
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Cycles
5
3
3
5
4
6
4
1
1
4
3
5
2
3
4
4
3
2
4
5
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
M ← (M) + 1
A ← (A) + 1
Increment
Jump PC ← Jump Address ––––––
PC ← (PC) + n (n = 1, 2, or 3)
Jump to Subroutine
PC ← Unconditional Address
Load A from M A ← (M) 0 – – RR –
Load H:X from M H:X ← (M:M + 1) 0 – – RR–
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
R ––RR–
––––––
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
dd
3C
4C
5C
ff
6C
7C
9E6C
ff
dd
BC
hh ll
CC
ee ff
DC
ff
EC
FC
dd
BD
hh ll
CD
ee ff
DD
ff
ED
FD
ii
A6
dd
B6
hh ll
C6
ee ff
D6
ff
E6
F6
ff
9EE6
ee ff
9ED6
4555ii jjdd3
4
1
1
4
3
5
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
4
MC68HC908AP Family Data Sheet, Rev. 3
64 Freescale Semiconductor
Table 4-1. Instruction Set Summary
Opcode Map
Source
Form
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Effect on
Operation Description
CCR
VH I NZC
Load X from M X ← (M) 0 – – RR –
Logical Shift Left
(Same as ASL)
Logical Shift Right R ––0RR
Move
C
b7
b7
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
← (M)
0
b0
C0
b0
Source
R ––RRR
0––RR–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DD
DIX+
IMD
IX+D
Address
Mode
Opcode
AE
BE
CE
DE
EE
FE
9EEE
9EDE
38
48
58
68
78
9E68
34
44
54
64
74
9E64
4E
5E
6E
7E
Operand
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
Cycles
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
5
4
4
4
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
4
1
1
4
3
5
2
3
4
4
3
2
4
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP No Operation None ––––––INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – RR–
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
R ––RRR
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
30
40
50
60
70
9E60
AA
BA
CA
DA
EA
FA
9EEA
9EDA
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 65
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Source
Form
PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
Rotate Left through Carry R ––RRR
Rotate Right through Carry R ––RRR
Operation Description
C
b7
b7
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
b0
b0
C
CCR
Mode
39
49
59
69
79
9E69
36
46
56
66
76
9E66
Opcode
Operand
dd
ff
ff
dd
ff
ff
VH I NZC
RRRRRRINH 80 7
Address
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
4
1
1
4
3
5
4
1
1
4
3
5
Effect on
Cycles
RTS Return from Subroutine
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – RR– DIR 35 dd 4
STOP Enable IRQ
Subtract with Carry A ← (A) – (M) – (C) R ––RRR
Store A in M M ← (A) 0 – – RR–
Pin; Stop Processing I ← 0; Stop Processing ––0–––INH 8E 1
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
––––––INH 81 4
2
ii
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
B7
C7
D7
E7
F7
9EE7
9ED7
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
3
4
4
3
2
4
5
MC68HC908AP Family Data Sheet, Rev. 3
66 Freescale Semiconductor
Table 4-1. Instruction Set Summary
Opcode Map
Source
Form
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI Software Interrupt
Store X in M M ← (X) 0 – – RR–
Subtract A ← (A) – (M) R ––RRR
Operation Description
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP
← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Effect on
CCR
Mode
VH I NZC
––1–––INH 83 9
Address
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Opcode
BF
CF
DF
EF
FF
9EEF
9EDF
A0
B0
C0
D0
E0
F0
9EE0
9ED0
Operand
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
Cycles
TAP Transfer A to CCR CCR ← (A) RRRRRRINH 84 2
TAX Transfer A to X X ← (A) ––––––INH 97 1
TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1
dd
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A ← (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
WAIT Enable Interrupts; Wait for Interrupt
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – RR–
I ← 0; Inhibit CPU clocking until
interrupted
––0–––INH 8F 1
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
3
1
1
3
ff
2
4
ff
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 67
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Source
Form
A Accumulator n Any bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location R Set or cleared
N Negative bit — Not affected
Operation Description
⊕ Logical EXCLUSIVE OR
« Sign extend
CCR
VH I NZC
Address
Mode
Opcode
Effect on
Cycles
Operand
MC68HC908AP Family Data Sheet, Rev. 3
68 Freescale Semiconductor
Freescale Semiconductor 69
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
MSB
LSB
05BRSET0
15BRCLR0
25BRSET1
35BRCLR1
MC68HC908AP Family Data Sheet, Rev. 3
45BRSET2
55BRCLR2
65BRSET3
75BRCLR3
85BRSET4
95BRCLR4
A5BRSET5
B5BRCLR5
C5BRSET6
D5BRCLR6
E5BRSET7
F5BRCLR7
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
01234569E6789ABCD9EDE9EEF
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
4
BSET0
2DIR
4
BCLR0
2DIR
4
BSET1
2DIR
4
BCLR1
2DIR
4
BSET2
2DIR
4
BCLR2
2DIR
4
BSET3
2DIR
4
BCLR3
2DIR
4
BSET4
2DIR
4
BCLR4
2DIR
4
BSET5
2DIR
4
BCLR5
2DIR
4
BSET6
2DIR
4
BCLR6
2DIR
4
BSET7
2DIR
4
BCLR7
2DIR
3
BRA
2REL
3
BRN
2REL
3
BHI
2REL
3
BLS
2REL
3
BCC
2REL
3
BCS
2REL
3
BNE
2REL
3
BEQ
2REL
3
BHCC
2REL
3
BHCS
2REL
3
BPL
2REL
3
BMI
2REL
3
BMC
2REL
3
BMS
2REL
3
BIL
2REL
3
BIH
2REL
4
NEG
2DIR
5
CBEQ
3DIR
4
COM
2DIR
4
LSR
2DIR
4
STHX
2DIR
4
ROR
2DIR
4
ASR
2DIR
4
LSL
2DIR
4
ROL
2DIR
4
DEC
2DIR
5
DBNZ
3DIR
4
INC
2DIR
3
TST
2DIR
3
CLR
2DIR
1
NEGA
1INH
4
CBEQA
3IMM
5
MUL
1INH
1
COMA
1INH
1
LSRA
1INH
3
LDHX
3IMM
1
RORA
1INH
1
ASRA
1INH
1
LSLA
1INH
1
ROLA
1INH
1
DECA
1INH
3
DBNZA
2INH
1
INCA
1INH
1
TSTA
1INH
5
MOV
3DD
1
CLRA
1INH
1
NEGX
1INH
4
CBEQX
3IMM
7
DIV
1INH
1
COMX
1INH
1
LSRX
1INH
4
LDHX
2DIR
1
RORX
1INH
1
ASRX
1INH
1
LSLX
1INH
1
ROLX
1INH
1
DECX
1INH
3
DBNZX
2INH
1
INCX
1INH
1
TSTX
1INH
4
MOV
2DIX+
1
CLRX
1INH
*Pre-byte for stack pointer indexed instructions
4
NEG
2IX1
3IX1+
1INH
2IX1
2IX1
3IMM
2IX1
2IX1
2IX1
2IX1
2IX1
3IX1
2IX1
2IX1
3IMD
2IX1
5
CBEQ
3
NSA
4
COM
4
LSR
3
CPHX
4
ROR
4
ASR
4
LSL
4
ROL
4
DEC
5
DBNZ
4
INC
3
TST
4
MOV
3
CLR
3SP1
4SP1
3SP1
3SP1
3SP1
3SP1
3SP1
3SP1
3SP1
4SP1
3SP1
3SP1
3SP1
Table 4-2. Opcode Map
5
NEG
6
CBEQ
5
COM
5
LSR
ROR
5
ASR
5
LSL
5
ROL
5
DEC
6
DBNZ
5
INC
4
TST
4
CLR
3
NEG
1IX
4
CBEQ
2IX+
2
DAA
1INH
3
COM
1IX
3
LSR
1IX
4
CPHX
2DIR
5
3
ROR
1IX
3
ASR
1IX
3
LSL
1IX
3
ROL
1IX
3
DEC
1IX
4
DBNZ
2IX
3
INC
1IX
2
TST
1IX
4
MOV
2IX+D
2
CLR
1IX
Low Byte of Opcode in Hexadecimal 05BRSET0
7
RTI
1INH
4
RTS
1INH
9
SWI
1INH
2
TA P
1INH
1
TPA
1INH
2
PULA
1INH
2
PSHA
1INH
2
PULX
1INH
2
PSHX
1INH
2
PULH
1INH
2
PSHH
1INH
1
CLRH
1INH
1
STOP
1INH
1
WAIT
1INH
3
BGE
2REL
3
BLT
2REL
3
BGT
2REL
3
BLE
2REL
2
TXS
1INH
2
TSX
1INH
1
TA X
1INH
1
CLC
1INH
1
SEC
1INH
2
CLI
1INH
2
SEI
1INH
1
RSP
1INH
1
NOP
1INH
*
1
TXA
1INH
2
SUB
2IMM
2
CMP
2IMM
2
SBC
2IMM
2
CPX
2IMM
2
AND
2IMM
2
BIT
2IMM
2
LDA
2IMM
2
AIS
2IMM
2
EOR
2IMM
2
ADC
2IMM
2
ORA
2IMM
2
ADD
2IMM
4
BSR
2REL
2
LDX
2IMM
2
AIX
2IMM
3
SUB
2DIR
3
CMP
2DIR
3
SBC
2DIR
3
CPX
2DIR
3
AND
2DIR
3
BIT
2DIR
3
LDA
2DIR
3
STA
2DIR
3
EOR
2DIR
3
ADC
2DIR
3
ORA
2DIR
3
ADD
2DIR
2
JMP
2DIR
4
JSR
2DIR
3
LDX
2DIR
3
STX
2DIR
MSB
LSB
4
SUB
3EXT
4
CMP
3EXT
4
SBC
3EXT
4
CPX
3EXT
4
AND
3EXT
4
BIT
3EXT
4
LDA
3EXT
4
STA
3EXT
4
EOR
3EXT
4
ADC
3EXT
4
ORA
3EXT
4
ADD
3EXT
3
JMP
3EXT
5
JSR
3EXT
4
LDX
3EXT
4
STX
3EXT
0 High Byte of Opcode in Hexadecimal
3DIR
4
SUB
3IX2
4
CMP
3IX2
4
SBC
3IX2
4
CPX
3IX2
4
AND
3IX2
4
BIT
3IX2
4
LDA
3IX2
4
STA
3IX2
4
EOR
3IX2
4
ADC
3IX2
4
ORA
3IX2
4
ADD
3IX2
4
JMP
3IX2
6
JSR
3IX2
4
LDX
3IX2
4
STX
3IX2
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
5
SUB
4SP2
5
CMP
4SP2
5
SBC
4SP2
5
CPX
4SP2
5
AND
4SP2
5
BIT
4SP2
5
LDA
4SP2
5
STA
4SP2
5
EOR
4SP2
5
ADC
4SP2
5
ORA
4SP2
5
ADD
4SP2
5
LDX
4SP2
5
STX
4SP2
3
SUB
2IX1
3
CMP
2IX1
3
SBC
2IX1
3
CPX
2IX1
3
AND
2IX1
3
BIT
2IX1
3
LDA
2IX1
3
STA
2IX1
3
EOR
2IX1
3
ADC
2IX1
3
ORA
2IX1
3
ADD
2IX1
3
JMP
2IX1
5
JSR
2IX1
3
LDX
2IX1
3
STX
2IX1
4
SUB
3SP1
4
CMP
3SP1
4
SBC
3SP1
4
CPX
3SP1
4
AND
3SP1
4
BIT
3SP1
4
LDA
3SP1
4
STA
3SP1
4
EOR
3SP1
4
ADC
3SP1
4
ORA
3SP1
4
ADD
3SP1
4
LDX
3SP1
4
STX
3SP1
2
SUB
1IX
2
CMP
1IX
2
SBC
1IX
2
CPX
1IX
2
AND
1IX
2
BIT
1IX
2
LDA
1IX
2
STA
1IX
2
EOR
1IX
2
ADC
1IX
2
ORA
1IX
2
ADD
1IX
2
JMP
1IX
4
JSR
1IX
2
LDX
1IX
2
STX
1IX
Opcode Map
Central Processor Unit (CPU)
MC68HC908AP Family Data Sheet, Rev. 3
70 Freescale Semiconductor
Chapter 5 Oscillator (OSC)
5.1 Introduction
The oscillator module consist of three types of oscillator circuits:
• Internal oscillator
• RC oscillator
• 32.768 kHz crystal (x-tal) oscillator
The reference clock for the CGM and other MCU sub-systems is selected by programming the mask
option register located at $FFCF.
The reference clock for the timebase module (TBM) is selected by the two bits, OSCCLK1 and OSCCLK0,
in the CONFIG2 register.
The internal oscillator runs continuously after a POR or reset, and is always available. The RC and crystal
oscillator cannot run concurrently; one is disabled while the other is selected; because the RC and x-tal
circuits share the same OSC1 pin.
NOTE
The oscillator circuits are powered by the on-chip V
therefore, the output swing on OSC1 and OSC2 is from V
Figure 5-1. shows the block diagram of the oscillator module.
regulator,
REG
SS
to V
REG
.
5.2 Clock Selection
Reference clocks are selectable for the following sub-systems:
• CGMXCLK and CGMRCLK — Reference clock for clock generator module (CGM) and other MCU
sub-systems other than TBM and COP. This is the main reference clock for the MCU.
• OSCCLK — Reference clock for timebase module (TBM).
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 71
Oscillator (OSC)
To CGM and others
CGMXCLK CGMRCLK
MOR CONFIG2
OSCSEL1
MUX
OSCSEL0
XCLK
X-TAL OSCILLATOR RC OSCILLATOR INTERNAL OSCILLATOR
To CGM PLL
RCCLK
To TBM
OSCCLK
OSCCLK1
MUX
OSCCLK0
XRCIXRCI
To SIM
(and COP)
ICLK
BUS CLOCK
OSC1 OSC2
From SIM
Figure 5-1. Oscillator Module Block Diagram
5.2.1 CGM Reference Clock Selection
The clock generator module (CGM) reference clock (CGMXCLK) is the reference clock input to the MCU.
It is selected by programming two bits in a FLASH memory location; the mask option register (MOR), at
$FFCF. See 3.5 Mask Option Register (MOR).
Address: $FFCF
Bit 7654321Bit 0
Read:
OSCSEL1OSCSEL0RRRRRR
Write:
Reset: Unaffected by reset
Erased:11111111
R=Reserved
Figure 5-2. Mask Option Register (MOR)
MC68HC908AP Family Data Sheet, Rev. 3
72 Freescale Semiconductor
Table 5-1. CGMXCLK Clock Selection
OSCSEL1 OSCSEL0 CGMXCLK OSC2 Pin Comments
0 0 — — Not used
Clock Selection
01ICLK
1 0 RCCLK
11XCLK
f
BUS
f
BUS
Inverting
output of
X-TAL
Internal oscillator generates the CGMXCLK.
RC oscillator generates the CGMXCLK.
Internal oscillator is available after each POR or
reset.
X-tal oscillator generates the CGMXCLK.
Internal oscillator is available after each POR or
reset.
NOTE
The internal oscillator is a free running oscillator and is available after each
POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS
bit in CONFIG2.
5.2.2 TBM Reference Clock Selection
The timebase module reference clock (OSCCLK) is selected by configuring two bits in the CONFIG2
register, at $001D. See Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR).
Address: $001D
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
STOP_
ICLKDIS
STOP_
RCLKEN
STOP_
XCLKEN
OSCCLK1 OSCCLK0
00
SCIBD-
SRC
Figure 5-3. Configuration Register 2 (CONFIG2)
Table 5-2. Timebase Module Reference Clock Selection
OSCCLK1 OSCCLK0 Timebase Clock Source
0 0 Internal oscillator (ICLK)
0 1 RC oscillator (RCCLK)
1 0 X-tal oscillator (XCLK)
1 1 Not used
NOTE
The RCCLK or XCLK is only available if that clock is selected as the CGM
reference clock, whereas the ICLK is always available.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 73
Oscillator (OSC)
5.3 Internal Oscillator
The internal oscillator clock (ICLK), with a frequency of f
, is a free running clock that requires no
ICLK
external components. It can be selected as the CGMXCLK for the CGM and MCU sub-systems; and the
OSCCLK clock for the TBM. The ICLK is also the reference clock input to the computer operating properly
(COP) module.
Due to the simplicity of the internal oscillator, it does not have the accuracy and stability of the RC
oscillator or the x-tal oscillator. Therefore, the ICLK is not suitable where an accurate bus clock is required
and it should not be used as the CGMRCLK to the CGM PLL.
The internal oscillator by default is always available and is free running after POR or reset. It can be
turned-off in stop mode by setting the STOP_ICLKDIS bit before executing the STOP instruction.
Figure 5-4 shows the logical representation of components of the internal oscillator circuitry.
CONFIG2
STOP_ICLKDIS
From SIM
SIMOSCEN
To Clock Selection MUX
and COP
ICLK
EN
INTERNAL OSCILLATOR
BUS CLOCK
From SIM
MCU
OSC2
Figure 5-4. Internal Oscillator
MC68HC908AP Family Data Sheet, Rev. 3
74 Freescale Semiconductor
RC Oscillator
5.4 RC Oscillator
The RC oscillator circuit is designed for use with an external resistor and a capacitor.
In its typical configuration, the RC oscillator requires two external components, one R and one C.
Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10%
tolerance. The oscillator configuration uses two components:
•C
EXT
•R
EXT
From SIM
SIMOSCEN
CONFIG2
STOP_RCLKEN
MCU
See Chapter 22 for component value requirements.
Figure 5-5. RC Oscillator
To Clock Selection MUX
RCCLK
EN
RC OSCILLATOR
OSC1
V
REG
R
EXT
From SIM
BUS CLOCK
OSC2
C
EXT
5.5 X-tal Oscillator
The crystal (x-tal) oscillator circuit is designed for use with an external 32.768kHz crystal to provide an
accurate clock source.
In its typical configuration, the x-tal oscillator is connected in a Pierce oscillator configuration, as shown
in Figure 5-6. This figure shows only the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five components:
•Crystal, X
• Fixed capacitor, C
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, R
• Series resistor, RS (optional)
Freescale Semiconductor 75
(32.768kHz)
1
1
B
MC68HC908AP Family Data Sheet, Rev. 3
Oscillator (OSC)
From SIM
SIMOSCEN
CONFIG2
STOP_XCLKEN
MCU
See Chapter 22 for component value requirements.
C
1
To Clock Selection MUX
OSC2OSC1
R
B
R
X
1
32.768kHz
C
XCLK
S
2
Figure 5-6. Crystal Oscillator
The series resistor (R
) is included in the diagram to follow strict Pierce oscillator guidelines and may not
S
be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
5.6 I/O Signals
The following paragraphs describe the oscillator I/O signals.
5.6.1 Crystal Amplifier Input Pin (OSC1)
OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.
5.6.2 Crystal Amplifier Output Pin (OSC2)
When the x-tal oscillator is selected, OSC2 pin is the output of the crystal oscillator inverting amplifier.
When the RC oscillator or internal oscillator is selected, OSC2 pin is the output of the internal bus clock.
5.6.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal from the system integration module (SIM) enables/disables the x-tal oscillator, the
RC-oscillator, or the internal oscillator circuit.
MC68HC908AP Family Data Sheet, Rev. 3
76 Freescale Semiconductor
Low Power Modes
5.6.4 CGM Oscillator Clock (CGMXCLK)
The CGMXCLK clock is output from the x-tal oscillator, RC oscillator or the internal oscillator. This clock
drives to CGM and other MCU sub-systems.
5.6.5 CGM Reference Clock (CGMRCLK)
This is buffered signal of CGMXCLK, it is used by the CGM as the phase-locked-loop (PLL) reference
clock.
5.6.6 Oscillator Clock to Time Base Module (OSCCLK)
The OSCCLK is the reference clock that drives the timebase module. See Chapter 10 Timebase Module
(TBM).
5.7 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
5.7.1 Wait Mode
The WAIT instruction has no effect on the oscillator module. CGMXCLK continues to drive to the clock
generator module, and OSCCLK continues to drive the timebase module.
5.7.2 Stop Mode
The STOP instruction disables the x-tal or the RC oscillator circuit, and hence the CGMXCLK clock stops
running. For continuous x-tal or RC oscillator operation in stop mode, set the STOP_XCLKEN (for x-tal)
or STOP_RCLKEN (for RC) bit to logic 1 before entering stop mode.
The internal oscillator clock continues operation in stop mode. It can be disabled by setting the
STOP_ICLKDIS bit to logic 1 before entering stop mode.
5.8 Oscillator During Break Mode
The oscillator continues to drive CGMXCLK when the device enters the break state.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 77
Oscillator (OSC)
MC68HC908AP Family Data Sheet, Rev. 3
78 Freescale Semiconductor
Chapter 6 Clock Generator Module (CGM)
6.1 Introduction
This section describes the clock generator module (CGM). The CGM generates the base clock signal,
CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop
(PLL) clock, CGMPCLK, divided by two. CGMOUT is the clock from which the SIM derives the system
clocks, including the bus clock, which is at a frequency of CGMOUT÷2.
The PLL is a frequency generator designed for use with a low frequency crystal (typically 32.768kHz) to
generate a base frequency and dividing to a maximum bus frequency of 8MHz.
6.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
• Low-frequency crystal operation with low-power operation and high-output frequency resolution
• Programmable prescaler for power-of-two increases in frequency
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop mode
6.3 Functional Description
The CGM consists of three major sub-modules:
• Oscillator module — The oscillator module generates the constant reference frequency clock,
CGMRCLK (buffered CGMXCLK).
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK, and the divided VCO clock, CGMPCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the divided VCO clock, CGMPCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from either CGMOUT or CGMXCLK.
Figure 6-1 shows the structure of the CGM.
Figure 6-2 is a summary of the CGM registers.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 79
Clock Generator Module (CGM)
OSC2
OSC1
OSCSEL[1:0]
OSCCLK[1:0]
SIMOSCEN
From SIM
CGMRDV
OSCILLATOR (OSC) MODULE
See Chapter 5 Oscillator (OSC).
INTERNAL OSCILLATOR
RC OSCILLATOR
CRYSTAL OSCILLATOR
PHASE-LOCKED LOOP (PLL)
REFERENCE
DIVIDER
R
RDS[3:0]
V
DDA
MUX
CGMRCLK
CGMXFC V
ICLK
OSCCLK
CGMXCLK
CGMRCLK
SSA
VRS[7:0]
BCS
L
VPR[1:0]
E
2
CLOCK
SELECT
CIRCUIT
CGMPCLK
To SIM (and COP)
To Timebase Module (TBM)
To ADC
A
÷ 2
B
*WHEN S = 1,
CGMOUT = B
CGMOUT
1
S*
To SIM
SIMDIV2
From SIM
CGMVDV
PHASE
DETECTOR
LOCK
DETECTOR
LOOP
FILTER
AUTOMATIC
MODE
CONTROL
LOCK AUTO ACQ
MUL[11:0]
N
FREQUENCY
DIVIDER
Figure 6-1. CGM Block Diagram
PLL ANALOG
PRE[1:0]
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
INTERRUPT
CONTROL
PLLIE PLLF
P
2
CGMVCLK
CGMINT
To SIM
MC68HC908AP Family Data Sheet, Rev. 3
80 Freescale Semiconductor
Functional Description
Addr.Register Name Bit 7654321Bit 0
$0036
$0037
$0038
$0039
$003A
$003B
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Control Register
(PTCL)
PLL Bandwidth Control
Register
(PBWC)
PLL Multiplier Select
Register High
(PMSH)
PLL Multiplier Select
Register Low
(PMSL)
PLL VCO Range Select
Register
(PMRS)
PLL Reference Divider
Select Register
(PMDS)
Read:
Write:
Reset:00100000
Read:
Write:
Reset:0000000
Read:0000
Write:
Reset:00000000
Read:
Write:
Reset:01000000
Read:
Write:
Reset:01000000
Read:0000
Write:
Reset:00000001
PLLIE
AUTO
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
PLLF
LOCK
PLLON BCS PRE1 PRE0 VPR1 VPR0
ACQ
0000
MUL11 MUL10 MUL9 MUL8
RDS3 RDS2 RDS1 RDS0
= Unimplemented R
R
= Reserved
Figure 6-2. CGM I/O Register Summary
6.3.1 Oscillator Module
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module.
CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used
by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also
provides the reference clock for the timebase module (TBM). See Chapter 5 Oscillator (OSC) for detailed
oscillator circuit description. See Chapter 10 Timebase Module (TBM) for detailed description on TBM.
6.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
6.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency pre-scaler
• Modulo VCO frequency divider
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 81
Clock Generator Module (CGM)
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGMXFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
E
)f
(L × 2
NOM
.
, (125 kHz) times a linear factor, L, and a power-of-two factor, E, or
NOM
. Modulating the voltage on the
VRS
is equal to the nominal
VRS
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
, and is fed to the PLL through a programmable modulo reference divider, which divides f
f
RCLK
RCLK
by a
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
RDV=fRCLK
/R. With an external crystal
(30kHz–100kHz), always set R = 1 for specified performance. With an external high-frequency clock
source, use R to divide the external frequency to between 30kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
, is fed back through a programmable
VCLK
pre-scaler divider and a programmable modulo divider. The pre-scaler divides the VCO clock by a
power-of-two factor P (the CGMPCLK) and the modulo divider reduces the VCO clock by a factor, N. The
dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, f
VDV=fVCLK
/(N × 2P). (See
6.3.6 Programming the PLL for more information.)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 6.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
. The circuit determines the mode of the PLL and the lock condition based on
RDV
this comparison.
6.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
• Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See 6.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 6.3.8 Base Clock Selector Circuit.) The PLL is automatically in
tracking mode when not in acquisition mode or when the ACQ
bit is set.
MC68HC908AP Family Data Sheet, Rev. 3
82 Freescale Semiconductor
Functional Description
6.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 6.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL start-up, usually) or at periodic intervals. In either case, when the LOCK bit is
set, the VCO clock is safe to use as the source for the base clock. (See 6.3.8 Base Clock Selector Circuit.)
If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See 6.6
Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control mode:
•The ACQ
the filter. (See 6.3.4 Acquisition and Tracking Modes.)
•The ACQ
VCO frequency is out of a certain tolerance. (See 6.8 Acquisition/Lock Time Specifications for
more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 6.8 Acquisition/Lock Time Specifications for
more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 6.5.1 PLL Control Register.)
bit (See 6.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of
bit is set when the VCO frequency is within a certain tolerance and is cleared when the
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f
BUSMAX
.
The following conditions apply when in manual mode:
•ACQ
• Before entering tracking mode (ACQ
is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ
bit must be clear.
= 1), software must wait a given time, t
(See 6.8
ACQ
Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, t
, after entering tracking mode before selecting the PLL as the
AL
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
6.3.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 83
Clock Generator Module (CGM)
1. Choose the desired bus frequency, f
BUSDES
, or the desired VCO frequency, f
VCLKDES
; and then
solve for the other.
The relationship between f
BUS
f
VCLK
and f
is governed by the equation:
VCLK
2Pf
× 2P4× f
CGMPCLK
×==
BUS
where P is the power of two multiplier, and can be 0, 1, 2, or 3
2. Choose a practical PLL reference frequency, f
, and the reference clock divider, R. Typically,
RCLK
the reference is 32.768kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
/R. For stability and lock time reduction,
RCLK
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
f
VCLK
, and the reference frequency, f
VCLK
2PN
()=
----------- f
RCLK
R
RCLK,
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f
to a value determined
RCLK
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 22 Electrical
Specifications.
Choose the reference divider, R = 1.
is
When the tolerance on the bus frequency is tight, choose f
and R = 1. If f
practical choices of f
cannot meet this requirement, use the following equation to solve for R with
RCLK
, and choose the f
RCLK
R round R
f
⎛⎞
⎧⎫
VCLKDES
--------------------------
×=
⎜⎟
⎨⎬
MAX
f
⎝⎠
RCLK
⎩⎭
that gives the lowest R.
RCLK
integer
–
to an integer divisor of f
RCLK
f
⎛⎞
VCLKDES
--------------------------
⎜⎟
f
⎝⎠
RCLK
3. Calculate N:
×
Rf
⎛⎞
VCLKDES
N round
=
-------------------------------------
⎜⎟
⎝⎠
f
RCLK
2P×
4. Calculate and verify the adequacy of the VCO and bus frequencies f
2PN
=
----------- f
R
f
VCLK
-----------
2P4×
()=
RCLK
f
VCLK
f
BUS
VCLK
and f
BUS
.
BUSDES
,
MC68HC908AP Family Data Sheet, Rev. 3
84 Freescale Semiconductor
5. Select the VCO’s power-of-two range multiplier E, according to this table:
Frequency Range E
Functional Description
0 < f
9,830,400 ≤ f
19,660,800 ≤ f
NOTE: Do not program E to a value of 3.
6. Select a VCO linear range multiplier, L, where f
< 9,830,400
VCLK
VCLK
VCLK
L round
=
< 19,660,800
< 39,321,600
= 125kHz
NOM
f
⎛⎞
VCLK
--------------------------
⎜⎟
⎝⎠
2Ef
×
NOM
0
1
2
7. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, f
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
VRS
NOM
E
L2
×()f
=
f
For proper operation,
f
–
VRSfVCLK
f
NOM
--------------------------
≤
2E×
2
VRS
. The
8. Verify the choice of P, R, N, E, and L by comparing f
operation, f
as possible to f
must be within the application’s tolerance of f
VCLK
VCLK.
VCLK
to f
and f
VRS
VCLKDES
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
9. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program the binary coded equivalent of
R.
NOTE
The values for P, E, N, L, and R can only be programmed when the PLL is
off (PLLON = 0).
Table 6-1 provides numeric examples (numbers are in hexadecimal notation):
VCLKDES
, and f
. For proper
must be as close
VRS
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 85
Clock Generator Module (CGM)
Table 6-1. Numeric Examples
CGMVCLK CGMPCLK
8.0 MHz 8.0 MHz 2.0 MHz 32.768 kHz 1 F5 0 0 40
9.8304 MHz 9.8304 MHz 2.4576 MHz 32.768 kHz 1 12C 0 1 27
10.0 MHz 10.0 MHz 2.5 MHz 32.768 kHz 1 132 0 1 28
16 MHz 16 MHz 4.0 MHz 32.768 kHz 1 1E9 0 1 40
19.6608 MHz 19.6608 MHz 4.9152 MHz 32.768 kHz 1 258 0 2 27
20 MHz 20 MHz 5.0 MHz 32.768 kHz 1 263 0 2 28
29.4912 MHz 29.4912 MHz 7.3728 MHz 32.768 kHz 1 384 0 2 3B
32 MHz 32 MHz 8.0 MHz 32.768 kHz 1 3D1 0 2 40
32 MHz 16 MHz 4.0 MHz 32.768 kHz 1 1E9 1 2 40
32 MHz 8 MHz 2.0 MHz 32.768 kHz 1 F5 2 2 40
32 MHz 4 MHz 1.0 MHz 32.768 kHz 1 7B 3 2 40
f
BUS
f
RCLK
RNPEL
6.3.7 Special Programming Exceptions
The programming method described in 6.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
(See 6.3.8 Base Clock Selector Circuit.)
6.3.8 Base Clock Selector Circuit
This circuit is used to select either the oscillator clock, CGMXCLK, or the divided VCO clock, CGMPCLK,
as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that
waits up to three CGMXCLK cycles and three CGMPCLK cycles to change from one clock source to the
other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then
divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base
clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMPCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The divided VCO
clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned
off if the divided VCO clock is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the divided VCO clock. The divided VCO clock also cannot be selected as the
base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent
with the operation of the PLL, so that the PLL would be disabled and the oscillator clock would be forced
as the source of the base clock.
MC68HC908AP Family Data Sheet, Rev. 3
86 Freescale Semiconductor
I/O Signals
6.3.9 CGM External Connections
In its typical configuration, the CGM requires up to four external components.
Figure 6-3 shows the external components for the PLL:
• Bypass capacitor, C
• Filter network
Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 6.8
Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL
performance.)
BYP
MCU
CGMXFC
1 kΩ
0.22 µF
Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability.
10 nF
V
SSA
V
DDA
C
BYP
0.1 µF
V
DD
Figure 6-3. CGM External Connections
6.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
6.4.1 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 6-3.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
6.4.2 PLL Analog Power Pin (V
V
is a power pin used by the analog portions of the PLL. Connect the V
DDA
potential as the V
DD
pin.
DDA
)
pin to the same voltage
DDA
NOTE
Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 87
Clock Generator Module (CGM)
6.4.3 PLL Analog Ground Pin (V
V
is a ground pin used by the analog portions of the PLL. Connect the V
SSA
potential as the V
SS
pin.
SSA
)
pin to the same voltage
SSA
NOTE
Route V
carefully for maximum noise immunity and place bypass
SSA
capacitors as close as possible to the package.
6.4.4 Oscillator Output Frequency Signal (CGMXCLK)
CGMXCLK is the oscillator output signal. It runs at the full speed of the oscillator, and is generated directly
from the crystal oscillator circuit, the RC oscillator circuit, or the internal oscillator circuit.
6.4.5 CGM Reference Clock (CGMRCLK)
CGMRCLK is a buffered version of CGMXCLK, this clock is the reference clock for the phase-locked-loop
circuit.
6.4.6 CGM VCO Clock Output (CGMVCLK)
CGMVCLK is the clock output from the VCO.
6.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the divided VCO clock,
CGMPCLK, divided by two.
6.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
6.5 CGM Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL)
(See 6.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 6.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select registers (PMSH and PMSL)
(See 6.5.3 PLL Multiplier Select Registers.)
• PLL VCO range select register (PMRS)
(See 6.5.4 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 6.5.5 PLL Reference Divider Select Register.)
MC68HC908AP Family Data Sheet, Rev. 3
88 Freescale Semiconductor
CGM Registers
6.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
Address: $0036
Bit 7654321Bit 0
Read:
Write:
Reset:00100000
PLLIE
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = Change in lock condition
0 = No change in lock condition
PLLF
= Unimplemented
PLLON BCS PRE1 PRE0 VPR1 VPR0
Figure 6-4. PLL Control Register (PCTL)
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 6.3.8 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the oscillator output, CGMXCLK, or the divided VCO clock,
CGMPCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMPCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See 6.3.8 Base Clock
Selector Circuit.) Reset clears the BCS bit.
1 = CGMPCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 89
Clock Generator Module (CGM)
NOTE
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMPCLK requires two writes to the PLL control register. (See
6.3.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
6.3.3 PLL Circuits and 6.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
These prescaler bits affects the relationship between the VCO clock and the final system bus clock.
Table 6-2. PRE1 and PRE0 Programming
PRE1 and PRE0 P Prescaler Multiplier
00 0 1
01 1 2
10 2 4
11 3 8
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See 6.3.3 PLL Circuits, 6.3.6 Programming the PLL, and 6.5.4 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, f
. VPR1:VPR0 cannot be written when
VRS
the PLLON bit is set. Reset clears these bits.
Table 6-3. VPR1 and VPR0 Programming
VPR1 and VPR0 E
00 0 1
01 1 2
10 2 4
NOTE: Do not program E to a value of 3.
VCO Power-of-Two
Range Multiplier
MC68HC908AP Family Data Sheet, Rev. 3
90 Freescale Semiconductor
CGM Registers
6.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address: $0037
Bit 7654321Bit 0
Read:
Write:
Reset:0000000
AUTO
LOCK
= Unimplemented R=Reserved
ACQ
Figure 6-5. PLL Bandwidth Control Register (PBWCR)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ
bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
0000
R
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ
— Acquisition Mode Bit
When the AUTO bit is set, ACQ
or tracking mode. When the AUTO bit is clear, ACQ
is a read-only bit that indicates whether the PLL is in acquisition mode
is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 91
Clock Generator Module (CGM)
6.5.3 PLL Multiplier Select Registers
The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the
modulo feedback divider.
Address: $0038
Bit 7654321Bit 0
Read: 0 0 0 0
Write:
Reset:00000000
= Unimplemented
Figure 6-6. PLL Multiplier Select Register High (PMSH)
Address: $0039
Bit 7654321Bit 0
Read:
Write:
Reset:01000000
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Figure 6-7. PLL Multiplier Select Register Low (PMSL)
MUL11 MUL10 MUL9 MUL8
MUL[11:0] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier N.
(See 6.3.3 PLL Circuits and 6.3.6 Programming the PLL.) A value of $0000 in the multiplier select
registers configure the modulo feedback divider the same as a value of $0001. Reset initializes the
registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
6.5.4 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address: $003A
Bit 7654321Bit 0
Read:
Write:
Reset:01000000
VRS[7:0] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See 6.3.3 PLL Circuits, 6.3.6 Programming the PLL, and 6.5.1 PLL Control Register.), controls the
hardware center-of-range frequency, f
PCTL is set. (See 6.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Figure 6-8. PLL VCO Range Select Register (PMRS)
. VRS[7:0] cannot be written when the PLLON bit in the
VRS
MC68HC908AP Family Data Sheet, Rev. 3
92 Freescale Semiconductor
Interrupts
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 6.3.8 Base
Clock Selector Circuit and 6.3.7 Special Programming Exceptions.). Reset initializes the register to $40
for a default range multiply value of 64.
NOTE
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
6.5.5 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
Address: $003B
Bit 7654321Bit 0
Read: 0 0 0 0
Write:
Reset:00000001
= Unimplemented
RDS3 RDS2 RDS1 RDS0
Figure 6-9. PLL Reference Divider Select Register (PMDS)
RDS[3:0] — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See 6.3.3 PLL Circuits and 6.3.6 Programming the PLL.) RDS[3:0] cannot be written when the PLLON
bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference
divider the same as a value of $01. (See 6.3.7 Special Programming Exceptions.) Reset initializes the
register to $01 for a default divide value of 1.
NOTE
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE
The default divide value of 1 is recommended for all applications.
6.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the divided VCO clock, CGMPCLK, divided by
two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 93
Clock Generator Module (CGM)
VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not
frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding
software performance or from exceeding stack limitations.
NOTE
Software can select the CGMPCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
6.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
6.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
6.7.2 Stop Mode
The STOP instruction disables the PLL analog circuits and no clock will be driven out of the VCO.
When entering stop mode with the VCO clock (CGMPCLK) selected, before executing the STOP
instruction:
1. Set the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2) if continuos clock is required
in stop mode.
2. Clear the BCS bit to select CGMXCLK as CGMOUT.
On exit from stop mode:
1. Set the PLLON bit if cleared before entering stop mode.
2. Wait for PLL to lock by checking the LOCK bit.
3. Set BCS bit to select CGMPCLK as CGMOUT.
6.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 7.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
MC68HC908AP Family Data Sheet, Rev. 3
94 Freescale Semiconductor
Acquisition/Lock Time Specifications
6.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
6.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0Hz to 1MHz, the acquisition time is the time taken for the frequency to reach 1MHz ±50 kHz. 50 kHz =
5% of the 1MHz step input. If the system is operating at 1MHz and suffers a –100kHz noise hit, the
acquisition time is the time taken to return from 900kHz to 1MHz ±5kHz. 5kHz = 5% of the 100kHz step
input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
6.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, f
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency f
XCLK
R value programmed in the reference divider. (See 6.3.3 PLL Circuits, 6.3.6 Programming the PLL, and
6.5.5 PLL Reference Divider Select Register.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by
adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size
of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make
small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL
may not be able to adjust the voltage in a reasonable time. (See 6.8.3 Choosing a Filter.)
Also important is the operating voltage potential applied to V
. The power supply potential alters the
DDA
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
RDV
and the
.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 95
Clock Generator Module (CGM)
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
6.8.3 Choosing a Filter
As described in 6.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the
stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage.
Either of the filter networks in Figure 6-10 is recommended when using a 32.768kHz reference clock
(CGMRCLK). Figure 6-10 (a) is used for applications requiring better stability. Figure 6-10 (b) is used in
low-cost applications where stability is not critical.
1 kΩ
0.22 µF
CGMXFC
10 nF
V
SSA
(a) (b)
Figure 6-10. PLL Filter
CGMXFC
V
SSA
0.22 µF
MC68HC908AP Family Data Sheet, Rev. 3
96 Freescale Semiconductor
Chapter 7 System Integration Module (SIM)
7.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 7-1 shows the internal signal names used in this section.
Table 7-1. Signal Name Conventions
Signal Name Description
ICLK Internal oscillator clock
CGMXCLK Selected oscillator clock from oscillator module
CGMVCLK, CGMPCLK PLL output and the divided PLL output
CGMOUT
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
CGMPCLK-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Read/write signal
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 97
System Integration Module (SIM)
STOP/WAIT
CONTROL
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
RESET
PIN LOGIC
V
DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
CLOCK GENERATORS
RESET
SIM
COUNTER
÷ 2
CONTROL
MASTER
RESET
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
Figure 7-1. SIM Block Diagram
Addr.Register Name Bit 7654321Bit 0
$FE00
SIM Break Status Register
(SBSR)
Read:
Write: NOTE
RRRRRR
SBSW
R
Reset:00000000
Note: Writing a logic 0 clears SBSW.
Read: POR PIN COP ILOP ILAD MODRST LVI 0
$FE01
SIM Reset Status Register
(SRSR)
Write:
POR:10000000
$FE03
SIM Break Flag Control
Register (SBFCR)
Read:
Write:
BCFERRRRRRR
Reset: 0
Figure 7-2. SIM I/O Register Summary
MC68HC908AP Family Data Sheet, Rev. 3
98 Freescale Semiconductor
SIM Bus Clock Control and Generation
$FE04
Interrupt Status Register 1
(INT1)
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
$FE05
Interrupt Status Register 2
(INT2)
Write: RRRRRRRR
Reset: 00000000
Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15
$FE06
Interrupt Status Register 3
(INT3)
Write: RRRRRRRR
Reset: 00000000
= Unimplemented
Figure 7-2. SIM I/O Register Summary
7.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 6 Clock Generator Module
(CGM).)
OSC2
OSC1
STOP MODE CLOCK
ENABLE SIGNALS
FROM CONFIG2
7.2.1 Bus Timing
OSCILLATOR (OSC) MODULE
CGMRCLK
PHASE-LOCKED LOOP (PLL)
Figure 7-3. CGM Clock Signals
OSCCLK
CGMXCLK
ICLK
CGMOUT
SIMDIV2
CGMVCLK
TO TBM
TO TIM, ADC
SIM COUNTER
SYSTEM INTEGRATION MODULE
÷ 2
TO PWM
BUS CLOCK
GENERATORS
MONITOR MODE
USER MODE
SIMOSCEN
IT12
TO REST
OF MCU
IT23
TO REST
OF MCU
PTB0
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the
divided PLL output (CGMPCLK) divided by four.
MC68HC908AP Family Data Sheet, Rev. 3
Freescale Semiconductor 99
System Integration Module (SIM)
7.2.2 Clock Start-up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST
pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
7.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 ICLK cycles. (See 7.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
)
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 7.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 7.7 SIM Registers.)
7.3.1 External Pin Reset
The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST
minimum of 67 ICLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See
Table 7-2 for details. Figure 7-4 shows the relative timing.
Table 7-2. PIN Bit Set Timing
Reset Type Number of Cycles Required to Set PIN
POR/LVI 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
is held low for a
MC68HC908AP Family Data Sheet, Rev. 3
100 Freescale Semiconductor
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