Freescale MC68HC705P6A DATA SHEET
www.DataSheet4U.com
查询MC705P6A供应商
MC68HC705P6A
Advance Information Data Sheet
M68HC05
Microcontrollers
MC68HC705P6A
Rev. 2.1
9/2005
freescale.com
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
Blank
MC68HC705P6A
Advance Information Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
November,
2001
September,
2005
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Revision
Level
Format update to current publication standards N/A
2.0
2.1 Updated to meet Freescale identity guidelines. Throughout
Figure 11-1. Mask Option Register (MOR) — Definition of bit 6
corrected.
Description
Page
Number(s)
92
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 3
Revision History
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Chapter 4 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Chapter 5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Chapter 6 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chapter 7 Serial Input/Output Port (SIOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chapter 8 Capture/Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Chapter 9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chapter 10 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 11 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Chapter 12 Central Processor Unit (CPU) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 13 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Chapter 15 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Chapter 16 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 5
List of Chapters
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
6 Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.1 V
1.3.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.2.2 Ceramic Resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.2.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.3 RESET
1.3.4 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.5 PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V
1.3.7 PD5 and PD7/TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.8 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.9 IRQ
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8 Computer Operating Properly (COP) Clear Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . 16
REFH
/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2
Memory
Chapter 3
Operating Modes
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.2 WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 COP Watchdog Timer Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 7
Table of Contents
Chapter 4
Resets
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 External Reset (RESET
4.3 Internal Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 5
Interrupts
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Interrupt Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.1 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.2 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.3.1 External Interrupt (IRQ
5.2.3.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.3.3 Output Compare Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.3.4 Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 6
Input/Output Ports
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.6 I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 7
Serial Input/Output Port (SIOP)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.2 Serial Data Input (SDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.3 Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.1 SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.2 SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.3 SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
8 Freescale Semiconductor
Table of Contents
Chapter 8
Capture/Compare Timer
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.2 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3 Timer I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3.1 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.3.2 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.3.4 Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.3.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.3.6 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.4 Timer During Wait/Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.5 Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 9
Analog Subsystem
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2 Analog Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.2 Reference Voltage (V
9.2.3 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.3 Conversion Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4 Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4.1 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.3 Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.5 A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.6 A/D Conversion Data Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.7 A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.8 A/D Subsystem Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
REFH
Chapter 10
EPROM
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2 EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3 EPROM Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.4 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.5 EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.6 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.7 Programming from an External Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 9
Table of Contents
Chapter 11
Mask Option Register (MOR)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.2 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.3 MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 12
Central Processor Unit (CPU) Core
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.2.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.2.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.2.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 13
Instruction Set
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.2.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.2.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.2.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.2.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.3 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.3.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.3.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.3.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
13.3.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13.3.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
13.5 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Chapter 14
Electrical Specifications
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.3 Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.5 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.6 3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14.7 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
10 Freescale Semiconductor
Table of Contents
14.8 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.9 SIOP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.10 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 15
Mechanical Specifications
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15.2 Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15.3 Small Outline Integrated Circuit Package (Case 751F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 16
Ordering Information
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 11
Table of Contents
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
12 Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC705P6A is an EPROM version of the MC68HC05P6 microcontroller. It is a low-cost
combination of an M68HC05 Family microprocessor with a 4-channel, 8-bit analog-to-digital (A/D)
converter, a 16-bit timer with output compare and input capture, a serial communications port (SIOP), and
a computer operating properly (COP) watchdog timer. The M68HC05 CPU core contains 176 bytes of
RAM, 4672 bytes of user EPROM, 239 bytes of bootloader ROM, and 21 input/output (I/O) pins (20
bidirectional, 1 input-only). This device is available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin
small outline integrated circuit (SOIC) package.
A functional block diagram of the MC68HC705P6A is shown in Figure 1-1.
1.2 Features
Features of the MC68HC705P6A include:
• Low cost
• M68HC05 core
• 28-pin SOIC, PDIP, or windowed DIP package
• 4672 bytes of user EPROM (including 48 bytes of page zero EPROM and 16 bytes of user vectors)
• 239 bytes of bootloader ROM
• 176 bytes of on-chip RAM
• 4-channel 8-bit A/D converter
• SIOP serial communications port
• 16-bit timer with output compare and input capture
• 20 bidirectional I/O lines and 1 input-only line
• PC0 and PC1 high-current outputs
• Single-chip, bootloader, and test modes
• Power-saving stop, halt, and wait modes
• Static EPROM mask option register (MOR) selectable options:
– COP watchdog timer enable or disable
– Edge-sensitive or edge- and level-sensitive external interrupt
– SIOP most significant bit (MSB) or least significant bit (LSB) first
– SIOP clock rates: OSC divided by 8, 16, 32, or 64
– Stop instruction mode, STOP or HALT
– EPROM security external lockout
– Programmable keyscan (pullups/interrupts) on PA0–PA7
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 13
General Description
COP
INTERNAL
CPU CLOCK
÷2
OSC
OSC 1
OSC 2
RESET
IRQ/V
PB5/SDO
PB6/SDI
PB7/SCK
CPU CONTROL
M68HC05 CPU
PP
CPU REGISTERS
0 0 0 STK PNTR1100000
PROGRAM COUNTER
COND CODE REG 1 1 1 I N Z CH
SRAM — 176 BYTES
USER EPROM — 4672 BYTES
BOOTLOADER ROM — 239 BYTES
PORT B AND
SIOP
REGISTERS
AND LOGIC
ALU
ACCUM
INDEX REG
÷4
16-BIT TIMER
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
A/ D CONVERTER
PORT C
DATA DIRECTION REGISTER
DATA DIRECTION REG
MUX
PORT A
PD7/TCAP
TCMP
PD5
PC7/VR
EFH
PC6/AD0
PC5/AD1
PC4/AD2
PC3/AD3
PC2
PC1
PC0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
V
DD
V
SS
Figure 1-1. MC68HC705P6A Block Diagram
NOTE
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET
is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerances or limits are specified in Chapter 14 Electrical Specifications.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
14 Freescale Semiconductor
Functional Pin Description
1.3 Functional Pin Description
The following paragraphs describe the functionality of each pin on the MC68HC705P6A package. Pins
connected to subsystems described in other chapters provide a reference to the chapter instead of a
detailed functional description.
1.3.1 VDD and V
SS
Power is supplied to the MCU through VDD and VSS. VDD is connected to a regulated +5 volt supply and
is connected to ground.
V
SS
Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high
short-duration current demands on the power supply. To prevent noise problems, take special care to
provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency
characteristics and position them as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily the MCU pins are loaded.
1.3.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. The OSC1 and OSC2
pins can accept the following:
1. A crystal as shown in Figure 1-2(a)
2. A ceramic resonator as shown in Figure 1-2(a)
3. An external clock signal as shown in Figure 1-2(b)
The frequency, f
clock operating frequency, f
is clear when a STOP instruction is executed.
, of the oscillator or external clock source is divided by two to produce the internal bus
osc
. The oscillator cannot be turned off by software unless the MOR bit, SWAIT,
op
OSC1 OSC2
4.7 MΩ
37 pF 37 pF
(a) Crystal or Ceramic
Resonator Connections
Figure 1-2. Oscillator Connections
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
MCU
To VDD (or STOP) To VDD (or STOP)
OSC1 OSC2
UNCONNECTED
EXTERNAL CLOCK
(b) External Clock Source
Connections
MCU
Freescale Semiconductor 15
General Description
1.3.2.1 Crystal
The circuit in Figure 1-2(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. Follow
the crystal manufacturer’s recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable startup. The load capacitance
values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and
components as close as possible to the pins for startup stabilization and to minimize output distortion.
1.3.2.2 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a crystal. Use the circuit in Figure 1-2(a)
for a ceramic resonator and follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for startup stabilization and to
minimize output distortion.
1.3.2.3 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-2(b).
1.3.3 RESET
Driving this input low will reset the MCU to a known startup state. The RESET pin contains an internal
Schmitt trigger to improve its noise immunity. Refer to Chapter 4 Resets.
1.3.4 PA0–PA7
These eight I/O pins comprise port A. The state of any pin is software programmable and all port A lines
are configured as inputs during power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to Chapter 6 Input/Output Ports.
1.3.5 PB5/SDO, PB6/SDI, and PB7/SCK
These three I/O pins comprise port B and are shared with the SIOP communications subsystem. The
state of any pin is software programmable, and all port B lines are configured as inputs during power-on
or reset. Refer to Chapter 6 Input/Output Ports and Chapter 7 Serial Input/Output Port (SIOP).
1.3.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V
REFH
These eight I/O pins comprise port C and are shared with the A/D converter subsystem. The state of any
pin is software programmable and all port C lines are configured as inputs during power-on or reset. Refer
to Chapter 6 Input/Output Ports and Chapter 9 Analog Subsystem.
1.3.7 PD5 and PD7/TCAP
These two I/O pins comprise port D and one of them is shared with the 16-bit timer subsystem. The state
of PD5 is software programmable and is configured as an input during power-on or reset. PD7 is always
an input. It may be read at any time, regardless of which mode of operation the 16-bit timer is in. Refer to
Chapter 6 Input/Output Ports and Chapter 8 Capture/Compare Timer.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
16 Freescale Semiconductor
Functional Pin Description
1.3.8 TCMP
This pin is the output from the 16-bit timer’s output compare function. It is low after reset. Refer to
Chapter 8 Capture/Compare Timer.
1.3.9 IRQ/VPP (Maskable Interrupt Request)
This input pin drives the asynchronous interrupt function of the MCU in user mode and provides the VPP
programming voltage in bootloader mode. The MCU will complete the current instruction being executed
before it responds to the IRQ
internally to signify an interrupt has been requested. When the MCU completes its current instruction, the
interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
interrupt request. When the IRQ/VPP pin is driven low, the event is latched
Depending on the MOR LEVEL bit, the IRQ
the IRQ
be held low for at least one t
set), the IRQ
IRQ
/VPP pin and/or while the IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must
time period. If the edge- and level-sensitive mode is selected (LEVEL bit
ILIH
/VPP input pin requires an external resistor connected to VDD for wired-OR operation. If the
/VPP pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin input circuitry contains an
/VPP pin will trigger an interrupt on either a negative edge at
internal Schmitt trigger to improve noise immunity. Refer to Chapter 5 Interrupts.
NOTE
If the voltage level applied to the IRQ
/VPP pin exceeds VDD, it may affect
the MCU’s mode of operation. See Chapter 3 Operating Modes.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 17
General Description
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
18 Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The MC68HC705P6A utilizes 13 address lines to access an internal memory space covering 8 Kbytes.
This memory space is divided into I/O, RAM, ROM, and EPROM areas.
2.2 User Mode Memory Map
When the MC68HC705P6A is in the user mode, the 32 bytes of I/O, 176 bytes of RAM, 4608 bytes of user
EPROM, 48 bytes of user page zero EPROM, 239 bytes of bootloader ROM, and 16 bytes of user vectors
EPROM are all active as shown in Figure 2-1.
2.3 Bootloader Mode Memory Map
Memory space is identical to the user mode. See Figure 2-1.
2.4 Input/Output and Control Registers
Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers at locations $0000–$001F.
Reading unimplemented bits will return unknown states, and writing unimplemented bits will be ignored.
2.5 RAM
The user RAM consists of 176 bytes (including the stack) at locations $0050 through $00FF. The stack
begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0.
NOTE
Using the stack area for data storage or temporary work locations requires
care to prevent it from being overwritten due to stacking from an interrupt
or subroutine call.
2.6 EPROM/ROM
There are 4608 bytes of user EPROM at locations $0100 through $12FF, plus 48 bytes in user page zero
locations $0020 through $004F, and 16 additional bytes for user vectors at locations $1FF0 through
$1FFF. The bootloader ROM and vectors are at locations $1F01 through $1FEF.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 19
Memory
$0000
$001F
$0020
$004F
$0050
$00BF
$00C0
$00FF 0255
$0100
$12FF
$1300
$1EFE 7934
$1EFF
$1F00
$1F01 7937
$1FEF
$1FF0
$1FFF
MASK OPTION REGISTERS
AND VECTORS 239 BYTES
USER VECTORS EPROM
I/O
32 BYTES
USER EPROM
48 BYTES
INTERNAL RAM
176 BYTES
STACK
64 BYTES
USER EPROM
4608 BYTES
UNIMPLEMENTED
3071 BYTES
BOOTLOADER ROM
16 BYTES
0000
0031
0032
0079
0080
0191
0192
0256
4863
4864
7935
7936
8175
8176
8191
I/O REGISTERS
SEE Figure 2-2
COP CLEAR REGISTER
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
IRQ VECTOR (HIGH BYTE)
IRQ VECTOR (LOW BYTE)
SWI VECTOR (HIGH BYTE)
SWI VECTOR (LOW BYTE)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
(1)
$0000
$001F
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
Note 1. Writing zero to bit 0 of $1FF0 clears the COP watchdog timer. Reading $1FF0 returns user EPROM data.
Figure 2-1. MC68HC705P6A User Mode Memory Map
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
20 Freescale Semiconductor
PORT A DATA REGISTER $0000
PORT B DATA REGISTER $0001
PORT C DATA REGISTER $0002
PORT D DATA REGISTER $0003
PORT A DATA DIRECTION REGISTER $0004
PORT B DATA DIRECTION REGISTER $0005
PORT C DATA DIRECTION REGISTER $0006
PORT D DATA DIRECTION REGISTER $0007
UNIMPLEMENTED $0008
UMIMPLEMENTED $0009
SIOP CONTROL REGISTER $000A
SIOP STATUS REGISTER $000B
SIOP DATA REGISTER $000C
RESERVED $000D
UNIMPLEMENTED $000E
EPROM/ROM
UNIMPLEMENTED $000F
UNIMPLEMENTED $0010
UNIMPLEMENTED $0011
TIMER CONTROL REGISTER $0012
TIMER STATUS REGISTER $0013
INPUT CAPTURE MSB $0015
INPUT CAPTURE LSB $0016
OUTPUT COMPARE MSB $0017
OUTPUT COMPARE LSB $0017
TIMER MSB $0018
TIMER LSB $0019
ALTERNATE COUNTER MSB $001A
ALTERNATE COUNTER LSB $001B
EPROM PROGRAMMING REGISTER $001C
A/D CONVERTER DATA REGISTER $001D
A/D CONVERTER CONTROL AND STATUS REGISTER $001E
RESERVED $001F
Figure 2-2. MC68HC705P6A I/O and Control
Registers Memory Map
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 21
Memory
Addr. Register Name Bit 7654321Bit 0
Port A Data Register
$0000
Port B Data Register
$0001
Port C Data Register
$0002
Port D Data Register
$0003
Port A Data Direction
$0004
Port B Data Direction
$0005
Port C Data Direction
$0006
Port D Data Direction
$0007
$0008 Unimplemented
(PORTA)
See page 37.
(PORTB)
See page 38.
(PORTC)
See page 38.
(PORTD)
See page 39.
Register (DDRA)
See page 37.
Register (DDRB)
See page 38.
Register (DDRC)
See page 38.
Register (DDRD)
See page 39.
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read: PD7 0
Write:
Reset: Unaffected by reset
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0 0
Write:
Reset:00000000
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PB7 PB6 PB5
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PD5
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
DDRD5
00000
10000
11111
00000
$0009 Unimplemented
$000A
$000B
$000C
SIOP Control Register
(SCR)
See page 43.
SIOP Status Register
(SSR)
See page 44.
SIOP Data Register
(SDR)
See page 44.
Read: 0
Write:
Reset:00000000
Read:SPIFDCOL000000
Write:
Reset:00000000
Read:
Write:
Reset: Unaffected by reset
SDR7 SDR6 SDR5 SDR4 SDR3 SSDR2 SDR1 SDR0
SPE
= Unimplemented R = Reserved U = Undetermined
0
MSTR
0000
Figure 2-3. I/O and Control Register Summary (Sheet 1 of 3)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
22 Freescale Semiconductor
EPROM/ROM
Addr. Register Name Bit 7654321Bit 0
$000DReserved for Test RRRRRRRR
$000E Unimplemented
$000F Unimplemented
$0010 Unimplemented
$0011 Unimplemented
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
Timer Control Register
(TCR)
See page 47.
Timer Status Register
(TSR)
See page 48.
Input Capture Register
MSB (ICRH)
See page 50.
Input Capture Register
LSB (ICRL)
See page 50.
Output Compare
Register MSB (OCRH)
See page 50.
Output Compare
Register LSB (OCRL)
See page 50.
Timer Register MSB
(TRH)
See page 49.
Timer Register LSB (TRL)
See page 49.
Alternate Timer
Register MSB (ATRH)
See page 49.
Read:
Write:
Reset:000000U0
Read:ICFOCFTOF00000
Write:
Reset:UUU00000
Read: ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
Write:
Reset: Unaffected by reset
Read: ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset
Read: TRH7 TRH6 TRH5 TRH4 TRH3 TRH2 TRH1 TRH0
Write:
Reset:11111111
Read: TRL7 TRL6 TRL5 TRL4 TRL3 TRL2 TRL1 TRL0
Write:
Reset:11111100
Read: ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
Write:
Reset:11111111
ICIE OCIE TOIE
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
= Unimplemented R = Reserved U = Undetermined
000
IEDG OLVL
Figure 2-3. I/O and Control Register Summary (Sheet 2 of 3)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 23
Memory
Addr. Register Name Bit 7654321Bit 0
Alternate Timer
$001B
$001C
$001D
$001E
$001FReserved for Test RRRRRRRR
Register LSB (ATRL)
See page 49.
EPROM Programming
Register (EPROG)
See page 58.
A/D Conversion Value
Data Register (ADC)
See page 55.
A/D Status and Control
Register (ADSC)
See page 54.
Read: ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
Write:
Reset:11111100
Read:00000
Write:
Reset:00000000
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Unaffected by reset
Read: CC
Write:
Reset:00000000
ADRC ADON
= Unimplemented R = Reserved U = Undetermined
00
ELAT
CH2 CH1 CH0
0
EPGM
Figure 2-3. I/O and Control Register Summary (Sheet 3 of 3)
2.7 Mask Option Register
The mask option register (MOR) is a pair of EPROM bytes located at $1EFF and $1F00. It controls the
programmable options on the MC68HC705P6A. See Chapter 11 Mask Option Register (MOR) for
additional information.
$1EFFBit 7654321Bit 0
Read:
Write:
Erased State:00000000
$1F00Bit 7654321Bit 0
Read:
Write:
Erased State:00000000
PA7PU PA6PU PA5PU PA4PU PA3PU PA2PU PA1PU PA0PU
SECURE SWAIT SPR1 SPR0 LSBF LEVEL COP
= Unimplemented
Figure 2-4. Mask Option Register (MOR)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
24 Freescale Semiconductor
Computer Operating Properly (COP) Clear Register
2.8 Computer Operating Properly (COP) Clear Register
The computer operating properly (COP) watchdog timer is located at address $1FF0. Writing a logical 0
to bit zero of this location will clear the COP watchdog counter as described in 4.3.2 Computer Operating
Properly (COP) Reset.
$1FF0Bit 7654321Bit 0
Read:00000000
Write:
Reset:00000000
= Unimplemented
Figure 2-5. COP Watchdog Timer Location
COPR
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 25
Memory
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
26 Freescale Semiconductor
Chapter 3
Operating Modes
3.1 Introduction
The MC68HC705P6A has two modes of operation that affect the pinout and architecture of the MCU:
user mode and bootloader mode. The user mode is normally used for the application and the bootloader
mode is used for programming the EPROM. The conditions required to enter each mode are shown in
Table 3-1. The mode of operation is determined by the voltages on the IRQ
the rising edge of the external RESET
pin.
Table 3-1. Operating Mode Conditions After Reset
/V
V
IRQ
SS
to V
PP
DD
PD7/TCAP Mode
VSS to V
DD
RESET Pin
/VPP and PD7/TCAP pins on
Single chip
V
PP
V
DD
Bootloader
The mode of operation is also determined whenever the internal computer operating properly (COP)
watchdog timer resets the MCU. When the COP timer expires, the voltage applied to the IRQ
/VPP pin
controls the mode of operation while the voltage applied to PD7/TCAP is ignored. The voltage applied to
PD7/TCAP during the last rising edge on RESET
is stored in a latch and used to determine the mode of
operation when the COP watchdog timer resets the MCU.
3.2 User Mode
The user mode allows the MCU to function as a self-contained microcontroller, with maximum use of the
pins for on-chip peripheral functions. All address and data activity occurs within the MCU and are not
available externally. User mode is entered on the rising edge of RESET
if the IRQ/VPP pin is within the
normal operating voltage range. The pinout for the user mode is shown in Figure 3-1.
In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared with the analog-to-digital (A/D)
subsystem, one 3-bit I/O port shared with the serial input/output port (SIOP), and a 3-bit port shared with
the 16-bit timer subsystem, which includes one general-purpose I/O pin.
3.3 Bootloader Mode
The bootloader mode provides a means to program the user EPROM from an external memory device or
host computer. This mode is entered on the rising edge of RESET
V
is applied to the PD7/TCAP pin. The user code in the external memory device must have data located
DD
if VPP is applied to the IRQ/V
in the same address space it will occupy in the internal MCU EPROM, including the mask option register
(MOR) at $1EFF and $1F00.
pin and
PP
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 27
Operating Modes
RESET
IRQ/V
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
SDO/PB5
SDI/PB6
SCK/PB7
V
1
PP
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
28
V
DD
27
OSC1
26
OSC2
25
PD7/TCAP
24
TCMP
23
PD5
22
PC0
21
PC1
20
PC2
19
PC3/AD3
18
PC4/AD2
17
PC5/AD1
16
PC6/AD0
15
PC7/V
REFH
Figure 3-1. User Mode Pinout
3.4 Low-Power Modes
The MC68HC705P6A is capable of running in a low-power mode in each of its configurations. The WAIT
and STOP instructions provide three modes that reduce the power required for the MCU by stopping
various internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR is used to modify the
behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes
is shown in Figure 3-2.
3.4.1 STOP Instruction
The STOP instruction can result in one of two modes of operation depending on the state of the SWAIT
bit in the MOR. If the SWAIT bit is clear, the STOP instruction will behave like a normal STOP instruction
in the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit in the MOR is set, the STOP
instruction will behave like a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.
3.4.1.1 Stop Mode
Execution of the STOP instruction when the SWAIT bit in the MOR is clear places the MCU in its lowest
power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register so that the IRQ
remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of stop mode only by an IRQ
RESET
. When exiting stop mode, the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.
Execution of the STOP instruction when the SWAIT bit in the MOR is clear
will cause the oscillator to stop, and, therefore, disable the COP watchdog
timer. To avoid turning off the COP watchdog timer, stop mode should be
changed to halt mode by setting the SWAIT bit in the MOR. See 3.5 COP
Watchdog Timer Considerations for additional information.
external interrupt is enabled. All other registers and memory
external interrupt or an externally generated
NOTE
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
28 Freescale Semiconductor
Low-Power Modes
STOP
MOR
SWAIT
BIT SET?
N
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET
?
N
IRQ
EXTERNAL
INTERRUPT?
N
Y
Y
Y
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
END
OF STABILIZATION
DELAY?
N
INTERNAL PROCESSOR CLOCK
Y
RESTART
HALT
EXTERNAL OSCILLATOR ACTIVE
INTERNAL TIMER CLOCK ACTIVE
Y
Y
Y
Y
AND
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET
?
N
IRQ
EXTERNAL
INTERRUPT?
N
TIMER
INTERNAL
INTERRUPT?
N
COP
INTERNAL
RESET?
N
WAIT
EXTERNAL OSCILLATOR ACTIVE
INTERNAL TIMER CLOCK ACTIVE
Y
Y
Y
Y
AND
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET
?
N
IRQ
EXTERNAL
INTERRUPT?
N
TIMER
INTERNAL
INTERRUPT?
N
COP
INTERNAL
RESET?
N
1. FETCH RESET VECTOR
2. SERVICE INTERRUPT
OR
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 3-2. STOP/WAIT Flowcharts
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor 29
Operating Modes
3.4.1.2 Halt Mode
NOTE
Halt mode is NOT designed for intentional use. Halt mode is only provided
to keep the COP watchdog timer active in the event a STOP instruction is
executed inadvertently. This mode of operation is usually achieved by
invoking wait mode.
Execution of the STOP instruction when the SWAIT bit in the MOR is set places the MCU in this low-power
mode. Halt mode consumes the same amount of power as wait mode (both halt and wait modes consume
more power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated
from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register, enabling the IRQ
external interrupt. All other registers, memory, and input/output
lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt mode and resume normal
operation. The halt mode also can be exited when an IRQ
external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay of one to 4064 internal clock
cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization
delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode).
3.4.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which consumes more power than stop mode.
In wait mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated
from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ
external interrupt. All other registers, memory, and input/output
lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal
operation. The 16-bit timer may be used to generate a periodic exit from wait mode. Wait mode may also
be exited when an IRQ
external interrupt or RESET occurs.
3.5 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when the COP bit in the MOR is set.
Executing the STOP instruction when the SWAIT bit in the MOR is clear will cause the COP to be
disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode (set
bit SWAIT in the MOR) if the COP watchdog timer is required to function at all times.
Furthermore, it is recommended that the COP watchdog timer be disabled for applications that will use
the wait mode for time periods that will exceed the COP timeout period.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
30 Freescale Semiconductor
Loading...