Freescale MC68HC11F1 User Manual
Freescale Semiconductor
© Freescale Semiconductor, Inc., 2004. All rights reserved.
HC11
MC68HC11F1
Technical Data
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TABLE OF CONTENTS
Paragraph Title Page
SECTION 1INTRODUCTION
1.1 Features ....................................................................................................1-1
SECTION 2 PIN DESCRIPTIONS
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2.1 V
2.2 Reset (RESET
DD
and V
..............................................................................................2-2
SS
) ..........................................................................................2-3
2.3 E-Clock Output (E) ....................................................................................2-3
2.4 Crystal Driver and External Clock Input (XTAL, EXTAL) ...........................2-3
2.5 Four Times E-Clock Frequency Output (4XOUT) .....................................2-5
2.6 Interrupt Request (IRQ
2.7 Non-Maskable Interrupt (XIRQ
2.8 MODA and MODB (MODA/LIR
2.9 V
RH
2.10 R/W
and V
...........................................................................................................2-6
.............................................................................................. 2-6
RL
) ............................................................................. 2-5
) .................................................................2-5
and MODB/V
) ..................................2-6
STBY
2.11 Port Signals ...............................................................................................2-6
2.11.1 Port A ................................................................................................2-7
2.11.2 Port B ................................................................................................2-8
2.11.3 Port C ................................................................................................2-8
2.11.4 Port D ................................................................................................2-8
2.11.5 Port E ................................................................................................2-9
2.11.6 Port F .................................................................................................2-9
2.11.7 Port G ................................................................................................2-9
SECTION 3 CENTRAL PROCESSING UNIT
3.1 CPU Registers ...........................................................................................3-1
3.1.1 Accumulators A, B, and D .................................................................3-2
3.1.2 Index Register X (IX) .........................................................................3-3
3.1.3 Index Register Y (IY) .........................................................................3-3
3.1.4 Stack Pointer (SP) .............................................................................3-3
3.1.5 Program Counter (PC) ......................................................................3-5
3.1.6 Condition Code Register (CCR) ........................................................3-5
3.1.6.1 Carry/Borrow (C) .......................................................................3-5
3.1.6.2 Overflow (V) ..............................................................................3-5
3.1.6.3 Zero (Z) .....................................................................................3-6
3.1.6.4 Negative (N) ..............................................................................3-6
3.1.6.5 Interrupt Mask (I) .......................................................................3-6
3.1.6.6 Half Carry (H) ............................................................................3-6
3.1.6.7 X Interrupt Mask (X) ..................................................................3-6
3.1.6.8 Stop Disable (S) ........................................................................3-7
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3.2 Data Types ................................................................................................3-7
3.3 Opcodes and Operands ............................................................................3-7
3.4 Addressing Modes .....................................................................................3-7
3.4.1 Immediate ..........................................................................................3-7
3.4.2 Direct ................................................................................................. 3-8
3.4.3 Extended ...........................................................................................3-8
3.4.4 Indexed ..............................................................................................3-8
3.4.5 Inherent .............................................................................................3-8
3.4.6 Relative .............................................................................................3-8
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3.5 Instruction Set ...........................................................................................3-8
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SECTION 4OPERATING MODES AND ON-CHIP MEMORY
4.1 Operating Modes .......................................................................................4-1
4.1.1 Single-Chip Operating Mode .............................................................4-1
4.1.2 Expanded Operating Mode ...............................................................4-1
4.1.3 Special Test Mode .............................................................................4-1
4.1.4 Special Bootstrap Mode ....................................................................4-1
4.2 On-Chip Memory .......................................................................................4-2
4.2.1 Mapping Allocations ..........................................................................4-2
4.2.2 Memory Map .....................................................................................4-3
4.2.2.1 RAM ..........................................................................................4-3
4.2.2.2 Bootloader ROM .......................................................................4-4
4.2.2.3 EEPROM ...................................................................................4-4
4.2.3 Registers ...........................................................................................4-4
4.3 System Initialization ...................................................................................4-6
4.3.1 Mode Selection ..................................................................................4-7
4.3.1.1 HPRIO Register ........................................................................4-8
4.3.2 Initialization ........................................................................................4-9
4.3.2.1 CONFIG Register ......................................................................4-9
4.3.2.2 INIT Register ...........................................................................4-10
4.3.2.3 OPTION Register ....................................................................4-11
4.3.2.4 OPT2 Register ........................................................................4-12
4.3.2.5 Block Protect Register (BPROT) .............................................4-13
4.4 EEPROM and CONFIG Register ............................................................4-14
4.4.1 EEPROM ......................................................................................... 4-14
4.4.1.1 EEPROM Programming ..........................................................4-14
4.4.1.2 EEPROM Bulk Erase ..............................................................4-15
4.4.1.3 EEPROM Row Erase ..............................................................4-15
4.4.1.4 EEPROM Byte Erase ..............................................................4-16
4.4.2 PPROG EEPROM Programming Control Register .........................4-16
4.4.3 CONFIG Register Programming .....................................................4-17
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TABLE OF CONTENTS
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4.5 Chip Selects ............................................................................................4-18
4.5.1 Program Chip Select .......................................................................4-18
4.5.2 I/O Chip Selects ..............................................................................4-18
4.5.3 General-Purpose Chip Select ..........................................................4-19
SECTION 5 RESETS AND INTERRUPTS
5.1 Resets .......................................................................................................5-1
5.1.1 Power-On Reset ................................................................................5-1
5.1.2 External Reset (RESET
5.1.3 Computer Operating Properly (COP) Reset ......................................5-2
5.1.4 Clock Monitor Reset ..........................................................................5-2
5.1.5 OPTION Register ..............................................................................5-3
5.1.6 CONFIG Register ..............................................................................5-4
5.2 Effects of Reset .........................................................................................5-4
5.2.1 Central Processing Unit .....................................................................5-5
5.2.2 Memory Map .....................................................................................5-5
5.2.3 Parallel I/O .........................................................................................5-5
5.2.4 Timer .................................................................................................5-5
5.2.5 Real-Time Interrupt (RTI) ..................................................................5-5
5.2.6 Pulse Accumulator ............................................................................5-6
5.2.7 Computer Operating Properly (COP) ................................................5-6
5.2.8 Serial Communications Interface (SCI) .............................................5-6
5.2.9 Serial Peripheral Interface (SPI) ........................................................5-6
5.2.10 Analog-to-Digital Converter ...............................................................5-6
5.2.11 System ..............................................................................................5-6
5.3 Reset and Interrupt Priority .......................................................................5-6
5.3.1 Highest Priority Interrupt and Miscellaneous Register ......................5-7
5.4 Interrupts ...................................................................................................5-8
5.4.1 Interrupt Recognition and Register Stacking .....................................5-9
5.4.2 Non-Maskable Interrupt Request (XIRQ
5.4.3 Illegal Opcode Trap .........................................................................5-10
5.4.4 Software Interrupt ............................................................................5-11
5.4.5 Maskable Interrupts .........................................................................5-11
5.4.6 Reset and Interrupt Processing .......................................................5-11
5.5 Low Power Operation ..............................................................................5-16
5.5.1 WAIT ...............................................................................................5-17
5.5.2 STOP ...............................................................................................5-17
) ...................................................................5-1
) ........................................5-10
SECTION 6 PARALLEL INPUT/OUTPUT
6.1 Port A ........................................................................................................6-1
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Paragraph Title Page
6.2 Port B ........................................................................................................6-2
6.3 Port C ........................................................................................................6-2
6.4 Port D ........................................................................................................6-3
6.5 Port E ........................................................................................................6-4
6.6 Port F .........................................................................................................6-4
6.7 Port G ........................................................................................................6-5
6.8 System Configuration Options 2 ................................................................6-5
SECTION 7 SERIAL COMMUNICATIONS INTERFACE
7.1 Data Format ..............................................................................................7-1
7.2 Transmit Operation ....................................................................................7-1
7.3 Receive Operation .....................................................................................7-2
7.4 Wakeup Feature ........................................................................................7-4
7.4.1 Idle-Line Wakeup ..............................................................................7-4
7.4.2 Address-Mark Wakeup ......................................................................7-4
7.5 SCI Error Detection ...................................................................................7-5
7.6 SCI Registers ............................................................................................7-5
7.6.1 Serial Communications Data Register ..............................................7-5
7.6.2 Serial Communications Control Register 1 .......................................7-5
7.6.3 Serial Communications Control Register 2 .......................................7-6
7.6.4 Serial Communication Status Register ..............................................7-7
7.6.5 Baud Rate Register ...........................................................................7-8
7.7 Status Flags and Interrupts .....................................................................7-10
7.7.1 Receiver Flags ................................................................................7-11
SECTION 8 SERIAL PERIPHERAL INTERFACE
8.1 Functional Description ...............................................................................8-1
8.2 SPI Transfer Formats ................................................................................8-2
8.2.1 Clock Phase and Polarity Controls ....................................................8-3
8.3 SPI Signals ................................................................................................8-3
8.3.1 Master In Slave Out ...........................................................................8-4
8.3.2 Master Out Slave In ...........................................................................8-4
8.3.3 Serial Clock .......................................................................................8-4
8.3.4 Slave Select ......................................................................................8-4
8.4 SPI System Errors .....................................................................................8-4
8.5 SPI Registers ............................................................................................8-5
8.5.1 Serial Peripheral Control ...................................................................8-5
8.5.2 Serial Peripheral Status .....................................................................8-7
8.5.3 Serial Peripheral Data Register .........................................................8-7
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TABLE OF CONTENTS
(Continued)
Paragraph Title Page
SECTION 9 TIMING SYSTEM
9.1 Timer Structure ..........................................................................................9-3
9.2 Input Capture .............................................................................................9-5
9.2.1 Timer Control Register 2 ...................................................................9-5
9.2.2 Timer Input Capture Registers ..........................................................9-6
9.2.3 Timer Input Capture 4/Output Compare 5 Register ..........................9-6
9.3 Output Compare ........................................................................................9-6
9.3.1 Timer Output Compare Registers .....................................................9-7
9.3.2 Timer Compare Force Register .........................................................9-8
9.3.3 Output Compare Mask Registers ......................................................9-8
9.3.4 Output Compare Data Register .........................................................9-9
9.3.5 Timer Counter Register .....................................................................9-9
9.3.6 Timer Control Register 1 ...................................................................9-9
9.3.7 Timer Interrupt Mask Register 1 ......................................................9-10
9.3.8 Timer Interrupt Flag Register 1 .......................................................9-11
9.3.9 Timer Interrupt Mask Register 2 ......................................................9-11
9.3.10 Timer Interrupt Flag Register 2 .......................................................9-12
9.4 Real-Time Interrupt .................................................................................9-12
9.4.1 Timer Interrupt Mask Register 2 ......................................................9-13
9.4.2 Timer Interrupt Flag Register 2 .......................................................9-14
9.4.3 Pulse Accumulator Control Register ...............................................9-14
9.5 Computer Operating Properly Watchdog Function .................................9-15
9.6 Pulse Accumulator ..................................................................................9-15
9.6.1 Pulse Accumulator Control Register ...............................................9-16
9.6.2 Pulse Accumulator Count Register .................................................9-17
9.6.3 Pulse Accumulator Status and Interrupt Bits ...................................9-18
SECTION 10 ANALOG-TO-DIGITAL CONVERTER
10.1 Overview .................................................................................................10-1
10.1.1 Multiplexer ....................................................................................... 10-1
10.1.2 Analog Converter ............................................................................10-3
10.1.3 Digital Control ..................................................................................10-3
10.1.4 Result Registers ..............................................................................10-3
10.1.5 A/D Converter Clocks ......................................................................10-4
10.1.6 Conversion Sequence .....................................................................10-4
10.2 A/D Converter Power-Up and Clock Select .............................................10-5
10.3 Conversion Process ................................................................................10-5
10.4 Channel Assignments .............................................................................10-6
10.5 Single-Channel Operation .......................................................................10-6
10.6 Multiple-Channel Operation .....................................................................10-6
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10.7 Operation in STOP and WAIT Modes ....................................................10-7
10.8 A/D Control/Status Registers ..................................................................10-7
10.9 A/D Converter Result Registers ..............................................................10-8
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX BMECHANICAL DATA AND ORDERING INFORMATION
B.1 Pin Assignments ....................................................................................... B-1
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B.2 Package Dimensions ................................................................................ B-2
B.3 Ordering Information ................................................................................ B-3
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APPENDIX CDEVELOPMENT SUPPORT
C.1 MC68HC11F1 Development Tools .......................................................... C-1
C.2 MC68HC11EVS — Evaluation System .................................................... C-1
C.3 M68MMDS11 — Modular Development System for M68HC11 Devices . C-1
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LIST OF ILLUSTRATIONS
Figure Title Page
1-1 MC68HC11F1 Block Diagram ........................................................................ 1-2
2-1 Pin Assignments for MC68HC11F1 68-Pin PLCC ......................................... 2-1
2-2 Pin Assignments for MC68HC11F1 80-Pin QFP ............................................2-2
2-3 External Reset Circuit .....................................................................................2-3
2-4 Common Crystal Connections ........................................................................2-4
2-5 External Oscillator Connections ..................................................................... 2-4
2-6 One Crystal Driving Two MCUs ..................................................................... 2-4
2-7 4XOUT Signal Driving a Second MCU ........................................................... 2-5
3-1 Programming Model ....................................................................................... 3-2
3-2 Stacking Operations ....................................................................................... 3-4
4-1 MC68HC11F1 Memory Map .......................................................................... 4-3
4-2 RAM Standby MODB/V
4-3 Address Map for I/O and Program Chip Selects .......................................... 4-19
4-4 Address Map for General-Purpose Chip Select ........................................... 4-20
5-1 Processing Flow Out of Reset (1 of 2) ......................................................... 5-12
5-2 Processing Flow Out of Reset (2 of 2) ......................................................... 5-13
5-3 Interrupt Priority Resolution (1 of 2) ............................................................. 5-14
5-4 Interrupt Priority Resolution (2 of 2) ............................................................. 5-15
5-5 Interrupt Source Resolution Within SCI ........................................................5-16
7-1 SCI Transmitter Block Diagram ...................................................................... 7-2
7-2 SCI Receiver Block Diagram .......................................................................... 7-3
7-3 SCI Baud Rate Generator Block Diagram .................................................... 7-10
7-4 Interrupt Source Resolution Within SCI ........................................................7-12
8-1 SPI Block Diagram ......................................................................................... 8-2
8-2 SPI Transfer Format ....................................................................................... 8-3
9-1 Timer Clock Divider Chains ............................................................................ 9-2
9-2 Capture/Compare Block Diagram .................................................................. 9-4
9-3 Pulse Accumulator ....................................................................................... 9-16
10-1 A/D Converter Block Diagram ...................................................................... 10-2
10-2 Electrical Model of an A/D Input Pin (Sample Mode) ................................... 10-3
10-3 A/D Conversion Sequence ........................................................................... 10-4
A-1 Test Methods ..................................................................................................A-4
A-2 Timer Inputs ...................................................................................................A-5
A-3 POR External Reset Timing Diagram .............................................................A-6
A-4 STOP Recovery Timing Diagram ...................................................................A-7
A-5 WAIT Recovery from Interrupt Timing Diagram .............................................A-8
A-6 Interrupt Timing Diagram ................................................................................A-9
A-7 Port Read Timing Diagram ...........................................................................A-10
A-8 Port Write Timing Diagram ...........................................................................A-10
A-9 Expansion Bus Timing ..................................................................................A-13
A-10 SPI Master Timing (CPHA = 0) ....................................................................A-15
Connections ..................................................... 4-4
STBY
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LIST OF ILLUSTRATIONS
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Figure Title Page
A-11 SPI Master Timing (CPHA = 1) ....................................................................A-15
A-12 SPI Slave Timing (CPHA = 0) ......................................................................A-16
A-13 SPI Slave Timing (CPHA = 1) ......................................................................A-16
B-1 MC68HC11F1 68-Pin PLCC ..........................................................................B-1
B-2 MC68HC11F1 80-Pin Quad Flat Pack ...........................................................B-2
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LIST OF TABLES
Table Title Page
2-1 Port Signal Functions...................................................................................... 2-7
3-1 Reset Vector Comparison............................................................................... 3-5
3-2 Instruction Set................................................................................................. 3-9
4-1 Register and Control Bit Assignments.............................................................4-5
4-2 Write Access Limited Registers.......................................................................4-7
4-3 Hardware Mode Select Summary................................................................... 4-7
4-4 EEPROM Mapping........................................................................................ 4-10
4-5 RAM and Register Mapping.......................................................................... 4-11
4-6 EEPROM Block Protection............................................................................ 4-14
4-7 EEPROM Erase Mode Control...................................................................... 4-17
4-8 Chip Select Clock Stretch Control................................................................. 4-20
4-9 Program Chip Select Size Control.................................................................4-21
4-10 General-Purpose Chip Select Starting Address............................................ 4-22
4-11 General-Purpose Chip Select Size Control................................................... 4-22
4-12 Chip Select Control Parameter Summary..................................................... 4-23
5-1 COP Timer Rate Selection.............................................................................. 5-2
5-2 Reset Cause, Operating Mode, and Reset Vector.......................................... 5-4
5-3 Highest Priority Interrupt Selection.................................................................. 5-8
5-4 Interrupt and Reset Vector Assignments.........................................................5-9
5-5 Stacking Order on Entry to Interrupts............................................................ 5-10
6-1 I/O Port Configuration......................................................................................6-1
7-1 Baud Rate Prescaler Selection....................................................................... 7-8
7-2 Baud Rate Selection........................................................................................7-9
8-1 SPI Clock Rates.............................................................................................. 8-6
9-1 Timer Summary............................................................................................... 9-3
9-2 Timer Output Compare Configuration........................................................... 9-10
9-3 Timer Prescaler Selection............................................................................. 9-12
9-4 RTI Rate Selection........................................................................................ 9-13
9-5 Pulse Accumulator Timing.............................................................................9-16
9-6 Pulse Accumulator Edge Detection Control.................................................. 9-17
10-1 A/D Converter Channel Assignments............................................................ 10-6
10-2 A/D Converter Channel Selection ................................................................. 10-8
A-1 Maximum Ratings............................................................................................A-1
A-2 Thermal Characteristics ..................................................................................A-2
A-3 DC Electrical Characteristics...........................................................................A-3
A-4 Control Timing.................................................................................................A-5
A-5 Peripheral Port Timing...................................................................................A-10
A-6 Analog-To-Digital Converter Characteristics.................................................A-11
A-7 Expansion Bus Timing...................................................................................A-12
A-8 Serial Peripheral Interface Timing.................................................................A-14
A-9 EEPROM Characteristics..............................................................................A-17
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LIST OF TABLES
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Table Title Page
B-1 Device Ordering Information ...........................................................................B-3
C-1 MC68HC11F1 Development Tools.................................................................C-1
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SECTION 1INTRODUCTION
The MC68HC11F1 high-performance microcontroller unit (MCU) is an enhanced derivative of the M68HC11 family of microcontrollers and includes many advanced features. This MCU, with a nonmultiplexed expanded bus, is characterized by high speed
and low power consumption. The fully static design allows operation at frequencies
from 4 MHz to dc.
1.1 Features
• M68HC11 Central Processing Unit (CPU)
• Power Saving STOP and WAIT Modes
• 512 Bytes Electrically Erasable Programmable Read-Only Memory (EEPROM)
• 1024 Bytes RAM, Data Retained During Standby
• Nonmultiplexed Address and Data Buses
• Enhanced 16-Bit Timer
• Three Input Capture (IC) Channels
• Four Output Compare (OC) Channels
• One Additional Channel, Selectable as Fourth IC or Fifth OC
• 8-Bit Pulse Accumulator
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog
• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Enhanced Synchronous Serial Peripheral Interface (SPI)
• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter
• Four Chip-Select Signal Outputs with Programmable Clock Stretching
— Two I/O Chip Selects
— One Program Chip Select
— One General-Purpose Chip Select
• Available in 68-Pin Plastic Leaded Chip Carrier (PLCC) and 80-Pin Plastic Quad
Flat Pack (QFP)
Freescale Semiconductor, I
TECHNICAL DATA 1-1
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INTRODUCTION
Freescale Semiconductor, Inc.
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XTAL
EXTAL
4XOUT
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
R/W
PORT E
PORT G
PORT D
IRQ
XIRQ
RESET
MODA/
LIR
MODB/
V
STBY
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
V
RH
V
RL
V
DD
V
SS
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PD5
PD4
PD3
PD2
PD1
PD0
INTERRUPT
LOGIC
E
MODE
CONTROL
A/D
CONVERTER
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
V
RH
V
RL
CHIP
SELECTS
CSPROG
CSGEN
CSIO1
CSIO2
SS
SCK
SPI
MOSI
MISO
TxD
SCI
RxD
PORT G DDR
PORT D DDR
PORT A
PORT A DDR
PORT B
PORT F
PORT C
PORT C DDR
PAI/OC1
OC2/OC1
OC3/OC1
OC4/OC1
OC5/IC4/OC1
IC1
IC2
IC3
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ACCUMULATOR
PULSE
TIMER
SYSTEM
ADDRESS BUS
DATA BUS
R/W
COP
PERIODIC
INTERRUPT
CPU
CLOCK
LOGIC
1024
BYTES
RAM
OSCILLATOR
512
BYTES
EEPROM
Figure 1-1 MC68HC11F1 Block Diagram
1-2 TECHNICAL DATA
For More Information On This Product,
INTRODUCTION
MC68HC11F1
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SECTION 2 PIN DESCRIPTIONS
The MC68HC11F1 MCU is available in a 68-pin plastic leaded chip carrier (PLCC) and
an 80-pin plastic quad flat pack (QFP). Most pins on this MCU serve two or more functions, as described in the following paragraphs.
for the PLCC.
Figure 2-2 shows the pin assignments for the QFP.
STBY
EXTAL
XTAL
4XOUT
PC0/DATA0
8
7
9
PC1/DATA1
PC2/DATA2
PC3/DATA3
PC4/DATA4
PC5/DATA5
PC6/DATA6
PC7/DATA7
RESET
PG7/CSPROG
PG6/CSGEN
PG5/CSIO1
PG4/CSIO2 PB3/ADDR11
XIRQ
IRQ
PG3
PG2
PG1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27282930313233
PG0
PD1/TxD
PD0/RxD
E
R/W
65432
PD4/SCK
PD3/MOSI
PD2/MISO
V
MODB/V
MODA/LIR
1
MC68HC11F1
3435363738
DD
V
PD5/SS
Figure 2-1 shows the pin assignments
SS
RL
VRHV
PE7/AN7
PE3/AN3
PE6/AN6
PE2/AN2
PE5/AN5
PE1/AN1
6768656463
PA7/PAI/OC1
PA5/OC3/OC1
PA6/OC2/OC1
66
39
404142
PA2/IC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
62
PA1/IC2
PA0/IC3
61
60
PE4/AN4
59
PE0/AN0
58
PF0/ADDR0
57
PF1/ADDR1
PF2/ADDR2
56
PF3/ADDR3
55
PF4/ADDR4
54
PF5/ADDR5
53
PF6/ADDR6
52
PF7/ADDR7
51
PB0/ADDR8
50
PB1/ADDR9
49
PB2/ADDR10
48
47
PB4/ADDR12
46
PB5/ADDR13
45
PB6/ADDR14
44
43
PB7/ADDR15
Figure 2-1 Pin Assignments for MC68HC11F1 68-Pin PLCC
TECHNICAL DATA 2-1
For More Information On This Product,
PIN DESCRIPTIONS
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Freescale Semiconductor, I
DD
V
PA6/OC2/OC1
PA7/PAI/OC1
69
313233
SS
RH
V
V
STBY
MODB/V
PD5/SS
PD4/SCK
PD3/MOSI
686766
343536
E
R/W
MODA/LIR
PD0/RxD
PD2/MISO
PD1/TxD
64
65
636261
37
383940
NC
XTAL
EXTAL
PG0
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44 PC2/DATA2
43
42
41
4XOUT
PC0/DATA0
NC
PG1
PG2
PG3
PG4/CSIO2
PG5/CSIO1
PG6/CSGEN
PG7/CSPROG
IRQ
XIRQ
RESET
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC1/DATA1
NC
NC
NC
NC
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0
PE0/AN0
PE4/AN4
NC
PB7/ADDR15
NC
NC
79
78
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21222324252627
NC
PE1/AN1
PA3/OC5/IC4/OC1
PA5/OC3/OC1
PA2/IC1
PE3/AN3
PA4/OC4/OC1
72
MC68HC11F1
282930
RL
V
PE7/AN7
PA1/IC2
PA0/IC3
77767574737071
PE2/AN2NCPE6/AN6
PE5/AN5
Figure 2-2 Pin Assignments for MC68HC11F1 80-Pin QFP
2.1 V
DD and
Power is supplied to the MCU through V
V
SS
V
SS
DD
and V
SS
. V
is the power supply, and
DD
is ground. The MCU operates from a single 5-volt (nominal) power supply. Very
fast signal transitions occur on the MCU pins. The short rise and fall times place high,
short duration current demands on the power supply. To prevent noise problems, provide good power-supply bypassing at the MCU. Also, use bypass capacitors that have
good high-frequency characteristics and situate them as close to the MCU as possible.
Bypass requirements vary, depending on how heavily the MCU pins are loaded.
2-2 TECHNICAL DATA
For More Information On This Product,
PIN DESCRIPTIONS
MC68HC11F1
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2.2 Reset (RESET )
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU
to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The
CPU distinguishes between internal and external reset conditions by sensing whether
the reset pin rises to a logic one in less than two E-clock cycles after a reset has occurred. It is not advisable to connect an external resistor-capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices because the circuit charge time
constant can cause the device to misinterpret the type of reset that occurred. Refer to
SECTION 5 RESETS AND INTERRUPTS for further information.
Figure 2-3 illustrates a reset circuit that uses an external switch. Other circuits can be
used, however, it is important to incorporate a low voltage interrupt (LVI) circuit to prevent operation at insufficient voltage levels which could result in erratic behavior or cor-
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Freescale Semiconductor, I
V
DD
4.7 kΩ
1
TO RESET
OF M68HC11
MANUAL
RESET SWITCH
4.7 kΩ
OPTIONAL POWER-ON DELAY
AND MANUAL RESET SWITCH
V
DD
V
DD
4.7 kΩ
1.0 µF
MC34164
2
IN
RESET
GND
3
MC34064
1
2
IN
RESET
GND
3
Figure 2-3 External Reset Circuit
2.3 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E is
used as a timing reference. The frequency of the E-clock output is one fourth that of
the input frequency at the EXTAL pin. When E-clock output is low, an internal process
is taking place. When it is high, data is being accessed. All clocks, including the E
clock, are halted when the MCU is in STOP mode. The E clock can be turned off in
single-chip modes to reduce the effects of radio frequency interference (RFI). Refer to
SECTION 9 TIMING SYSTEM .
2.4 Crystal Driver and External Clock Input (XTAL, EXTAL)
These two pins provide the interface for either a crystal or a CMOS-compatible clock
to control the internal clock generator circuitry. Either a crystal oscillator or a CMOS
compatible clock can be used. The resulting E-clock rate is the input frequency divided
by four.
TECHNICAL DATA 2-3
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Freescale Semiconductor, Inc.
The XTAL pin is normally left unterminated when an external CMOS compatible clock
is connected to the EXTAL pin. However, a 10 k
to 100 k Ω load resistor connected
from the XTAL output to ground can be used to reduce RFI noise emission.
The XTAL output is normally used to drive a crystal. The XTAL output can be buffered
with a high-impedance buffer, or it can be used to drive the EXTAL input of another
M68HC11 device. Refer to
Figure 2-6 .
In all cases, use caution when designing circuitry associated with the oscillator pins.
Load capacitances shown in the oscillator circuits include all stray layout capacitances. Refer to Figure 2-4, Figure 2-5, and Figure 2-6.
25 pF*
EXTAL
MCU
10M
XTAL
4 x E
CRYSTAL
25 pF*
Values include all stray capacitances.
*
Figure 2-4 Common Crystal Connections
CMOS-COMPATIBLE
EXTERNAL
OSCILLATOR
MCU
EXTAL
XTAL
NC OR
10 k – 100 k
LOAD
Figure 2-5 External Oscillator Connections
Freescale Semiconductor, I
FIRST
MCU
EXTAL
XTAL
10M
25 pF*
4 x E
CRYSTAL
25 pF*
220
NC OR
10 k – 100 k
LOAD
EXTAL
SECOND
MCU
XTAL
Values include all stray capacitances.
*
Figure 2-6 One Crystal Driving Two MCUs
2-4 TECHNICAL DATA
For More Information On This Product,
PIN DESCRIPTIONS
Go to: www.freescale.com
MC68HC11F1
Freescale Semiconductor, Inc.
2.5 Four Times E-Clock Frequency Output (4XOUT)
Although the circuit shown in Figure 2-6 will work for any M68HC11 MCU, the
MC68HC11F1 has an additional clock output that is four times the E-clock frequency.
This output (4XOUT) can be used to directly drive the EXTAL input of another
M68HC11 MCU. Refer to Figure 2-7. The 4XOUT output is enabled after reset and
can be disabled by clearing the CLK4X bit in the OPT2 register.
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Freescale Semiconductor, I
MC68HC11F1
4XOUT
EXTAL
XTAL
OSCILLATOR
CIRCUIT OR
CMOS-COMPATIBLE
CLOCK
NC OR
10 k – 100 k
LOAD
EXTAL
XTAL
SECOND
MCU
Figure 2-7 4XOUT Signal Driving a Second MCU
2.6 Interrupt Request (IRQ
)
The IRQ input provides a means of generating asynchronous interrupt requests for the
CPU. Either falling-edge triggering or low-level triggering is selected by the IRQE bit
in the OPTION register. IRQ
Connect an external pull-up resistor, typically 4.7 kΩ, to V
is always configured for level-sensitive triggering at reset.
when IRQ is used in a
DD
level-sensitive wired-OR configuration. Refer to SECTION 5 RESETS AND INTER-
RUPTS.
2.7 Non-Maskable Interrupt (XIRQ
)
The XIRQ input provides a means of requesting a non-maskable interrupt after reset
initialization. During reset, the X bit in the condition code register (CCR) is set and any
interrupt is masked until MCU software enables it. Because the XIRQ
input is level
sensitive, it can be connected to a multiple-source wired-OR network with an external
pull-up resistor to V
. XIRQ is often used as a power loss detect interrupt.
DD
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be configured for level-sensitive operation if there is more than one source of IRQ
interrupt),
each source must drive the interrupt input with an open-drain type of driver to avoid
contention between outputs. There should be a single pull-up resistor near the MCU
interrupt input pin (typically 4.7 kΩ). There must also be an interlock mechanism at
each interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request. If one or more interrupt sources are
still pending after the MCU services a request, the interrupt line will still be held low
and the MCU will be interrupted again as soon as the interrupt mask bit in the condition
code register (CCR) is cleared (normally upon return from an interrupt). Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
TECHNICAL DATA 2-5
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PIN DESCRIPTIONS
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2.8 MODA and MODB (MODA/LIR and MODB/V
During reset, MODA and MODB select one of the four operating modes. Refer to SEC-
TION 4 OPERATING MODES AND ON-CHIP MEMORY.
After the operating mode has been selected, the LIR
to indicate that execution of an instruction has begun. The LIR pin is configured for
wired-OR operation (only pulls low). A series of E-clock cycles occurs during execution
of each instruction. The LIR
of each instruction (opcode fetch). This output is provided for assistance in program
debugging.
The V
signal unless the difference between the level of V
V
DD
one MOS threshold (about 0.7 volts). When these voltages differ by more than 0.7
volts, the internal 768-byte RAM and part of the reset logic are powered from V
rather than VDD. This allows RAM contents to be retained without V
to the MCU.
until V
2.9 V
2.10 R/W
and V
RH
These pins provide the reference voltage for the analog-to-digital converter. Bypass
capacitors should be used to minimize noise on these signals. Any noise on V
will directly affect A/D accuracy.
V
RL
In expanded and test modes, R/W indicates the direction of transfers on the external
data bus. A logic level one on this pin indicates that a read cycle is in progress. A logic
zero on this pin indicates that a write cycle is in progress and that no external device
should drive the data bus.
The E-clock can be used to enable external devices to drive data onto the data bus
during the second half of a read bus cycle (E clock high). R/W
control the direction of data transfers. R/W
external data bus. R/W
as when a double-byte store occurs.
pin is used to input RAM standby power. The MCU is powered from the
STBY
Reset must be driven low before V
has been restored to a valid level.
DD
RL
signal is asserted (drives low) during the first E-clock cycle
drives low when data is being written to the
will remain low during consecutive data bus write cycles, such
)
STBY
pin provides an open-drain output
and Vdd is greater than
STBY
power applied
DD
is removed and must remain low
DD
can then be used to
STBY
RH
and
2.11 Port Signals
For the MC68HC11F1, 54 pins are arranged into six 8-bit ports: A, B, C, E, F, and G,
and one 6-bit port (D). Each of these seven ports serves a purpose other than I/O, depending on the operating mode or peripheral functions selected. Note that ports B, C,
and F are available for I/O functions only in single-chip and bootstrap modes. The pins
of ports A, C, D, and G are fully bidirectional. Ports B and F are output-only ports. Port
E is an input-only port. Refer to Table 2-1 for details about the 54 port signals’ functions within different operating modes.
2-6 TECHNICAL DATA
For More Information On This Product,
PIN DESCRIPTIONS MC68HC11F1
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Table 2-1 Port Signal Functions
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Port/Bit Single-Chip and
Bootstrap Mode
PA0 PA0/IC3
PA1 PA1/IC2
PA2 PA2/IC1
PA3 PA3/OC5/IC4/OC1
PA4 PA4/OC4/OC1
PA5 PA5/OC3/OC1
PA6 PA6/OC2/OC1
PA7 PA7/PAI/OC1
PB[7:0] PB[7:0] ADDR[15:8]
PC[7:0] PC[7:0] DATA[7:0]
PD0 PD0/RxD
PD1 PD1/TxD
PD2 PD2/MISO
PD3 PD3/MOSI
PD4 PD4/SCK
PD5 PD5/SS
PE[7:0] PE[7:0]/AN[7:0]
PF[7:0] PF[7:0] ADDR[7:0]
PG0 PG0
PG1 PG1
PG2 PG2
PG3 PG3
PG4 PG4 PG4/CSIO2
PG5 PG5 PG5/CSIO1
PG6 PG6 PG6/CSGEN
PG7 PG7 PG7/CSPROG
Expanded and
Special Test Mode
2.11.1 Port A
Port A is an 8-bit general-purpose I/O port with a data register (PORTA) and a data
direction register (DDRA). Port A pins share functions with the 16-bit timer system.
PORTA can be read at any time. Inputs return the pin level; outputs return the pin driver input level. If written, PORTA stores the data in internal latches. It drives the pins
only if they are configured as outputs. Writes to PORTA do not change the pin state
when the pins are configured for timer output compares.
Out of reset, port A pins [7:0] are general-purpose high-impedance inputs. When the
timer functions associated with these pins are disabled, the bits in DDRA govern the
I/O state of the associated pin. For further information, refer to SECTION 6 PARAL-
LEL INPUT/OUTPUT.
NOTE
When using the information about port functions, do not confuse pin
function with the electrical state of the pin at reset. All general-purpose I/O pins configured as inputs at reset are in a high-impedance
state. Port data registers reflect the logic state of the port at reset.
The pin function is mode dependent.
TECHNICAL DATA 2-7
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2.11.2 Port B
Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-purpose output pins (PB[7:0]). In expanded modes, port B pins act as the high-order address lines (ADDR[15:8]) of the address bus.
PORTB can be read at any time. Reads of PORTB return the pin driver input level. If
PORTB is written, the data is stored in internal latches. It drives the pins only in singlechip or bootstrap mode. In expanded operating modes, port B pins are the high-order
address outputs (ADDR[15:8]).
Refer to SECTION 6 PARALLEL INPUT/OUTPUT.
2.11.3 Port C
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Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data
direction register (DDRC). In single-chip modes, port C pins are general-purpose I/O
pins (PC[7:0]). In expanded modes, port C pins are configured as data bus pins (DATA[7:0]).
PORTC can be read at any time. Inputs return the pin level; outputs return the pin driver input level. If PORTC is written, the data is stored in internal latches. It drives the
pins only if they are configured as outputs in single-chip or bootstrap mode. Port C pins
are general-purpose inputs out of reset in single-chip and bootstrap modes. In expanded and test modes, these pins are data bus lines out of reset.
The CWOM control bit in the OPT2 register disables port C’s P-channel output drivers.
Because the N-channel driver is not affected by CWOM, setting CWOM causes port
C to become an open-drain-type output port suitable for wired-OR operation. In wiredOR mode, (PORTC bits are at logic level zero), pins are actively driven low by the Nchannel driver. When a port C bit is at logic level one, the associated pin is in a highimpedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port C can only be configured for wired-OR operation when the MCU is in single-chip or bootstrap modes.
Refer to SECTION 6 PARALLEL INPUT/OUTPUT.
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2.11.4 Port D
Port D, a 6-bit general-purpose I/O port, has a data register (PORTD) and a data direction register (DDRD). The six port D lines (D[5:0]) can be used for general-purpose
I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)
subsystems.
PORTD can be read at any time. Inputs return the pin level; outputs return the pin driver input level. If PORTD is written, the data is stored in internal latches and can be driven only if port D is configured for general-purpose output.
The DWOM control bit in the SPCR register disables port D’s P-channel output drivers.
Because the N-channel driver is not affected by DWOM, setting DWOM causes port
D to become an open-drain-type output port suitable for wired-OR operation. In wired-
2-8 TECHNICAL DATA
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OR mode, (PORTD bits are at logic level zero), pins are actively driven low by the Nchannel driver. When a port D bit is at logic level one, the associated pin is in a highimpedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation in any operating mode.
Refer to SECTION 6 PARALLEL INPUT/OUTPUT, SECTION 7 SERIAL COMMUNI-
CATIONS INTERFACE, and SECTION 8 SERIAL PERIPHERAL INTERFACE.
2.11.5 Port E
Port E is an 8-bit input-only port that is also used as the analog input port for the analog-to-digital converter. Port E pins that are not used for the A/D system can be used
as general-purpose inputs. However, PORTE should not be read during the sample
portion of an A/D conversion sequence.
Refer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.
2.11.6 Port F
Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose
output pins (PF[7:0]). In expanded mode, port F pins act as the low-order address outputs (ADDR[7:0]).
PORTF can be read at any time. Reads of PORTF return the pin driver input level. If
PORTF is written, the data is stored in internal latches. It drives the pins only in singlechip or bootstrap mode. In expanded operating modes, port F pins are the low-order
address outputs (ADDR[7:0]).
Refer to SECTION 6 PARALLEL INPUT/OUTPUT.
2.11.7 Port G
Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are
alternate functions of port G bits [7:4].
PORTG can be read at any time. Inputs return the pin level; outputs return the pin driver input level. If PORTG is written, the data is stored in internal latches. It drives the
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pins only if they are configured as outputs.
The GWOM control bit in the OPT2 register disables port G's P-channel output drivers.
Because the N-channel driver is not affected by GWOM, setting GWOM causes port
G to become an open-drain-type output port suitable for wired-OR operation. In wiredOR mode, (PORTG bits are at logic level zero), pins are actively driven low by the Nchannel driver. When a port G bit is at logic level one, the associated pin is in a highimpedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port G can be configured for wired-OR operation in any operating mode.
Refer to SECTION 6 PARALLEL INPUT/OUTPUT and SECTION 4 OPERATING
MODES AND ON-CHIP MEMORY.
TECHNICAL DATA 2-9
For More Information On This Product,
PIN DESCRIPTIONS
Go to: www.freescale.com
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2-10 TECHNICAL DATA
For More Information On This Product,
PIN DESCRIPTIONS MC68HC11F1
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 3 CENTRAL PROCESSING UNIT
This section presents information on M68HC11 central processing unit (CPU) architecture. Data types, addressing modes, the instruction set, and the extended addressing range required to support this MCU’s memory expansion feature are also included,
as are special operations such as subroutine calls and interrupts.
The CPU is designed to treat all peripheral, I/O, and memory locations identically as
addresses in the 64 Kbyte memory map. This is referred to as memory-mapped I/O.
There are no special instructions for I/O that are separate from those used for memory.
This architecture also allows accessing an operand from an external memory location
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Freescale Semiconductor, I
3.1 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if
they were memory locations. The seven registers, discussed in the following paragraphs, are shown in Figure 3-1.
CENTRAL PROCESSING UNIT
TECHNICAL DATA 3-1
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15
DOUBLE ACCUMULATOR D
CONDITION CODE REGISTER X H I N Z V C
70
70
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
70
S
ACCUMULATOR A
ACCUMULATOR B
A
B
0
D
015
IX
015
IY
015
SP
015
PC
123456
CCR
CARRY
OVERFLOW
ZERO
NEGATIVE
I INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
X INTERRUPT MASK
STOP DISABLE
Figure 3-1 Programming Model
3.1.1 Accumulators A, B, and D
Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two
accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Although most instructions can use accumulators A or B interchangeably, the
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following exceptions apply:
The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents
of 16-bit register X or Y, but there are no equivalent instructions that use A instead of B.
The TAP and TPA instructions transfer data from accumulator A to the condition code
register, or from the condition code register to accumulator A, however, there are no
equivalent instructions that use B rather than A.
The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations, but there is no equivalent BCD instruction to adjust
accumulator B.
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The add, subtract, and compare instructions associated with both A and B (ABA, SBA,
and CBA) only operate in one direction, making it important to plan ahead to ensure
that the correct operand is in the correct accumulator.
3.1.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the 8-bit offset
provided in an instruction to create an effective address. The IX register can also be
used as a counter or as a temporary storage register.
3.1.3 Index Register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that of the IX register. However, most instructions using the IY register require an extra byte of machine
code and an extra cycle of execution time because of the way the opcode map is im-
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plemented. Refer to 3.3 Opcodes and Operands for further information.
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3.1.4 Stack Pointer (SP)
The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the address space and can be any size up to the amount of memory available
in the system. Normally the SP is initialized by one of the first instructions in an application program. The stack is configured as a data structure that grows downward from
high memory to low memory. Each time a new byte is pushed onto the stack, the SP
is decremented. Each time a byte is pulled from the stack, the SP is incremented. At
any given time, the SP holds the 16-bit address of the next free location in the stack.
Figure 3-2 is a summary of SP operations.
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JSR, JUMP TO SUBROUTINE
MAIN PROGRAM
PC
DIRECT
RTN
PC
INDXD,X
RTN
PC
INDXD,Y
RTN
PC
EXTEND
RTN
BSR, BRANCH TO SUBROUTINE
PC
RTN
$9D = JSR
dd
NEXT MAIN INSTR
MAIN PROGRAM
$AD = JSR
ff
NEXT MAIN INSTR
MAIN PROGRAM
$18 = PRE
$AD = JSR
ff
NEXT MAIN INSTR
MAIN PROGRAM
$BD = JSR
hh
NEXT MAIN INSTR
MAIN PROGRAM
$8D = BSR
rr
NEXT MAIN INSTR
RTI, RETURN FROM INTERRUPT
INTERRUPT PROGRAM
PC
STACK
SP-2
SP-1
SP
ll
SP-2
SP-1
SP
RTN
RTN
STACK
RTN
RTN
H
L
SWI, SOFTWARE INTERRUPT
PC
RTN
WAI, WAIT FOR INTERRUPT
PC
H
RTN
L
$3B = RTI
MAIN PROGRAM
$3F = SWI
MAIN PROGRAM
$3E = WAI
SP
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
SP-9
SP-8
SP-7
SP-6
SP-5
SP-4
SP-3
SP-2
SP-1
STACK
CONDITION CODE
ACMLTR B
ACMLTR A
STACK
CONDITION CODE
ACMLTR B
ACMLTR A
INDEX REGISTER (X
INDEX REGISTER (X
INDEX REGISTER (YH)
INDEX REGISTER (Y
RTN
H
RTN
L
)
H
)
L
)
L
RTS, RETURN FROM SUBROUTINE
SUBROUTINE
PC
$39 = RTS
SP
SP+1
SP+2
STACK
RTN
LEGEND:
RTN
RTN
H
RTN
L
dd
ff
hh
ll
rr
Address of next instruction in main program to be
executed upon return from subroutine.
Most significant byte of return address.
Least significant byte of return address.
Shaded cells show stack pointer position after
operation is complete.
8-bit direct address ($0000-$00FF) (high byte
assumed to be $00).
8-bit positive offset $00 (0) to $FF (256) is added
to index.
High-order byte of 16-bit extended address.
Low-order byte of 16-bit extended address.
Signed-relative offset $80 (-128) to $7F (+127)
(offset relative to the address following the
machine code offset byte).
Figure 3-2 Stacking Operations
When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine
(BSR) instruction, the address of the instruction after the JSR or BSR is automatically
pushed onto the stack, least significant byte first. When the subroutine is finished, a
return from subroutine (RTS) instruction is executed. The RTS pulls the previously
stacked return address from the stack, and loads it into the program counter. Execution then continues at this recovered return address.
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When an interrupt is recognized, the current instruction finishes normally, the return
address (the current value in the program counter) is pushed onto the stack, all of the
CPU registers are pushed onto the stack, and execution continues at the address
specified by the vector for the interrupt. At the end of the interrupt service routine, an
RTI instruction is executed. The RTI instruction causes the saved registers to be pulled
off the stack in reverse order. Program execution resumes at the return address.
There are instructions that push and pull the A and B accumulators and the X and Y
index registers. These instructions are often used to preserve program context. For
example, pushing accumulator A onto the stack when entering a subroutine that uses
accumulator A, and then pulling accumulator A off the stack just before leaving the
subroutine, ensures that the contents of a register will be the same after returning from
the subroutine as it was before starting the subroutine.
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3.1.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to
be executed. After reset, the program counter is initialized from one of six possible
vectors, depending on operating mode and the cause of reset.
Table 3-1 Reset Vector Comparison
POR or RESET Pin Clock Monitor COP Watchdog
Normal $FFFE, F $FFFC, D $FFFA, B
Test or Boot $BFFE, F $BFFC, D $BFFA, B
3.1.6 Condition Code Register (CCR)
This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking bits, (I and X) and a stop disable bit (S). In the M68HC11 CPU, condition
codes are automatically updated by most instructions. For example, load accumulator
A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the
N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY),
and transfer/exchange instructions do not affect the condition codes. Refer to Table
3-2, which shows what condition codes are affected by a particular instruction.
3.1.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an
arithmetic operation. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitate
multiple-word shift operations.
3.1.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V
bit is cleared.
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3.1.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is
zero. Otherwise, the Z bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including Z, reflect the results of that subtraction. A
few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags.
For these operations, only = and - conditions can be determined.
3.1.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation is
negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if
its most significant bit (MSB) is a one. A quick way to test whether the contents of a
memory location has the MSB set is to load it into an accumulator and then check the
status of the N bit.
3.1.6.5 Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources. While the I bit is set, interrupts can become pending, but the operation
of the CPU continues uninterrupted until the I bit is cleared. After any reset, the I bit is
set by default and can only be cleared by a software instruction. When an interrupt is
recognized, the I bit is set after the registers are stacked, but before the interrupt vector
is fetched. After the interrupt has been serviced, a return from interrupt instruction is
normally executed, restoring the registers to the values that were present before the
interrupt occurred. Normally, the I bit is zero after a return from interrupt is executed.
Although the I bit can be cleared within an interrupt service routine, “nesting” interrupts
in this way should only be done when there is a clear understanding of latency and of
the arbitration mechanism. Refer to SECTION 5 RESETS AND INTERRUPTS.
3.1.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit
during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry is
used during BCD operations.
3.1.6.7 X Interrupt Mask (X)
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The XIRQ
by default and must be cleared by a software instruction. When an XIRQ
recognized, the X and I bits are set after the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI instruction is
normally executed, causing the registers to be restored to the values that were present
before the interrupt occurred. The X interrupt mask bit is set only by hardware (RESET
or XIRQ acknowledge). X is cleared only by program instruction (TAP, where the associated bit of A is zero; or RTI, where bit 6 of the value loaded into the CCR from the
stack has been cleared). There is no hardware action for clearing X.
3-6 TECHNICAL DATA
mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set
interrupt is
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