Freescale MC68040, MC68040V, MC68LC040, MC68EC040, MC68EC040V User Guide
Freescale Semiconductor, Inc.
µ MOTOROLA
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M68040 User’s Manual
cale Semiconductor,
Frees
Including the
MC68040,
MC68040V,
MC68LC040,
MC68EC040,
and
MC68EC040V
©MOTOROLA INC., 1990
Revised 1992, 1993
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Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
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Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and the are registered trademarks of Motorola, Inc. Motorola, Inc. is an
Equal Opportunity/Affirmative Action Employer.
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©MOTOROLA INC., 1992
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PREFACE
The complete documentation package for the MC68040, MC68040V, MC68LC040,
MC68EC040, and MC68EC040V (collectively called M68040) consists of the
M68040UM/AD,
Programmer’s Reference Manual
operation, and programming of the M68040 32-bit third-generation microprocessors. The
M68040 User’s Manual
. The
M68000 Family Programmer’s Reference Manual
the M68000 family.
The introduction of this manual includes general information concerning the MC68040 and
summarizes the differences between the M68040 member devices. Additionally, three
appendices provide detailed information on how these M68040 dirivatives operate
differently from the MC68040. For detailed information on one of these M68040
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dirivatives, use the following table to determine which appendices to read in conjunction
with the rest of this manual.
, and the M68000PM/AD,
M68040 User’s Manual
contains the complete instruction set for
describes the capabilities,
M68000 Family
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Device Number Appendices
MC68040V Appendix A MC68LC040 and Appendix C MC68040V and MC68EC040V
MC68LC040 Appendix A MC68LC040
MC68EC040 Appendix B MC68EC040
MC68EC040V Appendix B MC68EC040 and Appendix C MC68040V and MC68EC040V
When reading this manual, remember to disregard information concerning floating-point
in reference to the MC68040V and MC68LC040, and to disregard information concerning
floating-point and memory management in reference to the MC68EC040 and
MC68EC040V. The organization of this manual is as follows:
Section 1 Introduction
Section 2 Integer Unit
Section 3 Memory Management Unit (Except MC68EC040 and MC68EC040V)
Section 4 Instruction and Data Caches
Section 5 Signal Description
Section 6 IEEE 1149.1 Test Access Port (JTAG)
Section 7 Bus Operation
Section 8 Exception Processing
Section 9 Floating-Point Unit (MC68040)
Section 10 Instruction Timings
Section 11 MC68040 Electrical and Thermal Characteristics
Section 12 Ordering Information and Mechanical Data
Appendix A MC68LC040
Appendix B MC68EC040
Appendix C MC68040V and MC68EC040V
Appendix D M68000 Family Summary
Appendix E Floating-Point Emulation (M68040FPSP)
Index
iv M68040 USER’S MANUAL MOTOROLA
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TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Introduction
1.1 Differences............................................................................................ 1-1
1.1.1 MC68040V and MC68LC040 ............................................................ 1-1
1.1.2 MC68EC040 and MC68EC040V....................................................... 1-2
1.2 Features................................................................................................ 1-3
1.3 Extensions to the M68000 Family......................................................... 1-3
1.4 Functional Blocks.................................................................................. 1-3
1.5 Processing States ................................................................................. 1-5
1.6 Programming Model.............................................................................. 1-5
1.7 Data Format Summary.......................................................................... 1-9
1.8 Addressing Capabilities Summary........................................................ 1-9
1.9 Notational Conventions......................................................................... 1-11
1.10 Instruction Set Overview....................................................................... 1-13
Section 2
Integer Unit
2.1 Integer Unit Pipeline.............................................................................. 2-1
2.2 Integer Unit Register Description .......................................................... 2-4
2.2.1 Integer Unit User Programming Model.............................................. 2-4
2.2.1.1 Data Registers (D7–D0) ................................................................ 2-4
2.2.1.2 Address Registers (A6–A0) ........................................................... 2-4
2.2.1.3 System Stack Pointer (A7)............................................................. 2-5
2.2.1.4 Program Counter ........................................................................... 2-5
2.2.1.5 Condition Code Register................................................................ 2-5
2.2.2 Integer Unit Supervisor Programming Model .................................... 2-5
2.2.2.1 Interrupt and Master Stack Pointers .............................................. 2-6
2.2.2.2 Status Register .............................................................................. 2-7
2.2.2.3 Vector Base Register..................................................................... 2-7
2.2.2.4 Alternate Function Code Registers................................................ 2-7
2.2.2.5 Cache Control Register ................................................................. 2-8
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 3
Memory Management Unit
(Except MC68EC040 and MC68EC040V)
3.1 Memory Management Programming Model.......................................... 3-3
3.1.1 User and Supervisor Root Pointer Registers..................................... 3-3
3.1.2 Translation Control Register.............................................................. 3-4
3.1.3 Transparent Translation Registers .................................................... 3-5
3.1.4 MMU Status Register ........................................................................ 3-6
3.2 Logical Address Translation.................................................................. 3-7
3.2.1 Translation Tables ............................................................................. 3-7
3.2.2 Descriptors ........................................................................................ 3-12
3.2.2.1 Table Descriptors ........................................................................... 3-12
3.2.2.2 Page Descriptors ........................................................................... 3-13
3.2.2.3 Descriptor Field Definitions ............................................................ 3-13
3.2.3 Translation Table Example................................................................ 3-16
3.2.4 Variations in Translation Table Structure .......................................... 3-16
3.2.4.1 Indirect Action ................................................................................ 3-16
3.2.4.2 Table Sharing Between Tasks....................................................... 3-18
3.2.4.3 Table Paging.................................................................................. 3-19
3.2.4.4 Dynamically Allocated Tables ........................................................ 3-21
3.2.5 Table Search Accesses..................................................................... 3-21
3.2.6 Address Translation Protection ......................................................... 3-23
3.2.6.1 Supervisor and User Translation Tables........................................ 3-23
3.2.6.2 Supervisor Only.............................................................................. 3-23
3.2.6.3 Write Protect .................................................................................. 3-24
3.3 Address Translation Caches ................................................................. 3-26
3.4 Transparent Translation ........................................................................ 3-29
3.5 Address Translation Summary.............................................................. 3-30
3.6 MMU Effect on RSTI and MDIS ............................................................. 3-31
3.6.1 Effect of RSTI on the MMUs .............................................................. 3-31
3.6.2 Effect of MDIS on Address Translation.............................................. 3-31
3.7 MMU Instructions .................................................................................. 3-33
3.7.1 MOVEC ............................................................................................. 3-33
3.7.2 PFLUSH............................................................................................. 3-33
3.7.3 PTEST............................................................................................... 3-33
3.7.4 Register Programming Considerations.............................................. 3-34
MOTOROLA M68040 USER’S MANUAL vii
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 4
Instruction and Data Caches
4.1 Cache Operation................................................................................... 4-2
4.2 Cache Management.............................................................................. 4-5
4.3 Caching Modes ..................................................................................... 4-6
4.3.1 Cachable Accesses........................................................................... 4-6
4.3.1.1 Write-Through Mode ...................................................................... 4-6
4.3.1.2 Copyback Mode............................................................................. 4-6
4.3.2 Cache-Inhibited Accesses................................................................. 4-7
4.3.3 Special Accesses .............................................................................. 4-7
4.4 Cache Protocol ..................................................................................... 4-7
4.4.1 Read Miss ......................................................................................... 4-8
4.4.2 Write Miss.......................................................................................... 4-8
4.4.3 Read Hit ............................................................................................ 4-8
4.4.4 Write Hit............................................................................................. 4-8
4.5 Cache Coherency ................................................................................. 4-9
4.6 Memory Accesses for Cache Maintenance........................................... 4-11
4.6.1 Cache Filling...................................................................................... 4-11
4.6.2 Cache Pushes................................................................................... 4-13
4.7 Cache Operation Summary................................................................... 4-13
4.7.1 Instruction Cache............................................................................... 4-14
4.7.2 Data Cache........................................................................................ 4-15
Section 5
Signal Description
5.1 Address Bus (A31–A0) ......................................................................... 5-4
5.2 Data Bus (D31–D0)............................................................................... 5-5
5.3 Transfer Attribute Signals...................................................................... 5-5
5.3.1 Transfer Type (TT1, TT0).................................................................. 5-5
5.3.2 Transfer Modifier (TM2–TM0) ........................................................... 5-6
5.3.3 Transfer Line Number (TLN1, TLN0)................................................. 5-6
5.3.4 User-Programmable Attributes (UPA1, UPA0).................................. 5-7
5.3.5 Read/Write (R/W) .............................................................................. 5-7
5.3.6 Transfer Size (SIZ1, SIZ0) ................................................................ 5-7
5.3.7 Lock (LOCK) ...................................................................................... 5-7
5.3.8 Lock End (LOCKE) ............................................................................ 5-7
5.3.9 Cache Inhibit Out (CIOUT) ................................................................ 5-8
5.4 Bus Transfer Control Signals ................................................................ 5-8
5.4.1 Transfer Start (TS)............................................................................. 5-8
viii M68040 USER’S MANUAL MOTOROLA
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5.4.2 Transfer in Progress (TIP ) ................................................................. 5-8
5.4.3 Transfer Acknowledge (TA )............................................................... 5-8
5.4.4 Transfer Error Acknowledge (TEA).................................................... 5-8
5.4.5 Transfer Cache Inhibit ( TCI) .............................................................. 5-9
5.4.6 Transfer Burst Inhibit (TBI)................................................................. 5-9
5.5 Snoop Control Signals........................................................................... 5-9
5.5.1 Snoop Control (SC1, SC0) ................................................................ 5-9
5.5.2 Memory Inhibit (MI )............................................................................ 5-9
5.6 Arbitration Signals ................................................................................. 5-10
5.6.1 Bus Request (BR).............................................................................. 5-10
5.6.2 Bus Grant (BG) .................................................................................. 5-10
5.6.3 Bus Busy (BB).................................................................................... 5-10
5.7 Processor Control Signals..................................................................... 5-10
5.7.1 Cache Disable (CDIS)........................................................................ 5-10
5.7.2 Reset In (RSTI) .................................................................................. 5-11
5.7.3 Reset Out (RSTO).............................................................................. 5-11
5.8 Interrupt Control Signals........................................................................ 5-11
5.8.1 Interrupt Priority Level (IPL2–IPL0).................................................... 5-11
5.8.2 Interrupt Pending Status (IPEND) ...................................................... 5-12
5.8.3 Autovector (AVEC)............................................................................. 5-12
5.9 Status And Clock Signals...................................................................... 5-12
5.9.1 Processor Status (PST3–PST0)........................................................ 5-12
5.9.2 Bus Clock (BCLK).............................................................................. 5-14
5.9.3 Processor Clock (PCLK)—Not on MC68040V and MC68EC040V ... 5-14
5.10 MMU Disable (MDIS)—Not on MC68EC040......................................... 5-14
5.11 Data Latch Enable (DLE)—Only on MC68040...................................... 5-14
5.12 Test Signals .......................................................................................... 5-15
5.12.1 Test Clock (TCK) ............................................................................... 5-15
5.12.2 Test Mode Select (TMS).................................................................... 5-15
5.12.3 Test Data In (TDI) .............................................................................. 5-15
5.12.4 Test Data Out (TDO) ......................................................................... 5-15
5.12.5 Test Reset (TRST)—Not on MC68040V and MC68EC040V............. 5-15
5.13 Power Supply Connections................................................................... 5-15
5.14 Signal Summary.................................................................................... 5-16
Section 6
IEEE 1149.1 Test Access Port (JTAG)
6.1 Overview ............................................................................................... 6-2
6.2 Instruction Shift Register ....................................................................... 6-3
6.2.1 EXTEST............................................................................................. 6-3
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TABLE OF CONTENTS (Continued)
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Number Title Number
6.2.2 HIGHZ ............................................................................................... 6-4
6.2.3 SAMPLE/PRELOAD.......................................................................... 6-4
6.2.4 DRVCTL.T......................................................................................... 6-4
6.2.5 SHUTDOWN ..................................................................................... 6-5
6.2.6 PRIVATE ........................................................................................... 6-5
6.2.7 DRVCTL.S......................................................................................... 6-5
6.2.8 BYPASS............................................................................................ 6-6
6.3 Boundary Scan Register....................................................................... 6-6
6.4 Restrictions ........................................................................................... 6-12
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6.5 Disabling The IEEE Standard 1149.1A Operation................................ 6-13
6.6 Motorola M68040 BSDL Description (Version 2.2) ............................... 6-15
6.7 MC68040, MC68LC040, MC68EC040
JTAG Electrical Characteristics .......................................................... 6-21
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Section 7
Bus Operation
7.1 Bus Characteristics ............................................................................... 7-1
7.2 Data Transfer Mechanism..................................................................... 7-3
7.3 Misaligned Operands ............................................................................ 7-6
7.4 Processor Data Transfers ..................................................................... 7-9
7.4.1 Byte, Word, and Long-Word Read Transfers .................................... 7-10
7.4.2 Line Read Transfer............................................................................ 7-12
7.4.3 Byte, Word, and Long-Word Write Transfers .................................... 7-20
7.4.4 Line Write Transfers .......................................................................... 7-22
7.4.5 Read-Modify-Write Transfers (Locked Transfers) ............................. 7-26
7.5 Acknowledge Bus Cycles...................................................................... 7-29
7.5.1 Interrupt Acknowledge Bus Cycles.................................................... 7-29
7.5.1.1 Interrupt Acknowledge BUS Cycle (Terminated Normally)............ 7-31
7.5.1.2 Autovector Interrupt Acknowledge bus Cycle................................ 7-33
7.5.1.3 Spurious Interrupt Acknowledge Bus Cycle................................... 7-34
7.5.2 Breakpoint Interrupt Acknowledge Bus Cycle....................................... 7-35
7.6 Bus Exception Control Cycles............................................................... 7-36
7.6.1 Bus Errors ......................................................................................... 7-37
7.6.2 Retry Operation ................................................................................. 7-41
7.6.3 Double Bus Fault............................................................................... 7-43
7.7 Bus Synchronization ............................................................................. 7-43
7.8 Bus Arbitration And Examples .............................................................. 7-44
7.8.1 Bus Arbitration................................................................................... 7-45
7.8.2 Bus Arbitration Examples .................................................................. 7-52
7.8.2.1 Dual M68040 Fairness Arbitration ................................................. 7-52
7.8.2.2 Dual M68040 Prioritized Arbitration............................................... 7-54
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TABLE OF CONTENTS (Continued)
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7.8.2.3 M68040 Synchronous DMA Arbitration.......................................... 7-55
7.8.2.4 M68040 Asynchronous DMA Arbitration........................................ 7-57
7.9 Bus Snooping Operation ....................................................................... 7-59
7.9.1 Snoop-Inhibited Cycle........................................................................ 7-60
7.9.2 Snoop-Enabled Cycle (No Intervention Required) ............................ 7-61
7.9.3 Snoop Read Cycle (Intervention Required)....................................... 7-63
7.9.4 Snoop Write Cycle (Intervention Required) ....................................... 7-63
7.10 Reset Operation .................................................................................... 7-65
7.11 Special Modes of Operation.................................................................. 7-68
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7.11.1 Output Buffer Impedance Selection................................................... 7-68
7.11.2 Multiplexed Bus Mode ....................................................................... 7-68
7.11.3 Data Latch Enable Mode................................................................... 7-69
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Section 8
Exception Processing
8.1 Exception Processing Overview............................................................ 8-1
8.2 Integer Unit Exceptions......................................................................... 8-5
8.2.1 Access Fault Exception ..................................................................... 8-6
8.2.2 Address Error Exception.................................................................... 8-8
8.2.3 Instruction Trap Exception................................................................. 8-8
8.2.4 Illegal Instruction and Unimplemented Instruction Exceptions .......... 8-9
8.2.5 Privilege Violation Exception ............................................................. 8-9
8.2.6 Trace Exception................................................................................. 8-10
8.2.7 Format Error Exception ..................................................................... 8-11
8.2.8 Breakpoint Instruction Exception....................................................... 8-12
8.2.9 Interrupt Exception ............................................................................ 8-12
8.2.10 Reset Exception................................................................................. 8-17
8.3 Exception Priorities ............................................................................... 8-19
8.4 Return From Exceptions........................................................................ 8-20
8.4.1 Four-Word Stack Frame (Format $0) ................................................ 8-21
8.4.2 Four-Word Throwaway Stack Frame (Format $1)............................. 8-21
8.4.3 Six-Word Stack Frame (Format $2)................................................... 8-22
8.4.4 Floating-Point Post-Instruction Stack Frame (Format $3) ................. 8-23
8.4.5 Eight-Word Stack Frame (Format $4)................................................ 8-23
8.4.6 Access Error Stack Frame (Format $7) ............................................. 8-24
8.4.6.1 Effective Address ........................................................................... 8-24
8.4.6.2 Special Status Word (SSW)........................................................... 8-24
8.4.6.3 Write-Back Status .......................................................................... 8-26
8.4.6.4 Fault Address................................................................................. 8-26
MOTOROLA M68040 USER’S MANUAL xi
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8.4.6.5 Write-Back Address and Write-Back Data..................................... 8-26
8.4.6.6 Push Data...................................................................................... 8-27
8.4.6.7 Access Error Stack Frame Return From Exception....................... 8-27
Section 9
Floating-Point Unit (MC68040 Only)
9.1 Floating-Point Unit Pipeline................................................................... 9-1
9.2 Floating-Point User Programming Model.............................................. 9-2
9.2.1 Floating-Point Data Registers (FP7–FP0)......................................... 9-2
9.2.2 Floating-Point Control Register (FPCR) ............................................ 9-3
9.2.2.1 Exception Enable Byte................................................................... 9-3
9.2.2.2 Mode Control Byte ......................................................................... 9-3
9.2.3 Floating-Point Status Register (FPSR).............................................. 9-4
9.2.3.1 Floating-Point Condition Code Byte............................................... 9-4
9.2.3.2 Quotient Byte ................................................................................. 9-5
9.2.3.3 Exception Status Byte.................................................................... 9-5
9.2.3.4 Accrued Exception (AEXC) Byte. .................................................. 9-5
9.2.4 Floating-Point Instruction Address Register (FPIAR) ........................ 9-6
9.3 Floating-Point Data Formats and Data Types....................................... 9-7
9.4 Computational Accuracy....................................................................... 9-11
9.4.1 Intermediate Result ........................................................................... 9-12
9.4.2 Rounding the Result.......................................................................... 9-13
9.5 Postprocessing Operation..................................................................... 9-15
9.5.1 Underflow, Round, Overflow ............................................................. 9-16
9.5.2 Conditional Testing............................................................................ 9-16
9.6 Floating-Point Exceptions ..................................................................... 9-20
9.6.1 Unimplemented Floating-Point Instructions....................................... 9-20
9.6.2 Unsupported Floating-Point Data Types ........................................... 9-22
9.7 Floating-Point Arithmetic Exceptions .................................................... 9-24
9.7.1 Branch/Set on Unordered (BSUN) .................................................... 9-25
9.7.1.1 Maskable Exception Conditions..................................................... 9-26
9.7.1.2 Nonmaskable Exception Conditions .............................................. 9-27
9.7.2 Signaling Not-a-Number (SNAN)....................................................... 9-27
9.7.2.1 Maskable Exception Conditions..................................................... 9-27
9.7.2.2 Nonmaskable Exception Conditions .............................................. 9-27
9.7.3 Operand Error ................................................................................... 9-28
9.7.3.1 Maskable Exception Conditions..................................................... 9-29
9.7.3.2 Nonmaskable Exception Conditions .............................................. 9-30
9.7.4 Overflow ............................................................................................ 9-31
9.7.4.1 Maskable Exception Conditions..................................................... 9-31
9.7.4.2 Nonmaskable Exception Conditions .............................................. 9-31
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TABLE OF CONTENTS (Continued)
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9.7.5 Underflow .......................................................................................... 9-33
9.7.5.1 Maskable Exception Conditions..................................................... 9-34
9.7.5.2 Nonmaskable Exception Conditions .............................................. 9-34
9.7.6 Divide by Zero.................................................................................... 9-36
9.7.7 Inexact Result.................................................................................... 9-36
9.8 Floating-Point State Frames.................................................................. 9-39
Section 10
Instruction Timings
10.1 Overview ............................................................................................... 10-3
10.2 Instruction Timing Examples ................................................................. 10-5
10.3 CINV and CPUSH Instruction Timing.................................................... 10-8
10.4 MOVE Instruction Timing ...................................................................... 10-9
10.5 Miscellaneous Integer Unit Instruction Timings..................................... 10-11
10.6 Integer Unit Instruction Timings ............................................................ 10-13
10.7 Floating-Point Unit Instruction Timings ................................................. 10-29
10.7.1 Miscellaneous Integer Unit Support Timings..................................... 10-29
10.7.2 Integer Unit Support Timings............................................................. 10-30
10.7.3 Timings in the Floating-Point Unit...................................................... 10-35
Section 11
MC68040 Electrical and Thermal Characteristics
11.1 Maximum Ratings ................................................................................. 11-1
11.2 Thermal Characteristics ........................................................................ 11-1
11.3 DC Electrical Specifications .................................................................. 11-2
11.4 Power Dissipation ................................................................................. 11-2
11.5 Clock AC Timing Specifications ............................................................ 11-3
11.6 Output AC Timing Specifications .......................................................... 11-4
11.7 Input AC Timing Specifications ............................................................. 11-5
11.8 MC68040 Thermal Device Characteristics............................................ 11-12
11.8.1 MC68040 Die and Package............................................................... 11-12
11.8.2 MC68040 Power Considerations....................................................... 11-12
11.9 MC68040 Thermal Management Techniques....................................... 11-14
11.9.1 Still Air................................................................................................ 11-17
11.9.2 Forced Air .......................................................................................... 11-18
11.9.3 With Heat Sink................................................................................... 11-19
11.9.4 With Heat Sink and Forced Air .......................................................... 11-22
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TABLE OF CONTENTS (Continued)
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Section 12
Ordering Information and Mechanical Data
12.1 Ordering Information............................................................................. 12-1
12.2 Pin Assignments ................................................................................... 12-1
12.2.1 MC68040 Pin Grid Array ................................................................... 12-2
12.2.2 MC68LC040 Pin Grid Array............................................................... 12-3
12.2.3 MC68EC040 Pin Grid Array .............................................................. 12-4
12.2.4 MC68040V and MC68EC040V Pin Grid Array.................................. 12-5
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12.2.5 MC68LC040 Quad Flat Pack............................................................. 12-6
12.2.6 MC68EC040 Quad Flat Pack ............................................................ 12-6
12.2.7 MC68040V and MC68EC040V Quad Flat Pack................................ 12-7
12.3 Mechanical Data ................................................................................... 12-9
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Appendix A
MC68LC040
A.1 MC68LC040 Differences....................................................................... A-5
A.2 Interrupt Priority Level (IPL2–IPL0) ....................................................... A-5
A.3 JTAG Scan (JS0) .................................................................................. A-5
A.4 Data Latch And Multiplexed Bus Modes............................................... A-5
A.5 Floating-Point Unit (FPU) ...................................................................... A-5
A.5.1 Unimplemented Floating-Point Instructions and Exceptions ............. A-6
A.5.2 MC68LC040 Stack Frames ............................................................... A-7
A.6 MC68LC040 Electrical Characteristics ................................................. A-7
A.6.1 Maximum Ratings.............................................................................. A-8
A.6.2 Thermal Characteristics .................................................................... A-8
A.6.3 DC Electrical Specifications .............................................................. A-8
A.6.4 Power Dissipation.............................................................................. A-9
A.6.5 Clock AC Timing Specifications ........................................................ A-9
A.6.6 Output AC Timing Specifications....................................................... A-11
A.6.7 Input AC Timing Specifications.......................................................... A-12
Appendix B
MC68EC040
B.1 MC68EC040 Differences ...................................................................... B-4
B.2 JTAG Scan (JS1–JS0).......................................................................... B-5
B.3 Access Control Units............................................................................. B-5
B.3.1 Access Control Registers .................................................................. B-5
B.3.2 Address Comparison......................................................................... B-7
B.3.3 Effect of RSTI on the ACU................................................................. B-8
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B.4 Special Modes Of Operation ................................................................. B-8
B.5 Exception Processing............................................................................ B-10
B.5.1 Unimplemented Floating-Point Instructions and Exceptions ............. B-10
B.5.2 MC68EC040 Stack Frames............................................................... B-11
B.6 Software Considerations ....................................................................... B-12
B.7 MC68EC040 Electrical Characteristics ................................................. B-12
B.7.1 Maximum Ratings .............................................................................. B-12
B.7.2 Thermal Characteristics..................................................................... B-12
B.7.3 DC Electrical Specifications............................................................... B-13
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B.7.4 Power Dissipation.............................................................................. B-13
B.7.5 Clock AC Timing Specifications......................................................... B-14
B.7.6 Output AC Timing Specifications....................................................... B-15
B.7.7 Input AC Timing Specifications.......................................................... B-16
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Appendix C
MC68040V and MC68EC040V
C.1 Additional Signals.................................................................................. C-1
C.1.1 Low Frequency Operation (LFO)....................................................... C-2
C.1.2 Loss of Clock (LOC) .......................................................................... C-2
C.1.3 System Clock Disable (SCD)............................................................. C-2
C.2 Low-Power Stop Mode.......................................................................... C-3
C.2.1 Bus Arbitration and Snooping............................................................ C-5
C.2.2 Low Frequency Operation ................................................................. C-5
C.2.3 Changing BCLK Frequency............................................................... C-5
C.2.4 LPSTOP Instruction Summary .......................................................... C-6
C.3 Clocking During Normal Operation ....................................................... C-7
C.4 Reset Operation .................................................................................... C-7
C.5 Power Cycling ....................................................................................... C-9
C.6 MC68040V and MC68EC040V JTAG (Preliminary).............................. C-10
C.6.1 Instruction Shift Register ................................................................... C-11
C.6.1.1 EXTEST ......................................................................................... C-12
C.6.1.2 HIGHZ............................................................................................ C-12
C.6.1.3 SAMPLE/PRELOAD ...................................................................... C-12
C.6.1.4 CLAMP........................................................................................... C-12
C.6.1.5 BYPASS......................................................................................... C-13
C.6.2 Boundary Scan Register.................................................................... C-13
C.6.3 Restrictions........................................................................................ C-16
C.6.4 Disabling The IEEE Standard 1149.1A Operation............................. C-16
C.6.5 MC68040V and MC68EC040V JTAG Electrical Characteristics....... C-17
MOTOROLA M68040 USER’S MANUAL xv
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
C.7 MC68040V and MC68EC040V Electrical Characteristics..................... C-19
C.7.1 Maximum Ratings.............................................................................. C-19
C.7.2 Thermal Characteristics .................................................................... C-19
C.7.3 DC Electrical Specifications .............................................................. C-20
C.7.4 Power Dissipation.............................................................................. C-20
C.7.5 Clock AC Timing Specifications ........................................................ C-21
C.7.6 Output AC Timing Specifications....................................................... C-22
C.7.7 Input AC Timing Specifications.......................................................... C-23
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Appendix D
M68000 Family Summary
Appendix E
Floating-Point Emulation (M68040FPSP)
Index
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LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 Block Diagram .............................................................................................. 1-4
1-2 Programming Model ..................................................................................... 1-7
2-1 Integer Unit Pipeline..................................................................................... 2-2
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2-2 Write-Back Cycle Block Diagram ................................................................. 2-3
2-3 Integer Unit User Programming Model......................................................... 2-4
2-4 Integer Unit Supervisor Programming Model............................................... 2-6
2-5 Status Register............................................................................................. 2-7
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3-1 Memory Management Unit........................................................................... 3-2
3-2 Memory Management Programming Model................................................. 3-3
3-3 URP and SRP Register Formats.................................................................. 3-4
3-4 Translation Control Register Format ............................................................ 3-4
3-5 Transparent Translation Register Format .................................................... 3-5
3-6 MMU Status Register Format....................................................................... 3-6
3-7 Translation Table Structure.......................................................................... 3-8
3-8 Logical Address Format ............................................................................... 3-9
3-9 Detailed Flowchart of Table Search Operation ............................................ 3-10
3-10 Detailed Flowchart of Descriptor Fetch Operation ....................................... 3-11
3-11 Table Descriptor Formats............................................................................. 3-13
3-12 Page Descriptor Formats ............................................................................. 3-13
3-13 Example Translation Table .......................................................................... 3-17
3-14 Translation Table Using Indirect Descriptors ............................................... 3-18
3-15 Translation Table Using Shared Tables....................................................... 3-19
3-16 Translation Table with Nonresident Tables.................................................. 3-20
3-17 Translation Table Structure for Two Tasks .................................................. 3-24
3-18 Logical Address Map with Shared Supervisor and User Address Spaces... 3-24
3-19 Translation Table Using S-Bit and W-Bit To Set Protection......................... 3-25
3-20 ATC Organization......................................................................................... 3-26
3-21 ATC Entry and Tag Fields............................................................................ 3-27
3-22 Address Translation Flowchart..................................................................... 3-32
3-23 MMU Status Interpretation ........................................................................... 3-35
4-1 Overview of Internal Caches ........................................................................ 4-2
4-2 Cache Line Formats..................................................................................... 4-3
4-3 Caching Operation ....................................................................................... 4-4
4-4 Cache Control Register................................................................................ 4-5
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
4-5 Instruction-Cache Line State Diagram......................................................... 4-14
4-6 Data-Cache Line State Diagram.................................................................. 4-16
5-1 Functional Signal Groups............................................................................. 5-4
6-1 M68040 Test Logic Block Diagram .............................................................. 6-2
6-2 Bypass Register........................................................................................... 6-6
6-3 Output Latch Cell (O.Latch) ......................................................................... 6-7
6-4 Input Pin Cell (I.Pin) ..................................................................................... 6-7
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6-5 Output Control Cells (IO.Ctl) ........................................................................ 6-8
6-6 General Arrangement of Bidirectional Pins.................................................. 6-8
6-7 Circuit Disabling IEEE Standard 1149.1A.................................................... 6-14
6-8 Clock Input Timing Diagram......................................................................... 6-22
6-9 TRST Timing Diagram.................................................................................. 6-22
6-10 Boundary Scan Timing Diagram.................................................................. 6-23
6-11 Test Access Port Timing Diagram ............................................................... 6-23
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7-1 Signal Relationships to Clocks..................................................................... 7-2
7-2 Internal Operand Representation................................................................. 7-3
7-3 Data Multiplexing ......................................................................................... 7-4
7-4 Byte Enable Signal Generation and PAL Equation...................................... 7-5
7-5 Example of a Misaligned Long-Word Transfer............................................. 7-7
7-6 Example of a Misaligned Word Transfer...................................................... 7-7
7-7 Misaligned Long-Word Read Transfer Timing ............................................. 7-8
7-8 Byte, Word, and Long-Word Read Transfer Flowchart................................ 7-10
7-9 Byte, Word, and Long-Word Read Transfer Timing..................................... 7-11
7-10 Line Read Transfer Flowchart...................................................................... 7-14
7-11 Line Read Transfer Timing .......................................................................... 7-15
7-12 Burst-Inhibited Line Read Transfer Flowchart ............................................. 7-18
7-13 Burst-Inhibited Line Read Transfer Timing .................................................. 7-19
7-14 Byte, Word, and Long-Word Write Transfer Flowchart ................................ 7-20
7-15 Long-Word Write Transfer Timing................................................................ 7-21
7-16 Line Write Transfer Flowchart...................................................................... 7-23
7-17 Line Write Transfer Timing........................................................................... 7-24
7-18 Locked Transfer for TAS Instruction Timing ................................................ 7-27
7-19 Interrupt Pending Procedure........................................................................ 7-30
7-20 Assertion of IPEND ...................................................................................... 7-30
7-21 Interrupt Acknowledge Bus Cycle Flowchart ............................................... 7-32
7-22 Interrupt Acknowledge Bus Cycle Timing .................................................... 7-33
7-23 Autovector Interrupt Acknowledge Bus Cycle Timing .................................. 7-34
7-24 Breakpoint Interrupt Acknowledge Bus Cycle Flowchart ............................. 7-35
7-25 Breakpoint Interrupt Acknowledge Bus Cycle Timing .................................. 7-36
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
7-26 Word Write Access Terminated with TEA Timing ........................................ 7-39
7-27 Line Read Access Terminated with TEA Timing .......................................... 7-40
7-28 Retry Read Transfer Timing ......................................................................... 7-41
7-29 Retry Operation on Line Write...................................................................... 7-42
7-30 M68040 Internal Interpretation State Diagram and
External Bus Arbiter Circuit ........................................................................ 7-47
7-31 Lock Violation Example................................................................................ 7-49
7-32 Processor Bus Request Timing.................................................................... 7-50
7-33 Arbitration During Relinquish and Retry Timing ........................................... 7-51
7-34 Implicit Bus Ownership Arbitration Timing.................................................... 7-52
7-35 Dual M68040 Fairness Arbitration State Diagram........................................ 7-53
7-36 Dual M68040 Prioritized Arbitration State Diagram ..................................... 7-55
7-37 M68040 Synchronous DMA Arbitration........................................................ 7-56
7-38 Sample Synchronizer Circuit........................................................................ 7-57
7-39 M68040 Asynchronous DMA Arbitration ...................................................... 7-58
7-40 Snoop-Inhibited Bus Cycle........................................................................... 7-61
7-41 Snoop Access with Memory Response........................................................ 7-62
7-42 Snooped Line Read, Memory Inhibited........................................................ 7-64
7-43 Snooped Long-Word Write, Memory Inhibited ............................................. 7-65
7-44 Initial Power-On Reset Timing...................................................................... 7-66
7-45 Normal Reset Timing ................................................................................... 7-67
7-46 Multiplexed Address and Data Bus (Line Write)........................................... 7-69
7-47 DLE Mode Block Diagram............................................................................ 7-70
7-48 DLE versus Normal Data Read Timing........................................................ 7-71
8-1 General Exception Processing Flowchart .................................................... 8-3
8-2 General Form of Exception Stack Frame..................................................... 8-4
8-3 Interrupt Recognition Examples ................................................................... 8-14
8-4 Interrupt Exception Processing Flowchart.................................................... 8-16
8-5 Reset Exception Processing Flowchart........................................................ 8-18
8-6 Flowchart of RTE Instruction for Throwaway Four-Word Frame.................. 8-22
8-7 Special Status Word Format ........................................................................ 8-24
8-8 Write-Back Status Format ............................................................................ 8-26
9-1 Floating-Point User Programming Model..................................................... 9-2
9-2 Floating-Point Control Register.................................................................... 9-4
9-3 FPSR Condition Code Byte.......................................................................... 9-4
9-4 FPSR Quotient Byte..................................................................................... 9-5
9-5 FPSR Exception Status Byte ....................................................................... 9-5
9-6 FPSR Accrued Exception Byte .................................................................... 9-6
9-7 Intermediate Result Format.......................................................................... 9-12
9-8 Rounding Algorithm Flowchart ..................................................................... 9-14
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
9-9 Format of Denormalized Operand in State Frame....................................... 9-24
9-10 MC68040 Floating-Point State Frames........................................................ 9-40
9-11 Mapping of Command Bits for CMDREG3B Field ....................................... 9-42
10-1 Simple Instruction Timing Example.............................................................. 10-5
10-2 Instruction Overlap with Multiple Clocks ...................................................... 10-6
10-3 Interlocked Stages ....................................................................................... 10-7
11-1 Clock Input Timing Diagram......................................................................... 11-3
11-2 Drive Levels and Test Points for AC Specifications..................................... 11-6
11-3 Read/Write Timing ....................................................................................... 11-7
11-4 Bus Arbitration Timing.................................................................................. 11-8
11-5 Snoop Hit Timing ......................................................................................... 11-9
11-6 Snoop Miss Timing ...................................................................................... 11-10
11-7 Other Signal Timing ..................................................................................... 11-11
11-8 MC68040 Termination Network ................................................................... 11-15
11-9 Typical Configuration for RC Termination Network...................................... 11-15
11-10 Heat Sink with Adhesive .............................................................................. 11-20
11-11 Heat Sink with Attachment........................................................................... 11-21
12-1 PGA Package Dimensions........................................................................... 12-9
12-2 QFP Package Dimensions........................................................................... 12-10
A-1 MC68LC040 Block Diagram ........................................................................ A-2
A-2 MC68LC040 Programming Model ............................................................... A-3
A-3 MC68LC040 Functional Signal Groups........................................................ A-4
A-4 Clock Input Timing Diagram......................................................................... A-10
A-5 Read/Write Timing ....................................................................................... A-13
A-6 Bus Arbitration Timing.................................................................................. A-14
A-7 Snoop Hit Timing ......................................................................................... A-15
A-8 Snoop Miss Timing ...................................................................................... A-16
A-9 Other Signal Timing ..................................................................................... A-17
B-1 MC68EC040 Block Diagram........................................................................ B-2
B-2 MC68EC040 Programming Model............................................................... B-3
B-3 MC68EC040 Functional Signal Groups ....................................................... B-4
B-4 MC68EC040 Access Control Register Format ............................................ B-6
B-5 MC68EC040 Initial Power-On Reset Timing................................................ B-8
B-6 MC68EC040 Normal Reset Timing.............................................................. B-9
B-7 Clock Input Timing Diagram......................................................................... B-14
B-8 Read/Write Timing ....................................................................................... B-17
B-9 Bus Arbitration Timing.................................................................................. B-18
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
B-10 Snoop Hit Timing.......................................................................................... B-19
B-11 Snoop Miss Timing....................................................................................... B-20
B-12 Other Signal Timing ..................................................................................... B-21
C-1 MC68040V and MC68EC040V Functional Signal Groups........................... C-3
C-2 MC68040V and MC68EC040V Initial Power-On Reset Timing ................... C-8
C-3 MC68040V and MC68EC040V Normal Reset Timing.................................. C-9
C-4 MC68040V and MC68EC040V Test Logic Block Diagram .......................... C-11
C-5 Bypass Register ........................................................................................... C-13
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C-6 Output Latch Cell (O.Latch) ......................................................................... C-14
C-7 Input Pin Cell (I.Pin) ..................................................................................... C-14
C-8 Output Control Cells (IO.Ctl) ........................................................................ C-15
C-9 General Arrangement of Bidirectional Pins.................................................. C-15
C-10 Circuit Disabling IEEE Standard 1149.1A ................................................... C-17
C-11 Drive Levels and Test Points for AC Specifications ..................................... C-18
C-12 Clock Input Timing Diagram ......................................................................... C-21
C-13 Read/Write Timing........................................................................................ C-24
C-14 Bus Arbitration Timing.................................................................................. C-25
C-15 Snoop Hit Timing.......................................................................................... C-26
C-16 Snoop Miss Timing....................................................................................... C-27
C-17 Other Signal Timing ..................................................................................... C-28
C-18 Going into LPSTOP with Arbitration............................................................. C-29
C-19 LPSTOP no Arbitration, CPU is Master ....................................................... C-30
C-20 Exiting LPSTOP with Interrupt...................................................................... C-31
C-21 Exiting of LPSTOP with RESET................................................................... C-31
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LIST OF TABLES
Table Page
Number Title Number
1-1 M68040 Data Formats ................................................................................. 1-9
1-2 Effective Addressing Modes ........................................................................ 1-10
1-3 Notational Conventions................................................................................ 1-11
1-4 Instruction Set Summary.............................................................................. 1-14
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3-1 Updating U-Bit and M-Bit for Page Descriptors............................................ 3-22
3-2 SFC and DFC Values................................................................................... 3-22
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4-1 Snoop Control Encoding.............................................................................. 4-9
4-2 TLNx Encoding ............................................................................................ 4-11
4-3 Instruction-Cache Line State Transitions ..................................................... 4-15
4-4 Data-Cache Line State Transitions .............................................................. 4-17
5-1 Signal Index ................................................................................................. 5-2
5-2 Transfer-Type Encoding .............................................................................. 5-5
5-3 Normal and MOVE16 Access Transfer Modifier Encoding .......................... 5-6
5-4 Alternate Access Transfer Modifier Encoding.............................................. 5-6
5-5 Output Driver Control Groups ...................................................................... 5-11
5-6 Processor Status Encoding.......................................................................... 5-13
5-7 Signal Summary........................................................................................... 5-16
6-1 IEEE Standard 1149.1A Instructions ........................................................... 6-3
6-2 Boundary Scan Bit Definitions ..................................................................... 6-10
7-1 Data Bus Requirements for Read and Write Cycles.................................... 7-4
7-2 Summary of Access Types versus Bus Signal Encodings........................... 7-6
7-3 Memory Alignment Influence on Noncachable and
Write-Through Bus Cycles ......................................................................... 7-9
7-4 Interrupt Acknowledge Termination Summary............................................. 7-31
7-5 TA and TEA Assertion Results..................................................................... 7-37
7-6 M68040 Bus Arbitration States .................................................................... 7-48
8-1 Exception Vector Assignments .................................................................... 8-5
8-2 Tracing Control ............................................................................................ 8-11
8-3 Interrupt Levels and Mask Values................................................................ 8-12
8-4 Exception Priority Groups ............................................................................ 8-19
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LIST OF TABLES (Continued)
Table Page
Number Title Number
8-5 Write-Back Data Alignment.......................................................................... 8-27
8-6 Access Error Stack Frame Combinations .................................................... 8-31
9-1 Floating-Point Control Register Encodings .................................................. 9-3
9-2 MC68040 FPU Data Formats and Data Types ............................................ 9-7
9-3 Single-Precision Real Format Summary ...................................................... 9-8
9-4 Double-Precision Real Format Summary..................................................... 9-9
9-5 Extended-Precision Real Format Summary................................................. 9-10
9-6 Packed Decimal Real Format Summary ...................................................... 9-11
9-7 Floating-Point Condition Code Encodings.................................................... 9-17
9-8 Floating-Point Conditional Tests .................................................................. 9-19
9-9 Floating-Point Exception Vectors................................................................. 9-20
9-10 Unimplemented Instructions......................................................................... 9-21
9-11 Possible Operand Errors Exceptions ........................................................... 9-29
9-12 Overflow Rounding Mode Values................................................................. 9-32
9-13 Underflow Rounding Mode Values............................................................... 9-34
9-14 Possible Divide by Zero Exceptions............................................................. 9-36
9-15 Divide by Zero Rounding Mode Values........................................................ 9-37
9-16 State Frame Field Information...................................................................... 9-44
10-1 Instruction Timing Index ............................................................................... 10-1
10-2 Number of Memory Accesses ...................................................................... 10-3
10-3 CINV Timing ................................................................................................. 10-8
10-4 CPUSH Best and Worst Case Timing.......................................................... 10-8
11-1 Maximum Power Dissipation for Output Buffer Mode Configuration............ 11-13
11-2 Thermal Parameters with No Heat Sink or Airflow....................................... 11-17
11-3 Thermal Parameters with Forced Airflow and
No Heat Sink for the MC68040 .................................................................. 11-18
11-4 Thermal Parameters with Forced Airflow and
No Heat Sink for the MC68LC040 and MC68EC040 ................................. 11-19
11-5 Thermal Parameters with Heat Sink and No Airflow .................................... 11-21
11-6 Thermal Parameters with Heat Sink and Airflow.......................................... 11-22
C-1 Additional MC68040V and MC68EC040V Signals....................................... C-2
C-2 Bus Encodings During LPSTOP Broadcast Cycle ....................................... C-4
C-3 IEEE Standard 1149.1A Instructions............................................................ C-12
E-1 MC68040 Floating-Point Instructions........................................................... E-2
E-2 MC68040FPSP Floating-Point Instructions.................................................. E-3
E-3 Support for Data Types and Data Formats .................................................. E-4
E-4 Exception Conditions ................................................................................... E-4
MOTOROLA M68040 USER’S MANUAL xxiii
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SECTION 1
INTRODUCTION
The MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V (collectively
called M68040) are Motorola’s third generation of M68000-compatible, high-performance,
32-bit microprocessors. All five devices are virtual memory microprocessors employing
multiple concurrent execution units and a highly integrated architecture that provides very
high performance in a monolithic HCMOS device. They integrate an MC68030-compatible
integer unit (IU) and two independent caches. The MC68040, MC68040V, and
MC68LC040 contain dual, independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction
and data caches. The MC68040 contains an MC68881/MC68882-compatible floatingpoint unit (FPU). The use of multiple independent execution pipelines, multiple internal
buses, and a full internal Harvard architecture, including separate physical caches for both
instruction and data accesses, achieves a high degree of instruction execution parallelism
on all three processors. The on-chip bus snoop logic, which directly supports cache
coherency in multimaster applications, enhances cache functionality.
The M68040 family is user object-code compatible with previous M68000 family members
and is specifically optimized to reduce the execution time of compiler-generated code. All
five processors implement Motorola’s latest HCMOS technology, providing an ideal
balance between speed, power, and physical device size.
1.1 DIFFERENCES
Because the functionality of individual M68040 family members are similar, this manual is
organized so that the reader will take the following differences into account while reading
the rest of this manual. Unless otherwise noted, all references to M68040, with the
exception of the differences outlined below, will apply to the MC68040, MC68040V,
MC68LC040, MC68EC040, and MC68EC040V. The following paragraphs describe the
differences of MC68040V, MC68LC040, MC68EC040, and the MC68EC040V from the
MC68040.
1.1.1 MC68040V and MC68LC040
The MC68040V and MC68LC040 are derivatives of the MC68040. They implement the
same IU and MMU as the MC68040, but have no FPU. The MC68LC040 is pin compatible
with the MC68040. The MC68040V is not pin compatible with the MC68040 and contains
some additional features. The following differences exist between the MC68040V,
MC68LC040, and MC68040:
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• The DLE pin name has been changed to JS0 on both the MC68040V and
MC68LC040. In addition, the MC68040V contains three new pins, system clock
disable (SCD ), low frequency operation (LFO), and loss of clock (LOC).
• The MC68040V and MC68LC040 do not implement the data latch enable (DLE),
multiplexed, or output buffer impedance selection modes of operation. They
implement only the small output buffer mode of operation. All timing and drive
capabilities on both devices are equivalent to those of the MC68040 in small output
buffer impedance mode. The MC68040V has an additional mode of operation, the
low-power stop mode of operation.
• The MC68040V and MC68LC040 do not contain an FPU, causing unimplemented
floating-point exceptions to occur using a new stack frame format.
• The MC68040V is a 3.3 volt static microprocessor that operates down to 0 MHz.
For specific details on the MC68LC040, refer to Appendix A MC68LC040 . For specific
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details on the MC68040V, refer to both Appendix A MC68LC040 and Appendix C
MC68040V and MC68EC040V. Disregard all information concerning the FPU when
reading the following subsections.
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1.1.2 MC68EC040 and MC68EC040V
The MC68EC040 and MC68EC040V are derivatives of the MC68040. They implement the
same IU as the MC68040, but have no FPU or MMU, which embedded control
applications generally do not require. The MC68EC040 is pin compatible with the
MC68040. The following differences exist between the MC68EC040, MC68EC040V, and
the MC68040:
• The DLE and MDIS pin names have been changed to JS0 and JS1, respectively.
• PTEST and PFLUSH instructions cause an undetermined number of bus cycles; the
user should not execute these instructions.
• The access control unit (ACU) replaces the MMU. The MC68EC040 and
MC68EC040V ACU has two data and two instruction registers that are called data
and instruction transparent translation registers in the MC68040.
• The MC68EC040 and MC68EC040V do not implement the DLE, multiplexed, or
output buffer impedance selection modes of operation. They only implement the small
output buffer mode of operation. All MC68EC040 and MC68EC040V timing and drive
capabilities are equivalent to the MC68040 in small output buffer mode.
• The MC68EC040 and MC68EC040V do not contain an FPU, causing unimplemented
floating-point exceptions to occur using a new stack frame format.
• The MC68040V is a 3.3 volt static microprocessor that operates down to 0 MHz.
Refer to Appendix B MC68EC040 for specific details on the MC68EC040. Refer to
Appendix B MC68EC040 and Appendix C MC68040V and MC68EC040V for specific
details on the MC68EC040V. Disregard information concerning the FPU and MMU
when reading the following subsections.
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1.2 FEATURES
The main features of the M68040 are as follows:
• 6-Stage Pipeline, MC68030-Compatible IU
• MC68881/MC68882-Compatible FPU
• Independent Instruction and Data MMUs
• Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical
Data Cache
• Low-Latency Bus Accesses for Reduced Cache Miss Penalty
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput
• 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User Object-Code Compatible with All Earlier M68000 Microprocessors
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• 4-Gbyte Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX
®
System V Port
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The on-chip FPU and large physical instruction and data caches yield improved system
performance and increased functionality. The independent instruction and data MMUs and
increased internal parallelism also improve performance.
1.3 EXTENSIONS TO THE M68000 FAMILY
The M68040 is compatible with the ANSI/IEEE
Arithmetic
subset of the MC68881/MC68882 instruction sets and includes additional instruction
formats for single- and double-precision rounding results. Software emulates floating-point
instructions not directly supported in hardware. Refer to Appendix E M68040 Floating -
Point Emulation (MC68040FPSP) for details on software emulation. The MOVE16 user
instruction is new to the instruction set, supporting efficient 16-byte memory-to-memory
data transfers.
. The MC68040’s FPU has been optimized to execute the most commonly used
Standard 754 for Binary Floating-Point
1.4 FUNCTIONAL BLOCKS
Figure 1-1 illustrates a simplified block diagram of the MC68040. Refer to Appendix A
MC68LC040 for information on the MC68LC040’s and MC68040V's functional blocks; and
Appendix B MC68EC040 for information on the MC68EC040’s and MC68EC040V's
functional blocks.
The M68040 IU pipeline has been expanded from the MC68030 to include effective
address calculation (<ea> calculate) and operand fetch (<ea> fetch) stages with
commonly used effective addressing modes. Conditional branches are optimized for the
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more common case of the branch taken, and both execution paths of the branch are
fetched and decoded to minimize refilling of the instruction pipeline.
INSTRUCTION DATA BUS
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CONVERT
EXECUTE
WRITE-
BACK
FLOATING-
POINT
UNIT
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EA
FETCH
EXECUTE
WRITE-
BACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
MMU/CACHE/SNOOP
CONTROLLER
DATA
ATC
OPERAND DATA BUS
DATA
INSTRUCTION
CACHE
DATA
CACHE
INSTRUCTION
ADDRESS
DATA
ADDRESS
B
U
S
C
O
N
T
R
O
L
L
E
R
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
Figure 1-1. Block Diagram
To improve memory management, the M68040 includes separate, independent paged
MMUs for instruction and data accesses. Each MMU stores recently used address
mappings in separate 64-entry address translation caches (ATCs). Each MMU also has
two transparent translation registers that define a one-to-one mapping for address space
segments ranging in size from 16 Mbytes to 4 Gbytes each.
Two memory units independently interface with the IU and FPU. Each unit consists of an
MMU, an ATC, a main cache, and a snoop controller. The MMUs perform memory
management on a demand-page basis. By translating logical-to-physical addresses using
translation tables stored in memory, the MMUs support virtual memory systems. Each
MMU stores recently used address mappings in an ATC, reducing the average translation
time.
Separate on-chip instruction and data caches operate independently and are accessed in
parallel with address translation. The caches improve the overall performance of the
system by reducing the number of bus transfers required by the processor to fetch
information from memory and by increasing the bus bandwidth available for alternate bus
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masters in the system. Both caches are organized as four-way set associative with 64
sets of four lines. Each line contains four long words for a storage capability of 4 Kbytes
for each cache (8 Kbytes total). Each cache and corresponding MMU is allocated
separate internal address and data buses, allowing simultaneous access to both. The
data cache provides write-through or copyback write modes that can be configured on a
page-by-page basis. The caches are physically mapped, reducing software support for
multitasking operating systems, and support external bus snooping to maintain cache
coherency in multimaster systems.
The bus snoop logic provides cache coherency in multimaster applications. The bus
controller executes bus transfers on the external bus and prioritizes external memory
requests from each cache. The M68040 bus controller supports a high-speed,
nonmultiplexed, synchronous, external bus interface supporting burst accesses for both
reads and writes to provide high data transfer rates to and from the caches. Additional bus
signals support bus snooping and external cache tag maintenance.
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The MC68040 contains an on-chip FPU, which is user object-code compatible with the
MC68881/MC68882 floating-point coprocessors. The FPU has pipelined instruction
execution. Floating-point instructions in the FPU execute concurrently with integer
instructions in the IU.
1.5 PROCESSING STATES
The processor is always in one of three states: normal processing, exception processing,
or halted. It is in the normal processing state when executing instructions, fetching
instructions and operands, and storing instruction results.
Exception processing is the transition from program processing to system, interrupt, and
exception handling. Exception processing includes fetching the exception vector, stacking
operations, and refilling the instruction pipe caused after an exception. The processor
enters exception processing when an exceptional internal condition arises such as tracing
an instruction, an instruction results in a trap, or executing specific instructions. External
conditions, such as interrupts and access errors, also cause exceptions. Exception
processing ends when the first instruction of the exception handler begins to execute.
The processor halts when it receives an access error or generates an address error while
in the exception processing state. For example, if during exception processing of one
access error another access error occurs, the MC68040 is unable to complete the
transition to normal processing and cannot save the internal state of the machine. The
processor assumes that the system is not operational and halts. Only an external reset
can restart a halted processor. Note that when the processor executes a STOP
instruction, it is in a special type of normal processing state, one without bus cycles. The
processor stops, but it does not halt.
1.6 PROGRAMMING MODEL
The MC68040 programming model is separated into two privilege modes : supervisor and
user. The S-bit in the status register (SR) indicates the privilege mode that the processor
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uses. The IU identifies a logical address by accessing either the supervisor or user
address space, maintaining the differentiation between supervisor and user modes. The
MMUs use the indicated privilege mode to control and translate memory accesses,
protecting supervisor code, data, and resources from user program accesses. Refer to
Appendix B MC68EC040 for details concerning the MC68EC040 address translation.
Programs access registers based on the indicated mode. User programs can only access
registers specific to the user mode; whereas, system software executing in the supervisor
mode can access all registers, using the control registers to perform supervisory functions.
User programs are thus restricted from accessing privileged information, and the
operating system performs management and service tasks for the user programs by
coordinating their activities. This difference allows the supervisor mode to protect system
resources from uncontrolled accesses.
Most instructions execute in either mode, but some instructions that have important
system effects are privileged and can only execute in the supervisor mode. For instance,
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user programs cannot execute the STOP or RESET instructions. To prevent a user
program from entering the supervisor mode, except in a controlled manner, instructions
that can alter the S-bit in the SR are privileged. The TRAP instructions provide controlled
access to operating system services for user programs.
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If the S-bit in the SR is set, the processor executes instructions in the supervisor mode.
Because the processor performs all exception processing in the supervisor mode, all bus
cycles generated during exception processing are supervisor references, and all stack
accesses use the active supervisor stack pointer. If the S-bit of the SR is clear, the
processor executes instructions in the user mode. The bus cycles for an instruction
executed in the user mode are user references. The values on the transfer modifier pins
indicate either supervisor or user accesses.
The processor utilizes the user mode and the user programming model when it is in
normal processing. During exception processing, the processor changes from user to
supervisor mode. Exception processing saves the current value of the SR on the active
supervisor stack and then sets the S-bit, forcing the processor into the supervisor mode.
To return to the user mode, a system routine must execute one of the following
instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE, which execute in
the supervisor mode, modifying the S-bit of the SR. After these instructions execute, the
instruction pipeline is flushed and is refilled from the appropriate address space.
The MC68040 integrates the functions of the IU, FPU, and MMU. The registers depicted
in the programming model (see Figure 1-2) provide operand storage and control for these
three units. The registers are partitioned into two levels of privilege modes: user and
supervisor. The user programming model is the same as the user programming model of
the MC68030, which consists of 16, general-purpose, 32-bit registers and two control
registers. The MC68040 user programming model also incorporates the
MC68881/MC68882 programming model consisting of eight, 80-bit, floating-point data
registers, a floating-point control register, a floating-point status register, and a floating point instruction address register.
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Only system programmers can use the supervisor programming model to implement
operating system functions, I/O control, and memory management subsystems. This
supervisor/user distinction in the M68000 family architecture allows for the writing of
application software that executes in the user mode and migrates to the MC68040 from
any M68000 family platform without modification. The supervisor programming model
contains the control features that system designers need to modify system software when
porting to a new design. For example, only the supervisor software can read or write to
the transparent translation registers of the MC68040. The existence of the transparent
translation registers does not affect the programming resources of user application
programs.
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31 0
DATA
REGISTERS
ADDRESS
REGISTERS
31 0
(CCR)
79 0
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7/USP
PC
CCR
A7'/ISP
A7"/MSP
SR
VBR
SFC
DFC
CACR
URP
SRP
TC
DTT0
DTT1
ITT0
ITT1
MMUSR
FP INSTRUCTION ADDRESS REGISTER
USER STACK POINTER
PROGRAM COUNTER
CONDITION CODE REGISTER
USER PROGRAMMING MODEL
INTERRUPT STACK POINTER
MASTER STACK POINTER
STATUS REGISTER (CCR IS ALSO SHOWN IN THE USER PROGRAMMING MODEL)
VECTOR BASE REGISTER
SOURCE FUNCTION CODE
DESTINATION FUNCTION CODE
CACHE CONTROL REGISTER
USER ROOT POINTER REGISTER
SUPERVISOR ROOT POINTER REGISTER
TRANSLATION CONTROL REGISTER
DATA TRANSPARENT TRANSLATION REGISTER 0
DATA TRANSPARENT TRANSLATION REGISTER 1
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1
MMU STATUS REGISTER
FLOATING-POINT
DATA
REGISTERS
FP CONTROL REGISTER
FP STATUS REGISTER
31 0
15
0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
SUPERVISOR PROGRAMMING MODEL
Figure 1-2. Programming Model
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The user programming model includes eight data registers, seven address registers, and
a stack pointer register. The address registers and stack pointer can be used as base
address registers or software stack pointers, and any of the 16 registers can be used as
index registers. Two control registers are available in the user mode—the program
counter (PC), which usually contains the address of the instruction that the MC68040 is
executing, and the lower byte of the SR, which is accessible as the condition code register
(CCR). The CCR contains the condition codes that reflect the results of a previous
operation and can be used for conditional instruction execution in a program.
The supervisor programming model includes the upper byte of the SR, which contains
operation control information. The vector base register (VBR) contains the base address
of the exception vector table, which is used in exception processing. The source function
code (SFC) and destination function code (DFC) registers contain 3-bit function codes.
These function codes can be considered extensions to the 32-bit logical address. The
processor automatically generates function codes to select address spaces for data and
program accesses in the user and supervisor modes. Some instructions use the alternate
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function code registers to specify the function codes for various operations.
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The cache control register (CACR) controls enabling of the on-chip instruction and data
caches of the MC68040. The supervisor root pointer (SRP) and user root pointer (URP)
registers point to the root of the address translation table tree to be used for supervisor
and user mode accesses.
The translation control register (TCR) enables logical-to-physical address translation and
selects either 4- or 8-Kbyte page sizes. There are four transparent translation registers,
two for instruction accesses and two for data accesses. These registers allow portions of
the logical address space to be transparently mapped and accessed without the use of
resident descriptors in an ATC. The MMU status register (MMUSR) contains status
information derived from the execution of a PTEST instruction. The PTEST instruction
searches the translation tables for the logical address, specified by this instruction’s
effective address field and the DFC, and returns status information corresponding to the
translation.
The user programming model can also access the entire floating-point programming
model. The eight 80-bit floating-point data registers are analogous to the integer data
registers. A 32-bit floating-point control register (FPCR) contains an exception enable byte
that enables and disables traps for each class of floating-point exceptions and a mode
byte that sets the user-selectable rounding and precision modes. A floating-point status
register (FPSR) contains a condition code byte, quotient byte, exception status byte, and
accrued exception byte. A floating-point exception handler can use the address in the 32bit floating-point instruction address register (FPIAR) to locate the floating-point instruction
that has caused an exception. Instructions that do not modify the FPIAR can be used to
read the FPIAR in the exception handler without changing the previous value.
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1.7 DATA FORMAT SUMMARY
The M68040 supports the basic data formats of the M68000 family. Some data formats
apply only to the IU, some only to the FPU, and some to both. In addition, the instruction
set supports operations on other data formats such as memory addresses.
The operand data formats supported by the IU are the standard twos-complement data
formats defined in the M68000 family architecture plus a new data format (16-byte block)
for the MOVE16 instruction. Registers, memory, or instructions themselves can contain IU
operands. The operand size for each instruction is either explicitly encoded in the
instruction or implicitly defined by the instruction operation.
Whenever an integer is used in a floating-point operation, the FPU automatically converts
it to an extended-precision floating-point number before using the integer. The FPU
implements single- and double-precision floating-point data formats as defined by the
IEEE 754 standard. The FPU does not directly support packed decimal real format.
However, by trapping as an unimplemented data format instead of as an illegal instruction,
software emulation supports the packed decimal format. Additionally, each data format
has a special encoding that represents one of five data types: normalized numbers,
denormalized numbers, zeros, infinities, and not-a-numbers (NANs). Table 1-1 lists the
data formats for both the IU and the FPU. Refer to M68000PM/AD,
Programmer’s Reference Manual,
for details on data format organization in registers and
memory.
Table 1-1. M68040 Data Formats
Operand Data Format Size Supported In Notes
Bit 1 Bit IU —
Bit Field 1–32 Bits IU Field of Consecutive Bits
Binary-Coded Decimal (BCD) 8 Bits IU Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte
Byte Integer 8 Bits IU, FPU —
Word Integer 16 Bits IU, FPU —
Long-Word Integer 32 Bits IU, FPU —
Quad-Word Integer 64 Bits IU Any Two Data Registers
16-Byte 128 Bits IU Memory Only, Aligned to 16-Byte Boundary
Single-Precision Real 32 Bits FPU 1-Bit Sign, 8-Bit Exponent, 23-Bit Fraction
Double-Precision Real 64 Bits FPU 1-Bit Sign, 11-Bit Exponent, 52-Bit Fraction
Extended-Precision Real 80 Bits FPU 1-Bit Sign, 15-Bit Exponent, 64-Bit Mantissa
M68000 Family
1.8 ADDRESSING CAPABILITIES SUMMARY
The M68040 supports the basic addressing modes of the M68000 family. The register
indirect addressing modes support postincrement, predecrement, offset, and indexing,
which are particularly useful for handling data structures common to sophisticated
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